diff --git a/db/ip/nios_system/nios_system.bsf b/db/ip/nios_system/nios_system.bsf index b495623..dac37b1 100644 --- a/db/ip/nios_system/nios_system.bsf +++ b/db/ip/nios_system/nios_system.bsf @@ -1,248 +1,248 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 384 792) + (text "nios_system" (rect 155 -1 206 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 776 20 788)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 160 72)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 160 152)(line_width 1)) + ) + (port + (pt 0 232) + (input) + (text "switches_export[17..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) + (text "switches_export[17..0]" (rect 4 221 136 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 160 232)(line_width 3)) + ) + (port + (pt 0 272) + (input) + (text "push_switches_export[2..0]" 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532)(pt 162 556)(line_width 1)) + (line (pt 161 572)(pt 161 596)(line_width 1)) + (line (pt 162 572)(pt 162 596)(line_width 1)) + (line (pt 161 612)(pt 161 684)(line_width 1)) + (line (pt 162 612)(pt 162 684)(line_width 1)) + (line (pt 161 700)(pt 161 724)(line_width 1)) + (line (pt 162 700)(pt 162 724)(line_width 1)) + (line (pt 161 740)(pt 161 764)(line_width 1)) + (line (pt 162 740)(pt 162 764)(line_width 1)) + (line (pt 160 32)(pt 224 32)(line_width 1)) + (line (pt 224 32)(pt 224 776)(line_width 1)) + (line (pt 160 776)(pt 224 776)(line_width 1)) + (line (pt 160 32)(pt 160 776)(line_width 1)) + (line (pt 0 0)(pt 384 0)(line_width 1)) + (line (pt 384 0)(pt 384 792)(line_width 1)) + (line (pt 0 792)(pt 384 792)(line_width 1)) + (line (pt 0 0)(pt 0 792)(line_width 1)) + ) +) diff --git a/db/ip/nios_system/nios_system.v b/db/ip/nios_system/nios_system.v index 0b211ba..7cbf870 100644 --- a/db/ip/nios_system/nios_system.v +++ b/db/ip/nios_system/nios_system.v @@ -1,9 +1,9 @@ -// nios_system.v - -// Generated using ACDS version 13.0sp1 232 at 2016.12.02.01:32:16 - +// nios_system.v + +// Generated using ACDS version 13.0sp1 232 at 2016.12.22.10:07:22 + `timescale 1 ps / 1 ps -module nios_system ( +module nios_system ( input wire clk_clk, // clk.clk output wire [7:0] leds_export, // leds.export input wire reset_reset_n, // reset.reset_n @@ -24,1056 +24,1056 @@ output wire lcd_16207_0_E, // .E output wire lcd_on_export, // lcd_on.export output wire lcd_blon_export // lcd_blon.export - ); - - wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest - wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address - wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read - wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata - wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest - wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata - wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address - wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write - wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read - wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata - wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess - wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata - wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata - wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address - wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect - wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken - wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata - wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable - wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata - wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address - wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect - wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n - wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata - wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata - wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address - wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect - wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata - wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address - wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata - wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address - wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata - wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address - wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect - wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata - wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address - wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect - wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata - wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address - wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect - wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata - wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address - wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect - wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata - wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address - wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect - wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata - wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address - wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect - wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata - wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address - wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect - wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata - wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address - wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect - wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata - wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata - wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address - wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect - wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata - wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address - wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect - wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest - wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid - wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest - wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata - wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata - wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata - wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess - wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata - wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess - wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata - wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess - wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata - wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess - wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata - wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess - wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata - wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess - wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata - wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess - wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata - wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess - wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata - wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess - wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata - wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess - wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata - wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess - wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata - wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess - wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata - wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess - wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata - wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess - wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata - wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess - wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata - wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess - wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata - wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess - wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket - wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket - wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket - wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket - wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket - wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket - wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket - wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket - wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket - wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket - wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket - wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket - wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket - wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket - wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket - wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket - wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket - wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket - wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket - wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket - wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] - wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req - wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 - wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket - wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid - wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data - wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel - wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready - wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket - wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid - wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data - wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel - wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready - wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket - wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid - wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data - wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel - wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready - wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket - wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid - wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data - wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel - wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready - wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket - wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid - wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data - wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel - wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready - wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket - wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid - wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data - wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel - wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready - wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket - wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid - wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data - wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel - wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready - wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket - wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid - wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data - wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel - wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready - wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket - wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid - wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket - wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data - wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel - wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready - wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket - wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid - wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket - wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data - wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel - wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready - wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket - wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid - wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket - wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data - wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel - wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready - wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket - wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid - wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket - wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data - wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel - wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready - wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket - wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid - wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket - wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data - wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel - wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready - wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket - wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid - wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket - wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data - wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel - wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready - wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket - wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid - wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket - wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data - wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel - wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready - wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket - wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid - wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket - wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data - wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel - wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready - wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket - wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid - wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket - wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data - wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel - wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready - wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket - wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid - wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket - wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data - wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel - wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready - wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket - wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid - wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket - wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data - wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel - wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready - wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket - wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid - wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket - wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data - wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel - wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready - wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket - wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid - wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket - wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data - wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel - wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready - wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket - wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid - wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket - wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data - wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel - wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready - wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket - wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid - wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket - wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data - wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel - wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready - wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket - wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid - wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket - wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data - wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel - wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready - wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket - wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid - wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket - wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data - wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel - wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready - wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready - wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket - wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid - wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket - wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data - wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel - wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready - wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready - wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready - wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket - wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid - wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket - wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data - wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel - wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready - wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready - wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket - wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid - wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket - wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data - wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel - wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready - wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready - wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket - wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid - wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket - wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data - wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel - wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready - wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready - wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket - wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid - wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket - wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data - wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel - wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready - wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready - wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket - wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid - wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket - wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data - wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel - wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready - wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready - wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket - wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid - wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket - wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data - wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel - wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready - wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready - wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket - wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid - wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket - wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data - wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel - wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready - wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready - wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket - wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid - wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket - wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data - wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel - wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready - wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready - wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket - wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid - wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket - wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data - wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel - wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready - wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready - wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket - wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid - wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket - wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data - wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel - wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready - wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready - wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket - wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid - wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket - wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data - wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel - wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready - wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready - wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket - wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid - wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket - wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data - wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel - wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready - wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready - wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket - wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid - wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket - wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data - wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel - wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready - wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready - wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket - wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid - wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket - wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data - wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel - wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready - wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready - wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket - wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid - wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket - wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data - wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel - wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready - wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready - wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket - wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid - wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket - wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data - wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel - wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready - wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready - wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket - wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid - wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket - wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data - wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel - wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready - wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready - wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket - wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid - wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket - wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data - wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel - wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready - wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq - wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq - + ); + + wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest + wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address + wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read + wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata + wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest + wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata + wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address + wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write + wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read + wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata + wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess + wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata + wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata + wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address + wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect + wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken + wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata + wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable + wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata + wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address + wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect + wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n + wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata + wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata + wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address + wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect + wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata + wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address + wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata + wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address + wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata + wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address + wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect + wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata + wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address + wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect + wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata + wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address + wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect + wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata + wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address + wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect + wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata + wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address + wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect + wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata + wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address + wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect + wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata + wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address + wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect + wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata + wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address + wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect + wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata + wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata + wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address + wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect + wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata + wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address + wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect + wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest + wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid + wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest + wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata + wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata + wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata + wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess + wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata + wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess + wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata + wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess + wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata + wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess + wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata + wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess + wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata + wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess + wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata + wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess + wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata + wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess + wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata + wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess + wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata + wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess + wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata + wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess + wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata + wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess + wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata + wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess + wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata + wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess + wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata + wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess + wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata + wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess + wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata + wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess + wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket + wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket + wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket + wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket + wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket + wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket + wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket + wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket + wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket + wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket + wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket + wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket + wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket + wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket + wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket + wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket + wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket + wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket + wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket + wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket + wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] + wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req + wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 + wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket + wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid + wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data + wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel + wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready + wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket + wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid + wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data + wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel + wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready + wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket + wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid + wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data + wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel + wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready + wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket + wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid + wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data + wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel + wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready + wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket + wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid + wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data + wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel + wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready + wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket + wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid + wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data + wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel + wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready + wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket + wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid + wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data + wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel + wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready + wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket + wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid + wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data + wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel + wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready + wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket + wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid + wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket + wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data + wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel + wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready + wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket + wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid + wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket + wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data + wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel + wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready + wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket + wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid + wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket + wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data + wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel + wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready + wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket + wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid + wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket + wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data + wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel + wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready + wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket + wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid + wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket + wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data + wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel + wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready + wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket + wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid + wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket + wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data + wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel + wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready + wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket + wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid + wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket + wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data + wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel + wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready + wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket + wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid + wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket + wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data + wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel + wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready + wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket + wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid + wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket + wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data + wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel + wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready + wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket + wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid + wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket + wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data + wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel + wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready + wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket + wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid + wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket + wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data + wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel + wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready + wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket + wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid + wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket + wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data + wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel + wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready + wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket + wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid + wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket + wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data + wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel + wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready + wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket + wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid + wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket + wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data + wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel + wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready + wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket + wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid + wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket + wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data + wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel + wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready + wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket + wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid + wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket + wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data + wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel + wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready + wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket + wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid + wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket + wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data + wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel + wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready + wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready + wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket + wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid + wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket + wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data + wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel + wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready + wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready + wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready + wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket + wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid + wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket + wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data + wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel + wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready + wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready + wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket + wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid + wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket + wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data + wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel + wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready + wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready + wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket + wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid + wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket + wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data + wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel + wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready + wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready + wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket + wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid + wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket + wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data + wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel + wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready + wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready + wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket + wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid + wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket + wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data + wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel + wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready + wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready + wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket + wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid + wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket + wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data + wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel + wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready + wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready + wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket + wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid + wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket + wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data + wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel + wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready + wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready + wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket + wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid + wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket + wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data + wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel + wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready + wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready + wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket + wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid + wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket + wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data + wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel + wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready + wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready + wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket + wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid + wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket + wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data + wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel + wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready + wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready + wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket + wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid + wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket + wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data + wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel + wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready + wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready + wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket + wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid + wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket + wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data + wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel + wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready + wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready + wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket + wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid + wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket + wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data + wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel + wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready + wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready + wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket + wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid + wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket + wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data + wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel + wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready + wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready + wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket + wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid + wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket + wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data + wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel + wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready + wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready + wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket + wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid + wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket + wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data + wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel + wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready + wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready + wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket + wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid + wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket + wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data + wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel + wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready + wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready + wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket + wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid + wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket + wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data + wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel + wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready + wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq + wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq + nios_system_nios2_processor nios2_processor ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n @@ -1100,8 +1100,8 @@ .jtag_debug_module_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write .jtag_debug_module_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata .no_ci_readra () // custom_instruction_master.readra - ); - + ); + nios_system_onchip_memory onchip_memory ( .clk (clk_clk), // clk1.clk .address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address @@ -1113,8 +1113,8 @@ .byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .reset (rst_controller_reset_out_reset), // reset1.reset .reset_req (rst_controller_reset_out_reset_req) // .reset_req - ); - + ); + nios_system_jtag_uart jtag_uart ( .clk (clk_clk), // clk.clk .rst_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1126,8 +1126,8 @@ .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_irq (irq_mapper_receiver0_irq) // irq.irq - ); - + ); + nios_system_LEDs leds ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1137,8 +1137,8 @@ .chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (leds_export) // external_connection.export - ); - + ); + nios_system_LEDRs ledrs ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1148,24 +1148,24 @@ .chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (ledrs_export) // external_connection.export - ); - + ); + nios_system_switches switches ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address .readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata .in_port (switches_export) // external_connection.export - ); - + ); + nios_system_push_switches push_switches ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (push_switches_s1_translator_avalon_anti_slave_0_address), // s1.address .readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata .in_port (push_switches_export) // external_connection.export - ); - + ); + nios_system_hex0 hex0 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1175,8 +1175,8 @@ .chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex0_export) // external_connection.export - ); - + ); + nios_system_hex0 hex1 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1186,8 +1186,8 @@ .chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex1_export) // external_connection.export - ); - + ); + nios_system_hex0 hex2 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1197,8 +1197,8 @@ .chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex2_export) // external_connection.export - ); - + ); + nios_system_hex0 hex3 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1208,8 +1208,8 @@ .chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex3_export) // external_connection.export - ); - + ); + nios_system_hex0 hex4 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1219,8 +1219,8 @@ .chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex4_export) // external_connection.export - ); - + ); + nios_system_hex0 hex5 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1230,8 +1230,8 @@ .chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex5_export) // external_connection.export - ); - + ); + nios_system_hex0 hex6 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1241,8 +1241,8 @@ .chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex6_export) // external_connection.export - ); - + ); + nios_system_hex0 hex7 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1252,8 +1252,8 @@ .chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex7_export) // external_connection.export - ); - + ); + nios_system_lcd_16207_0 lcd_16207_0 ( .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .clk (clk_clk), // clk.clk @@ -1267,8 +1267,8 @@ .LCD_RW (lcd_16207_0_RW), // .export .LCD_data (lcd_16207_0_data), // .export .LCD_E (lcd_16207_0_E) // .export - ); - + ); + nios_system_lcd_on lcd_on ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1278,8 +1278,8 @@ .chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (lcd_on_export) // external_connection.export - ); - + ); + nios_system_lcd_on lcd_blon ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1289,32 +1289,32 @@ .chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (lcd_blon_export) // external_connection.export - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (0), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (1), - .AV_REGISTERINCOMINGSIGNALS (0) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (0), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (1), + .AV_REGISTERINCOMINGSIGNALS (0) ) nios2_processor_instruction_master_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1351,32 +1351,32 @@ .uav_writeresponsevalid (1'b0), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (1), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (0), - .AV_REGISTERINCOMINGSIGNALS (1) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (1) ) nios2_processor_data_master_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1413,34 +1413,34 @@ .uav_writeresponsevalid (1'b0), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (9), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (9), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) nios2_processor_jtag_debug_module_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1479,34 +1479,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (16), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (1), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (0), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (16), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) onchip_memory_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1545,34 +1545,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) leds_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1611,34 +1611,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (1), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (1), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) jtag_uart_avalon_jtag_slave_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1677,34 +1677,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) ledrs_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1743,34 +1743,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) switches_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1809,34 +1809,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) push_switches_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1875,34 +1875,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex0_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1941,34 +1941,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex1_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2007,34 +2007,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex2_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2073,34 +2073,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex3_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2139,34 +2139,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex4_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2205,34 +2205,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex5_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2271,34 +2271,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex6_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2337,34 +2337,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex7_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2403,34 +2403,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (8), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (13), - .AV_WRITE_WAIT_CYCLES (13), - .AV_SETUP_WAIT_CYCLES (13), - .AV_DATA_HOLD_CYCLES (13) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (8), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (13), + .AV_WRITE_WAIT_CYCLES (13), + .AV_SETUP_WAIT_CYCLES (13), + .AV_DATA_HOLD_CYCLES (13) ) lcd_16207_0_control_slave_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2469,34 +2469,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) lcd_on_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2535,34 +2535,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) lcd_blon_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2601,58 +2601,58 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (1), - .BURSTWRAP_VALUE (3), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (1), + .BURSTWRAP_VALUE (3), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2681,58 +2681,58 @@ .av_response (), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (0), - .BURSTWRAP_VALUE (7), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (0), + .BURSTWRAP_VALUE (7), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) nios2_processor_data_master_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2761,43 +2761,43 @@ .av_response (), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2842,21 +2842,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2883,43 +2883,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) onchip_memory_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2964,21 +2964,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3005,43 +3005,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) leds_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3086,21 +3086,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3127,43 +3127,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3208,21 +3208,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3249,43 +3249,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) ledrs_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3330,21 +3330,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3371,43 +3371,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) switches_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3452,21 +3452,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3493,43 +3493,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) push_switches_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3574,21 +3574,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3615,43 +3615,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex0_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3696,21 +3696,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3737,43 +3737,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex1_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3818,21 +3818,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3859,43 +3859,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex2_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3940,21 +3940,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3981,43 +3981,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex3_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4062,21 +4062,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4103,43 +4103,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex4_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4184,21 +4184,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4225,43 +4225,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex5_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4306,21 +4306,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4347,43 +4347,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex6_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4428,21 +4428,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4469,43 +4469,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex7_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4550,21 +4550,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4591,43 +4591,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4672,21 +4672,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4713,43 +4713,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) lcd_on_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4794,21 +4794,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4835,43 +4835,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) lcd_blon_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4916,21 +4916,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4957,8 +4957,8 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - + ); + nios_system_addr_router addr_router ( .sink_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid @@ -4973,8 +4973,8 @@ .src_channel (addr_router_src_channel), // .channel .src_startofpacket (addr_router_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_src_endofpacket) // .endofpacket - ); - + ); + nios_system_addr_router_001 addr_router_001 ( .sink_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid @@ -4989,8 +4989,8 @@ .src_channel (addr_router_001_src_channel), // .channel .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router id_router ( .sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5005,8 +5005,8 @@ .src_channel (id_router_src_channel), // .channel .src_startofpacket (id_router_src_startofpacket), // .startofpacket .src_endofpacket (id_router_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router id_router_001 ( .sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5021,8 +5021,8 @@ .src_channel (id_router_001_src_channel), // .channel .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_002 ( .sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5037,8 +5037,8 @@ .src_channel (id_router_002_src_channel), // .channel .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_003 ( .sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5053,8 +5053,8 @@ .src_channel (id_router_003_src_channel), // .channel .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_004 ( .sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5069,8 +5069,8 @@ .src_channel (id_router_004_src_channel), // .channel .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_005 ( .sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5085,8 +5085,8 @@ .src_channel (id_router_005_src_channel), // .channel .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_006 ( .sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5101,8 +5101,8 @@ .src_channel (id_router_006_src_channel), // .channel .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_007 ( .sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5117,8 +5117,8 @@ .src_channel (id_router_007_src_channel), // .channel .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_008 ( .sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5133,8 +5133,8 @@ .src_channel (id_router_008_src_channel), // .channel .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_009 ( .sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5149,8 +5149,8 @@ .src_channel (id_router_009_src_channel), // .channel .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_010 ( .sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5165,8 +5165,8 @@ .src_channel (id_router_010_src_channel), // .channel .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_011 ( .sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5181,8 +5181,8 @@ .src_channel (id_router_011_src_channel), // .channel .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_012 ( .sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5197,8 +5197,8 @@ .src_channel (id_router_012_src_channel), // .channel .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_013 ( .sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5213,8 +5213,8 @@ .src_channel (id_router_013_src_channel), // .channel .src_startofpacket (id_router_013_src_startofpacket), // .startofpacket .src_endofpacket (id_router_013_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_014 ( .sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5229,8 +5229,8 @@ .src_channel (id_router_014_src_channel), // .channel .src_startofpacket (id_router_014_src_startofpacket), // .startofpacket .src_endofpacket (id_router_014_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_015 ( .sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5245,8 +5245,8 @@ .src_channel (id_router_015_src_channel), // .channel .src_startofpacket (id_router_015_src_startofpacket), // .startofpacket .src_endofpacket (id_router_015_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_016 ( .sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5261,8 +5261,8 @@ .src_channel (id_router_016_src_channel), // .channel .src_startofpacket (id_router_016_src_startofpacket), // .startofpacket .src_endofpacket (id_router_016_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_017 ( .sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5277,13 +5277,13 @@ .src_channel (id_router_017_src_channel), // .channel .src_startofpacket (id_router_017_src_startofpacket), // .startofpacket .src_endofpacket (id_router_017_src_endofpacket) // .endofpacket - ); - - altera_reset_controller #( - .NUM_RESET_INPUTS (2), - .OUTPUT_RESET_SYNC_EDGES ("deassert"), - .SYNC_DEPTH (2), - .RESET_REQUEST_PRESENT (1) + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (2), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (1) ) rst_controller ( .reset_in0 (~reset_reset_n), // reset_in0.reset .reset_in1 (nios2_processor_jtag_debug_module_reset_reset), // reset_in1.reset @@ -5304,8 +5304,8 @@ .reset_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_in15 (1'b0) // (terminated) - ); - + ); + nios_system_cmd_xbar_demux cmd_xbar_demux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5327,8 +5327,8 @@ .src1_channel (cmd_xbar_demux_src1_channel), // .channel .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5446,8 +5446,8 @@ .src17_channel (cmd_xbar_demux_001_src17_channel), // .channel .src17_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket .src17_endofpacket (cmd_xbar_demux_001_src17_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_mux cmd_xbar_mux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5469,8 +5469,8 @@ .sink1_data (cmd_xbar_demux_001_src0_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_mux cmd_xbar_mux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5492,8 +5492,8 @@ .sink1_data (cmd_xbar_demux_001_src1_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_demux rsp_xbar_demux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5515,8 +5515,8 @@ .src1_channel (rsp_xbar_demux_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_demux rsp_xbar_demux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5538,8 +5538,8 @@ .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_002 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5555,8 +5555,8 @@ .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_003 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5572,8 +5572,8 @@ .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_004 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5589,8 +5589,8 @@ .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_005 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5606,8 +5606,8 @@ .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_006 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5623,8 +5623,8 @@ .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_007 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5640,8 +5640,8 @@ .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_008 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5657,8 +5657,8 @@ .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_009 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5674,8 +5674,8 @@ .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_010 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5691,8 +5691,8 @@ .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_011 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5708,8 +5708,8 @@ .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_012 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5725,8 +5725,8 @@ .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_013 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5742,8 +5742,8 @@ .src0_channel (rsp_xbar_demux_013_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_013_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_014 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5759,8 +5759,8 @@ .src0_channel (rsp_xbar_demux_014_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_014_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_015 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5776,8 +5776,8 @@ .src0_channel (rsp_xbar_demux_015_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_015_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_016 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5793,8 +5793,8 @@ .src0_channel (rsp_xbar_demux_016_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_017 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5810,8 +5810,8 @@ .src0_channel (rsp_xbar_demux_017_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_mux rsp_xbar_mux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5833,8 +5833,8 @@ .sink1_data (rsp_xbar_demux_001_src0_data), // .data .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5952,13 +5952,13 @@ .sink17_data (rsp_xbar_demux_017_src0_data), // .data .sink17_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket .sink17_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_irq_mapper irq_mapper ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq .sender_irq (nios2_processor_d_irq_irq) // sender.irq - ); - -endmodule + ); + +endmodule diff --git a/db/ip/nios_system/nios_system__report.html b/db/ip/nios_system/nios_system__report.html index fa39d9b..223f088 100644 --- a/db/ip/nios_system/nios_system__report.html +++ b/db/ip/nios_system/nios_system__report.html @@ -67,7 +67,7 @@ - +
2016.12.02.01:32:122016.12.22.10:07:17 Datasheet
@@ -4854,8 +4854,8 @@ - - + +
generation took 0.01 secondsrendering took 0.16 secondsgeneration took 0.00 secondsrendering took 0.15 seconds
diff --git a/db/ip/nios_system/nios_system__report.xml b/db/ip/nios_system/nios_system__report.xml index 52efdff..1cebda8 100644 --- a/db/ip/nios_system/nios_system__report.xml +++ b/db/ip/nios_system/nios_system__report.xml @@ -1,6 +1,6 @@ - + nios_system" reuses altera_irq_mapper "submodules/nios_system_irq_mapper"]]> queue size: 121 starting:altera_nios2_qsys "submodules/nios_system_nios2_processor" Starting RTL generation for module 'nios_system_nios2_processor' - Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] - # 2016.12.02 01:32:17 (*) Starting Nios II generation - # 2016.12.02 01:32:17 (*) Checking for plaintext license. - # 2016.12.02 01:32:17 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus - # 2016.12.02 01:32:17 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2016.12.02 01:32:17 (*) LM_LICENSE_FILE environment variable is empty - # 2016.12.02 01:32:17 (*) Plaintext license not found. - # 2016.12.02 01:32:17 (*) No license required to generate encrypted Nios II/e. - # 2016.12.02 01:32:17 (*) Elaborating CPU configuration settings - # 2016.12.02 01:32:17 (*) Creating all objects for CPU - # 2016.12.02 01:32:18 (*) Generating RTL from CPU objects - # 2016.12.02 01:32:18 (*) Creating plain-text RTL - # 2016.12.02 01:32:20 (*) Done Nios II generation + Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] + # 2016.12.22 10:07:23 (*) Starting Nios II generation + # 2016.12.22 10:07:23 (*) Checking for plaintext license. + # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus + # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty + # 2016.12.22 10:07:23 (*) Plaintext license not found. + # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. + # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings + # 2016.12.22 10:07:23 (*) Creating all objects for CPU + # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects + # 2016.12.22 10:07:24 (*) Creating plain-text RTL + # 2016.12.22 10:07:26 (*) Done Nios II generation Done RTL generation for module 'nios_system_nios2_processor' nios_system" instantiated altera_nios2_qsys "nios2_processor"]]> queue size: 120 starting:altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory" Starting RTL generation for module 'nios_system_onchip_memory' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_onchip_memory' nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory"]]> queue size: 119 starting:altera_avalon_jtag_uart "submodules/nios_system_jtag_uart" Starting RTL generation for module 'nios_system_jtag_uart' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_jtag_uart' nios_system" instantiated altera_avalon_jtag_uart "jtag_uart"]]> queue size: 118 starting:altera_avalon_pio "submodules/nios_system_LEDs" Starting RTL generation for module 'nios_system_LEDs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_LEDs' nios_system" instantiated altera_avalon_pio "LEDs"]]> queue size: 117 starting:altera_avalon_pio "submodules/nios_system_LEDRs" Starting RTL generation for module 'nios_system_LEDRs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_LEDRs' nios_system" instantiated altera_avalon_pio "LEDRs"]]> queue size: 116 starting:altera_avalon_pio "submodules/nios_system_switches" Starting RTL generation for module 'nios_system_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_switches' nios_system" instantiated altera_avalon_pio "switches"]]> queue size: 115 starting:altera_avalon_pio "submodules/nios_system_push_switches" Starting RTL generation for module 'nios_system_push_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_push_switches' nios_system" instantiated altera_avalon_pio "push_switches"]]> queue size: 114 starting:altera_avalon_pio "submodules/nios_system_hex0" Starting RTL generation for module 'nios_system_hex0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_hex0' nios_system" instantiated altera_avalon_pio "hex0"]]> queue size: 106 starting:altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0" Starting RTL generation for module 'nios_system_lcd_16207_0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_lcd_16207_0' nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0"]]> queue size: 105 starting:altera_avalon_pio "submodules/nios_system_lcd_on" Starting RTL generation for module 'nios_system_lcd_on' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_lcd_on' nios_system" instantiated altera_avalon_pio "lcd_on"]]> queue size: 103 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" @@ -1443,19 +1443,19 @@ queue size: 121 starting:altera_nios2_qsys "submodules/nios_system_nios2_processor" Starting RTL generation for module 'nios_system_nios2_processor' - Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] - # 2016.12.02 01:32:17 (*) Starting Nios II generation - # 2016.12.02 01:32:17 (*) Checking for plaintext license. - # 2016.12.02 01:32:17 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus - # 2016.12.02 01:32:17 (*) Defaulting to contents of LM_LICENSE_FILE environment variable - # 2016.12.02 01:32:17 (*) LM_LICENSE_FILE environment variable is empty - # 2016.12.02 01:32:17 (*) Plaintext license not found. - # 2016.12.02 01:32:17 (*) No license required to generate encrypted Nios II/e. - # 2016.12.02 01:32:17 (*) Elaborating CPU configuration settings - # 2016.12.02 01:32:17 (*) Creating all objects for CPU - # 2016.12.02 01:32:18 (*) Generating RTL from CPU objects - # 2016.12.02 01:32:18 (*) Creating plain-text RTL - # 2016.12.02 01:32:20 (*) Done Nios II generation + Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] + # 2016.12.22 10:07:23 (*) Starting Nios II generation + # 2016.12.22 10:07:23 (*) Checking for plaintext license. + # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus + # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty + # 2016.12.22 10:07:23 (*) Plaintext license not found. + # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. + # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings + # 2016.12.22 10:07:23 (*) Creating all objects for CPU + # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects + # 2016.12.22 10:07:24 (*) Creating plain-text RTL + # 2016.12.22 10:07:26 (*) Done Nios II generation Done RTL generation for module 'nios_system_nios2_processor' nios_system" instantiated altera_nios2_qsys "nios2_processor"]]> @@ -1514,7 +1514,7 @@ queue size: 120 starting:altera_avalon_onchip_memory2 "submodules/nios_system_onchip_memory" Starting RTL generation for module 'nios_system_onchip_memory' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_onchip_memory' nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory"]]> @@ -1558,7 +1558,7 @@ queue size: 119 starting:altera_avalon_jtag_uart "submodules/nios_system_jtag_uart" Starting RTL generation for module 'nios_system_jtag_uart' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_jtag_uart' nios_system" instantiated altera_avalon_jtag_uart "jtag_uart"]]> @@ -1607,7 +1607,7 @@ queue size: 118 starting:altera_avalon_pio "submodules/nios_system_LEDs" Starting RTL generation for module 'nios_system_LEDs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_LEDs' nios_system" instantiated altera_avalon_pio "LEDs"]]> @@ -1656,7 +1656,7 @@ queue size: 117 starting:altera_avalon_pio "submodules/nios_system_LEDRs" Starting RTL generation for module 'nios_system_LEDRs' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_LEDRs' nios_system" instantiated altera_avalon_pio "LEDRs"]]> @@ -1705,7 +1705,7 @@ queue size: 116 starting:altera_avalon_pio "submodules/nios_system_switches" Starting RTL generation for module 'nios_system_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_switches' nios_system" instantiated altera_avalon_pio "switches"]]> @@ -1754,7 +1754,7 @@ queue size: 115 starting:altera_avalon_pio "submodules/nios_system_push_switches" Starting RTL generation for module 'nios_system_push_switches' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_push_switches' nios_system" instantiated altera_avalon_pio "push_switches"]]> @@ -1805,7 +1805,7 @@ queue size: 114 starting:altera_avalon_pio "submodules/nios_system_hex0" Starting RTL generation for module 'nios_system_hex0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_hex0' nios_system" instantiated altera_avalon_pio "hex0"]]> @@ -1834,7 +1834,7 @@ queue size: 106 starting:altera_avalon_lcd_16207 "submodules/nios_system_lcd_16207_0" Starting RTL generation for module 'nios_system_lcd_16207_0' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_lcd_16207_0' nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0"]]> @@ -1883,7 +1883,7 @@ queue size: 105 starting:altera_avalon_pio "submodules/nios_system_lcd_on" Starting RTL generation for module 'nios_system_lcd_on' - Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] + Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] Done RTL generation for module 'nios_system_lcd_on' nios_system" instantiated altera_avalon_pio "lcd_on"]]> diff --git a/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v b/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v index 8f846b8..94e2787 100644 --- a/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v +++ b/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v @@ -1,877 +1,877 @@ -// ----------------------------------------------------------- -// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your -// use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any -// output files any of the foregoing (including device programming or -// simulation files), and any associated documentation or information are -// expressly subject to the terms and conditions of the Altera Program -// License Subscription Agreement or other applicable license agreement, -// including, without limitation, that your use is for the sole purpose -// of programming logic devices manufactured by Altera and sold by Altera -// or its authorized distributors. Please refer to the applicable -// agreement for further details. -// -// Description: Single clock Avalon-ST FIFO. -// ----------------------------------------------------------- - -`timescale 1 ns / 1 ns - - -//altera message_off 10036 -module altera_avalon_sc_fifo -#( - // -------------------------------------------------- - // Parameters - // -------------------------------------------------- - parameter SYMBOLS_PER_BEAT = 1, - parameter BITS_PER_SYMBOL = 8, - parameter FIFO_DEPTH = 16, - parameter CHANNEL_WIDTH = 0, - parameter ERROR_WIDTH = 0, - parameter USE_PACKETS = 0, - parameter USE_FILL_LEVEL = 0, - parameter USE_STORE_FORWARD = 0, - parameter USE_ALMOST_FULL_IF = 0, - parameter USE_ALMOST_EMPTY_IF = 0, - - // -------------------------------------------------- - // Empty latency is defined as the number of cycles - // required for a write to deassert the empty flag. - // For example, a latency of 1 means that the empty - // flag is deasserted on the cycle after a write. - // - // Another way to think of it is the latency for a - // write to propagate to the output. - // - // An empty latency of 0 implies lookahead, which is - // only implemented for the register-based FIFO. - // -------------------------------------------------- - parameter EMPTY_LATENCY = 3, - parameter USE_MEMORY_BLOCKS = 1, - - // -------------------------------------------------- - // Internal Parameters - // -------------------------------------------------- - parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, - parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) -) -( - // -------------------------------------------------- - // Ports - // -------------------------------------------------- - input clk, - input reset, - - input [DATA_WIDTH-1: 0] in_data, - input in_valid, - input in_startofpacket, - input in_endofpacket, - input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, - input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, - input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, - output in_ready, - - output [DATA_WIDTH-1 : 0] out_data, - output reg out_valid, - output out_startofpacket, - output out_endofpacket, - output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, - output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, - output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, - input out_ready, - - input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, - input csr_write, - input csr_read, - input [31 : 0] csr_writedata, - output reg [31 : 0] csr_readdata, - - output wire almost_full_data, - output wire almost_empty_data -); - - // -------------------------------------------------- - // Local Parameters - // -------------------------------------------------- - localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); - localparam DEPTH = FIFO_DEPTH; - localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; - localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? - 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: - DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; - - // -------------------------------------------------- - // Internal Signals - // -------------------------------------------------- - genvar i; - - reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; - reg [ADDR_WIDTH-1 : 0] wr_ptr; - reg [ADDR_WIDTH-1 : 0] rd_ptr; - reg [DEPTH-1 : 0] mem_used; - - wire [ADDR_WIDTH-1 : 0] next_wr_ptr; - wire [ADDR_WIDTH-1 : 0] next_rd_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; - - wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; - - wire read; - wire write; - - reg empty; - reg next_empty; - reg full; - reg next_full; - - wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; - wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; - wire [PAYLOAD_WIDTH-1 : 0] in_payload; - reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; - reg [PAYLOAD_WIDTH-1 : 0] out_payload; - - reg internal_out_valid; - wire internal_out_ready; - - reg [ADDR_WIDTH : 0] fifo_fill_level; - reg [ADDR_WIDTH : 0] fill_level; - - reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; - reg [23:0] almost_full_threshold; - reg [23:0] almost_empty_threshold; - reg [23:0] cut_through_threshold; - reg [15:0] pkt_cnt; - reg [15:0] pkt_cnt_r; - reg [15:0] pkt_cnt_plusone; - reg [15:0] pkt_cnt_minusone; - reg drop_on_error_en; - reg error_in_pkt; - reg pkt_has_started; - reg sop_has_left_fifo; - reg fifo_too_small_r; - reg pkt_cnt_eq_zero; - reg pkt_cnt_eq_one; - reg pkt_cnt_changed; - - wire wait_for_threshold; - reg pkt_mode; - wire wait_for_pkt; - wire ok_to_forward; - wire in_pkt_eop_arrive; - wire out_pkt_leave; - wire in_pkt_start; - wire in_pkt_error; - wire drop_on_error; - wire fifo_too_small; - wire out_pkt_sop_leave; - wire [31:0] max_fifo_size; - reg fifo_fill_level_lt_cut_through_threshold; - - // -------------------------------------------------- - // Define Payload - // - // Icky part where we decide which signals form the - // payload to the FIFO with generate blocks. - // -------------------------------------------------- - generate - if (EMPTY_WIDTH > 0) begin - assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; - assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; - end - else begin - assign out_empty = in_error; - assign in_packet_signals = {in_startofpacket, in_endofpacket}; - assign {out_startofpacket, out_endofpacket} = out_packet_signals; - end - endgenerate - - generate - if (USE_PACKETS) begin - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; - assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data, in_error}; - assign {out_packet_signals, out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_channel}; - assign {out_packet_signals, out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data}; - assign {out_packet_signals, out_data} = out_payload; - end - end - end - else begin - assign out_packet_signals = 0; - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_error, in_channel}; - assign {out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_data, in_error}; - assign {out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_channel}; - assign {out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = in_data; - assign out_data = out_payload; - end - end - end - endgenerate - - // -------------------------------------------------- - // Memory-based FIFO storage - // - // To allow a ready latency of 0, the read index is - // obtained from the next read pointer and memory - // outputs are unregistered. - // - // If the empty latency is 1, we infer bypass logic - // around the memory so writes propagate to the - // outputs on the next cycle. - // - // Do not change the way this is coded: Quartus needs - // a perfect match to the template, and any attempt to - // refactor the two always blocks into one will break - // memory inference. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - if (EMPTY_LATENCY == 1) begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] = in_payload; - - internal_out_payload = mem[mem_rd_ptr]; - end - - end else begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] <= in_payload; - - internal_out_payload <= mem[mem_rd_ptr]; - end - - end - - assign mem_rd_ptr = next_rd_ptr; - - end else begin - - // -------------------------------------------------- - // Register-based FIFO storage - // - // Uses a shift register as the storage element. Each - // shift register slot has a bit which indicates if - // the slot is occupied (credit to Sam H for the idea). - // The occupancy bits are contiguous and start from the - // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep - // FIFO. - // - // Each slot is enabled during a read or when it - // is unoccupied. New data is always written to every - // going-to-be-empty slot (we keep track of which ones - // are actually useful with the occupancy bits). On a - // read we shift occupied slots. - // - // The exception is the last slot, which always gets - // new data when it is unoccupied. - // -------------------------------------------------- - for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg - always @(posedge clk or posedge reset) begin - if (reset) begin - mem[i] <= 0; - end - else if (read || !mem_used[i]) begin - if (!mem_used[i+1]) - mem[i] <= in_payload; - else - mem[i] <= mem[i+1]; - end - end - end - - always @(posedge clk, posedge reset) begin - if (reset) begin - mem[DEPTH-1] <= 0; - end - else begin - if (!mem_used[DEPTH-1]) - mem[DEPTH-1] <= in_payload; - - if (DEPTH == 1) begin - if (write) - mem[DEPTH-1] <= in_payload; - end - end - end - - end - endgenerate - - assign read = internal_out_ready && internal_out_valid && ok_to_forward; - assign write = in_ready && in_valid; - - // -------------------------------------------------- - // Pointer Management - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - assign incremented_wr_ptr = wr_ptr + 1'b1; - assign incremented_rd_ptr = rd_ptr + 1'b1; - assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; - assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; - - always @(posedge clk or posedge reset) begin - if (reset) begin - wr_ptr <= 0; - rd_ptr <= 0; - end - else begin - wr_ptr <= next_wr_ptr; - rd_ptr <= next_rd_ptr; - end - end - - end else begin - - // -------------------------------------------------- - // Shift Register Occupancy Bits - // - // Consider a 4-deep FIFO with 2 entries: 0011 - // On a read and write, do not modify the bits. - // On a write, left-shift the bits to get 0111. - // On a read, right-shift the bits to get 0001. - // - // Also, on a write we set bit0 (the head), while - // clearing the tail on a read. - // -------------------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[0] <= 0; - end - else begin - if (write ^ read) begin - if (read) begin - if (DEPTH > 1) - mem_used[0] <= mem_used[1]; - else - mem_used[0] <= 0; - end - if (write) - mem_used[0] <= 1; - end - end - end - - if (DEPTH > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[DEPTH-1] <= 0; - end - else begin - if (write ^ read) begin - mem_used[DEPTH-1] <= 0; - if (write) - mem_used[DEPTH-1] <= mem_used[DEPTH-2]; - end - end - end - end - - for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic - always @(posedge clk, posedge reset) begin - if (reset) begin - mem_used[i] <= 0; - end - else begin - if (write ^ read) begin - if (read) - mem_used[i] <= mem_used[i+1]; - if (write) - mem_used[i] <= mem_used[i-1]; - end - end - end - end - - end - endgenerate - - - // -------------------------------------------------- - // Memory FIFO Status Management - // - // Generates the full and empty signals from the - // pointers. The FIFO is full when the next write - // pointer will be equal to the read pointer after - // a write. Reading from a FIFO clears full. - // - // The FIFO is empty when the next read pointer will - // be equal to the write pointer after a read. Writing - // to a FIFO clears empty. - // - // A simultaneous read and write must not change any of - // the empty or full flags unless there is a drop on error event. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - always @* begin - next_full = full; - next_empty = empty; - - if (read && !write) begin - next_full = 1'b0; - - if (incremented_rd_ptr == wr_ptr) - next_empty = 1'b1; - end - - if (write && !read) begin - if (!drop_on_error) - next_empty = 1'b0; - else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo - next_empty = 1'b1; - - if (incremented_wr_ptr == rd_ptr && !drop_on_error) - next_full = 1'b1; - end - - if (write && read && drop_on_error) begin - if (sop_ptr == next_rd_ptr) - next_empty = 1'b1; - end - end - - always @(posedge clk or posedge reset) begin - if (reset) begin - empty <= 1; - full <= 0; - end - else begin - empty <= next_empty; - full <= next_full; - end - end - - end else begin - // -------------------------------------------------- - // Register FIFO Status Management - // - // Full when the tail occupancy bit is 1. Empty when - // the head occupancy bit is 0. - // -------------------------------------------------- - always @* begin - full = mem_used[DEPTH-1]; - empty = !mem_used[0]; - - // ------------------------------------------ - // For a single slot FIFO, reading clears the - // full status immediately. - // ------------------------------------------ - if (DEPTH == 1) - full = mem_used[0] && !read; - - internal_out_payload = mem[0]; - - // ------------------------------------------ - // Writes clear empty immediately for lookahead modes. - // Note that we use in_valid instead of write to avoid - // combinational loops (in lookahead mode, qualifying - // with in_ready is meaningless). - // - // In a 1-deep FIFO, a possible combinational loop runs - // from write -> out_valid -> out_ready -> write - // ------------------------------------------ - if (EMPTY_LATENCY == 0) begin - empty = !mem_used[0] && !in_valid; - - if (!mem_used[0] && in_valid) - internal_out_payload = in_payload; - end - end - - end - endgenerate - - // -------------------------------------------------- - // Avalon-ST Signals - // - // The in_ready signal is straightforward. - // - // To match memory latency when empty latency > 1, - // out_valid assertions must be delayed by one clock - // cycle. - // - // Note: out_valid deassertions must not be delayed or - // the FIFO will underflow. - // -------------------------------------------------- - assign in_ready = !full; - assign internal_out_ready = out_ready || !out_valid; - - generate if (EMPTY_LATENCY > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) - internal_out_valid <= 0; - else begin - internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; - - if (read) begin - if (incremented_rd_ptr == wr_ptr) - internal_out_valid <= 1'b0; - end - end - end - end else begin - always @* begin - internal_out_valid = !empty & ok_to_forward; - end - end - endgenerate - - // -------------------------------------------------- - // Single Output Pipeline Stage - // - // This output pipeline stage is enabled if the FIFO's - // empty latency is set to 3 (default). It is disabled - // for all other allowed latencies. - // - // Reason: The memory outputs are unregistered, so we have to - // register the output or fmax will drop if combinatorial - // logic is present on the output datapath. - // - // Q: The Avalon-ST spec says that I have to register my outputs - // But isn't the memory counted as a register? - // A: The path from the address lookup to the memory output is - // slow. Registering the memory outputs is a good idea. - // - // The registers get packed into the memory by the fitter - // which means minimal resources are consumed (the result - // is a altsyncram with registered outputs, available on - // all modern Altera devices). - // - // This output stage acts as an extra slot in the FIFO, - // and complicates the fill level. - // -------------------------------------------------- - generate if (EMPTY_LATENCY == 3) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - out_valid <= 0; - out_payload <= 0; - end - else begin - if (internal_out_ready) begin - out_valid <= internal_out_valid & ok_to_forward; - out_payload <= internal_out_payload; - end - end - end - end - else begin - always @* begin - out_valid = internal_out_valid; - out_payload = internal_out_payload; - end - end - endgenerate - - // -------------------------------------------------- - // Fill Level - // - // The fill level is calculated from the next write - // and read pointers to avoid unnecessary latency. - // - // If the output pipeline is enabled, the fill level - // must account for it, or we'll always be off by one. - // This may, or may not be important depending on the - // application. - // - // For now, we'll always calculate the exact fill level - // at the cost of an extra adder when the output stage - // is enabled. - // -------------------------------------------------- - generate if (USE_FILL_LEVEL) begin - wire [31:0] depth32; - assign depth32 = DEPTH; - always @(posedge clk or posedge reset) begin - if (reset) - fifo_fill_level <= 0; - else if (next_full & !drop_on_error) - fifo_fill_level <= depth32[ADDR_WIDTH:0]; - else begin - fifo_fill_level[ADDR_WIDTH] <= 1'b0; - fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; - end - end - - always @* begin - fill_level = fifo_fill_level; - - if (EMPTY_LATENCY == 3) - fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; - end - end - else begin - initial fill_level = 0; - end - endgenerate - - generate if (USE_ALMOST_FULL_IF) begin - assign almost_full_data = (fill_level >= almost_full_threshold); - end - else - assign almost_full_data = 0; - endgenerate - - generate if (USE_ALMOST_EMPTY_IF) begin - assign almost_empty_data = (fill_level <= almost_empty_threshold); - end - else - assign almost_empty_data = 0; - endgenerate - - // -------------------------------------------------- - // Avalon-MM Status & Control Connection Point - // - // Register map: - // - // | Addr | RW | 31 - 0 | - // | 0 | R | Fill level | - // - // The registering of this connection point means - // that there is a cycle of latency between - // reads/writes and the updating of the fill level. - // -------------------------------------------------- - generate if (USE_STORE_FORWARD) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - cut_through_threshold <= 0; - drop_on_error_en <= 0; - csr_readdata <= 0; - pkt_mode <= 1'b1; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b100) begin - cut_through_threshold <= csr_writedata[23:0]; - pkt_mode <= (csr_writedata[23:0] == 0); - end - if(csr_address == 3'b101) - drop_on_error_en <= csr_writedata[0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - if (csr_address == 4) - csr_readdata <= {8'b0, cut_through_threshold}; - if (csr_address == 5) - csr_readdata <= {31'b0, drop_on_error_en}; - end - end - end - end - else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - csr_readdata <= 0; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - end - end - end - end - else begin - always @(posedge clk or posedge reset) begin - if (reset) begin - csr_readdata <= 0; - end - else if (csr_read) begin - csr_readdata <= 0; - - if (csr_address == 0) - csr_readdata <= fill_level; - end - end - end - endgenerate - - // -------------------------------------------------- - // Store and forward logic - // -------------------------------------------------- - // if the fifo gets full before the entire packet or the - // cut-threshold condition is met then start sending out - // data in order to avoid dead-lock situation - - generate if (USE_STORE_FORWARD) begin - assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; - assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); - assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : - ~wait_for_threshold) | fifo_too_small_r; - assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; - assign in_pkt_start = in_valid & in_ready & in_startofpacket; - assign in_pkt_error = in_valid & in_ready & |in_error; - assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; - assign out_pkt_leave = out_valid & out_ready & out_endofpacket; - assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; - - // count packets coming and going into the fifo - always @(posedge clk or posedge reset) begin - if (reset) begin - pkt_cnt <= 0; - pkt_cnt_r <= 0; - pkt_cnt_plusone <= 1; - pkt_cnt_minusone <= 0; - pkt_cnt_changed <= 0; - pkt_has_started <= 0; - sop_has_left_fifo <= 0; - fifo_too_small_r <= 0; - pkt_cnt_eq_zero <= 1'b1; - pkt_cnt_eq_one <= 1'b0; - fifo_fill_level_lt_cut_through_threshold <= 1'b1; - end - else begin - fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; - fifo_too_small_r <= fifo_too_small; - pkt_cnt_plusone <= pkt_cnt + 1'b1; - pkt_cnt_minusone <= pkt_cnt - 1'b1; - pkt_cnt_r <= pkt_cnt; - pkt_cnt_changed <= 1'b0; - - if( in_pkt_eop_arrive ) - sop_has_left_fifo <= 1'b0; - else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) - sop_has_left_fifo <= 1'b1; - - if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; - pkt_cnt_eq_zero <= 0; - if (pkt_cnt == 0) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; - if (pkt_cnt == 1) - pkt_cnt_eq_zero <= 1'b1; - else - pkt_cnt_eq_zero <= 1'b0; - if (pkt_cnt == 2) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - - if (in_pkt_start) - pkt_has_started <= 1'b1; - else if (in_pkt_eop_arrive) - pkt_has_started <= 1'b0; - end - end - - // drop on error logic - always @(posedge clk or posedge reset) begin - if (reset) begin - sop_ptr <= 0; - error_in_pkt <= 0; - end - else begin - // save the location of the SOP - if ( in_pkt_start ) - sop_ptr <= wr_ptr; - - // remember if error in pkt - // log error only if packet has already started - if (in_pkt_eop_arrive) - error_in_pkt <= 1'b0; - else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) - error_in_pkt <= 1'b1; - end - end - assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & - ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); - - end - else begin - assign ok_to_forward = 1'b1; - assign drop_on_error = 1'b0; - end - endgenerate - - - // -------------------------------------------------- - // Calculates the log2ceil of the input value - // -------------------------------------------------- - function integer log2ceil; - input integer val; - integer i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule +// ----------------------------------------------------------- +// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your +// use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any +// output files any of the foregoing (including device programming or +// simulation files), and any associated documentation or information are +// expressly subject to the terms and conditions of the Altera Program +// License Subscription Agreement or other applicable license agreement, +// including, without limitation, that your use is for the sole purpose +// of programming logic devices manufactured by Altera and sold by Altera +// or its authorized distributors. Please refer to the applicable +// agreement for further details. +// +// Description: Single clock Avalon-ST FIFO. +// ----------------------------------------------------------- + +`timescale 1 ns / 1 ns + + +//altera message_off 10036 +module altera_avalon_sc_fifo +#( + // -------------------------------------------------- + // Parameters + // -------------------------------------------------- + parameter SYMBOLS_PER_BEAT = 1, + parameter BITS_PER_SYMBOL = 8, + parameter FIFO_DEPTH = 16, + parameter CHANNEL_WIDTH = 0, + parameter ERROR_WIDTH = 0, + parameter USE_PACKETS = 0, + parameter USE_FILL_LEVEL = 0, + parameter USE_STORE_FORWARD = 0, + parameter USE_ALMOST_FULL_IF = 0, + parameter USE_ALMOST_EMPTY_IF = 0, + + // -------------------------------------------------- + // Empty latency is defined as the number of cycles + // required for a write to deassert the empty flag. + // For example, a latency of 1 means that the empty + // flag is deasserted on the cycle after a write. + // + // Another way to think of it is the latency for a + // write to propagate to the output. + // + // An empty latency of 0 implies lookahead, which is + // only implemented for the register-based FIFO. + // -------------------------------------------------- + parameter EMPTY_LATENCY = 3, + parameter USE_MEMORY_BLOCKS = 1, + + // -------------------------------------------------- + // Internal Parameters + // -------------------------------------------------- + parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) +) +( + // -------------------------------------------------- + // Ports + // -------------------------------------------------- + input clk, + input reset, + + input [DATA_WIDTH-1: 0] in_data, + input in_valid, + input in_startofpacket, + input in_endofpacket, + input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, + input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, + input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, + output in_ready, + + output [DATA_WIDTH-1 : 0] out_data, + output reg out_valid, + output out_startofpacket, + output out_endofpacket, + output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, + output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, + output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, + input out_ready, + + input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, + input csr_write, + input csr_read, + input [31 : 0] csr_writedata, + output reg [31 : 0] csr_readdata, + + output wire almost_full_data, + output wire almost_empty_data +); + + // -------------------------------------------------- + // Local Parameters + // -------------------------------------------------- + localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); + localparam DEPTH = FIFO_DEPTH; + localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; + localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? + 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; + + // -------------------------------------------------- + // Internal Signals + // -------------------------------------------------- + genvar i; + + reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; + reg [ADDR_WIDTH-1 : 0] wr_ptr; + reg [ADDR_WIDTH-1 : 0] rd_ptr; + reg [DEPTH-1 : 0] mem_used; + + wire [ADDR_WIDTH-1 : 0] next_wr_ptr; + wire [ADDR_WIDTH-1 : 0] next_rd_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; + + wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; + + wire read; + wire write; + + reg empty; + reg next_empty; + reg full; + reg next_full; + + wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; + wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; + wire [PAYLOAD_WIDTH-1 : 0] in_payload; + reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; + reg [PAYLOAD_WIDTH-1 : 0] out_payload; + + reg internal_out_valid; + wire internal_out_ready; + + reg [ADDR_WIDTH : 0] fifo_fill_level; + reg [ADDR_WIDTH : 0] fill_level; + + reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; + reg [23:0] almost_full_threshold; + reg [23:0] almost_empty_threshold; + reg [23:0] cut_through_threshold; + reg [15:0] pkt_cnt; + reg [15:0] pkt_cnt_r; + reg [15:0] pkt_cnt_plusone; + reg [15:0] pkt_cnt_minusone; + reg drop_on_error_en; + reg error_in_pkt; + reg pkt_has_started; + reg sop_has_left_fifo; + reg fifo_too_small_r; + reg pkt_cnt_eq_zero; + reg pkt_cnt_eq_one; + reg pkt_cnt_changed; + + wire wait_for_threshold; + reg pkt_mode; + wire wait_for_pkt; + wire ok_to_forward; + wire in_pkt_eop_arrive; + wire out_pkt_leave; + wire in_pkt_start; + wire in_pkt_error; + wire drop_on_error; + wire fifo_too_small; + wire out_pkt_sop_leave; + wire [31:0] max_fifo_size; + reg fifo_fill_level_lt_cut_through_threshold; + + // -------------------------------------------------- + // Define Payload + // + // Icky part where we decide which signals form the + // payload to the FIFO with generate blocks. + // -------------------------------------------------- + generate + if (EMPTY_WIDTH > 0) begin + assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; + assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; + end + else begin + assign out_empty = in_error; + assign in_packet_signals = {in_startofpacket, in_endofpacket}; + assign {out_startofpacket, out_endofpacket} = out_packet_signals; + end + endgenerate + + generate + if (USE_PACKETS) begin + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; + assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data, in_error}; + assign {out_packet_signals, out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_channel}; + assign {out_packet_signals, out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data}; + assign {out_packet_signals, out_data} = out_payload; + end + end + end + else begin + assign out_packet_signals = 0; + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_error, in_channel}; + assign {out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_data, in_error}; + assign {out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_channel}; + assign {out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = in_data; + assign out_data = out_payload; + end + end + end + endgenerate + + // -------------------------------------------------- + // Memory-based FIFO storage + // + // To allow a ready latency of 0, the read index is + // obtained from the next read pointer and memory + // outputs are unregistered. + // + // If the empty latency is 1, we infer bypass logic + // around the memory so writes propagate to the + // outputs on the next cycle. + // + // Do not change the way this is coded: Quartus needs + // a perfect match to the template, and any attempt to + // refactor the two always blocks into one will break + // memory inference. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + if (EMPTY_LATENCY == 1) begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] = in_payload; + + internal_out_payload = mem[mem_rd_ptr]; + end + + end else begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] <= in_payload; + + internal_out_payload <= mem[mem_rd_ptr]; + end + + end + + assign mem_rd_ptr = next_rd_ptr; + + end else begin + + // -------------------------------------------------- + // Register-based FIFO storage + // + // Uses a shift register as the storage element. Each + // shift register slot has a bit which indicates if + // the slot is occupied (credit to Sam H for the idea). + // The occupancy bits are contiguous and start from the + // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep + // FIFO. + // + // Each slot is enabled during a read or when it + // is unoccupied. New data is always written to every + // going-to-be-empty slot (we keep track of which ones + // are actually useful with the occupancy bits). On a + // read we shift occupied slots. + // + // The exception is the last slot, which always gets + // new data when it is unoccupied. + // -------------------------------------------------- + for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg + always @(posedge clk or posedge reset) begin + if (reset) begin + mem[i] <= 0; + end + else if (read || !mem_used[i]) begin + if (!mem_used[i+1]) + mem[i] <= in_payload; + else + mem[i] <= mem[i+1]; + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + mem[DEPTH-1] <= 0; + end + else begin + if (!mem_used[DEPTH-1]) + mem[DEPTH-1] <= in_payload; + + if (DEPTH == 1) begin + if (write) + mem[DEPTH-1] <= in_payload; + end + end + end + + end + endgenerate + + assign read = internal_out_ready && internal_out_valid && ok_to_forward; + assign write = in_ready && in_valid; + + // -------------------------------------------------- + // Pointer Management + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + + end else begin + + // -------------------------------------------------- + // Shift Register Occupancy Bits + // + // Consider a 4-deep FIFO with 2 entries: 0011 + // On a read and write, do not modify the bits. + // On a write, left-shift the bits to get 0111. + // On a read, right-shift the bits to get 0001. + // + // Also, on a write we set bit0 (the head), while + // clearing the tail on a read. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[0] <= 0; + end + else begin + if (write ^ read) begin + if (read) begin + if (DEPTH > 1) + mem_used[0] <= mem_used[1]; + else + mem_used[0] <= 0; + end + if (write) + mem_used[0] <= 1; + end + end + end + + if (DEPTH > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[DEPTH-1] <= 0; + end + else begin + if (write ^ read) begin + mem_used[DEPTH-1] <= 0; + if (write) + mem_used[DEPTH-1] <= mem_used[DEPTH-2]; + end + end + end + end + + for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic + always @(posedge clk, posedge reset) begin + if (reset) begin + mem_used[i] <= 0; + end + else begin + if (write ^ read) begin + if (read) + mem_used[i] <= mem_used[i+1]; + if (write) + mem_used[i] <= mem_used[i-1]; + end + end + end + end + + end + endgenerate + + + // -------------------------------------------------- + // Memory FIFO Status Management + // + // Generates the full and empty signals from the + // pointers. The FIFO is full when the next write + // pointer will be equal to the read pointer after + // a write. Reading from a FIFO clears full. + // + // The FIFO is empty when the next read pointer will + // be equal to the write pointer after a read. Writing + // to a FIFO clears empty. + // + // A simultaneous read and write must not change any of + // the empty or full flags unless there is a drop on error event. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + always @* begin + next_full = full; + next_empty = empty; + + if (read && !write) begin + next_full = 1'b0; + + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + + if (write && !read) begin + if (!drop_on_error) + next_empty = 1'b0; + else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo + next_empty = 1'b1; + + if (incremented_wr_ptr == rd_ptr && !drop_on_error) + next_full = 1'b1; + end + + if (write && read && drop_on_error) begin + if (sop_ptr == next_rd_ptr) + next_empty = 1'b1; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + empty <= 1; + full <= 0; + end + else begin + empty <= next_empty; + full <= next_full; + end + end + + end else begin + // -------------------------------------------------- + // Register FIFO Status Management + // + // Full when the tail occupancy bit is 1. Empty when + // the head occupancy bit is 0. + // -------------------------------------------------- + always @* begin + full = mem_used[DEPTH-1]; + empty = !mem_used[0]; + + // ------------------------------------------ + // For a single slot FIFO, reading clears the + // full status immediately. + // ------------------------------------------ + if (DEPTH == 1) + full = mem_used[0] && !read; + + internal_out_payload = mem[0]; + + // ------------------------------------------ + // Writes clear empty immediately for lookahead modes. + // Note that we use in_valid instead of write to avoid + // combinational loops (in lookahead mode, qualifying + // with in_ready is meaningless). + // + // In a 1-deep FIFO, a possible combinational loop runs + // from write -> out_valid -> out_ready -> write + // ------------------------------------------ + if (EMPTY_LATENCY == 0) begin + empty = !mem_used[0] && !in_valid; + + if (!mem_used[0] && in_valid) + internal_out_payload = in_payload; + end + end + + end + endgenerate + + // -------------------------------------------------- + // Avalon-ST Signals + // + // The in_ready signal is straightforward. + // + // To match memory latency when empty latency > 1, + // out_valid assertions must be delayed by one clock + // cycle. + // + // Note: out_valid deassertions must not be delayed or + // the FIFO will underflow. + // -------------------------------------------------- + assign in_ready = !full; + assign internal_out_ready = out_ready || !out_valid; + + generate if (EMPTY_LATENCY > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) + internal_out_valid <= 0; + else begin + internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; + + if (read) begin + if (incremented_rd_ptr == wr_ptr) + internal_out_valid <= 1'b0; + end + end + end + end else begin + always @* begin + internal_out_valid = !empty & ok_to_forward; + end + end + endgenerate + + // -------------------------------------------------- + // Single Output Pipeline Stage + // + // This output pipeline stage is enabled if the FIFO's + // empty latency is set to 3 (default). It is disabled + // for all other allowed latencies. + // + // Reason: The memory outputs are unregistered, so we have to + // register the output or fmax will drop if combinatorial + // logic is present on the output datapath. + // + // Q: The Avalon-ST spec says that I have to register my outputs + // But isn't the memory counted as a register? + // A: The path from the address lookup to the memory output is + // slow. Registering the memory outputs is a good idea. + // + // The registers get packed into the memory by the fitter + // which means minimal resources are consumed (the result + // is a altsyncram with registered outputs, available on + // all modern Altera devices). + // + // This output stage acts as an extra slot in the FIFO, + // and complicates the fill level. + // -------------------------------------------------- + generate if (EMPTY_LATENCY == 3) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + out_valid <= 0; + out_payload <= 0; + end + else begin + if (internal_out_ready) begin + out_valid <= internal_out_valid & ok_to_forward; + out_payload <= internal_out_payload; + end + end + end + end + else begin + always @* begin + out_valid = internal_out_valid; + out_payload = internal_out_payload; + end + end + endgenerate + + // -------------------------------------------------- + // Fill Level + // + // The fill level is calculated from the next write + // and read pointers to avoid unnecessary latency. + // + // If the output pipeline is enabled, the fill level + // must account for it, or we'll always be off by one. + // This may, or may not be important depending on the + // application. + // + // For now, we'll always calculate the exact fill level + // at the cost of an extra adder when the output stage + // is enabled. + // -------------------------------------------------- + generate if (USE_FILL_LEVEL) begin + wire [31:0] depth32; + assign depth32 = DEPTH; + always @(posedge clk or posedge reset) begin + if (reset) + fifo_fill_level <= 0; + else if (next_full & !drop_on_error) + fifo_fill_level <= depth32[ADDR_WIDTH:0]; + else begin + fifo_fill_level[ADDR_WIDTH] <= 1'b0; + fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; + end + end + + always @* begin + fill_level = fifo_fill_level; + + if (EMPTY_LATENCY == 3) + fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; + end + end + else begin + initial fill_level = 0; + end + endgenerate + + generate if (USE_ALMOST_FULL_IF) begin + assign almost_full_data = (fill_level >= almost_full_threshold); + end + else + assign almost_full_data = 0; + endgenerate + + generate if (USE_ALMOST_EMPTY_IF) begin + assign almost_empty_data = (fill_level <= almost_empty_threshold); + end + else + assign almost_empty_data = 0; + endgenerate + + // -------------------------------------------------- + // Avalon-MM Status & Control Connection Point + // + // Register map: + // + // | Addr | RW | 31 - 0 | + // | 0 | R | Fill level | + // + // The registering of this connection point means + // that there is a cycle of latency between + // reads/writes and the updating of the fill level. + // -------------------------------------------------- + generate if (USE_STORE_FORWARD) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + cut_through_threshold <= 0; + drop_on_error_en <= 0; + csr_readdata <= 0; + pkt_mode <= 1'b1; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b100) begin + cut_through_threshold <= csr_writedata[23:0]; + pkt_mode <= (csr_writedata[23:0] == 0); + end + if(csr_address == 3'b101) + drop_on_error_en <= csr_writedata[0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + if (csr_address == 4) + csr_readdata <= {8'b0, cut_through_threshold}; + if (csr_address == 5) + csr_readdata <= {31'b0, drop_on_error_en}; + end + end + end + end + else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + csr_readdata <= 0; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + end + end + end + end + else begin + always @(posedge clk or posedge reset) begin + if (reset) begin + csr_readdata <= 0; + end + else if (csr_read) begin + csr_readdata <= 0; + + if (csr_address == 0) + csr_readdata <= fill_level; + end + end + end + endgenerate + + // -------------------------------------------------- + // Store and forward logic + // -------------------------------------------------- + // if the fifo gets full before the entire packet or the + // cut-threshold condition is met then start sending out + // data in order to avoid dead-lock situation + + generate if (USE_STORE_FORWARD) begin + assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; + assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); + assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : + ~wait_for_threshold) | fifo_too_small_r; + assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; + assign in_pkt_start = in_valid & in_ready & in_startofpacket; + assign in_pkt_error = in_valid & in_ready & |in_error; + assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; + assign out_pkt_leave = out_valid & out_ready & out_endofpacket; + assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; + + // count packets coming and going into the fifo + always @(posedge clk or posedge reset) begin + if (reset) begin + pkt_cnt <= 0; + pkt_cnt_r <= 0; + pkt_cnt_plusone <= 1; + pkt_cnt_minusone <= 0; + pkt_cnt_changed <= 0; + pkt_has_started <= 0; + sop_has_left_fifo <= 0; + fifo_too_small_r <= 0; + pkt_cnt_eq_zero <= 1'b1; + pkt_cnt_eq_one <= 1'b0; + fifo_fill_level_lt_cut_through_threshold <= 1'b1; + end + else begin + fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; + fifo_too_small_r <= fifo_too_small; + pkt_cnt_plusone <= pkt_cnt + 1'b1; + pkt_cnt_minusone <= pkt_cnt - 1'b1; + pkt_cnt_r <= pkt_cnt; + pkt_cnt_changed <= 1'b0; + + if( in_pkt_eop_arrive ) + sop_has_left_fifo <= 1'b0; + else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) + sop_has_left_fifo <= 1'b1; + + if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; + pkt_cnt_eq_zero <= 0; + if (pkt_cnt == 0) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; + if (pkt_cnt == 1) + pkt_cnt_eq_zero <= 1'b1; + else + pkt_cnt_eq_zero <= 1'b0; + if (pkt_cnt == 2) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + + if (in_pkt_start) + pkt_has_started <= 1'b1; + else if (in_pkt_eop_arrive) + pkt_has_started <= 1'b0; + end + end + + // drop on error logic + always @(posedge clk or posedge reset) begin + if (reset) begin + sop_ptr <= 0; + error_in_pkt <= 0; + end + else begin + // save the location of the SOP + if ( in_pkt_start ) + sop_ptr <= wr_ptr; + + // remember if error in pkt + // log error only if packet has already started + if (in_pkt_eop_arrive) + error_in_pkt <= 1'b0; + else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) + error_in_pkt <= 1'b1; + end + end + assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & + ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); + + end + else begin + assign ok_to_forward = 1'b1; + assign drop_on_error = 1'b0; + end + endgenerate + + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + integer i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv b/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv index 9edba1d..00dc788 100644 --- a/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv +++ b/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv @@ -11,260 +11,260 @@ // agreement for further details. -// (C) 2001-2010 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ -// $Revision: #3 $ -// $Date: 2010/07/07 $ -// $Author: jyeap $ - -/* ----------------------------------------------------------------------- -Round-robin/fixed arbitration implementation. - -Q: how do you find the least-significant set-bit in an n-bit binary number, X? - -A: M = X & (~X + 1) - -Example: X = 101000100 - 101000100 & - 010111011 + 1 = - - 101000100 & - 010111100 = - ----------- - 000000100 - -The method can be generalized to find the first set-bit -at a bit index no lower than bit-index N, simply by adding -2**N rather than 1. - - -Q: how does this relate to round-robin arbitration? -A: -Let X be the concatenation of all request signals. -Let the number to be added to X (hereafter called the -top_priority) initialize to 1, and be assigned from the -concatenation of the previous saved-grant, left-rotated -by one position, each time arbitration occurs. The -concatenation of grants is then M. - -Problem: consider this case: - -top_priority = 010000 -request = 001001 -~request + top_priority = 000110 -next_grant = 000000 <- no one is granted! - -There was no "set bit at a bit index no lower than bit-index 4", so -the result was 0. - -We need to propagate the carry out from (~request + top_priority) to the LSB, so -that the sum becomes 000111, and next_grant is 000001. This operation could be -called a "circular add". - -A bit of experimentation on the circular add reveals a significant amount of -delay in exiting and re-entering the carry chain - this will vary with device -family. Quartus also reports a combinational loop warning. Finally, -Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But -Modelsim _doesn't_ report a combinational loop!) - -An alternate solution: concatenate the request vector with itself, and OR -corresponding bits from the top and bottom halves to determine next_grant. - -Example: - -top_priority = 010000 -{request, request} = 001001 001001 -{~request, ~request} + top_priority = 110111 000110 -result of & operation = 000001 000000 -next_grant = 000001 - -Notice that if request = 0, the sum operation will overflow, but we can ignore -this; the next_grant result is 0 (no one granted), as you might expect. -In the implementation, the last-granted value must be maintained as -a non-zero value - best probably simply not to update it when no requests -occur. - ------------------------------------------------------------------------ */ - -`timescale 1 ns / 1 ns - -module altera_merlin_arbitrator -#( - parameter NUM_REQUESTERS = 8, - // -------------------------------------- - // Implemented schemes - // "round-robin" - // "fixed-priority" - // "no-arb" - // -------------------------------------- - parameter SCHEME = "round-robin", - parameter PIPELINE = 0 -) -( - input clk, - input reset, - - // -------------------------------------- - // Requests - // -------------------------------------- - input [NUM_REQUESTERS-1:0] request, - - // -------------------------------------- - // Grants - // -------------------------------------- - output [NUM_REQUESTERS-1:0] grant, - - // -------------------------------------- - // Control Signals - // -------------------------------------- - input increment_top_priority, - input save_top_priority -); - - // -------------------------------------- - // Signals - // -------------------------------------- - wire [NUM_REQUESTERS-1:0] top_priority; - reg [NUM_REQUESTERS-1:0] top_priority_reg; - reg [NUM_REQUESTERS-1:0] last_grant; - wire [2*NUM_REQUESTERS-1:0] result; - - // -------------------------------------- - // Scheme Selection - // -------------------------------------- - generate - if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin - assign top_priority = top_priority_reg; - end - else begin - // Fixed arbitration (or single-requester corner case) - assign top_priority = 1'b1; - end - endgenerate - - // -------------------------------------- - // Decision Logic - // -------------------------------------- - altera_merlin_arb_adder - #( - .WIDTH (2 * NUM_REQUESTERS) - ) - adder - ( - .a ({ ~request, ~request }), - .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), - .sum (result) - ); - - - generate if (SCHEME == "no-arb") begin - - // -------------------------------------- - // No arbitration: just wire request directly to grant - // -------------------------------------- - assign grant = request; - - end else begin - // Do the math in double-vector domain - wire [2*NUM_REQUESTERS-1:0] grant_double_vector; - assign grant_double_vector = {request, request} & result; - - // -------------------------------------- - // Extract grant from the top and bottom halves - // of the double vector. - // -------------------------------------- - assign grant = - grant_double_vector[NUM_REQUESTERS - 1 : 0] | - grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; - - end - endgenerate - - // -------------------------------------- - // Left-rotate the last grant vector to create top_priority. - // -------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - top_priority_reg <= 1'b1; - end - else begin - if (PIPELINE) begin - if (increment_top_priority) begin - top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1]} : top_priority_reg; - end - end else begin - if (save_top_priority) begin - top_priority_reg <= grant; - end - if (increment_top_priority) begin - if (|request) - top_priority_reg <= { grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1] }; - else - top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; - end - end - end - end - -endmodule - -// ---------------------------------------------- -// Adder for the standard arbitrator -// ---------------------------------------------- -module altera_merlin_arb_adder -#( - parameter WIDTH = 8 -) -( - input [WIDTH-1:0] a, - input [WIDTH-1:0] b, - - output [WIDTH-1:0] sum -); - - // ---------------------------------------------- - // Benchmarks indicate that for small widths, the full - // adder has higher fmax because synthesis can merge - // it with the mux, allowing partial decisions to be - // made early. - // - // The magic number is 4 requesters, which means an - // 8 bit adder. - // ---------------------------------------------- - genvar i; - generate if (WIDTH <= 8) begin : full_adder - - wire cout[WIDTH-1:0]; - - assign sum[0] = (a[0] ^ b[0]); - assign cout[0] = (a[0] & b[0]); - - for (i = 1; i < WIDTH; i = i+1) begin : arb - - assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; - assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); - - end - - end else begin : carry_chain - - assign sum = a + b; - - end - endgenerate - -endmodule +// (C) 2001-2010 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ +// $Revision: #3 $ +// $Date: 2010/07/07 $ +// $Author: jyeap $ + +/* ----------------------------------------------------------------------- +Round-robin/fixed arbitration implementation. + +Q: how do you find the least-significant set-bit in an n-bit binary number, X? + +A: M = X & (~X + 1) + +Example: X = 101000100 + 101000100 & + 010111011 + 1 = + + 101000100 & + 010111100 = + ----------- + 000000100 + +The method can be generalized to find the first set-bit +at a bit index no lower than bit-index N, simply by adding +2**N rather than 1. + + +Q: how does this relate to round-robin arbitration? +A: +Let X be the concatenation of all request signals. +Let the number to be added to X (hereafter called the +top_priority) initialize to 1, and be assigned from the +concatenation of the previous saved-grant, left-rotated +by one position, each time arbitration occurs. The +concatenation of grants is then M. + +Problem: consider this case: + +top_priority = 010000 +request = 001001 +~request + top_priority = 000110 +next_grant = 000000 <- no one is granted! + +There was no "set bit at a bit index no lower than bit-index 4", so +the result was 0. + +We need to propagate the carry out from (~request + top_priority) to the LSB, so +that the sum becomes 000111, and next_grant is 000001. This operation could be +called a "circular add". + +A bit of experimentation on the circular add reveals a significant amount of +delay in exiting and re-entering the carry chain - this will vary with device +family. Quartus also reports a combinational loop warning. Finally, +Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But +Modelsim _doesn't_ report a combinational loop!) + +An alternate solution: concatenate the request vector with itself, and OR +corresponding bits from the top and bottom halves to determine next_grant. + +Example: + +top_priority = 010000 +{request, request} = 001001 001001 +{~request, ~request} + top_priority = 110111 000110 +result of & operation = 000001 000000 +next_grant = 000001 + +Notice that if request = 0, the sum operation will overflow, but we can ignore +this; the next_grant result is 0 (no one granted), as you might expect. +In the implementation, the last-granted value must be maintained as +a non-zero value - best probably simply not to update it when no requests +occur. + +----------------------------------------------------------------------- */ + +`timescale 1 ns / 1 ns + +module altera_merlin_arbitrator +#( + parameter NUM_REQUESTERS = 8, + // -------------------------------------- + // Implemented schemes + // "round-robin" + // "fixed-priority" + // "no-arb" + // -------------------------------------- + parameter SCHEME = "round-robin", + parameter PIPELINE = 0 +) +( + input clk, + input reset, + + // -------------------------------------- + // Requests + // -------------------------------------- + input [NUM_REQUESTERS-1:0] request, + + // -------------------------------------- + // Grants + // -------------------------------------- + output [NUM_REQUESTERS-1:0] grant, + + // -------------------------------------- + // Control Signals + // -------------------------------------- + input increment_top_priority, + input save_top_priority +); + + // -------------------------------------- + // Signals + // -------------------------------------- + wire [NUM_REQUESTERS-1:0] top_priority; + reg [NUM_REQUESTERS-1:0] top_priority_reg; + reg [NUM_REQUESTERS-1:0] last_grant; + wire [2*NUM_REQUESTERS-1:0] result; + + // -------------------------------------- + // Scheme Selection + // -------------------------------------- + generate + if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin + assign top_priority = top_priority_reg; + end + else begin + // Fixed arbitration (or single-requester corner case) + assign top_priority = 1'b1; + end + endgenerate + + // -------------------------------------- + // Decision Logic + // -------------------------------------- + altera_merlin_arb_adder + #( + .WIDTH (2 * NUM_REQUESTERS) + ) + adder + ( + .a ({ ~request, ~request }), + .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), + .sum (result) + ); + + + generate if (SCHEME == "no-arb") begin + + // -------------------------------------- + // No arbitration: just wire request directly to grant + // -------------------------------------- + assign grant = request; + + end else begin + // Do the math in double-vector domain + wire [2*NUM_REQUESTERS-1:0] grant_double_vector; + assign grant_double_vector = {request, request} & result; + + // -------------------------------------- + // Extract grant from the top and bottom halves + // of the double vector. + // -------------------------------------- + assign grant = + grant_double_vector[NUM_REQUESTERS - 1 : 0] | + grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; + + end + endgenerate + + // -------------------------------------- + // Left-rotate the last grant vector to create top_priority. + // -------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + top_priority_reg <= 1'b1; + end + else begin + if (PIPELINE) begin + if (increment_top_priority) begin + top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1]} : top_priority_reg; + end + end else begin + if (save_top_priority) begin + top_priority_reg <= grant; + end + if (increment_top_priority) begin + if (|request) + top_priority_reg <= { grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1] }; + else + top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; + end + end + end + end + +endmodule + +// ---------------------------------------------- +// Adder for the standard arbitrator +// ---------------------------------------------- +module altera_merlin_arb_adder +#( + parameter WIDTH = 8 +) +( + input [WIDTH-1:0] a, + input [WIDTH-1:0] b, + + output [WIDTH-1:0] sum +); + + // ---------------------------------------------- + // Benchmarks indicate that for small widths, the full + // adder has higher fmax because synthesis can merge + // it with the mux, allowing partial decisions to be + // made early. + // + // The magic number is 4 requesters, which means an + // 8 bit adder. + // ---------------------------------------------- + genvar i; + generate if (WIDTH <= 8) begin : full_adder + + wire cout[WIDTH-1:0]; + + assign sum[0] = (a[0] ^ b[0]); + assign cout[0] = (a[0] & b[0]); + + for (i = 1; i < WIDTH; i = i+1) begin : arb + + assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; + assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); + + end + + end else begin : carry_chain + + assign sum = a + b; + + end + endgenerate + +endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv b/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv index 30eaf7d..9b49c44 100644 --- a/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv +++ b/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv @@ -11,276 +11,276 @@ // agreement for further details. -// (C) 2001-2012 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Burst Uncompressor -// -// Compressed read bursts -> uncompressed -// ------------------------------------------ - -`timescale 1 ns / 1 ns - -module altera_merlin_burst_uncompressor -#( - parameter ADDR_W = 16, - parameter BURSTWRAP_W = 3, - parameter BYTE_CNT_W = 4, - parameter PKT_SYMBOLS = 4, - parameter BURST_SIZE_W = 3 -) -( - input clk, - input reset, - - // sink ST signals - input sink_startofpacket, - input sink_endofpacket, - input sink_valid, - output sink_ready, - - // sink ST "data" - input [ADDR_W - 1: 0] sink_addr, - input [BURSTWRAP_W - 1 : 0] sink_burstwrap, - input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, - input sink_is_compressed, - input [BURST_SIZE_W-1 : 0] sink_burstsize, - - // source ST signals - output source_startofpacket, - output source_endofpacket, - output source_valid, - input source_ready, - - // source ST "data" - output [ADDR_W - 1: 0] source_addr, - output [BURSTWRAP_W - 1 : 0] source_burstwrap, - output [BYTE_CNT_W - 1 : 0] source_byte_cnt, - - // Note: in the slave agent, the output should always be uncompressed. In - // other applications, it may be required to leave-compressed or not. How to - // control? Seems like a simple mux - pass-through if no uncompression is - // required. - output source_is_compressed, - output [BURST_SIZE_W-1 : 0] source_burstsize -); - -//---------------------------------------------------- -// AXSIZE decoding -// -// Turns the axsize value into the actual number of bytes -// being transferred. -// --------------------------------------------------- -function reg[63:0] bytes_in_transfer; - input [2:0] axsize; - case (axsize) - 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; - 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; - 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; - 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; - 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; - 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; - 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; - default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - endcase - -endfunction - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - // def: Burst Compression. In a merlin network, a compressed burst is one - // which is transmitted in a single beat. Example: read burst. In - // constrast, an uncompressed burst (example: write burst) is transmitted in - // one beat per writedata item. - // - // For compressed bursts which require response packets, burst - // uncompression is required. Concrete example: a read burst of size 8 - // occupies one response-fifo position. When that fifo position reaches the - // front of the FIFO, the slave starts providing the required 8 readdatavalid - // pulses. The 8 return response beats must be provided in a single packet, - // with incrementing address and decrementing byte_cnt fields. Upon receipt - // of the final readdata item of the burst, the response FIFO item is - // retired. - // Burst uncompression logic provides: - // a) 2-state FSM (idle, busy) - // reset to idle state - // transition to busy state for 2nd and subsequent rdv pulses - // - a single-cycle burst (aka non-burst read) causes no transition to - // busy state. - // b) response startofpacket/endofpacket logic. The response FIFO item - // will have sop asserted, and may have eop asserted. (In the case of - // multiple read bursts transmit in the command fabric in a single packet, - // the eop assertion will come in a later FIFO item.) To support packet - // conservation, and emit a well-formed packet on the response fabric, - // i) response fabric startofpacket is asserted only for the first resp. - // beat; - // ii) response fabric endofpacket is asserted only for the last resp. - // beat. - // c) response address field. The response address field contains an - // incrementing sequence, such that each readdata item is associated with - // its slave-map location. N.b. a) computing the address correctly requires - // knowledge of burstwrap behavior b) there may be no clients of the address - // field, which makes this field a good target for optimization. See - // burst_uncompress_address_counter below. - // d) response byte_cnt field. The response byte_cnt field contains a - // decrementing sequence, such that each beat of the response contains the - // count of bytes to follow. In the case of sub-bursts in a single packet, - // the byte_cnt field may decrement down to num_symbols, then back up to - // some value, multiple times in the packet. - - reg burst_uncompress_busy; - reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; - wire first_packet_beat; - wire last_packet_beat; - - assign first_packet_beat = sink_valid & ~burst_uncompress_busy; - - // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to - // the output. - assign source_byte_cnt = - first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; - assign source_valid = sink_valid; - - // Last packet beat is set throughout receipt of an uncompressed read burst - // from the response FIFO - this forces all the burst uncompression machinery - // idle. - assign last_packet_beat = ~sink_is_compressed | - ( - burst_uncompress_busy ? - (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : - sink_valid & (sink_byte_cnt == num_symbols) - ); - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (source_valid & source_ready & sink_valid) begin - // No matter what the current state, last_packet_beat leads to - // idle. - if (last_packet_beat) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (burst_uncompress_busy) begin - burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? - (burst_uncompress_byte_counter - num_symbols) : - (sink_byte_cnt - num_symbols); - end - else begin // not busy, at least one more beat to go - burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; - // To do: should busy go true for numsymbols-size compressed - // bursts? - burst_uncompress_busy <= '1; - end - end - end - end - end - - wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; - reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; - reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; - - wire [63:0] decoded_burstsize_wire; - wire [ADDR_W-1:0] decoded_burstsize; - - // The input burstwrap value can be used as a mask against address values, - // but with one caveat: the address width may be (probably is) wider than - // the burstwrap width. The spec says: extend the msb of the burstwrap - // value out over the entire address width (but only if the address width - // actually is wider than the burstwrap width; otherwise it's a 0-width or - // negative range and concatenation multiplier). - assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; - generate - if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend - // Sign-extend, just wires: - assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = - {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; - end - endgenerate - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_base <= '0; - end - else if (first_packet_beat & source_ready) begin - burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; - end - end - - assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits - assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed - - wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = - ( - (first_packet_beat ? - sink_addr : - burst_uncompress_address_offset) + decoded_burstsize - ) & - addr_width_burstwrap; - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_offset <= '0; - end - else begin - if (source_ready & source_valid) begin - burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; - // if (first_packet_beat) begin - // burst_uncompress_address_offset <= - // (sink_addr + num_symbols) & addr_width_burstwrap; - // end - // else begin - // burst_uncompress_address_offset <= - // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; - // end - end - end - end - - // On the first packet beat, send the input address out unchanged, - // while values are computed/registered for 2nd and subsequent beats. - assign source_addr = first_packet_beat ? sink_addr : - burst_uncompress_address_base | burst_uncompress_address_offset; - assign source_burstwrap = sink_burstwrap; - assign source_burstsize = sink_burstsize; - - //------------------------------------------------------------------- - // A single (compressed) read burst will have sop/eop in the same beat. - // A sequence of read sub-bursts emitted by a burst adapter in response to a - // single read burst will have sop on the first sub-burst, eop on the last. - // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve - // packet conservation. - assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; - assign source_endofpacket = sink_endofpacket & last_packet_beat; - assign sink_ready = source_valid & source_ready & last_packet_beat; - - // This is correct for the slave agent usage, but won't always be true in the - // width adapter. To do: add an "please uncompress" input, and use it to - // pass-through or modify, and set source_is_compressed accordingly. - assign source_is_compressed = 1'b0; -endmodule - +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Burst Uncompressor +// +// Compressed read bursts -> uncompressed +// ------------------------------------------ + +`timescale 1 ns / 1 ns + +module altera_merlin_burst_uncompressor +#( + parameter ADDR_W = 16, + parameter BURSTWRAP_W = 3, + parameter BYTE_CNT_W = 4, + parameter PKT_SYMBOLS = 4, + parameter BURST_SIZE_W = 3 +) +( + input clk, + input reset, + + // sink ST signals + input sink_startofpacket, + input sink_endofpacket, + input sink_valid, + output sink_ready, + + // sink ST "data" + input [ADDR_W - 1: 0] sink_addr, + input [BURSTWRAP_W - 1 : 0] sink_burstwrap, + input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, + input sink_is_compressed, + input [BURST_SIZE_W-1 : 0] sink_burstsize, + + // source ST signals + output source_startofpacket, + output source_endofpacket, + output source_valid, + input source_ready, + + // source ST "data" + output [ADDR_W - 1: 0] source_addr, + output [BURSTWRAP_W - 1 : 0] source_burstwrap, + output [BYTE_CNT_W - 1 : 0] source_byte_cnt, + + // Note: in the slave agent, the output should always be uncompressed. In + // other applications, it may be required to leave-compressed or not. How to + // control? Seems like a simple mux - pass-through if no uncompression is + // required. + output source_is_compressed, + output [BURST_SIZE_W-1 : 0] source_burstsize +); + +//---------------------------------------------------- +// AXSIZE decoding +// +// Turns the axsize value into the actual number of bytes +// being transferred. +// --------------------------------------------------- +function reg[63:0] bytes_in_transfer; + input [2:0] axsize; + case (axsize) + 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; + 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; + 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; + 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; + 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; + 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; + 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; + default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + endcase + +endfunction + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + // def: Burst Compression. In a merlin network, a compressed burst is one + // which is transmitted in a single beat. Example: read burst. In + // constrast, an uncompressed burst (example: write burst) is transmitted in + // one beat per writedata item. + // + // For compressed bursts which require response packets, burst + // uncompression is required. Concrete example: a read burst of size 8 + // occupies one response-fifo position. When that fifo position reaches the + // front of the FIFO, the slave starts providing the required 8 readdatavalid + // pulses. The 8 return response beats must be provided in a single packet, + // with incrementing address and decrementing byte_cnt fields. Upon receipt + // of the final readdata item of the burst, the response FIFO item is + // retired. + // Burst uncompression logic provides: + // a) 2-state FSM (idle, busy) + // reset to idle state + // transition to busy state for 2nd and subsequent rdv pulses + // - a single-cycle burst (aka non-burst read) causes no transition to + // busy state. + // b) response startofpacket/endofpacket logic. The response FIFO item + // will have sop asserted, and may have eop asserted. (In the case of + // multiple read bursts transmit in the command fabric in a single packet, + // the eop assertion will come in a later FIFO item.) To support packet + // conservation, and emit a well-formed packet on the response fabric, + // i) response fabric startofpacket is asserted only for the first resp. + // beat; + // ii) response fabric endofpacket is asserted only for the last resp. + // beat. + // c) response address field. The response address field contains an + // incrementing sequence, such that each readdata item is associated with + // its slave-map location. N.b. a) computing the address correctly requires + // knowledge of burstwrap behavior b) there may be no clients of the address + // field, which makes this field a good target for optimization. See + // burst_uncompress_address_counter below. + // d) response byte_cnt field. The response byte_cnt field contains a + // decrementing sequence, such that each beat of the response contains the + // count of bytes to follow. In the case of sub-bursts in a single packet, + // the byte_cnt field may decrement down to num_symbols, then back up to + // some value, multiple times in the packet. + + reg burst_uncompress_busy; + reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; + wire first_packet_beat; + wire last_packet_beat; + + assign first_packet_beat = sink_valid & ~burst_uncompress_busy; + + // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to + // the output. + assign source_byte_cnt = + first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; + assign source_valid = sink_valid; + + // Last packet beat is set throughout receipt of an uncompressed read burst + // from the response FIFO - this forces all the burst uncompression machinery + // idle. + assign last_packet_beat = ~sink_is_compressed | + ( + burst_uncompress_busy ? + (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : + sink_valid & (sink_byte_cnt == num_symbols) + ); + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (source_valid & source_ready & sink_valid) begin + // No matter what the current state, last_packet_beat leads to + // idle. + if (last_packet_beat) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (burst_uncompress_busy) begin + burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? + (burst_uncompress_byte_counter - num_symbols) : + (sink_byte_cnt - num_symbols); + end + else begin // not busy, at least one more beat to go + burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; + // To do: should busy go true for numsymbols-size compressed + // bursts? + burst_uncompress_busy <= '1; + end + end + end + end + end + + wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; + reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; + reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; + + wire [63:0] decoded_burstsize_wire; + wire [ADDR_W-1:0] decoded_burstsize; + + // The input burstwrap value can be used as a mask against address values, + // but with one caveat: the address width may be (probably is) wider than + // the burstwrap width. The spec says: extend the msb of the burstwrap + // value out over the entire address width (but only if the address width + // actually is wider than the burstwrap width; otherwise it's a 0-width or + // negative range and concatenation multiplier). + assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; + generate + if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend + // Sign-extend, just wires: + assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = + {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; + end + endgenerate + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_base <= '0; + end + else if (first_packet_beat & source_ready) begin + burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; + end + end + + assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits + assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed + + wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = + ( + (first_packet_beat ? + sink_addr : + burst_uncompress_address_offset) + decoded_burstsize + ) & + addr_width_burstwrap; + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_offset <= '0; + end + else begin + if (source_ready & source_valid) begin + burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; + // if (first_packet_beat) begin + // burst_uncompress_address_offset <= + // (sink_addr + num_symbols) & addr_width_burstwrap; + // end + // else begin + // burst_uncompress_address_offset <= + // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; + // end + end + end + end + + // On the first packet beat, send the input address out unchanged, + // while values are computed/registered for 2nd and subsequent beats. + assign source_addr = first_packet_beat ? sink_addr : + burst_uncompress_address_base | burst_uncompress_address_offset; + assign source_burstwrap = sink_burstwrap; + assign source_burstsize = sink_burstsize; + + //------------------------------------------------------------------- + // A single (compressed) read burst will have sop/eop in the same beat. + // A sequence of read sub-bursts emitted by a burst adapter in response to a + // single read burst will have sop on the first sub-burst, eop on the last. + // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve + // packet conservation. + assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; + assign source_endofpacket = sink_endofpacket & last_packet_beat; + assign sink_ready = source_valid & source_ready & last_packet_beat; + + // This is correct for the slave agent usage, but won't always be true in the + // width adapter. To do: add an "please uncompress" input, and use it to + // pass-through or modify, and set source_is_compressed accordingly. + assign source_is_compressed = 1'b0; +endmodule + diff --git a/db/ip/nios_system/submodules/altera_merlin_master_agent.sv b/db/ip/nios_system/submodules/altera_merlin_master_agent.sv index 305107d..070f26f 100644 --- a/db/ip/nios_system/submodules/altera_merlin_master_agent.sv +++ b/db/ip/nios_system/submodules/altera_merlin_master_agent.sv @@ -11,299 +11,299 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Agent -// -// Converts Avalon-MM transactions into -// Merlin network packets. -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_merlin_master_agent -#( - // ------------------- - // Packet Format Parameters - // ------------------- - parameter PKT_QOS_H = 109, - PKT_QOS_L = 106, - PKT_DATA_SIDEBAND_H = 105, - PKT_DATA_SIDEBAND_L = 98, - PKT_ADDR_SIDEBAND_H = 97, - PKT_ADDR_SIDEBAND_L = 93, - PKT_CACHE_H = 92, - PKT_CACHE_L = 89, - PKT_THREAD_ID_H = 88, - PKT_THREAD_ID_L = 87, - PKT_BEGIN_BURST = 81, - PKT_PROTECTION_H = 80, - PKT_PROTECTION_L = 80, - PKT_BURSTWRAP_H = 79, - PKT_BURSTWRAP_L = 77, - PKT_BYTE_CNT_H = 76, - PKT_BYTE_CNT_L = 74, - PKT_ADDR_H = 73, - PKT_ADDR_L = 42, - PKT_BURST_SIZE_H = 86, - PKT_BURST_SIZE_L = 84, - PKT_BURST_TYPE_H = 94, - PKT_BURST_TYPE_L = 93, - PKT_TRANS_EXCLUSIVE = 83, - PKT_TRANS_LOCK = 82, - PKT_TRANS_COMPRESSED_READ = 41, - PKT_TRANS_POSTED = 40, - PKT_TRANS_WRITE = 39, - PKT_TRANS_READ = 38, - PKT_DATA_H = 37, - PKT_DATA_L = 6, - PKT_BYTEEN_H = 5, - PKT_BYTEEN_L = 2, - PKT_SRC_ID_H = 1, - PKT_SRC_ID_L = 1, - PKT_DEST_ID_H = 0, - PKT_DEST_ID_L = 0, - PKT_RESPONSE_STATUS_L = 110, - PKT_RESPONSE_STATUS_H = 111, - ST_DATA_W = 112, - ST_CHANNEL_W = 1, - - // ------------------- - // Agent Parameters - // ------------------- - AV_BURSTCOUNT_W = 3, - ID = 1, - SUPPRESS_0_BYTEEN_RSP = 1, - BURSTWRAP_VALUE = 4, - CACHE_VALUE = 0, - SECURE_ACCESS_BIT = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - // ------------------- - // Derived Parameters - // ------------------- - PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, - PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, - PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, - PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, - PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 -) -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Avalon-MM Anti-Master - // ------------------- - input [PKT_ADDR_W-1 : 0] av_address, - input av_write, - input av_read, - input [PKT_DATA_W-1 : 0] av_writedata, - output reg [PKT_DATA_W-1 : 0] av_readdata, - output reg av_waitrequest, - output reg av_readdatavalid, - input [PKT_BYTEEN_W-1 : 0] av_byteenable, - input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, - input av_debugaccess, - input av_lock, - output reg [1:0] av_response, - input av_writeresponserequest, - output reg av_writeresponsevalid, - - // ------------------- - // Command Source - // ------------------- - output reg cp_valid, - output reg [ST_DATA_W-1 : 0] cp_data, - output wire cp_startofpacket, - output wire cp_endofpacket, - input cp_ready, - - // ------------------- - // Response Sink - // ------------------- - input rp_valid, - input [ST_DATA_W-1 : 0] rp_data, - input [ST_CHANNEL_W-1 : 0] rp_channel, - input rp_startofpacket, - input rp_endofpacket, - output reg rp_ready -); - // ------------------------------------------------------------ - // Utility Functions - // ------------------------------------------------------------ - function integer clogb2; - input [31:0] value; - begin - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) - value = value >> 1; - clogb2 = clogb2 - 1; - end - endfunction // clogb2 - - localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); - localparam NUMSYMBOLS = PKT_BYTEEN_W; - localparam BURSTING = (MAX_BURST > NUMSYMBOLS); - localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); - localparam BURST_SIZE = clogb2(NUMSYMBOLS); - - typedef enum bit [1:0] - { - FIXED = 2'b00, - INCR = 2'b01, - WRAP = 2'b10, - OTHER_WRAP = 2'b11 - } MerlinBurstType; - - // -------------------------------------- - // Potential optimization: compare in words to save bits? - // -------------------------------------- - wire is_burst; - assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); - - wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; - wire [31:0] id_int = ID; - wire [2:0] burstsize_sig = BURST_SIZE[2:0]; - wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; - - // -------------------------------------- - // Address alignment - // - // The packet format requires that addresses be aligned to - // the transaction size. - // -------------------------------------- - wire [PKT_ADDR_W-1 : 0] av_address_aligned; - generate - if (NUMSYMBOLS > 1) begin - assign av_address_aligned = - {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; - end - else begin - assign av_address_aligned = av_address; - end - endgenerate - - // -------------------------------------- - // Command & Response Construction - // -------------------------------------- - always @* begin - cp_data = '0; // default assignment; override below as needed. - - cp_data[PKT_PROTECTION_L] = av_debugaccess; - cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) - cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) - cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; - cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; - cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; - cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; - cp_data[PKT_TRANS_LOCK ] = av_lock; - cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; - cp_data[PKT_TRANS_READ ] = av_read; - cp_data[PKT_TRANS_WRITE ] = av_write; - // posted and non-posted write avaiable now - cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; - cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; - cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; - cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; - cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; - cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; - cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; - cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; - cp_data[PKT_QOS_H : PKT_QOS_L] = '0; - cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; - cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; - - av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; - if (USE_WRITERESPONSE || USE_READRESPONSE) - av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; - else - av_response = '0; - - end - - // -------------------------------------- - // Command Control - // -------------------------------------- - always @* begin - cp_valid = 0; - - if (av_write || av_read) - cp_valid = 1; - end - - generate if (BURSTING) begin - reg sop_enable; - - always @(posedge clk, posedge reset) begin - if (reset) begin - sop_enable <= 1'b1; - end - else begin - if (cp_valid && cp_ready) begin - sop_enable <= 1'b0; - if (cp_endofpacket) - sop_enable <= 1'b1; - end - end - end - - assign cp_startofpacket = sop_enable; - assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); - - end - else begin - - assign cp_startofpacket = 1'b1; - assign cp_endofpacket = 1'b1; - - end - endgenerate - - // -------------------------------------- - // Backpressure & Readdatavalid - // -------------------------------------- - reg hold_waitrequest; - - always @ (posedge clk, posedge reset) begin - if (reset) - hold_waitrequest <= 1'b1; - else - hold_waitrequest <= 1'b0; - end - - always @* begin - rp_ready = 1; - av_readdatavalid = 0; - av_writeresponsevalid = 0; - av_waitrequest = hold_waitrequest | !cp_ready; - - // -------------------------------------- - // Currently, responses are _always_ read responses because - // this Avalon agent only issues posted writes, which do - // not have responses. -> not true for now - // Now Avalon supports response, so based on type of transaction - // return, assert correct thing - // -------------------------------------- - if (rp_data[PKT_TRANS_WRITE] == 1) - av_writeresponsevalid = rp_valid; - else - av_readdatavalid = rp_valid; - - if (SUPPRESS_0_BYTEEN_RSP) begin - if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) - av_readdatavalid = 0; - end - end - -endmodule +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Agent +// +// Converts Avalon-MM transactions into +// Merlin network packets. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_agent +#( + // ------------------- + // Packet Format Parameters + // ------------------- + parameter PKT_QOS_H = 109, + PKT_QOS_L = 106, + PKT_DATA_SIDEBAND_H = 105, + PKT_DATA_SIDEBAND_L = 98, + PKT_ADDR_SIDEBAND_H = 97, + PKT_ADDR_SIDEBAND_L = 93, + PKT_CACHE_H = 92, + PKT_CACHE_L = 89, + PKT_THREAD_ID_H = 88, + PKT_THREAD_ID_L = 87, + PKT_BEGIN_BURST = 81, + PKT_PROTECTION_H = 80, + PKT_PROTECTION_L = 80, + PKT_BURSTWRAP_H = 79, + PKT_BURSTWRAP_L = 77, + PKT_BYTE_CNT_H = 76, + PKT_BYTE_CNT_L = 74, + PKT_ADDR_H = 73, + PKT_ADDR_L = 42, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + PKT_BURST_TYPE_H = 94, + PKT_BURST_TYPE_L = 93, + PKT_TRANS_EXCLUSIVE = 83, + PKT_TRANS_LOCK = 82, + PKT_TRANS_COMPRESSED_READ = 41, + PKT_TRANS_POSTED = 40, + PKT_TRANS_WRITE = 39, + PKT_TRANS_READ = 38, + PKT_DATA_H = 37, + PKT_DATA_L = 6, + PKT_BYTEEN_H = 5, + PKT_BYTEEN_L = 2, + PKT_SRC_ID_H = 1, + PKT_SRC_ID_L = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + PKT_RESPONSE_STATUS_L = 110, + PKT_RESPONSE_STATUS_H = 111, + ST_DATA_W = 112, + ST_CHANNEL_W = 1, + + // ------------------- + // Agent Parameters + // ------------------- + AV_BURSTCOUNT_W = 3, + ID = 1, + SUPPRESS_0_BYTEEN_RSP = 1, + BURSTWRAP_VALUE = 4, + CACHE_VALUE = 0, + SECURE_ACCESS_BIT = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + // ------------------- + // Derived Parameters + // ------------------- + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, + PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 +) +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Avalon-MM Anti-Master + // ------------------- + input [PKT_ADDR_W-1 : 0] av_address, + input av_write, + input av_read, + input [PKT_DATA_W-1 : 0] av_writedata, + output reg [PKT_DATA_W-1 : 0] av_readdata, + output reg av_waitrequest, + output reg av_readdatavalid, + input [PKT_BYTEEN_W-1 : 0] av_byteenable, + input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, + input av_debugaccess, + input av_lock, + output reg [1:0] av_response, + input av_writeresponserequest, + output reg av_writeresponsevalid, + + // ------------------- + // Command Source + // ------------------- + output reg cp_valid, + output reg [ST_DATA_W-1 : 0] cp_data, + output wire cp_startofpacket, + output wire cp_endofpacket, + input cp_ready, + + // ------------------- + // Response Sink + // ------------------- + input rp_valid, + input [ST_DATA_W-1 : 0] rp_data, + input [ST_CHANNEL_W-1 : 0] rp_channel, + input rp_startofpacket, + input rp_endofpacket, + output reg rp_ready +); + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + function integer clogb2; + input [31:0] value; + begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); + localparam NUMSYMBOLS = PKT_BYTEEN_W; + localparam BURSTING = (MAX_BURST > NUMSYMBOLS); + localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); + localparam BURST_SIZE = clogb2(NUMSYMBOLS); + + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + OTHER_WRAP = 2'b11 + } MerlinBurstType; + + // -------------------------------------- + // Potential optimization: compare in words to save bits? + // -------------------------------------- + wire is_burst; + assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); + + wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; + wire [31:0] id_int = ID; + wire [2:0] burstsize_sig = BURST_SIZE[2:0]; + wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; + + // -------------------------------------- + // Address alignment + // + // The packet format requires that addresses be aligned to + // the transaction size. + // -------------------------------------- + wire [PKT_ADDR_W-1 : 0] av_address_aligned; + generate + if (NUMSYMBOLS > 1) begin + assign av_address_aligned = + {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; + end + else begin + assign av_address_aligned = av_address; + end + endgenerate + + // -------------------------------------- + // Command & Response Construction + // -------------------------------------- + always @* begin + cp_data = '0; // default assignment; override below as needed. + + cp_data[PKT_PROTECTION_L] = av_debugaccess; + cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) + cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) + cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; + cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; + cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; + cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; + cp_data[PKT_TRANS_LOCK ] = av_lock; + cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; + cp_data[PKT_TRANS_READ ] = av_read; + cp_data[PKT_TRANS_WRITE ] = av_write; + // posted and non-posted write avaiable now + cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; + cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; + cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; + cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; + cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; + cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; + cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; + cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; + cp_data[PKT_QOS_H : PKT_QOS_L] = '0; + cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; + cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; + + av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; + if (USE_WRITERESPONSE || USE_READRESPONSE) + av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; + else + av_response = '0; + + end + + // -------------------------------------- + // Command Control + // -------------------------------------- + always @* begin + cp_valid = 0; + + if (av_write || av_read) + cp_valid = 1; + end + + generate if (BURSTING) begin + reg sop_enable; + + always @(posedge clk, posedge reset) begin + if (reset) begin + sop_enable <= 1'b1; + end + else begin + if (cp_valid && cp_ready) begin + sop_enable <= 1'b0; + if (cp_endofpacket) + sop_enable <= 1'b1; + end + end + end + + assign cp_startofpacket = sop_enable; + assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); + + end + else begin + + assign cp_startofpacket = 1'b1; + assign cp_endofpacket = 1'b1; + + end + endgenerate + + // -------------------------------------- + // Backpressure & Readdatavalid + // -------------------------------------- + reg hold_waitrequest; + + always @ (posedge clk, posedge reset) begin + if (reset) + hold_waitrequest <= 1'b1; + else + hold_waitrequest <= 1'b0; + end + + always @* begin + rp_ready = 1; + av_readdatavalid = 0; + av_writeresponsevalid = 0; + av_waitrequest = hold_waitrequest | !cp_ready; + + // -------------------------------------- + // Currently, responses are _always_ read responses because + // this Avalon agent only issues posted writes, which do + // not have responses. -> not true for now + // Now Avalon supports response, so based on type of transaction + // return, assert correct thing + // -------------------------------------- + if (rp_data[PKT_TRANS_WRITE] == 1) + av_writeresponsevalid = rp_valid; + else + av_readdatavalid = rp_valid; + + if (SUPPRESS_0_BYTEEN_RSP) begin + if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) + av_readdatavalid = 0; + end + end + +endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_master_translator.sv b/db/ip/nios_system/submodules/altera_merlin_master_translator.sv index b2be2d2..a43760f 100644 --- a/db/ip/nios_system/submodules/altera_merlin_master_translator.sv +++ b/db/ip/nios_system/submodules/altera_merlin_master_translator.sv @@ -11,544 +11,544 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Translator -// -// Converts Avalon-MM Master Interfaces into -// Avalon-MM Universal Master Interfaces -// -------------------------------------- - -`timescale 1 ns / 1 ns - - - -module altera_merlin_master_translator #( - parameter - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - - //Optional Port Declarations - - USE_BURSTCOUNT = 1, - USE_BEGINBURSTTRANSFER = 0, - USE_BEGINTRANSFER = 0, - USE_CHIPSELECT = 0, - USE_READ = 1, - USE_READDATAVALID = 1, - USE_WRITE = 1, - USE_WAITREQUEST = 1, - USE_WRITERESPONSE = 0, - USE_READRESPONSE = 0, - - AV_REGISTERINCOMINGSIGNALS = 0, - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_CONSTANT_BURST_BEHAVIOR = 1, - AV_BURSTCOUNT_SYMBOLS = 0, - AV_LINEWRAPBURSTS = 0, - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_CONSTANT_BURST_BEHAVIOR = 0 - )( - //Universal Avalon Master - input wire clk, - input wire reset, - output reg uav_write, - output reg uav_read, - output reg [UAV_ADDRESS_W -1 : 0] uav_address, - output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, - output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, - output wire [AV_DATA_W -1 : 0] uav_writedata, - output wire uav_lock, - output wire uav_debugaccess, - output wire uav_clken, - - input wire [ AV_DATA_W -1 : 0] uav_readdata, - input wire uav_readdatavalid, - input wire uav_waitrequest, - input wire [1:0] uav_response, - output reg uav_writeresponserequest, - input wire uav_writeresponsevalid, - - //Avalon-MM !Master - input reg av_write, - input reg av_read, - input wire [AV_ADDRESS_W -1 : 0] av_address, - input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, - input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, - input wire [AV_DATA_W -1 : 0] av_writedata, - input wire av_begintransfer, - input wire av_beginbursttransfer, - input wire av_lock, - input wire av_chipselect, - input wire av_debugaccess, - input wire av_clken, - - output wire [AV_DATA_W -1 : 0] av_readdata, - output wire av_readdatavalid, - output reg av_waitrequest, - output reg [1:0] av_response, - input wire av_writeresponserequest, - output reg av_writeresponsevalid - - ); - - - localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); - localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); - localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; - - localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; - localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; - - - // -1 for burstcount restriction 2^(n-1) - - localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; - localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; - - localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; - localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; - - localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; - localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; - - function integer flog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - if ( i <= 0 ) flog2 = 0; - else begin - for(flog2 = -1; i > 0; flog2 = flog2 + 1) - i = i >> 1; - end - end - - endfunction // flog2 - - function integer clog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2 = 0; i > 0; clog2 = clog2 + 1) - i = i >> 1; - end - - endfunction - - function integer pow2; - input [31:0] toShift; - begin - pow2=1; - pow2= pow2 << toShift; - end - endfunction // pow2 - - // ------------------------------------------------- - // Assign some constants to appropriately-sized signals to - // avoid synthesis warnings. This also helps some simulators - // with their inferred sensitivity lists. - // ------------------------------------------------- - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); - wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; - - - reg internal_beginbursttransfer; - reg internal_begintransfer; - reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; - reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; - - - - reg uav_read_pre; - reg uav_write_pre; - reg read_accepted; - - //Passthru assignmenst - - assign uav_writedata = av_writedata; - assign av_readdata = uav_readdata; - assign uav_byteenable = av_byteenable; - assign uav_lock = av_lock; - assign av_readdatavalid = uav_readdatavalid; - assign uav_debugaccess = av_debugaccess; - assign uav_clken = av_clken; - - //Response signals - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) - av_response = '0; - else - av_response = uav_response; - if (USE_WRITERESPONSE) begin - uav_writeresponserequest = av_writeresponserequest; - av_writeresponsevalid = uav_writeresponsevalid; - end else begin - uav_writeresponserequest = '0; - av_writeresponsevalid = '0; - end - end - - //address + burstcount assignment - - reg [UAV_ADDRESS_W - 1 : 0] address_register; - reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; - - always @* begin - uav_address=uav_address_pre; - uav_burstcount=uav_burstcount_pre; - - if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin - uav_address=address_register; - uav_burstcount=burstcount_register; - end - end - - reg first_burst_stalled; - reg burst_stalled; - - - wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; - wire [UAV_ADDRESS_W-1:0] combi_addr_reg; - generate - if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin - if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - end - else begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - end - end - else begin - assign combi_burst_addr_reg = - uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - assign combi_addr_reg = - address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - end - endgenerate - - always@(posedge clk, posedge reset) begin - - if(reset) begin - address_register <= '0; - burstcount_register <= '0; - first_burst_stalled <= 1'b0; - burst_stalled <= 1'b0; - end - else begin - address_register <= address_register; - burstcount_register <= burstcount_register; - - if(internal_beginbursttransfer||first_burst_stalled) begin - - if(av_waitrequest) begin - first_burst_stalled <= 1'b1; - address_register <= uav_address_pre; - burstcount_register <= uav_burstcount_pre; - end else begin - first_burst_stalled <= 1'b0; - address_register <= combi_burst_addr_reg; - burstcount_register <= uav_burstcount_pre - symbols_per_word; - end - end - - else if(internal_begintransfer || burst_stalled) begin - if(~av_waitrequest) begin - burst_stalled <= 1'b0; - address_register <= combi_addr_reg; - burstcount_register <= burstcount_register - symbols_per_word; - end else - burst_stalled<=1'b1; - end - end - - end - - //Address - always @* begin - uav_address_pre = '0; - - if(AV_ADDRESS_SYMBOLS) - uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; - else begin - uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; - end - end - - //Burstcount - always@* begin - uav_burstcount_pre = symbols_per_word; // default to a single transfer - - if(USE_BURSTCOUNT) begin - uav_burstcount_pre = '0; - - if(AV_BURSTCOUNT_SYMBOLS) - uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; - else begin - uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; - end - - end - - end - - - //waitrequest translation - - always@(posedge clk, posedge reset) begin - if(reset) - read_accepted <= 1'b0; - else begin - read_accepted <= read_accepted; - - if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives - read_accepted <= 1'b0; - - if(read_accepted == 0) - read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; - end - - end - - reg write_accepted = 0; - generate if (AV_REGISTERINCOMINGSIGNALS) begin - always@(posedge clk, posedge reset) begin - if(reset) - write_accepted <= 1'b0; - else begin - write_accepted <= - ~av_waitrequest ? 1'b0 : - uav_write & ~uav_waitrequest? 1'b1 : - write_accepted; - end - end - end endgenerate - - always@* begin - av_waitrequest = uav_waitrequest; - - if(USE_READDATAVALID == 0 ) begin - av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; - end - - if (AV_REGISTERINCOMINGSIGNALS) begin - av_waitrequest = - uav_read_pre ? ~uav_readdatavalid : - uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : - 1'b1; - end - - if(USE_WAITREQUEST == 0) begin - av_waitrequest = 0; - end - end - - //read/write generation - always@* begin - - uav_write = 1'b0; - uav_write_pre = 1'b0; - uav_read = 1'b0; - uav_read_pre = 1'b0; - - if(!USE_CHIPSELECT) begin - if (USE_READ) begin - uav_read_pre=av_read; - end - - if (USE_WRITE) begin - uav_write_pre=av_write; - end - end - else begin - if(!USE_WRITE && USE_READ) begin - uav_read_pre=av_read; - uav_write_pre=av_chipselect & ~av_read; - end - else if(!USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre = av_chipselect & ~av_write; - end - else if (USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre=av_read; - end - end - - if(USE_READDATAVALID == 0) - uav_read = uav_read_pre & ~read_accepted; - else - uav_read = uav_read_pre; - - if(AV_REGISTERINCOMINGSIGNALS == 0) - uav_write=uav_write_pre; - else - uav_write=uav_write_pre & ~write_accepted; - - - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - if(USE_BEGINTRANSFER) begin - internal_begintransfer = av_begintransfer; - end else begin - internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(internal_begintransfer == 1 && uav_waitrequest) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - wire last_burst_transfer_pre; - wire last_burst_transfer_reg; - wire last_burst_transfer; - - // compare values before the mux to shorten critical path; benchmark before changing - assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); - assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); - assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; - - always@* begin - if(USE_BEGINBURSTTRANSFER) begin - internal_beginbursttransfer = av_beginbursttransfer; - end else begin - internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_beginbursttransfer <= 1'b0; - end - else begin - end_beginbursttransfer <= end_beginbursttransfer; - if( last_burst_transfer && internal_begintransfer || uav_read ) begin - end_beginbursttransfer <= 1'b0; - end - else if(uav_write && internal_begintransfer) begin - end_beginbursttransfer <= 1'b1; - end - end - - end - - // synthesis translate_off - - // ------------------------------------------------ - // check_1 : for waitrequest signal violation - // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls - // Exception : begintransfer / beginbursttransfer - // : previously not in any transaction (idle) - // Note : Not checking clken which is not exactly part of Avalon controls/inputs - // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE - // ------------------------------------------------ - - reg av_waitrequest_r; - reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; - reg [AV_ADDRESS_W-1:0] av_address_r; - reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; - reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; - reg [AV_DATA_W-1:0] av_writedata_r; - - always @(posedge clk or posedge reset) begin - if (reset) begin - av_waitrequest_r <= '0; - av_write_r <= '0; - av_writeresponserequest_r <= '0; - av_read_r <= '0; - av_lock_r <= '0; - av_chipselect_r <= '0; - av_debugaccess_r <= '0; - av_address_r <= '0; - av_byteenable_r <= '0; - av_burstcount_r <= '0; - av_writedata_r <= '0; - - end - else begin - av_waitrequest_r <= av_waitrequest; - av_write_r <= av_write; - av_writeresponserequest_r <= av_writeresponserequest; - av_read_r <= av_read; - av_lock_r <= av_lock; - av_chipselect_r <= av_chipselect; - av_debugaccess_r <= av_debugaccess; - av_address_r <= av_address; - av_byteenable_r <= av_byteenable; - av_burstcount_r <= av_burstcount; - av_writedata_r <= av_writedata; - - if ( av_waitrequest_r && // When waitrequest is asserted - ( (av_write != av_write_r) || // Checks that : Input controls/data does not change - (av_writeresponserequest != av_writeresponserequest_r) || - (av_read != av_read_r) || - (av_lock != av_lock_r) || - (av_debugaccess != av_debugaccess_r) || - (av_address != av_address_r) || - (av_byteenable != av_byteenable_r) || - (av_burstcount != av_burstcount_r) - ) && - (av_write_r | av_read_r) && // Check only when : previously initiated a write/read - (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) - ) - $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), - av_address_r , av_address, - av_byteenable_r , av_byteenable, - av_burstcount_r , av_burstcount, - av_writedata_r , av_writedata, - av_writeresponserequest_r, av_writeresponserequest, - av_write_r , av_write, - av_read_r , av_read, - av_lock_r , av_lock, - av_chipselect_r, av_chipselect, - av_debugaccess_r, av_debugaccess); - end - - // end check_1 - - end - - // synthesis translate_on - - - endmodule +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Translator +// +// Converts Avalon-MM Master Interfaces into +// Avalon-MM Universal Master Interfaces +// -------------------------------------- + +`timescale 1 ns / 1 ns + + + +module altera_merlin_master_translator #( + parameter + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + + //Optional Port Declarations + + USE_BURSTCOUNT = 1, + USE_BEGINBURSTTRANSFER = 0, + USE_BEGINTRANSFER = 0, + USE_CHIPSELECT = 0, + USE_READ = 1, + USE_READDATAVALID = 1, + USE_WRITE = 1, + USE_WAITREQUEST = 1, + USE_WRITERESPONSE = 0, + USE_READRESPONSE = 0, + + AV_REGISTERINCOMINGSIGNALS = 0, + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_CONSTANT_BURST_BEHAVIOR = 1, + AV_BURSTCOUNT_SYMBOLS = 0, + AV_LINEWRAPBURSTS = 0, + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_CONSTANT_BURST_BEHAVIOR = 0 + )( + //Universal Avalon Master + input wire clk, + input wire reset, + output reg uav_write, + output reg uav_read, + output reg [UAV_ADDRESS_W -1 : 0] uav_address, + output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, + output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, + output wire [AV_DATA_W -1 : 0] uav_writedata, + output wire uav_lock, + output wire uav_debugaccess, + output wire uav_clken, + + input wire [ AV_DATA_W -1 : 0] uav_readdata, + input wire uav_readdatavalid, + input wire uav_waitrequest, + input wire [1:0] uav_response, + output reg uav_writeresponserequest, + input wire uav_writeresponsevalid, + + //Avalon-MM !Master + input reg av_write, + input reg av_read, + input wire [AV_ADDRESS_W -1 : 0] av_address, + input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, + input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, + input wire [AV_DATA_W -1 : 0] av_writedata, + input wire av_begintransfer, + input wire av_beginbursttransfer, + input wire av_lock, + input wire av_chipselect, + input wire av_debugaccess, + input wire av_clken, + + output wire [AV_DATA_W -1 : 0] av_readdata, + output wire av_readdatavalid, + output reg av_waitrequest, + output reg [1:0] av_response, + input wire av_writeresponserequest, + output reg av_writeresponsevalid + + ); + + + localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); + localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); + localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; + + localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; + localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; + + + // -1 for burstcount restriction 2^(n-1) + + localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; + localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; + + localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; + localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; + + localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; + localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; + + function integer flog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + if ( i <= 0 ) flog2 = 0; + else begin + for(flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + + endfunction // flog2 + + function integer clog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2 = 0; i > 0; clog2 = clog2 + 1) + i = i >> 1; + end + + endfunction + + function integer pow2; + input [31:0] toShift; + begin + pow2=1; + pow2= pow2 << toShift; + end + endfunction // pow2 + + // ------------------------------------------------- + // Assign some constants to appropriately-sized signals to + // avoid synthesis warnings. This also helps some simulators + // with their inferred sensitivity lists. + // ------------------------------------------------- + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); + wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; + + + reg internal_beginbursttransfer; + reg internal_begintransfer; + reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; + reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; + + + + reg uav_read_pre; + reg uav_write_pre; + reg read_accepted; + + //Passthru assignmenst + + assign uav_writedata = av_writedata; + assign av_readdata = uav_readdata; + assign uav_byteenable = av_byteenable; + assign uav_lock = av_lock; + assign av_readdatavalid = uav_readdatavalid; + assign uav_debugaccess = av_debugaccess; + assign uav_clken = av_clken; + + //Response signals + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) + av_response = '0; + else + av_response = uav_response; + if (USE_WRITERESPONSE) begin + uav_writeresponserequest = av_writeresponserequest; + av_writeresponsevalid = uav_writeresponsevalid; + end else begin + uav_writeresponserequest = '0; + av_writeresponsevalid = '0; + end + end + + //address + burstcount assignment + + reg [UAV_ADDRESS_W - 1 : 0] address_register; + reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; + + always @* begin + uav_address=uav_address_pre; + uav_burstcount=uav_burstcount_pre; + + if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin + uav_address=address_register; + uav_burstcount=burstcount_register; + end + end + + reg first_burst_stalled; + reg burst_stalled; + + + wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; + wire [UAV_ADDRESS_W-1:0] combi_addr_reg; + generate + if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin + if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + end + else begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + end + end + else begin + assign combi_burst_addr_reg = + uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + assign combi_addr_reg = + address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + end + endgenerate + + always@(posedge clk, posedge reset) begin + + if(reset) begin + address_register <= '0; + burstcount_register <= '0; + first_burst_stalled <= 1'b0; + burst_stalled <= 1'b0; + end + else begin + address_register <= address_register; + burstcount_register <= burstcount_register; + + if(internal_beginbursttransfer||first_burst_stalled) begin + + if(av_waitrequest) begin + first_burst_stalled <= 1'b1; + address_register <= uav_address_pre; + burstcount_register <= uav_burstcount_pre; + end else begin + first_burst_stalled <= 1'b0; + address_register <= combi_burst_addr_reg; + burstcount_register <= uav_burstcount_pre - symbols_per_word; + end + end + + else if(internal_begintransfer || burst_stalled) begin + if(~av_waitrequest) begin + burst_stalled <= 1'b0; + address_register <= combi_addr_reg; + burstcount_register <= burstcount_register - symbols_per_word; + end else + burst_stalled<=1'b1; + end + end + + end + + //Address + always @* begin + uav_address_pre = '0; + + if(AV_ADDRESS_SYMBOLS) + uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; + else begin + uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; + end + end + + //Burstcount + always@* begin + uav_burstcount_pre = symbols_per_word; // default to a single transfer + + if(USE_BURSTCOUNT) begin + uav_burstcount_pre = '0; + + if(AV_BURSTCOUNT_SYMBOLS) + uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; + else begin + uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; + end + + end + + end + + + //waitrequest translation + + always@(posedge clk, posedge reset) begin + if(reset) + read_accepted <= 1'b0; + else begin + read_accepted <= read_accepted; + + if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives + read_accepted <= 1'b0; + + if(read_accepted == 0) + read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; + end + + end + + reg write_accepted = 0; + generate if (AV_REGISTERINCOMINGSIGNALS) begin + always@(posedge clk, posedge reset) begin + if(reset) + write_accepted <= 1'b0; + else begin + write_accepted <= + ~av_waitrequest ? 1'b0 : + uav_write & ~uav_waitrequest? 1'b1 : + write_accepted; + end + end + end endgenerate + + always@* begin + av_waitrequest = uav_waitrequest; + + if(USE_READDATAVALID == 0 ) begin + av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; + end + + if (AV_REGISTERINCOMINGSIGNALS) begin + av_waitrequest = + uav_read_pre ? ~uav_readdatavalid : + uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : + 1'b1; + end + + if(USE_WAITREQUEST == 0) begin + av_waitrequest = 0; + end + end + + //read/write generation + always@* begin + + uav_write = 1'b0; + uav_write_pre = 1'b0; + uav_read = 1'b0; + uav_read_pre = 1'b0; + + if(!USE_CHIPSELECT) begin + if (USE_READ) begin + uav_read_pre=av_read; + end + + if (USE_WRITE) begin + uav_write_pre=av_write; + end + end + else begin + if(!USE_WRITE && USE_READ) begin + uav_read_pre=av_read; + uav_write_pre=av_chipselect & ~av_read; + end + else if(!USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre = av_chipselect & ~av_write; + end + else if (USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre=av_read; + end + end + + if(USE_READDATAVALID == 0) + uav_read = uav_read_pre & ~read_accepted; + else + uav_read = uav_read_pre; + + if(AV_REGISTERINCOMINGSIGNALS == 0) + uav_write=uav_write_pre; + else + uav_write=uav_write_pre & ~write_accepted; + + + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + if(USE_BEGINTRANSFER) begin + internal_begintransfer = av_begintransfer; + end else begin + internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(internal_begintransfer == 1 && uav_waitrequest) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + wire last_burst_transfer_pre; + wire last_burst_transfer_reg; + wire last_burst_transfer; + + // compare values before the mux to shorten critical path; benchmark before changing + assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); + assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); + assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; + + always@* begin + if(USE_BEGINBURSTTRANSFER) begin + internal_beginbursttransfer = av_beginbursttransfer; + end else begin + internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_beginbursttransfer <= 1'b0; + end + else begin + end_beginbursttransfer <= end_beginbursttransfer; + if( last_burst_transfer && internal_begintransfer || uav_read ) begin + end_beginbursttransfer <= 1'b0; + end + else if(uav_write && internal_begintransfer) begin + end_beginbursttransfer <= 1'b1; + end + end + + end + + // synthesis translate_off + + // ------------------------------------------------ + // check_1 : for waitrequest signal violation + // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls + // Exception : begintransfer / beginbursttransfer + // : previously not in any transaction (idle) + // Note : Not checking clken which is not exactly part of Avalon controls/inputs + // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE + // ------------------------------------------------ + + reg av_waitrequest_r; + reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; + reg [AV_ADDRESS_W-1:0] av_address_r; + reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; + reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; + reg [AV_DATA_W-1:0] av_writedata_r; + + always @(posedge clk or posedge reset) begin + if (reset) begin + av_waitrequest_r <= '0; + av_write_r <= '0; + av_writeresponserequest_r <= '0; + av_read_r <= '0; + av_lock_r <= '0; + av_chipselect_r <= '0; + av_debugaccess_r <= '0; + av_address_r <= '0; + av_byteenable_r <= '0; + av_burstcount_r <= '0; + av_writedata_r <= '0; + + end + else begin + av_waitrequest_r <= av_waitrequest; + av_write_r <= av_write; + av_writeresponserequest_r <= av_writeresponserequest; + av_read_r <= av_read; + av_lock_r <= av_lock; + av_chipselect_r <= av_chipselect; + av_debugaccess_r <= av_debugaccess; + av_address_r <= av_address; + av_byteenable_r <= av_byteenable; + av_burstcount_r <= av_burstcount; + av_writedata_r <= av_writedata; + + if ( av_waitrequest_r && // When waitrequest is asserted + ( (av_write != av_write_r) || // Checks that : Input controls/data does not change + (av_writeresponserequest != av_writeresponserequest_r) || + (av_read != av_read_r) || + (av_lock != av_lock_r) || + (av_debugaccess != av_debugaccess_r) || + (av_address != av_address_r) || + (av_byteenable != av_byteenable_r) || + (av_burstcount != av_burstcount_r) + ) && + (av_write_r | av_read_r) && // Check only when : previously initiated a write/read + (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) + ) + $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), + av_address_r , av_address, + av_byteenable_r , av_byteenable, + av_burstcount_r , av_burstcount, + av_writedata_r , av_writedata, + av_writeresponserequest_r, av_writeresponserequest, + av_write_r , av_write, + av_read_r , av_read, + av_lock_r , av_lock, + av_chipselect_r, av_chipselect, + av_debugaccess_r, av_debugaccess); + end + + // end check_1 + + end + + // synthesis translate_on + + + endmodule diff --git a/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv b/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv index e7c183d..ea599eb 100644 --- a/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv +++ b/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv @@ -11,578 +11,578 @@ // agreement for further details. -// (C) 2001-2011 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_agent -#( - // Packet parameters - parameter PKT_BEGIN_BURST = 81, - parameter PKT_DATA_H = 31, - parameter PKT_DATA_L = 0, - parameter PKT_SYMBOL_W = 8, - parameter PKT_BYTEEN_H = 71, - parameter PKT_BYTEEN_L = 68, - parameter PKT_ADDR_H = 63, - parameter PKT_ADDR_L = 32, - parameter PKT_TRANS_LOCK = 87, - parameter PKT_TRANS_COMPRESSED_READ = 67, - parameter PKT_TRANS_POSTED = 66, - parameter PKT_TRANS_WRITE = 65, - parameter PKT_TRANS_READ = 64, - parameter PKT_SRC_ID_H = 74, - parameter PKT_SRC_ID_L = 72, - parameter PKT_DEST_ID_H = 77, - parameter PKT_DEST_ID_L = 75, - parameter PKT_BURSTWRAP_H = 85, - parameter PKT_BURSTWRAP_L = 82, - parameter PKT_BYTE_CNT_H = 81, - parameter PKT_BYTE_CNT_L = 78, - parameter PKT_PROTECTION_H = 86, - parameter PKT_PROTECTION_L = 86, - parameter PKT_RESPONSE_STATUS_H = 89, - parameter PKT_RESPONSE_STATUS_L = 88, - parameter PKT_BURST_SIZE_H = 92, - parameter PKT_BURST_SIZE_L = 90, - parameter ST_DATA_W = 93, - parameter ST_CHANNEL_W = 32, - - // Slave parameters - parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - parameter AVS_BURSTCOUNT_W = 4, - parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, - - // Slave agent parameters - parameter PREVENT_FIFO_OVERFLOW = 0, - parameter SUPPRESS_0_BYTEEN_CMD = 1, - parameter USE_READRESPONSE = 0, - parameter USE_WRITERESPONSE = 0, - - // Derived slave parameters - parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - parameter BURST_SIZE_W = 3, - - // Derived FIFO width - parameter FIFO_DATA_W = ST_DATA_W + 1 -) -( - - input clk, - input reset, - - // Universal-Avalon anti-slave - output [ADDR_W-1:0] m0_address, - output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, - output [AVS_BE_W-1:0] m0_byteenable, - output m0_read, - input [AVS_DATA_W-1:0] m0_readdata, - input m0_waitrequest, - output m0_write, - output [AVS_DATA_W-1:0] m0_writedata, - input m0_readdatavalid, - output m0_debugaccess, - output m0_lock, - input [1:0] m0_response, - output m0_writeresponserequest, - input m0_writeresponsevalid, - - // Avalon-ST FIFO interfaces. - // Note: there's no need to include the "data" field here, at least for - // reads, since readdata is filled in from slave info. To keep life - // simple, have a data field, but fill it with 0s. - // Av-st response fifo source interface - output reg [FIFO_DATA_W-1:0] rf_source_data, - output rf_source_valid, - output rf_source_startofpacket, - output rf_source_endofpacket, - input rf_source_ready, - - // Av-st response fifo sink interface - input [FIFO_DATA_W-1:0] rf_sink_data, - input rf_sink_valid, - input rf_sink_startofpacket, - input rf_sink_endofpacket, - output rf_sink_ready, - - // Av-st readdata fifo src interface, data and response - // extra 2 bits for storing RESPONSE STATUS - output [AVS_DATA_W+1:0] rdata_fifo_src_data, - output rdata_fifo_src_valid, - input rdata_fifo_src_ready, - - // Av-st readdata fifo sink interface - input [AVS_DATA_W+1:0] rdata_fifo_sink_data, - input rdata_fifo_sink_valid, - output rdata_fifo_sink_ready, - - // Av-st sink command packet interface - output cp_ready, - input cp_valid, - input [ST_DATA_W-1:0] cp_data, - input [ST_CHANNEL_W-1:0] cp_channel, - input cp_startofpacket, - input cp_endofpacket, - - // Av-st source response packet interface - input rp_ready, - output reg rp_valid, - output reg [ST_DATA_W-1:0] rp_data, - output rp_startofpacket, - output rp_endofpacket -); - - // -------------------------------------------------- - // Ceil(log2()) function log2ceil of 4 = 2 - // -------------------------------------------------- - function integer log2ceil; - input reg[63:0] val; - reg [63:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - - // ------------------------------------------------ - // Local Parameters - // ------------------------------------------------ - localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; - localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; - localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; - localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; - localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; - localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; - localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; - localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); - - // ------------------------------------------------ - // Signals - // ------------------------------------------------ - wire [DATA_W-1:0] cmd_data; - wire [BE_W-1:0] cmd_byteen; - wire [ADDR_W-1:0] cmd_addr; - wire [MID_W-1:0] cmd_mid; - wire [SID_W-1:0] cmd_sid; - wire cmd_read; - wire cmd_write; - wire cmd_compressed; - wire cmd_posted; - wire [BYTE_CNT_W-1:0] cmd_byte_cnt; - wire [BURSTWRAP_W-1:0] cmd_burstwrap; - wire [BURSTSIZE_W-1:0] cmd_burstsize; - wire cmd_debugaccess; - - wire byteen_asserted; - wire needs_response_synthesis; - wire generate_response; - - // Assign command fields - assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; - assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; - assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; - assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; - assign cmd_posted = cp_data[PKT_TRANS_POSTED]; - assign cmd_write = cp_data[PKT_TRANS_WRITE]; - assign cmd_read = cp_data[PKT_TRANS_READ]; - assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; - assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; - assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; - - // Local "ready_for_command" signal: deasserted when the agent is unable to accept - // another command, e.g. rdv FIFO is full, (local readdata storage is full && - // ~rp_ready), ... - // Say, this could depend on the type of command, for example, even if the - // rdv FIFO is full, a write request can be accepted. For later. - wire ready_for_command; - - wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; - wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; - wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; - wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; - wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - generate - if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow - // --------------------------------------------------- - // Backpressure if the slave says to, or if FIFO overflow may occur. - // - // All commands are backpressured once the FIFO is full - // even if they don't need storage. This breaks a long - // combinatorial path from the master read/write through - // this logic and back to the master via the backpressure - // path. - // - // To avoid a loss of throughput the FIFO will be parameterized - // one slot deeper. The extra slot should never be used in normal - // operation, but should a slave misbehave and accept one more - // read than it should then backpressure will kick in. - // - // An example: assume a slave with MPRT = 2. It can accept a - // command sequence RRWW without backpressuring. If the FIFO is - // only 2 deep, we'd backpressure the writes leading to loss of - // throughput. If the FIFO is 3 deep, we'll only backpressure when - // RRR... which is an illegal condition anyway. - // --------------------------------------------------- - - assign ready_for_command = rf_source_ready; - assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; - - end else begin : no_prevent_fifo_overflow - - // Do not suppress the command or the slave will - // not be able to waitrequest - assign ready_for_command = 1'b1; - // Backpressure only if the slave says to. - assign cp_ready = ~m0_waitrequest | ~byteen_asserted; - - end - endgenerate - - generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd - assign byteen_asserted = |cmd_byteen; - end else begin : no_suppress_0_byteen_cmd - assign byteen_asserted = 1'b1; - end - endgenerate - - // ------------------------------------------------------------------- - // Extract avalon signals from command packet. - // ------------------------------------------------------------------- - // Mask off the lower bits of address. - // The burst adapter before this component will break narrow sized packets - // into sub-bursts of length 1. However, the packet addresses are preserved, - // which means this component may see size-aligned addresses. - // - // Masking ensures that the addresses seen by an Avalon slave are aligned to - // the full data width instead of the size. - // - // Example: - // output from burst adapter (datawidth=4, size=2 bytes): - // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 - // expected output from slave agent: - // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 - generate - if (BITS_TO_MASK > 0) begin : mask_address - - assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; - - end else begin : no_mask_address - - assign m0_address = cmd_addr; - - end - endgenerate - - assign m0_byteenable = cmd_byteen; - assign m0_writedata = cmd_data; - - // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - - // this sort of burst exists only in merlin fabric ST packets. What to do - // if we see such a burst? All beats in that burst need to be transmitted - // to the slave so we have enough space-time for byteenable expression. - // - // There can be multiple bursts in a packet, but only one beat per burst - // in cases. The exception is when we've decided not to insert a - // burst adapter for efficiency reasons, in which case this agent is also - // responsible for driving burstcount to 1 on each beat of an uncompressed - // read burst. - - assign m0_read = ready_for_command & byteen_asserted & - (local_compressed_read | local_read); - - generate - begin : m0_burstcount_zero_pad - // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount - // from a sub-range, or 0-pad, as appropriate. - if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin - wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = - {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; - assign m0_burstcount = (local_read & ~local_compressed_read) ? - {zero_pad, num_symbols} : - {zero_pad, cmd_byte_cnt}; - end - else begin : m0_burstcount_no_pad - assign m0_burstcount = (local_read & ~local_compressed_read) ? - num_symbols[AVS_BURSTCOUNT_W-1:0] : - cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; - end - end - endgenerate - - assign m0_write = ready_for_command & local_write & byteen_asserted; - assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); - assign m0_debugaccess = cmd_debugaccess; - // For now, to support write response - assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; - //assign m0_writeresponserequest = '0; - - // ------------------------------------------------------------------- - // Indirection layer for response packet values. Some may always wire - // directly from the slave translator; others will no doubt emerge from - // various FIFOs. - // What to put in resp_data when a write occured? Answer: it does not - // matter, because only response status is needed for non-posted writes, - // and the packet already has a field for that. - - // tgngo:Use the rdata_fifo to store write response as well - // So that we wont lost response if master can back-pressured - // as well as it needs for write response merging - assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; - //assign rdata_fifo_src_valid = m0_readdatavalid; - assign rdata_fifo_src_data = {m0_response,m0_readdata}; - - // ------------------------------------------------------------------ - // Generate a token when read commands are suppressed. The token - // is stored in the response FIFO, and will be used to synthesize - // a read response. The same token is used for non-posted write - // response synthesis. - // - // Note: this token is not generated for suppressed uncompressed read cycles; - // the burst uncompression logic at the read side of the response FIFO - // generates the correct number of responses. - // ------------------------------------------------------------------ - // When the slave can return the response, let it does its works. Dont generate sysnthesis response - assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); - - // Avalon-ST interfaces to external response fifo: - // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write - // To support response from slave, we need to store each sub-burst of write command into fifo. - // Each sub-burst will return a response and these two command and response are popped out together - // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write - // the slave agent will send out the final merged response - - wire internal_cp_endofburst; - wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning - wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; - assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; - assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); - wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; - wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; - - assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) - & ready_for_command & cp_ready; - assign rf_source_startofpacket = cp_startofpacket; - assign rf_source_endofpacket = cp_endofpacket; - always @* begin - // default: assign every command packet field to the response FIFO... - rf_source_data = {1'b0, cp_data}; - - // ... and override select fields as needed. - rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; - rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; - rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; - rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; - //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; - rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; - rf_source_data[PKT_TRANS_POSTED] = cmd_posted; - rf_source_data[PKT_TRANS_WRITE] = cmd_write; - rf_source_data[PKT_TRANS_READ] = cmd_read; - rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; - rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; - rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; - rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; - rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; - rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; - rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; - end - - wire uncompressor_source_valid; - wire [BURSTSIZE_W-1:0] uncompressor_burstsize; - - //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) - // at this time, the final response merged will send out, and rp_valid is only asserted - // for one response for whole burst - generate - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; - always @* begin - if (rf_sink_data[PKT_TRANS_WRITE] == 1) - rp_valid = rdata_fifo_sink_valid & last_write_response; - else - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end else begin - always @* begin - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end - endgenerate - // ------------------------------------------------------------------ - // Response merging - // ------------------------------------------------------------------ - wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; - reg [1:0] response_merged; - generate - begin: response_merging - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - reg first_write_response; - reg reset_merged_output; - reg [1:0] previous_response_in; - reg [1:0] previous_response; - - always_ff @(posedge clk, posedge reset) begin - if (reset) begin - first_write_response <= 1'b1; - end - else begin // Merging work for write response, for read: previous_response_in = current_response - if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin - first_write_response <= 1'b0; - if (rf_sink_endofpacket) - first_write_response <= 1'b1; - end - end - end - - always_comb begin - reset_merged_output = first_write_response && rdata_fifo_sink_valid; - previous_response_in = reset_merged_output ? current_response : previous_response; - response_merged = current_response >= previous_response ? current_response: previous_response_in; - end - - always_ff @(posedge clk or posedge reset) begin - if (reset) begin - previous_response <= 2'b00; - end - else begin - if (rf_sink_valid & rdata_fifo_sink_valid) begin - previous_response <= response_merged; - end - end - end - end else begin - always @* begin - response_merged = current_response; - end - end - end - endgenerate - - assign generate_response = rf_sink_data[FIFO_DATA_W-1]; - - wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; - // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo - wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; - - wire [BYTE_CNT_W-1:0] burst_byte_cnt; - wire [BURSTWRAP_W-1:0] rp_burstwrap; - wire [ADDR_W-1:0] rp_address; - wire rp_is_compressed; - - // ------------------------------------------------------------------ - // Backpressure the readdata fifo if we're supposed to synthesize a response. - // This may be a read response (for suppressed reads) or a write response - // (for non-posted writes). - // ------------------------------------------------------------------ - assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); - - always @* begin - // By default, return all fields... - rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; - - // ... and override specific fields. - rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; - // Assignments directly from the response fifo. - rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; - rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; - rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; - rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; - rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; - - // Burst uncompressor assignments - rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; - rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; - rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; - rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; - - // avalon slaves always respond with "okay" -> not true for now - //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; - rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; - rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; - end - - // ------------------------------------------------------------------ - // Note: the burst uncompressor may be asked to generate responses for - // write packets; these are treated the same as single-cycle uncompressed - // reads. - // ------------------------------------------------------------------ - altera_merlin_burst_uncompressor #( - .ADDR_W (ADDR_W), - .BURSTWRAP_W (BURSTWRAP_W), - .BYTE_CNT_W (BYTE_CNT_W), - .PKT_SYMBOLS (PKT_SYMBOLS) - ) uncompressor - ( - .clk (clk), - .reset (reset), - .sink_startofpacket (rf_sink_startofpacket_wire), - .sink_endofpacket (rf_sink_endofpacket), - .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), - .sink_ready (rf_sink_ready), - .sink_addr (rf_sink_addr), - .sink_burstwrap (rf_sink_burstwrap), - .sink_byte_cnt (rf_sink_byte_cnt), - .sink_is_compressed (rf_sink_compressed), - .sink_burstsize (rf_sink_burstsize), - - .source_startofpacket (rp_startofpacket), - .source_endofpacket (rp_endofpacket), - .source_valid (uncompressor_source_valid), - .source_ready (rp_ready), - .source_addr (rp_address), - .source_burstwrap (rp_burstwrap), - .source_byte_cnt (burst_byte_cnt), - .source_is_compressed (rp_is_compressed), - .source_burstsize (uncompressor_burstsize) - ); - -//-------------------------------------- -// Assertion: In case slave support response. Yhe slave needs return response in order -// Ex: non-posted write followed by a read: write response must complete before read data -//-------------------------------------- -// synthesis translate_off -ERROR_write_response_and_read_response_cannot_happen_same_time: - assert property ( @(posedge clk) - disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) - ); - -// synthesis translate_on -endmodule - +// (C) 2001-2011 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_agent +#( + // Packet parameters + parameter PKT_BEGIN_BURST = 81, + parameter PKT_DATA_H = 31, + parameter PKT_DATA_L = 0, + parameter PKT_SYMBOL_W = 8, + parameter PKT_BYTEEN_H = 71, + parameter PKT_BYTEEN_L = 68, + parameter PKT_ADDR_H = 63, + parameter PKT_ADDR_L = 32, + parameter PKT_TRANS_LOCK = 87, + parameter PKT_TRANS_COMPRESSED_READ = 67, + parameter PKT_TRANS_POSTED = 66, + parameter PKT_TRANS_WRITE = 65, + parameter PKT_TRANS_READ = 64, + parameter PKT_SRC_ID_H = 74, + parameter PKT_SRC_ID_L = 72, + parameter PKT_DEST_ID_H = 77, + parameter PKT_DEST_ID_L = 75, + parameter PKT_BURSTWRAP_H = 85, + parameter PKT_BURSTWRAP_L = 82, + parameter PKT_BYTE_CNT_H = 81, + parameter PKT_BYTE_CNT_L = 78, + parameter PKT_PROTECTION_H = 86, + parameter PKT_PROTECTION_L = 86, + parameter PKT_RESPONSE_STATUS_H = 89, + parameter PKT_RESPONSE_STATUS_L = 88, + parameter PKT_BURST_SIZE_H = 92, + parameter PKT_BURST_SIZE_L = 90, + parameter ST_DATA_W = 93, + parameter ST_CHANNEL_W = 32, + + // Slave parameters + parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + parameter AVS_BURSTCOUNT_W = 4, + parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, + + // Slave agent parameters + parameter PREVENT_FIFO_OVERFLOW = 0, + parameter SUPPRESS_0_BYTEEN_CMD = 1, + parameter USE_READRESPONSE = 0, + parameter USE_WRITERESPONSE = 0, + + // Derived slave parameters + parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + parameter BURST_SIZE_W = 3, + + // Derived FIFO width + parameter FIFO_DATA_W = ST_DATA_W + 1 +) +( + + input clk, + input reset, + + // Universal-Avalon anti-slave + output [ADDR_W-1:0] m0_address, + output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, + output [AVS_BE_W-1:0] m0_byteenable, + output m0_read, + input [AVS_DATA_W-1:0] m0_readdata, + input m0_waitrequest, + output m0_write, + output [AVS_DATA_W-1:0] m0_writedata, + input m0_readdatavalid, + output m0_debugaccess, + output m0_lock, + input [1:0] m0_response, + output m0_writeresponserequest, + input m0_writeresponsevalid, + + // Avalon-ST FIFO interfaces. + // Note: there's no need to include the "data" field here, at least for + // reads, since readdata is filled in from slave info. To keep life + // simple, have a data field, but fill it with 0s. + // Av-st response fifo source interface + output reg [FIFO_DATA_W-1:0] rf_source_data, + output rf_source_valid, + output rf_source_startofpacket, + output rf_source_endofpacket, + input rf_source_ready, + + // Av-st response fifo sink interface + input [FIFO_DATA_W-1:0] rf_sink_data, + input rf_sink_valid, + input rf_sink_startofpacket, + input rf_sink_endofpacket, + output rf_sink_ready, + + // Av-st readdata fifo src interface, data and response + // extra 2 bits for storing RESPONSE STATUS + output [AVS_DATA_W+1:0] rdata_fifo_src_data, + output rdata_fifo_src_valid, + input rdata_fifo_src_ready, + + // Av-st readdata fifo sink interface + input [AVS_DATA_W+1:0] rdata_fifo_sink_data, + input rdata_fifo_sink_valid, + output rdata_fifo_sink_ready, + + // Av-st sink command packet interface + output cp_ready, + input cp_valid, + input [ST_DATA_W-1:0] cp_data, + input [ST_CHANNEL_W-1:0] cp_channel, + input cp_startofpacket, + input cp_endofpacket, + + // Av-st source response packet interface + input rp_ready, + output reg rp_valid, + output reg [ST_DATA_W-1:0] rp_data, + output rp_startofpacket, + output rp_endofpacket +); + + // -------------------------------------------------- + // Ceil(log2()) function log2ceil of 4 = 2 + // -------------------------------------------------- + function integer log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + // ------------------------------------------------ + // Local Parameters + // ------------------------------------------------ + localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; + localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; + localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; + localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; + localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); + + // ------------------------------------------------ + // Signals + // ------------------------------------------------ + wire [DATA_W-1:0] cmd_data; + wire [BE_W-1:0] cmd_byteen; + wire [ADDR_W-1:0] cmd_addr; + wire [MID_W-1:0] cmd_mid; + wire [SID_W-1:0] cmd_sid; + wire cmd_read; + wire cmd_write; + wire cmd_compressed; + wire cmd_posted; + wire [BYTE_CNT_W-1:0] cmd_byte_cnt; + wire [BURSTWRAP_W-1:0] cmd_burstwrap; + wire [BURSTSIZE_W-1:0] cmd_burstsize; + wire cmd_debugaccess; + + wire byteen_asserted; + wire needs_response_synthesis; + wire generate_response; + + // Assign command fields + assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; + assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; + assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; + assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; + assign cmd_posted = cp_data[PKT_TRANS_POSTED]; + assign cmd_write = cp_data[PKT_TRANS_WRITE]; + assign cmd_read = cp_data[PKT_TRANS_READ]; + assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; + assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; + + // Local "ready_for_command" signal: deasserted when the agent is unable to accept + // another command, e.g. rdv FIFO is full, (local readdata storage is full && + // ~rp_ready), ... + // Say, this could depend on the type of command, for example, even if the + // rdv FIFO is full, a write request can be accepted. For later. + wire ready_for_command; + + wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; + wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; + wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; + wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; + wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + generate + if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow + // --------------------------------------------------- + // Backpressure if the slave says to, or if FIFO overflow may occur. + // + // All commands are backpressured once the FIFO is full + // even if they don't need storage. This breaks a long + // combinatorial path from the master read/write through + // this logic and back to the master via the backpressure + // path. + // + // To avoid a loss of throughput the FIFO will be parameterized + // one slot deeper. The extra slot should never be used in normal + // operation, but should a slave misbehave and accept one more + // read than it should then backpressure will kick in. + // + // An example: assume a slave with MPRT = 2. It can accept a + // command sequence RRWW without backpressuring. If the FIFO is + // only 2 deep, we'd backpressure the writes leading to loss of + // throughput. If the FIFO is 3 deep, we'll only backpressure when + // RRR... which is an illegal condition anyway. + // --------------------------------------------------- + + assign ready_for_command = rf_source_ready; + assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; + + end else begin : no_prevent_fifo_overflow + + // Do not suppress the command or the slave will + // not be able to waitrequest + assign ready_for_command = 1'b1; + // Backpressure only if the slave says to. + assign cp_ready = ~m0_waitrequest | ~byteen_asserted; + + end + endgenerate + + generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd + assign byteen_asserted = |cmd_byteen; + end else begin : no_suppress_0_byteen_cmd + assign byteen_asserted = 1'b1; + end + endgenerate + + // ------------------------------------------------------------------- + // Extract avalon signals from command packet. + // ------------------------------------------------------------------- + // Mask off the lower bits of address. + // The burst adapter before this component will break narrow sized packets + // into sub-bursts of length 1. However, the packet addresses are preserved, + // which means this component may see size-aligned addresses. + // + // Masking ensures that the addresses seen by an Avalon slave are aligned to + // the full data width instead of the size. + // + // Example: + // output from burst adapter (datawidth=4, size=2 bytes): + // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 + // expected output from slave agent: + // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 + generate + if (BITS_TO_MASK > 0) begin : mask_address + + assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; + + end else begin : no_mask_address + + assign m0_address = cmd_addr; + + end + endgenerate + + assign m0_byteenable = cmd_byteen; + assign m0_writedata = cmd_data; + + // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - + // this sort of burst exists only in merlin fabric ST packets. What to do + // if we see such a burst? All beats in that burst need to be transmitted + // to the slave so we have enough space-time for byteenable expression. + // + // There can be multiple bursts in a packet, but only one beat per burst + // in cases. The exception is when we've decided not to insert a + // burst adapter for efficiency reasons, in which case this agent is also + // responsible for driving burstcount to 1 on each beat of an uncompressed + // read burst. + + assign m0_read = ready_for_command & byteen_asserted & + (local_compressed_read | local_read); + + generate + begin : m0_burstcount_zero_pad + // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount + // from a sub-range, or 0-pad, as appropriate. + if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin + wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = + {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; + assign m0_burstcount = (local_read & ~local_compressed_read) ? + {zero_pad, num_symbols} : + {zero_pad, cmd_byte_cnt}; + end + else begin : m0_burstcount_no_pad + assign m0_burstcount = (local_read & ~local_compressed_read) ? + num_symbols[AVS_BURSTCOUNT_W-1:0] : + cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; + end + end + endgenerate + + assign m0_write = ready_for_command & local_write & byteen_asserted; + assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); + assign m0_debugaccess = cmd_debugaccess; + // For now, to support write response + assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; + //assign m0_writeresponserequest = '0; + + // ------------------------------------------------------------------- + // Indirection layer for response packet values. Some may always wire + // directly from the slave translator; others will no doubt emerge from + // various FIFOs. + // What to put in resp_data when a write occured? Answer: it does not + // matter, because only response status is needed for non-posted writes, + // and the packet already has a field for that. + + // tgngo:Use the rdata_fifo to store write response as well + // So that we wont lost response if master can back-pressured + // as well as it needs for write response merging + assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; + //assign rdata_fifo_src_valid = m0_readdatavalid; + assign rdata_fifo_src_data = {m0_response,m0_readdata}; + + // ------------------------------------------------------------------ + // Generate a token when read commands are suppressed. The token + // is stored in the response FIFO, and will be used to synthesize + // a read response. The same token is used for non-posted write + // response synthesis. + // + // Note: this token is not generated for suppressed uncompressed read cycles; + // the burst uncompression logic at the read side of the response FIFO + // generates the correct number of responses. + // ------------------------------------------------------------------ + // When the slave can return the response, let it does its works. Dont generate sysnthesis response + assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); + + // Avalon-ST interfaces to external response fifo: + // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write + // To support response from slave, we need to store each sub-burst of write command into fifo. + // Each sub-burst will return a response and these two command and response are popped out together + // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write + // the slave agent will send out the final merged response + + wire internal_cp_endofburst; + wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning + wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; + assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; + assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); + wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; + wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; + + assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) + & ready_for_command & cp_ready; + assign rf_source_startofpacket = cp_startofpacket; + assign rf_source_endofpacket = cp_endofpacket; + always @* begin + // default: assign every command packet field to the response FIFO... + rf_source_data = {1'b0, cp_data}; + + // ... and override select fields as needed. + rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; + rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; + rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; + rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; + //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; + rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; + rf_source_data[PKT_TRANS_POSTED] = cmd_posted; + rf_source_data[PKT_TRANS_WRITE] = cmd_write; + rf_source_data[PKT_TRANS_READ] = cmd_read; + rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; + rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; + rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; + rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; + rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; + rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; + rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; + end + + wire uncompressor_source_valid; + wire [BURSTSIZE_W-1:0] uncompressor_burstsize; + + //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) + // at this time, the final response merged will send out, and rp_valid is only asserted + // for one response for whole burst + generate + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; + always @* begin + if (rf_sink_data[PKT_TRANS_WRITE] == 1) + rp_valid = rdata_fifo_sink_valid & last_write_response; + else + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end else begin + always @* begin + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end + endgenerate + // ------------------------------------------------------------------ + // Response merging + // ------------------------------------------------------------------ + wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; + reg [1:0] response_merged; + generate + begin: response_merging + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + reg first_write_response; + reg reset_merged_output; + reg [1:0] previous_response_in; + reg [1:0] previous_response; + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + first_write_response <= 1'b1; + end + else begin // Merging work for write response, for read: previous_response_in = current_response + if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin + first_write_response <= 1'b0; + if (rf_sink_endofpacket) + first_write_response <= 1'b1; + end + end + end + + always_comb begin + reset_merged_output = first_write_response && rdata_fifo_sink_valid; + previous_response_in = reset_merged_output ? current_response : previous_response; + response_merged = current_response >= previous_response ? current_response: previous_response_in; + end + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + previous_response <= 2'b00; + end + else begin + if (rf_sink_valid & rdata_fifo_sink_valid) begin + previous_response <= response_merged; + end + end + end + end else begin + always @* begin + response_merged = current_response; + end + end + end + endgenerate + + assign generate_response = rf_sink_data[FIFO_DATA_W-1]; + + wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; + // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo + wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; + + wire [BYTE_CNT_W-1:0] burst_byte_cnt; + wire [BURSTWRAP_W-1:0] rp_burstwrap; + wire [ADDR_W-1:0] rp_address; + wire rp_is_compressed; + + // ------------------------------------------------------------------ + // Backpressure the readdata fifo if we're supposed to synthesize a response. + // This may be a read response (for suppressed reads) or a write response + // (for non-posted writes). + // ------------------------------------------------------------------ + assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); + + always @* begin + // By default, return all fields... + rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; + + // ... and override specific fields. + rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; + // Assignments directly from the response fifo. + rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; + rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; + rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; + rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; + + // Burst uncompressor assignments + rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; + rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; + rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; + rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; + + // avalon slaves always respond with "okay" -> not true for now + //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; + rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; + rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; + end + + // ------------------------------------------------------------------ + // Note: the burst uncompressor may be asked to generate responses for + // write packets; these are treated the same as single-cycle uncompressed + // reads. + // ------------------------------------------------------------------ + altera_merlin_burst_uncompressor #( + .ADDR_W (ADDR_W), + .BURSTWRAP_W (BURSTWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (PKT_SYMBOLS) + ) uncompressor + ( + .clk (clk), + .reset (reset), + .sink_startofpacket (rf_sink_startofpacket_wire), + .sink_endofpacket (rf_sink_endofpacket), + .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), + .sink_ready (rf_sink_ready), + .sink_addr (rf_sink_addr), + .sink_burstwrap (rf_sink_burstwrap), + .sink_byte_cnt (rf_sink_byte_cnt), + .sink_is_compressed (rf_sink_compressed), + .sink_burstsize (rf_sink_burstsize), + + .source_startofpacket (rp_startofpacket), + .source_endofpacket (rp_endofpacket), + .source_valid (uncompressor_source_valid), + .source_ready (rp_ready), + .source_addr (rp_address), + .source_burstwrap (rp_burstwrap), + .source_byte_cnt (burst_byte_cnt), + .source_is_compressed (rp_is_compressed), + .source_burstsize (uncompressor_burstsize) + ); + +//-------------------------------------- +// Assertion: In case slave support response. Yhe slave needs return response in order +// Ex: non-posted write followed by a read: write response must complete before read data +//-------------------------------------- +// synthesis translate_off +ERROR_write_response_and_read_response_cannot_happen_same_time: + assert property ( @(posedge clk) + disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) + ); + +// synthesis translate_on +endmodule + diff --git a/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv b/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv index d5bd6e9..bcb2311 100644 --- a/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv +++ b/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv @@ -11,523 +11,523 @@ // agreement for further details. - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Slave Translator -// -// Translates Universal Avalon MM Slave -// to any Avalon MM Slave -// ------------------------------------- -// -//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one -//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero -//The key feature here is that no same cycle turnaround data is processed through the fabric. - -//import avalon_utilities_pkg::*; - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_translator - #( - parameter - //Widths - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - UAV_BYTEENABLE_W = 4, - - //Read Latency - AV_READLATENCY = 1, - - //Timing - AV_READ_WAIT_CYCLES = 0, - AV_WRITE_WAIT_CYCLES = 0, - AV_SETUP_WAIT_CYCLES = 0, - AV_DATA_HOLD_CYCLES = 0, - - //Optional Port Declarations - USE_READDATAVALID = 1, - USE_WAITREQUEST = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - //Variable Addressing - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_BURSTCOUNT_SYMBOLS = 0, - BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_DATA_W = 32, - - AV_CONSTANT_BURST_BEHAVIOR = 0, - UAV_CONSTANT_BURST_BEHAVIOR = 0, - CHIPSELECT_THROUGH_READLATENCY = 0, - - // Tightly-Coupled Options - USE_UAV_CLKEN = 0, - AV_REQUIRE_UNALIGNED_ADDRESSES = 0 - ) - ( - - // ------------------- - // Clock & Reset - // ------------------- - input wire clk, - input wire reset, - - // ------------------- - // Universal Avalon Slave - // ------------------- - - input wire [UAV_ADDRESS_W - 1 : 0] uav_address, - input wire [UAV_DATA_W - 1 : 0] uav_writedata, - input wire uav_write, - input wire uav_read, - input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, - input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, - input wire uav_lock, - input wire uav_debugaccess, - input wire uav_clken, - - output logic uav_readdatavalid, - output logic uav_waitrequest, - output logic [UAV_DATA_W - 1 : 0] uav_readdata, - output logic [1:0] uav_response, - input wire uav_writeresponserequest, - output logic uav_writeresponsevalid, - - // ------------------- - // Customizable Avalon Master - // ------------------- - output logic [AV_ADDRESS_W - 1 : 0] av_address, - output logic [AV_DATA_W - 1 : 0] av_writedata, - output logic av_write, - output logic av_read, - output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, - output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, - output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, - output logic av_begintransfer, - output wire av_chipselect, - output logic av_beginbursttransfer, - output logic av_lock, - output wire av_clken, - output wire av_debugaccess, - output wire av_outputenable, - - input logic [AV_DATA_W - 1 : 0] av_readdata, - input logic av_readdatavalid, - input logic av_waitrequest, - - input logic [1:0] av_response, - output logic av_writeresponserequest, - input wire av_writeresponsevalid - - ); - - function integer clog2_plusone; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) - i = i >> 1; - end - - endfunction - - function integer max; - //returns the larger of two passed arguments - input [31:0] one; - input [31:0] two; - - if(one > two) - max=one; - else - max=two; - endfunction // int - - localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); - localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); - localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); - localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); - localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; - localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; - - localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? - AV_ADDRESS_W : - UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; - - localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? - AV_BURSTCOUNT_W : - UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; - localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; - - - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); - wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; - - // +-------------------------------- - // |Backwards Compatibility Signals - // +-------------------------------- - assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; - assign av_debugaccess = uav_debugaccess; - - // +------------------- - // |Passthru Signals - // +------------------- - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin - uav_response = '0; - end else begin - uav_response = av_response; - end - end - assign av_writeresponserequest = uav_writeresponserequest; - assign uav_writeresponsevalid = av_writeresponsevalid; - - //------------------------- - //Writedata and Byteenable - //------------------------- - - always@* begin - av_byteenable = '0; - av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; - end - - always@* begin - av_writedata = '0; - av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; - end - - // +------------------- - // |Calculated Signals - // +------------------- - - logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; - - function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; - input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; - - for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin - if(byteenable[i] == 1) begin - return i; - end - end - - return '0; - - endfunction - - reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; - reg [AV_ADDRESS_W - 1 : 0] address_reg; - - - always@(posedge clk, posedge reset) begin - if(reset) begin - burstcount_reg <= '0; - address_reg <= '0; - end - else begin - burstcount_reg <= burstcount_reg; - address_reg <= address_reg; - - if(av_beginbursttransfer) begin - burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - end - end - end - - - logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; - - always@* begin - if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin - temp_wire = decode_byteenable(uav_byteenable); - - real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; - end - else begin - real_uav_address = uav_address; - end - - av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_address = address_reg; - end - - always@* begin - av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_burstcount = burstcount_reg; - end - - always@* begin - av_lock = uav_lock; - end - - // ------------------- - // Writebyteenable Assignment - // ------------------- - -always@* begin - av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; -end - - // ------------------- - // Waitrequest Assignment - // ------------------- - - reg av_waitrequest_generated; - reg av_waitrequest_generated_read; - reg av_waitrequest_generated_write; - reg waitrequest_reset_override; - - reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; - - always@(posedge reset, posedge clk) begin - - if(reset) begin - wait_latency_counter <= '0; - waitrequest_reset_override <= 1'h1; - end - else begin - waitrequest_reset_override <= 1'h0; - - wait_latency_counter <= '0; - - if( uav_read | uav_write ) - wait_latency_counter <= wait_latency_counter + 1'h1; - - if( ~uav_waitrequest | waitrequest_reset_override ) - wait_latency_counter <= '0; - - end - - end - - - always @* begin - - av_read = uav_read; - av_write = uav_write; - - av_waitrequest_generated = 1'h1; - av_waitrequest_generated_read = 1'h1; - av_waitrequest_generated_write = 1'h1; - - if(LOG2_OF_LATENCY_SUM == 1) - av_waitrequest_generated = 0; - - if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin - av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; - av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; - - av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; - av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; - - if(uav_write) - av_waitrequest_generated = av_waitrequest_generated_write; - else - av_waitrequest_generated = av_waitrequest_generated_read; - - end - - if(USE_WAITREQUEST) begin - uav_waitrequest = av_waitrequest; - end - else begin - uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; - end - - end - - // -------------- - // Readdata Assignment - // -------------- - - reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; - - always@(posedge clk, posedge reset) begin - if(reset) - av_readdata_pre <= 'b0; - else - av_readdata_pre <= av_readdata; - end - - always@* begin - uav_readdata = '0; - - if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin - uav_readdata = av_readdata; - end - else begin - uav_readdata = av_readdata_pre; - end - end - // ------------------- - // Readdatavalid Assigment - // ------------------- - - reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; - reg top_read_latency_shift_reg; - - - - always@* begin - - uav_readdatavalid=top_read_latency_shift_reg; - - if(USE_READDATAVALID) begin - uav_readdatavalid = av_readdatavalid; - end - - end - - always@* begin - - top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; - - if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin - top_read_latency_shift_reg=read_latency_shift_reg; - end - - if (AV_READLATENCY > 1) begin - top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; - end - - end - - always@(posedge reset, posedge clk) begin - - if (reset) begin - read_latency_shift_reg <= '0; - end - else if (av_clken) begin - - read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; - - for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin - read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; - end - - end - - end - - // ------------ - // Chipselect and OutputEnable - // ------------ - - reg av_chipselect_pre; - wire cs_extension; - reg av_outputenable_pre; - - - assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; - assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); - - assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; - - always@(posedge reset, posedge clk) begin - if(reset) - av_outputenable_pre <= 1'b0; - else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) - av_outputenable_pre <= 0; - else - av_outputenable_pre <= cs_extension | uav_read; - end - - always@(posedge reset, posedge clk) begin - if(reset) begin - av_chipselect_pre <= 1'b0; - end - else begin - av_chipselect_pre <= 1'b0; - - if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin - //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. - //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. - if(uav_read) begin - av_chipselect_pre <= 1'b1; - end - else if(cs_extension == 1) begin - av_chipselect_pre <= 1'b1; - end - - end - end - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - reg in_transfer; - - - - always@* begin - av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); - end - - always@ ( posedge clk or posedge reset ) begin - if(reset) begin - end_beginbursttransfer <= 1'b0; - in_transfer <= 1'b0; - end - else begin - - end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); - - if(uav_write && uav_burstcount == symbols_per_word) - in_transfer <=1'b0; - else if(uav_write) - in_transfer <=1'b1; - - end - - end - -endmodule + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Slave Translator +// +// Translates Universal Avalon MM Slave +// to any Avalon MM Slave +// ------------------------------------- +// +//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one +//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero +//The key feature here is that no same cycle turnaround data is processed through the fabric. + +//import avalon_utilities_pkg::*; + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_translator + #( + parameter + //Widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + UAV_BYTEENABLE_W = 4, + + //Read Latency + AV_READLATENCY = 1, + + //Timing + AV_READ_WAIT_CYCLES = 0, + AV_WRITE_WAIT_CYCLES = 0, + AV_SETUP_WAIT_CYCLES = 0, + AV_DATA_HOLD_CYCLES = 0, + + //Optional Port Declarations + USE_READDATAVALID = 1, + USE_WAITREQUEST = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + //Variable Addressing + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_DATA_W = 32, + + AV_CONSTANT_BURST_BEHAVIOR = 0, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + CHIPSELECT_THROUGH_READLATENCY = 0, + + // Tightly-Coupled Options + USE_UAV_CLKEN = 0, + AV_REQUIRE_UNALIGNED_ADDRESSES = 0 + ) + ( + + // ------------------- + // Clock & Reset + // ------------------- + input wire clk, + input wire reset, + + // ------------------- + // Universal Avalon Slave + // ------------------- + + input wire [UAV_ADDRESS_W - 1 : 0] uav_address, + input wire [UAV_DATA_W - 1 : 0] uav_writedata, + input wire uav_write, + input wire uav_read, + input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, + input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, + input wire uav_lock, + input wire uav_debugaccess, + input wire uav_clken, + + output logic uav_readdatavalid, + output logic uav_waitrequest, + output logic [UAV_DATA_W - 1 : 0] uav_readdata, + output logic [1:0] uav_response, + input wire uav_writeresponserequest, + output logic uav_writeresponsevalid, + + // ------------------- + // Customizable Avalon Master + // ------------------- + output logic [AV_ADDRESS_W - 1 : 0] av_address, + output logic [AV_DATA_W - 1 : 0] av_writedata, + output logic av_write, + output logic av_read, + output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, + output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, + output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, + output logic av_begintransfer, + output wire av_chipselect, + output logic av_beginbursttransfer, + output logic av_lock, + output wire av_clken, + output wire av_debugaccess, + output wire av_outputenable, + + input logic [AV_DATA_W - 1 : 0] av_readdata, + input logic av_readdatavalid, + input logic av_waitrequest, + + input logic [1:0] av_response, + output logic av_writeresponserequest, + input wire av_writeresponsevalid + + ); + + function integer clog2_plusone; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) + i = i >> 1; + end + + endfunction + + function integer max; + //returns the larger of two passed arguments + input [31:0] one; + input [31:0] two; + + if(one > two) + max=one; + else + max=two; + endfunction // int + + localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); + localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); + localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); + localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); + localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; + + localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? + AV_ADDRESS_W : + UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; + + localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? + AV_BURSTCOUNT_W : + UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; + localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; + + + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); + wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; + + // +-------------------------------- + // |Backwards Compatibility Signals + // +-------------------------------- + assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; + assign av_debugaccess = uav_debugaccess; + + // +------------------- + // |Passthru Signals + // +------------------- + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin + uav_response = '0; + end else begin + uav_response = av_response; + end + end + assign av_writeresponserequest = uav_writeresponserequest; + assign uav_writeresponsevalid = av_writeresponsevalid; + + //------------------------- + //Writedata and Byteenable + //------------------------- + + always@* begin + av_byteenable = '0; + av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + always@* begin + av_writedata = '0; + av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; + end + + // +------------------- + // |Calculated Signals + // +------------------- + + logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; + + function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; + input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; + + for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin + if(byteenable[i] == 1) begin + return i; + end + end + + return '0; + + endfunction + + reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; + reg [AV_ADDRESS_W - 1 : 0] address_reg; + + + always@(posedge clk, posedge reset) begin + if(reset) begin + burstcount_reg <= '0; + address_reg <= '0; + end + else begin + burstcount_reg <= burstcount_reg; + address_reg <= address_reg; + + if(av_beginbursttransfer) begin + burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + end + end + end + + + logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; + + always@* begin + if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin + temp_wire = decode_byteenable(uav_byteenable); + + real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; + end + else begin + real_uav_address = uav_address; + end + + av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_address = address_reg; + end + + always@* begin + av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_burstcount = burstcount_reg; + end + + always@* begin + av_lock = uav_lock; + end + + // ------------------- + // Writebyteenable Assignment + // ------------------- + +always@* begin + av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; +end + + // ------------------- + // Waitrequest Assignment + // ------------------- + + reg av_waitrequest_generated; + reg av_waitrequest_generated_read; + reg av_waitrequest_generated_write; + reg waitrequest_reset_override; + + reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; + + always@(posedge reset, posedge clk) begin + + if(reset) begin + wait_latency_counter <= '0; + waitrequest_reset_override <= 1'h1; + end + else begin + waitrequest_reset_override <= 1'h0; + + wait_latency_counter <= '0; + + if( uav_read | uav_write ) + wait_latency_counter <= wait_latency_counter + 1'h1; + + if( ~uav_waitrequest | waitrequest_reset_override ) + wait_latency_counter <= '0; + + end + + end + + + always @* begin + + av_read = uav_read; + av_write = uav_write; + + av_waitrequest_generated = 1'h1; + av_waitrequest_generated_read = 1'h1; + av_waitrequest_generated_write = 1'h1; + + if(LOG2_OF_LATENCY_SUM == 1) + av_waitrequest_generated = 0; + + if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin + av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; + av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; + + av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; + av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; + + if(uav_write) + av_waitrequest_generated = av_waitrequest_generated_write; + else + av_waitrequest_generated = av_waitrequest_generated_read; + + end + + if(USE_WAITREQUEST) begin + uav_waitrequest = av_waitrequest; + end + else begin + uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; + end + + end + + // -------------- + // Readdata Assignment + // -------------- + + reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; + + always@(posedge clk, posedge reset) begin + if(reset) + av_readdata_pre <= 'b0; + else + av_readdata_pre <= av_readdata; + end + + always@* begin + uav_readdata = '0; + + if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin + uav_readdata = av_readdata; + end + else begin + uav_readdata = av_readdata_pre; + end + end + // ------------------- + // Readdatavalid Assigment + // ------------------- + + reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; + reg top_read_latency_shift_reg; + + + + always@* begin + + uav_readdatavalid=top_read_latency_shift_reg; + + if(USE_READDATAVALID) begin + uav_readdatavalid = av_readdatavalid; + end + + end + + always@* begin + + top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; + + if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin + top_read_latency_shift_reg=read_latency_shift_reg; + end + + if (AV_READLATENCY > 1) begin + top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; + end + + end + + always@(posedge reset, posedge clk) begin + + if (reset) begin + read_latency_shift_reg <= '0; + end + else if (av_clken) begin + + read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; + + for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin + read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; + end + + end + + end + + // ------------ + // Chipselect and OutputEnable + // ------------ + + reg av_chipselect_pre; + wire cs_extension; + reg av_outputenable_pre; + + + assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; + assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); + + assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; + + always@(posedge reset, posedge clk) begin + if(reset) + av_outputenable_pre <= 1'b0; + else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) + av_outputenable_pre <= 0; + else + av_outputenable_pre <= cs_extension | uav_read; + end + + always@(posedge reset, posedge clk) begin + if(reset) begin + av_chipselect_pre <= 1'b0; + end + else begin + av_chipselect_pre <= 1'b0; + + if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin + //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. + //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. + if(uav_read) begin + av_chipselect_pre <= 1'b1; + end + else if(cs_extension == 1) begin + av_chipselect_pre <= 1'b1; + end + + end + end + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + reg in_transfer; + + + + always@* begin + av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_beginbursttransfer <= 1'b0; + in_transfer <= 1'b0; + end + else begin + + end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); + + if(uav_write && uav_burstcount == symbols_per_word) + in_transfer <=1'b0; + else if(uav_write) + in_transfer <=1'b1; + + end + + end + +endmodule diff --git a/db/ip/nios_system/submodules/altera_reset_controller.sdc b/db/ip/nios_system/submodules/altera_reset_controller.sdc index 28476af..d58dd05 100644 --- a/db/ip/nios_system/submodules/altera_reset_controller.sdc +++ b/db/ip/nios_system/submodules/altera_reset_controller.sdc @@ -11,23 +11,23 @@ # agreement for further details. -# +--------------------------------------------------- -# | Cut the async clear paths -# +--------------------------------------------------- -set aclr_counter 0 -set clrn_counter 0 -set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -foreach_in_collection aclr_pin $aclr_collection { - set aclr_counter [expr $aclr_counter + 1] -} -foreach_in_collection clrn_pin $clrn_collection { - set clrn_counter [expr $clrn_counter + 1] -} -if {$aclr_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -} - -if {$clrn_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -} +# +--------------------------------------------------- +# | Cut the async clear paths +# +--------------------------------------------------- +set aclr_counter 0 +set clrn_counter 0 +set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +foreach_in_collection aclr_pin $aclr_collection { + set aclr_counter [expr $aclr_counter + 1] +} +foreach_in_collection clrn_pin $clrn_collection { + set clrn_counter [expr $clrn_counter + 1] +} +if {$aclr_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +} + +if {$clrn_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +} diff --git a/db/ip/nios_system/submodules/altera_reset_controller.v b/db/ip/nios_system/submodules/altera_reset_controller.v index 05dd901..7c250c7 100644 --- a/db/ip/nios_system/submodules/altera_reset_controller.v +++ b/db/ip/nios_system/submodules/altera_reset_controller.v @@ -11,196 +11,196 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ -// $Revision: #2 $ -// $Date: 2013/06/03 $ -// $Author: wkleong $ - -// -------------------------------------- -// Reset controller -// -// Combines all the input resets and synchronizes -// the result to the clk. -// ACDS13.1 - Added reset request as part of reset sequencing -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_reset_controller -#( - parameter NUM_RESET_INPUTS = 6, - parameter OUTPUT_RESET_SYNC_EDGES = "deassert", - parameter SYNC_DEPTH = 2, - parameter RESET_REQUEST_PRESENT = 0 -) -( - // -------------------------------------- - // We support up to 16 reset inputs, for now - // -------------------------------------- - input reset_in0, - input reset_in1, - input reset_in2, - input reset_in3, - input reset_in4, - input reset_in5, - input reset_in6, - input reset_in7, - input reset_in8, - input reset_in9, - input reset_in10, - input reset_in11, - input reset_in12, - input reset_in13, - input reset_in14, - input reset_in15, - - input clk, - output reg reset_out, - output reg reset_req -); - - localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); - - localparam DEPTH = 2; - localparam CLKEN_LAGS_RESET = 0; - localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; - - wire merged_reset; - wire reset_out_pre; - - // Registers and Interconnect - (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; - reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; - reg r_sync_rst_dly; - reg r_sync_rst; - reg r_early_rst; - - // -------------------------------------- - // "Or" all the input resets together - // -------------------------------------- - assign merged_reset = ( - reset_in0 | - reset_in1 | - reset_in2 | - reset_in3 | - reset_in4 | - reset_in5 | - reset_in6 | - reset_in7 | - reset_in8 | - reset_in9 | - reset_in10 | - reset_in11 | - reset_in12 | - reset_in13 | - reset_in14 | - reset_in15 - ); - - // -------------------------------------- - // And if required, synchronize it to the required clock domain, - // with the correct synchronization type - // -------------------------------------- - generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin - - assign reset_out_pre = merged_reset; - - end else begin - - altera_reset_synchronizer - #( - .DEPTH (SYNC_DEPTH), - .ASYNC_RESET(ASYNC_RESET) - ) - alt_rst_sync_uq1 - ( - .clk (clk), - .reset_in (merged_reset), - .reset_out (reset_out_pre) - ); - - end - endgenerate - - generate if (RESET_REQUEST_PRESENT == 0) begin - always @* begin - reset_out = reset_out_pre; - reset_req = 1'b0; - end - end - else begin - - // 3-FF Metastability Synchronizer - initial - begin - altera_reset_synchronizer_int_chain <= 3'b111; - end - - always @(posedge clk) - begin - altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; - end - - - // Synchronous reset pipe - initial - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - - always @(posedge clk) - begin - if (altera_reset_synchronizer_int_chain[2] == 1'b1) - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - else - begin - r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; - end - end - - // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition - // matches the early input. - initial - begin - r_sync_rst_dly <= 1'b1; - r_sync_rst <= 1'b1; - r_early_rst <= 1'b1; - end - - always @(posedge clk) - begin - // Delayed reset pipeline register - r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; - - case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) - 3'b000: r_sync_rst <= 1'b0; // Not reset - 3'b001: r_sync_rst <= 1'b0; - 3'b010: r_sync_rst <= 1'b0; - 3'b011: r_sync_rst <= 1'b1; - 3'b100: r_sync_rst <= 1'b1; - 3'b101: r_sync_rst <= 1'b1; - 3'b110: r_sync_rst <= 1'b1; - 3'b111: r_sync_rst <= 1'b1; // In Reset - default: r_sync_rst <= 1'b1; - endcase - - case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) - 2'b00: r_early_rst <= 1'b0; // Not reset - 2'b01: r_early_rst <= 1'b1; // Coming out of reset - 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. - 2'b11: r_early_rst <= 1'b1; // Held in reset - default: r_early_rst <= 1'b1; - endcase - end - - always @* begin - reset_out = r_sync_rst; - reset_req = r_early_rst; - end - - end - endgenerate - -endmodule +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ +// $Revision: #2 $ +// $Date: 2013/06/03 $ +// $Author: wkleong $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// ACDS13.1 - Added reset request as part of reset sequencing +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2, + parameter RESET_REQUEST_PRESENT = 0 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + + input clk, + output reg reset_out, + output reg reset_req +); + + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + localparam DEPTH = 2; + localparam CLKEN_LAGS_RESET = 0; + localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; + + wire merged_reset; + wire reset_out_pre; + + // Registers and Interconnect + (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; + reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; + reg r_sync_rst_dly; + reg r_sync_rst; + reg r_early_rst; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin + + assign reset_out_pre = merged_reset; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out_pre) + ); + + end + endgenerate + + generate if (RESET_REQUEST_PRESENT == 0) begin + always @* begin + reset_out = reset_out_pre; + reset_req = 1'b0; + end + end + else begin + + // 3-FF Metastability Synchronizer + initial + begin + altera_reset_synchronizer_int_chain <= 3'b111; + end + + always @(posedge clk) + begin + altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; + end + + + // Synchronous reset pipe + initial + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + + always @(posedge clk) + begin + if (altera_reset_synchronizer_int_chain[2] == 1'b1) + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; + end + end + + // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition + // matches the early input. + initial + begin + r_sync_rst_dly <= 1'b1; + r_sync_rst <= 1'b1; + r_early_rst <= 1'b1; + end + + always @(posedge clk) + begin + // Delayed reset pipeline register + r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; + + case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; // Not reset + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; // In Reset + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) + 2'b00: r_early_rst <= 1'b0; // Not reset + 2'b01: r_early_rst <= 1'b1; // Coming out of reset + 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. + 2'b11: r_early_rst <= 1'b1; // Held in reset + default: r_early_rst <= 1'b1; + endcase + end + + always @* begin + reset_out = r_sync_rst; + reset_req = r_early_rst; + end + + end + endgenerate + +endmodule diff --git a/db/ip/nios_system/submodules/altera_reset_synchronizer.v b/db/ip/nios_system/submodules/altera_reset_synchronizer.v index 5e24fe7..14936c3 100644 --- a/db/ip/nios_system/submodules/altera_reset_synchronizer.v +++ b/db/ip/nios_system/submodules/altera_reset_synchronizer.v @@ -11,77 +11,77 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ----------------------------------------------- -// Reset Synchronizer -// ----------------------------------------------- -`timescale 1 ns / 1 ns - -module altera_reset_synchronizer -#( - parameter ASYNC_RESET = 1, - parameter DEPTH = 2 -) -( - input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, - - input clk, - output reset_out -); - - // ----------------------------------------------- - // Synchronizer register chain. We cannot reuse the - // standard synchronizer in this implementation - // because our timing constraints are different. - // - // Instead of cutting the timing path to the d-input - // on the first flop we need to cut the aclr input. - // - // We omit the "preserve" attribute on the final - // output register, so that the synthesis tool can - // duplicate it where needed. - // ----------------------------------------------- - (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; - reg altera_reset_synchronizer_int_chain_out; - - generate if (ASYNC_RESET) begin - - // ----------------------------------------------- - // Assert asynchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk or posedge reset_in) begin - if (reset_in) begin - altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; - altera_reset_synchronizer_int_chain_out <= 1'b1; - end - else begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end else begin - - // ----------------------------------------------- - // Assert synchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk) begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end - endgenerate - -endmodule - +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_LEDRs.v b/db/ip/nios_system/submodules/nios_system_LEDRs.v index 142f077..63ed909 100644 --- a/db/ip/nios_system/submodules/nios_system_LEDRs.v +++ b/db/ip/nios_system/submodules/nios_system_LEDRs.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDRs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 17: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 17: 0] data_out; - wire [ 17: 0] out_port; - wire [ 17: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[17 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDRs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 17: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 17: 0] data_out; + wire [ 17: 0] out_port; + wire [ 17: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[17 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_LEDs.v b/db/ip/nios_system/submodules/nios_system_LEDs.v index 6c38eeb..4e22fe4 100644 --- a/db/ip/nios_system/submodules/nios_system_LEDs.v +++ b/db/ip/nios_system/submodules/nios_system_LEDs.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 7: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 7: 0] data_out; - wire [ 7: 0] out_port; - wire [ 7: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {8 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[7 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 7: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 7: 0] data_out; + wire [ 7: 0] out_port; + wire [ 7: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {8 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[7 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_addr_router.sv b/db/ip/nios_system/submodules/nios_system_addr_router.sv index 005a859..3c8760e 100644 --- a/db/ip/nios_system/submodules/nios_system_addr_router.sv +++ b/db/ip/nios_system/submodules/nios_system_addr_router.sv @@ -1,224 +1,224 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41000; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b10; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b01; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41000; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b10; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b01; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_addr_router_001.sv b/db/ip/nios_system/submodules/nios_system_addr_router_001.sv index 73a4ee3..7b8c2d0 100644 --- a/db/ip/nios_system/submodules/nios_system_addr_router_001.sv +++ b/db/ip/nios_system/submodules/nios_system_addr_router_001.sv @@ -1,336 +1,336 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_001_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router_001 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - localparam PAD2 = log2ceil(64'h41020 - 64'h41010); - localparam PAD3 = log2ceil(64'h41030 - 64'h41020); - localparam PAD4 = log2ceil(64'h41040 - 64'h41030); - localparam PAD5 = log2ceil(64'h41050 - 64'h41040); - localparam PAD6 = log2ceil(64'h41060 - 64'h41050); - localparam PAD7 = log2ceil(64'h41070 - 64'h41060); - localparam PAD8 = log2ceil(64'h41080 - 64'h41070); - localparam PAD9 = log2ceil(64'h41090 - 64'h41080); - localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); - localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); - localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); - localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); - localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); - localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); - localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); - localparam PAD17 = log2ceil(64'h41108 - 64'h41100); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41108; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_001_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b000000000000000010; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b000000000000000001; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - - // ( 0x41010 .. 0x41020 ) - if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin - src_channel = 18'b010000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; - end - - // ( 0x41020 .. 0x41030 ) - if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin - src_channel = 18'b100000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; - end - - // ( 0x41030 .. 0x41040 ) - if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin - src_channel = 18'b001000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; - end - - // ( 0x41040 .. 0x41050 ) - if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin - src_channel = 18'b000100000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; - end - - // ( 0x41050 .. 0x41060 ) - if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin - src_channel = 18'b000010000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; - end - - // ( 0x41060 .. 0x41070 ) - if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin - src_channel = 18'b000001000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; - end - - // ( 0x41070 .. 0x41080 ) - if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin - src_channel = 18'b000000100000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; - end - - // ( 0x41080 .. 0x41090 ) - if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin - src_channel = 18'b000000010000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; - end - - // ( 0x41090 .. 0x410a0 ) - if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin - src_channel = 18'b000000001000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; - end - - // ( 0x410a0 .. 0x410b0 ) - if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin - src_channel = 18'b000000000100000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; - end - - // ( 0x410b0 .. 0x410c0 ) - if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin - src_channel = 18'b000000000010000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; - end - - // ( 0x410c0 .. 0x410d0 ) - if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin - src_channel = 18'b000000000001000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; - end - - // ( 0x410d0 .. 0x410e0 ) - if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin - src_channel = 18'b000000000000100000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; - end - - // ( 0x410e0 .. 0x410f0 ) - if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin - src_channel = 18'b000000000000010000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; - end - - // ( 0x410f0 .. 0x41100 ) - if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin - src_channel = 18'b000000000000000100; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; - end - - // ( 0x41100 .. 0x41108 ) - if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin - src_channel = 18'b000000000000001000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + localparam PAD2 = log2ceil(64'h41020 - 64'h41010); + localparam PAD3 = log2ceil(64'h41030 - 64'h41020); + localparam PAD4 = log2ceil(64'h41040 - 64'h41030); + localparam PAD5 = log2ceil(64'h41050 - 64'h41040); + localparam PAD6 = log2ceil(64'h41060 - 64'h41050); + localparam PAD7 = log2ceil(64'h41070 - 64'h41060); + localparam PAD8 = log2ceil(64'h41080 - 64'h41070); + localparam PAD9 = log2ceil(64'h41090 - 64'h41080); + localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); + localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); + localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); + localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); + localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); + localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); + localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); + localparam PAD17 = log2ceil(64'h41108 - 64'h41100); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41108; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_001_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b000000000000000010; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b000000000000000001; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + + // ( 0x41010 .. 0x41020 ) + if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin + src_channel = 18'b010000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; + end + + // ( 0x41020 .. 0x41030 ) + if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin + src_channel = 18'b100000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; + end + + // ( 0x41030 .. 0x41040 ) + if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin + src_channel = 18'b001000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; + end + + // ( 0x41040 .. 0x41050 ) + if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin + src_channel = 18'b000100000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; + end + + // ( 0x41050 .. 0x41060 ) + if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin + src_channel = 18'b000010000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; + end + + // ( 0x41060 .. 0x41070 ) + if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin + src_channel = 18'b000001000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; + end + + // ( 0x41070 .. 0x41080 ) + if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin + src_channel = 18'b000000100000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; + end + + // ( 0x41080 .. 0x41090 ) + if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin + src_channel = 18'b000000010000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; + end + + // ( 0x41090 .. 0x410a0 ) + if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin + src_channel = 18'b000000001000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; + end + + // ( 0x410a0 .. 0x410b0 ) + if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin + src_channel = 18'b000000000100000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; + end + + // ( 0x410b0 .. 0x410c0 ) + if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin + src_channel = 18'b000000000010000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; + end + + // ( 0x410c0 .. 0x410d0 ) + if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin + src_channel = 18'b000000000001000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; + end + + // ( 0x410d0 .. 0x410e0 ) + if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin + src_channel = 18'b000000000000100000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; + end + + // ( 0x410e0 .. 0x410f0 ) + if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin + src_channel = 18'b000000000000010000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + + // ( 0x410f0 .. 0x41100 ) + if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin + src_channel = 18'b000000000000000100; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x41100 .. 0x41108 ) + if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin + src_channel = 18'b000000000000001000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv index d833b2f..0aef300 100644 --- a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv +++ b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv @@ -1,116 +1,116 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv index 61d921c..433e8d0 100644 --- a/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv +++ b/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv @@ -1,356 +1,356 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux_001 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 18 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux_001 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - output reg src2_valid, - output reg [96-1 : 0] src2_data, // ST_DATA_W=96 - output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 - output reg src2_startofpacket, - output reg src2_endofpacket, - input src2_ready, - - output reg src3_valid, - output reg [96-1 : 0] src3_data, // ST_DATA_W=96 - output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 - output reg src3_startofpacket, - output reg src3_endofpacket, - input src3_ready, - - output reg src4_valid, - output reg [96-1 : 0] src4_data, // ST_DATA_W=96 - output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 - output reg src4_startofpacket, - output reg src4_endofpacket, - input src4_ready, - - output reg src5_valid, - output reg [96-1 : 0] src5_data, // ST_DATA_W=96 - output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 - output reg src5_startofpacket, - output reg src5_endofpacket, - input src5_ready, - - output reg src6_valid, - output reg [96-1 : 0] src6_data, // ST_DATA_W=96 - output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 - output reg src6_startofpacket, - output reg src6_endofpacket, - input src6_ready, - - output reg src7_valid, - output reg [96-1 : 0] src7_data, // ST_DATA_W=96 - output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 - output reg src7_startofpacket, - output reg src7_endofpacket, - input src7_ready, - - output reg src8_valid, - output reg [96-1 : 0] src8_data, // ST_DATA_W=96 - output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 - output reg src8_startofpacket, - output reg src8_endofpacket, - input src8_ready, - - output reg src9_valid, - output reg [96-1 : 0] src9_data, // ST_DATA_W=96 - output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 - output reg src9_startofpacket, - output reg src9_endofpacket, - input src9_ready, - - output reg src10_valid, - output reg [96-1 : 0] src10_data, // ST_DATA_W=96 - output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 - output reg src10_startofpacket, - output reg src10_endofpacket, - input src10_ready, - - output reg src11_valid, - output reg [96-1 : 0] src11_data, // ST_DATA_W=96 - output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 - output reg src11_startofpacket, - output reg src11_endofpacket, - input src11_ready, - - output reg src12_valid, - output reg [96-1 : 0] src12_data, // ST_DATA_W=96 - output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 - output reg src12_startofpacket, - output reg src12_endofpacket, - input src12_ready, - - output reg src13_valid, - output reg [96-1 : 0] src13_data, // ST_DATA_W=96 - output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 - output reg src13_startofpacket, - output reg src13_endofpacket, - input src13_ready, - - output reg src14_valid, - output reg [96-1 : 0] src14_data, // ST_DATA_W=96 - output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 - output reg src14_startofpacket, - output reg src14_endofpacket, - input src14_ready, - - output reg src15_valid, - output reg [96-1 : 0] src15_data, // ST_DATA_W=96 - output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 - output reg src15_startofpacket, - output reg src15_endofpacket, - input src15_ready, - - output reg src16_valid, - output reg [96-1 : 0] src16_data, // ST_DATA_W=96 - output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 - output reg src16_startofpacket, - output reg src16_endofpacket, - input src16_ready, - - output reg src17_valid, - output reg [96-1 : 0] src17_data, // ST_DATA_W=96 - output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 - output reg src17_startofpacket, - output reg src17_endofpacket, - input src17_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 18; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - src2_data = sink_data; - src2_startofpacket = sink_startofpacket; - src2_endofpacket = sink_endofpacket; - src2_channel = sink_channel >> NUM_OUTPUTS; - - src2_valid = sink_channel[2] && sink_valid; - - src3_data = sink_data; - src3_startofpacket = sink_startofpacket; - src3_endofpacket = sink_endofpacket; - src3_channel = sink_channel >> NUM_OUTPUTS; - - src3_valid = sink_channel[3] && sink_valid; - - src4_data = sink_data; - src4_startofpacket = sink_startofpacket; - src4_endofpacket = sink_endofpacket; - src4_channel = sink_channel >> NUM_OUTPUTS; - - src4_valid = sink_channel[4] && sink_valid; - - src5_data = sink_data; - src5_startofpacket = sink_startofpacket; - src5_endofpacket = sink_endofpacket; - src5_channel = sink_channel >> NUM_OUTPUTS; - - src5_valid = sink_channel[5] && sink_valid; - - src6_data = sink_data; - src6_startofpacket = sink_startofpacket; - src6_endofpacket = sink_endofpacket; - src6_channel = sink_channel >> NUM_OUTPUTS; - - src6_valid = sink_channel[6] && sink_valid; - - src7_data = sink_data; - src7_startofpacket = sink_startofpacket; - src7_endofpacket = sink_endofpacket; - src7_channel = sink_channel >> NUM_OUTPUTS; - - src7_valid = sink_channel[7] && sink_valid; - - src8_data = sink_data; - src8_startofpacket = sink_startofpacket; - src8_endofpacket = sink_endofpacket; - src8_channel = sink_channel >> NUM_OUTPUTS; - - src8_valid = sink_channel[8] && sink_valid; - - src9_data = sink_data; - src9_startofpacket = sink_startofpacket; - src9_endofpacket = sink_endofpacket; - src9_channel = sink_channel >> NUM_OUTPUTS; - - src9_valid = sink_channel[9] && sink_valid; - - src10_data = sink_data; - src10_startofpacket = sink_startofpacket; - src10_endofpacket = sink_endofpacket; - src10_channel = sink_channel >> NUM_OUTPUTS; - - src10_valid = sink_channel[10] && sink_valid; - - src11_data = sink_data; - src11_startofpacket = sink_startofpacket; - src11_endofpacket = sink_endofpacket; - src11_channel = sink_channel >> NUM_OUTPUTS; - - src11_valid = sink_channel[11] && sink_valid; - - src12_data = sink_data; - src12_startofpacket = sink_startofpacket; - src12_endofpacket = sink_endofpacket; - src12_channel = sink_channel >> NUM_OUTPUTS; - - src12_valid = sink_channel[12] && sink_valid; - - src13_data = sink_data; - src13_startofpacket = sink_startofpacket; - src13_endofpacket = sink_endofpacket; - src13_channel = sink_channel >> NUM_OUTPUTS; - - src13_valid = sink_channel[13] && sink_valid; - - src14_data = sink_data; - src14_startofpacket = sink_startofpacket; - src14_endofpacket = sink_endofpacket; - src14_channel = sink_channel >> NUM_OUTPUTS; - - src14_valid = sink_channel[14] && sink_valid; - - src15_data = sink_data; - src15_startofpacket = sink_startofpacket; - src15_endofpacket = sink_endofpacket; - src15_channel = sink_channel >> NUM_OUTPUTS; - - src15_valid = sink_channel[15] && sink_valid; - - src16_data = sink_data; - src16_startofpacket = sink_startofpacket; - src16_endofpacket = sink_endofpacket; - src16_channel = sink_channel >> NUM_OUTPUTS; - - src16_valid = sink_channel[16] && sink_valid; - - src17_data = sink_data; - src17_startofpacket = sink_startofpacket; - src17_endofpacket = sink_endofpacket; - src17_channel = sink_channel >> NUM_OUTPUTS; - - src17_valid = sink_channel[17] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - assign ready_vector[2] = src2_ready; - assign ready_vector[3] = src3_ready; - assign ready_vector[4] = src4_ready; - assign ready_vector[5] = src5_ready; - assign ready_vector[6] = src6_ready; - assign ready_vector[7] = src7_ready; - assign ready_vector[8] = src8_ready; - assign ready_vector[9] = src9_ready; - assign ready_vector[10] = src10_ready; - assign ready_vector[11] = src11_ready; - assign ready_vector[12] = src12_ready; - assign ready_vector[13] = src13_ready; - assign ready_vector[14] = src14_ready; - assign ready_vector[15] = src15_ready; - assign ready_vector[16] = src16_ready; - assign ready_vector[17] = src17_ready; - - assign sink_ready = |(sink_channel & ready_vector); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux_001 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 18 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux_001 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + output reg src2_valid, + output reg [96-1 : 0] src2_data, // ST_DATA_W=96 + output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 + output reg src2_startofpacket, + output reg src2_endofpacket, + input src2_ready, + + output reg src3_valid, + output reg [96-1 : 0] src3_data, // ST_DATA_W=96 + output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 + output reg src3_startofpacket, + output reg src3_endofpacket, + input src3_ready, + + output reg src4_valid, + output reg [96-1 : 0] src4_data, // ST_DATA_W=96 + output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 + output reg src4_startofpacket, + output reg src4_endofpacket, + input src4_ready, + + output reg src5_valid, + output reg [96-1 : 0] src5_data, // ST_DATA_W=96 + output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 + output reg src5_startofpacket, + output reg src5_endofpacket, + input src5_ready, + + output reg src6_valid, + output reg [96-1 : 0] src6_data, // ST_DATA_W=96 + output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 + output reg src6_startofpacket, + output reg src6_endofpacket, + input src6_ready, + + output reg src7_valid, + output reg [96-1 : 0] src7_data, // ST_DATA_W=96 + output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 + output reg src7_startofpacket, + output reg src7_endofpacket, + input src7_ready, + + output reg src8_valid, + output reg [96-1 : 0] src8_data, // ST_DATA_W=96 + output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 + output reg src8_startofpacket, + output reg src8_endofpacket, + input src8_ready, + + output reg src9_valid, + output reg [96-1 : 0] src9_data, // ST_DATA_W=96 + output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 + output reg src9_startofpacket, + output reg src9_endofpacket, + input src9_ready, + + output reg src10_valid, + output reg [96-1 : 0] src10_data, // ST_DATA_W=96 + output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 + output reg src10_startofpacket, + output reg src10_endofpacket, + input src10_ready, + + output reg src11_valid, + output reg [96-1 : 0] src11_data, // ST_DATA_W=96 + output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 + output reg src11_startofpacket, + output reg src11_endofpacket, + input src11_ready, + + output reg src12_valid, + output reg [96-1 : 0] src12_data, // ST_DATA_W=96 + output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 + output reg src12_startofpacket, + output reg src12_endofpacket, + input src12_ready, + + output reg src13_valid, + output reg [96-1 : 0] src13_data, // ST_DATA_W=96 + output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 + output reg src13_startofpacket, + output reg src13_endofpacket, + input src13_ready, + + output reg src14_valid, + output reg [96-1 : 0] src14_data, // ST_DATA_W=96 + output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 + output reg src14_startofpacket, + output reg src14_endofpacket, + input src14_ready, + + output reg src15_valid, + output reg [96-1 : 0] src15_data, // ST_DATA_W=96 + output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 + output reg src15_startofpacket, + output reg src15_endofpacket, + input src15_ready, + + output reg src16_valid, + output reg [96-1 : 0] src16_data, // ST_DATA_W=96 + output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 + output reg src16_startofpacket, + output reg src16_endofpacket, + input src16_ready, + + output reg src17_valid, + output reg [96-1 : 0] src17_data, // ST_DATA_W=96 + output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 + output reg src17_startofpacket, + output reg src17_endofpacket, + input src17_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 18; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + src2_data = sink_data; + src2_startofpacket = sink_startofpacket; + src2_endofpacket = sink_endofpacket; + src2_channel = sink_channel >> NUM_OUTPUTS; + + src2_valid = sink_channel[2] && sink_valid; + + src3_data = sink_data; + src3_startofpacket = sink_startofpacket; + src3_endofpacket = sink_endofpacket; + src3_channel = sink_channel >> NUM_OUTPUTS; + + src3_valid = sink_channel[3] && sink_valid; + + src4_data = sink_data; + src4_startofpacket = sink_startofpacket; + src4_endofpacket = sink_endofpacket; + src4_channel = sink_channel >> NUM_OUTPUTS; + + src4_valid = sink_channel[4] && sink_valid; + + src5_data = sink_data; + src5_startofpacket = sink_startofpacket; + src5_endofpacket = sink_endofpacket; + src5_channel = sink_channel >> NUM_OUTPUTS; + + src5_valid = sink_channel[5] && sink_valid; + + src6_data = sink_data; + src6_startofpacket = sink_startofpacket; + src6_endofpacket = sink_endofpacket; + src6_channel = sink_channel >> NUM_OUTPUTS; + + src6_valid = sink_channel[6] && sink_valid; + + src7_data = sink_data; + src7_startofpacket = sink_startofpacket; + src7_endofpacket = sink_endofpacket; + src7_channel = sink_channel >> NUM_OUTPUTS; + + src7_valid = sink_channel[7] && sink_valid; + + src8_data = sink_data; + src8_startofpacket = sink_startofpacket; + src8_endofpacket = sink_endofpacket; + src8_channel = sink_channel >> NUM_OUTPUTS; + + src8_valid = sink_channel[8] && sink_valid; + + src9_data = sink_data; + src9_startofpacket = sink_startofpacket; + src9_endofpacket = sink_endofpacket; + src9_channel = sink_channel >> NUM_OUTPUTS; + + src9_valid = sink_channel[9] && sink_valid; + + src10_data = sink_data; + src10_startofpacket = sink_startofpacket; + src10_endofpacket = sink_endofpacket; + src10_channel = sink_channel >> NUM_OUTPUTS; + + src10_valid = sink_channel[10] && sink_valid; + + src11_data = sink_data; + src11_startofpacket = sink_startofpacket; + src11_endofpacket = sink_endofpacket; + src11_channel = sink_channel >> NUM_OUTPUTS; + + src11_valid = sink_channel[11] && sink_valid; + + src12_data = sink_data; + src12_startofpacket = sink_startofpacket; + src12_endofpacket = sink_endofpacket; + src12_channel = sink_channel >> NUM_OUTPUTS; + + src12_valid = sink_channel[12] && sink_valid; + + src13_data = sink_data; + src13_startofpacket = sink_startofpacket; + src13_endofpacket = sink_endofpacket; + src13_channel = sink_channel >> NUM_OUTPUTS; + + src13_valid = sink_channel[13] && sink_valid; + + src14_data = sink_data; + src14_startofpacket = sink_startofpacket; + src14_endofpacket = sink_endofpacket; + src14_channel = sink_channel >> NUM_OUTPUTS; + + src14_valid = sink_channel[14] && sink_valid; + + src15_data = sink_data; + src15_startofpacket = sink_startofpacket; + src15_endofpacket = sink_endofpacket; + src15_channel = sink_channel >> NUM_OUTPUTS; + + src15_valid = sink_channel[15] && sink_valid; + + src16_data = sink_data; + src16_startofpacket = sink_startofpacket; + src16_endofpacket = sink_endofpacket; + src16_channel = sink_channel >> NUM_OUTPUTS; + + src16_valid = sink_channel[16] && sink_valid; + + src17_data = sink_data; + src17_startofpacket = sink_startofpacket; + src17_endofpacket = sink_endofpacket; + src17_channel = sink_channel >> NUM_OUTPUTS; + + src17_valid = sink_channel[17] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + assign ready_vector[2] = src2_ready; + assign ready_vector[3] = src3_ready; + assign ready_vector[4] = src4_ready; + assign ready_vector[5] = src5_ready; + assign ready_vector[6] = src6_ready; + assign ready_vector[7] = src7_ready; + assign ready_vector[8] = src8_ready; + assign ready_vector[9] = src9_ready; + assign ready_vector[10] = src10_ready; + assign ready_vector[11] = src11_ready; + assign ready_vector[12] = src12_ready; + assign ready_vector[13] = src13_ready; + assign ready_vector[14] = src14_ready; + assign ready_vector[15] = src15_ready; + assign ready_vector[16] = src16_ready; + assign ready_vector[17] = src17_ready; + + assign sink_ready = |(sink_channel & ready_vector); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv b/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv index 494c070..76ec5b4 100644 --- a/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv +++ b/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv @@ -1,308 +1,308 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "round-robin" -// PIPELINE_ARB: 1 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_cmd_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 1; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - wire [NUM_INPUTS - 1 : 0] eop; - assign eop[0] = sink0_endofpacket; - assign eop[1] = sink1_endofpacket; - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - reg [NUM_INPUTS - 1 : 0] locked = '0; - always @(posedge clk or posedge reset) begin - if (reset) begin - locked <= '0; - end - else begin - locked <= next_grant & lock; - end - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (update_grant) begin - share_count <= next_grant_share; - share_count_zero_flag <= (next_grant_share == '0); - end - else if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // The pipeline delays grant by one cycle, so - // we have to calculate the update_grant signal - // one cycle ahead of time. - // - // Possible optimization: omit the first clause - // "if (!packet_in_progress & ~src_valid) ..." - // cost: one idle cycle at the the beginning of each - // grant cycle. - // benefit: save a small amount of logic. - // ------------------------------------------ - if (!packet_in_progress & !src_valid) - update_grant = 1; - if (last_cycle && share_count_zero_flag) - update_grant = 1; - end - - wire save_grant; - assign save_grant = update_grant; - assign grant = saved_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] prev_request; - always @(posedge clk, posedge reset) begin - if (reset) - prev_request <= '0; - else - prev_request <= request & ~(valid & eop); - end - - assign request = (PIPELINE_ARB == 1) ? valid | locked : - prev_request | valid | locked; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("round-robin"), - .PIPELINE (1) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 1 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_cmd_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 1; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + wire [NUM_INPUTS - 1 : 0] eop; + assign eop[0] = sink0_endofpacket; + assign eop[1] = sink1_endofpacket; + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + reg [NUM_INPUTS - 1 : 0] locked = '0; + always @(posedge clk or posedge reset) begin + if (reset) begin + locked <= '0; + end + else begin + locked <= next_grant & lock; + end + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (update_grant) begin + share_count <= next_grant_share; + share_count_zero_flag <= (next_grant_share == '0); + end + else if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // The pipeline delays grant by one cycle, so + // we have to calculate the update_grant signal + // one cycle ahead of time. + // + // Possible optimization: omit the first clause + // "if (!packet_in_progress & ~src_valid) ..." + // cost: one idle cycle at the the beginning of each + // grant cycle. + // benefit: save a small amount of logic. + // ------------------------------------------ + if (!packet_in_progress & !src_valid) + update_grant = 1; + if (last_cycle && share_count_zero_flag) + update_grant = 1; + end + + wire save_grant; + assign save_grant = update_grant; + assign grant = saved_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] prev_request; + always @(posedge clk, posedge reset) begin + if (reset) + prev_request <= '0; + else + prev_request <= request & ~(valid & eop); + end + + assign request = (PIPELINE_ARB == 1) ? valid | locked : + prev_request | valid | locked; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("round-robin"), + .PIPELINE (1) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/db/ip/nios_system/submodules/nios_system_hex0.v b/db/ip/nios_system/submodules/nios_system_hex0.v index ec4cd20..365eed9 100644 --- a/db/ip/nios_system/submodules/nios_system_hex0.v +++ b/db/ip/nios_system/submodules/nios_system_hex0.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_hex0 ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 6: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 6: 0] data_out; - wire [ 6: 0] out_port; - wire [ 6: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {7 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[6 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_hex0 ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 6: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 6: 0] data_out; + wire [ 6: 0] out_port; + wire [ 6: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {7 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[6 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_id_router.sv b/db/ip/nios_system/submodules/nios_system_id_router.sv index cb46634..90937e8 100644 --- a/db/ip/nios_system/submodules/nios_system_id_router.sv +++ b/db/ip/nios_system/submodules/nios_system_id_router.sv @@ -1,221 +1,221 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 1 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 1 ) begin - src_channel = 18'b01; - end - - if (destid == 0 ) begin - src_channel = 18'b10; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 1 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 1 ) begin + src_channel = 18'b01; + end + + if (destid == 0 ) begin + src_channel = 18'b10; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_id_router_002.sv b/db/ip/nios_system/submodules/nios_system_id_router_002.sv index 6006063..a80e831 100644 --- a/db/ip/nios_system/submodules/nios_system_id_router_002.sv +++ b/db/ip/nios_system/submodules/nios_system_id_router_002.sv @@ -1,217 +1,217 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_002_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_002 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_002_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_002_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_002 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_002_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_irq_mapper.sv b/db/ip/nios_system/submodules/nios_system_irq_mapper.sv index d318630..cc0a8bb 100644 --- a/db/ip/nios_system/submodules/nios_system_irq_mapper.sv +++ b/db/ip/nios_system/submodules/nios_system_irq_mapper.sv @@ -1,59 +1,59 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Altera IRQ Mapper -// -// Parameters -// NUM_RCVRS : 1 -// SENDER_IRW_WIDTH : 32 -// IRQ_MAP : 0:5 -// -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_irq_mapper -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // IRQ Receivers - // ------------------- - input receiver0_irq, - - // ------------------- - // Command Source (Output) - // ------------------- - output reg [31 : 0] sender_irq -); - - - always @* begin - sender_irq = 0; - - sender_irq[5] = receiver0_irq; - end - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 1 +// SENDER_IRW_WIDTH : 32 +// IRQ_MAP : 0:5 +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + input receiver0_irq, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [31 : 0] sender_irq +); + + + always @* begin + sender_irq = 0; + + sender_irq[5] = receiver0_irq; + end + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_jtag_uart.v b/db/ip/nios_system/submodules/nios_system_jtag_uart.v index 11ff56f..0d02445 100644 --- a/db/ip/nios_system/submodules/nios_system_jtag_uart.v +++ b/db/ip/nios_system/submodules/nios_system_jtag_uart.v @@ -1,583 +1,583 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_w ( - // inputs: - clk, - fifo_wdata, - fifo_wr, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input [ 7: 0] fifo_wdata; - input fifo_wr; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - always @(posedge clk) - begin - if (fifo_wr) - $write("%c", fifo_wdata); - end - - - assign wfifo_used = {6{1'b0}}; - assign r_dat = {8{1'b0}}; - assign fifo_FF = 1'b0; - assign wfifo_empty = 1'b1; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_w ( - // inputs: - clk, - fifo_clear, - fifo_wdata, - fifo_wr, - rd_wfifo, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input fifo_clear; - input [ 7: 0] fifo_wdata; - input fifo_wr; - input rd_wfifo; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo wfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (fifo_wdata), -// .empty (wfifo_empty), -// .full (fifo_FF), -// .q (r_dat), -// .rdreq (rd_wfifo), -// .usedw (wfifo_used), -// .wrreq (fifo_wr) -// ); -// -// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// wfifo.lpm_numwords = 64, -// wfifo.lpm_showahead = "OFF", -// wfifo.lpm_type = "scfifo", -// wfifo.lpm_width = 8, -// wfifo.lpm_widthu = 6, -// wfifo.overflow_checking = "OFF", -// wfifo.underflow_checking = "OFF", -// wfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_r ( - // inputs: - clk, - fifo_rd, - rst_n, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_rd; - input rst_n; - - reg [ 31: 0] bytes_left; - wire fifo_EF; - reg fifo_rd_d; - wire [ 7: 0] fifo_rdata; - wire new_rom; - wire [ 31: 0] num_bytes; - wire [ 6: 0] rfifo_entries; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Generate rfifo_entries for simulation - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - bytes_left <= 32'h0; - fifo_rd_d <= 1'b0; - end - else - begin - fifo_rd_d <= fifo_rd; - // decrement on read - if (fifo_rd_d) - bytes_left <= bytes_left - 1'b1; - // catch new contents - if (new_rom) - bytes_left <= num_bytes; - end - end - - - assign fifo_EF = bytes_left == 32'b0; - assign rfifo_full = bytes_left > 7'h40; - assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; - assign rfifo_used = rfifo_entries[5 : 0]; - assign new_rom = 1'b0; - assign num_bytes = 32'b0; - assign fifo_rdata = 8'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_r ( - // inputs: - clk, - fifo_clear, - fifo_rd, - rst_n, - t_dat, - wr_rfifo, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_clear; - input fifo_rd; - input rst_n; - input [ 7: 0] t_dat; - input wr_rfifo; - - wire fifo_EF; - wire [ 7: 0] fifo_rdata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo rfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (t_dat), -// .empty (fifo_EF), -// .full (rfifo_full), -// .q (fifo_rdata), -// .rdreq (fifo_rd), -// .usedw (rfifo_used), -// .wrreq (wr_rfifo) -// ); -// -// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// rfifo.lpm_numwords = 64, -// rfifo.lpm_showahead = "OFF", -// rfifo.lpm_type = "scfifo", -// rfifo.lpm_width = 8, -// rfifo.lpm_widthu = 6, -// rfifo.overflow_checking = "OFF", -// rfifo.underflow_checking = "OFF", -// rfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart ( - // inputs: - av_address, - av_chipselect, - av_read_n, - av_write_n, - av_writedata, - clk, - rst_n, - - // outputs: - av_irq, - av_readdata, - av_waitrequest, - dataavailable, - readyfordata - ) - /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; - - output av_irq; - output [ 31: 0] av_readdata; - output av_waitrequest; - output dataavailable; - output readyfordata; - input av_address; - input av_chipselect; - input av_read_n; - input av_write_n; - input [ 31: 0] av_writedata; - input clk; - input rst_n; - - reg ac; - wire activity; - wire av_irq; - wire [ 31: 0] av_readdata; - reg av_waitrequest; - reg dataavailable; - reg fifo_AE; - reg fifo_AF; - wire fifo_EF; - wire fifo_FF; - wire fifo_clear; - wire fifo_rd; - wire [ 7: 0] fifo_rdata; - wire [ 7: 0] fifo_wdata; - reg fifo_wr; - reg ien_AE; - reg ien_AF; - wire ipen_AE; - wire ipen_AF; - reg pause_irq; - wire [ 7: 0] r_dat; - wire r_ena; - reg r_val; - wire rd_wfifo; - reg read_0; - reg readyfordata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - reg rvalid; - reg sim_r_ena; - reg sim_t_dat; - reg sim_t_ena; - reg sim_t_pause; - wire [ 7: 0] t_dat; - reg t_dav; - wire t_ena; - wire t_pause; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - reg woverflow; - wire wr_rfifo; - //avalon_jtag_slave, which is an e_avalon_slave - assign rd_wfifo = r_ena & ~wfifo_empty; - assign wr_rfifo = t_ena & ~rfifo_full; - assign fifo_clear = ~rst_n; - nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_clear (fifo_clear), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .rd_wfifo (rd_wfifo), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_clear (fifo_clear), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n), - .t_dat (t_dat), - .wr_rfifo (wr_rfifo) - ); - - assign ipen_AE = ien_AE & fifo_AE; - assign ipen_AF = ien_AF & (pause_irq | fifo_AF); - assign av_irq = ipen_AE | ipen_AF; - assign activity = t_pause | t_ena; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - pause_irq <= 1'b0; - else // only if fifo is not empty... - if (t_pause & ~fifo_EF) - pause_irq <= 1'b1; - else if (read_0) - pause_irq <= 1'b0; - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - r_val <= 1'b0; - t_dav <= 1'b1; - end - else - begin - r_val <= r_ena & ~wfifo_empty; - t_dav <= ~rfifo_full; - end - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - fifo_AE <= 1'b0; - fifo_AF <= 1'b0; - fifo_wr <= 1'b0; - rvalid <= 1'b0; - read_0 <= 1'b0; - ien_AE <= 1'b0; - ien_AF <= 1'b0; - ac <= 1'b0; - woverflow <= 1'b0; - av_waitrequest <= 1'b1; - end - else - begin - fifo_AE <= {fifo_FF,wfifo_used} <= 8; - fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; - fifo_wr <= 1'b0; - read_0 <= 1'b0; - av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); - if (activity) - ac <= 1'b1; - // write - if (av_chipselect & ~av_write_n & av_waitrequest) - // addr 1 is control; addr 0 is data - if (av_address) - begin - ien_AF <= av_writedata[0]; - ien_AE <= av_writedata[1]; - if (av_writedata[10] & ~activity) - ac <= 1'b0; - end - else - begin - fifo_wr <= ~fifo_FF; - woverflow <= fifo_FF; - end - // read - if (av_chipselect & ~av_read_n & av_waitrequest) - begin - // addr 1 is interrupt; addr 0 is data - if (~av_address) - rvalid <= ~fifo_EF; - read_0 <= ~av_address; - end - end - end - - - assign fifo_wdata = av_writedata[7 : 0]; - assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; - assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - readyfordata <= 0; - else - readyfordata <= ~fifo_FF; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Tie off Atlantic Interface signals not used for simulation - always @(posedge clk) - begin - sim_t_pause <= 1'b0; - sim_t_ena <= 1'b0; - sim_t_dat <= t_dav ? r_dat : {8{r_val}}; - sim_r_ena <= 1'b0; - end - - - assign r_ena = sim_r_ena; - assign t_ena = sim_t_ena; - assign t_dat = sim_t_dat; - assign t_pause = sim_t_pause; - always @(fifo_EF) - begin - dataavailable = ~fifo_EF; - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic -// ( -// .clk (clk), -// .r_dat (r_dat), -// .r_ena (r_ena), -// .r_val (r_val), -// .rst_n (rst_n), -// .t_dat (t_dat), -// .t_dav (t_dav), -// .t_ena (t_ena), -// .t_pause (t_pause) -// ); -// -// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; -// -// always @(posedge clk or negedge rst_n) -// begin -// if (rst_n == 0) -// dataavailable <= 0; -// else -// dataavailable <= ~fifo_EF; -// end -// -// -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_w ( + // inputs: + clk, + fifo_wdata, + fifo_wr, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input [ 7: 0] fifo_wdata; + input fifo_wr; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + always @(posedge clk) + begin + if (fifo_wr) + $write("%c", fifo_wdata); + end + + + assign wfifo_used = {6{1'b0}}; + assign r_dat = {8{1'b0}}; + assign fifo_FF = 1'b0; + assign wfifo_empty = 1'b1; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_w ( + // inputs: + clk, + fifo_clear, + fifo_wdata, + fifo_wr, + rd_wfifo, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input fifo_clear; + input [ 7: 0] fifo_wdata; + input fifo_wr; + input rd_wfifo; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo wfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (fifo_wdata), +// .empty (wfifo_empty), +// .full (fifo_FF), +// .q (r_dat), +// .rdreq (rd_wfifo), +// .usedw (wfifo_used), +// .wrreq (fifo_wr) +// ); +// +// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// wfifo.lpm_numwords = 64, +// wfifo.lpm_showahead = "OFF", +// wfifo.lpm_type = "scfifo", +// wfifo.lpm_width = 8, +// wfifo.lpm_widthu = 6, +// wfifo.overflow_checking = "OFF", +// wfifo.underflow_checking = "OFF", +// wfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_r ( + // inputs: + clk, + fifo_rd, + rst_n, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_rd; + input rst_n; + + reg [ 31: 0] bytes_left; + wire fifo_EF; + reg fifo_rd_d; + wire [ 7: 0] fifo_rdata; + wire new_rom; + wire [ 31: 0] num_bytes; + wire [ 6: 0] rfifo_entries; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Generate rfifo_entries for simulation + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + bytes_left <= 32'h0; + fifo_rd_d <= 1'b0; + end + else + begin + fifo_rd_d <= fifo_rd; + // decrement on read + if (fifo_rd_d) + bytes_left <= bytes_left - 1'b1; + // catch new contents + if (new_rom) + bytes_left <= num_bytes; + end + end + + + assign fifo_EF = bytes_left == 32'b0; + assign rfifo_full = bytes_left > 7'h40; + assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; + assign rfifo_used = rfifo_entries[5 : 0]; + assign new_rom = 1'b0; + assign num_bytes = 32'b0; + assign fifo_rdata = 8'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_r ( + // inputs: + clk, + fifo_clear, + fifo_rd, + rst_n, + t_dat, + wr_rfifo, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_clear; + input fifo_rd; + input rst_n; + input [ 7: 0] t_dat; + input wr_rfifo; + + wire fifo_EF; + wire [ 7: 0] fifo_rdata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo rfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (t_dat), +// .empty (fifo_EF), +// .full (rfifo_full), +// .q (fifo_rdata), +// .rdreq (fifo_rd), +// .usedw (rfifo_used), +// .wrreq (wr_rfifo) +// ); +// +// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// rfifo.lpm_numwords = 64, +// rfifo.lpm_showahead = "OFF", +// rfifo.lpm_type = "scfifo", +// rfifo.lpm_width = 8, +// rfifo.lpm_widthu = 6, +// rfifo.overflow_checking = "OFF", +// rfifo.underflow_checking = "OFF", +// rfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart ( + // inputs: + av_address, + av_chipselect, + av_read_n, + av_write_n, + av_writedata, + clk, + rst_n, + + // outputs: + av_irq, + av_readdata, + av_waitrequest, + dataavailable, + readyfordata + ) + /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; + + output av_irq; + output [ 31: 0] av_readdata; + output av_waitrequest; + output dataavailable; + output readyfordata; + input av_address; + input av_chipselect; + input av_read_n; + input av_write_n; + input [ 31: 0] av_writedata; + input clk; + input rst_n; + + reg ac; + wire activity; + wire av_irq; + wire [ 31: 0] av_readdata; + reg av_waitrequest; + reg dataavailable; + reg fifo_AE; + reg fifo_AF; + wire fifo_EF; + wire fifo_FF; + wire fifo_clear; + wire fifo_rd; + wire [ 7: 0] fifo_rdata; + wire [ 7: 0] fifo_wdata; + reg fifo_wr; + reg ien_AE; + reg ien_AF; + wire ipen_AE; + wire ipen_AF; + reg pause_irq; + wire [ 7: 0] r_dat; + wire r_ena; + reg r_val; + wire rd_wfifo; + reg read_0; + reg readyfordata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + reg rvalid; + reg sim_r_ena; + reg sim_t_dat; + reg sim_t_ena; + reg sim_t_pause; + wire [ 7: 0] t_dat; + reg t_dav; + wire t_ena; + wire t_pause; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + reg woverflow; + wire wr_rfifo; + //avalon_jtag_slave, which is an e_avalon_slave + assign rd_wfifo = r_ena & ~wfifo_empty; + assign wr_rfifo = t_ena & ~rfifo_full; + assign fifo_clear = ~rst_n; + nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_clear (fifo_clear), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .rd_wfifo (rd_wfifo), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_clear (fifo_clear), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n), + .t_dat (t_dat), + .wr_rfifo (wr_rfifo) + ); + + assign ipen_AE = ien_AE & fifo_AE; + assign ipen_AF = ien_AF & (pause_irq | fifo_AF); + assign av_irq = ipen_AE | ipen_AF; + assign activity = t_pause | t_ena; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + pause_irq <= 1'b0; + else // only if fifo is not empty... + if (t_pause & ~fifo_EF) + pause_irq <= 1'b1; + else if (read_0) + pause_irq <= 1'b0; + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + r_val <= 1'b0; + t_dav <= 1'b1; + end + else + begin + r_val <= r_ena & ~wfifo_empty; + t_dav <= ~rfifo_full; + end + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + fifo_AE <= 1'b0; + fifo_AF <= 1'b0; + fifo_wr <= 1'b0; + rvalid <= 1'b0; + read_0 <= 1'b0; + ien_AE <= 1'b0; + ien_AF <= 1'b0; + ac <= 1'b0; + woverflow <= 1'b0; + av_waitrequest <= 1'b1; + end + else + begin + fifo_AE <= {fifo_FF,wfifo_used} <= 8; + fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; + fifo_wr <= 1'b0; + read_0 <= 1'b0; + av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); + if (activity) + ac <= 1'b1; + // write + if (av_chipselect & ~av_write_n & av_waitrequest) + // addr 1 is control; addr 0 is data + if (av_address) + begin + ien_AF <= av_writedata[0]; + ien_AE <= av_writedata[1]; + if (av_writedata[10] & ~activity) + ac <= 1'b0; + end + else + begin + fifo_wr <= ~fifo_FF; + woverflow <= fifo_FF; + end + // read + if (av_chipselect & ~av_read_n & av_waitrequest) + begin + // addr 1 is interrupt; addr 0 is data + if (~av_address) + rvalid <= ~fifo_EF; + read_0 <= ~av_address; + end + end + end + + + assign fifo_wdata = av_writedata[7 : 0]; + assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; + assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + readyfordata <= 0; + else + readyfordata <= ~fifo_FF; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Tie off Atlantic Interface signals not used for simulation + always @(posedge clk) + begin + sim_t_pause <= 1'b0; + sim_t_ena <= 1'b0; + sim_t_dat <= t_dav ? r_dat : {8{r_val}}; + sim_r_ena <= 1'b0; + end + + + assign r_ena = sim_r_ena; + assign t_ena = sim_t_ena; + assign t_dat = sim_t_dat; + assign t_pause = sim_t_pause; + always @(fifo_EF) + begin + dataavailable = ~fifo_EF; + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic +// ( +// .clk (clk), +// .r_dat (r_dat), +// .r_ena (r_ena), +// .r_val (r_val), +// .rst_n (rst_n), +// .t_dat (t_dat), +// .t_dav (t_dav), +// .t_ena (t_ena), +// .t_pause (t_pause) +// ); +// +// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; +// +// always @(posedge clk or negedge rst_n) +// begin +// if (rst_n == 0) +// dataavailable <= 0; +// else +// dataavailable <= ~fifo_EF; +// end +// +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v b/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v index 221f3db..f58d30f 100644 --- a/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v +++ b/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_16207_0 ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_16207_0 ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_lcd_on.v b/db/ip/nios_system/submodules/nios_system_lcd_on.v index ed02e25..4e9a8dc 100644 --- a/db/ip/nios_system/submodules/nios_system_lcd_on.v +++ b/db/ip/nios_system/submodules/nios_system_lcd_on.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_on ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_on ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc b/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc index 41645ff..4848c5a 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor.sdc @@ -1,53 +1,53 @@ -# Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -# use of Altera Corporation's design tools, logic functions and other -# software and tools, and its AMPP partner logic functions, and any -# output files any of the foregoing (including device programming or -# simulation files), and any associated documentation or information are -# expressly subject to the terms and conditions of the Altera Program -# License Subscription Agreement or other applicable license agreement, -# including, without limitation, that your use is for the sole purpose -# of programming logic devices manufactured by Altera and sold by Altera -# or its authorized distributors. Please refer to the applicable -# agreement for further details. - -#************************************************************** -# Timequest JTAG clock definition -# Uncommenting the following lines will define the JTAG -# clock in TimeQuest Timing Analyzer -#************************************************************** - -#create_clock -period 10MHz {altera_reserved_tck} -#set_clock_groups -asynchronous -group {altera_reserved_tck} - -#************************************************************** -# Set TCL Path Variables -#************************************************************** - -set nios_system_nios2_processor nios_system_nios2_processor:* -set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci -set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break -set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem -set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug -set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper -set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck -set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk -set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] -set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] -set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] -set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] -set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] -set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] -set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] - -#************************************************************** -# Set False Paths -#************************************************************** - -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* -set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* -set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go +# Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +# use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any +# output files any of the foregoing (including device programming or +# simulation files), and any associated documentation or information are +# expressly subject to the terms and conditions of the Altera Program +# License Subscription Agreement or other applicable license agreement, +# including, without limitation, that your use is for the sole purpose +# of programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +#************************************************************** +# Timequest JTAG clock definition +# Uncommenting the following lines will define the JTAG +# clock in TimeQuest Timing Analyzer +#************************************************************** + +#create_clock -period 10MHz {altera_reserved_tck} +#set_clock_groups -asynchronous -group {altera_reserved_tck} + +#************************************************************** +# Set TCL Path Variables +#************************************************************** + +set nios_system_nios2_processor nios_system_nios2_processor:* +set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci +set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break +set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem +set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug +set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper +set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck +set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk +set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] +set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] +set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] +set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] +set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] +set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] +set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] + +#************************************************************** +# Set False Paths +#************************************************************** + +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* +set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* +set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor.v b/db/ip/nios_system/submodules/nios_system_nios2_processor.v index e1640d4..7e8e063 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor.v +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor.v @@ -1,5672 +1,5672 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_a_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_b_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_debug ( - // inputs: - clk, - dbrk_break, - debugreq, - hbreak_enabled, - jdo, - jrst_n, - ocireg_ers, - ocireg_mrs, - reset, - st_ready_test_idle, - take_action_ocimem_a, - take_action_ocireg, - xbrk_break, - - // outputs: - debugack, - monitor_error, - monitor_go, - monitor_ready, - oci_hbreak_req, - resetlatch, - resetrequest - ) -; - - output debugack; - output monitor_error; - output monitor_go; - output monitor_ready; - output oci_hbreak_req; - output resetlatch; - output resetrequest; - input clk; - input dbrk_break; - input debugreq; - input hbreak_enabled; - input [ 37: 0] jdo; - input jrst_n; - input ocireg_ers; - input ocireg_mrs; - input reset; - input st_ready_test_idle; - input take_action_ocimem_a; - input take_action_ocireg; - input xbrk_break; - - reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire debugack; - reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire oci_hbreak_req; - wire reset_sync; - reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire unxcomplemented_resetxx0; - assign unxcomplemented_resetxx0 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer - ( - .clk (clk), - .din (reset), - .dout (reset_sync), - .reset_n (unxcomplemented_resetxx0) - ); - - defparam the_altera_std_synchronizer.depth = 2; - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - break_on_reset <= 1'b0; - resetrequest <= 1'b0; - jtag_break <= 1'b0; - end - else if (take_action_ocimem_a) - begin - resetrequest <= jdo[22]; - jtag_break <= jdo[21] ? 1 - : jdo[20] ? 0 - : jtag_break; - - break_on_reset <= jdo[19] ? 1 - : jdo[18] ? 0 - : break_on_reset; - - resetlatch <= jdo[24] ? 0 : resetlatch; - end - else if (reset_sync) - begin - jtag_break <= break_on_reset; - resetlatch <= 1; - end - else if (debugreq & ~debugack & break_on_reset) - jtag_break <= 1'b1; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - monitor_ready <= 1'b0; - monitor_error <= 1'b0; - monitor_go <= 1'b0; - end - else - begin - if (take_action_ocimem_a && jdo[25]) - monitor_ready <= 1'b0; - else if (take_action_ocireg && ocireg_mrs) - monitor_ready <= 1'b1; - if (take_action_ocimem_a && jdo[25]) - monitor_error <= 1'b0; - else if (take_action_ocireg && ocireg_ers) - monitor_error <= 1'b1; - if (take_action_ocimem_a && jdo[23]) - monitor_go <= 1'b1; - else if (st_ready_test_idle) - monitor_go <= 1'b0; - end - end - - - assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; - assign debugack = ~hbreak_enabled; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_ociram_sp_ram_module ( - // inputs: - address, - byteenable, - clock, - data, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input [ 7: 0] address; - input [ 3: 0] byteenable; - input clock; - input [ 31: 0] data; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clock), - .data_a (data), - .q_a (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 256, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 8; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_ocimem ( - // inputs: - address, - byteenable, - clk, - debugaccess, - jdo, - jrst_n, - read, - take_action_ocimem_a, - take_action_ocimem_b, - take_no_action_ocimem_a, - write, - writedata, - - // outputs: - MonDReg, - ociram_readdata, - waitrequest - ) -; - - output [ 31: 0] MonDReg; - output [ 31: 0] ociram_readdata; - output waitrequest; - input [ 8: 0] address; - input [ 3: 0] byteenable; - input clk; - input debugaccess; - input [ 37: 0] jdo; - input jrst_n; - input read; - input take_action_ocimem_a; - input take_action_ocimem_b; - input take_no_action_ocimem_a; - input write; - input [ 31: 0] writedata; - - reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 8: 0] MonARegAddrInc; - wire MonARegAddrIncAccessingRAM; - reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire avalon_ram_wr; - wire [ 31: 0] cfgrom_readdata; - reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 7: 0] ociram_addr; - wire [ 3: 0] ociram_byteenable; - wire [ 31: 0] ociram_readdata; - wire [ 31: 0] ociram_wr_data; - wire ociram_wr_en; - reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - jtag_rd <= 1'b0; - jtag_rd_d1 <= 1'b0; - jtag_ram_wr <= 1'b0; - jtag_ram_rd <= 1'b0; - jtag_ram_rd_d1 <= 1'b0; - jtag_ram_access <= 1'b0; - MonAReg <= 0; - MonDReg <= 0; - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else - begin - if (take_no_action_ocimem_a) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - jtag_rd <= 1'b1; - jtag_ram_rd <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else if (take_action_ocimem_a) - begin - MonAReg[10 : 2] <= { jdo[17], - jdo[33 : 26] }; - - jtag_rd <= 1'b1; - jtag_ram_rd <= ~jdo[17]; - jtag_ram_access <= ~jdo[17]; - end - else if (take_action_ocimem_b) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - MonDReg <= jdo[34 : 3]; - jtag_ram_wr <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else - begin - jtag_rd <= 0; - jtag_ram_wr <= 0; - jtag_ram_rd <= 0; - jtag_ram_access <= 0; - if (jtag_rd_d1) - MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; - end - jtag_rd_d1 <= jtag_rd; - jtag_ram_rd_d1 <= jtag_ram_rd; - if (~waitrequest) - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else if (write) - waitrequest <= ~address[8] & jtag_ram_access; - else if (read) - begin - avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); - waitrequest <= ~avalon_ociram_readdata_ready; - end - else - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - end - end - - - assign MonARegAddrInc = MonAReg[10 : 2]+1; - assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; - assign avalon_ram_wr = write & ~address[8] & debugaccess; - assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; - assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; - assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; - assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; -//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram -nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram - ( - .address (ociram_addr), - .byteenable (ociram_byteenable), - .clock (clk), - .data (ociram_wr_data), - .q (ociram_readdata), - .wren (ociram_wr_en) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; -`else -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; -//synthesis read_comments_as_HDL off - assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : - (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : - (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : - (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : - (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : - 32'h00000000; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_avalon_reg ( - // inputs: - address, - clk, - debugaccess, - monitor_error, - monitor_go, - monitor_ready, - reset_n, - write, - writedata, - - // outputs: - oci_ienable, - oci_reg_readdata, - oci_single_step_mode, - ocireg_ers, - ocireg_mrs, - take_action_ocireg - ) -; - - output [ 31: 0] oci_ienable; - output [ 31: 0] oci_reg_readdata; - output oci_single_step_mode; - output ocireg_ers; - output ocireg_mrs; - output take_action_ocireg; - input [ 8: 0] address; - input clk; - input debugaccess; - input monitor_error; - input monitor_go; - input monitor_ready; - input reset_n; - input write; - input [ 31: 0] writedata; - - reg [ 31: 0] oci_ienable; - wire oci_reg_00_addressed; - wire oci_reg_01_addressed; - wire [ 31: 0] oci_reg_readdata; - reg oci_single_step_mode; - wire ocireg_ers; - wire ocireg_mrs; - wire ocireg_sstep; - wire take_action_oci_intr_mask_reg; - wire take_action_ocireg; - wire write_strobe; - assign oci_reg_00_addressed = address == 9'h100; - assign oci_reg_01_addressed = address == 9'h101; - assign write_strobe = write & debugaccess; - assign take_action_ocireg = write_strobe & oci_reg_00_addressed; - assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; - assign ocireg_ers = writedata[1]; - assign ocireg_mrs = writedata[0]; - assign ocireg_sstep = writedata[3]; - assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, - monitor_ready, monitor_error} : - oci_reg_01_addressed ? oci_ienable : - 32'b0; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_single_step_mode <= 1'b0; - else if (take_action_ocireg) - oci_single_step_mode <= ocireg_sstep; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_ienable <= 32'b00000000000000000000000000100000; - else if (take_action_oci_intr_mask_reg) - oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_break ( - // inputs: - clk, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - jdo, - jrst_n, - reset_n, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - xbrk_goto0, - xbrk_goto1, - - // outputs: - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - trigbrktype, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3 - ) -; - - output [ 31: 0] break_readreg; - output dbrk_hit0_latch; - output dbrk_hit1_latch; - output dbrk_hit2_latch; - output dbrk_hit3_latch; - output trigbrktype; - output trigger_state_0; - output trigger_state_1; - output [ 7: 0] xbrk_ctrl0; - output [ 7: 0] xbrk_ctrl1; - output [ 7: 0] xbrk_ctrl2; - output [ 7: 0] xbrk_ctrl3; - input clk; - input dbrk_break; - input dbrk_goto0; - input dbrk_goto1; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_break_a; - input take_action_break_b; - input take_action_break_c; - input take_no_action_break_a; - input take_no_action_break_b; - input take_no_action_break_c; - input xbrk_goto0; - input xbrk_goto1; - - wire [ 3: 0] break_a_wpr; - wire [ 1: 0] break_a_wpr_high_bits; - wire [ 1: 0] break_a_wpr_low_bits; - wire [ 1: 0] break_b_rr; - wire [ 1: 0] break_c_rr; - reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire dbrk0_high_value; - wire dbrk0_low_value; - wire dbrk1_high_value; - wire dbrk1_low_value; - wire dbrk2_high_value; - wire dbrk2_low_value; - wire dbrk3_high_value; - wire dbrk3_low_value; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire take_action_any_break; - reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg trigger_state; - wire trigger_state_0; - wire trigger_state_1; - wire [ 31: 0] xbrk0_value; - wire [ 31: 0] xbrk1_value; - wire [ 31: 0] xbrk2_value; - wire [ 31: 0] xbrk3_value; - reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - assign break_a_wpr = jdo[35 : 32]; - assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; - assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; - assign break_b_rr = jdo[33 : 32]; - assign break_c_rr = jdo[33 : 32]; - assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - xbrk_ctrl0 <= 0; - xbrk_ctrl1 <= 0; - xbrk_ctrl2 <= 0; - xbrk_ctrl3 <= 0; - trigbrktype <= 0; - end - else - begin - if (take_action_any_break) - trigbrktype <= 0; - else if (dbrk_break) - trigbrktype <= 1; - if (take_action_break_b) - begin - if ((break_b_rr == 2'b00) && (0 >= 1)) - begin - xbrk_ctrl0[0] <= jdo[27]; - xbrk_ctrl0[1] <= jdo[28]; - xbrk_ctrl0[2] <= jdo[29]; - xbrk_ctrl0[3] <= jdo[30]; - xbrk_ctrl0[4] <= jdo[21]; - xbrk_ctrl0[5] <= jdo[20]; - xbrk_ctrl0[6] <= jdo[19]; - xbrk_ctrl0[7] <= jdo[18]; - end - if ((break_b_rr == 2'b01) && (0 >= 2)) - begin - xbrk_ctrl1[0] <= jdo[27]; - xbrk_ctrl1[1] <= jdo[28]; - xbrk_ctrl1[2] <= jdo[29]; - xbrk_ctrl1[3] <= jdo[30]; - xbrk_ctrl1[4] <= jdo[21]; - xbrk_ctrl1[5] <= jdo[20]; - xbrk_ctrl1[6] <= jdo[19]; - xbrk_ctrl1[7] <= jdo[18]; - end - if ((break_b_rr == 2'b10) && (0 >= 3)) - begin - xbrk_ctrl2[0] <= jdo[27]; - xbrk_ctrl2[1] <= jdo[28]; - xbrk_ctrl2[2] <= jdo[29]; - xbrk_ctrl2[3] <= jdo[30]; - xbrk_ctrl2[4] <= jdo[21]; - xbrk_ctrl2[5] <= jdo[20]; - xbrk_ctrl2[6] <= jdo[19]; - xbrk_ctrl2[7] <= jdo[18]; - end - if ((break_b_rr == 2'b11) && (0 >= 4)) - begin - xbrk_ctrl3[0] <= jdo[27]; - xbrk_ctrl3[1] <= jdo[28]; - xbrk_ctrl3[2] <= jdo[29]; - xbrk_ctrl3[3] <= jdo[30]; - xbrk_ctrl3[4] <= jdo[21]; - xbrk_ctrl3[5] <= jdo[20]; - xbrk_ctrl3[6] <= jdo[19]; - xbrk_ctrl3[7] <= jdo[18]; - end - end - end - end - - - assign dbrk_hit0_latch = 1'b0; - assign dbrk0_low_value = 0; - assign dbrk0_high_value = 0; - assign dbrk_hit1_latch = 1'b0; - assign dbrk1_low_value = 0; - assign dbrk1_high_value = 0; - assign dbrk_hit2_latch = 1'b0; - assign dbrk2_low_value = 0; - assign dbrk2_high_value = 0; - assign dbrk_hit3_latch = 1'b0; - assign dbrk3_low_value = 0; - assign dbrk3_high_value = 0; - assign xbrk0_value = 32'b0; - assign xbrk1_value = 32'b0; - assign xbrk2_value = 32'b0; - assign xbrk3_value = 32'b0; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - break_readreg <= 32'b0; - else if (take_action_any_break) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_a) - case (break_a_wpr_high_bits) - - 2'd0: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= xbrk0_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= xbrk1_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= xbrk2_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= xbrk3_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd0 - - 2'd1: begin - break_readreg <= 32'b0; - end // 2'd1 - - 2'd2: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_low_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_low_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_low_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_low_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd2 - - 2'd3: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_high_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_high_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_high_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_high_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd3 - - endcase // break_a_wpr_high_bits - else if (take_no_action_break_b) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_c) - break_readreg <= jdo[31 : 0]; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trigger_state <= 0; - else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) - trigger_state <= 0; - else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) - trigger_state <= -1; - end - - - assign trigger_state_0 = ~trigger_state; - assign trigger_state_1 = trigger_state; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_xbrk ( - // inputs: - D_valid, - E_valid, - F_pc, - clk, - reset_n, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3, - - // outputs: - xbrk_break, - xbrk_goto0, - xbrk_goto1, - xbrk_traceoff, - xbrk_traceon, - xbrk_trigout - ) -; - - output xbrk_break; - output xbrk_goto0; - output xbrk_goto1; - output xbrk_traceoff; - output xbrk_traceon; - output xbrk_trigout; - input D_valid; - input E_valid; - input [ 16: 0] F_pc; - input clk; - input reset_n; - input trigger_state_0; - input trigger_state_1; - input [ 7: 0] xbrk_ctrl0; - input [ 7: 0] xbrk_ctrl1; - input [ 7: 0] xbrk_ctrl2; - input [ 7: 0] xbrk_ctrl3; - - wire D_cpu_addr_en; - wire E_cpu_addr_en; - reg E_xbrk_goto0; - reg E_xbrk_goto1; - reg E_xbrk_traceoff; - reg E_xbrk_traceon; - reg E_xbrk_trigout; - wire [ 18: 0] cpu_i_address; - wire xbrk0_armed; - wire xbrk0_break_hit; - wire xbrk0_goto0_hit; - wire xbrk0_goto1_hit; - wire xbrk0_toff_hit; - wire xbrk0_ton_hit; - wire xbrk0_tout_hit; - wire xbrk1_armed; - wire xbrk1_break_hit; - wire xbrk1_goto0_hit; - wire xbrk1_goto1_hit; - wire xbrk1_toff_hit; - wire xbrk1_ton_hit; - wire xbrk1_tout_hit; - wire xbrk2_armed; - wire xbrk2_break_hit; - wire xbrk2_goto0_hit; - wire xbrk2_goto1_hit; - wire xbrk2_toff_hit; - wire xbrk2_ton_hit; - wire xbrk2_tout_hit; - wire xbrk3_armed; - wire xbrk3_break_hit; - wire xbrk3_goto0_hit; - wire xbrk3_goto1_hit; - wire xbrk3_toff_hit; - wire xbrk3_ton_hit; - wire xbrk3_tout_hit; - reg xbrk_break; - wire xbrk_break_hit; - wire xbrk_goto0; - wire xbrk_goto0_hit; - wire xbrk_goto1; - wire xbrk_goto1_hit; - wire xbrk_toff_hit; - wire xbrk_ton_hit; - wire xbrk_tout_hit; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - assign cpu_i_address = {F_pc, 2'b00}; - assign D_cpu_addr_en = D_valid; - assign E_cpu_addr_en = E_valid; - assign xbrk0_break_hit = 0; - assign xbrk0_ton_hit = 0; - assign xbrk0_toff_hit = 0; - assign xbrk0_tout_hit = 0; - assign xbrk0_goto0_hit = 0; - assign xbrk0_goto1_hit = 0; - assign xbrk1_break_hit = 0; - assign xbrk1_ton_hit = 0; - assign xbrk1_toff_hit = 0; - assign xbrk1_tout_hit = 0; - assign xbrk1_goto0_hit = 0; - assign xbrk1_goto1_hit = 0; - assign xbrk2_break_hit = 0; - assign xbrk2_ton_hit = 0; - assign xbrk2_toff_hit = 0; - assign xbrk2_tout_hit = 0; - assign xbrk2_goto0_hit = 0; - assign xbrk2_goto1_hit = 0; - assign xbrk3_break_hit = 0; - assign xbrk3_ton_hit = 0; - assign xbrk3_toff_hit = 0; - assign xbrk3_tout_hit = 0; - assign xbrk3_goto0_hit = 0; - assign xbrk3_goto1_hit = 0; - assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); - assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); - assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); - assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); - assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); - assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - xbrk_break <= 0; - else if (E_cpu_addr_en) - xbrk_break <= xbrk_break_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceon <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceon <= xbrk_ton_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceoff <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceoff <= xbrk_toff_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_trigout <= 0; - else if (E_cpu_addr_en) - E_xbrk_trigout <= xbrk_tout_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto0 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto0 <= xbrk_goto0_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto1 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto1 <= xbrk_goto1_hit; - end - - - assign xbrk_traceon = 1'b0; - assign xbrk_traceoff = 1'b0; - assign xbrk_trigout = 1'b0; - assign xbrk_goto0 = 1'b0; - assign xbrk_goto1 = 1'b0; - assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || - (xbrk_ctrl0[5] & trigger_state_1); - - assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || - (xbrk_ctrl1[5] & trigger_state_1); - - assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || - (xbrk_ctrl2[5] & trigger_state_1); - - assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || - (xbrk_ctrl3[5] & trigger_state_1); - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dbrk ( - // inputs: - E_st_data, - av_ld_data_aligned_filtered, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugack, - reset_n, - - // outputs: - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dbrk_trigout - ) -; - - output [ 18: 0] cpu_d_address; - output cpu_d_read; - output [ 31: 0] cpu_d_readdata; - output cpu_d_wait; - output cpu_d_write; - output [ 31: 0] cpu_d_writedata; - output dbrk_break; - output dbrk_goto0; - output dbrk_goto1; - output dbrk_traceme; - output dbrk_traceoff; - output dbrk_traceon; - output dbrk_trigout; - input [ 31: 0] E_st_data; - input [ 31: 0] av_ld_data_aligned_filtered; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugack; - input reset_n; - - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk0_armed; - wire dbrk0_break_pulse; - wire dbrk0_goto0; - wire dbrk0_goto1; - wire dbrk0_traceme; - wire dbrk0_traceoff; - wire dbrk0_traceon; - wire dbrk0_trigout; - wire dbrk1_armed; - wire dbrk1_break_pulse; - wire dbrk1_goto0; - wire dbrk1_goto1; - wire dbrk1_traceme; - wire dbrk1_traceoff; - wire dbrk1_traceon; - wire dbrk1_trigout; - wire dbrk2_armed; - wire dbrk2_break_pulse; - wire dbrk2_goto0; - wire dbrk2_goto1; - wire dbrk2_traceme; - wire dbrk2_traceoff; - wire dbrk2_traceon; - wire dbrk2_trigout; - wire dbrk3_armed; - wire dbrk3_break_pulse; - wire dbrk3_goto0; - wire dbrk3_goto1; - wire dbrk3_traceme; - wire dbrk3_traceoff; - wire dbrk3_traceon; - wire dbrk3_trigout; - reg dbrk_break; - reg dbrk_break_pulse; - wire [ 31: 0] dbrk_data; - reg dbrk_goto0; - reg dbrk_goto1; - reg dbrk_traceme; - reg dbrk_traceoff; - reg dbrk_traceon; - reg dbrk_trigout; - assign cpu_d_address = d_address; - assign cpu_d_readdata = av_ld_data_aligned_filtered; - assign cpu_d_read = d_read; - assign cpu_d_writedata = E_st_data; - assign cpu_d_write = d_write; - assign cpu_d_wait = d_waitrequest; - assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - dbrk_break <= 0; - else - dbrk_break <= dbrk_break ? ~debugack - : dbrk_break_pulse; - - end - - - assign dbrk0_armed = 1'b0; - assign dbrk0_trigout = 1'b0; - assign dbrk0_break_pulse = 1'b0; - assign dbrk0_traceoff = 1'b0; - assign dbrk0_traceon = 1'b0; - assign dbrk0_traceme = 1'b0; - assign dbrk0_goto0 = 1'b0; - assign dbrk0_goto1 = 1'b0; - assign dbrk1_armed = 1'b0; - assign dbrk1_trigout = 1'b0; - assign dbrk1_break_pulse = 1'b0; - assign dbrk1_traceoff = 1'b0; - assign dbrk1_traceon = 1'b0; - assign dbrk1_traceme = 1'b0; - assign dbrk1_goto0 = 1'b0; - assign dbrk1_goto1 = 1'b0; - assign dbrk2_armed = 1'b0; - assign dbrk2_trigout = 1'b0; - assign dbrk2_break_pulse = 1'b0; - assign dbrk2_traceoff = 1'b0; - assign dbrk2_traceon = 1'b0; - assign dbrk2_traceme = 1'b0; - assign dbrk2_goto0 = 1'b0; - assign dbrk2_goto1 = 1'b0; - assign dbrk3_armed = 1'b0; - assign dbrk3_trigout = 1'b0; - assign dbrk3_break_pulse = 1'b0; - assign dbrk3_traceoff = 1'b0; - assign dbrk3_traceon = 1'b0; - assign dbrk3_traceme = 1'b0; - assign dbrk3_goto0 = 1'b0; - assign dbrk3_goto1 = 1'b0; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - dbrk_trigout <= 0; - dbrk_break_pulse <= 0; - dbrk_traceoff <= 0; - dbrk_traceon <= 0; - dbrk_traceme <= 0; - dbrk_goto0 <= 0; - dbrk_goto1 <= 0; - end - else - begin - dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; - dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; - dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; - dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; - dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; - dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; - dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_itrace ( - // inputs: - clk, - dbrk_traceoff, - dbrk_traceon, - jdo, - jrst_n, - take_action_tracectrl, - trc_enb, - xbrk_traceoff, - xbrk_traceon, - xbrk_wrap_traceoff, - - // outputs: - dct_buffer, - dct_count, - itm, - trc_ctrl, - trc_on - ) -; - - output [ 29: 0] dct_buffer; - output [ 3: 0] dct_count; - output [ 35: 0] itm; - output [ 15: 0] trc_ctrl; - output trc_on; - input clk; - input dbrk_traceoff; - input dbrk_traceon; - input [ 15: 0] jdo; - input jrst_n; - input take_action_tracectrl; - input trc_enb; - input xbrk_traceoff; - input xbrk_traceon; - input xbrk_wrap_traceoff; - - wire curr_pid; - reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] dct_code; - reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire dct_is_taken; - wire [ 31: 0] excaddr; - wire instr_retired; - wire is_advanced_exception; - wire is_cond_dct; - wire is_dct; - wire is_exception_no_break; - wire is_fast_tlb_miss_exception; - wire is_idct; - reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire not_in_debug_mode; - reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_dct_outcome_in_sync; - wire record_itrace; - wire [ 31: 0] retired_pcb; - reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] sync_code; - wire [ 6: 0] sync_interval; - wire sync_pending; - reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 6: 0] sync_timer_next; - reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire [ 15: 0] trc_ctrl; - reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire trc_on; - assign is_cond_dct = 1'b0; - assign is_dct = 1'b0; - assign dct_is_taken = 1'b0; - assign is_idct = 1'b0; - assign retired_pcb = 32'b0; - assign not_in_debug_mode = 1'b0; - assign instr_retired = 1'b0; - assign is_advanced_exception = 1'b0; - assign is_exception_no_break = 1'b0; - assign is_fast_tlb_miss_exception = 1'b0; - assign curr_pid = 1'b0; - assign excaddr = 32'b0; - assign sync_code = trc_ctrl[3 : 2]; - assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; - assign sync_pending = sync_timer == 0; - assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; - assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); - assign record_itrace = trc_on & trc_ctrl[4]; - assign dct_code = {is_cond_dct, dct_is_taken}; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - trc_clear <= 0; - else - trc_clear <= ~trc_enb & - take_action_tracectrl & jdo[4]; - - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else if (trc_clear || (!0 && !0)) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else - begin - if (!prev_pid_valid) - begin - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if (instr_retired | is_advanced_exception) - begin - if (~record_itrace) - pending_frametype <= 4'b1010; - else if (is_exception_no_break) - begin - pending_frametype <= 4'b0010; - pending_excaddr <= excaddr; - if (is_fast_tlb_miss_exception) - pending_exctype <= 1'b1; - else - pending_exctype <= 1'b0; - end - else if (is_idct) - pending_frametype <= 4'b1001; - else if (record_dct_outcome_in_sync) - pending_frametype <= 4'b1000; - else if (!is_dct & snapped_pid) - begin - pending_frametype <= 4'b0011; - pending_curr_pid <= snapped_curr_pid; - pending_prev_pid <= snapped_prev_pid; - snapped_pid <= 0; - end - else - pending_frametype <= 4'b0000; - if ((dct_count != 0) & - (~record_itrace | - is_exception_no_break | - is_idct | - record_dct_outcome_in_sync | - (!is_dct & snapped_pid))) - begin - itm <= {4'b0001, dct_buffer, 2'b00}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - begin - if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) - begin - dct_buffer <= {dct_code, dct_buffer[29 : 2]}; - dct_count <= dct_count + 1; - end - if (record_itrace & (pending_frametype == 4'b0010)) - itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; - else if (record_itrace & ( - (pending_frametype == 4'b1000) | - (pending_frametype == 4'b1010) | - (pending_frametype == 4'b1001))) - begin - itm <= {pending_frametype, retired_pcb}; - sync_timer <= sync_interval; - if (0 & - ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & - !snapped_pid & prev_pid_valid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - end - end - else if (record_itrace & - 0 & (pending_frametype == 4'b0011)) - itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; - else if (record_itrace & is_dct) - begin - if (dct_count == 4'd15) - begin - itm <= {4'b0001, dct_code, dct_buffer}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - itm <= 4'b0000; - end - else - itm <= {4'b0000, 32'b0}; - end - end - else - itm <= {4'b0000, 32'b0}; - end - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_ctrl_reg[0] <= 1'b0; - trc_ctrl_reg[1] <= 1'b0; - trc_ctrl_reg[3 : 2] <= 2'b00; - trc_ctrl_reg[4] <= 1'b0; - trc_ctrl_reg[7 : 5] <= 3'b000; - trc_ctrl_reg[8] <= 0; - trc_ctrl_reg[9] <= 1'b0; - trc_ctrl_reg[10] <= 1'b0; - end - else if (take_action_tracectrl) - begin - trc_ctrl_reg[0] <= jdo[5]; - trc_ctrl_reg[1] <= jdo[6]; - trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; - trc_ctrl_reg[4] <= jdo[9]; - trc_ctrl_reg[9] <= jdo[14]; - trc_ctrl_reg[10] <= jdo[2]; - if (0) - trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; - if (0 & 0) - trc_ctrl_reg[8] <= jdo[13]; - end - else if (xbrk_wrap_traceoff) - begin - trc_ctrl_reg[1] <= 0; - trc_ctrl_reg[0] <= 0; - end - else if (dbrk_traceoff | xbrk_traceoff) - trc_ctrl_reg[1] <= 0; - else if (trc_ctrl_reg[0] & - (dbrk_traceon | xbrk_traceon)) - trc_ctrl_reg[1] <= 1; - end - - - assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; - assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_td_mode ( - // inputs: - ctrl, - - // outputs: - td_mode - ) -; - - output [ 3: 0] td_mode; - input [ 8: 0] ctrl; - - wire [ 2: 0] ctrl_bits_for_mux; - reg [ 3: 0] td_mode; - assign ctrl_bits_for_mux = ctrl[7 : 5]; - always @(ctrl_bits_for_mux) - begin - case (ctrl_bits_for_mux) - - 3'b000: begin - td_mode = 4'b0000; - end // 3'b000 - - 3'b001: begin - td_mode = 4'b1000; - end // 3'b001 - - 3'b010: begin - td_mode = 4'b0100; - end // 3'b010 - - 3'b011: begin - td_mode = 4'b1100; - end // 3'b011 - - 3'b100: begin - td_mode = 4'b0010; - end // 3'b100 - - 3'b101: begin - td_mode = 4'b1010; - end // 3'b101 - - 3'b110: begin - td_mode = 4'b0101; - end // 3'b110 - - 3'b111: begin - td_mode = 4'b1111; - end // 3'b111 - - endcase // ctrl_bits_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dtrace ( - // inputs: - clk, - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - jrst_n, - trc_ctrl, - - // outputs: - atm, - dtm - ) -; - - output [ 35: 0] atm; - output [ 35: 0] dtm; - input clk; - input [ 18: 0] cpu_d_address; - input cpu_d_read; - input [ 31: 0] cpu_d_readdata; - input cpu_d_wait; - input cpu_d_write; - input [ 31: 0] cpu_d_writedata; - input jrst_n; - input [ 15: 0] trc_ctrl; - - reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 31: 0] cpu_d_address_0_padded; - wire [ 31: 0] cpu_d_readdata_0_padded; - wire [ 31: 0] cpu_d_writedata_0_padded; - reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_load_addr; - wire record_load_data; - wire record_store_addr; - wire record_store_data; - wire [ 3: 0] td_mode_trc_ctrl; - assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; - assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; - assign cpu_d_address_0_padded = cpu_d_address | 32'b0; - //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance - nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode - ( - .ctrl (trc_ctrl[8 : 0]), - .td_mode (td_mode_trc_ctrl) - ); - - assign {record_load_addr, record_store_addr, - record_load_data, record_store_data} = td_mode_trc_ctrl; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - atm <= 0; - dtm <= 0; - end - else if (0) - begin - if (cpu_d_write & ~cpu_d_wait & record_store_addr) - atm <= {4'b0101, cpu_d_address_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_addr) - atm <= {4'b0100, cpu_d_address_0_padded}; - else - atm <= {4'b0000, cpu_d_address_0_padded}; - if (cpu_d_write & ~cpu_d_wait & record_store_data) - dtm <= {4'b0111, cpu_d_writedata_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_data) - dtm <= {4'b0110, cpu_d_readdata_0_padded}; - else - dtm <= {4'b0000, cpu_d_readdata_0_padded}; - end - else - begin - atm <= 0; - dtm <= 0; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_compute_tm_count ( - // inputs: - atm_valid, - dtm_valid, - itm_valid, - - // outputs: - compute_tm_count - ) -; - - output [ 1: 0] compute_tm_count; - input atm_valid; - input dtm_valid; - input itm_valid; - - reg [ 1: 0] compute_tm_count; - wire [ 2: 0] switch_for_mux; - assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; - always @(switch_for_mux) - begin - case (switch_for_mux) - - 3'b000: begin - compute_tm_count = 0; - end // 3'b000 - - 3'b001: begin - compute_tm_count = 1; - end // 3'b001 - - 3'b010: begin - compute_tm_count = 1; - end // 3'b010 - - 3'b011: begin - compute_tm_count = 2; - end // 3'b011 - - 3'b100: begin - compute_tm_count = 1; - end // 3'b100 - - 3'b101: begin - compute_tm_count = 2; - end // 3'b101 - - 3'b110: begin - compute_tm_count = 2; - end // 3'b110 - - 3'b111: begin - compute_tm_count = 3; - end // 3'b111 - - endcase // switch_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifowp_inc ( - // inputs: - free2, - free3, - tm_count, - - // outputs: - fifowp_inc - ) -; - - output [ 3: 0] fifowp_inc; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 3: 0] fifowp_inc; - always @(free2 or free3 or tm_count) - begin - if (free3 & (tm_count == 3)) - fifowp_inc = 3; - else if (free2 & (tm_count >= 2)) - fifowp_inc = 2; - else if (tm_count >= 1) - fifowp_inc = 1; - else - fifowp_inc = 0; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifocount_inc ( - // inputs: - empty, - free2, - free3, - tm_count, - - // outputs: - fifocount_inc - ) -; - - output [ 4: 0] fifocount_inc; - input empty; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 4: 0] fifocount_inc; - always @(empty or free2 or free3 or tm_count) - begin - if (empty) - fifocount_inc = tm_count[1 : 0]; - else if (free3 & (tm_count == 3)) - fifocount_inc = 2; - else if (free2 & (tm_count >= 2)) - fifocount_inc = 1; - else if (tm_count >= 1) - fifocount_inc = 0; - else - fifocount_inc = {5{1'b1}}; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifo ( - // inputs: - atm, - clk, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dct_buffer, - dct_count, - dtm, - itm, - jrst_n, - reset_n, - test_ending, - test_has_ended, - trc_on, - - // outputs: - tw - ) -; - - output [ 35: 0] tw; - input [ 35: 0] atm; - input clk; - input dbrk_traceme; - input dbrk_traceoff; - input dbrk_traceon; - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input [ 35: 0] dtm; - input [ 35: 0] itm; - input jrst_n; - input reset_n; - input test_ending; - input test_has_ended; - input trc_on; - - wire atm_valid; - wire [ 1: 0] compute_tm_count_tm_count; - wire dtm_valid; - wire empty; - reg [ 35: 0] fifo_0; - wire fifo_0_enable; - wire [ 35: 0] fifo_0_mux; - reg [ 35: 0] fifo_1; - reg [ 35: 0] fifo_10; - wire fifo_10_enable; - wire [ 35: 0] fifo_10_mux; - reg [ 35: 0] fifo_11; - wire fifo_11_enable; - wire [ 35: 0] fifo_11_mux; - reg [ 35: 0] fifo_12; - wire fifo_12_enable; - wire [ 35: 0] fifo_12_mux; - reg [ 35: 0] fifo_13; - wire fifo_13_enable; - wire [ 35: 0] fifo_13_mux; - reg [ 35: 0] fifo_14; - wire fifo_14_enable; - wire [ 35: 0] fifo_14_mux; - reg [ 35: 0] fifo_15; - wire fifo_15_enable; - wire [ 35: 0] fifo_15_mux; - wire fifo_1_enable; - wire [ 35: 0] fifo_1_mux; - reg [ 35: 0] fifo_2; - wire fifo_2_enable; - wire [ 35: 0] fifo_2_mux; - reg [ 35: 0] fifo_3; - wire fifo_3_enable; - wire [ 35: 0] fifo_3_mux; - reg [ 35: 0] fifo_4; - wire fifo_4_enable; - wire [ 35: 0] fifo_4_mux; - reg [ 35: 0] fifo_5; - wire fifo_5_enable; - wire [ 35: 0] fifo_5_mux; - reg [ 35: 0] fifo_6; - wire fifo_6_enable; - wire [ 35: 0] fifo_6_mux; - reg [ 35: 0] fifo_7; - wire fifo_7_enable; - wire [ 35: 0] fifo_7_mux; - reg [ 35: 0] fifo_8; - wire fifo_8_enable; - wire [ 35: 0] fifo_8_mux; - reg [ 35: 0] fifo_9; - wire fifo_9_enable; - wire [ 35: 0] fifo_9_mux; - wire [ 35: 0] fifo_read_mux; - reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 4: 0] fifocount_inc_fifocount; - wire [ 35: 0] fifohead; - reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 3: 0] fifowp1; - wire [ 3: 0] fifowp2; - wire [ 3: 0] fifowp_inc_fifowp; - wire free2; - wire free3; - wire itm_valid; - reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 35: 0] ovr_pending_atm; - wire [ 35: 0] ovr_pending_dtm; - wire [ 1: 0] tm_count; - wire tm_count_ge1; - wire tm_count_ge2; - wire tm_count_ge3; - wire trc_this; - wire [ 35: 0] tw; - assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; - assign itm_valid = |itm[35 : 32]; - assign atm_valid = |atm[35 : 32] & trc_this; - assign dtm_valid = |dtm[35 : 32] & trc_this; - assign free2 = ~fifocount[4]; - assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; - assign empty = ~|fifocount; - assign fifowp1 = fifowp + 1; - assign fifowp2 = fifowp + 2; - //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance - nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count - ( - .atm_valid (atm_valid), - .compute_tm_count (compute_tm_count_tm_count), - .dtm_valid (dtm_valid), - .itm_valid (itm_valid) - ); - - assign tm_count = compute_tm_count_tm_count; - //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp - ( - .fifowp_inc (fifowp_inc_fifowp), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount - ( - .empty (empty), - .fifocount_inc (fifocount_inc_fifocount), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance - nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench - ( - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .test_ending (test_ending), - .test_has_ended (test_has_ended) - ); - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - fiforp <= 0; - fifowp <= 0; - fifocount <= 0; - ovf_pending <= 1; - end - else - begin - fifowp <= fifowp + fifowp_inc_fifowp; - fifocount <= fifocount + fifocount_inc_fifocount; - if (~empty) - fiforp <= fiforp + 1; - if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) - ovf_pending <= 1; - else if (atm_valid | dtm_valid) - ovf_pending <= 0; - end - end - - - assign fifohead = fifo_read_mux; - assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; - assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_0 <= 0; - else if (fifo_0_enable) - fifo_0 <= fifo_0_mux; - end - - - assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : - (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_1 <= 0; - else if (fifo_1_enable) - fifo_1 <= fifo_1_mux; - end - - - assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : - (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_2 <= 0; - else if (fifo_2_enable) - fifo_2 <= fifo_2_mux; - end - - - assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : - (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_3 <= 0; - else if (fifo_3_enable) - fifo_3 <= fifo_3_mux; - end - - - assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : - (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_4 <= 0; - else if (fifo_4_enable) - fifo_4 <= fifo_4_mux; - end - - - assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : - (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_5 <= 0; - else if (fifo_5_enable) - fifo_5 <= fifo_5_mux; - end - - - assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : - (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_6 <= 0; - else if (fifo_6_enable) - fifo_6 <= fifo_6_mux; - end - - - assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : - (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_7 <= 0; - else if (fifo_7_enable) - fifo_7 <= fifo_7_mux; - end - - - assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : - (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_8 <= 0; - else if (fifo_8_enable) - fifo_8 <= fifo_8_mux; - end - - - assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : - (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_9 <= 0; - else if (fifo_9_enable) - fifo_9 <= fifo_9_mux; - end - - - assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : - (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_10 <= 0; - else if (fifo_10_enable) - fifo_10 <= fifo_10_mux; - end - - - assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : - (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_11 <= 0; - else if (fifo_11_enable) - fifo_11 <= fifo_11_mux; - end - - - assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : - (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_12 <= 0; - else if (fifo_12_enable) - fifo_12 <= fifo_12_mux; - end - - - assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : - (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_13 <= 0; - else if (fifo_13_enable) - fifo_13 <= fifo_13_mux; - end - - - assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : - (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_14 <= 0; - else if (fifo_14_enable) - fifo_14 <= fifo_14_mux; - end - - - assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : - (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_15 <= 0; - else if (fifo_15_enable) - fifo_15 <= fifo_15_mux; - end - - - assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : - (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign tm_count_ge1 = |tm_count; - assign tm_count_ge2 = tm_count[1]; - assign tm_count_ge3 = &tm_count; - assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; - assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; - assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : - (fiforp == 4'd1)? fifo_1 : - (fiforp == 4'd2)? fifo_2 : - (fiforp == 4'd3)? fifo_3 : - (fiforp == 4'd4)? fifo_4 : - (fiforp == 4'd5)? fifo_5 : - (fiforp == 4'd6)? fifo_6 : - (fiforp == 4'd7)? fifo_7 : - (fiforp == 4'd8)? fifo_8 : - (fiforp == 4'd9)? fifo_9 : - (fiforp == 4'd10)? fifo_10 : - (fiforp == 4'd11)? fifo_11 : - (fiforp == 4'd12)? fifo_12 : - (fiforp == 4'd13)? fifo_13 : - (fiforp == 4'd14)? fifo_14 : - fifo_15; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_pib ( - // inputs: - clk, - clkx2, - jrst_n, - tw, - - // outputs: - tr_clk, - tr_data - ) -; - - output tr_clk; - output [ 17: 0] tr_data; - input clk; - input clkx2; - input jrst_n; - input [ 35: 0] tw; - - wire phase; - wire tr_clk; - reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 17: 0] tr_data; - reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - assign phase = x1^x2; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - x1 <= 0; - else - x1 <= ~x1; - end - - - always @(posedge clkx2 or negedge jrst_n) - begin - if (jrst_n == 0) - begin - x2 <= 0; - tr_clk_reg <= 0; - tr_data_reg <= 0; - end - else - begin - x2 <= x1; - tr_clk_reg <= ~phase; - tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; - end - end - - - assign tr_clk = 0 ? tr_clk_reg : 0; - assign tr_data = 0 ? tr_data_reg : 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_im ( - // inputs: - clk, - jdo, - jrst_n, - reset_n, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_tracemem_a, - trc_ctrl, - tw, - - // outputs: - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_enb, - trc_im_addr, - trc_wrap, - xbrk_wrap_traceoff - ) -; - - output tracemem_on; - output [ 35: 0] tracemem_trcdata; - output tracemem_tw; - output trc_enb; - output [ 6: 0] trc_im_addr; - output trc_wrap; - output xbrk_wrap_traceoff; - input clk; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_tracectrl; - input take_action_tracemem_a; - input take_action_tracemem_b; - input take_no_action_tracemem_a; - input [ 15: 0] trc_ctrl; - input [ 35: 0] tw; - - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire trc_enb; - reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 35: 0] trc_im_data; - reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire trc_on_chip; - reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire tw_valid; - wire xbrk_wrap_traceoff; - assign trc_im_data = tw; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (!0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (take_action_tracectrl && - (jdo[4] | jdo[3])) - begin - if (jdo[4]) - trc_im_addr <= 0; - if (jdo[3]) - trc_wrap <= 0; - end - else if (trc_enb & trc_on_chip & tw_valid) - begin - trc_im_addr <= trc_im_addr+1; - if (&trc_im_addr) - trc_wrap <= 1; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trc_jtag_addr <= 0; - else if (take_action_tracemem_a || - take_no_action_tracemem_a || - take_action_tracemem_b) - trc_jtag_addr <= take_action_tracemem_a ? - jdo[35 : 19] : - trc_jtag_addr + 1; - - end - - - assign trc_enb = trc_ctrl[0]; - assign trc_on_chip = ~trc_ctrl[8]; - assign tw_valid = |trc_im_data[35 : 32]; - assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; - assign tracemem_tw = trc_wrap; - assign tracemem_on = trc_enb; - assign tracemem_trcdata = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_performance_monitors -; - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci ( - // inputs: - D_valid, - E_st_data, - E_valid, - F_pc, - address_nxt, - av_ld_data_aligned_filtered, - byteenable_nxt, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugaccess_nxt, - hbreak_enabled, - read_nxt, - reset, - reset_n, - test_ending, - test_has_ended, - write_nxt, - writedata_nxt, - - // outputs: - jtag_debug_module_debugaccess_to_roms, - oci_hbreak_req, - oci_ienable, - oci_single_step_mode, - readdata, - resetrequest, - waitrequest - ) -; - - output jtag_debug_module_debugaccess_to_roms; - output oci_hbreak_req; - output [ 31: 0] oci_ienable; - output oci_single_step_mode; - output [ 31: 0] readdata; - output resetrequest; - output waitrequest; - input D_valid; - input [ 31: 0] E_st_data; - input E_valid; - input [ 16: 0] F_pc; - input [ 8: 0] address_nxt; - input [ 31: 0] av_ld_data_aligned_filtered; - input [ 3: 0] byteenable_nxt; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugaccess_nxt; - input hbreak_enabled; - input read_nxt; - input reset; - input reset_n; - input test_ending; - input test_has_ended; - input write_nxt; - input [ 31: 0] writedata_nxt; - - wire [ 31: 0] MonDReg; - reg [ 8: 0] address; - wire [ 35: 0] atm; - wire [ 31: 0] break_readreg; - reg [ 3: 0] byteenable; - wire clkx2; - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk_break; - wire dbrk_goto0; - wire dbrk_goto1; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire dbrk_traceme; - wire dbrk_traceoff; - wire dbrk_traceon; - wire dbrk_trigout; - wire [ 29: 0] dct_buffer; - wire [ 3: 0] dct_count; - reg debugaccess; - wire debugack; - wire debugreq; - wire [ 35: 0] dtm; - wire dummy_sink; - wire [ 35: 0] itm; - wire [ 37: 0] jdo; - wire jrst_n; - wire jtag_debug_module_debugaccess_to_roms; - wire monitor_error; - wire monitor_go; - wire monitor_ready; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire [ 31: 0] oci_reg_readdata; - wire oci_single_step_mode; - wire [ 31: 0] ociram_readdata; - wire ocireg_ers; - wire ocireg_mrs; - reg read; - reg [ 31: 0] readdata; - wire resetlatch; - wire resetrequest; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_ocireg; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire tr_clk; - wire [ 17: 0] tr_data; - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire [ 15: 0] trc_ctrl; - wire trc_enb; - wire [ 6: 0] trc_im_addr; - wire trc_on; - wire trc_wrap; - wire trigbrktype; - wire trigger_state_0; - wire trigger_state_1; - wire trigout; - wire [ 35: 0] tw; - wire waitrequest; - reg write; - reg [ 31: 0] writedata; - wire xbrk_break; - wire [ 7: 0] xbrk_ctrl0; - wire [ 7: 0] xbrk_ctrl1; - wire [ 7: 0] xbrk_ctrl2; - wire [ 7: 0] xbrk_ctrl3; - wire xbrk_goto0; - wire xbrk_goto1; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - wire xbrk_wrap_traceoff; - nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug - ( - .clk (clk), - .dbrk_break (dbrk_break), - .debugack (debugack), - .debugreq (debugreq), - .hbreak_enabled (hbreak_enabled), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_hbreak_req (oci_hbreak_req), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset (reset), - .resetlatch (resetlatch), - .resetrequest (resetrequest), - .st_ready_test_idle (st_ready_test_idle), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocireg (take_action_ocireg), - .xbrk_break (xbrk_break) - ); - - nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem - ( - .MonDReg (MonDReg), - .address (address), - .byteenable (byteenable), - .clk (clk), - .debugaccess (debugaccess), - .jdo (jdo), - .jrst_n (jrst_n), - .ociram_readdata (ociram_readdata), - .read (read), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .waitrequest (waitrequest), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg - ( - .address (address), - .clk (clk), - .debugaccess (debugaccess), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_ienable (oci_ienable), - .oci_reg_readdata (oci_reg_readdata), - .oci_single_step_mode (oci_single_step_mode), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset_n (reset_n), - .take_action_ocireg (take_action_ocireg), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break - ( - .break_readreg (break_readreg), - .clk (clk), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .trigbrktype (trigbrktype), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1) - ); - - nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk - ( - .D_valid (D_valid), - .E_valid (E_valid), - .F_pc (F_pc), - .clk (clk), - .reset_n (reset_n), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_break (xbrk_break), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_trigout (xbrk_trigout) - ); - - nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk - ( - .E_st_data (E_st_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dbrk_trigout (dbrk_trigout), - .debugack (debugack), - .reset_n (reset_n) - ); - - nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace - ( - .clk (clk), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .itm (itm), - .jdo (jdo), - .jrst_n (jrst_n), - .take_action_tracectrl (take_action_tracectrl), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_on (trc_on), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace - ( - .atm (atm), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .dtm (dtm), - .jrst_n (jrst_n), - .trc_ctrl (trc_ctrl) - ); - - nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo - ( - .atm (atm), - .clk (clk), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .dtm (dtm), - .itm (itm), - .jrst_n (jrst_n), - .reset_n (reset_n), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .trc_on (trc_on), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib - ( - .clk (clk), - .clkx2 (clkx2), - .jrst_n (jrst_n), - .tr_clk (tr_clk), - .tr_data (tr_data), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im - ( - .clk (clk), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_im_addr (trc_im_addr), - .trc_wrap (trc_wrap), - .tw (tw), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - assign trigout = dbrk_trigout | xbrk_trigout; - assign jtag_debug_module_debugaccess_to_roms = debugack; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - address <= 0; - else - address <= address_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - byteenable <= 0; - else - byteenable <= byteenable_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - writedata <= 0; - else - writedata <= writedata_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - debugaccess <= 0; - else - debugaccess <= debugaccess_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - read <= 0; - else - read <= read ? waitrequest : read_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - write <= 0; - else - write <= write ? waitrequest : write_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - readdata <= 0; - else - readdata <= address[8] ? oci_reg_readdata : ociram_readdata; - end - - - nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .clk (clk), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .st_ready_test_idle (st_ready_test_idle), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1) - ); - - //dummy sink, which is an e_mux - assign dummy_sink = tr_clk | - tr_data | - trigout | - debugack; - - assign debugreq = 0; - assign clkx2 = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor ( - // inputs: - clk, - d_irq, - d_readdata, - d_waitrequest, - i_readdata, - i_waitrequest, - jtag_debug_module_address, - jtag_debug_module_byteenable, - jtag_debug_module_debugaccess, - jtag_debug_module_read, - jtag_debug_module_write, - jtag_debug_module_writedata, - reset_n, - - // outputs: - d_address, - d_byteenable, - d_read, - d_write, - d_writedata, - i_address, - i_read, - jtag_debug_module_debugaccess_to_roms, - jtag_debug_module_readdata, - jtag_debug_module_resetrequest, - jtag_debug_module_waitrequest, - no_ci_readra - ) -; - - output [ 18: 0] d_address; - output [ 3: 0] d_byteenable; - output d_read; - output d_write; - output [ 31: 0] d_writedata; - output [ 18: 0] i_address; - output i_read; - output jtag_debug_module_debugaccess_to_roms; - output [ 31: 0] jtag_debug_module_readdata; - output jtag_debug_module_resetrequest; - output jtag_debug_module_waitrequest; - output no_ci_readra; - input clk; - input [ 31: 0] d_irq; - input [ 31: 0] d_readdata; - input d_waitrequest; - input [ 31: 0] i_readdata; - input i_waitrequest; - input [ 8: 0] jtag_debug_module_address; - input [ 3: 0] jtag_debug_module_byteenable; - input jtag_debug_module_debugaccess; - input jtag_debug_module_read; - input jtag_debug_module_write; - input [ 31: 0] jtag_debug_module_writedata; - input reset_n; - - wire [ 1: 0] D_compare_op; - wire D_ctrl_alu_force_xor; - wire D_ctrl_alu_signed_comparison; - wire D_ctrl_alu_subtract; - wire D_ctrl_b_is_dst; - wire D_ctrl_br; - wire D_ctrl_br_cmp; - wire D_ctrl_br_uncond; - wire D_ctrl_break; - wire D_ctrl_crst; - wire D_ctrl_custom; - wire D_ctrl_custom_multi; - wire D_ctrl_exception; - wire D_ctrl_force_src2_zero; - wire D_ctrl_hi_imm16; - wire D_ctrl_ignore_dst; - wire D_ctrl_implicit_dst_eretaddr; - wire D_ctrl_implicit_dst_retaddr; - wire D_ctrl_jmp_direct; - wire D_ctrl_jmp_indirect; - wire D_ctrl_ld; - wire D_ctrl_ld_io; - wire D_ctrl_ld_non_io; - wire D_ctrl_ld_signed; - wire D_ctrl_logic; - wire D_ctrl_rdctl_inst; - wire D_ctrl_retaddr; - wire D_ctrl_rot_right; - wire D_ctrl_shift_logical; - wire D_ctrl_shift_right_arith; - wire D_ctrl_shift_rot; - wire D_ctrl_shift_rot_right; - wire D_ctrl_src2_choose_imm; - wire D_ctrl_st; - wire D_ctrl_uncond_cti_non_br; - wire D_ctrl_unsigned_lo_imm16; - wire D_ctrl_wrctl_inst; - wire [ 4: 0] D_dst_regnum; - wire [ 55: 0] D_inst; - reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 4: 0] D_iw_a; - wire [ 4: 0] D_iw_b; - wire [ 4: 0] D_iw_c; - wire [ 2: 0] D_iw_control_regnum; - wire [ 7: 0] D_iw_custom_n; - wire D_iw_custom_readra; - wire D_iw_custom_readrb; - wire D_iw_custom_writerc; - wire [ 15: 0] D_iw_imm16; - wire [ 25: 0] D_iw_imm26; - wire [ 4: 0] D_iw_imm5; - wire [ 1: 0] D_iw_memsz; - wire [ 5: 0] D_iw_op; - wire [ 5: 0] D_iw_opx; - wire [ 4: 0] D_iw_shift_imm5; - wire [ 4: 0] D_iw_trap_break_imm5; - wire [ 16: 0] D_jmp_direct_target_waddr; - wire [ 1: 0] D_logic_op; - wire [ 1: 0] D_logic_op_raw; - wire D_mem16; - wire D_mem32; - wire D_mem8; - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - reg D_valid; - wire [ 55: 0] D_vinst; - wire D_wr_dst_reg; - wire [ 31: 0] E_alu_result; - reg E_alu_sub; - wire [ 32: 0] E_arith_result; - wire [ 31: 0] E_arith_src1; - wire [ 31: 0] E_arith_src2; - wire E_ci_multi_stall; - wire [ 31: 0] E_ci_result; - wire E_cmp_result; - wire [ 31: 0] E_control_rd_data; - wire E_eq; - reg E_invert_arith_src_msb; - wire E_ld_stall; - wire [ 31: 0] E_logic_result; - wire E_logic_result_is_0; - wire E_lt; - wire [ 18: 0] E_mem_baddr; - wire [ 3: 0] E_mem_byte_en; - reg E_new_inst; - reg [ 4: 0] E_shift_rot_cnt; - wire [ 4: 0] E_shift_rot_cnt_nxt; - wire E_shift_rot_done; - wire E_shift_rot_fill_bit; - reg [ 31: 0] E_shift_rot_result; - wire [ 31: 0] E_shift_rot_result_nxt; - wire E_shift_rot_stall; - reg [ 31: 0] E_src1; - reg [ 31: 0] E_src2; - wire [ 31: 0] E_st_data; - wire E_st_stall; - wire E_stall; - reg E_valid; - wire [ 55: 0] E_vinst; - wire E_wrctl_bstatus; - wire E_wrctl_estatus; - wire E_wrctl_ienable; - wire E_wrctl_status; - wire [ 31: 0] F_av_iw; - wire [ 4: 0] F_av_iw_a; - wire [ 4: 0] F_av_iw_b; - wire [ 4: 0] F_av_iw_c; - wire [ 2: 0] F_av_iw_control_regnum; - wire [ 7: 0] F_av_iw_custom_n; - wire F_av_iw_custom_readra; - wire F_av_iw_custom_readrb; - wire F_av_iw_custom_writerc; - wire [ 15: 0] F_av_iw_imm16; - wire [ 25: 0] F_av_iw_imm26; - wire [ 4: 0] F_av_iw_imm5; - wire [ 1: 0] F_av_iw_memsz; - wire [ 5: 0] F_av_iw_op; - wire [ 5: 0] F_av_iw_opx; - wire [ 4: 0] F_av_iw_shift_imm5; - wire [ 4: 0] F_av_iw_trap_break_imm5; - wire F_av_mem16; - wire F_av_mem32; - wire F_av_mem8; - wire [ 55: 0] F_inst; - wire [ 31: 0] F_iw; - wire [ 4: 0] F_iw_a; - wire [ 4: 0] F_iw_b; - wire [ 4: 0] F_iw_c; - wire [ 2: 0] F_iw_control_regnum; - wire [ 7: 0] F_iw_custom_n; - wire F_iw_custom_readra; - wire F_iw_custom_readrb; - wire F_iw_custom_writerc; - wire [ 15: 0] F_iw_imm16; - wire [ 25: 0] F_iw_imm26; - wire [ 4: 0] F_iw_imm5; - wire [ 1: 0] F_iw_memsz; - wire [ 5: 0] F_iw_op; - wire [ 5: 0] F_iw_opx; - wire [ 4: 0] F_iw_shift_imm5; - wire [ 4: 0] F_iw_trap_break_imm5; - wire F_mem16; - wire F_mem32; - wire F_mem8; - wire F_op_add; - wire F_op_addi; - wire F_op_and; - wire F_op_andhi; - wire F_op_andi; - wire F_op_beq; - wire F_op_bge; - wire F_op_bgeu; - wire F_op_blt; - wire F_op_bltu; - wire F_op_bne; - wire F_op_br; - wire F_op_break; - wire F_op_bret; - wire F_op_call; - wire F_op_callr; - wire F_op_cmpeq; - wire F_op_cmpeqi; - wire F_op_cmpge; - wire F_op_cmpgei; - wire F_op_cmpgeu; - wire F_op_cmpgeui; - wire F_op_cmplt; - wire F_op_cmplti; - wire F_op_cmpltu; - wire F_op_cmpltui; - wire F_op_cmpne; - wire F_op_cmpnei; - wire F_op_crst; - wire F_op_custom; - wire F_op_div; - wire F_op_divu; - wire F_op_eret; - wire F_op_flushd; - wire F_op_flushda; - wire F_op_flushi; - wire F_op_flushp; - wire F_op_hbreak; - wire F_op_initd; - wire F_op_initda; - wire F_op_initi; - wire F_op_intr; - wire F_op_jmp; - wire F_op_jmpi; - wire F_op_ldb; - wire F_op_ldbio; - wire F_op_ldbu; - wire F_op_ldbuio; - wire F_op_ldh; - wire F_op_ldhio; - wire F_op_ldhu; - wire F_op_ldhuio; - wire F_op_ldl; - wire F_op_ldw; - wire F_op_ldwio; - wire F_op_mul; - wire F_op_muli; - wire F_op_mulxss; - wire F_op_mulxsu; - wire F_op_mulxuu; - wire F_op_nextpc; - wire F_op_nor; - wire F_op_opx; - wire F_op_or; - wire F_op_orhi; - wire F_op_ori; - wire F_op_rdctl; - wire F_op_rdprs; - wire F_op_ret; - wire F_op_rol; - wire F_op_roli; - wire F_op_ror; - wire F_op_rsv02; - wire F_op_rsv09; - wire F_op_rsv10; - wire F_op_rsv17; - wire F_op_rsv18; - wire F_op_rsv25; - wire F_op_rsv26; - wire F_op_rsv33; - wire F_op_rsv34; - wire F_op_rsv41; - wire F_op_rsv42; - wire F_op_rsv49; - wire F_op_rsv57; - wire F_op_rsv61; - wire F_op_rsv62; - wire F_op_rsv63; - wire F_op_rsvx00; - wire F_op_rsvx10; - wire F_op_rsvx15; - wire F_op_rsvx17; - wire F_op_rsvx21; - wire F_op_rsvx25; - wire F_op_rsvx33; - wire F_op_rsvx34; - wire F_op_rsvx35; - wire F_op_rsvx42; - wire F_op_rsvx43; - wire F_op_rsvx44; - wire F_op_rsvx47; - wire F_op_rsvx50; - wire F_op_rsvx51; - wire F_op_rsvx55; - wire F_op_rsvx56; - wire F_op_rsvx60; - wire F_op_rsvx63; - wire F_op_sll; - wire F_op_slli; - wire F_op_sra; - wire F_op_srai; - wire F_op_srl; - wire F_op_srli; - wire F_op_stb; - wire F_op_stbio; - wire F_op_stc; - wire F_op_sth; - wire F_op_sthio; - wire F_op_stw; - wire F_op_stwio; - wire F_op_sub; - wire F_op_sync; - wire F_op_trap; - wire F_op_wrctl; - wire F_op_wrprs; - wire F_op_xor; - wire F_op_xorhi; - wire F_op_xori; - reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire F_pc_en; - wire [ 16: 0] F_pc_no_crst_nxt; - wire [ 16: 0] F_pc_nxt; - wire [ 16: 0] F_pc_plus_one; - wire [ 1: 0] F_pc_sel_nxt; - wire [ 18: 0] F_pcb; - wire [ 18: 0] F_pcb_nxt; - wire [ 18: 0] F_pcb_plus_four; - wire F_valid; - wire [ 55: 0] F_vinst; - reg [ 1: 0] R_compare_op; - reg R_ctrl_alu_force_xor; - wire R_ctrl_alu_force_xor_nxt; - reg R_ctrl_alu_signed_comparison; - wire R_ctrl_alu_signed_comparison_nxt; - reg R_ctrl_alu_subtract; - wire R_ctrl_alu_subtract_nxt; - reg R_ctrl_b_is_dst; - wire R_ctrl_b_is_dst_nxt; - reg R_ctrl_br; - reg R_ctrl_br_cmp; - wire R_ctrl_br_cmp_nxt; - wire R_ctrl_br_nxt; - reg R_ctrl_br_uncond; - wire R_ctrl_br_uncond_nxt; - reg R_ctrl_break; - wire R_ctrl_break_nxt; - reg R_ctrl_crst; - wire R_ctrl_crst_nxt; - reg R_ctrl_custom; - reg R_ctrl_custom_multi; - wire R_ctrl_custom_multi_nxt; - wire R_ctrl_custom_nxt; - reg R_ctrl_exception; - wire R_ctrl_exception_nxt; - reg R_ctrl_force_src2_zero; - wire R_ctrl_force_src2_zero_nxt; - reg R_ctrl_hi_imm16; - wire R_ctrl_hi_imm16_nxt; - reg R_ctrl_ignore_dst; - wire R_ctrl_ignore_dst_nxt; - reg R_ctrl_implicit_dst_eretaddr; - wire R_ctrl_implicit_dst_eretaddr_nxt; - reg R_ctrl_implicit_dst_retaddr; - wire R_ctrl_implicit_dst_retaddr_nxt; - reg R_ctrl_jmp_direct; - wire R_ctrl_jmp_direct_nxt; - reg R_ctrl_jmp_indirect; - wire R_ctrl_jmp_indirect_nxt; - reg R_ctrl_ld; - reg R_ctrl_ld_io; - wire R_ctrl_ld_io_nxt; - reg R_ctrl_ld_non_io; - wire R_ctrl_ld_non_io_nxt; - wire R_ctrl_ld_nxt; - reg R_ctrl_ld_signed; - wire R_ctrl_ld_signed_nxt; - reg R_ctrl_logic; - wire R_ctrl_logic_nxt; - reg R_ctrl_rdctl_inst; - wire R_ctrl_rdctl_inst_nxt; - reg R_ctrl_retaddr; - wire R_ctrl_retaddr_nxt; - reg R_ctrl_rot_right; - wire R_ctrl_rot_right_nxt; - reg R_ctrl_shift_logical; - wire R_ctrl_shift_logical_nxt; - reg R_ctrl_shift_right_arith; - wire R_ctrl_shift_right_arith_nxt; - reg R_ctrl_shift_rot; - wire R_ctrl_shift_rot_nxt; - reg R_ctrl_shift_rot_right; - wire R_ctrl_shift_rot_right_nxt; - reg R_ctrl_src2_choose_imm; - wire R_ctrl_src2_choose_imm_nxt; - reg R_ctrl_st; - wire R_ctrl_st_nxt; - reg R_ctrl_uncond_cti_non_br; - wire R_ctrl_uncond_cti_non_br_nxt; - reg R_ctrl_unsigned_lo_imm16; - wire R_ctrl_unsigned_lo_imm16_nxt; - reg R_ctrl_wrctl_inst; - wire R_ctrl_wrctl_inst_nxt; - reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire R_en; - reg [ 1: 0] R_logic_op; - wire [ 31: 0] R_rf_a; - wire [ 31: 0] R_rf_b; - wire [ 31: 0] R_src1; - wire [ 31: 0] R_src2; - wire [ 15: 0] R_src2_hi; - wire [ 15: 0] R_src2_lo; - reg R_src2_use_imm; - wire [ 7: 0] R_stb_data; - wire [ 15: 0] R_sth_data; - reg R_valid; - wire [ 55: 0] R_vinst; - reg R_wr_dst_reg; - reg [ 31: 0] W_alu_result; - wire W_br_taken; - reg W_bstatus_reg; - wire W_bstatus_reg_inst_nxt; - wire W_bstatus_reg_nxt; - reg W_cmp_result; - reg [ 31: 0] W_control_rd_data; - reg W_estatus_reg; - wire W_estatus_reg_inst_nxt; - wire W_estatus_reg_nxt; - reg [ 31: 0] W_ienable_reg; - wire [ 31: 0] W_ienable_reg_nxt; - reg [ 31: 0] W_ipending_reg; - wire [ 31: 0] W_ipending_reg_nxt; - wire [ 18: 0] W_mem_baddr; - wire [ 31: 0] W_rf_wr_data; - wire W_rf_wren; - wire W_status_reg; - reg W_status_reg_pie; - wire W_status_reg_pie_inst_nxt; - wire W_status_reg_pie_nxt; - reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 55: 0] W_vinst; - wire [ 31: 0] W_wr_data; - wire [ 31: 0] W_wr_data_non_zero; - wire av_fill_bit; - reg [ 1: 0] av_ld_align_cycle; - wire [ 1: 0] av_ld_align_cycle_nxt; - wire av_ld_align_one_more_cycle; - reg av_ld_aligning_data; - wire av_ld_aligning_data_nxt; - reg [ 7: 0] av_ld_byte0_data; - wire [ 7: 0] av_ld_byte0_data_nxt; - reg [ 7: 0] av_ld_byte1_data; - wire av_ld_byte1_data_en; - wire [ 7: 0] av_ld_byte1_data_nxt; - reg [ 7: 0] av_ld_byte2_data; - wire [ 7: 0] av_ld_byte2_data_nxt; - reg [ 7: 0] av_ld_byte3_data; - wire [ 7: 0] av_ld_byte3_data_nxt; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire [ 31: 0] av_ld_data_aligned_unfiltered; - wire av_ld_done; - wire av_ld_extend; - wire av_ld_getting_data; - wire av_ld_rshift8; - reg av_ld_waiting_for_data; - wire av_ld_waiting_for_data_nxt; - wire av_sign_bit; - wire [ 18: 0] d_address; - reg [ 3: 0] d_byteenable; - reg d_read; - wire d_read_nxt; - wire d_write; - wire d_write_nxt; - reg [ 31: 0] d_writedata; - reg hbreak_enabled; - reg hbreak_pending; - wire hbreak_pending_nxt; - wire hbreak_req; - wire [ 18: 0] i_address; - reg i_read; - wire i_read_nxt; - wire [ 31: 0] iactive; - wire intr_req; - wire jtag_debug_module_clk; - wire jtag_debug_module_debugaccess_to_roms; - wire [ 31: 0] jtag_debug_module_readdata; - wire jtag_debug_module_reset; - wire jtag_debug_module_resetrequest; - wire jtag_debug_module_waitrequest; - wire no_ci_readra; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire oci_single_step_mode; - wire oci_tb_hbreak_req; - wire test_ending; - wire test_has_ended; - reg wait_for_one_post_bret_inst; - //the_nios_system_nios2_processor_test_bench, which is an e_instance - nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench - ( - .D_iw (D_iw), - .D_iw_op (D_iw_op), - .D_iw_opx (D_iw_opx), - .D_valid (D_valid), - .E_valid (E_valid), - .F_pcb (F_pcb), - .F_valid (F_valid), - .R_ctrl_ld (R_ctrl_ld), - .R_ctrl_ld_non_io (R_ctrl_ld_non_io), - .R_dst_regnum (R_dst_regnum), - .R_wr_dst_reg (R_wr_dst_reg), - .W_valid (W_valid), - .W_vinst (W_vinst), - .W_wr_data (W_wr_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), - .clk (clk), - .d_address (d_address), - .d_byteenable (d_byteenable), - .d_read (d_read), - .d_write (d_write), - .d_write_nxt (d_write_nxt), - .i_address (i_address), - .i_read (i_read), - .i_readdata (i_readdata), - .i_waitrequest (i_waitrequest), - .reset_n (reset_n), - .test_has_ended (test_has_ended) - ); - - assign F_av_iw_a = F_av_iw[31 : 27]; - assign F_av_iw_b = F_av_iw[26 : 22]; - assign F_av_iw_c = F_av_iw[21 : 17]; - assign F_av_iw_custom_n = F_av_iw[13 : 6]; - assign F_av_iw_custom_readra = F_av_iw[16]; - assign F_av_iw_custom_readrb = F_av_iw[15]; - assign F_av_iw_custom_writerc = F_av_iw[14]; - assign F_av_iw_opx = F_av_iw[16 : 11]; - assign F_av_iw_op = F_av_iw[5 : 0]; - assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm16 = F_av_iw[21 : 6]; - assign F_av_iw_imm26 = F_av_iw[31 : 6]; - assign F_av_iw_memsz = F_av_iw[4 : 3]; - assign F_av_iw_control_regnum = F_av_iw[8 : 6]; - assign F_av_mem8 = F_av_iw_memsz == 2'b00; - assign F_av_mem16 = F_av_iw_memsz == 2'b01; - assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; - assign F_iw_a = F_iw[31 : 27]; - assign F_iw_b = F_iw[26 : 22]; - assign F_iw_c = F_iw[21 : 17]; - assign F_iw_custom_n = F_iw[13 : 6]; - assign F_iw_custom_readra = F_iw[16]; - assign F_iw_custom_readrb = F_iw[15]; - assign F_iw_custom_writerc = F_iw[14]; - assign F_iw_opx = F_iw[16 : 11]; - assign F_iw_op = F_iw[5 : 0]; - assign F_iw_shift_imm5 = F_iw[10 : 6]; - assign F_iw_trap_break_imm5 = F_iw[10 : 6]; - assign F_iw_imm5 = F_iw[10 : 6]; - assign F_iw_imm16 = F_iw[21 : 6]; - assign F_iw_imm26 = F_iw[31 : 6]; - assign F_iw_memsz = F_iw[4 : 3]; - assign F_iw_control_regnum = F_iw[8 : 6]; - assign F_mem8 = F_iw_memsz == 2'b00; - assign F_mem16 = F_iw_memsz == 2'b01; - assign F_mem32 = F_iw_memsz[1] == 1'b1; - assign D_iw_a = D_iw[31 : 27]; - assign D_iw_b = D_iw[26 : 22]; - assign D_iw_c = D_iw[21 : 17]; - assign D_iw_custom_n = D_iw[13 : 6]; - assign D_iw_custom_readra = D_iw[16]; - assign D_iw_custom_readrb = D_iw[15]; - assign D_iw_custom_writerc = D_iw[14]; - assign D_iw_opx = D_iw[16 : 11]; - assign D_iw_op = D_iw[5 : 0]; - assign D_iw_shift_imm5 = D_iw[10 : 6]; - assign D_iw_trap_break_imm5 = D_iw[10 : 6]; - assign D_iw_imm5 = D_iw[10 : 6]; - assign D_iw_imm16 = D_iw[21 : 6]; - assign D_iw_imm26 = D_iw[31 : 6]; - assign D_iw_memsz = D_iw[4 : 3]; - assign D_iw_control_regnum = D_iw[8 : 6]; - assign D_mem8 = D_iw_memsz == 2'b00; - assign D_mem16 = D_iw_memsz == 2'b01; - assign D_mem32 = D_iw_memsz[1] == 1'b1; - assign F_op_call = F_iw_op == 0; - assign F_op_jmpi = F_iw_op == 1; - assign F_op_ldbu = F_iw_op == 3; - assign F_op_addi = F_iw_op == 4; - assign F_op_stb = F_iw_op == 5; - assign F_op_br = F_iw_op == 6; - assign F_op_ldb = F_iw_op == 7; - assign F_op_cmpgei = F_iw_op == 8; - assign F_op_ldhu = F_iw_op == 11; - assign F_op_andi = F_iw_op == 12; - assign F_op_sth = F_iw_op == 13; - assign F_op_bge = F_iw_op == 14; - assign F_op_ldh = F_iw_op == 15; - assign F_op_cmplti = F_iw_op == 16; - assign F_op_initda = F_iw_op == 19; - assign F_op_ori = F_iw_op == 20; - assign F_op_stw = F_iw_op == 21; - assign F_op_blt = F_iw_op == 22; - assign F_op_ldw = F_iw_op == 23; - assign F_op_cmpnei = F_iw_op == 24; - assign F_op_flushda = F_iw_op == 27; - assign F_op_xori = F_iw_op == 28; - assign F_op_stc = F_iw_op == 29; - assign F_op_bne = F_iw_op == 30; - assign F_op_ldl = F_iw_op == 31; - assign F_op_cmpeqi = F_iw_op == 32; - assign F_op_ldbuio = F_iw_op == 35; - assign F_op_muli = F_iw_op == 36; - assign F_op_stbio = F_iw_op == 37; - assign F_op_beq = F_iw_op == 38; - assign F_op_ldbio = F_iw_op == 39; - assign F_op_cmpgeui = F_iw_op == 40; - assign F_op_ldhuio = F_iw_op == 43; - assign F_op_andhi = F_iw_op == 44; - assign F_op_sthio = F_iw_op == 45; - assign F_op_bgeu = F_iw_op == 46; - assign F_op_ldhio = F_iw_op == 47; - assign F_op_cmpltui = F_iw_op == 48; - assign F_op_initd = F_iw_op == 51; - assign F_op_orhi = F_iw_op == 52; - assign F_op_stwio = F_iw_op == 53; - assign F_op_bltu = F_iw_op == 54; - assign F_op_ldwio = F_iw_op == 55; - assign F_op_rdprs = F_iw_op == 56; - assign F_op_flushd = F_iw_op == 59; - assign F_op_xorhi = F_iw_op == 60; - assign F_op_rsv02 = F_iw_op == 2; - assign F_op_rsv09 = F_iw_op == 9; - assign F_op_rsv10 = F_iw_op == 10; - assign F_op_rsv17 = F_iw_op == 17; - assign F_op_rsv18 = F_iw_op == 18; - assign F_op_rsv25 = F_iw_op == 25; - assign F_op_rsv26 = F_iw_op == 26; - assign F_op_rsv33 = F_iw_op == 33; - assign F_op_rsv34 = F_iw_op == 34; - assign F_op_rsv41 = F_iw_op == 41; - assign F_op_rsv42 = F_iw_op == 42; - assign F_op_rsv49 = F_iw_op == 49; - assign F_op_rsv57 = F_iw_op == 57; - assign F_op_rsv61 = F_iw_op == 61; - assign F_op_rsv62 = F_iw_op == 62; - assign F_op_rsv63 = F_iw_op == 63; - assign F_op_eret = F_op_opx & (F_iw_opx == 1); - assign F_op_roli = F_op_opx & (F_iw_opx == 2); - assign F_op_rol = F_op_opx & (F_iw_opx == 3); - assign F_op_flushp = F_op_opx & (F_iw_opx == 4); - assign F_op_ret = F_op_opx & (F_iw_opx == 5); - assign F_op_nor = F_op_opx & (F_iw_opx == 6); - assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); - assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); - assign F_op_bret = F_op_opx & (F_iw_opx == 9); - assign F_op_ror = F_op_opx & (F_iw_opx == 11); - assign F_op_flushi = F_op_opx & (F_iw_opx == 12); - assign F_op_jmp = F_op_opx & (F_iw_opx == 13); - assign F_op_and = F_op_opx & (F_iw_opx == 14); - assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); - assign F_op_slli = F_op_opx & (F_iw_opx == 18); - assign F_op_sll = F_op_opx & (F_iw_opx == 19); - assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); - assign F_op_or = F_op_opx & (F_iw_opx == 22); - assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); - assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); - assign F_op_srli = F_op_opx & (F_iw_opx == 26); - assign F_op_srl = F_op_opx & (F_iw_opx == 27); - assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); - assign F_op_callr = F_op_opx & (F_iw_opx == 29); - assign F_op_xor = F_op_opx & (F_iw_opx == 30); - assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); - assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); - assign F_op_divu = F_op_opx & (F_iw_opx == 36); - assign F_op_div = F_op_opx & (F_iw_opx == 37); - assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); - assign F_op_mul = F_op_opx & (F_iw_opx == 39); - assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); - assign F_op_initi = F_op_opx & (F_iw_opx == 41); - assign F_op_trap = F_op_opx & (F_iw_opx == 45); - assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); - assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); - assign F_op_add = F_op_opx & (F_iw_opx == 49); - assign F_op_break = F_op_opx & (F_iw_opx == 52); - assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); - assign F_op_sync = F_op_opx & (F_iw_opx == 54); - assign F_op_sub = F_op_opx & (F_iw_opx == 57); - assign F_op_srai = F_op_opx & (F_iw_opx == 58); - assign F_op_sra = F_op_opx & (F_iw_opx == 59); - assign F_op_intr = F_op_opx & (F_iw_opx == 61); - assign F_op_crst = F_op_opx & (F_iw_opx == 62); - assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); - assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); - assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); - assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); - assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); - assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); - assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); - assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); - assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); - assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); - assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); - assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); - assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); - assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); - assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); - assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); - assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); - assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); - assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); - assign F_op_opx = F_iw_op == 58; - assign F_op_custom = F_iw_op == 50; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - assign R_en = 1'b1; - assign E_ci_result = 0; - //custom_instruction_master, which is an e_custom_instruction_master - assign no_ci_readra = 1'b0; - assign E_ci_multi_stall = 1'b0; - assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; - assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : - R_ctrl_break ? 2'b01 : - (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : - 2'b11; - - assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : - (F_pc_sel_nxt == 2'b01)? 66056 : - (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : - F_pc_plus_one; - - assign F_pc_nxt = F_pc_no_crst_nxt; - assign F_pcb_nxt = {F_pc_nxt, 2'b00}; - assign F_pc_en = W_valid; - assign F_pc_plus_one = F_pc + 1; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - F_pc <= 0; - else if (F_pc_en) - F_pc <= F_pc_nxt; - end - - - assign F_pcb = {F_pc, 2'b00}; - assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; - assign F_valid = i_read & ~i_waitrequest; - assign i_read_nxt = W_valid | (i_read & i_waitrequest); - assign i_address = {F_pc, 2'b00}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - i_read <= 1'b1; - else - i_read <= i_read_nxt; - end - - - assign oci_tb_hbreak_req = oci_hbreak_req; - assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); - assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled - : hbreak_req; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - wait_for_one_post_bret_inst <= 1'b0; - else - wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_pending <= 1'b0; - else - hbreak_pending <= hbreak_pending_nxt; - end - - - assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); - assign F_av_iw = i_readdata; - assign F_iw = hbreak_req ? 4040762 : - 1'b0 ? 127034 : - intr_req ? 3926074 : - F_av_iw; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_iw <= 0; - else if (F_valid) - D_iw <= F_iw; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_valid <= 0; - else - D_valid <= F_valid; - end - - - assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : - D_ctrl_implicit_dst_eretaddr ? 5'd29 : - D_ctrl_b_is_dst ? D_iw_b : - D_iw_c; - - assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; - assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; - assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_jmp_direct_target_waddr = D_iw[31 : 6]; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_valid <= 0; - else - R_valid <= D_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_wr_dst_reg <= 0; - else - R_wr_dst_reg <= D_wr_dst_reg; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_dst_regnum <= 0; - else - R_dst_regnum <= D_dst_regnum; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_logic_op <= 0; - else - R_logic_op <= D_logic_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_compare_op <= 0; - else - R_compare_op <= D_compare_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_src2_use_imm <= 0; - else - R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); - end - - - assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; - assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; -//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_a), - .rdaddress (D_iw_a), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; -`else -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; -//synthesis read_comments_as_HDL off -//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_b), - .rdaddress (D_iw_b), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; -`else -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; -//synthesis read_comments_as_HDL off - assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : - ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : - R_rf_a; - - assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : - (R_src2_use_imm)? D_iw_imm16 : - R_rf_b[15 : 0]; - - assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : - (R_ctrl_hi_imm16)? D_iw_imm16 : - (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : - R_rf_b[31 : 16]; - - assign R_src2 = {R_src2_hi, R_src2_lo}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_valid <= 0; - else - E_valid <= R_valid | E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_new_inst <= 0; - else - E_new_inst <= R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src1 <= 0; - else - E_src1 <= R_src1; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src2 <= 0; - else - E_src2 <= R_src2; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_invert_arith_src_msb <= 0; - else - E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_alu_sub <= 0; - else - E_alu_sub <= D_ctrl_alu_subtract & R_valid; - end - - - assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; - assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, - E_src1[30 : 0]}; - - assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, - E_src2[30 : 0]}; - - assign E_arith_result = E_alu_sub ? - E_arith_src1 - E_arith_src2 : - E_arith_src1 + E_arith_src2; - - assign E_mem_baddr = E_arith_result[18 : 0]; - assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : - (R_logic_op == 2'b01)? (E_src1 & E_src2) : - (R_logic_op == 2'b10)? (E_src1 | E_src2) : - (E_src1 ^ E_src2); - - assign E_logic_result_is_0 = E_logic_result == 0; - assign E_eq = E_logic_result_is_0; - assign E_lt = E_arith_result[32]; - assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : - (R_compare_op == 2'b01)? ~E_lt : - (R_compare_op == 2'b10)? E_lt : - ~E_eq; - - assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; - assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; - assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; - assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : - (R_ctrl_rot_right ? E_shift_rot_result[0] : - E_shift_rot_result[31]); - - assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : - (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : - {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_result <= 0; - else - E_shift_rot_result <= E_shift_rot_result_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_cnt <= 0; - else - E_shift_rot_cnt <= E_shift_rot_cnt_nxt; - end - - - assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : - (D_iw_control_regnum == 3'd1)? W_estatus_reg : - (D_iw_control_regnum == 3'd2)? W_bstatus_reg : - (D_iw_control_regnum == 3'd3)? W_ienable_reg : - (D_iw_control_regnum == 3'd4)? W_ipending_reg : - 0; - - assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : - (R_ctrl_shift_rot)? E_shift_rot_result : - (R_ctrl_logic)? E_logic_result : - (R_ctrl_custom)? E_ci_result : - E_arith_result; - - assign R_stb_data = R_rf_b[7 : 0]; - assign R_sth_data = R_rf_b[15 : 0]; - assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : - (D_mem16)? {R_sth_data, R_sth_data} : - R_rf_b; - - assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : - 4'b1111; - - assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); - assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); - assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); - assign E_st_stall = d_write_nxt; - assign d_address = W_mem_baddr; - assign av_ld_getting_data = d_read & ~d_waitrequest; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_read <= 0; - else - d_read <= d_read_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_writedata <= 0; - else - d_writedata <= E_st_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_byteenable <= 0; - else - d_byteenable <= E_mem_byte_en; - end - - - assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); - assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); - assign av_ld_aligning_data_nxt = av_ld_aligning_data ? - ~av_ld_align_one_more_cycle : - (~D_mem32 & av_ld_getting_data); - - assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? - ~av_ld_getting_data : - (R_ctrl_ld & E_new_inst); - - assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); - assign av_ld_rshift8 = av_ld_aligning_data & - (av_ld_align_cycle < (W_mem_baddr[1 : 0])); - - assign av_ld_extend = av_ld_aligning_data; - assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : - av_ld_extend ? av_ld_byte0_data : - d_readdata[7 : 0]; - - assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[15 : 8]; - - assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[23 : 16]; - - assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[31 : 24]; - - assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); - assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, - av_ld_byte1_data, av_ld_byte0_data}; - - assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; - assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_align_cycle <= 0; - else - av_ld_align_cycle <= av_ld_align_cycle_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_waiting_for_data <= 0; - else - av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_aligning_data <= 0; - else - av_ld_aligning_data <= av_ld_aligning_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte0_data <= 0; - else - av_ld_byte0_data <= av_ld_byte0_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte1_data <= 0; - else if (av_ld_byte1_data_en) - av_ld_byte1_data <= av_ld_byte1_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte2_data <= 0; - else - av_ld_byte2_data <= av_ld_byte2_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte3_data <= 0; - else - av_ld_byte3_data <= av_ld_byte3_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_valid <= 0; - else - W_valid <= E_valid & ~E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_control_rd_data <= 0; - else - W_control_rd_data <= E_control_rd_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_cmp_result <= 0; - else - W_cmp_result <= E_cmp_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_alu_result <= 0; - else - W_alu_result <= E_alu_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_status_reg_pie <= 0; - else - W_status_reg_pie <= W_status_reg_pie_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_estatus_reg <= 0; - else - W_estatus_reg <= W_estatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_bstatus_reg <= 0; - else - W_bstatus_reg <= W_bstatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ienable_reg <= 0; - else - W_ienable_reg <= W_ienable_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ipending_reg <= 0; - else - W_ipending_reg <= W_ipending_reg_nxt; - end - - - assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : - R_ctrl_rdctl_inst ? W_control_rd_data : - W_alu_result[31 : 0]; - - assign W_wr_data = W_wr_data_non_zero; - assign W_br_taken = R_ctrl_br & W_cmp_result; - assign W_mem_baddr = W_alu_result[18 : 0]; - assign W_status_reg = W_status_reg_pie; - assign E_wrctl_status = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd0); - - assign E_wrctl_estatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd1); - - assign E_wrctl_bstatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd2); - - assign E_wrctl_ienable = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd3); - - assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : - (D_op_eret) ? W_estatus_reg : - (D_op_bret) ? W_bstatus_reg : - (E_wrctl_status) ? E_src1[0] : - W_status_reg_pie; - - assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; - assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : - (R_ctrl_exception) ? W_status_reg : - (E_wrctl_estatus) ? E_src1[0] : - W_estatus_reg; - - assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; - assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : - (E_wrctl_bstatus) ? E_src1[0] : - W_bstatus_reg; - - assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; - assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? - E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; - - assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_enabled <= 1'b1; - else if (E_valid) - hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; - end - - - nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci - ( - .D_valid (D_valid), - .E_st_data (E_st_data), - .E_valid (E_valid), - .F_pc (F_pc), - .address_nxt (jtag_debug_module_address), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .byteenable_nxt (jtag_debug_module_byteenable), - .clk (jtag_debug_module_clk), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .debugaccess_nxt (jtag_debug_module_debugaccess), - .hbreak_enabled (hbreak_enabled), - .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), - .oci_hbreak_req (oci_hbreak_req), - .oci_ienable (oci_ienable), - .oci_single_step_mode (oci_single_step_mode), - .read_nxt (jtag_debug_module_read), - .readdata (jtag_debug_module_readdata), - .reset (jtag_debug_module_reset), - .reset_n (reset_n), - .resetrequest (jtag_debug_module_resetrequest), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .waitrequest (jtag_debug_module_waitrequest), - .write_nxt (jtag_debug_module_write), - .writedata_nxt (jtag_debug_module_writedata) - ); - - //jtag_debug_module, which is an e_avalon_slave - assign jtag_debug_module_clk = clk; - assign jtag_debug_module_reset = ~reset_n; - assign D_ctrl_custom = 1'b0; - assign R_ctrl_custom_nxt = D_ctrl_custom; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom <= 0; - else if (R_en) - R_ctrl_custom <= R_ctrl_custom_nxt; - end - - - assign D_ctrl_custom_multi = 1'b0; - assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom_multi <= 0; - else if (R_en) - R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; - end - - - assign D_ctrl_jmp_indirect = D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_indirect <= 0; - else if (R_en) - R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; - end - - - assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; - assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_direct <= 0; - else if (R_en) - R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; - end - - - assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; - assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_retaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; - end - - - assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; - assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_eretaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; - end - - - assign D_ctrl_exception = D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60; - - assign R_ctrl_exception_nxt = D_ctrl_exception; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_exception <= 0; - else if (R_en) - R_ctrl_exception <= R_ctrl_exception_nxt; - end - - - assign D_ctrl_break = D_op_break|D_op_hbreak; - assign R_ctrl_break_nxt = D_ctrl_break; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_break <= 0; - else if (R_en) - R_ctrl_break <= R_ctrl_break_nxt; - end - - - assign D_ctrl_crst = D_op_crst|D_op_rsvx63; - assign R_ctrl_crst_nxt = D_ctrl_crst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_crst <= 0; - else if (R_en) - R_ctrl_crst <= R_ctrl_crst_nxt; - end - - - assign D_ctrl_uncond_cti_non_br = D_op_call| - D_op_jmpi| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_uncond_cti_non_br <= 0; - else if (R_en) - R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; - end - - - assign D_ctrl_retaddr = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak; - - assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_retaddr <= 0; - else if (R_en) - R_ctrl_retaddr <= R_ctrl_retaddr_nxt; - end - - - assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; - assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_logical <= 0; - else if (R_en) - R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; - end - - - assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; - assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_right_arith <= 0; - else if (R_en) - R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; - end - - - assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; - assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rot_right <= 0; - else if (R_en) - R_ctrl_rot_right <= R_ctrl_rot_right_nxt; - end - - - assign D_ctrl_shift_rot_right = D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot_right <= 0; - else if (R_en) - R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; - end - - - assign D_ctrl_shift_rot = D_op_slli| - D_op_rsvx50| - D_op_sll| - D_op_rsvx51| - D_op_roli| - D_op_rsvx34| - D_op_rol| - D_op_rsvx35| - D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot <= 0; - else if (R_en) - R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; - end - - - assign D_ctrl_logic = D_op_and| - D_op_or| - D_op_xor| - D_op_nor| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori; - - assign R_ctrl_logic_nxt = D_ctrl_logic; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_logic <= 0; - else if (R_en) - R_ctrl_logic <= R_ctrl_logic_nxt; - end - - - assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; - assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_hi_imm16 <= 0; - else if (R_en) - R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; - end - - - assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| - D_op_cmpltui| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_unsigned_lo_imm16 <= 0; - else if (R_en) - R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; - end - - - assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; - assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_uncond <= 0; - else if (R_en) - R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; - end - - - assign D_ctrl_br = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62; - - assign R_ctrl_br_nxt = D_ctrl_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br <= 0; - else if (R_en) - R_ctrl_br <= R_ctrl_br_nxt; - end - - - assign D_ctrl_alu_subtract = D_op_sub| - D_op_rsvx25| - D_op_cmplti| - D_op_cmpltui| - D_op_cmplt| - D_op_cmpltu| - D_op_blt| - D_op_bltu| - D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpge| - D_op_cmpgeu| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42; - - assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_subtract <= 0; - else if (R_en) - R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; - end - - - assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; - assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_signed_comparison <= 0; - else if (R_en) - R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; - end - - - assign D_ctrl_br_cmp = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_rsvx00| - D_op_cmpge| - D_op_cmplt| - D_op_cmpne| - D_op_cmpgeu| - D_op_cmpltu| - D_op_cmpeq| - D_op_rsvx56; - - assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_cmp <= 0; - else if (R_en) - R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; - end - - - assign D_ctrl_ld_signed = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63; - - assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_signed <= 0; - else if (R_en) - R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; - end - - - assign D_ctrl_ld = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio; - - assign R_ctrl_ld_nxt = D_ctrl_ld; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld <= 0; - else if (R_en) - R_ctrl_ld <= R_ctrl_ld_nxt; - end - - - assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; - assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_non_io <= 0; - else if (R_en) - R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; - end - - - assign D_ctrl_st = D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61; - - assign R_ctrl_st_nxt = D_ctrl_st; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_st <= 0; - else if (R_en) - R_ctrl_st <= R_ctrl_st_nxt; - end - - - assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; - assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_io <= 0; - else if (R_en) - R_ctrl_ld_io <= R_ctrl_ld_io_nxt; - end - - - assign D_ctrl_b_is_dst = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda; - - assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_b_is_dst <= 0; - else if (R_en) - R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; - end - - - assign D_ctrl_ignore_dst = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57; - - assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ignore_dst <= 0; - else if (R_en) - R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; - end - - - assign D_ctrl_src2_choose_imm = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_src2_choose_imm <= 0; - else if (R_en) - R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; - end - - - assign D_ctrl_wrctl_inst = D_op_wrctl; - assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_wrctl_inst <= 0; - else if (R_en) - R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; - end - - - assign D_ctrl_rdctl_inst = D_op_rdctl; - assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rdctl_inst <= 0; - else if (R_en) - R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; - end - - - assign D_ctrl_force_src2_zero = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_jmpi; - - assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_force_src2_zero <= 0; - else if (R_en) - R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; - end - - - assign D_ctrl_alu_force_xor = D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpeqi| - D_op_cmpge| - D_op_cmpgeu| - D_op_cmpeq| - D_op_cmpnei| - D_op_cmpne| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42| - D_op_beq| - D_op_rsv34| - D_op_bne| - D_op_rsv62| - D_op_br| - D_op_rsv02; - - assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_force_xor <= 0; - else if (R_en) - R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; - end - - - //data_master, which is an e_avalon_master - //instruction_master, which is an e_avalon_master - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign F_inst = (F_op_call)? 56'h20202063616c6c : - (F_op_jmpi)? 56'h2020206a6d7069 : - (F_op_ldbu)? 56'h2020206c646275 : - (F_op_addi)? 56'h20202061646469 : - (F_op_stb)? 56'h20202020737462 : - (F_op_br)? 56'h20202020206272 : - (F_op_ldb)? 56'h202020206c6462 : - (F_op_cmpgei)? 56'h20636d70676569 : - (F_op_ldhu)? 56'h2020206c646875 : - (F_op_andi)? 56'h202020616e6469 : - (F_op_sth)? 56'h20202020737468 : - (F_op_bge)? 56'h20202020626765 : - (F_op_ldh)? 56'h202020206c6468 : - (F_op_cmplti)? 56'h20636d706c7469 : - (F_op_initda)? 56'h20696e69746461 : - (F_op_ori)? 56'h202020206f7269 : - (F_op_stw)? 56'h20202020737477 : - (F_op_blt)? 56'h20202020626c74 : - (F_op_ldw)? 56'h202020206c6477 : - (F_op_cmpnei)? 56'h20636d706e6569 : - (F_op_flushda)? 56'h666c7573686461 : - (F_op_xori)? 56'h202020786f7269 : - (F_op_bne)? 56'h20202020626e65 : - (F_op_cmpeqi)? 56'h20636d70657169 : - (F_op_ldbuio)? 56'h206c646275696f : - (F_op_muli)? 56'h2020206d756c69 : - (F_op_stbio)? 56'h2020737462696f : - (F_op_beq)? 56'h20202020626571 : - (F_op_ldbio)? 56'h20206c6462696f : - (F_op_cmpgeui)? 56'h636d7067657569 : - (F_op_ldhuio)? 56'h206c646875696f : - (F_op_andhi)? 56'h2020616e646869 : - (F_op_sthio)? 56'h2020737468696f : - (F_op_bgeu)? 56'h20202062676575 : - (F_op_ldhio)? 56'h20206c6468696f : - (F_op_cmpltui)? 56'h636d706c747569 : - (F_op_initd)? 56'h2020696e697464 : - (F_op_orhi)? 56'h2020206f726869 : - (F_op_stwio)? 56'h2020737477696f : - (F_op_bltu)? 56'h202020626c7475 : - (F_op_ldwio)? 56'h20206c6477696f : - (F_op_flushd)? 56'h20666c75736864 : - (F_op_xorhi)? 56'h2020786f726869 : - (F_op_eret)? 56'h20202065726574 : - (F_op_roli)? 56'h202020726f6c69 : - (F_op_rol)? 56'h20202020726f6c : - (F_op_flushp)? 56'h20666c75736870 : - (F_op_ret)? 56'h20202020726574 : - (F_op_nor)? 56'h202020206e6f72 : - (F_op_mulxuu)? 56'h206d756c787575 : - (F_op_cmpge)? 56'h2020636d706765 : - (F_op_bret)? 56'h20202062726574 : - (F_op_ror)? 56'h20202020726f72 : - (F_op_flushi)? 56'h20666c75736869 : - (F_op_jmp)? 56'h202020206a6d70 : - (F_op_and)? 56'h20202020616e64 : - (F_op_cmplt)? 56'h2020636d706c74 : - (F_op_slli)? 56'h202020736c6c69 : - (F_op_sll)? 56'h20202020736c6c : - (F_op_or)? 56'h20202020206f72 : - (F_op_mulxsu)? 56'h206d756c787375 : - (F_op_cmpne)? 56'h2020636d706e65 : - (F_op_srli)? 56'h20202073726c69 : - (F_op_srl)? 56'h2020202073726c : - (F_op_nextpc)? 56'h206e6578747063 : - (F_op_callr)? 56'h202063616c6c72 : - (F_op_xor)? 56'h20202020786f72 : - (F_op_mulxss)? 56'h206d756c787373 : - (F_op_cmpeq)? 56'h2020636d706571 : - (F_op_divu)? 56'h20202064697675 : - (F_op_div)? 56'h20202020646976 : - (F_op_rdctl)? 56'h2020726463746c : - (F_op_mul)? 56'h202020206d756c : - (F_op_cmpgeu)? 56'h20636d70676575 : - (F_op_initi)? 56'h2020696e697469 : - (F_op_trap)? 56'h20202074726170 : - (F_op_wrctl)? 56'h2020777263746c : - (F_op_cmpltu)? 56'h20636d706c7475 : - (F_op_add)? 56'h20202020616464 : - (F_op_break)? 56'h2020627265616b : - (F_op_hbreak)? 56'h2068627265616b : - (F_op_sync)? 56'h20202073796e63 : - (F_op_sub)? 56'h20202020737562 : - (F_op_srai)? 56'h20202073726169 : - (F_op_sra)? 56'h20202020737261 : - (F_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign D_inst = (D_op_call)? 56'h20202063616c6c : - (D_op_jmpi)? 56'h2020206a6d7069 : - (D_op_ldbu)? 56'h2020206c646275 : - (D_op_addi)? 56'h20202061646469 : - (D_op_stb)? 56'h20202020737462 : - (D_op_br)? 56'h20202020206272 : - (D_op_ldb)? 56'h202020206c6462 : - (D_op_cmpgei)? 56'h20636d70676569 : - (D_op_ldhu)? 56'h2020206c646875 : - (D_op_andi)? 56'h202020616e6469 : - (D_op_sth)? 56'h20202020737468 : - (D_op_bge)? 56'h20202020626765 : - (D_op_ldh)? 56'h202020206c6468 : - (D_op_cmplti)? 56'h20636d706c7469 : - (D_op_initda)? 56'h20696e69746461 : - (D_op_ori)? 56'h202020206f7269 : - (D_op_stw)? 56'h20202020737477 : - (D_op_blt)? 56'h20202020626c74 : - (D_op_ldw)? 56'h202020206c6477 : - (D_op_cmpnei)? 56'h20636d706e6569 : - (D_op_flushda)? 56'h666c7573686461 : - (D_op_xori)? 56'h202020786f7269 : - (D_op_bne)? 56'h20202020626e65 : - (D_op_cmpeqi)? 56'h20636d70657169 : - (D_op_ldbuio)? 56'h206c646275696f : - (D_op_muli)? 56'h2020206d756c69 : - (D_op_stbio)? 56'h2020737462696f : - (D_op_beq)? 56'h20202020626571 : - (D_op_ldbio)? 56'h20206c6462696f : - (D_op_cmpgeui)? 56'h636d7067657569 : - (D_op_ldhuio)? 56'h206c646875696f : - (D_op_andhi)? 56'h2020616e646869 : - (D_op_sthio)? 56'h2020737468696f : - (D_op_bgeu)? 56'h20202062676575 : - (D_op_ldhio)? 56'h20206c6468696f : - (D_op_cmpltui)? 56'h636d706c747569 : - (D_op_initd)? 56'h2020696e697464 : - (D_op_orhi)? 56'h2020206f726869 : - (D_op_stwio)? 56'h2020737477696f : - (D_op_bltu)? 56'h202020626c7475 : - (D_op_ldwio)? 56'h20206c6477696f : - (D_op_flushd)? 56'h20666c75736864 : - (D_op_xorhi)? 56'h2020786f726869 : - (D_op_eret)? 56'h20202065726574 : - (D_op_roli)? 56'h202020726f6c69 : - (D_op_rol)? 56'h20202020726f6c : - (D_op_flushp)? 56'h20666c75736870 : - (D_op_ret)? 56'h20202020726574 : - (D_op_nor)? 56'h202020206e6f72 : - (D_op_mulxuu)? 56'h206d756c787575 : - (D_op_cmpge)? 56'h2020636d706765 : - (D_op_bret)? 56'h20202062726574 : - (D_op_ror)? 56'h20202020726f72 : - (D_op_flushi)? 56'h20666c75736869 : - (D_op_jmp)? 56'h202020206a6d70 : - (D_op_and)? 56'h20202020616e64 : - (D_op_cmplt)? 56'h2020636d706c74 : - (D_op_slli)? 56'h202020736c6c69 : - (D_op_sll)? 56'h20202020736c6c : - (D_op_or)? 56'h20202020206f72 : - (D_op_mulxsu)? 56'h206d756c787375 : - (D_op_cmpne)? 56'h2020636d706e65 : - (D_op_srli)? 56'h20202073726c69 : - (D_op_srl)? 56'h2020202073726c : - (D_op_nextpc)? 56'h206e6578747063 : - (D_op_callr)? 56'h202063616c6c72 : - (D_op_xor)? 56'h20202020786f72 : - (D_op_mulxss)? 56'h206d756c787373 : - (D_op_cmpeq)? 56'h2020636d706571 : - (D_op_divu)? 56'h20202064697675 : - (D_op_div)? 56'h20202020646976 : - (D_op_rdctl)? 56'h2020726463746c : - (D_op_mul)? 56'h202020206d756c : - (D_op_cmpgeu)? 56'h20636d70676575 : - (D_op_initi)? 56'h2020696e697469 : - (D_op_trap)? 56'h20202074726170 : - (D_op_wrctl)? 56'h2020777263746c : - (D_op_cmpltu)? 56'h20636d706c7475 : - (D_op_add)? 56'h20202020616464 : - (D_op_break)? 56'h2020627265616b : - (D_op_hbreak)? 56'h2068627265616b : - (D_op_sync)? 56'h20202073796e63 : - (D_op_sub)? 56'h20202020737562 : - (D_op_srai)? 56'h20202073726169 : - (D_op_sra)? 56'h20202020737261 : - (D_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; - assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; - assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; - assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; - assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_a_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_b_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_debug ( + // inputs: + clk, + dbrk_break, + debugreq, + hbreak_enabled, + jdo, + jrst_n, + ocireg_ers, + ocireg_mrs, + reset, + st_ready_test_idle, + take_action_ocimem_a, + take_action_ocireg, + xbrk_break, + + // outputs: + debugack, + monitor_error, + monitor_go, + monitor_ready, + oci_hbreak_req, + resetlatch, + resetrequest + ) +; + + output debugack; + output monitor_error; + output monitor_go; + output monitor_ready; + output oci_hbreak_req; + output resetlatch; + output resetrequest; + input clk; + input dbrk_break; + input debugreq; + input hbreak_enabled; + input [ 37: 0] jdo; + input jrst_n; + input ocireg_ers; + input ocireg_mrs; + input reset; + input st_ready_test_idle; + input take_action_ocimem_a; + input take_action_ocireg; + input xbrk_break; + + reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire debugack; + reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire oci_hbreak_req; + wire reset_sync; + reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire unxcomplemented_resetxx0; + assign unxcomplemented_resetxx0 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer + ( + .clk (clk), + .din (reset), + .dout (reset_sync), + .reset_n (unxcomplemented_resetxx0) + ); + + defparam the_altera_std_synchronizer.depth = 2; + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + break_on_reset <= 1'b0; + resetrequest <= 1'b0; + jtag_break <= 1'b0; + end + else if (take_action_ocimem_a) + begin + resetrequest <= jdo[22]; + jtag_break <= jdo[21] ? 1 + : jdo[20] ? 0 + : jtag_break; + + break_on_reset <= jdo[19] ? 1 + : jdo[18] ? 0 + : break_on_reset; + + resetlatch <= jdo[24] ? 0 : resetlatch; + end + else if (reset_sync) + begin + jtag_break <= break_on_reset; + resetlatch <= 1; + end + else if (debugreq & ~debugack & break_on_reset) + jtag_break <= 1'b1; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + monitor_ready <= 1'b0; + monitor_error <= 1'b0; + monitor_go <= 1'b0; + end + else + begin + if (take_action_ocimem_a && jdo[25]) + monitor_ready <= 1'b0; + else if (take_action_ocireg && ocireg_mrs) + monitor_ready <= 1'b1; + if (take_action_ocimem_a && jdo[25]) + monitor_error <= 1'b0; + else if (take_action_ocireg && ocireg_ers) + monitor_error <= 1'b1; + if (take_action_ocimem_a && jdo[23]) + monitor_go <= 1'b1; + else if (st_ready_test_idle) + monitor_go <= 1'b0; + end + end + + + assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; + assign debugack = ~hbreak_enabled; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_ociram_sp_ram_module ( + // inputs: + address, + byteenable, + clock, + data, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input [ 7: 0] address; + input [ 3: 0] byteenable; + input clock; + input [ 31: 0] data; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clock), + .data_a (data), + .q_a (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 256, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 8; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_ocimem ( + // inputs: + address, + byteenable, + clk, + debugaccess, + jdo, + jrst_n, + read, + take_action_ocimem_a, + take_action_ocimem_b, + take_no_action_ocimem_a, + write, + writedata, + + // outputs: + MonDReg, + ociram_readdata, + waitrequest + ) +; + + output [ 31: 0] MonDReg; + output [ 31: 0] ociram_readdata; + output waitrequest; + input [ 8: 0] address; + input [ 3: 0] byteenable; + input clk; + input debugaccess; + input [ 37: 0] jdo; + input jrst_n; + input read; + input take_action_ocimem_a; + input take_action_ocimem_b; + input take_no_action_ocimem_a; + input write; + input [ 31: 0] writedata; + + reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 8: 0] MonARegAddrInc; + wire MonARegAddrIncAccessingRAM; + reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire avalon_ram_wr; + wire [ 31: 0] cfgrom_readdata; + reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 7: 0] ociram_addr; + wire [ 3: 0] ociram_byteenable; + wire [ 31: 0] ociram_readdata; + wire [ 31: 0] ociram_wr_data; + wire ociram_wr_en; + reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + jtag_rd <= 1'b0; + jtag_rd_d1 <= 1'b0; + jtag_ram_wr <= 1'b0; + jtag_ram_rd <= 1'b0; + jtag_ram_rd_d1 <= 1'b0; + jtag_ram_access <= 1'b0; + MonAReg <= 0; + MonDReg <= 0; + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else + begin + if (take_no_action_ocimem_a) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + jtag_rd <= 1'b1; + jtag_ram_rd <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else if (take_action_ocimem_a) + begin + MonAReg[10 : 2] <= { jdo[17], + jdo[33 : 26] }; + + jtag_rd <= 1'b1; + jtag_ram_rd <= ~jdo[17]; + jtag_ram_access <= ~jdo[17]; + end + else if (take_action_ocimem_b) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + MonDReg <= jdo[34 : 3]; + jtag_ram_wr <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else + begin + jtag_rd <= 0; + jtag_ram_wr <= 0; + jtag_ram_rd <= 0; + jtag_ram_access <= 0; + if (jtag_rd_d1) + MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; + end + jtag_rd_d1 <= jtag_rd; + jtag_ram_rd_d1 <= jtag_ram_rd; + if (~waitrequest) + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else if (write) + waitrequest <= ~address[8] & jtag_ram_access; + else if (read) + begin + avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); + waitrequest <= ~avalon_ociram_readdata_ready; + end + else + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + end + end + + + assign MonARegAddrInc = MonAReg[10 : 2]+1; + assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; + assign avalon_ram_wr = write & ~address[8] & debugaccess; + assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; + assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; + assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; + assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; +//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram +nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram + ( + .address (ociram_addr), + .byteenable (ociram_byteenable), + .clock (clk), + .data (ociram_wr_data), + .q (ociram_readdata), + .wren (ociram_wr_en) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; +`else +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; +//synthesis read_comments_as_HDL off + assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : + (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : + (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : + (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : + (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : + 32'h00000000; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_avalon_reg ( + // inputs: + address, + clk, + debugaccess, + monitor_error, + monitor_go, + monitor_ready, + reset_n, + write, + writedata, + + // outputs: + oci_ienable, + oci_reg_readdata, + oci_single_step_mode, + ocireg_ers, + ocireg_mrs, + take_action_ocireg + ) +; + + output [ 31: 0] oci_ienable; + output [ 31: 0] oci_reg_readdata; + output oci_single_step_mode; + output ocireg_ers; + output ocireg_mrs; + output take_action_ocireg; + input [ 8: 0] address; + input clk; + input debugaccess; + input monitor_error; + input monitor_go; + input monitor_ready; + input reset_n; + input write; + input [ 31: 0] writedata; + + reg [ 31: 0] oci_ienable; + wire oci_reg_00_addressed; + wire oci_reg_01_addressed; + wire [ 31: 0] oci_reg_readdata; + reg oci_single_step_mode; + wire ocireg_ers; + wire ocireg_mrs; + wire ocireg_sstep; + wire take_action_oci_intr_mask_reg; + wire take_action_ocireg; + wire write_strobe; + assign oci_reg_00_addressed = address == 9'h100; + assign oci_reg_01_addressed = address == 9'h101; + assign write_strobe = write & debugaccess; + assign take_action_ocireg = write_strobe & oci_reg_00_addressed; + assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; + assign ocireg_ers = writedata[1]; + assign ocireg_mrs = writedata[0]; + assign ocireg_sstep = writedata[3]; + assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, + monitor_ready, monitor_error} : + oci_reg_01_addressed ? oci_ienable : + 32'b0; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_single_step_mode <= 1'b0; + else if (take_action_ocireg) + oci_single_step_mode <= ocireg_sstep; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_ienable <= 32'b00000000000000000000000000100000; + else if (take_action_oci_intr_mask_reg) + oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_break ( + // inputs: + clk, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + jdo, + jrst_n, + reset_n, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + xbrk_goto0, + xbrk_goto1, + + // outputs: + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + trigbrktype, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3 + ) +; + + output [ 31: 0] break_readreg; + output dbrk_hit0_latch; + output dbrk_hit1_latch; + output dbrk_hit2_latch; + output dbrk_hit3_latch; + output trigbrktype; + output trigger_state_0; + output trigger_state_1; + output [ 7: 0] xbrk_ctrl0; + output [ 7: 0] xbrk_ctrl1; + output [ 7: 0] xbrk_ctrl2; + output [ 7: 0] xbrk_ctrl3; + input clk; + input dbrk_break; + input dbrk_goto0; + input dbrk_goto1; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_break_a; + input take_action_break_b; + input take_action_break_c; + input take_no_action_break_a; + input take_no_action_break_b; + input take_no_action_break_c; + input xbrk_goto0; + input xbrk_goto1; + + wire [ 3: 0] break_a_wpr; + wire [ 1: 0] break_a_wpr_high_bits; + wire [ 1: 0] break_a_wpr_low_bits; + wire [ 1: 0] break_b_rr; + wire [ 1: 0] break_c_rr; + reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire dbrk0_high_value; + wire dbrk0_low_value; + wire dbrk1_high_value; + wire dbrk1_low_value; + wire dbrk2_high_value; + wire dbrk2_low_value; + wire dbrk3_high_value; + wire dbrk3_low_value; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire take_action_any_break; + reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg trigger_state; + wire trigger_state_0; + wire trigger_state_1; + wire [ 31: 0] xbrk0_value; + wire [ 31: 0] xbrk1_value; + wire [ 31: 0] xbrk2_value; + wire [ 31: 0] xbrk3_value; + reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + assign break_a_wpr = jdo[35 : 32]; + assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; + assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; + assign break_b_rr = jdo[33 : 32]; + assign break_c_rr = jdo[33 : 32]; + assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + xbrk_ctrl0 <= 0; + xbrk_ctrl1 <= 0; + xbrk_ctrl2 <= 0; + xbrk_ctrl3 <= 0; + trigbrktype <= 0; + end + else + begin + if (take_action_any_break) + trigbrktype <= 0; + else if (dbrk_break) + trigbrktype <= 1; + if (take_action_break_b) + begin + if ((break_b_rr == 2'b00) && (0 >= 1)) + begin + xbrk_ctrl0[0] <= jdo[27]; + xbrk_ctrl0[1] <= jdo[28]; + xbrk_ctrl0[2] <= jdo[29]; + xbrk_ctrl0[3] <= jdo[30]; + xbrk_ctrl0[4] <= jdo[21]; + xbrk_ctrl0[5] <= jdo[20]; + xbrk_ctrl0[6] <= jdo[19]; + xbrk_ctrl0[7] <= jdo[18]; + end + if ((break_b_rr == 2'b01) && (0 >= 2)) + begin + xbrk_ctrl1[0] <= jdo[27]; + xbrk_ctrl1[1] <= jdo[28]; + xbrk_ctrl1[2] <= jdo[29]; + xbrk_ctrl1[3] <= jdo[30]; + xbrk_ctrl1[4] <= jdo[21]; + xbrk_ctrl1[5] <= jdo[20]; + xbrk_ctrl1[6] <= jdo[19]; + xbrk_ctrl1[7] <= jdo[18]; + end + if ((break_b_rr == 2'b10) && (0 >= 3)) + begin + xbrk_ctrl2[0] <= jdo[27]; + xbrk_ctrl2[1] <= jdo[28]; + xbrk_ctrl2[2] <= jdo[29]; + xbrk_ctrl2[3] <= jdo[30]; + xbrk_ctrl2[4] <= jdo[21]; + xbrk_ctrl2[5] <= jdo[20]; + xbrk_ctrl2[6] <= jdo[19]; + xbrk_ctrl2[7] <= jdo[18]; + end + if ((break_b_rr == 2'b11) && (0 >= 4)) + begin + xbrk_ctrl3[0] <= jdo[27]; + xbrk_ctrl3[1] <= jdo[28]; + xbrk_ctrl3[2] <= jdo[29]; + xbrk_ctrl3[3] <= jdo[30]; + xbrk_ctrl3[4] <= jdo[21]; + xbrk_ctrl3[5] <= jdo[20]; + xbrk_ctrl3[6] <= jdo[19]; + xbrk_ctrl3[7] <= jdo[18]; + end + end + end + end + + + assign dbrk_hit0_latch = 1'b0; + assign dbrk0_low_value = 0; + assign dbrk0_high_value = 0; + assign dbrk_hit1_latch = 1'b0; + assign dbrk1_low_value = 0; + assign dbrk1_high_value = 0; + assign dbrk_hit2_latch = 1'b0; + assign dbrk2_low_value = 0; + assign dbrk2_high_value = 0; + assign dbrk_hit3_latch = 1'b0; + assign dbrk3_low_value = 0; + assign dbrk3_high_value = 0; + assign xbrk0_value = 32'b0; + assign xbrk1_value = 32'b0; + assign xbrk2_value = 32'b0; + assign xbrk3_value = 32'b0; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + break_readreg <= 32'b0; + else if (take_action_any_break) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_a) + case (break_a_wpr_high_bits) + + 2'd0: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= xbrk0_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= xbrk1_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= xbrk2_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= xbrk3_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd0 + + 2'd1: begin + break_readreg <= 32'b0; + end // 2'd1 + + 2'd2: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_low_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_low_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_low_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_low_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd2 + + 2'd3: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_high_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_high_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_high_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_high_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd3 + + endcase // break_a_wpr_high_bits + else if (take_no_action_break_b) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_c) + break_readreg <= jdo[31 : 0]; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trigger_state <= 0; + else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) + trigger_state <= 0; + else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) + trigger_state <= -1; + end + + + assign trigger_state_0 = ~trigger_state; + assign trigger_state_1 = trigger_state; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_xbrk ( + // inputs: + D_valid, + E_valid, + F_pc, + clk, + reset_n, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3, + + // outputs: + xbrk_break, + xbrk_goto0, + xbrk_goto1, + xbrk_traceoff, + xbrk_traceon, + xbrk_trigout + ) +; + + output xbrk_break; + output xbrk_goto0; + output xbrk_goto1; + output xbrk_traceoff; + output xbrk_traceon; + output xbrk_trigout; + input D_valid; + input E_valid; + input [ 16: 0] F_pc; + input clk; + input reset_n; + input trigger_state_0; + input trigger_state_1; + input [ 7: 0] xbrk_ctrl0; + input [ 7: 0] xbrk_ctrl1; + input [ 7: 0] xbrk_ctrl2; + input [ 7: 0] xbrk_ctrl3; + + wire D_cpu_addr_en; + wire E_cpu_addr_en; + reg E_xbrk_goto0; + reg E_xbrk_goto1; + reg E_xbrk_traceoff; + reg E_xbrk_traceon; + reg E_xbrk_trigout; + wire [ 18: 0] cpu_i_address; + wire xbrk0_armed; + wire xbrk0_break_hit; + wire xbrk0_goto0_hit; + wire xbrk0_goto1_hit; + wire xbrk0_toff_hit; + wire xbrk0_ton_hit; + wire xbrk0_tout_hit; + wire xbrk1_armed; + wire xbrk1_break_hit; + wire xbrk1_goto0_hit; + wire xbrk1_goto1_hit; + wire xbrk1_toff_hit; + wire xbrk1_ton_hit; + wire xbrk1_tout_hit; + wire xbrk2_armed; + wire xbrk2_break_hit; + wire xbrk2_goto0_hit; + wire xbrk2_goto1_hit; + wire xbrk2_toff_hit; + wire xbrk2_ton_hit; + wire xbrk2_tout_hit; + wire xbrk3_armed; + wire xbrk3_break_hit; + wire xbrk3_goto0_hit; + wire xbrk3_goto1_hit; + wire xbrk3_toff_hit; + wire xbrk3_ton_hit; + wire xbrk3_tout_hit; + reg xbrk_break; + wire xbrk_break_hit; + wire xbrk_goto0; + wire xbrk_goto0_hit; + wire xbrk_goto1; + wire xbrk_goto1_hit; + wire xbrk_toff_hit; + wire xbrk_ton_hit; + wire xbrk_tout_hit; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + assign cpu_i_address = {F_pc, 2'b00}; + assign D_cpu_addr_en = D_valid; + assign E_cpu_addr_en = E_valid; + assign xbrk0_break_hit = 0; + assign xbrk0_ton_hit = 0; + assign xbrk0_toff_hit = 0; + assign xbrk0_tout_hit = 0; + assign xbrk0_goto0_hit = 0; + assign xbrk0_goto1_hit = 0; + assign xbrk1_break_hit = 0; + assign xbrk1_ton_hit = 0; + assign xbrk1_toff_hit = 0; + assign xbrk1_tout_hit = 0; + assign xbrk1_goto0_hit = 0; + assign xbrk1_goto1_hit = 0; + assign xbrk2_break_hit = 0; + assign xbrk2_ton_hit = 0; + assign xbrk2_toff_hit = 0; + assign xbrk2_tout_hit = 0; + assign xbrk2_goto0_hit = 0; + assign xbrk2_goto1_hit = 0; + assign xbrk3_break_hit = 0; + assign xbrk3_ton_hit = 0; + assign xbrk3_toff_hit = 0; + assign xbrk3_tout_hit = 0; + assign xbrk3_goto0_hit = 0; + assign xbrk3_goto1_hit = 0; + assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); + assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); + assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); + assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); + assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); + assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + xbrk_break <= 0; + else if (E_cpu_addr_en) + xbrk_break <= xbrk_break_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceon <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceon <= xbrk_ton_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceoff <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceoff <= xbrk_toff_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_trigout <= 0; + else if (E_cpu_addr_en) + E_xbrk_trigout <= xbrk_tout_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto0 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto0 <= xbrk_goto0_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto1 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto1 <= xbrk_goto1_hit; + end + + + assign xbrk_traceon = 1'b0; + assign xbrk_traceoff = 1'b0; + assign xbrk_trigout = 1'b0; + assign xbrk_goto0 = 1'b0; + assign xbrk_goto1 = 1'b0; + assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || + (xbrk_ctrl0[5] & trigger_state_1); + + assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || + (xbrk_ctrl1[5] & trigger_state_1); + + assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || + (xbrk_ctrl2[5] & trigger_state_1); + + assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || + (xbrk_ctrl3[5] & trigger_state_1); + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dbrk ( + // inputs: + E_st_data, + av_ld_data_aligned_filtered, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugack, + reset_n, + + // outputs: + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dbrk_trigout + ) +; + + output [ 18: 0] cpu_d_address; + output cpu_d_read; + output [ 31: 0] cpu_d_readdata; + output cpu_d_wait; + output cpu_d_write; + output [ 31: 0] cpu_d_writedata; + output dbrk_break; + output dbrk_goto0; + output dbrk_goto1; + output dbrk_traceme; + output dbrk_traceoff; + output dbrk_traceon; + output dbrk_trigout; + input [ 31: 0] E_st_data; + input [ 31: 0] av_ld_data_aligned_filtered; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugack; + input reset_n; + + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk0_armed; + wire dbrk0_break_pulse; + wire dbrk0_goto0; + wire dbrk0_goto1; + wire dbrk0_traceme; + wire dbrk0_traceoff; + wire dbrk0_traceon; + wire dbrk0_trigout; + wire dbrk1_armed; + wire dbrk1_break_pulse; + wire dbrk1_goto0; + wire dbrk1_goto1; + wire dbrk1_traceme; + wire dbrk1_traceoff; + wire dbrk1_traceon; + wire dbrk1_trigout; + wire dbrk2_armed; + wire dbrk2_break_pulse; + wire dbrk2_goto0; + wire dbrk2_goto1; + wire dbrk2_traceme; + wire dbrk2_traceoff; + wire dbrk2_traceon; + wire dbrk2_trigout; + wire dbrk3_armed; + wire dbrk3_break_pulse; + wire dbrk3_goto0; + wire dbrk3_goto1; + wire dbrk3_traceme; + wire dbrk3_traceoff; + wire dbrk3_traceon; + wire dbrk3_trigout; + reg dbrk_break; + reg dbrk_break_pulse; + wire [ 31: 0] dbrk_data; + reg dbrk_goto0; + reg dbrk_goto1; + reg dbrk_traceme; + reg dbrk_traceoff; + reg dbrk_traceon; + reg dbrk_trigout; + assign cpu_d_address = d_address; + assign cpu_d_readdata = av_ld_data_aligned_filtered; + assign cpu_d_read = d_read; + assign cpu_d_writedata = E_st_data; + assign cpu_d_write = d_write; + assign cpu_d_wait = d_waitrequest; + assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + dbrk_break <= 0; + else + dbrk_break <= dbrk_break ? ~debugack + : dbrk_break_pulse; + + end + + + assign dbrk0_armed = 1'b0; + assign dbrk0_trigout = 1'b0; + assign dbrk0_break_pulse = 1'b0; + assign dbrk0_traceoff = 1'b0; + assign dbrk0_traceon = 1'b0; + assign dbrk0_traceme = 1'b0; + assign dbrk0_goto0 = 1'b0; + assign dbrk0_goto1 = 1'b0; + assign dbrk1_armed = 1'b0; + assign dbrk1_trigout = 1'b0; + assign dbrk1_break_pulse = 1'b0; + assign dbrk1_traceoff = 1'b0; + assign dbrk1_traceon = 1'b0; + assign dbrk1_traceme = 1'b0; + assign dbrk1_goto0 = 1'b0; + assign dbrk1_goto1 = 1'b0; + assign dbrk2_armed = 1'b0; + assign dbrk2_trigout = 1'b0; + assign dbrk2_break_pulse = 1'b0; + assign dbrk2_traceoff = 1'b0; + assign dbrk2_traceon = 1'b0; + assign dbrk2_traceme = 1'b0; + assign dbrk2_goto0 = 1'b0; + assign dbrk2_goto1 = 1'b0; + assign dbrk3_armed = 1'b0; + assign dbrk3_trigout = 1'b0; + assign dbrk3_break_pulse = 1'b0; + assign dbrk3_traceoff = 1'b0; + assign dbrk3_traceon = 1'b0; + assign dbrk3_traceme = 1'b0; + assign dbrk3_goto0 = 1'b0; + assign dbrk3_goto1 = 1'b0; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + dbrk_trigout <= 0; + dbrk_break_pulse <= 0; + dbrk_traceoff <= 0; + dbrk_traceon <= 0; + dbrk_traceme <= 0; + dbrk_goto0 <= 0; + dbrk_goto1 <= 0; + end + else + begin + dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; + dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; + dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; + dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; + dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; + dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; + dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_itrace ( + // inputs: + clk, + dbrk_traceoff, + dbrk_traceon, + jdo, + jrst_n, + take_action_tracectrl, + trc_enb, + xbrk_traceoff, + xbrk_traceon, + xbrk_wrap_traceoff, + + // outputs: + dct_buffer, + dct_count, + itm, + trc_ctrl, + trc_on + ) +; + + output [ 29: 0] dct_buffer; + output [ 3: 0] dct_count; + output [ 35: 0] itm; + output [ 15: 0] trc_ctrl; + output trc_on; + input clk; + input dbrk_traceoff; + input dbrk_traceon; + input [ 15: 0] jdo; + input jrst_n; + input take_action_tracectrl; + input trc_enb; + input xbrk_traceoff; + input xbrk_traceon; + input xbrk_wrap_traceoff; + + wire curr_pid; + reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] dct_code; + reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire dct_is_taken; + wire [ 31: 0] excaddr; + wire instr_retired; + wire is_advanced_exception; + wire is_cond_dct; + wire is_dct; + wire is_exception_no_break; + wire is_fast_tlb_miss_exception; + wire is_idct; + reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire not_in_debug_mode; + reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_dct_outcome_in_sync; + wire record_itrace; + wire [ 31: 0] retired_pcb; + reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] sync_code; + wire [ 6: 0] sync_interval; + wire sync_pending; + reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 6: 0] sync_timer_next; + reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire [ 15: 0] trc_ctrl; + reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire trc_on; + assign is_cond_dct = 1'b0; + assign is_dct = 1'b0; + assign dct_is_taken = 1'b0; + assign is_idct = 1'b0; + assign retired_pcb = 32'b0; + assign not_in_debug_mode = 1'b0; + assign instr_retired = 1'b0; + assign is_advanced_exception = 1'b0; + assign is_exception_no_break = 1'b0; + assign is_fast_tlb_miss_exception = 1'b0; + assign curr_pid = 1'b0; + assign excaddr = 32'b0; + assign sync_code = trc_ctrl[3 : 2]; + assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; + assign sync_pending = sync_timer == 0; + assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; + assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); + assign record_itrace = trc_on & trc_ctrl[4]; + assign dct_code = {is_cond_dct, dct_is_taken}; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + trc_clear <= 0; + else + trc_clear <= ~trc_enb & + take_action_tracectrl & jdo[4]; + + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else if (trc_clear || (!0 && !0)) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else + begin + if (!prev_pid_valid) + begin + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if (instr_retired | is_advanced_exception) + begin + if (~record_itrace) + pending_frametype <= 4'b1010; + else if (is_exception_no_break) + begin + pending_frametype <= 4'b0010; + pending_excaddr <= excaddr; + if (is_fast_tlb_miss_exception) + pending_exctype <= 1'b1; + else + pending_exctype <= 1'b0; + end + else if (is_idct) + pending_frametype <= 4'b1001; + else if (record_dct_outcome_in_sync) + pending_frametype <= 4'b1000; + else if (!is_dct & snapped_pid) + begin + pending_frametype <= 4'b0011; + pending_curr_pid <= snapped_curr_pid; + pending_prev_pid <= snapped_prev_pid; + snapped_pid <= 0; + end + else + pending_frametype <= 4'b0000; + if ((dct_count != 0) & + (~record_itrace | + is_exception_no_break | + is_idct | + record_dct_outcome_in_sync | + (!is_dct & snapped_pid))) + begin + itm <= {4'b0001, dct_buffer, 2'b00}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + begin + if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) + begin + dct_buffer <= {dct_code, dct_buffer[29 : 2]}; + dct_count <= dct_count + 1; + end + if (record_itrace & (pending_frametype == 4'b0010)) + itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; + else if (record_itrace & ( + (pending_frametype == 4'b1000) | + (pending_frametype == 4'b1010) | + (pending_frametype == 4'b1001))) + begin + itm <= {pending_frametype, retired_pcb}; + sync_timer <= sync_interval; + if (0 & + ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & + !snapped_pid & prev_pid_valid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + end + end + else if (record_itrace & + 0 & (pending_frametype == 4'b0011)) + itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; + else if (record_itrace & is_dct) + begin + if (dct_count == 4'd15) + begin + itm <= {4'b0001, dct_code, dct_buffer}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + itm <= 4'b0000; + end + else + itm <= {4'b0000, 32'b0}; + end + end + else + itm <= {4'b0000, 32'b0}; + end + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_ctrl_reg[0] <= 1'b0; + trc_ctrl_reg[1] <= 1'b0; + trc_ctrl_reg[3 : 2] <= 2'b00; + trc_ctrl_reg[4] <= 1'b0; + trc_ctrl_reg[7 : 5] <= 3'b000; + trc_ctrl_reg[8] <= 0; + trc_ctrl_reg[9] <= 1'b0; + trc_ctrl_reg[10] <= 1'b0; + end + else if (take_action_tracectrl) + begin + trc_ctrl_reg[0] <= jdo[5]; + trc_ctrl_reg[1] <= jdo[6]; + trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; + trc_ctrl_reg[4] <= jdo[9]; + trc_ctrl_reg[9] <= jdo[14]; + trc_ctrl_reg[10] <= jdo[2]; + if (0) + trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; + if (0 & 0) + trc_ctrl_reg[8] <= jdo[13]; + end + else if (xbrk_wrap_traceoff) + begin + trc_ctrl_reg[1] <= 0; + trc_ctrl_reg[0] <= 0; + end + else if (dbrk_traceoff | xbrk_traceoff) + trc_ctrl_reg[1] <= 0; + else if (trc_ctrl_reg[0] & + (dbrk_traceon | xbrk_traceon)) + trc_ctrl_reg[1] <= 1; + end + + + assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; + assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_td_mode ( + // inputs: + ctrl, + + // outputs: + td_mode + ) +; + + output [ 3: 0] td_mode; + input [ 8: 0] ctrl; + + wire [ 2: 0] ctrl_bits_for_mux; + reg [ 3: 0] td_mode; + assign ctrl_bits_for_mux = ctrl[7 : 5]; + always @(ctrl_bits_for_mux) + begin + case (ctrl_bits_for_mux) + + 3'b000: begin + td_mode = 4'b0000; + end // 3'b000 + + 3'b001: begin + td_mode = 4'b1000; + end // 3'b001 + + 3'b010: begin + td_mode = 4'b0100; + end // 3'b010 + + 3'b011: begin + td_mode = 4'b1100; + end // 3'b011 + + 3'b100: begin + td_mode = 4'b0010; + end // 3'b100 + + 3'b101: begin + td_mode = 4'b1010; + end // 3'b101 + + 3'b110: begin + td_mode = 4'b0101; + end // 3'b110 + + 3'b111: begin + td_mode = 4'b1111; + end // 3'b111 + + endcase // ctrl_bits_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dtrace ( + // inputs: + clk, + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + jrst_n, + trc_ctrl, + + // outputs: + atm, + dtm + ) +; + + output [ 35: 0] atm; + output [ 35: 0] dtm; + input clk; + input [ 18: 0] cpu_d_address; + input cpu_d_read; + input [ 31: 0] cpu_d_readdata; + input cpu_d_wait; + input cpu_d_write; + input [ 31: 0] cpu_d_writedata; + input jrst_n; + input [ 15: 0] trc_ctrl; + + reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 31: 0] cpu_d_address_0_padded; + wire [ 31: 0] cpu_d_readdata_0_padded; + wire [ 31: 0] cpu_d_writedata_0_padded; + reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_load_addr; + wire record_load_data; + wire record_store_addr; + wire record_store_data; + wire [ 3: 0] td_mode_trc_ctrl; + assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; + assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; + assign cpu_d_address_0_padded = cpu_d_address | 32'b0; + //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance + nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode + ( + .ctrl (trc_ctrl[8 : 0]), + .td_mode (td_mode_trc_ctrl) + ); + + assign {record_load_addr, record_store_addr, + record_load_data, record_store_data} = td_mode_trc_ctrl; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + atm <= 0; + dtm <= 0; + end + else if (0) + begin + if (cpu_d_write & ~cpu_d_wait & record_store_addr) + atm <= {4'b0101, cpu_d_address_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_addr) + atm <= {4'b0100, cpu_d_address_0_padded}; + else + atm <= {4'b0000, cpu_d_address_0_padded}; + if (cpu_d_write & ~cpu_d_wait & record_store_data) + dtm <= {4'b0111, cpu_d_writedata_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_data) + dtm <= {4'b0110, cpu_d_readdata_0_padded}; + else + dtm <= {4'b0000, cpu_d_readdata_0_padded}; + end + else + begin + atm <= 0; + dtm <= 0; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_compute_tm_count ( + // inputs: + atm_valid, + dtm_valid, + itm_valid, + + // outputs: + compute_tm_count + ) +; + + output [ 1: 0] compute_tm_count; + input atm_valid; + input dtm_valid; + input itm_valid; + + reg [ 1: 0] compute_tm_count; + wire [ 2: 0] switch_for_mux; + assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; + always @(switch_for_mux) + begin + case (switch_for_mux) + + 3'b000: begin + compute_tm_count = 0; + end // 3'b000 + + 3'b001: begin + compute_tm_count = 1; + end // 3'b001 + + 3'b010: begin + compute_tm_count = 1; + end // 3'b010 + + 3'b011: begin + compute_tm_count = 2; + end // 3'b011 + + 3'b100: begin + compute_tm_count = 1; + end // 3'b100 + + 3'b101: begin + compute_tm_count = 2; + end // 3'b101 + + 3'b110: begin + compute_tm_count = 2; + end // 3'b110 + + 3'b111: begin + compute_tm_count = 3; + end // 3'b111 + + endcase // switch_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifowp_inc ( + // inputs: + free2, + free3, + tm_count, + + // outputs: + fifowp_inc + ) +; + + output [ 3: 0] fifowp_inc; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 3: 0] fifowp_inc; + always @(free2 or free3 or tm_count) + begin + if (free3 & (tm_count == 3)) + fifowp_inc = 3; + else if (free2 & (tm_count >= 2)) + fifowp_inc = 2; + else if (tm_count >= 1) + fifowp_inc = 1; + else + fifowp_inc = 0; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifocount_inc ( + // inputs: + empty, + free2, + free3, + tm_count, + + // outputs: + fifocount_inc + ) +; + + output [ 4: 0] fifocount_inc; + input empty; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 4: 0] fifocount_inc; + always @(empty or free2 or free3 or tm_count) + begin + if (empty) + fifocount_inc = tm_count[1 : 0]; + else if (free3 & (tm_count == 3)) + fifocount_inc = 2; + else if (free2 & (tm_count >= 2)) + fifocount_inc = 1; + else if (tm_count >= 1) + fifocount_inc = 0; + else + fifocount_inc = {5{1'b1}}; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifo ( + // inputs: + atm, + clk, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dct_buffer, + dct_count, + dtm, + itm, + jrst_n, + reset_n, + test_ending, + test_has_ended, + trc_on, + + // outputs: + tw + ) +; + + output [ 35: 0] tw; + input [ 35: 0] atm; + input clk; + input dbrk_traceme; + input dbrk_traceoff; + input dbrk_traceon; + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input [ 35: 0] dtm; + input [ 35: 0] itm; + input jrst_n; + input reset_n; + input test_ending; + input test_has_ended; + input trc_on; + + wire atm_valid; + wire [ 1: 0] compute_tm_count_tm_count; + wire dtm_valid; + wire empty; + reg [ 35: 0] fifo_0; + wire fifo_0_enable; + wire [ 35: 0] fifo_0_mux; + reg [ 35: 0] fifo_1; + reg [ 35: 0] fifo_10; + wire fifo_10_enable; + wire [ 35: 0] fifo_10_mux; + reg [ 35: 0] fifo_11; + wire fifo_11_enable; + wire [ 35: 0] fifo_11_mux; + reg [ 35: 0] fifo_12; + wire fifo_12_enable; + wire [ 35: 0] fifo_12_mux; + reg [ 35: 0] fifo_13; + wire fifo_13_enable; + wire [ 35: 0] fifo_13_mux; + reg [ 35: 0] fifo_14; + wire fifo_14_enable; + wire [ 35: 0] fifo_14_mux; + reg [ 35: 0] fifo_15; + wire fifo_15_enable; + wire [ 35: 0] fifo_15_mux; + wire fifo_1_enable; + wire [ 35: 0] fifo_1_mux; + reg [ 35: 0] fifo_2; + wire fifo_2_enable; + wire [ 35: 0] fifo_2_mux; + reg [ 35: 0] fifo_3; + wire fifo_3_enable; + wire [ 35: 0] fifo_3_mux; + reg [ 35: 0] fifo_4; + wire fifo_4_enable; + wire [ 35: 0] fifo_4_mux; + reg [ 35: 0] fifo_5; + wire fifo_5_enable; + wire [ 35: 0] fifo_5_mux; + reg [ 35: 0] fifo_6; + wire fifo_6_enable; + wire [ 35: 0] fifo_6_mux; + reg [ 35: 0] fifo_7; + wire fifo_7_enable; + wire [ 35: 0] fifo_7_mux; + reg [ 35: 0] fifo_8; + wire fifo_8_enable; + wire [ 35: 0] fifo_8_mux; + reg [ 35: 0] fifo_9; + wire fifo_9_enable; + wire [ 35: 0] fifo_9_mux; + wire [ 35: 0] fifo_read_mux; + reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 4: 0] fifocount_inc_fifocount; + wire [ 35: 0] fifohead; + reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 3: 0] fifowp1; + wire [ 3: 0] fifowp2; + wire [ 3: 0] fifowp_inc_fifowp; + wire free2; + wire free3; + wire itm_valid; + reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 35: 0] ovr_pending_atm; + wire [ 35: 0] ovr_pending_dtm; + wire [ 1: 0] tm_count; + wire tm_count_ge1; + wire tm_count_ge2; + wire tm_count_ge3; + wire trc_this; + wire [ 35: 0] tw; + assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; + assign itm_valid = |itm[35 : 32]; + assign atm_valid = |atm[35 : 32] & trc_this; + assign dtm_valid = |dtm[35 : 32] & trc_this; + assign free2 = ~fifocount[4]; + assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; + assign empty = ~|fifocount; + assign fifowp1 = fifowp + 1; + assign fifowp2 = fifowp + 2; + //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance + nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count + ( + .atm_valid (atm_valid), + .compute_tm_count (compute_tm_count_tm_count), + .dtm_valid (dtm_valid), + .itm_valid (itm_valid) + ); + + assign tm_count = compute_tm_count_tm_count; + //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp + ( + .fifowp_inc (fifowp_inc_fifowp), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount + ( + .empty (empty), + .fifocount_inc (fifocount_inc_fifocount), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance + nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench + ( + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .test_ending (test_ending), + .test_has_ended (test_has_ended) + ); + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + fiforp <= 0; + fifowp <= 0; + fifocount <= 0; + ovf_pending <= 1; + end + else + begin + fifowp <= fifowp + fifowp_inc_fifowp; + fifocount <= fifocount + fifocount_inc_fifocount; + if (~empty) + fiforp <= fiforp + 1; + if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) + ovf_pending <= 1; + else if (atm_valid | dtm_valid) + ovf_pending <= 0; + end + end + + + assign fifohead = fifo_read_mux; + assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; + assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_0 <= 0; + else if (fifo_0_enable) + fifo_0 <= fifo_0_mux; + end + + + assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : + (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_1 <= 0; + else if (fifo_1_enable) + fifo_1 <= fifo_1_mux; + end + + + assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : + (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_2 <= 0; + else if (fifo_2_enable) + fifo_2 <= fifo_2_mux; + end + + + assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : + (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_3 <= 0; + else if (fifo_3_enable) + fifo_3 <= fifo_3_mux; + end + + + assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : + (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_4 <= 0; + else if (fifo_4_enable) + fifo_4 <= fifo_4_mux; + end + + + assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : + (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_5 <= 0; + else if (fifo_5_enable) + fifo_5 <= fifo_5_mux; + end + + + assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : + (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_6 <= 0; + else if (fifo_6_enable) + fifo_6 <= fifo_6_mux; + end + + + assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : + (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_7 <= 0; + else if (fifo_7_enable) + fifo_7 <= fifo_7_mux; + end + + + assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : + (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_8 <= 0; + else if (fifo_8_enable) + fifo_8 <= fifo_8_mux; + end + + + assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : + (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_9 <= 0; + else if (fifo_9_enable) + fifo_9 <= fifo_9_mux; + end + + + assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : + (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_10 <= 0; + else if (fifo_10_enable) + fifo_10 <= fifo_10_mux; + end + + + assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : + (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_11 <= 0; + else if (fifo_11_enable) + fifo_11 <= fifo_11_mux; + end + + + assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : + (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_12 <= 0; + else if (fifo_12_enable) + fifo_12 <= fifo_12_mux; + end + + + assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : + (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_13 <= 0; + else if (fifo_13_enable) + fifo_13 <= fifo_13_mux; + end + + + assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : + (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_14 <= 0; + else if (fifo_14_enable) + fifo_14 <= fifo_14_mux; + end + + + assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : + (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_15 <= 0; + else if (fifo_15_enable) + fifo_15 <= fifo_15_mux; + end + + + assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : + (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign tm_count_ge1 = |tm_count; + assign tm_count_ge2 = tm_count[1]; + assign tm_count_ge3 = &tm_count; + assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; + assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; + assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : + (fiforp == 4'd1)? fifo_1 : + (fiforp == 4'd2)? fifo_2 : + (fiforp == 4'd3)? fifo_3 : + (fiforp == 4'd4)? fifo_4 : + (fiforp == 4'd5)? fifo_5 : + (fiforp == 4'd6)? fifo_6 : + (fiforp == 4'd7)? fifo_7 : + (fiforp == 4'd8)? fifo_8 : + (fiforp == 4'd9)? fifo_9 : + (fiforp == 4'd10)? fifo_10 : + (fiforp == 4'd11)? fifo_11 : + (fiforp == 4'd12)? fifo_12 : + (fiforp == 4'd13)? fifo_13 : + (fiforp == 4'd14)? fifo_14 : + fifo_15; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_pib ( + // inputs: + clk, + clkx2, + jrst_n, + tw, + + // outputs: + tr_clk, + tr_data + ) +; + + output tr_clk; + output [ 17: 0] tr_data; + input clk; + input clkx2; + input jrst_n; + input [ 35: 0] tw; + + wire phase; + wire tr_clk; + reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 17: 0] tr_data; + reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + assign phase = x1^x2; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + x1 <= 0; + else + x1 <= ~x1; + end + + + always @(posedge clkx2 or negedge jrst_n) + begin + if (jrst_n == 0) + begin + x2 <= 0; + tr_clk_reg <= 0; + tr_data_reg <= 0; + end + else + begin + x2 <= x1; + tr_clk_reg <= ~phase; + tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; + end + end + + + assign tr_clk = 0 ? tr_clk_reg : 0; + assign tr_data = 0 ? tr_data_reg : 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_im ( + // inputs: + clk, + jdo, + jrst_n, + reset_n, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_tracemem_a, + trc_ctrl, + tw, + + // outputs: + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_enb, + trc_im_addr, + trc_wrap, + xbrk_wrap_traceoff + ) +; + + output tracemem_on; + output [ 35: 0] tracemem_trcdata; + output tracemem_tw; + output trc_enb; + output [ 6: 0] trc_im_addr; + output trc_wrap; + output xbrk_wrap_traceoff; + input clk; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_tracectrl; + input take_action_tracemem_a; + input take_action_tracemem_b; + input take_no_action_tracemem_a; + input [ 15: 0] trc_ctrl; + input [ 35: 0] tw; + + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire trc_enb; + reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 35: 0] trc_im_data; + reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire trc_on_chip; + reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire tw_valid; + wire xbrk_wrap_traceoff; + assign trc_im_data = tw; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (!0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (take_action_tracectrl && + (jdo[4] | jdo[3])) + begin + if (jdo[4]) + trc_im_addr <= 0; + if (jdo[3]) + trc_wrap <= 0; + end + else if (trc_enb & trc_on_chip & tw_valid) + begin + trc_im_addr <= trc_im_addr+1; + if (&trc_im_addr) + trc_wrap <= 1; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trc_jtag_addr <= 0; + else if (take_action_tracemem_a || + take_no_action_tracemem_a || + take_action_tracemem_b) + trc_jtag_addr <= take_action_tracemem_a ? + jdo[35 : 19] : + trc_jtag_addr + 1; + + end + + + assign trc_enb = trc_ctrl[0]; + assign trc_on_chip = ~trc_ctrl[8]; + assign tw_valid = |trc_im_data[35 : 32]; + assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; + assign tracemem_tw = trc_wrap; + assign tracemem_on = trc_enb; + assign tracemem_trcdata = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_performance_monitors +; + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci ( + // inputs: + D_valid, + E_st_data, + E_valid, + F_pc, + address_nxt, + av_ld_data_aligned_filtered, + byteenable_nxt, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugaccess_nxt, + hbreak_enabled, + read_nxt, + reset, + reset_n, + test_ending, + test_has_ended, + write_nxt, + writedata_nxt, + + // outputs: + jtag_debug_module_debugaccess_to_roms, + oci_hbreak_req, + oci_ienable, + oci_single_step_mode, + readdata, + resetrequest, + waitrequest + ) +; + + output jtag_debug_module_debugaccess_to_roms; + output oci_hbreak_req; + output [ 31: 0] oci_ienable; + output oci_single_step_mode; + output [ 31: 0] readdata; + output resetrequest; + output waitrequest; + input D_valid; + input [ 31: 0] E_st_data; + input E_valid; + input [ 16: 0] F_pc; + input [ 8: 0] address_nxt; + input [ 31: 0] av_ld_data_aligned_filtered; + input [ 3: 0] byteenable_nxt; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugaccess_nxt; + input hbreak_enabled; + input read_nxt; + input reset; + input reset_n; + input test_ending; + input test_has_ended; + input write_nxt; + input [ 31: 0] writedata_nxt; + + wire [ 31: 0] MonDReg; + reg [ 8: 0] address; + wire [ 35: 0] atm; + wire [ 31: 0] break_readreg; + reg [ 3: 0] byteenable; + wire clkx2; + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk_break; + wire dbrk_goto0; + wire dbrk_goto1; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire dbrk_traceme; + wire dbrk_traceoff; + wire dbrk_traceon; + wire dbrk_trigout; + wire [ 29: 0] dct_buffer; + wire [ 3: 0] dct_count; + reg debugaccess; + wire debugack; + wire debugreq; + wire [ 35: 0] dtm; + wire dummy_sink; + wire [ 35: 0] itm; + wire [ 37: 0] jdo; + wire jrst_n; + wire jtag_debug_module_debugaccess_to_roms; + wire monitor_error; + wire monitor_go; + wire monitor_ready; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire [ 31: 0] oci_reg_readdata; + wire oci_single_step_mode; + wire [ 31: 0] ociram_readdata; + wire ocireg_ers; + wire ocireg_mrs; + reg read; + reg [ 31: 0] readdata; + wire resetlatch; + wire resetrequest; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_ocireg; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire tr_clk; + wire [ 17: 0] tr_data; + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire [ 15: 0] trc_ctrl; + wire trc_enb; + wire [ 6: 0] trc_im_addr; + wire trc_on; + wire trc_wrap; + wire trigbrktype; + wire trigger_state_0; + wire trigger_state_1; + wire trigout; + wire [ 35: 0] tw; + wire waitrequest; + reg write; + reg [ 31: 0] writedata; + wire xbrk_break; + wire [ 7: 0] xbrk_ctrl0; + wire [ 7: 0] xbrk_ctrl1; + wire [ 7: 0] xbrk_ctrl2; + wire [ 7: 0] xbrk_ctrl3; + wire xbrk_goto0; + wire xbrk_goto1; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + wire xbrk_wrap_traceoff; + nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug + ( + .clk (clk), + .dbrk_break (dbrk_break), + .debugack (debugack), + .debugreq (debugreq), + .hbreak_enabled (hbreak_enabled), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_hbreak_req (oci_hbreak_req), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset (reset), + .resetlatch (resetlatch), + .resetrequest (resetrequest), + .st_ready_test_idle (st_ready_test_idle), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocireg (take_action_ocireg), + .xbrk_break (xbrk_break) + ); + + nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem + ( + .MonDReg (MonDReg), + .address (address), + .byteenable (byteenable), + .clk (clk), + .debugaccess (debugaccess), + .jdo (jdo), + .jrst_n (jrst_n), + .ociram_readdata (ociram_readdata), + .read (read), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .waitrequest (waitrequest), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg + ( + .address (address), + .clk (clk), + .debugaccess (debugaccess), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_ienable (oci_ienable), + .oci_reg_readdata (oci_reg_readdata), + .oci_single_step_mode (oci_single_step_mode), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset_n (reset_n), + .take_action_ocireg (take_action_ocireg), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break + ( + .break_readreg (break_readreg), + .clk (clk), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .trigbrktype (trigbrktype), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1) + ); + + nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk + ( + .D_valid (D_valid), + .E_valid (E_valid), + .F_pc (F_pc), + .clk (clk), + .reset_n (reset_n), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_break (xbrk_break), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_trigout (xbrk_trigout) + ); + + nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk + ( + .E_st_data (E_st_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dbrk_trigout (dbrk_trigout), + .debugack (debugack), + .reset_n (reset_n) + ); + + nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace + ( + .clk (clk), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .itm (itm), + .jdo (jdo), + .jrst_n (jrst_n), + .take_action_tracectrl (take_action_tracectrl), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_on (trc_on), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace + ( + .atm (atm), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .dtm (dtm), + .jrst_n (jrst_n), + .trc_ctrl (trc_ctrl) + ); + + nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo + ( + .atm (atm), + .clk (clk), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .dtm (dtm), + .itm (itm), + .jrst_n (jrst_n), + .reset_n (reset_n), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .trc_on (trc_on), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib + ( + .clk (clk), + .clkx2 (clkx2), + .jrst_n (jrst_n), + .tr_clk (tr_clk), + .tr_data (tr_data), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im + ( + .clk (clk), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_im_addr (trc_im_addr), + .trc_wrap (trc_wrap), + .tw (tw), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + assign trigout = dbrk_trigout | xbrk_trigout; + assign jtag_debug_module_debugaccess_to_roms = debugack; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + address <= 0; + else + address <= address_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + byteenable <= 0; + else + byteenable <= byteenable_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + writedata <= 0; + else + writedata <= writedata_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + debugaccess <= 0; + else + debugaccess <= debugaccess_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + read <= 0; + else + read <= read ? waitrequest : read_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + write <= 0; + else + write <= write ? waitrequest : write_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + readdata <= 0; + else + readdata <= address[8] ? oci_reg_readdata : ociram_readdata; + end + + + nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .clk (clk), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .st_ready_test_idle (st_ready_test_idle), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1) + ); + + //dummy sink, which is an e_mux + assign dummy_sink = tr_clk | + tr_data | + trigout | + debugack; + + assign debugreq = 0; + assign clkx2 = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor ( + // inputs: + clk, + d_irq, + d_readdata, + d_waitrequest, + i_readdata, + i_waitrequest, + jtag_debug_module_address, + jtag_debug_module_byteenable, + jtag_debug_module_debugaccess, + jtag_debug_module_read, + jtag_debug_module_write, + jtag_debug_module_writedata, + reset_n, + + // outputs: + d_address, + d_byteenable, + d_read, + d_write, + d_writedata, + i_address, + i_read, + jtag_debug_module_debugaccess_to_roms, + jtag_debug_module_readdata, + jtag_debug_module_resetrequest, + jtag_debug_module_waitrequest, + no_ci_readra + ) +; + + output [ 18: 0] d_address; + output [ 3: 0] d_byteenable; + output d_read; + output d_write; + output [ 31: 0] d_writedata; + output [ 18: 0] i_address; + output i_read; + output jtag_debug_module_debugaccess_to_roms; + output [ 31: 0] jtag_debug_module_readdata; + output jtag_debug_module_resetrequest; + output jtag_debug_module_waitrequest; + output no_ci_readra; + input clk; + input [ 31: 0] d_irq; + input [ 31: 0] d_readdata; + input d_waitrequest; + input [ 31: 0] i_readdata; + input i_waitrequest; + input [ 8: 0] jtag_debug_module_address; + input [ 3: 0] jtag_debug_module_byteenable; + input jtag_debug_module_debugaccess; + input jtag_debug_module_read; + input jtag_debug_module_write; + input [ 31: 0] jtag_debug_module_writedata; + input reset_n; + + wire [ 1: 0] D_compare_op; + wire D_ctrl_alu_force_xor; + wire D_ctrl_alu_signed_comparison; + wire D_ctrl_alu_subtract; + wire D_ctrl_b_is_dst; + wire D_ctrl_br; + wire D_ctrl_br_cmp; + wire D_ctrl_br_uncond; + wire D_ctrl_break; + wire D_ctrl_crst; + wire D_ctrl_custom; + wire D_ctrl_custom_multi; + wire D_ctrl_exception; + wire D_ctrl_force_src2_zero; + wire D_ctrl_hi_imm16; + wire D_ctrl_ignore_dst; + wire D_ctrl_implicit_dst_eretaddr; + wire D_ctrl_implicit_dst_retaddr; + wire D_ctrl_jmp_direct; + wire D_ctrl_jmp_indirect; + wire D_ctrl_ld; + wire D_ctrl_ld_io; + wire D_ctrl_ld_non_io; + wire D_ctrl_ld_signed; + wire D_ctrl_logic; + wire D_ctrl_rdctl_inst; + wire D_ctrl_retaddr; + wire D_ctrl_rot_right; + wire D_ctrl_shift_logical; + wire D_ctrl_shift_right_arith; + wire D_ctrl_shift_rot; + wire D_ctrl_shift_rot_right; + wire D_ctrl_src2_choose_imm; + wire D_ctrl_st; + wire D_ctrl_uncond_cti_non_br; + wire D_ctrl_unsigned_lo_imm16; + wire D_ctrl_wrctl_inst; + wire [ 4: 0] D_dst_regnum; + wire [ 55: 0] D_inst; + reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 4: 0] D_iw_a; + wire [ 4: 0] D_iw_b; + wire [ 4: 0] D_iw_c; + wire [ 2: 0] D_iw_control_regnum; + wire [ 7: 0] D_iw_custom_n; + wire D_iw_custom_readra; + wire D_iw_custom_readrb; + wire D_iw_custom_writerc; + wire [ 15: 0] D_iw_imm16; + wire [ 25: 0] D_iw_imm26; + wire [ 4: 0] D_iw_imm5; + wire [ 1: 0] D_iw_memsz; + wire [ 5: 0] D_iw_op; + wire [ 5: 0] D_iw_opx; + wire [ 4: 0] D_iw_shift_imm5; + wire [ 4: 0] D_iw_trap_break_imm5; + wire [ 16: 0] D_jmp_direct_target_waddr; + wire [ 1: 0] D_logic_op; + wire [ 1: 0] D_logic_op_raw; + wire D_mem16; + wire D_mem32; + wire D_mem8; + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + reg D_valid; + wire [ 55: 0] D_vinst; + wire D_wr_dst_reg; + wire [ 31: 0] E_alu_result; + reg E_alu_sub; + wire [ 32: 0] E_arith_result; + wire [ 31: 0] E_arith_src1; + wire [ 31: 0] E_arith_src2; + wire E_ci_multi_stall; + wire [ 31: 0] E_ci_result; + wire E_cmp_result; + wire [ 31: 0] E_control_rd_data; + wire E_eq; + reg E_invert_arith_src_msb; + wire E_ld_stall; + wire [ 31: 0] E_logic_result; + wire E_logic_result_is_0; + wire E_lt; + wire [ 18: 0] E_mem_baddr; + wire [ 3: 0] E_mem_byte_en; + reg E_new_inst; + reg [ 4: 0] E_shift_rot_cnt; + wire [ 4: 0] E_shift_rot_cnt_nxt; + wire E_shift_rot_done; + wire E_shift_rot_fill_bit; + reg [ 31: 0] E_shift_rot_result; + wire [ 31: 0] E_shift_rot_result_nxt; + wire E_shift_rot_stall; + reg [ 31: 0] E_src1; + reg [ 31: 0] E_src2; + wire [ 31: 0] E_st_data; + wire E_st_stall; + wire E_stall; + reg E_valid; + wire [ 55: 0] E_vinst; + wire E_wrctl_bstatus; + wire E_wrctl_estatus; + wire E_wrctl_ienable; + wire E_wrctl_status; + wire [ 31: 0] F_av_iw; + wire [ 4: 0] F_av_iw_a; + wire [ 4: 0] F_av_iw_b; + wire [ 4: 0] F_av_iw_c; + wire [ 2: 0] F_av_iw_control_regnum; + wire [ 7: 0] F_av_iw_custom_n; + wire F_av_iw_custom_readra; + wire F_av_iw_custom_readrb; + wire F_av_iw_custom_writerc; + wire [ 15: 0] F_av_iw_imm16; + wire [ 25: 0] F_av_iw_imm26; + wire [ 4: 0] F_av_iw_imm5; + wire [ 1: 0] F_av_iw_memsz; + wire [ 5: 0] F_av_iw_op; + wire [ 5: 0] F_av_iw_opx; + wire [ 4: 0] F_av_iw_shift_imm5; + wire [ 4: 0] F_av_iw_trap_break_imm5; + wire F_av_mem16; + wire F_av_mem32; + wire F_av_mem8; + wire [ 55: 0] F_inst; + wire [ 31: 0] F_iw; + wire [ 4: 0] F_iw_a; + wire [ 4: 0] F_iw_b; + wire [ 4: 0] F_iw_c; + wire [ 2: 0] F_iw_control_regnum; + wire [ 7: 0] F_iw_custom_n; + wire F_iw_custom_readra; + wire F_iw_custom_readrb; + wire F_iw_custom_writerc; + wire [ 15: 0] F_iw_imm16; + wire [ 25: 0] F_iw_imm26; + wire [ 4: 0] F_iw_imm5; + wire [ 1: 0] F_iw_memsz; + wire [ 5: 0] F_iw_op; + wire [ 5: 0] F_iw_opx; + wire [ 4: 0] F_iw_shift_imm5; + wire [ 4: 0] F_iw_trap_break_imm5; + wire F_mem16; + wire F_mem32; + wire F_mem8; + wire F_op_add; + wire F_op_addi; + wire F_op_and; + wire F_op_andhi; + wire F_op_andi; + wire F_op_beq; + wire F_op_bge; + wire F_op_bgeu; + wire F_op_blt; + wire F_op_bltu; + wire F_op_bne; + wire F_op_br; + wire F_op_break; + wire F_op_bret; + wire F_op_call; + wire F_op_callr; + wire F_op_cmpeq; + wire F_op_cmpeqi; + wire F_op_cmpge; + wire F_op_cmpgei; + wire F_op_cmpgeu; + wire F_op_cmpgeui; + wire F_op_cmplt; + wire F_op_cmplti; + wire F_op_cmpltu; + wire F_op_cmpltui; + wire F_op_cmpne; + wire F_op_cmpnei; + wire F_op_crst; + wire F_op_custom; + wire F_op_div; + wire F_op_divu; + wire F_op_eret; + wire F_op_flushd; + wire F_op_flushda; + wire F_op_flushi; + wire F_op_flushp; + wire F_op_hbreak; + wire F_op_initd; + wire F_op_initda; + wire F_op_initi; + wire F_op_intr; + wire F_op_jmp; + wire F_op_jmpi; + wire F_op_ldb; + wire F_op_ldbio; + wire F_op_ldbu; + wire F_op_ldbuio; + wire F_op_ldh; + wire F_op_ldhio; + wire F_op_ldhu; + wire F_op_ldhuio; + wire F_op_ldl; + wire F_op_ldw; + wire F_op_ldwio; + wire F_op_mul; + wire F_op_muli; + wire F_op_mulxss; + wire F_op_mulxsu; + wire F_op_mulxuu; + wire F_op_nextpc; + wire F_op_nor; + wire F_op_opx; + wire F_op_or; + wire F_op_orhi; + wire F_op_ori; + wire F_op_rdctl; + wire F_op_rdprs; + wire F_op_ret; + wire F_op_rol; + wire F_op_roli; + wire F_op_ror; + wire F_op_rsv02; + wire F_op_rsv09; + wire F_op_rsv10; + wire F_op_rsv17; + wire F_op_rsv18; + wire F_op_rsv25; + wire F_op_rsv26; + wire F_op_rsv33; + wire F_op_rsv34; + wire F_op_rsv41; + wire F_op_rsv42; + wire F_op_rsv49; + wire F_op_rsv57; + wire F_op_rsv61; + wire F_op_rsv62; + wire F_op_rsv63; + wire F_op_rsvx00; + wire F_op_rsvx10; + wire F_op_rsvx15; + wire F_op_rsvx17; + wire F_op_rsvx21; + wire F_op_rsvx25; + wire F_op_rsvx33; + wire F_op_rsvx34; + wire F_op_rsvx35; + wire F_op_rsvx42; + wire F_op_rsvx43; + wire F_op_rsvx44; + wire F_op_rsvx47; + wire F_op_rsvx50; + wire F_op_rsvx51; + wire F_op_rsvx55; + wire F_op_rsvx56; + wire F_op_rsvx60; + wire F_op_rsvx63; + wire F_op_sll; + wire F_op_slli; + wire F_op_sra; + wire F_op_srai; + wire F_op_srl; + wire F_op_srli; + wire F_op_stb; + wire F_op_stbio; + wire F_op_stc; + wire F_op_sth; + wire F_op_sthio; + wire F_op_stw; + wire F_op_stwio; + wire F_op_sub; + wire F_op_sync; + wire F_op_trap; + wire F_op_wrctl; + wire F_op_wrprs; + wire F_op_xor; + wire F_op_xorhi; + wire F_op_xori; + reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire F_pc_en; + wire [ 16: 0] F_pc_no_crst_nxt; + wire [ 16: 0] F_pc_nxt; + wire [ 16: 0] F_pc_plus_one; + wire [ 1: 0] F_pc_sel_nxt; + wire [ 18: 0] F_pcb; + wire [ 18: 0] F_pcb_nxt; + wire [ 18: 0] F_pcb_plus_four; + wire F_valid; + wire [ 55: 0] F_vinst; + reg [ 1: 0] R_compare_op; + reg R_ctrl_alu_force_xor; + wire R_ctrl_alu_force_xor_nxt; + reg R_ctrl_alu_signed_comparison; + wire R_ctrl_alu_signed_comparison_nxt; + reg R_ctrl_alu_subtract; + wire R_ctrl_alu_subtract_nxt; + reg R_ctrl_b_is_dst; + wire R_ctrl_b_is_dst_nxt; + reg R_ctrl_br; + reg R_ctrl_br_cmp; + wire R_ctrl_br_cmp_nxt; + wire R_ctrl_br_nxt; + reg R_ctrl_br_uncond; + wire R_ctrl_br_uncond_nxt; + reg R_ctrl_break; + wire R_ctrl_break_nxt; + reg R_ctrl_crst; + wire R_ctrl_crst_nxt; + reg R_ctrl_custom; + reg R_ctrl_custom_multi; + wire R_ctrl_custom_multi_nxt; + wire R_ctrl_custom_nxt; + reg R_ctrl_exception; + wire R_ctrl_exception_nxt; + reg R_ctrl_force_src2_zero; + wire R_ctrl_force_src2_zero_nxt; + reg R_ctrl_hi_imm16; + wire R_ctrl_hi_imm16_nxt; + reg R_ctrl_ignore_dst; + wire R_ctrl_ignore_dst_nxt; + reg R_ctrl_implicit_dst_eretaddr; + wire R_ctrl_implicit_dst_eretaddr_nxt; + reg R_ctrl_implicit_dst_retaddr; + wire R_ctrl_implicit_dst_retaddr_nxt; + reg R_ctrl_jmp_direct; + wire R_ctrl_jmp_direct_nxt; + reg R_ctrl_jmp_indirect; + wire R_ctrl_jmp_indirect_nxt; + reg R_ctrl_ld; + reg R_ctrl_ld_io; + wire R_ctrl_ld_io_nxt; + reg R_ctrl_ld_non_io; + wire R_ctrl_ld_non_io_nxt; + wire R_ctrl_ld_nxt; + reg R_ctrl_ld_signed; + wire R_ctrl_ld_signed_nxt; + reg R_ctrl_logic; + wire R_ctrl_logic_nxt; + reg R_ctrl_rdctl_inst; + wire R_ctrl_rdctl_inst_nxt; + reg R_ctrl_retaddr; + wire R_ctrl_retaddr_nxt; + reg R_ctrl_rot_right; + wire R_ctrl_rot_right_nxt; + reg R_ctrl_shift_logical; + wire R_ctrl_shift_logical_nxt; + reg R_ctrl_shift_right_arith; + wire R_ctrl_shift_right_arith_nxt; + reg R_ctrl_shift_rot; + wire R_ctrl_shift_rot_nxt; + reg R_ctrl_shift_rot_right; + wire R_ctrl_shift_rot_right_nxt; + reg R_ctrl_src2_choose_imm; + wire R_ctrl_src2_choose_imm_nxt; + reg R_ctrl_st; + wire R_ctrl_st_nxt; + reg R_ctrl_uncond_cti_non_br; + wire R_ctrl_uncond_cti_non_br_nxt; + reg R_ctrl_unsigned_lo_imm16; + wire R_ctrl_unsigned_lo_imm16_nxt; + reg R_ctrl_wrctl_inst; + wire R_ctrl_wrctl_inst_nxt; + reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire R_en; + reg [ 1: 0] R_logic_op; + wire [ 31: 0] R_rf_a; + wire [ 31: 0] R_rf_b; + wire [ 31: 0] R_src1; + wire [ 31: 0] R_src2; + wire [ 15: 0] R_src2_hi; + wire [ 15: 0] R_src2_lo; + reg R_src2_use_imm; + wire [ 7: 0] R_stb_data; + wire [ 15: 0] R_sth_data; + reg R_valid; + wire [ 55: 0] R_vinst; + reg R_wr_dst_reg; + reg [ 31: 0] W_alu_result; + wire W_br_taken; + reg W_bstatus_reg; + wire W_bstatus_reg_inst_nxt; + wire W_bstatus_reg_nxt; + reg W_cmp_result; + reg [ 31: 0] W_control_rd_data; + reg W_estatus_reg; + wire W_estatus_reg_inst_nxt; + wire W_estatus_reg_nxt; + reg [ 31: 0] W_ienable_reg; + wire [ 31: 0] W_ienable_reg_nxt; + reg [ 31: 0] W_ipending_reg; + wire [ 31: 0] W_ipending_reg_nxt; + wire [ 18: 0] W_mem_baddr; + wire [ 31: 0] W_rf_wr_data; + wire W_rf_wren; + wire W_status_reg; + reg W_status_reg_pie; + wire W_status_reg_pie_inst_nxt; + wire W_status_reg_pie_nxt; + reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 55: 0] W_vinst; + wire [ 31: 0] W_wr_data; + wire [ 31: 0] W_wr_data_non_zero; + wire av_fill_bit; + reg [ 1: 0] av_ld_align_cycle; + wire [ 1: 0] av_ld_align_cycle_nxt; + wire av_ld_align_one_more_cycle; + reg av_ld_aligning_data; + wire av_ld_aligning_data_nxt; + reg [ 7: 0] av_ld_byte0_data; + wire [ 7: 0] av_ld_byte0_data_nxt; + reg [ 7: 0] av_ld_byte1_data; + wire av_ld_byte1_data_en; + wire [ 7: 0] av_ld_byte1_data_nxt; + reg [ 7: 0] av_ld_byte2_data; + wire [ 7: 0] av_ld_byte2_data_nxt; + reg [ 7: 0] av_ld_byte3_data; + wire [ 7: 0] av_ld_byte3_data_nxt; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire [ 31: 0] av_ld_data_aligned_unfiltered; + wire av_ld_done; + wire av_ld_extend; + wire av_ld_getting_data; + wire av_ld_rshift8; + reg av_ld_waiting_for_data; + wire av_ld_waiting_for_data_nxt; + wire av_sign_bit; + wire [ 18: 0] d_address; + reg [ 3: 0] d_byteenable; + reg d_read; + wire d_read_nxt; + wire d_write; + wire d_write_nxt; + reg [ 31: 0] d_writedata; + reg hbreak_enabled; + reg hbreak_pending; + wire hbreak_pending_nxt; + wire hbreak_req; + wire [ 18: 0] i_address; + reg i_read; + wire i_read_nxt; + wire [ 31: 0] iactive; + wire intr_req; + wire jtag_debug_module_clk; + wire jtag_debug_module_debugaccess_to_roms; + wire [ 31: 0] jtag_debug_module_readdata; + wire jtag_debug_module_reset; + wire jtag_debug_module_resetrequest; + wire jtag_debug_module_waitrequest; + wire no_ci_readra; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire oci_single_step_mode; + wire oci_tb_hbreak_req; + wire test_ending; + wire test_has_ended; + reg wait_for_one_post_bret_inst; + //the_nios_system_nios2_processor_test_bench, which is an e_instance + nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench + ( + .D_iw (D_iw), + .D_iw_op (D_iw_op), + .D_iw_opx (D_iw_opx), + .D_valid (D_valid), + .E_valid (E_valid), + .F_pcb (F_pcb), + .F_valid (F_valid), + .R_ctrl_ld (R_ctrl_ld), + .R_ctrl_ld_non_io (R_ctrl_ld_non_io), + .R_dst_regnum (R_dst_regnum), + .R_wr_dst_reg (R_wr_dst_reg), + .W_valid (W_valid), + .W_vinst (W_vinst), + .W_wr_data (W_wr_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), + .clk (clk), + .d_address (d_address), + .d_byteenable (d_byteenable), + .d_read (d_read), + .d_write (d_write), + .d_write_nxt (d_write_nxt), + .i_address (i_address), + .i_read (i_read), + .i_readdata (i_readdata), + .i_waitrequest (i_waitrequest), + .reset_n (reset_n), + .test_has_ended (test_has_ended) + ); + + assign F_av_iw_a = F_av_iw[31 : 27]; + assign F_av_iw_b = F_av_iw[26 : 22]; + assign F_av_iw_c = F_av_iw[21 : 17]; + assign F_av_iw_custom_n = F_av_iw[13 : 6]; + assign F_av_iw_custom_readra = F_av_iw[16]; + assign F_av_iw_custom_readrb = F_av_iw[15]; + assign F_av_iw_custom_writerc = F_av_iw[14]; + assign F_av_iw_opx = F_av_iw[16 : 11]; + assign F_av_iw_op = F_av_iw[5 : 0]; + assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm16 = F_av_iw[21 : 6]; + assign F_av_iw_imm26 = F_av_iw[31 : 6]; + assign F_av_iw_memsz = F_av_iw[4 : 3]; + assign F_av_iw_control_regnum = F_av_iw[8 : 6]; + assign F_av_mem8 = F_av_iw_memsz == 2'b00; + assign F_av_mem16 = F_av_iw_memsz == 2'b01; + assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; + assign F_iw_a = F_iw[31 : 27]; + assign F_iw_b = F_iw[26 : 22]; + assign F_iw_c = F_iw[21 : 17]; + assign F_iw_custom_n = F_iw[13 : 6]; + assign F_iw_custom_readra = F_iw[16]; + assign F_iw_custom_readrb = F_iw[15]; + assign F_iw_custom_writerc = F_iw[14]; + assign F_iw_opx = F_iw[16 : 11]; + assign F_iw_op = F_iw[5 : 0]; + assign F_iw_shift_imm5 = F_iw[10 : 6]; + assign F_iw_trap_break_imm5 = F_iw[10 : 6]; + assign F_iw_imm5 = F_iw[10 : 6]; + assign F_iw_imm16 = F_iw[21 : 6]; + assign F_iw_imm26 = F_iw[31 : 6]; + assign F_iw_memsz = F_iw[4 : 3]; + assign F_iw_control_regnum = F_iw[8 : 6]; + assign F_mem8 = F_iw_memsz == 2'b00; + assign F_mem16 = F_iw_memsz == 2'b01; + assign F_mem32 = F_iw_memsz[1] == 1'b1; + assign D_iw_a = D_iw[31 : 27]; + assign D_iw_b = D_iw[26 : 22]; + assign D_iw_c = D_iw[21 : 17]; + assign D_iw_custom_n = D_iw[13 : 6]; + assign D_iw_custom_readra = D_iw[16]; + assign D_iw_custom_readrb = D_iw[15]; + assign D_iw_custom_writerc = D_iw[14]; + assign D_iw_opx = D_iw[16 : 11]; + assign D_iw_op = D_iw[5 : 0]; + assign D_iw_shift_imm5 = D_iw[10 : 6]; + assign D_iw_trap_break_imm5 = D_iw[10 : 6]; + assign D_iw_imm5 = D_iw[10 : 6]; + assign D_iw_imm16 = D_iw[21 : 6]; + assign D_iw_imm26 = D_iw[31 : 6]; + assign D_iw_memsz = D_iw[4 : 3]; + assign D_iw_control_regnum = D_iw[8 : 6]; + assign D_mem8 = D_iw_memsz == 2'b00; + assign D_mem16 = D_iw_memsz == 2'b01; + assign D_mem32 = D_iw_memsz[1] == 1'b1; + assign F_op_call = F_iw_op == 0; + assign F_op_jmpi = F_iw_op == 1; + assign F_op_ldbu = F_iw_op == 3; + assign F_op_addi = F_iw_op == 4; + assign F_op_stb = F_iw_op == 5; + assign F_op_br = F_iw_op == 6; + assign F_op_ldb = F_iw_op == 7; + assign F_op_cmpgei = F_iw_op == 8; + assign F_op_ldhu = F_iw_op == 11; + assign F_op_andi = F_iw_op == 12; + assign F_op_sth = F_iw_op == 13; + assign F_op_bge = F_iw_op == 14; + assign F_op_ldh = F_iw_op == 15; + assign F_op_cmplti = F_iw_op == 16; + assign F_op_initda = F_iw_op == 19; + assign F_op_ori = F_iw_op == 20; + assign F_op_stw = F_iw_op == 21; + assign F_op_blt = F_iw_op == 22; + assign F_op_ldw = F_iw_op == 23; + assign F_op_cmpnei = F_iw_op == 24; + assign F_op_flushda = F_iw_op == 27; + assign F_op_xori = F_iw_op == 28; + assign F_op_stc = F_iw_op == 29; + assign F_op_bne = F_iw_op == 30; + assign F_op_ldl = F_iw_op == 31; + assign F_op_cmpeqi = F_iw_op == 32; + assign F_op_ldbuio = F_iw_op == 35; + assign F_op_muli = F_iw_op == 36; + assign F_op_stbio = F_iw_op == 37; + assign F_op_beq = F_iw_op == 38; + assign F_op_ldbio = F_iw_op == 39; + assign F_op_cmpgeui = F_iw_op == 40; + assign F_op_ldhuio = F_iw_op == 43; + assign F_op_andhi = F_iw_op == 44; + assign F_op_sthio = F_iw_op == 45; + assign F_op_bgeu = F_iw_op == 46; + assign F_op_ldhio = F_iw_op == 47; + assign F_op_cmpltui = F_iw_op == 48; + assign F_op_initd = F_iw_op == 51; + assign F_op_orhi = F_iw_op == 52; + assign F_op_stwio = F_iw_op == 53; + assign F_op_bltu = F_iw_op == 54; + assign F_op_ldwio = F_iw_op == 55; + assign F_op_rdprs = F_iw_op == 56; + assign F_op_flushd = F_iw_op == 59; + assign F_op_xorhi = F_iw_op == 60; + assign F_op_rsv02 = F_iw_op == 2; + assign F_op_rsv09 = F_iw_op == 9; + assign F_op_rsv10 = F_iw_op == 10; + assign F_op_rsv17 = F_iw_op == 17; + assign F_op_rsv18 = F_iw_op == 18; + assign F_op_rsv25 = F_iw_op == 25; + assign F_op_rsv26 = F_iw_op == 26; + assign F_op_rsv33 = F_iw_op == 33; + assign F_op_rsv34 = F_iw_op == 34; + assign F_op_rsv41 = F_iw_op == 41; + assign F_op_rsv42 = F_iw_op == 42; + assign F_op_rsv49 = F_iw_op == 49; + assign F_op_rsv57 = F_iw_op == 57; + assign F_op_rsv61 = F_iw_op == 61; + assign F_op_rsv62 = F_iw_op == 62; + assign F_op_rsv63 = F_iw_op == 63; + assign F_op_eret = F_op_opx & (F_iw_opx == 1); + assign F_op_roli = F_op_opx & (F_iw_opx == 2); + assign F_op_rol = F_op_opx & (F_iw_opx == 3); + assign F_op_flushp = F_op_opx & (F_iw_opx == 4); + assign F_op_ret = F_op_opx & (F_iw_opx == 5); + assign F_op_nor = F_op_opx & (F_iw_opx == 6); + assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); + assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); + assign F_op_bret = F_op_opx & (F_iw_opx == 9); + assign F_op_ror = F_op_opx & (F_iw_opx == 11); + assign F_op_flushi = F_op_opx & (F_iw_opx == 12); + assign F_op_jmp = F_op_opx & (F_iw_opx == 13); + assign F_op_and = F_op_opx & (F_iw_opx == 14); + assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); + assign F_op_slli = F_op_opx & (F_iw_opx == 18); + assign F_op_sll = F_op_opx & (F_iw_opx == 19); + assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); + assign F_op_or = F_op_opx & (F_iw_opx == 22); + assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); + assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); + assign F_op_srli = F_op_opx & (F_iw_opx == 26); + assign F_op_srl = F_op_opx & (F_iw_opx == 27); + assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); + assign F_op_callr = F_op_opx & (F_iw_opx == 29); + assign F_op_xor = F_op_opx & (F_iw_opx == 30); + assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); + assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); + assign F_op_divu = F_op_opx & (F_iw_opx == 36); + assign F_op_div = F_op_opx & (F_iw_opx == 37); + assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); + assign F_op_mul = F_op_opx & (F_iw_opx == 39); + assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); + assign F_op_initi = F_op_opx & (F_iw_opx == 41); + assign F_op_trap = F_op_opx & (F_iw_opx == 45); + assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); + assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); + assign F_op_add = F_op_opx & (F_iw_opx == 49); + assign F_op_break = F_op_opx & (F_iw_opx == 52); + assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); + assign F_op_sync = F_op_opx & (F_iw_opx == 54); + assign F_op_sub = F_op_opx & (F_iw_opx == 57); + assign F_op_srai = F_op_opx & (F_iw_opx == 58); + assign F_op_sra = F_op_opx & (F_iw_opx == 59); + assign F_op_intr = F_op_opx & (F_iw_opx == 61); + assign F_op_crst = F_op_opx & (F_iw_opx == 62); + assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); + assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); + assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); + assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); + assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); + assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); + assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); + assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); + assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); + assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); + assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); + assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); + assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); + assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); + assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); + assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); + assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); + assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); + assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); + assign F_op_opx = F_iw_op == 58; + assign F_op_custom = F_iw_op == 50; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + assign R_en = 1'b1; + assign E_ci_result = 0; + //custom_instruction_master, which is an e_custom_instruction_master + assign no_ci_readra = 1'b0; + assign E_ci_multi_stall = 1'b0; + assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; + assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : + R_ctrl_break ? 2'b01 : + (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : + 2'b11; + + assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : + (F_pc_sel_nxt == 2'b01)? 66056 : + (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : + F_pc_plus_one; + + assign F_pc_nxt = F_pc_no_crst_nxt; + assign F_pcb_nxt = {F_pc_nxt, 2'b00}; + assign F_pc_en = W_valid; + assign F_pc_plus_one = F_pc + 1; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + F_pc <= 0; + else if (F_pc_en) + F_pc <= F_pc_nxt; + end + + + assign F_pcb = {F_pc, 2'b00}; + assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; + assign F_valid = i_read & ~i_waitrequest; + assign i_read_nxt = W_valid | (i_read & i_waitrequest); + assign i_address = {F_pc, 2'b00}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + i_read <= 1'b1; + else + i_read <= i_read_nxt; + end + + + assign oci_tb_hbreak_req = oci_hbreak_req; + assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); + assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled + : hbreak_req; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + wait_for_one_post_bret_inst <= 1'b0; + else + wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_pending <= 1'b0; + else + hbreak_pending <= hbreak_pending_nxt; + end + + + assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); + assign F_av_iw = i_readdata; + assign F_iw = hbreak_req ? 4040762 : + 1'b0 ? 127034 : + intr_req ? 3926074 : + F_av_iw; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_iw <= 0; + else if (F_valid) + D_iw <= F_iw; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_valid <= 0; + else + D_valid <= F_valid; + end + + + assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : + D_ctrl_implicit_dst_eretaddr ? 5'd29 : + D_ctrl_b_is_dst ? D_iw_b : + D_iw_c; + + assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; + assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; + assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_jmp_direct_target_waddr = D_iw[31 : 6]; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_valid <= 0; + else + R_valid <= D_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_wr_dst_reg <= 0; + else + R_wr_dst_reg <= D_wr_dst_reg; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_dst_regnum <= 0; + else + R_dst_regnum <= D_dst_regnum; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_logic_op <= 0; + else + R_logic_op <= D_logic_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_compare_op <= 0; + else + R_compare_op <= D_compare_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_src2_use_imm <= 0; + else + R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); + end + + + assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; + assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; +//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_a), + .rdaddress (D_iw_a), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; +`else +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; +//synthesis read_comments_as_HDL off +//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_b), + .rdaddress (D_iw_b), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; +`else +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; +//synthesis read_comments_as_HDL off + assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : + ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : + R_rf_a; + + assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : + (R_src2_use_imm)? D_iw_imm16 : + R_rf_b[15 : 0]; + + assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : + (R_ctrl_hi_imm16)? D_iw_imm16 : + (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : + R_rf_b[31 : 16]; + + assign R_src2 = {R_src2_hi, R_src2_lo}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_valid <= 0; + else + E_valid <= R_valid | E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_new_inst <= 0; + else + E_new_inst <= R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src1 <= 0; + else + E_src1 <= R_src1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src2 <= 0; + else + E_src2 <= R_src2; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_invert_arith_src_msb <= 0; + else + E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_alu_sub <= 0; + else + E_alu_sub <= D_ctrl_alu_subtract & R_valid; + end + + + assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; + assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, + E_src1[30 : 0]}; + + assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, + E_src2[30 : 0]}; + + assign E_arith_result = E_alu_sub ? + E_arith_src1 - E_arith_src2 : + E_arith_src1 + E_arith_src2; + + assign E_mem_baddr = E_arith_result[18 : 0]; + assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : + (R_logic_op == 2'b01)? (E_src1 & E_src2) : + (R_logic_op == 2'b10)? (E_src1 | E_src2) : + (E_src1 ^ E_src2); + + assign E_logic_result_is_0 = E_logic_result == 0; + assign E_eq = E_logic_result_is_0; + assign E_lt = E_arith_result[32]; + assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : + (R_compare_op == 2'b01)? ~E_lt : + (R_compare_op == 2'b10)? E_lt : + ~E_eq; + + assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; + assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; + assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; + assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : + (R_ctrl_rot_right ? E_shift_rot_result[0] : + E_shift_rot_result[31]); + + assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : + (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : + {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_result <= 0; + else + E_shift_rot_result <= E_shift_rot_result_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_cnt <= 0; + else + E_shift_rot_cnt <= E_shift_rot_cnt_nxt; + end + + + assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : + (D_iw_control_regnum == 3'd1)? W_estatus_reg : + (D_iw_control_regnum == 3'd2)? W_bstatus_reg : + (D_iw_control_regnum == 3'd3)? W_ienable_reg : + (D_iw_control_regnum == 3'd4)? W_ipending_reg : + 0; + + assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : + (R_ctrl_shift_rot)? E_shift_rot_result : + (R_ctrl_logic)? E_logic_result : + (R_ctrl_custom)? E_ci_result : + E_arith_result; + + assign R_stb_data = R_rf_b[7 : 0]; + assign R_sth_data = R_rf_b[15 : 0]; + assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : + (D_mem16)? {R_sth_data, R_sth_data} : + R_rf_b; + + assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : + 4'b1111; + + assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); + assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); + assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); + assign E_st_stall = d_write_nxt; + assign d_address = W_mem_baddr; + assign av_ld_getting_data = d_read & ~d_waitrequest; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_read <= 0; + else + d_read <= d_read_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_writedata <= 0; + else + d_writedata <= E_st_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_byteenable <= 0; + else + d_byteenable <= E_mem_byte_en; + end + + + assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); + assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); + assign av_ld_aligning_data_nxt = av_ld_aligning_data ? + ~av_ld_align_one_more_cycle : + (~D_mem32 & av_ld_getting_data); + + assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? + ~av_ld_getting_data : + (R_ctrl_ld & E_new_inst); + + assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); + assign av_ld_rshift8 = av_ld_aligning_data & + (av_ld_align_cycle < (W_mem_baddr[1 : 0])); + + assign av_ld_extend = av_ld_aligning_data; + assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : + av_ld_extend ? av_ld_byte0_data : + d_readdata[7 : 0]; + + assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[15 : 8]; + + assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[23 : 16]; + + assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[31 : 24]; + + assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); + assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, + av_ld_byte1_data, av_ld_byte0_data}; + + assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; + assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_align_cycle <= 0; + else + av_ld_align_cycle <= av_ld_align_cycle_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_waiting_for_data <= 0; + else + av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_aligning_data <= 0; + else + av_ld_aligning_data <= av_ld_aligning_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte0_data <= 0; + else + av_ld_byte0_data <= av_ld_byte0_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte1_data <= 0; + else if (av_ld_byte1_data_en) + av_ld_byte1_data <= av_ld_byte1_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte2_data <= 0; + else + av_ld_byte2_data <= av_ld_byte2_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte3_data <= 0; + else + av_ld_byte3_data <= av_ld_byte3_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_valid <= 0; + else + W_valid <= E_valid & ~E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_control_rd_data <= 0; + else + W_control_rd_data <= E_control_rd_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_cmp_result <= 0; + else + W_cmp_result <= E_cmp_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_alu_result <= 0; + else + W_alu_result <= E_alu_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_status_reg_pie <= 0; + else + W_status_reg_pie <= W_status_reg_pie_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_estatus_reg <= 0; + else + W_estatus_reg <= W_estatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_bstatus_reg <= 0; + else + W_bstatus_reg <= W_bstatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ienable_reg <= 0; + else + W_ienable_reg <= W_ienable_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ipending_reg <= 0; + else + W_ipending_reg <= W_ipending_reg_nxt; + end + + + assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : + R_ctrl_rdctl_inst ? W_control_rd_data : + W_alu_result[31 : 0]; + + assign W_wr_data = W_wr_data_non_zero; + assign W_br_taken = R_ctrl_br & W_cmp_result; + assign W_mem_baddr = W_alu_result[18 : 0]; + assign W_status_reg = W_status_reg_pie; + assign E_wrctl_status = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd0); + + assign E_wrctl_estatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd1); + + assign E_wrctl_bstatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd2); + + assign E_wrctl_ienable = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd3); + + assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : + (D_op_eret) ? W_estatus_reg : + (D_op_bret) ? W_bstatus_reg : + (E_wrctl_status) ? E_src1[0] : + W_status_reg_pie; + + assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; + assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : + (R_ctrl_exception) ? W_status_reg : + (E_wrctl_estatus) ? E_src1[0] : + W_estatus_reg; + + assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; + assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : + (E_wrctl_bstatus) ? E_src1[0] : + W_bstatus_reg; + + assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; + assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? + E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; + + assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_enabled <= 1'b1; + else if (E_valid) + hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; + end + + + nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci + ( + .D_valid (D_valid), + .E_st_data (E_st_data), + .E_valid (E_valid), + .F_pc (F_pc), + .address_nxt (jtag_debug_module_address), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .byteenable_nxt (jtag_debug_module_byteenable), + .clk (jtag_debug_module_clk), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .debugaccess_nxt (jtag_debug_module_debugaccess), + .hbreak_enabled (hbreak_enabled), + .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), + .oci_hbreak_req (oci_hbreak_req), + .oci_ienable (oci_ienable), + .oci_single_step_mode (oci_single_step_mode), + .read_nxt (jtag_debug_module_read), + .readdata (jtag_debug_module_readdata), + .reset (jtag_debug_module_reset), + .reset_n (reset_n), + .resetrequest (jtag_debug_module_resetrequest), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .waitrequest (jtag_debug_module_waitrequest), + .write_nxt (jtag_debug_module_write), + .writedata_nxt (jtag_debug_module_writedata) + ); + + //jtag_debug_module, which is an e_avalon_slave + assign jtag_debug_module_clk = clk; + assign jtag_debug_module_reset = ~reset_n; + assign D_ctrl_custom = 1'b0; + assign R_ctrl_custom_nxt = D_ctrl_custom; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom <= 0; + else if (R_en) + R_ctrl_custom <= R_ctrl_custom_nxt; + end + + + assign D_ctrl_custom_multi = 1'b0; + assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom_multi <= 0; + else if (R_en) + R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; + end + + + assign D_ctrl_jmp_indirect = D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_indirect <= 0; + else if (R_en) + R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; + end + + + assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; + assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_direct <= 0; + else if (R_en) + R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; + end + + + assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; + assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_retaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; + end + + + assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; + assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_eretaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; + end + + + assign D_ctrl_exception = D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60; + + assign R_ctrl_exception_nxt = D_ctrl_exception; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_exception <= 0; + else if (R_en) + R_ctrl_exception <= R_ctrl_exception_nxt; + end + + + assign D_ctrl_break = D_op_break|D_op_hbreak; + assign R_ctrl_break_nxt = D_ctrl_break; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_break <= 0; + else if (R_en) + R_ctrl_break <= R_ctrl_break_nxt; + end + + + assign D_ctrl_crst = D_op_crst|D_op_rsvx63; + assign R_ctrl_crst_nxt = D_ctrl_crst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_crst <= 0; + else if (R_en) + R_ctrl_crst <= R_ctrl_crst_nxt; + end + + + assign D_ctrl_uncond_cti_non_br = D_op_call| + D_op_jmpi| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_uncond_cti_non_br <= 0; + else if (R_en) + R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; + end + + + assign D_ctrl_retaddr = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak; + + assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_retaddr <= 0; + else if (R_en) + R_ctrl_retaddr <= R_ctrl_retaddr_nxt; + end + + + assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; + assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_logical <= 0; + else if (R_en) + R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; + end + + + assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; + assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_right_arith <= 0; + else if (R_en) + R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; + end + + + assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; + assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rot_right <= 0; + else if (R_en) + R_ctrl_rot_right <= R_ctrl_rot_right_nxt; + end + + + assign D_ctrl_shift_rot_right = D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot_right <= 0; + else if (R_en) + R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; + end + + + assign D_ctrl_shift_rot = D_op_slli| + D_op_rsvx50| + D_op_sll| + D_op_rsvx51| + D_op_roli| + D_op_rsvx34| + D_op_rol| + D_op_rsvx35| + D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot <= 0; + else if (R_en) + R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; + end + + + assign D_ctrl_logic = D_op_and| + D_op_or| + D_op_xor| + D_op_nor| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori; + + assign R_ctrl_logic_nxt = D_ctrl_logic; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_logic <= 0; + else if (R_en) + R_ctrl_logic <= R_ctrl_logic_nxt; + end + + + assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; + assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_hi_imm16 <= 0; + else if (R_en) + R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; + end + + + assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| + D_op_cmpltui| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_unsigned_lo_imm16 <= 0; + else if (R_en) + R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; + end + + + assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; + assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_uncond <= 0; + else if (R_en) + R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; + end + + + assign D_ctrl_br = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62; + + assign R_ctrl_br_nxt = D_ctrl_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br <= 0; + else if (R_en) + R_ctrl_br <= R_ctrl_br_nxt; + end + + + assign D_ctrl_alu_subtract = D_op_sub| + D_op_rsvx25| + D_op_cmplti| + D_op_cmpltui| + D_op_cmplt| + D_op_cmpltu| + D_op_blt| + D_op_bltu| + D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpge| + D_op_cmpgeu| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42; + + assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_subtract <= 0; + else if (R_en) + R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; + end + + + assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; + assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_signed_comparison <= 0; + else if (R_en) + R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; + end + + + assign D_ctrl_br_cmp = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_rsvx00| + D_op_cmpge| + D_op_cmplt| + D_op_cmpne| + D_op_cmpgeu| + D_op_cmpltu| + D_op_cmpeq| + D_op_rsvx56; + + assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_cmp <= 0; + else if (R_en) + R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; + end + + + assign D_ctrl_ld_signed = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63; + + assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_signed <= 0; + else if (R_en) + R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; + end + + + assign D_ctrl_ld = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio; + + assign R_ctrl_ld_nxt = D_ctrl_ld; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld <= 0; + else if (R_en) + R_ctrl_ld <= R_ctrl_ld_nxt; + end + + + assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; + assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_non_io <= 0; + else if (R_en) + R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; + end + + + assign D_ctrl_st = D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61; + + assign R_ctrl_st_nxt = D_ctrl_st; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_st <= 0; + else if (R_en) + R_ctrl_st <= R_ctrl_st_nxt; + end + + + assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; + assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_io <= 0; + else if (R_en) + R_ctrl_ld_io <= R_ctrl_ld_io_nxt; + end + + + assign D_ctrl_b_is_dst = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda; + + assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_b_is_dst <= 0; + else if (R_en) + R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; + end + + + assign D_ctrl_ignore_dst = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57; + + assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ignore_dst <= 0; + else if (R_en) + R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; + end + + + assign D_ctrl_src2_choose_imm = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_src2_choose_imm <= 0; + else if (R_en) + R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; + end + + + assign D_ctrl_wrctl_inst = D_op_wrctl; + assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_wrctl_inst <= 0; + else if (R_en) + R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; + end + + + assign D_ctrl_rdctl_inst = D_op_rdctl; + assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rdctl_inst <= 0; + else if (R_en) + R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; + end + + + assign D_ctrl_force_src2_zero = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_jmpi; + + assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_force_src2_zero <= 0; + else if (R_en) + R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; + end + + + assign D_ctrl_alu_force_xor = D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpeqi| + D_op_cmpge| + D_op_cmpgeu| + D_op_cmpeq| + D_op_cmpnei| + D_op_cmpne| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42| + D_op_beq| + D_op_rsv34| + D_op_bne| + D_op_rsv62| + D_op_br| + D_op_rsv02; + + assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_force_xor <= 0; + else if (R_en) + R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; + end + + + //data_master, which is an e_avalon_master + //instruction_master, which is an e_avalon_master + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign F_inst = (F_op_call)? 56'h20202063616c6c : + (F_op_jmpi)? 56'h2020206a6d7069 : + (F_op_ldbu)? 56'h2020206c646275 : + (F_op_addi)? 56'h20202061646469 : + (F_op_stb)? 56'h20202020737462 : + (F_op_br)? 56'h20202020206272 : + (F_op_ldb)? 56'h202020206c6462 : + (F_op_cmpgei)? 56'h20636d70676569 : + (F_op_ldhu)? 56'h2020206c646875 : + (F_op_andi)? 56'h202020616e6469 : + (F_op_sth)? 56'h20202020737468 : + (F_op_bge)? 56'h20202020626765 : + (F_op_ldh)? 56'h202020206c6468 : + (F_op_cmplti)? 56'h20636d706c7469 : + (F_op_initda)? 56'h20696e69746461 : + (F_op_ori)? 56'h202020206f7269 : + (F_op_stw)? 56'h20202020737477 : + (F_op_blt)? 56'h20202020626c74 : + (F_op_ldw)? 56'h202020206c6477 : + (F_op_cmpnei)? 56'h20636d706e6569 : + (F_op_flushda)? 56'h666c7573686461 : + (F_op_xori)? 56'h202020786f7269 : + (F_op_bne)? 56'h20202020626e65 : + (F_op_cmpeqi)? 56'h20636d70657169 : + (F_op_ldbuio)? 56'h206c646275696f : + (F_op_muli)? 56'h2020206d756c69 : + (F_op_stbio)? 56'h2020737462696f : + (F_op_beq)? 56'h20202020626571 : + (F_op_ldbio)? 56'h20206c6462696f : + (F_op_cmpgeui)? 56'h636d7067657569 : + (F_op_ldhuio)? 56'h206c646875696f : + (F_op_andhi)? 56'h2020616e646869 : + (F_op_sthio)? 56'h2020737468696f : + (F_op_bgeu)? 56'h20202062676575 : + (F_op_ldhio)? 56'h20206c6468696f : + (F_op_cmpltui)? 56'h636d706c747569 : + (F_op_initd)? 56'h2020696e697464 : + (F_op_orhi)? 56'h2020206f726869 : + (F_op_stwio)? 56'h2020737477696f : + (F_op_bltu)? 56'h202020626c7475 : + (F_op_ldwio)? 56'h20206c6477696f : + (F_op_flushd)? 56'h20666c75736864 : + (F_op_xorhi)? 56'h2020786f726869 : + (F_op_eret)? 56'h20202065726574 : + (F_op_roli)? 56'h202020726f6c69 : + (F_op_rol)? 56'h20202020726f6c : + (F_op_flushp)? 56'h20666c75736870 : + (F_op_ret)? 56'h20202020726574 : + (F_op_nor)? 56'h202020206e6f72 : + (F_op_mulxuu)? 56'h206d756c787575 : + (F_op_cmpge)? 56'h2020636d706765 : + (F_op_bret)? 56'h20202062726574 : + (F_op_ror)? 56'h20202020726f72 : + (F_op_flushi)? 56'h20666c75736869 : + (F_op_jmp)? 56'h202020206a6d70 : + (F_op_and)? 56'h20202020616e64 : + (F_op_cmplt)? 56'h2020636d706c74 : + (F_op_slli)? 56'h202020736c6c69 : + (F_op_sll)? 56'h20202020736c6c : + (F_op_or)? 56'h20202020206f72 : + (F_op_mulxsu)? 56'h206d756c787375 : + (F_op_cmpne)? 56'h2020636d706e65 : + (F_op_srli)? 56'h20202073726c69 : + (F_op_srl)? 56'h2020202073726c : + (F_op_nextpc)? 56'h206e6578747063 : + (F_op_callr)? 56'h202063616c6c72 : + (F_op_xor)? 56'h20202020786f72 : + (F_op_mulxss)? 56'h206d756c787373 : + (F_op_cmpeq)? 56'h2020636d706571 : + (F_op_divu)? 56'h20202064697675 : + (F_op_div)? 56'h20202020646976 : + (F_op_rdctl)? 56'h2020726463746c : + (F_op_mul)? 56'h202020206d756c : + (F_op_cmpgeu)? 56'h20636d70676575 : + (F_op_initi)? 56'h2020696e697469 : + (F_op_trap)? 56'h20202074726170 : + (F_op_wrctl)? 56'h2020777263746c : + (F_op_cmpltu)? 56'h20636d706c7475 : + (F_op_add)? 56'h20202020616464 : + (F_op_break)? 56'h2020627265616b : + (F_op_hbreak)? 56'h2068627265616b : + (F_op_sync)? 56'h20202073796e63 : + (F_op_sub)? 56'h20202020737562 : + (F_op_srai)? 56'h20202073726169 : + (F_op_sra)? 56'h20202020737261 : + (F_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign D_inst = (D_op_call)? 56'h20202063616c6c : + (D_op_jmpi)? 56'h2020206a6d7069 : + (D_op_ldbu)? 56'h2020206c646275 : + (D_op_addi)? 56'h20202061646469 : + (D_op_stb)? 56'h20202020737462 : + (D_op_br)? 56'h20202020206272 : + (D_op_ldb)? 56'h202020206c6462 : + (D_op_cmpgei)? 56'h20636d70676569 : + (D_op_ldhu)? 56'h2020206c646875 : + (D_op_andi)? 56'h202020616e6469 : + (D_op_sth)? 56'h20202020737468 : + (D_op_bge)? 56'h20202020626765 : + (D_op_ldh)? 56'h202020206c6468 : + (D_op_cmplti)? 56'h20636d706c7469 : + (D_op_initda)? 56'h20696e69746461 : + (D_op_ori)? 56'h202020206f7269 : + (D_op_stw)? 56'h20202020737477 : + (D_op_blt)? 56'h20202020626c74 : + (D_op_ldw)? 56'h202020206c6477 : + (D_op_cmpnei)? 56'h20636d706e6569 : + (D_op_flushda)? 56'h666c7573686461 : + (D_op_xori)? 56'h202020786f7269 : + (D_op_bne)? 56'h20202020626e65 : + (D_op_cmpeqi)? 56'h20636d70657169 : + (D_op_ldbuio)? 56'h206c646275696f : + (D_op_muli)? 56'h2020206d756c69 : + (D_op_stbio)? 56'h2020737462696f : + (D_op_beq)? 56'h20202020626571 : + (D_op_ldbio)? 56'h20206c6462696f : + (D_op_cmpgeui)? 56'h636d7067657569 : + (D_op_ldhuio)? 56'h206c646875696f : + (D_op_andhi)? 56'h2020616e646869 : + (D_op_sthio)? 56'h2020737468696f : + (D_op_bgeu)? 56'h20202062676575 : + (D_op_ldhio)? 56'h20206c6468696f : + (D_op_cmpltui)? 56'h636d706c747569 : + (D_op_initd)? 56'h2020696e697464 : + (D_op_orhi)? 56'h2020206f726869 : + (D_op_stwio)? 56'h2020737477696f : + (D_op_bltu)? 56'h202020626c7475 : + (D_op_ldwio)? 56'h20206c6477696f : + (D_op_flushd)? 56'h20666c75736864 : + (D_op_xorhi)? 56'h2020786f726869 : + (D_op_eret)? 56'h20202065726574 : + (D_op_roli)? 56'h202020726f6c69 : + (D_op_rol)? 56'h20202020726f6c : + (D_op_flushp)? 56'h20666c75736870 : + (D_op_ret)? 56'h20202020726574 : + (D_op_nor)? 56'h202020206e6f72 : + (D_op_mulxuu)? 56'h206d756c787575 : + (D_op_cmpge)? 56'h2020636d706765 : + (D_op_bret)? 56'h20202062726574 : + (D_op_ror)? 56'h20202020726f72 : + (D_op_flushi)? 56'h20666c75736869 : + (D_op_jmp)? 56'h202020206a6d70 : + (D_op_and)? 56'h20202020616e64 : + (D_op_cmplt)? 56'h2020636d706c74 : + (D_op_slli)? 56'h202020736c6c69 : + (D_op_sll)? 56'h20202020736c6c : + (D_op_or)? 56'h20202020206f72 : + (D_op_mulxsu)? 56'h206d756c787375 : + (D_op_cmpne)? 56'h2020636d706e65 : + (D_op_srli)? 56'h20202073726c69 : + (D_op_srl)? 56'h2020202073726c : + (D_op_nextpc)? 56'h206e6578747063 : + (D_op_callr)? 56'h202063616c6c72 : + (D_op_xor)? 56'h20202020786f72 : + (D_op_mulxss)? 56'h206d756c787373 : + (D_op_cmpeq)? 56'h2020636d706571 : + (D_op_divu)? 56'h20202064697675 : + (D_op_div)? 56'h20202020646976 : + (D_op_rdctl)? 56'h2020726463746c : + (D_op_mul)? 56'h202020206d756c : + (D_op_cmpgeu)? 56'h20636d70676575 : + (D_op_initi)? 56'h2020696e697469 : + (D_op_trap)? 56'h20202074726170 : + (D_op_wrctl)? 56'h2020777263746c : + (D_op_cmpltu)? 56'h20636d706c7475 : + (D_op_add)? 56'h20202020616464 : + (D_op_break)? 56'h2020627265616b : + (D_op_hbreak)? 56'h2068627265616b : + (D_op_sync)? 56'h20202073796e63 : + (D_op_sub)? 56'h20202020737562 : + (D_op_srai)? 56'h20202073726169 : + (D_op_sra)? 56'h20202020737261 : + (D_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; + assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; + assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; + assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; + assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v index 7eead98..7daaec7 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v @@ -1,181 +1,181 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_sysclk ( - // inputs: - clk, - ir_in, - sr, - vs_udr, - vs_uir, - - // outputs: - jdo, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input clk; - input [ 1: 0] ir_in; - input [ 37: 0] sr; - input vs_udr; - input vs_uir; - - reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - wire sync_udr; - wire sync_uir; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire unxunused_resetxx3; - wire unxunused_resetxx4; - reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - assign unxunused_resetxx3 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer3 - ( - .clk (clk), - .din (vs_udr), - .dout (sync_udr), - .reset_n (unxunused_resetxx3) - ); - - defparam the_altera_std_synchronizer3.depth = 2; - - assign unxunused_resetxx4 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer4 - ( - .clk (clk), - .din (vs_uir), - .dout (sync_uir), - .reset_n (unxunused_resetxx4) - ); - - defparam the_altera_std_synchronizer4.depth = 2; - - always @(posedge clk) - begin - sync2_udr <= sync_udr; - update_jdo_strobe <= sync_udr & ~sync2_udr; - enable_action_strobe <= update_jdo_strobe; - sync2_uir <= sync_uir; - jxuir <= sync_uir & ~sync2_uir; - end - - - assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && jdo[34]; - - assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && ~jdo[34]; - - assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && - jdo[35]; - - assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - jdo[36]; - - assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - ~jdo[36]; - - assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && - jdo[37]; - - assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - jdo[37]; - - assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - ~jdo[37]; - - assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - jdo[37]; - - assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - ~jdo[37]; - - assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - jdo[37]; - - assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - ~jdo[37]; - - assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && - jdo[15]; - - always @(posedge clk) - begin - if (jxuir) - ir <= ir_in; - if (update_jdo_strobe) - jdo <= sr; - end - - - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_sysclk ( + // inputs: + clk, + ir_in, + sr, + vs_udr, + vs_uir, + + // outputs: + jdo, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input clk; + input [ 1: 0] ir_in; + input [ 37: 0] sr; + input vs_udr; + input vs_uir; + + reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + wire sync_udr; + wire sync_uir; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire unxunused_resetxx3; + wire unxunused_resetxx4; + reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + assign unxunused_resetxx3 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer3 + ( + .clk (clk), + .din (vs_udr), + .dout (sync_udr), + .reset_n (unxunused_resetxx3) + ); + + defparam the_altera_std_synchronizer3.depth = 2; + + assign unxunused_resetxx4 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer4 + ( + .clk (clk), + .din (vs_uir), + .dout (sync_uir), + .reset_n (unxunused_resetxx4) + ); + + defparam the_altera_std_synchronizer4.depth = 2; + + always @(posedge clk) + begin + sync2_udr <= sync_udr; + update_jdo_strobe <= sync_udr & ~sync2_udr; + enable_action_strobe <= update_jdo_strobe; + sync2_uir <= sync_uir; + jxuir <= sync_uir & ~sync2_uir; + end + + + assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && jdo[34]; + + assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && ~jdo[34]; + + assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && + jdo[35]; + + assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + jdo[36]; + + assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + ~jdo[36]; + + assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && + jdo[37]; + + assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + jdo[37]; + + assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + ~jdo[37]; + + assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + jdo[37]; + + assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + ~jdo[37]; + + assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + jdo[37]; + + assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + ~jdo[37]; + + assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && + jdo[15]; + + always @(posedge clk) + begin + if (jxuir) + ir <= ir_in; + if (update_jdo_strobe) + jdo <= sr; + end + + + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v index 09289db..8e3a593 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v @@ -1,239 +1,239 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_tck ( - // inputs: - MonDReg, - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - ir_in, - jtag_state_rti, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tck, - tdi, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - vs_cdr, - vs_sdr, - vs_uir, - - // outputs: - ir_out, - jrst_n, - sr, - st_ready_test_idle, - tdo - ) -; - - output [ 1: 0] ir_out; - output jrst_n; - output [ 37: 0] sr; - output st_ready_test_idle; - output tdo; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input [ 1: 0] ir_in; - input jtag_state_rti; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tck; - input tdi; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - input vs_cdr; - input vs_sdr; - input vs_uir; - - reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire debugack_sync; - reg [ 1: 0] ir_out; - wire jrst_n; - wire monitor_ready_sync; - reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire st_ready_test_idle; - wire tdo; - wire unxcomplemented_resetxx1; - wire unxcomplemented_resetxx2; - always @(posedge tck) - begin - if (vs_cdr) - case (ir_in) - - 2'b00: begin - sr[35] <= debugack_sync; - sr[34] <= monitor_error; - sr[33] <= resetlatch; - sr[32 : 1] <= MonDReg; - sr[0] <= monitor_ready_sync; - end // 2'b00 - - 2'b01: begin - sr[35 : 0] <= tracemem_trcdata; - sr[37] <= tracemem_tw; - sr[36] <= tracemem_on; - end // 2'b01 - - 2'b10: begin - sr[37] <= trigger_state_1; - sr[36] <= dbrk_hit3_latch; - sr[35] <= dbrk_hit2_latch; - sr[34] <= dbrk_hit1_latch; - sr[33] <= dbrk_hit0_latch; - sr[32 : 1] <= break_readreg; - sr[0] <= trigbrktype; - end // 2'b10 - - 2'b11: begin - sr[15 : 12] <= 1'b0; - sr[11 : 2] <= trc_im_addr; - sr[1] <= trc_wrap; - sr[0] <= trc_on; - end // 2'b11 - - endcase // ir_in - if (vs_sdr) - case (DRsize) - - 3'b000: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // 3'b000 - - 3'b001: begin - sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; - end // 3'b001 - - 3'b010: begin - sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; - end // 3'b010 - - 3'b011: begin - sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; - end // 3'b011 - - 3'b100: begin - sr <= {tdi, sr[37], tdi, sr[35 : 1]}; - end // 3'b100 - - 3'b101: begin - sr <= {tdi, sr[37 : 1]}; - end // 3'b101 - - default: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // default - - endcase // DRsize - if (vs_uir) - case (ir_in) - - 2'b00: begin - DRsize <= 3'b100; - end // 2'b00 - - 2'b01: begin - DRsize <= 3'b101; - end // 2'b01 - - 2'b10: begin - DRsize <= 3'b101; - end // 2'b10 - - 2'b11: begin - DRsize <= 3'b010; - end // 2'b11 - - endcase // ir_in - end - - - assign tdo = sr[0]; - assign st_ready_test_idle = jtag_state_rti; - assign unxcomplemented_resetxx1 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer1 - ( - .clk (tck), - .din (debugack), - .dout (debugack_sync), - .reset_n (unxcomplemented_resetxx1) - ); - - defparam the_altera_std_synchronizer1.depth = 2; - - assign unxcomplemented_resetxx2 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer2 - ( - .clk (tck), - .din (monitor_ready), - .dout (monitor_ready_sync), - .reset_n (unxcomplemented_resetxx2) - ); - - defparam the_altera_std_synchronizer2.depth = 2; - - always @(posedge tck or negedge jrst_n) - begin - if (jrst_n == 0) - ir_out <= 2'b0; - else - ir_out <= {debugack_sync, monitor_ready_sync}; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign jrst_n = reset_n; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// assign jrst_n = 1; -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_tck ( + // inputs: + MonDReg, + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + ir_in, + jtag_state_rti, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tck, + tdi, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + vs_cdr, + vs_sdr, + vs_uir, + + // outputs: + ir_out, + jrst_n, + sr, + st_ready_test_idle, + tdo + ) +; + + output [ 1: 0] ir_out; + output jrst_n; + output [ 37: 0] sr; + output st_ready_test_idle; + output tdo; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input [ 1: 0] ir_in; + input jtag_state_rti; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tck; + input tdi; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + input vs_cdr; + input vs_sdr; + input vs_uir; + + reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire debugack_sync; + reg [ 1: 0] ir_out; + wire jrst_n; + wire monitor_ready_sync; + reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire st_ready_test_idle; + wire tdo; + wire unxcomplemented_resetxx1; + wire unxcomplemented_resetxx2; + always @(posedge tck) + begin + if (vs_cdr) + case (ir_in) + + 2'b00: begin + sr[35] <= debugack_sync; + sr[34] <= monitor_error; + sr[33] <= resetlatch; + sr[32 : 1] <= MonDReg; + sr[0] <= monitor_ready_sync; + end // 2'b00 + + 2'b01: begin + sr[35 : 0] <= tracemem_trcdata; + sr[37] <= tracemem_tw; + sr[36] <= tracemem_on; + end // 2'b01 + + 2'b10: begin + sr[37] <= trigger_state_1; + sr[36] <= dbrk_hit3_latch; + sr[35] <= dbrk_hit2_latch; + sr[34] <= dbrk_hit1_latch; + sr[33] <= dbrk_hit0_latch; + sr[32 : 1] <= break_readreg; + sr[0] <= trigbrktype; + end // 2'b10 + + 2'b11: begin + sr[15 : 12] <= 1'b0; + sr[11 : 2] <= trc_im_addr; + sr[1] <= trc_wrap; + sr[0] <= trc_on; + end // 2'b11 + + endcase // ir_in + if (vs_sdr) + case (DRsize) + + 3'b000: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // 3'b000 + + 3'b001: begin + sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; + end // 3'b001 + + 3'b010: begin + sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; + end // 3'b010 + + 3'b011: begin + sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; + end // 3'b011 + + 3'b100: begin + sr <= {tdi, sr[37], tdi, sr[35 : 1]}; + end // 3'b100 + + 3'b101: begin + sr <= {tdi, sr[37 : 1]}; + end // 3'b101 + + default: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // default + + endcase // DRsize + if (vs_uir) + case (ir_in) + + 2'b00: begin + DRsize <= 3'b100; + end // 2'b00 + + 2'b01: begin + DRsize <= 3'b101; + end // 2'b01 + + 2'b10: begin + DRsize <= 3'b101; + end // 2'b10 + + 2'b11: begin + DRsize <= 3'b010; + end // 2'b11 + + endcase // ir_in + end + + + assign tdo = sr[0]; + assign st_ready_test_idle = jtag_state_rti; + assign unxcomplemented_resetxx1 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer1 + ( + .clk (tck), + .din (debugack), + .dout (debugack_sync), + .reset_n (unxcomplemented_resetxx1) + ); + + defparam the_altera_std_synchronizer1.depth = 2; + + assign unxcomplemented_resetxx2 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer2 + ( + .clk (tck), + .din (monitor_ready), + .dout (monitor_ready_sync), + .reset_n (unxcomplemented_resetxx2) + ); + + defparam the_altera_std_synchronizer2.depth = 2; + + always @(posedge tck or negedge jrst_n) + begin + if (jrst_n == 0) + ir_out <= 2'b0; + else + ir_out <= {debugack_sync, monitor_ready_sync}; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign jrst_n = reset_n; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// assign jrst_n = 1; +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v index 6a57330..1fd5cb7 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v @@ -1,233 +1,233 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_wrapper ( - // inputs: - MonDReg, - break_readreg, - clk, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - - // outputs: - jdo, - jrst_n, - st_ready_test_idle, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output jrst_n; - output st_ready_test_idle; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input clk; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - - wire [ 37: 0] jdo; - wire jrst_n; - wire [ 37: 0] sr; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire vji_cdr; - wire [ 1: 0] vji_ir_in; - wire [ 1: 0] vji_ir_out; - wire vji_rti; - wire vji_sdr; - wire vji_tck; - wire vji_tdi; - wire vji_tdo; - wire vji_udr; - wire vji_uir; - //Change the sld_virtual_jtag_basic's defparams to - //switch between a regular Nios II or an internally embedded Nios II. - //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. - //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. - nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .ir_in (vji_ir_in), - .ir_out (vji_ir_out), - .jrst_n (jrst_n), - .jtag_state_rti (vji_rti), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .sr (sr), - .st_ready_test_idle (st_ready_test_idle), - .tck (vji_tck), - .tdi (vji_tdi), - .tdo (vji_tdo), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1), - .vs_cdr (vji_cdr), - .vs_sdr (vji_sdr), - .vs_uir (vji_uir) - ); - - nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk - ( - .clk (clk), - .ir_in (vji_ir_in), - .jdo (jdo), - .sr (sr), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .vs_udr (vji_udr), - .vs_uir (vji_uir) - ); - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign vji_tck = 1'b0; - assign vji_tdi = 1'b0; - assign vji_sdr = 1'b0; - assign vji_cdr = 1'b0; - assign vji_rti = 1'b0; - assign vji_uir = 1'b0; - assign vji_udr = 1'b0; - assign vji_ir_in = 2'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy -// ( -// .ir_in (vji_ir_in), -// .ir_out (vji_ir_out), -// .jtag_state_rti (vji_rti), -// .tck (vji_tck), -// .tdi (vji_tdi), -// .tdo (vji_tdo), -// .virtual_state_cdr (vji_cdr), -// .virtual_state_sdr (vji_sdr), -// .virtual_state_udr (vji_udr), -// .virtual_state_uir (vji_uir) -// ); -// -// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; -// -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_wrapper ( + // inputs: + MonDReg, + break_readreg, + clk, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + + // outputs: + jdo, + jrst_n, + st_ready_test_idle, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output jrst_n; + output st_ready_test_idle; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input clk; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + + wire [ 37: 0] jdo; + wire jrst_n; + wire [ 37: 0] sr; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire vji_cdr; + wire [ 1: 0] vji_ir_in; + wire [ 1: 0] vji_ir_out; + wire vji_rti; + wire vji_sdr; + wire vji_tck; + wire vji_tdi; + wire vji_tdo; + wire vji_udr; + wire vji_uir; + //Change the sld_virtual_jtag_basic's defparams to + //switch between a regular Nios II or an internally embedded Nios II. + //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. + //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. + nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .ir_in (vji_ir_in), + .ir_out (vji_ir_out), + .jrst_n (jrst_n), + .jtag_state_rti (vji_rti), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .sr (sr), + .st_ready_test_idle (st_ready_test_idle), + .tck (vji_tck), + .tdi (vji_tdi), + .tdo (vji_tdo), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1), + .vs_cdr (vji_cdr), + .vs_sdr (vji_sdr), + .vs_uir (vji_uir) + ); + + nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk + ( + .clk (clk), + .ir_in (vji_ir_in), + .jdo (jdo), + .sr (sr), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .vs_udr (vji_udr), + .vs_uir (vji_uir) + ); + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign vji_tck = 1'b0; + assign vji_tdi = 1'b0; + assign vji_sdr = 1'b0; + assign vji_cdr = 1'b0; + assign vji_rti = 1'b0; + assign vji_uir = 1'b0; + assign vji_udr = 1'b0; + assign vji_ir_in = 2'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy +// ( +// .ir_in (vji_ir_in), +// .ir_out (vji_ir_out), +// .jtag_state_rti (vji_rti), +// .tck (vji_tck), +// .tdi (vji_tdi), +// .tdo (vji_tdo), +// .virtual_state_cdr (vji_cdr), +// .virtual_state_sdr (vji_sdr), +// .virtual_state_udr (vji_udr), +// .virtual_state_uir (vji_uir) +// ); +// +// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v index cf59495..0046686 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v @@ -1,37 +1,37 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_oci_test_bench ( - // inputs: - dct_buffer, - dct_count, - test_ending, - test_has_ended - ) -; - - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input test_ending; - input test_has_ended; - - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_oci_test_bench ( + // inputs: + dct_buffer, + dct_count, + test_ending, + test_has_ended + ) +; + + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input test_ending; + input test_has_ended; + + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif index aee33b3..44481aa 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_ociram_default_contents.mif @@ -1,267 +1,267 @@ --- Contents are randomly generated during RTL generation. -WIDTH=32; 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-7a : 74ede6d2; -7b : 080eafa5; -7c : f21052d8; -7d : cc0819fb; -7e : 8993e5b6; -7f : e20f2df6; -80 : 0f267a65; -81 : 7a8e8407; -82 : e7be656d; -83 : 01ba4ca3; -84 : 7f998e44; -85 : 29d83420; -86 : 149f9a73; -87 : 643ae51e; -88 : 125714d3; -89 : 6e49dc21; -8a : 0b227946; -8b : 360a837d; -8c : b2187074; -8d : 17b0bdbd; -8e : 938fc73d; -8f : e73f501e; -90 : 70b5b87e; -91 : 2a2aed8a; -92 : f96cc881; -93 : 021b49e1; -94 : 8691600d; -95 : b45e1d12; -96 : 64d9644e; -97 : 486cbaf9; -98 : 386acf20; -99 : 0d1384d4; -9a : 62455f77; -9b : 866fde20; -9c : 006fecec; -9d : 94e84514; -9e : 7babc333; -9f : afaa8445; -a0 : b1175e3a; -a1 : e08de629; -a2 : 7f12a52d; -a3 : 0e322909; -a4 : 18784dc6; -a5 : b23bcc20; -a6 : 266c9e34; -a7 : c857eaf3; -a8 : 2ae3b164; -a9 : 038acf2a; -aa : c1abc60d; -ab : 8af787bd; -ac : 043723a9; -ad : c37c952d; -ae : 693a361f; -af : da4b8e99; -b0 : fb8fdb10; -b1 : 4d6365f2; -b2 : 712358e9; -b3 : 85dae0fa; -b4 : 7e82a418; -b5 : d3493768; -b6 : 739c65ec; -b7 : 73b66b19; -b8 : 22142816; -b9 : ff498322; -ba : 3266495e; -bb : e26e8214; -bc : c8c47131; -bd : 660793d8; -be : 689f8d69; -bf : faae340b; -c0 : 37518ba7; -c1 : f2865fe5; -c2 : 1bb44f3d; -c3 : 3bce44c5; -c4 : aff2d188; -c5 : 985442da; -c6 : 85bb58bd; -c7 : 0c53135d; -c8 : 495f80bc; -c9 : 853c95dc; -ca : dde937f1; -cb : 418f9452; -cc : 7669641c; -cd : 0e752434; -ce : b0fe17a7; -cf : d1be9b88; -d0 : cfbfeb76; -d1 : 80b48a11; -d2 : 9327c69e; -d3 : beca5a88; -d4 : e71d428f; -d5 : b318d275; -d6 : 56fea35e; -d7 : 140cd6bd; -d8 : b8c937ce; -d9 : 540eea36; -da : ee58fc7f; -db : 5615c389; -dc : 46692ad0; -dd : 5c713e51; -de : 6ba95f60; -df : 0e166732; -e0 : ac0e49f5; -e1 : c9a5ea76; -e2 : 05b04d86; -e3 : b29ac712; -e4 : 4e344493; -e5 : d45ede48; -e6 : 3da7e426; -e7 : 4d6a8937; -e8 : 99b59bd4; -e9 : 1f8a5751; -ea : 8b07e64e; -eb : b4dcd496; -ec : 42f84fe6; -ed : f1d5952f; -ee : a2e5a42d; -ef : 15b1af16; -f0 : 168012bc; -f1 : 2e276612; -f2 : 89913eaa; -f3 : c607a1a2; -f4 : fd8b544d; -f5 : aec31a53; -f6 : 25f958ad; -f7 : 365903ec; -f8 : 14761865; -f9 : 568cc23b; -fa : b0386305; -fb : fb9ebd8a; -fc : a25911d4; -fd : 806e3fbb; -fe : 9df35264; -ff : d62b3814; - -END; +-- Contents are randomly generated during RTL generation. +WIDTH=32; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : 88997af9; +01 : abaae595; +02 : 32fd14d1; +03 : b66193c4; +04 : c6a6aa09; +05 : 0b43de5b; +06 : d1d93028; +07 : bcd08e2a; +08 : 1c8bae85; +09 : b11dad63; +0a : 864ddf62; +0b : 68301486; +0c : 51a3d8d0; +0d : 7af7d39e; +0e : 4761b503; +0f : 2a976e14; +10 : 98141041; +11 : 4c1f6471; +12 : 41dc0a35; +13 : 7d484ae3; +14 : 2a1329f3; +15 : 44ecf499; +16 : dccdd125; +17 : 240142e9; +18 : 3b7e4b05; +19 : bb92e762; +1a : 4594a3c5; +1b : ea0d940f; +1c : 66525d7c; +1d : 0f552242; +1e : 452bd52d; +1f : d1f4ed11; +20 : 5d590422; +21 : c8016b5f; +22 : 9ab94f07; +23 : 16bac9b4; +24 : fe569ae3; +25 : c6e1e6e7; +26 : 2ff19932; +27 : feb058ad; +28 : 1dcce651; +29 : e18b9bfb; +2a : e2f4fc64; +2b : 05d34847; +2c : 077a8143; +2d : 2ce4207f; +2e : 3f3e5113; +2f : c24d2803; +30 : e289b503; +31 : d16bcd4e; +32 : 57a841cf; +33 : 1194f754; +34 : 5c925a31; +35 : 40fd6946; +36 : e397e5d7; +37 : eada7553; +38 : eba8ec01; +39 : f5b39d0b; +3a : 88af39a3; +3b : 5b7f243e; +3c : 4f2bb4ba; +3d : 9451a234; +3e : 10fd984d; +3f : ad4ef4f7; +40 : 7fe97f8b; +41 : 08ea614d; +42 : 9f2c5cf4; +43 : 3f90b7a2; +44 : 8c2bc774; +45 : 45dd63a5; +46 : 3204329c; +47 : 9909be0d; +48 : be65c97b; +49 : 78f3d4a4; +4a : 3ee8b71c; +4b : 9e9a0de4; +4c : 56db426b; +4d : e6869d81; +4e : 20ab0652; +4f : 05d247ed; +50 : 1edccf12; +51 : 1e483b5a; +52 : 8e48ef1e; +53 : f19aefbf; +54 : 98335d23; +55 : 954ac923; +56 : 4679ced6; +57 : ae18d9b8; +58 : be57db48; +59 : 2af933e3; +5a : 3f04e244; +5b : 5d11c958; +5c : 65bda8cb; +5d : c53fe664; +5e : 797ceac8; +5f : aaa406e5; +60 : f785e24e; +61 : 95510077; +62 : 5b6f55a3; +63 : 2a3c749a; +64 : a92e6ae6; +65 : b2117fb0; +66 : 262a254e; +67 : b8c4da74; +68 : f69070ee; +69 : 9e7f80b8; +6a : 834528b4; +6b : 4aaf6d98; +6c : 96023372; +6d : d11663ed; +6e : 33a3c007; +6f : 0e7f06ee; +70 : 34385787; +71 : 2edfd7b0; +72 : 00d60e4b; +73 : 49535c30; +74 : e83f5c14; +75 : 5e0c4c59; +76 : 1d7b944a; +77 : 6ae69731; +78 : bf8414e4; +79 : 7451c212; +7a : 74ede6d2; +7b : 080eafa5; +7c : f21052d8; +7d : cc0819fb; +7e : 8993e5b6; +7f : e20f2df6; +80 : 0f267a65; +81 : 7a8e8407; +82 : e7be656d; +83 : 01ba4ca3; +84 : 7f998e44; +85 : 29d83420; +86 : 149f9a73; +87 : 643ae51e; +88 : 125714d3; +89 : 6e49dc21; +8a : 0b227946; +8b : 360a837d; +8c : b2187074; +8d : 17b0bdbd; +8e : 938fc73d; +8f : e73f501e; +90 : 70b5b87e; +91 : 2a2aed8a; +92 : f96cc881; +93 : 021b49e1; +94 : 8691600d; +95 : b45e1d12; +96 : 64d9644e; +97 : 486cbaf9; +98 : 386acf20; +99 : 0d1384d4; +9a : 62455f77; +9b : 866fde20; +9c : 006fecec; +9d : 94e84514; +9e : 7babc333; +9f : afaa8445; +a0 : b1175e3a; +a1 : e08de629; +a2 : 7f12a52d; +a3 : 0e322909; +a4 : 18784dc6; +a5 : b23bcc20; +a6 : 266c9e34; +a7 : c857eaf3; +a8 : 2ae3b164; +a9 : 038acf2a; +aa : c1abc60d; +ab : 8af787bd; +ac : 043723a9; +ad : c37c952d; +ae : 693a361f; +af : da4b8e99; +b0 : fb8fdb10; +b1 : 4d6365f2; +b2 : 712358e9; +b3 : 85dae0fa; +b4 : 7e82a418; +b5 : d3493768; +b6 : 739c65ec; +b7 : 73b66b19; +b8 : 22142816; +b9 : ff498322; +ba : 3266495e; +bb : e26e8214; +bc : c8c47131; +bd : 660793d8; +be : 689f8d69; +bf : faae340b; +c0 : 37518ba7; +c1 : f2865fe5; +c2 : 1bb44f3d; +c3 : 3bce44c5; +c4 : aff2d188; +c5 : 985442da; +c6 : 85bb58bd; +c7 : 0c53135d; +c8 : 495f80bc; +c9 : 853c95dc; +ca : dde937f1; +cb : 418f9452; +cc : 7669641c; +cd : 0e752434; +ce : b0fe17a7; +cf : d1be9b88; +d0 : cfbfeb76; +d1 : 80b48a11; +d2 : 9327c69e; +d3 : beca5a88; +d4 : e71d428f; +d5 : b318d275; +d6 : 56fea35e; +d7 : 140cd6bd; +d8 : b8c937ce; +d9 : 540eea36; +da : ee58fc7f; +db : 5615c389; +dc : 46692ad0; +dd : 5c713e51; +de : 6ba95f60; +df : 0e166732; +e0 : ac0e49f5; +e1 : c9a5ea76; +e2 : 05b04d86; +e3 : b29ac712; +e4 : 4e344493; +e5 : d45ede48; +e6 : 3da7e426; +e7 : 4d6a8937; +e8 : 99b59bd4; +e9 : 1f8a5751; +ea : 8b07e64e; +eb : b4dcd496; +ec : 42f84fe6; +ed : f1d5952f; +ee : a2e5a42d; +ef : 15b1af16; +f0 : 168012bc; +f1 : 2e276612; +f2 : 89913eaa; +f3 : c607a1a2; +f4 : fd8b544d; +f5 : aec31a53; +f6 : 25f958ad; +f7 : 365903ec; +f8 : 14761865; +f9 : 568cc23b; +fa : b0386305; +fb : fb9ebd8a; +fc : a25911d4; +fd : 806e3fbb; +fe : 9df35264; +ff : d62b3814; + +END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif index 644013a..7969f10 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_a.mif @@ -1,42 +1,42 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif index 644013a..7969f10 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_rf_ram_b.mif @@ -1,42 +1,42 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v b/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v index d707995..9ce093e 100644 --- a/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v +++ b/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v @@ -1,667 +1,667 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_test_bench ( - // inputs: - D_iw, - D_iw_op, - D_iw_opx, - D_valid, - E_valid, - F_pcb, - F_valid, - R_ctrl_ld, - R_ctrl_ld_non_io, - R_dst_regnum, - R_wr_dst_reg, - W_valid, - W_vinst, - W_wr_data, - av_ld_data_aligned_unfiltered, - clk, - d_address, - d_byteenable, - d_read, - d_write_nxt, - i_address, - i_read, - i_readdata, - i_waitrequest, - reset_n, - - // outputs: - av_ld_data_aligned_filtered, - d_write, - test_has_ended - ) -; - - output [ 31: 0] av_ld_data_aligned_filtered; - output d_write; - output test_has_ended; - input [ 31: 0] D_iw; - input [ 5: 0] D_iw_op; - input [ 5: 0] D_iw_opx; - input D_valid; - input E_valid; - input [ 18: 0] F_pcb; - input F_valid; - input R_ctrl_ld; - input R_ctrl_ld_non_io; - input [ 4: 0] R_dst_regnum; - input R_wr_dst_reg; - input W_valid; - input [ 55: 0] W_vinst; - input [ 31: 0] W_wr_data; - input [ 31: 0] av_ld_data_aligned_unfiltered; - input clk; - input [ 18: 0] d_address; - input [ 3: 0] d_byteenable; - input d_read; - input d_write_nxt; - input [ 18: 0] i_address; - input i_read; - input [ 31: 0] i_readdata; - input i_waitrequest; - input reset_n; - - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire av_ld_data_aligned_unfiltered_0_is_x; - wire av_ld_data_aligned_unfiltered_10_is_x; - wire av_ld_data_aligned_unfiltered_11_is_x; - wire av_ld_data_aligned_unfiltered_12_is_x; - wire av_ld_data_aligned_unfiltered_13_is_x; - wire av_ld_data_aligned_unfiltered_14_is_x; - wire av_ld_data_aligned_unfiltered_15_is_x; - wire av_ld_data_aligned_unfiltered_16_is_x; - wire av_ld_data_aligned_unfiltered_17_is_x; - wire av_ld_data_aligned_unfiltered_18_is_x; - wire av_ld_data_aligned_unfiltered_19_is_x; - wire av_ld_data_aligned_unfiltered_1_is_x; - wire av_ld_data_aligned_unfiltered_20_is_x; - wire av_ld_data_aligned_unfiltered_21_is_x; - wire av_ld_data_aligned_unfiltered_22_is_x; - wire av_ld_data_aligned_unfiltered_23_is_x; - wire av_ld_data_aligned_unfiltered_24_is_x; - wire av_ld_data_aligned_unfiltered_25_is_x; - wire av_ld_data_aligned_unfiltered_26_is_x; - wire av_ld_data_aligned_unfiltered_27_is_x; - wire av_ld_data_aligned_unfiltered_28_is_x; - wire av_ld_data_aligned_unfiltered_29_is_x; - wire av_ld_data_aligned_unfiltered_2_is_x; - wire av_ld_data_aligned_unfiltered_30_is_x; - wire av_ld_data_aligned_unfiltered_31_is_x; - wire av_ld_data_aligned_unfiltered_3_is_x; - wire av_ld_data_aligned_unfiltered_4_is_x; - wire av_ld_data_aligned_unfiltered_5_is_x; - wire av_ld_data_aligned_unfiltered_6_is_x; - wire av_ld_data_aligned_unfiltered_7_is_x; - wire av_ld_data_aligned_unfiltered_8_is_x; - wire av_ld_data_aligned_unfiltered_9_is_x; - reg d_write; - wire test_has_ended; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_write <= 0; - else - d_write <= d_write_nxt; - end - - - assign test_has_ended = 1'b0; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - //Clearing 'X' data bits - assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; - - assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; - assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; - assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; - assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; - assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; - assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; - assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; - assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; - assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; - assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; - assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; - assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; - assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; - assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; - assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; - assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; - assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; - assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; - assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; - assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; - assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; - assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; - assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; - assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; - assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; - assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; - assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; - assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; - assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; - assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; - assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; - assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; - assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; - assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; - assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; - assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; - assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; - assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; - assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; - assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; - assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; - assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; - assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; - assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; - assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; - assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; - assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; - assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; - assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; - assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; - assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; - assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; - assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; - assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; - assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; - assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; - assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; - assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; - assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; - assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; - assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; - assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; - assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; - always @(posedge clk) - begin - if (reset_n) - if (^(F_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(D_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(E_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(W_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid) - if (^(R_wr_dst_reg) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(R_dst_regnum) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_write) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write) - if (^(d_byteenable) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write | d_read) - if (^(d_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(i_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read) - if (^(i_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read & ~i_waitrequest) - if (^(i_readdata) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_ctrl_ld) - if (^(av_ld_data_aligned_unfiltered) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - end - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// -// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; -// -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_test_bench ( + // inputs: + D_iw, + D_iw_op, + D_iw_opx, + D_valid, + E_valid, + F_pcb, + F_valid, + R_ctrl_ld, + R_ctrl_ld_non_io, + R_dst_regnum, + R_wr_dst_reg, + W_valid, + W_vinst, + W_wr_data, + av_ld_data_aligned_unfiltered, + clk, + d_address, + d_byteenable, + d_read, + d_write_nxt, + i_address, + i_read, + i_readdata, + i_waitrequest, + reset_n, + + // outputs: + av_ld_data_aligned_filtered, + d_write, + test_has_ended + ) +; + + output [ 31: 0] av_ld_data_aligned_filtered; + output d_write; + output test_has_ended; + input [ 31: 0] D_iw; + input [ 5: 0] D_iw_op; + input [ 5: 0] D_iw_opx; + input D_valid; + input E_valid; + input [ 18: 0] F_pcb; + input F_valid; + input R_ctrl_ld; + input R_ctrl_ld_non_io; + input [ 4: 0] R_dst_regnum; + input R_wr_dst_reg; + input W_valid; + input [ 55: 0] W_vinst; + input [ 31: 0] W_wr_data; + input [ 31: 0] av_ld_data_aligned_unfiltered; + input clk; + input [ 18: 0] d_address; + input [ 3: 0] d_byteenable; + input d_read; + input d_write_nxt; + input [ 18: 0] i_address; + input i_read; + input [ 31: 0] i_readdata; + input i_waitrequest; + input reset_n; + + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire av_ld_data_aligned_unfiltered_0_is_x; + wire av_ld_data_aligned_unfiltered_10_is_x; + wire av_ld_data_aligned_unfiltered_11_is_x; + wire av_ld_data_aligned_unfiltered_12_is_x; + wire av_ld_data_aligned_unfiltered_13_is_x; + wire av_ld_data_aligned_unfiltered_14_is_x; + wire av_ld_data_aligned_unfiltered_15_is_x; + wire av_ld_data_aligned_unfiltered_16_is_x; + wire av_ld_data_aligned_unfiltered_17_is_x; + wire av_ld_data_aligned_unfiltered_18_is_x; + wire av_ld_data_aligned_unfiltered_19_is_x; + wire av_ld_data_aligned_unfiltered_1_is_x; + wire av_ld_data_aligned_unfiltered_20_is_x; + wire av_ld_data_aligned_unfiltered_21_is_x; + wire av_ld_data_aligned_unfiltered_22_is_x; + wire av_ld_data_aligned_unfiltered_23_is_x; + wire av_ld_data_aligned_unfiltered_24_is_x; + wire av_ld_data_aligned_unfiltered_25_is_x; + wire av_ld_data_aligned_unfiltered_26_is_x; + wire av_ld_data_aligned_unfiltered_27_is_x; + wire av_ld_data_aligned_unfiltered_28_is_x; + wire av_ld_data_aligned_unfiltered_29_is_x; + wire av_ld_data_aligned_unfiltered_2_is_x; + wire av_ld_data_aligned_unfiltered_30_is_x; + wire av_ld_data_aligned_unfiltered_31_is_x; + wire av_ld_data_aligned_unfiltered_3_is_x; + wire av_ld_data_aligned_unfiltered_4_is_x; + wire av_ld_data_aligned_unfiltered_5_is_x; + wire av_ld_data_aligned_unfiltered_6_is_x; + wire av_ld_data_aligned_unfiltered_7_is_x; + wire av_ld_data_aligned_unfiltered_8_is_x; + wire av_ld_data_aligned_unfiltered_9_is_x; + reg d_write; + wire test_has_ended; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_write <= 0; + else + d_write <= d_write_nxt; + end + + + assign test_has_ended = 1'b0; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //Clearing 'X' data bits + assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; + + assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; + assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; + assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; + assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; + assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; + assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; + assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; + assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; + assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; + assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; + assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; + assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; + assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; + assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; + assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; + assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; + assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; + assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; + assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; + assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; + assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; + assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; + assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; + assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; + assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; + assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; + assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; + assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; + assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; + assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; + assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; + assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; + assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; + assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; + assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; + assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; + assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; + assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; + assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; + assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; + assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; + assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; + assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; + assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; + assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; + assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; + assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; + assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; + assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; + assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; + assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; + assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; + assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; + assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; + assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; + assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; + assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; + assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; + assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; + assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; + assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; + assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; + assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; + always @(posedge clk) + begin + if (reset_n) + if (^(F_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(D_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(E_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(W_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid) + if (^(R_wr_dst_reg) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(R_dst_regnum) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_write) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write) + if (^(d_byteenable) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write | d_read) + if (^(d_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(i_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read) + if (^(i_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read & ~i_waitrequest) + if (^(i_readdata) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_ctrl_ld) + if (^(av_ld_data_aligned_unfiltered) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + end + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// +// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_onchip_memory.hex b/db/ip/nios_system/submodules/nios_system_onchip_memory.hex index f996dcd..e265501 100644 --- a/db/ip/nios_system/submodules/nios_system_onchip_memory.hex +++ b/db/ip/nios_system/submodules/nios_system_onchip_memory.hex @@ -1,51201 +1,51201 @@ -:0400000000000000FC -:0400010000000000FB -:0400020000000000FA -:0400030000000000F9 -:0400040000000000F8 -:0400050000000000F7 -:0400060000000000F6 -:0400070000000000F5 -:0400080000000000F4 -:0400090000000000F3 -:04000A0000000000F2 -:04000B0000000000F1 -:04000C0000000000F0 -:04000D0000000000EF -:04000E0000000000EE -:04000F0000000000ED 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+:04C7EE000000000047 +:04C7EF000000000046 +:04C7F0000000000045 +:04C7F1000000000044 +:04C7F2000000000043 +:04C7F3000000000042 +:04C7F4000000000041 +:04C7F5000000000040 +:04C7F600000000003F +:04C7F700000000003E +:04C7F800000000003D +:04C7F900000000003C +:04C7FA00000000003B +:04C7FB00000000003A +:04C7FC000000000039 +:04C7FD000000000038 +:04C7FE000000000037 +:04C7FF000000000036 +:00000001ff diff --git a/db/ip/nios_system/submodules/nios_system_onchip_memory.v b/db/ip/nios_system/submodules/nios_system_onchip_memory.v index 685f015..c12e1cd 100644 --- a/db/ip/nios_system/submodules/nios_system_onchip_memory.v +++ b/db/ip/nios_system/submodules/nios_system_onchip_memory.v @@ -1,85 +1,85 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_onchip_memory ( - // inputs: - address, - byteenable, - chipselect, - clk, - clken, - reset, - reset_req, - write, - writedata, - - // outputs: - readdata - ) -; - - parameter INIT_FILE = "nios_system_onchip_memory.hex"; - - - output [ 31: 0] readdata; - input [ 15: 0] address; - input [ 3: 0] byteenable; - input chipselect; - input clk; - input clken; - input reset; - input reset_req; - input write; - input [ 31: 0] writedata; - - wire clocken0; - wire [ 31: 0] readdata; - wire wren; - assign wren = chipselect & write; - assign clocken0 = clken & ~reset_req; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clk), - .clocken0 (clocken0), - .data_a (writedata), - .q_a (readdata), - .wren_a (wren) - ); - - defparam the_altsyncram.byte_size = 8, - the_altsyncram.init_file = INIT_FILE, - the_altsyncram.lpm_type = "altsyncram", - the_altsyncram.maximum_depth = 51200, - the_altsyncram.numwords_a = 51200, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 16; - - //s1, which is an e_avalon_slave - //s2, which is an e_avalon_slave - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_onchip_memory ( + // inputs: + address, + byteenable, + chipselect, + clk, + clken, + reset, + reset_req, + write, + writedata, + + // outputs: + readdata + ) +; + + parameter INIT_FILE = "nios_system_onchip_memory.hex"; + + + output [ 31: 0] readdata; + input [ 15: 0] address; + input [ 3: 0] byteenable; + input chipselect; + input clk; + input clken; + input reset; + input reset_req; + input write; + input [ 31: 0] writedata; + + wire clocken0; + wire [ 31: 0] readdata; + wire wren; + assign wren = chipselect & write; + assign clocken0 = clken & ~reset_req; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clk), + .clocken0 (clocken0), + .data_a (writedata), + .q_a (readdata), + .wren_a (wren) + ); + + defparam the_altsyncram.byte_size = 8, + the_altsyncram.init_file = INIT_FILE, + the_altsyncram.lpm_type = "altsyncram", + the_altsyncram.maximum_depth = 51200, + the_altsyncram.numwords_a = 51200, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 16; + + //s1, which is an e_avalon_slave + //s2, which is an e_avalon_slave + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_push_switches.v b/db/ip/nios_system/submodules/nios_system_push_switches.v index 381d964..5b3cb8d 100644 --- a/db/ip/nios_system/submodules/nios_system_push_switches.v +++ b/db/ip/nios_system/submodules/nios_system_push_switches.v @@ -1,58 +1,58 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_push_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 2: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 2: 0] data_in; - wire [ 2: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {3 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_push_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 2: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 2: 0] data_in; + wire [ 2: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {3 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv index d81d1d6..52411df 100644 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv @@ -1,101 +1,101 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_002 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_002 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_002 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_002 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv index a829592..6f30bfb 100644 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv @@ -1,331 +1,331 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv index ab346d9..ce9f7a1 100644 --- a/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv +++ b/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv @@ -1,651 +1,651 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux_001 -// NUM_INPUTS: 18 -// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux_001 -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - input sink2_valid, - input [96-1 : 0] sink2_data, - input [18-1: 0] sink2_channel, - input sink2_startofpacket, - input sink2_endofpacket, - output sink2_ready, - - input sink3_valid, - input [96-1 : 0] sink3_data, - input [18-1: 0] sink3_channel, - input sink3_startofpacket, - input sink3_endofpacket, - output sink3_ready, - - input sink4_valid, - input [96-1 : 0] sink4_data, - input [18-1: 0] sink4_channel, - input sink4_startofpacket, - input sink4_endofpacket, - output sink4_ready, - - input sink5_valid, - input [96-1 : 0] sink5_data, - input [18-1: 0] sink5_channel, - input sink5_startofpacket, - input sink5_endofpacket, - output sink5_ready, - - input sink6_valid, - input [96-1 : 0] sink6_data, - input [18-1: 0] sink6_channel, - input sink6_startofpacket, - input sink6_endofpacket, - output sink6_ready, - - input sink7_valid, - input [96-1 : 0] sink7_data, - input [18-1: 0] sink7_channel, - input sink7_startofpacket, - input sink7_endofpacket, - output sink7_ready, - - input sink8_valid, - input [96-1 : 0] sink8_data, - input [18-1: 0] sink8_channel, - input sink8_startofpacket, - input sink8_endofpacket, - output sink8_ready, - - input sink9_valid, - input [96-1 : 0] sink9_data, - input [18-1: 0] sink9_channel, - input sink9_startofpacket, - input sink9_endofpacket, - output sink9_ready, - - input sink10_valid, - input [96-1 : 0] sink10_data, - input [18-1: 0] sink10_channel, - input sink10_startofpacket, - input sink10_endofpacket, - output sink10_ready, - - input sink11_valid, - input [96-1 : 0] sink11_data, - input [18-1: 0] sink11_channel, - input sink11_startofpacket, - input sink11_endofpacket, - output sink11_ready, - - input sink12_valid, - input [96-1 : 0] sink12_data, - input [18-1: 0] sink12_channel, - input sink12_startofpacket, - input sink12_endofpacket, - output sink12_ready, - - input sink13_valid, - input [96-1 : 0] sink13_data, - input [18-1: 0] sink13_channel, - input sink13_startofpacket, - input sink13_endofpacket, - output sink13_ready, - - input sink14_valid, - input [96-1 : 0] sink14_data, - input [18-1: 0] sink14_channel, - input sink14_startofpacket, - input sink14_endofpacket, - output sink14_ready, - - input sink15_valid, - input [96-1 : 0] sink15_data, - input [18-1: 0] sink15_channel, - input sink15_startofpacket, - input sink15_endofpacket, - output sink15_ready, - - input sink16_valid, - input [96-1 : 0] sink16_data, - input [18-1: 0] sink16_channel, - input sink16_startofpacket, - input sink16_endofpacket, - output sink16_ready, - - input sink17_valid, - input [96-1 : 0] sink17_data, - input [18-1: 0] sink17_channel, - input sink17_startofpacket, - input sink17_endofpacket, - output sink17_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 18; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - wire [PAYLOAD_W - 1 : 0] sink2_payload; - wire [PAYLOAD_W - 1 : 0] sink3_payload; - wire [PAYLOAD_W - 1 : 0] sink4_payload; - wire [PAYLOAD_W - 1 : 0] sink5_payload; - wire [PAYLOAD_W - 1 : 0] sink6_payload; - wire [PAYLOAD_W - 1 : 0] sink7_payload; - wire [PAYLOAD_W - 1 : 0] sink8_payload; - wire [PAYLOAD_W - 1 : 0] sink9_payload; - wire [PAYLOAD_W - 1 : 0] sink10_payload; - wire [PAYLOAD_W - 1 : 0] sink11_payload; - wire [PAYLOAD_W - 1 : 0] sink12_payload; - wire [PAYLOAD_W - 1 : 0] sink13_payload; - wire [PAYLOAD_W - 1 : 0] sink14_payload; - wire [PAYLOAD_W - 1 : 0] sink15_payload; - wire [PAYLOAD_W - 1 : 0] sink16_payload; - wire [PAYLOAD_W - 1 : 0] sink17_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - assign valid[2] = sink2_valid; - assign valid[3] = sink3_valid; - assign valid[4] = sink4_valid; - assign valid[5] = sink5_valid; - assign valid[6] = sink6_valid; - assign valid[7] = sink7_valid; - assign valid[8] = sink8_valid; - assign valid[9] = sink9_valid; - assign valid[10] = sink10_valid; - assign valid[11] = sink11_valid; - assign valid[12] = sink12_valid; - assign valid[13] = sink13_valid; - assign valid[14] = sink14_valid; - assign valid[15] = sink15_valid; - assign valid[16] = sink16_valid; - assign valid[17] = sink17_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - lock[2] = sink2_data[59]; - lock[3] = sink3_data[59]; - lock[4] = sink4_data[59]; - lock[5] = sink5_data[59]; - lock[6] = sink6_data[59]; - lock[7] = sink7_data[59]; - lock[8] = sink8_data[59]; - lock[9] = sink9_data[59]; - lock[10] = sink10_data[59]; - lock[11] = sink11_data[59]; - lock[12] = sink12_data[59]; - lock[13] = sink13_data[59]; - lock[14] = sink14_data[59]; - lock[15] = sink15_data[59]; - lock[16] = sink16_data[59]; - lock[17] = sink17_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - // 2 | 1 | 0 - // 3 | 1 | 0 - // 4 | 1 | 0 - // 5 | 1 | 0 - // 6 | 1 | 0 - // 7 | 1 | 0 - // 8 | 1 | 0 - // 9 | 1 | 0 - // 10 | 1 | 0 - // 11 | 1 | 0 - // 12 | 1 | 0 - // 13 | 1 | 0 - // 14 | 1 | 0 - // 15 | 1 | 0 - // 16 | 1 | 0 - // 17 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} } | - share_2 & { SHARE_COUNTER_W {next_grant[2]} } | - share_3 & { SHARE_COUNTER_W {next_grant[3]} } | - share_4 & { SHARE_COUNTER_W {next_grant[4]} } | - share_5 & { SHARE_COUNTER_W {next_grant[5]} } | - share_6 & { SHARE_COUNTER_W {next_grant[6]} } | - share_7 & { SHARE_COUNTER_W {next_grant[7]} } | - share_8 & { SHARE_COUNTER_W {next_grant[8]} } | - share_9 & { SHARE_COUNTER_W {next_grant[9]} } | - share_10 & { SHARE_COUNTER_W {next_grant[10]} } | - share_11 & { SHARE_COUNTER_W {next_grant[11]} } | - share_12 & { SHARE_COUNTER_W {next_grant[12]} } | - share_13 & { SHARE_COUNTER_W {next_grant[13]} } | - share_14 & { SHARE_COUNTER_W {next_grant[14]} } | - share_15 & { SHARE_COUNTER_W {next_grant[15]} } | - share_16 & { SHARE_COUNTER_W {next_grant[16]} } | - share_17 & { SHARE_COUNTER_W {next_grant[17]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - wire final_packet_2 = 1'b1; - - wire final_packet_3 = 1'b1; - - wire final_packet_4 = 1'b1; - - wire final_packet_5 = 1'b1; - - wire final_packet_6 = 1'b1; - - wire final_packet_7 = 1'b1; - - wire final_packet_8 = 1'b1; - - wire final_packet_9 = 1'b1; - - wire final_packet_10 = 1'b1; - - wire final_packet_11 = 1'b1; - - wire final_packet_12 = 1'b1; - - wire final_packet_13 = 1'b1; - - wire final_packet_14 = 1'b1; - - wire final_packet_15 = 1'b1; - - wire final_packet_16 = 1'b1; - - wire final_packet_17 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_17, - final_packet_16, - final_packet_15, - final_packet_14, - final_packet_13, - final_packet_12, - final_packet_11, - final_packet_10, - final_packet_9, - final_packet_8, - final_packet_7, - final_packet_6, - final_packet_5, - final_packet_4, - final_packet_3, - final_packet_2, - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - assign sink2_ready = src_ready && grant[2]; - assign sink3_ready = src_ready && grant[3]; - assign sink4_ready = src_ready && grant[4]; - assign sink5_ready = src_ready && grant[5]; - assign sink6_ready = src_ready && grant[6]; - assign sink7_ready = src_ready && grant[7]; - assign sink8_ready = src_ready && grant[8]; - assign sink9_ready = src_ready && grant[9]; - assign sink10_ready = src_ready && grant[10]; - assign sink11_ready = src_ready && grant[11]; - assign sink12_ready = src_ready && grant[12]; - assign sink13_ready = src_ready && grant[13]; - assign sink14_ready = src_ready && grant[14]; - assign sink15_ready = src_ready && grant[15]; - assign sink16_ready = src_ready && grant[16]; - assign sink17_ready = src_ready && grant[17]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} } | - sink2_payload & {PAYLOAD_W {grant[2]} } | - sink3_payload & {PAYLOAD_W {grant[3]} } | - sink4_payload & {PAYLOAD_W {grant[4]} } | - sink5_payload & {PAYLOAD_W {grant[5]} } | - sink6_payload & {PAYLOAD_W {grant[6]} } | - sink7_payload & {PAYLOAD_W {grant[7]} } | - sink8_payload & {PAYLOAD_W {grant[8]} } | - sink9_payload & {PAYLOAD_W {grant[9]} } | - sink10_payload & {PAYLOAD_W {grant[10]} } | - sink11_payload & {PAYLOAD_W {grant[11]} } | - sink12_payload & {PAYLOAD_W {grant[12]} } | - sink13_payload & {PAYLOAD_W {grant[13]} } | - sink14_payload & {PAYLOAD_W {grant[14]} } | - sink15_payload & {PAYLOAD_W {grant[15]} } | - sink16_payload & {PAYLOAD_W {grant[16]} } | - sink17_payload & {PAYLOAD_W {grant[17]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - assign sink2_payload = {sink2_channel,sink2_data, - sink2_startofpacket,sink2_endofpacket}; - assign sink3_payload = {sink3_channel,sink3_data, - sink3_startofpacket,sink3_endofpacket}; - assign sink4_payload = {sink4_channel,sink4_data, - sink4_startofpacket,sink4_endofpacket}; - assign sink5_payload = {sink5_channel,sink5_data, - sink5_startofpacket,sink5_endofpacket}; - assign sink6_payload = {sink6_channel,sink6_data, - sink6_startofpacket,sink6_endofpacket}; - assign sink7_payload = {sink7_channel,sink7_data, - sink7_startofpacket,sink7_endofpacket}; - assign sink8_payload = {sink8_channel,sink8_data, - sink8_startofpacket,sink8_endofpacket}; - assign sink9_payload = {sink9_channel,sink9_data, - sink9_startofpacket,sink9_endofpacket}; - assign sink10_payload = {sink10_channel,sink10_data, - sink10_startofpacket,sink10_endofpacket}; - assign sink11_payload = {sink11_channel,sink11_data, - sink11_startofpacket,sink11_endofpacket}; - assign sink12_payload = {sink12_channel,sink12_data, - sink12_startofpacket,sink12_endofpacket}; - assign sink13_payload = {sink13_channel,sink13_data, - sink13_startofpacket,sink13_endofpacket}; - assign sink14_payload = {sink14_channel,sink14_data, - sink14_startofpacket,sink14_endofpacket}; - assign sink15_payload = {sink15_channel,sink15_data, - sink15_startofpacket,sink15_endofpacket}; - assign sink16_payload = {sink16_channel,sink16_data, - sink16_startofpacket,sink16_endofpacket}; - assign sink17_payload = {sink17_channel,sink17_data, - sink17_startofpacket,sink17_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux_001 +// NUM_INPUTS: 18 +// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux_001 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + input sink2_valid, + input [96-1 : 0] sink2_data, + input [18-1: 0] sink2_channel, + input sink2_startofpacket, + input sink2_endofpacket, + output sink2_ready, + + input sink3_valid, + input [96-1 : 0] sink3_data, + input [18-1: 0] sink3_channel, + input sink3_startofpacket, + input sink3_endofpacket, + output sink3_ready, + + input sink4_valid, + input [96-1 : 0] sink4_data, + input [18-1: 0] sink4_channel, + input sink4_startofpacket, + input sink4_endofpacket, + output sink4_ready, + + input sink5_valid, + input [96-1 : 0] sink5_data, + input [18-1: 0] sink5_channel, + input sink5_startofpacket, + input sink5_endofpacket, + output sink5_ready, + + input sink6_valid, + input [96-1 : 0] sink6_data, + input [18-1: 0] sink6_channel, + input sink6_startofpacket, + input sink6_endofpacket, + output sink6_ready, + + input sink7_valid, + input [96-1 : 0] sink7_data, + input [18-1: 0] sink7_channel, + input sink7_startofpacket, + input sink7_endofpacket, + output sink7_ready, + + input sink8_valid, + input [96-1 : 0] sink8_data, + input [18-1: 0] sink8_channel, + input sink8_startofpacket, + input sink8_endofpacket, + output sink8_ready, + + input sink9_valid, + input [96-1 : 0] sink9_data, + input [18-1: 0] sink9_channel, + input sink9_startofpacket, + input sink9_endofpacket, + output sink9_ready, + + input sink10_valid, + input [96-1 : 0] sink10_data, + input [18-1: 0] sink10_channel, + input sink10_startofpacket, + input sink10_endofpacket, + output sink10_ready, + + input sink11_valid, + input [96-1 : 0] sink11_data, + input [18-1: 0] sink11_channel, + input sink11_startofpacket, + input sink11_endofpacket, + output sink11_ready, + + input sink12_valid, + input [96-1 : 0] sink12_data, + input [18-1: 0] sink12_channel, + input sink12_startofpacket, + input sink12_endofpacket, + output sink12_ready, + + input sink13_valid, + input [96-1 : 0] sink13_data, + input [18-1: 0] sink13_channel, + input sink13_startofpacket, + input sink13_endofpacket, + output sink13_ready, + + input sink14_valid, + input [96-1 : 0] sink14_data, + input [18-1: 0] sink14_channel, + input sink14_startofpacket, + input sink14_endofpacket, + output sink14_ready, + + input sink15_valid, + input [96-1 : 0] sink15_data, + input [18-1: 0] sink15_channel, + input sink15_startofpacket, + input sink15_endofpacket, + output sink15_ready, + + input sink16_valid, + input [96-1 : 0] sink16_data, + input [18-1: 0] sink16_channel, + input sink16_startofpacket, + input sink16_endofpacket, + output sink16_ready, + + input sink17_valid, + input [96-1 : 0] sink17_data, + input [18-1: 0] sink17_channel, + input sink17_startofpacket, + input sink17_endofpacket, + output sink17_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 18; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + wire [PAYLOAD_W - 1 : 0] sink2_payload; + wire [PAYLOAD_W - 1 : 0] sink3_payload; + wire [PAYLOAD_W - 1 : 0] sink4_payload; + wire [PAYLOAD_W - 1 : 0] sink5_payload; + wire [PAYLOAD_W - 1 : 0] sink6_payload; + wire [PAYLOAD_W - 1 : 0] sink7_payload; + wire [PAYLOAD_W - 1 : 0] sink8_payload; + wire [PAYLOAD_W - 1 : 0] sink9_payload; + wire [PAYLOAD_W - 1 : 0] sink10_payload; + wire [PAYLOAD_W - 1 : 0] sink11_payload; + wire [PAYLOAD_W - 1 : 0] sink12_payload; + wire [PAYLOAD_W - 1 : 0] sink13_payload; + wire [PAYLOAD_W - 1 : 0] sink14_payload; + wire [PAYLOAD_W - 1 : 0] sink15_payload; + wire [PAYLOAD_W - 1 : 0] sink16_payload; + wire [PAYLOAD_W - 1 : 0] sink17_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + assign valid[2] = sink2_valid; + assign valid[3] = sink3_valid; + assign valid[4] = sink4_valid; + assign valid[5] = sink5_valid; + assign valid[6] = sink6_valid; + assign valid[7] = sink7_valid; + assign valid[8] = sink8_valid; + assign valid[9] = sink9_valid; + assign valid[10] = sink10_valid; + assign valid[11] = sink11_valid; + assign valid[12] = sink12_valid; + assign valid[13] = sink13_valid; + assign valid[14] = sink14_valid; + assign valid[15] = sink15_valid; + assign valid[16] = sink16_valid; + assign valid[17] = sink17_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + lock[2] = sink2_data[59]; + lock[3] = sink3_data[59]; + lock[4] = sink4_data[59]; + lock[5] = sink5_data[59]; + lock[6] = sink6_data[59]; + lock[7] = sink7_data[59]; + lock[8] = sink8_data[59]; + lock[9] = sink9_data[59]; + lock[10] = sink10_data[59]; + lock[11] = sink11_data[59]; + lock[12] = sink12_data[59]; + lock[13] = sink13_data[59]; + lock[14] = sink14_data[59]; + lock[15] = sink15_data[59]; + lock[16] = sink16_data[59]; + lock[17] = sink17_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + // 2 | 1 | 0 + // 3 | 1 | 0 + // 4 | 1 | 0 + // 5 | 1 | 0 + // 6 | 1 | 0 + // 7 | 1 | 0 + // 8 | 1 | 0 + // 9 | 1 | 0 + // 10 | 1 | 0 + // 11 | 1 | 0 + // 12 | 1 | 0 + // 13 | 1 | 0 + // 14 | 1 | 0 + // 15 | 1 | 0 + // 16 | 1 | 0 + // 17 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} } | + share_2 & { SHARE_COUNTER_W {next_grant[2]} } | + share_3 & { SHARE_COUNTER_W {next_grant[3]} } | + share_4 & { SHARE_COUNTER_W {next_grant[4]} } | + share_5 & { SHARE_COUNTER_W {next_grant[5]} } | + share_6 & { SHARE_COUNTER_W {next_grant[6]} } | + share_7 & { SHARE_COUNTER_W {next_grant[7]} } | + share_8 & { SHARE_COUNTER_W {next_grant[8]} } | + share_9 & { SHARE_COUNTER_W {next_grant[9]} } | + share_10 & { SHARE_COUNTER_W {next_grant[10]} } | + share_11 & { SHARE_COUNTER_W {next_grant[11]} } | + share_12 & { SHARE_COUNTER_W {next_grant[12]} } | + share_13 & { SHARE_COUNTER_W {next_grant[13]} } | + share_14 & { SHARE_COUNTER_W {next_grant[14]} } | + share_15 & { SHARE_COUNTER_W {next_grant[15]} } | + share_16 & { SHARE_COUNTER_W {next_grant[16]} } | + share_17 & { SHARE_COUNTER_W {next_grant[17]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + wire final_packet_2 = 1'b1; + + wire final_packet_3 = 1'b1; + + wire final_packet_4 = 1'b1; + + wire final_packet_5 = 1'b1; + + wire final_packet_6 = 1'b1; + + wire final_packet_7 = 1'b1; + + wire final_packet_8 = 1'b1; + + wire final_packet_9 = 1'b1; + + wire final_packet_10 = 1'b1; + + wire final_packet_11 = 1'b1; + + wire final_packet_12 = 1'b1; + + wire final_packet_13 = 1'b1; + + wire final_packet_14 = 1'b1; + + wire final_packet_15 = 1'b1; + + wire final_packet_16 = 1'b1; + + wire final_packet_17 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_17, + final_packet_16, + final_packet_15, + final_packet_14, + final_packet_13, + final_packet_12, + final_packet_11, + final_packet_10, + final_packet_9, + final_packet_8, + final_packet_7, + final_packet_6, + final_packet_5, + final_packet_4, + final_packet_3, + final_packet_2, + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + assign sink2_ready = src_ready && grant[2]; + assign sink3_ready = src_ready && grant[3]; + assign sink4_ready = src_ready && grant[4]; + assign sink5_ready = src_ready && grant[5]; + assign sink6_ready = src_ready && grant[6]; + assign sink7_ready = src_ready && grant[7]; + assign sink8_ready = src_ready && grant[8]; + assign sink9_ready = src_ready && grant[9]; + assign sink10_ready = src_ready && grant[10]; + assign sink11_ready = src_ready && grant[11]; + assign sink12_ready = src_ready && grant[12]; + assign sink13_ready = src_ready && grant[13]; + assign sink14_ready = src_ready && grant[14]; + assign sink15_ready = src_ready && grant[15]; + assign sink16_ready = src_ready && grant[16]; + assign sink17_ready = src_ready && grant[17]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} } | + sink2_payload & {PAYLOAD_W {grant[2]} } | + sink3_payload & {PAYLOAD_W {grant[3]} } | + sink4_payload & {PAYLOAD_W {grant[4]} } | + sink5_payload & {PAYLOAD_W {grant[5]} } | + sink6_payload & {PAYLOAD_W {grant[6]} } | + sink7_payload & {PAYLOAD_W {grant[7]} } | + sink8_payload & {PAYLOAD_W {grant[8]} } | + sink9_payload & {PAYLOAD_W {grant[9]} } | + sink10_payload & {PAYLOAD_W {grant[10]} } | + sink11_payload & {PAYLOAD_W {grant[11]} } | + sink12_payload & {PAYLOAD_W {grant[12]} } | + sink13_payload & {PAYLOAD_W {grant[13]} } | + sink14_payload & {PAYLOAD_W {grant[14]} } | + sink15_payload & {PAYLOAD_W {grant[15]} } | + sink16_payload & {PAYLOAD_W {grant[16]} } | + sink17_payload & {PAYLOAD_W {grant[17]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + assign sink2_payload = {sink2_channel,sink2_data, + sink2_startofpacket,sink2_endofpacket}; + assign sink3_payload = {sink3_channel,sink3_data, + sink3_startofpacket,sink3_endofpacket}; + assign sink4_payload = {sink4_channel,sink4_data, + sink4_startofpacket,sink4_endofpacket}; + assign sink5_payload = {sink5_channel,sink5_data, + sink5_startofpacket,sink5_endofpacket}; + assign sink6_payload = {sink6_channel,sink6_data, + sink6_startofpacket,sink6_endofpacket}; + assign sink7_payload = {sink7_channel,sink7_data, + sink7_startofpacket,sink7_endofpacket}; + assign sink8_payload = {sink8_channel,sink8_data, + sink8_startofpacket,sink8_endofpacket}; + assign sink9_payload = {sink9_channel,sink9_data, + sink9_startofpacket,sink9_endofpacket}; + assign sink10_payload = {sink10_channel,sink10_data, + sink10_startofpacket,sink10_endofpacket}; + assign sink11_payload = {sink11_channel,sink11_data, + sink11_startofpacket,sink11_endofpacket}; + assign sink12_payload = {sink12_channel,sink12_data, + sink12_startofpacket,sink12_endofpacket}; + assign sink13_payload = {sink13_channel,sink13_data, + sink13_startofpacket,sink13_endofpacket}; + assign sink14_payload = {sink14_channel,sink14_data, + sink14_startofpacket,sink14_endofpacket}; + assign sink15_payload = {sink15_channel,sink15_data, + sink15_startofpacket,sink15_endofpacket}; + assign sink16_payload = {sink16_channel,sink16_data, + sink16_startofpacket,sink16_endofpacket}; + assign sink17_payload = {sink17_channel,sink17_data, + sink17_startofpacket,sink17_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/db/ip/nios_system/submodules/nios_system_switches.v b/db/ip/nios_system/submodules/nios_system_switches.v index 5121337..1fd0e98 100644 --- a/db/ip/nios_system/submodules/nios_system_switches.v +++ b/db/ip/nios_system/submodules/nios_system_switches.v @@ -1,58 +1,58 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git "a/db/lights.\0501\051.cnf.cdb" "b/db/lights.\0501\051.cnf.cdb" index a8137fc..033a703 100644 --- "a/db/lights.\0501\051.cnf.cdb" +++ "b/db/lights.\0501\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\0501\051.cnf.hdb" "b/db/lights.\0501\051.cnf.hdb" index 97afe92..2dba14b 100644 --- "a/db/lights.\0501\051.cnf.hdb" +++ "b/db/lights.\0501\051.cnf.hdb" Binary files differ diff --git "a/db/lights.\05010\051.cnf.cdb" "b/db/lights.\05010\051.cnf.cdb" index 943faa3..591394b 100644 --- "a/db/lights.\05010\051.cnf.cdb" +++ "b/db/lights.\05010\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\05010\051.cnf.hdb" "b/db/lights.\05010\051.cnf.hdb" index 7db1759..8ec0795 100644 --- "a/db/lights.\05010\051.cnf.hdb" +++ "b/db/lights.\05010\051.cnf.hdb" Binary files differ diff --git "a/db/lights.\050102\051.cnf.cdb" "b/db/lights.\050102\051.cnf.cdb" new file mode 100644 index 0000000..8e2dbe3 --- /dev/null +++ "b/db/lights.\050102\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\050102\051.cnf.hdb" "b/db/lights.\050102\051.cnf.hdb" new file mode 100644 index 0000000..f4a58f8 --- /dev/null +++ "b/db/lights.\050102\051.cnf.hdb" Binary files differ diff --git "a/db/lights.\050103\051.cnf.cdb" "b/db/lights.\050103\051.cnf.cdb" new file mode 100644 index 0000000..4c448cf --- /dev/null +++ "b/db/lights.\050103\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\050103\051.cnf.hdb" "b/db/lights.\050103\051.cnf.hdb" new file mode 100644 index 0000000..6790875 --- /dev/null +++ "b/db/lights.\050103\051.cnf.hdb" Binary files differ diff --git "a/db/lights.\05011\051.cnf.cdb" "b/db/lights.\05011\051.cnf.cdb" index 7d17bc5..4d25f1e 100644 --- "a/db/lights.\05011\051.cnf.cdb" +++ "b/db/lights.\05011\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\05011\051.cnf.hdb" "b/db/lights.\05011\051.cnf.hdb" index 5f620d5..1a2d9c6 100644 --- "a/db/lights.\05011\051.cnf.hdb" +++ "b/db/lights.\05011\051.cnf.hdb" Binary files differ diff --git "a/db/lights.\05013\051.cnf.cdb" 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"b/db/lights.\05091\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\05091\051.cnf.hdb" "b/db/lights.\05091\051.cnf.hdb" index 28d2e24..d43928e 100644 --- "a/db/lights.\05091\051.cnf.hdb" +++ "b/db/lights.\05091\051.cnf.hdb" Binary files differ diff --git "a/db/lights.\05092\051.cnf.cdb" "b/db/lights.\05092\051.cnf.cdb" index 9a21810..ef14e99 100644 --- "a/db/lights.\05092\051.cnf.cdb" +++ "b/db/lights.\05092\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\05093\051.cnf.cdb" "b/db/lights.\05093\051.cnf.cdb" index 3d8aca7..1992179 100644 --- "a/db/lights.\05093\051.cnf.cdb" +++ "b/db/lights.\05093\051.cnf.cdb" Binary files differ diff --git "a/db/lights.\05093\051.cnf.hdb" "b/db/lights.\05093\051.cnf.hdb" index a25d3b1..de3eb88 100644 --- "a/db/lights.\05093\051.cnf.hdb" +++ "b/db/lights.\05093\051.cnf.hdb" Binary files differ diff --git a/db/lights.asm.qmsg b/db/lights.asm.qmsg index 675076d..d4c2583 100644 --- a/db/lights.asm.qmsg +++ b/db/lights.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609994956 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609994956 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:33:14 2016 " "Processing started: Fri Dec 02 01:33:14 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609994956 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480609994956 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480609994957 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1480609999579 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480609999709 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "477 " "Peak virtual memory: 477 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480610001361 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:33:21 2016 " "Processing ended: Fri Dec 02 01:33:21 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480610001361 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480610001361 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480610001361 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480610001361 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1482368914623 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1482368914623 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 22 10:08:34 2016 " "Processing started: Thu Dec 22 10:08:34 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1482368914623 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1482368914623 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1482368914623 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1482368919572 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1482368919706 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "481 " "Peak virtual memory: 481 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368921649 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:08:41 2016 " "Processing ended: Thu Dec 22 10:08:41 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368921649 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368921649 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368921649 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1482368921649 ""} diff --git a/db/lights.asm.rdb b/db/lights.asm.rdb index bc83e7f..9e7d533 100644 --- a/db/lights.asm.rdb +++ b/db/lights.asm.rdb Binary files differ diff --git a/db/lights.asm_labs.ddb b/db/lights.asm_labs.ddb index 03ed3a1..822b00c 100644 --- a/db/lights.asm_labs.ddb +++ b/db/lights.asm_labs.ddb Binary files differ diff --git a/db/lights.cbx.xml b/db/lights.cbx.xml index 8d699c9..e529c3c 100644 --- a/db/lights.cbx.xml +++ b/db/lights.cbx.xml @@ -1,11 +1,11 @@ - - - - - - - - - - - + + + + + + + + + + + diff --git a/db/lights.cmp.bpm b/db/lights.cmp.bpm index 1b1e21d..e89ad04 100644 --- a/db/lights.cmp.bpm +++ b/db/lights.cmp.bpm Binary files differ diff --git a/db/lights.cmp.cdb b/db/lights.cmp.cdb index c4330a5..3f5da5e 100644 --- a/db/lights.cmp.cdb +++ b/db/lights.cmp.cdb Binary files differ diff --git a/db/lights.cmp.hdb b/db/lights.cmp.hdb index 38ffd90..5aad9c6 100644 --- a/db/lights.cmp.hdb +++ b/db/lights.cmp.hdb Binary files differ diff --git a/db/lights.cmp.idb b/db/lights.cmp.idb index 4ec9861..9fc3827 100644 --- a/db/lights.cmp.idb +++ b/db/lights.cmp.idb Binary files differ diff --git a/db/lights.cmp.logdb b/db/lights.cmp.logdb index 9ea246c..1de615f 100644 --- a/db/lights.cmp.logdb +++ b/db/lights.cmp.logdb @@ -1,164 +1,164 @@ -v1 -IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, -IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, -IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, -IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, -IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, -IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, -IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, -IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, -IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, -IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, -IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, -IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, -IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, -IO_RULES_MATRIX,Total Pass,118;0;118;0;0;122;118;0;122;122;0;49;0;0;31;0;49;31;0;0;0;49;0;0;0;0;0;122;0;0, -IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,Total Inapplicable,4;122;4;122;122;0;4;122;0;0;122;73;122;122;91;122;73;91;122;122;122;73;122;122;122;122;122;0;122;122, -IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, -IO_RULES_MATRIX,LEDG[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDG[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LEDR[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX6[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,HEX7[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_RS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_RW,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_data[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_EN,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_ON,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,LCD_BLON,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,SW[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tms,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tck,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tdi,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_MATRIX,altera_reserved_tdo,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, -IO_RULES_SUMMARY,Total I/O Rules,30, -IO_RULES_SUMMARY,Number of I/O Rules Passed,12, -IO_RULES_SUMMARY,Number of I/O Rules Failed,0, -IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, -IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,118;0;118;0;0;122;118;0;122;122;0;49;0;0;31;0;49;31;0;0;0;49;0;0;0;0;0;122;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,4;122;4;122;122;0;4;122;0;0;122;73;122;122;91;122;73;91;122;122;122;73;122;122;122;122;122;0;122;122, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,LEDG[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 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+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tms,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tck,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tdi,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tdo,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/db/lights.cmp.rdb b/db/lights.cmp.rdb index be196ad..4c83dc6 100644 --- a/db/lights.cmp.rdb +++ b/db/lights.cmp.rdb Binary files differ diff --git a/db/lights.db_info b/db/lights.db_info index ee35097..4b78a0f 100644 --- a/db/lights.db_info +++ b/db/lights.db_info @@ -1,3 +1,3 @@ -Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -Version_Index = 302049280 -Creation_Time = Fri Dec 16 16:05:25 2016 +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Thu Dec 22 10:01:16 2016 diff --git a/db/lights.fit.qmsg b/db/lights.fit.qmsg index 6bdc00b..df5236c 100644 --- a/db/lights.fit.qmsg +++ b/db/lights.fit.qmsg @@ -1,53 +1,53 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1480609963052 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "lights EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"lights\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480609963096 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609963161 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609963162 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480609963162 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480609963377 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1480609963389 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1480609964002 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1480609964002 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11996 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609964012 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11998 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609964012 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12000 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609964012 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12002 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609964012 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12004 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1480609964012 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1480609964012 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480609964015 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480609964056 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480609966897 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1480609966897 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480609966945 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480609966956 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609967003 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609967003 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480609967003 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1480609967003 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1480609967004 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609967004 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609967004 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1480609967004 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1480609967004 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609967253 ""} } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11964 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609967253 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609967254 ""} } { { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4019 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609967254 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609967254 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 177 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4470 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609967254 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3700 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 3289 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609967254 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0 " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0" { } { { "altera_std_synchronizer.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5950 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1480609967254 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1480609967254 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 172 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 905 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609967254 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1480609967255 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 68 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5706 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1480609967255 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480609968247 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609968255 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1480609968255 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609968263 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480609968273 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480609968280 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480609968280 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480609968286 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480609968363 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 EC " "Packed 8 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1480609968370 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480609968370 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK2_50 " "Ignored I/O standard assignment to node \"CLOCK2_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK3_50 " "Ignored I/O standard assignment to node \"CLOCK3_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[0\] " "Ignored I/O standard assignment to node \"DRAM_BA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[1\] " "Ignored I/O standard assignment to node \"DRAM_BA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[16\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[17\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[18\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[19\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[20\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[21\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[22\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[23\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[24\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[25\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[26\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[27\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[28\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[29\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[30\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[31\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SCLK " "Ignored I/O standard assignment to node \"EEP_I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SDAT " "Ignored I/O standard assignment to node \"EEP_I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_GTX_CLK " "Ignored I/O standard assignment to node \"ENET0_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_INT_N " "Ignored I/O standard assignment to node \"ENET0_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_LINK100 " "Ignored I/O standard assignment to node \"ENET0_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDC " "Ignored I/O standard assignment to node \"ENET0_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDIO " "Ignored I/O standard assignment to node \"ENET0_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RST_N " "Ignored I/O standard assignment to node \"ENET0_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CLK " "Ignored I/O standard assignment to node \"ENET0_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_COL " "Ignored I/O standard assignment to node \"ENET0_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CRS " "Ignored I/O standard assignment to node \"ENET0_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DV " "Ignored I/O standard assignment to node \"ENET0_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_ER " "Ignored I/O standard assignment to node \"ENET0_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_CLK " "Ignored I/O standard assignment to node \"ENET0_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_EN " "Ignored I/O standard assignment to node \"ENET0_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_ER " "Ignored I/O standard assignment to node \"ENET0_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_GTX_CLK " "Ignored I/O standard assignment to node \"ENET1_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_INT_N " "Ignored I/O standard assignment to node \"ENET1_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_LINK100 " "Ignored I/O standard assignment to node \"ENET1_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDC " "Ignored I/O standard assignment to node \"ENET1_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDIO " "Ignored I/O standard assignment to node \"ENET1_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RST_N " "Ignored I/O standard assignment to node \"ENET1_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CLK " "Ignored I/O standard assignment to node \"ENET1_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_COL " "Ignored I/O standard assignment to node \"ENET1_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CRS " "Ignored I/O standard assignment to node \"ENET1_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DV " "Ignored I/O standard assignment to node \"ENET1_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_ER " "Ignored I/O standard assignment to node \"ENET1_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_CLK " "Ignored I/O standard assignment to node \"ENET1_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_EN " "Ignored I/O standard assignment to node \"ENET1_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_ER " "Ignored I/O standard assignment to node \"ENET1_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENETCLK_25 " "Ignored I/O standard assignment to node \"ENETCLK_25\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[0\] " "Ignored I/O standard assignment to node \"EX_IO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[1\] " "Ignored I/O standard assignment to node \"EX_IO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[2\] " "Ignored I/O standard assignment to node \"EX_IO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[3\] " "Ignored I/O standard assignment to node \"EX_IO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[4\] " "Ignored I/O standard assignment to node \"EX_IO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[5\] " "Ignored I/O standard assignment to node \"EX_IO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[6\] " "Ignored I/O standard assignment to node \"EX_IO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[22\] " "Ignored I/O standard assignment to node \"FL_ADDR\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968635 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[0\] " "Ignored I/O standard assignment to node \"GPIO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[10\] " "Ignored I/O standard assignment to node \"GPIO\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[11\] " "Ignored I/O standard assignment to node \"GPIO\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[12\] " "Ignored I/O standard assignment to node \"GPIO\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[13\] " "Ignored I/O standard assignment to node \"GPIO\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[14\] " "Ignored I/O standard assignment to node \"GPIO\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[15\] " "Ignored I/O standard assignment to node \"GPIO\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[16\] " "Ignored I/O standard assignment to node \"GPIO\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[17\] " "Ignored I/O standard assignment to node \"GPIO\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[18\] " "Ignored I/O standard assignment to node \"GPIO\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[19\] " "Ignored I/O standard assignment to node \"GPIO\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[1\] " "Ignored I/O standard assignment to node \"GPIO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[20\] " "Ignored I/O standard assignment to node \"GPIO\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[21\] " "Ignored I/O standard assignment to node \"GPIO\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[22\] " "Ignored I/O standard assignment to node \"GPIO\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[23\] " "Ignored I/O standard assignment to node \"GPIO\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[24\] " "Ignored I/O standard assignment to node \"GPIO\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[25\] " "Ignored I/O standard assignment to node \"GPIO\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[26\] " "Ignored I/O standard assignment to node \"GPIO\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[27\] " "Ignored I/O standard assignment to node \"GPIO\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[28\] " "Ignored I/O standard assignment to node \"GPIO\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[29\] " "Ignored I/O standard assignment to node \"GPIO\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[2\] " "Ignored I/O standard assignment to node \"GPIO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[30\] " "Ignored I/O standard assignment to node \"GPIO\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[31\] " "Ignored I/O standard assignment to node \"GPIO\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[32\] " "Ignored I/O standard assignment to node \"GPIO\[32\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[33\] " "Ignored I/O standard assignment to node \"GPIO\[33\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[34\] " "Ignored I/O standard assignment to node \"GPIO\[34\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[35\] " "Ignored I/O standard assignment to node \"GPIO\[35\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[3\] " "Ignored I/O standard assignment to node \"GPIO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[4\] " "Ignored I/O standard assignment to node \"GPIO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[5\] " "Ignored I/O standard assignment to node \"GPIO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[6\] " "Ignored I/O standard assignment to node \"GPIO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[7\] " "Ignored I/O standard assignment to node \"GPIO\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[8\] " "Ignored I/O standard assignment to node \"GPIO\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[9\] " "Ignored I/O standard assignment to node \"GPIO\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN0 " "Ignored I/O standard assignment to node \"HSMC_CLKIN0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT0 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[0\] " "Ignored I/O standard assignment to node \"HSMC_D\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[1\] " "Ignored I/O standard assignment to node \"HSMC_D\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[2\] " "Ignored I/O standard assignment to node \"HSMC_D\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[3\] " "Ignored I/O standard assignment to node \"HSMC_D\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "IRDA_RXD " "Ignored I/O standard assignment to node \"IRDA_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LEDG\[8\] " "Ignored I/O standard assignment to node \"LEDG\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[0\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[1\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_CS_N " "Ignored I/O standard assignment to node \"OTG_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[0\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[1\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[0\] " "Ignored I/O standard assignment to node \"OTG_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[10\] " "Ignored I/O standard assignment to node \"OTG_DATA\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[11\] " "Ignored I/O standard assignment to node \"OTG_DATA\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[12\] " "Ignored I/O standard assignment to node \"OTG_DATA\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[13\] " "Ignored I/O standard assignment to node \"OTG_DATA\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[14\] " "Ignored I/O standard assignment to node \"OTG_DATA\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[15\] " "Ignored I/O standard assignment to node \"OTG_DATA\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[1\] " "Ignored I/O standard assignment to node \"OTG_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[2\] " "Ignored I/O standard assignment to node \"OTG_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[3\] " "Ignored I/O standard assignment to node \"OTG_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[4\] " "Ignored I/O standard assignment to node \"OTG_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[5\] " "Ignored I/O standard assignment to node \"OTG_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[6\] " "Ignored I/O standard assignment to node \"OTG_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[7\] " "Ignored I/O standard assignment to node \"OTG_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[8\] " "Ignored I/O standard assignment to node \"OTG_DATA\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[9\] " "Ignored I/O standard assignment to node \"OTG_DATA\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[0\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[1\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_FSPEED " "Ignored I/O standard assignment to node \"OTG_FSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[0\] " "Ignored I/O standard assignment to node \"OTG_INT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[1\] " "Ignored I/O standard assignment to node \"OTG_INT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_LSPEED " "Ignored I/O standard assignment to node \"OTG_LSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RD_N " "Ignored I/O standard assignment to node \"OTG_RD_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RST_N " "Ignored I/O standard assignment to node \"OTG_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_WR_N " "Ignored I/O standard assignment to node \"OTG_WR_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK " "Ignored I/O standard assignment to node \"PS2_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK2 " "Ignored I/O standard assignment to node \"PS2_CLK2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT " "Ignored I/O standard assignment to node \"PS2_DAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT2 " "Ignored I/O standard assignment to node \"PS2_DAT2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[0\] " "Ignored I/O standard assignment to node \"SD_DAT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[1\] " "Ignored I/O standard assignment to node \"SD_DAT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[2\] " "Ignored I/O standard assignment to node \"SD_DAT\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[3\] " "Ignored I/O standard assignment to node \"SD_DAT\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKIN " "Ignored I/O standard assignment to node \"SMA_CLKIN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKOUT " "Ignored I/O standard assignment to node \"SMA_CLKOUT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[13\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[14\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[15\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[16\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[17\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[18\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[19\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_CE_N " "Ignored I/O standard assignment to node \"SRAM_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_LB_N " "Ignored I/O standard assignment to node \"SRAM_LB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_OE_N " "Ignored I/O standard assignment to node \"SRAM_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_UB_N " "Ignored I/O standard assignment to node \"SRAM_UB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_WE_N " "Ignored I/O standard assignment to node \"SRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_CLK27 " "Ignored I/O standard assignment to node \"TD_CLK27\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Ignored I/O standard assignment to node \"TD_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_RESET_N " "Ignored I/O standard assignment to node \"TD_RESET_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Ignored I/O standard assignment to node \"TD_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_BLANK_N " "Ignored I/O standard assignment to node \"VGA_BLANK_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[0\] " "Ignored I/O standard assignment to node \"VGA_B\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[1\] " "Ignored I/O standard assignment to node \"VGA_B\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[2\] " "Ignored I/O standard assignment to node \"VGA_B\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[3\] " "Ignored I/O standard assignment to node \"VGA_B\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[4\] " "Ignored I/O standard assignment to node \"VGA_B\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[5\] " "Ignored I/O standard assignment to node \"VGA_B\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[6\] " "Ignored I/O standard assignment to node \"VGA_B\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[7\] " "Ignored I/O standard assignment to node \"VGA_B\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_CLK " "Ignored I/O standard assignment to node \"VGA_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[0\] " "Ignored I/O standard assignment to node \"VGA_G\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[1\] " "Ignored I/O standard assignment to node \"VGA_G\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[2\] " "Ignored I/O standard assignment to node \"VGA_G\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[3\] " "Ignored I/O standard assignment to node \"VGA_G\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[4\] " "Ignored I/O standard assignment to node \"VGA_G\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[5\] " "Ignored I/O standard assignment to node \"VGA_G\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[6\] " "Ignored I/O standard assignment to node \"VGA_G\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[7\] " "Ignored I/O standard assignment to node \"VGA_G\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_HS " "Ignored I/O standard assignment to node \"VGA_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[0\] " "Ignored I/O standard assignment to node \"VGA_R\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[1\] " "Ignored I/O standard assignment to node \"VGA_R\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[2\] " "Ignored I/O standard assignment to node \"VGA_R\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[3\] " "Ignored I/O standard assignment to node \"VGA_R\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[4\] " "Ignored I/O standard assignment to node \"VGA_R\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[5\] " "Ignored I/O standard assignment to node \"VGA_R\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[6\] " "Ignored I/O standard assignment to node \"VGA_R\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[7\] " "Ignored I/O standard assignment to node \"VGA_R\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_SYNC_N " "Ignored I/O standard assignment to node \"VGA_SYNC_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_VS " "Ignored I/O standard assignment to node \"VGA_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609968636 ""} } { } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609968635 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[0\] " "Node \"OTG_DACK_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[1\] " "Node \"OTG_DACK_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[1\] " "Node \"OTG_DREQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[0\] " "Node \"OTG_INT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[1\] " "Node \"OTG_INT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1480609968663 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480609968663 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:05 " "Fitter preparation operations ending: elapsed time is 00:00:05" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609968690 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480609974963 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609976462 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480609976497 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480609978406 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609978407 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480609979528 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "23 X58_Y24 X68_Y36 " "Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X58_Y24 to location X68_Y36" { } { { "loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 1 { 0 "Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X58_Y24 to location X68_Y36"} { { 11 { 0 "Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X58_Y24 to location X68_Y36"} 58 24 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1480609984854 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480609984854 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Fitter routing operations ending: elapsed time is 00:00:03" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609985830 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1480609985833 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1480609985833 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480609985833 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.75 " "Total time spent on timing analysis during the Fitter is 0.75 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1480609985994 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609986074 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609987128 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480609987213 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480609988215 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480609989448 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480609991135 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "9 Cyclone IV E " "9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[0\] 3.3-V LVTTL L3 " "Pin LCD_data\[0\] uses I/O standard 3.3-V LVTTL at L3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[0\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 352 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[1\] 3.3-V LVTTL L1 " "Pin LCD_data\[1\] uses I/O standard 3.3-V LVTTL at L1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[1\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 353 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[2\] 3.3-V LVTTL L2 " "Pin LCD_data\[2\] uses I/O standard 3.3-V LVTTL at L2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[2\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[3\] 3.3-V LVTTL K7 " "Pin LCD_data\[3\] uses I/O standard 3.3-V LVTTL at K7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[3\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[4\] 3.3-V LVTTL K1 " "Pin LCD_data\[4\] uses I/O standard 3.3-V LVTTL at K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[4\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[5\] 3.3-V LVTTL K2 " "Pin LCD_data\[5\] uses I/O standard 3.3-V LVTTL at K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[5\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[6\] 3.3-V LVTTL M3 " "Pin LCD_data\[6\] uses I/O standard 3.3-V LVTTL at M3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[6\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[7\] 3.3-V LVTTL M5 " "Pin LCD_data\[7\] uses I/O standard 3.3-V LVTTL at M5" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[7\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL Y2 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1480609991178 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1480609991178 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480609991773 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 827 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 827 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1016 " "Peak virtual memory: 1016 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609993882 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:33:13 2016 " "Processing ended: Fri Dec 02 01:33:13 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609993882 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609993882 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609993882 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480609993882 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1482368874734 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "lights EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"lights\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1482368874772 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1482368874834 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1482368874834 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1482368874834 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1482368875056 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1482368875056 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1482368875657 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1482368875657 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11994 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11996 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11998 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12000 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 12002 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1482368875657 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1482368875657 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1482368875673 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1482368875704 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368879713 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1482368879713 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1482368879797 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1482368879828 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368879929 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1482368879929 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1482368879929 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879929 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1482368879929 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1482368879929 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 11962 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4019 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node nios_system:NiosII\|altera_reset_controller:rst_controller\|WideOr0~0" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 177 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 4470 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|W_rf_wren" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3700 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 3289 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0 " "Destination node nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1~0" { } { { "altera_std_synchronizer.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5950 9224 9983 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 172 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 905 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node nios_system:NiosII\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1482368880414 ""} } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 68 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 5706 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1482368880414 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1482368882447 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1482368882492 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1482368882493 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1482368882547 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1482368882613 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1482368882635 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1482368882636 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1482368882651 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1482368882819 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "8 EC " "Packed 8 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Quartus II" 0 -1 1482368882837 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1482368882837 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK2_50 " "Ignored I/O standard assignment to node \"CLOCK2_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK3_50 " "Ignored I/O standard assignment to node \"CLOCK3_50\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[0\] " "Ignored I/O standard assignment to node \"DRAM_BA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA\[1\] " "Ignored I/O standard assignment to node \"DRAM_BA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQM\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQM\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[16\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[17\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[18\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[19\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[20\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[21\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[22\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[23\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[24\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[25\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[26\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[27\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[28\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[29\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[30\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[31\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SCLK " "Ignored I/O standard assignment to node \"EEP_I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EEP_I2C_SDAT " "Ignored I/O standard assignment to node \"EEP_I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_GTX_CLK " "Ignored I/O standard assignment to node \"ENET0_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_INT_N " "Ignored I/O standard assignment to node \"ENET0_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_LINK100 " "Ignored I/O standard assignment to node \"ENET0_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDC " "Ignored I/O standard assignment to node \"ENET0_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_MDIO " "Ignored I/O standard assignment to node \"ENET0_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RST_N " "Ignored I/O standard assignment to node \"ENET0_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CLK " "Ignored I/O standard assignment to node \"ENET0_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_COL " "Ignored I/O standard assignment to node \"ENET0_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_CRS " "Ignored I/O standard assignment to node \"ENET0_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_DV " "Ignored I/O standard assignment to node \"ENET0_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_RX_ER " "Ignored I/O standard assignment to node \"ENET0_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_CLK " "Ignored I/O standard assignment to node \"ENET0_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET0_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_EN " "Ignored I/O standard assignment to node \"ENET0_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET0_TX_ER " "Ignored I/O standard assignment to node \"ENET0_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_GTX_CLK " "Ignored I/O standard assignment to node \"ENET1_GTX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_INT_N " "Ignored I/O standard assignment to node \"ENET1_INT_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_LINK100 " "Ignored I/O standard assignment to node \"ENET1_LINK100\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDC " "Ignored I/O standard assignment to node \"ENET1_MDC\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_MDIO " "Ignored I/O standard assignment to node \"ENET1_MDIO\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RST_N " "Ignored I/O standard assignment to node \"ENET1_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CLK " "Ignored I/O standard assignment to node \"ENET1_RX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_COL " "Ignored I/O standard assignment to node \"ENET1_RX_COL\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_CRS " "Ignored I/O standard assignment to node \"ENET1_RX_CRS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_RX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_DV " "Ignored I/O standard assignment to node \"ENET1_RX_DV\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_RX_ER " "Ignored I/O standard assignment to node \"ENET1_RX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_CLK " "Ignored I/O standard assignment to node \"ENET1_TX_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Ignored I/O standard assignment to node \"ENET1_TX_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_EN " "Ignored I/O standard assignment to node \"ENET1_TX_EN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENET1_TX_ER " "Ignored I/O standard assignment to node \"ENET1_TX_ER\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "ENETCLK_25 " "Ignored I/O standard assignment to node \"ENETCLK_25\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[0\] " "Ignored I/O standard assignment to node \"EX_IO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[1\] " "Ignored I/O standard assignment to node \"EX_IO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[2\] " "Ignored I/O standard assignment to node \"EX_IO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[3\] " "Ignored I/O standard assignment to node \"EX_IO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[4\] " "Ignored I/O standard assignment to node \"EX_IO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[5\] " "Ignored I/O standard assignment to node \"EX_IO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EX_IO\[6\] " "Ignored I/O standard assignment to node \"EX_IO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[22\] " "Ignored I/O standard assignment to node \"FL_ADDR\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[0\] " "Ignored I/O standard assignment to node \"GPIO\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[10\] " "Ignored I/O standard assignment to node \"GPIO\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[11\] " "Ignored I/O standard assignment to node \"GPIO\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[12\] " "Ignored I/O standard assignment to node \"GPIO\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[13\] " "Ignored I/O standard assignment to node \"GPIO\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[14\] " "Ignored I/O standard assignment to node \"GPIO\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[15\] " "Ignored I/O standard assignment to node \"GPIO\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[16\] " "Ignored I/O standard assignment to node \"GPIO\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[17\] " "Ignored I/O standard assignment to node \"GPIO\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[18\] " "Ignored I/O standard assignment to node \"GPIO\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[19\] " "Ignored I/O standard assignment to node \"GPIO\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[1\] " "Ignored I/O standard assignment to node \"GPIO\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[20\] " "Ignored I/O standard assignment to node \"GPIO\[20\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[21\] " "Ignored I/O standard assignment to node \"GPIO\[21\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[22\] " "Ignored I/O standard assignment to node \"GPIO\[22\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[23\] " "Ignored I/O standard assignment to node \"GPIO\[23\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[24\] " "Ignored I/O standard assignment to node \"GPIO\[24\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[25\] " "Ignored I/O standard assignment to node \"GPIO\[25\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[26\] " "Ignored I/O standard assignment to node \"GPIO\[26\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[27\] " "Ignored I/O standard assignment to node \"GPIO\[27\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[28\] " "Ignored I/O standard assignment to node \"GPIO\[28\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[29\] " "Ignored I/O standard assignment to node \"GPIO\[29\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[2\] " "Ignored I/O standard assignment to node \"GPIO\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[30\] " "Ignored I/O standard assignment to node \"GPIO\[30\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[31\] " "Ignored I/O standard assignment to node \"GPIO\[31\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[32\] " "Ignored I/O standard assignment to node \"GPIO\[32\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[33\] " "Ignored I/O standard assignment to node \"GPIO\[33\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[34\] " "Ignored I/O standard assignment to node \"GPIO\[34\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[35\] " "Ignored I/O standard assignment to node \"GPIO\[35\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[3\] " "Ignored I/O standard assignment to node \"GPIO\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[4\] " "Ignored I/O standard assignment to node \"GPIO\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[5\] " "Ignored I/O standard assignment to node \"GPIO\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[6\] " "Ignored I/O standard assignment to node \"GPIO\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[7\] " "Ignored I/O standard assignment to node \"GPIO\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[8\] " "Ignored I/O standard assignment to node \"GPIO\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO\[9\] " "Ignored I/O standard assignment to node \"GPIO\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN0 " "Ignored I/O standard assignment to node \"HSMC_CLKIN0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKIN_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKIN_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT0 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT0\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_N2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_N2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P1 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P1\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_CLKOUT_P2 " "Ignored I/O standard assignment to node \"HSMC_CLKOUT_P2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[0\] " "Ignored I/O standard assignment to node \"HSMC_D\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[1\] " "Ignored I/O standard assignment to node \"HSMC_D\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[2\] " "Ignored I/O standard assignment to node \"HSMC_D\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_D\[3\] " "Ignored I/O standard assignment to node \"HSMC_D\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_RX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_N\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Ignored I/O standard assignment to node \"HSMC_TX_D_P\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "IRDA_RXD " "Ignored I/O standard assignment to node \"IRDA_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LEDG\[8\] " "Ignored I/O standard assignment to node \"LEDG\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[0\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_ADDR\[1\] " "Ignored I/O standard assignment to node \"OTG_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_CS_N " "Ignored I/O standard assignment to node \"OTG_CS_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[0\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DACK_N\[1\] " "Ignored I/O standard assignment to node \"OTG_DACK_N\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[0\] " "Ignored I/O standard assignment to node \"OTG_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[10\] " "Ignored I/O standard assignment to node \"OTG_DATA\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[11\] " "Ignored I/O standard assignment to node \"OTG_DATA\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[12\] " "Ignored I/O standard assignment to node \"OTG_DATA\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[13\] " "Ignored I/O standard assignment to node \"OTG_DATA\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[14\] " "Ignored I/O standard assignment to node \"OTG_DATA\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[15\] " "Ignored I/O standard assignment to node \"OTG_DATA\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[1\] " "Ignored I/O standard assignment to node \"OTG_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[2\] " "Ignored I/O standard assignment to node \"OTG_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[3\] " "Ignored I/O standard assignment to node \"OTG_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[4\] " "Ignored I/O standard assignment to node \"OTG_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[5\] " "Ignored I/O standard assignment to node \"OTG_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[6\] " "Ignored I/O standard assignment to node \"OTG_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[7\] " "Ignored I/O standard assignment to node \"OTG_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[8\] " "Ignored I/O standard assignment to node \"OTG_DATA\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DATA\[9\] " "Ignored I/O standard assignment to node \"OTG_DATA\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[0\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_DREQ\[1\] " "Ignored I/O standard assignment to node \"OTG_DREQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_FSPEED " "Ignored I/O standard assignment to node \"OTG_FSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[0\] " "Ignored I/O standard assignment to node \"OTG_INT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_INT\[1\] " "Ignored I/O standard assignment to node \"OTG_INT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_LSPEED " "Ignored I/O standard assignment to node \"OTG_LSPEED\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RD_N " "Ignored I/O standard assignment to node \"OTG_RD_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_RST_N " "Ignored I/O standard assignment to node \"OTG_RST_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "OTG_WR_N " "Ignored I/O standard assignment to node \"OTG_WR_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK " "Ignored I/O standard assignment to node \"PS2_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_CLK2 " "Ignored I/O standard assignment to node \"PS2_CLK2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT " "Ignored I/O standard assignment to node \"PS2_DAT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_DAT2 " "Ignored I/O standard assignment to node \"PS2_DAT2\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[0\] " "Ignored I/O standard assignment to node \"SD_DAT\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[1\] " "Ignored I/O standard assignment to node \"SD_DAT\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[2\] " "Ignored I/O standard assignment to node \"SD_DAT\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT\[3\] " "Ignored I/O standard assignment to node \"SD_DAT\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKIN " "Ignored I/O standard assignment to node \"SMA_CLKIN\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SMA_CLKOUT " "Ignored I/O standard assignment to node \"SMA_CLKOUT\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[13\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[14\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[15\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[16\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[16\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[17\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[17\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[18\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[18\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[19\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[19\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"SRAM_ADDR\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_CE_N " "Ignored I/O standard assignment to node \"SRAM_CE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[10\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[11\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[12\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[13\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[14\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[15\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[8\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"SRAM_DQ\[9\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_LB_N " "Ignored I/O standard assignment to node \"SRAM_LB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_OE_N " "Ignored I/O standard assignment to node \"SRAM_OE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_UB_N " "Ignored I/O standard assignment to node \"SRAM_UB_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SRAM_WE_N " "Ignored I/O standard assignment to node \"SRAM_WE_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_CLK27 " "Ignored I/O standard assignment to node \"TD_CLK27\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[0\] " "Ignored I/O standard assignment to node \"TD_DATA\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[1\] " "Ignored I/O standard assignment to node \"TD_DATA\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[2\] " "Ignored I/O standard assignment to node \"TD_DATA\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[3\] " "Ignored I/O standard assignment to node \"TD_DATA\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[4\] " "Ignored I/O standard assignment to node \"TD_DATA\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[5\] " "Ignored I/O standard assignment to node \"TD_DATA\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[6\] " "Ignored I/O standard assignment to node \"TD_DATA\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_DATA\[7\] " "Ignored I/O standard assignment to node \"TD_DATA\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_HS " "Ignored I/O standard assignment to node \"TD_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_RESET_N " "Ignored I/O standard assignment to node \"TD_RESET_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "TD_VS " "Ignored I/O standard assignment to node \"TD_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_BLANK_N " "Ignored I/O standard assignment to node \"VGA_BLANK_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[0\] " "Ignored I/O standard assignment to node \"VGA_B\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[1\] " "Ignored I/O standard assignment to node \"VGA_B\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[2\] " "Ignored I/O standard assignment to node \"VGA_B\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[3\] " "Ignored I/O standard assignment to node \"VGA_B\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[4\] " "Ignored I/O standard assignment to node \"VGA_B\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[5\] " "Ignored I/O standard assignment to node \"VGA_B\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[6\] " "Ignored I/O standard assignment to node \"VGA_B\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_B\[7\] " "Ignored I/O standard assignment to node \"VGA_B\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_CLK " "Ignored I/O standard assignment to node \"VGA_CLK\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[0\] " "Ignored I/O standard assignment to node \"VGA_G\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[1\] " "Ignored I/O standard assignment to node \"VGA_G\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[2\] " "Ignored I/O standard assignment to node \"VGA_G\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[3\] " "Ignored I/O standard assignment to node \"VGA_G\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[4\] " "Ignored I/O standard assignment to node \"VGA_G\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[5\] " "Ignored I/O standard assignment to node \"VGA_G\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[6\] " "Ignored I/O standard assignment to node \"VGA_G\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_G\[7\] " "Ignored I/O standard assignment to node \"VGA_G\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_HS " "Ignored I/O standard assignment to node \"VGA_HS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[0\] " "Ignored I/O standard assignment to node \"VGA_R\[0\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[1\] " "Ignored I/O standard assignment to node \"VGA_R\[1\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[2\] " "Ignored I/O standard assignment to node \"VGA_R\[2\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[3\] " "Ignored I/O standard assignment to node \"VGA_R\[3\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[4\] " "Ignored I/O standard assignment to node \"VGA_R\[4\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[5\] " "Ignored I/O standard assignment to node \"VGA_R\[5\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[6\] " "Ignored I/O standard assignment to node \"VGA_R\[6\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_R\[7\] " "Ignored I/O standard assignment to node \"VGA_R\[7\]\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_SYNC_N " "Ignored I/O standard assignment to node \"VGA_SYNC_N\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "VGA_VS " "Ignored I/O standard assignment to node \"VGA_VS\"" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368883390 ""} } { } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1482368883390 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[0\] " "Node \"OTG_DACK_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DACK_N\[1\] " "Node \"OTG_DACK_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DACK_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[1\] " "Node \"OTG_DREQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_FSPEED " "Node \"OTG_FSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[0\] " "Node \"OTG_INT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT\[1\] " "Node \"OTG_INT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_INT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_LSPEED " "Node \"OTG_LSPEED\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1482368883435 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1482368883435 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368883485 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1482368892897 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368894400 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1482368894431 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1482368896380 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368896380 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1482368897502 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Router estimated average interconnect usage is 2% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X46_Y24 X57_Y36 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36" { } { { "loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36"} 46 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1482368903174 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1482368903174 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368904176 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1482368904176 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1482368904176 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1482368904176 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.84 " "Total time spent on timing analysis during the Fitter is 0.84 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1482368904345 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1482368904430 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1482368905498 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1482368905576 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1482368906647 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1482368907900 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1482368909597 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "9 Cyclone IV E " "9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[0\] 3.3-V LVTTL L3 " "Pin LCD_data\[0\] uses I/O standard 3.3-V LVTTL at L3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[0\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 352 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[1\] 3.3-V LVTTL L1 " "Pin LCD_data\[1\] uses I/O standard 3.3-V LVTTL at L1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[1\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 353 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[2\] 3.3-V LVTTL L2 " "Pin LCD_data\[2\] uses I/O standard 3.3-V LVTTL at L2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[2\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[3\] 3.3-V LVTTL K7 " "Pin LCD_data\[3\] uses I/O standard 3.3-V LVTTL at K7" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[3\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[4\] 3.3-V LVTTL K1 " "Pin LCD_data\[4\] uses I/O standard 3.3-V LVTTL at K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[4\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[5\] 3.3-V LVTTL K2 " "Pin LCD_data\[5\] uses I/O standard 3.3-V LVTTL at K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[5\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[6\] 3.3-V LVTTL M3 " "Pin LCD_data\[6\] uses I/O standard 3.3-V LVTTL at M3" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[6\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "LCD_data\[7\] 3.3-V LVTTL M5 " "Pin LCD_data\[7\] uses I/O standard 3.3-V LVTTL at M5" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LCD_data[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_data\[7\]" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LCD_data[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL Y2 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 5 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1482368909634 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1482368909634 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1482368910689 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 827 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 827 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1017 " "Peak virtual memory: 1017 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368913407 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:08:33 2016 " "Processing ended: Thu Dec 22 10:08:33 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368913407 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Elapsed time: 00:00:39" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368913407 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:38 " "Total CPU time (on all processors): 00:00:38" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368913407 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1482368913407 ""} diff --git a/db/lights.hier_info b/db/lights.hier_info index 120a90c..2695faa 100644 --- a/db/lights.hier_info +++ b/db/lights.hier_info @@ -1,68868 +1,68868 @@ -|lights -CLOCK_50 => nios_system:NiosII.clk_clk -KEY[0] => nios_system:NiosII.reset_reset_n -KEY[1] => nios_system:NiosII.push_switches_export[0] -KEY[2] => nios_system:NiosII.push_switches_export[1] -KEY[3] => nios_system:NiosII.push_switches_export[2] -SW[0] => nios_system:NiosII.switches_export[0] -SW[1] => nios_system:NiosII.switches_export[1] -SW[2] => nios_system:NiosII.switches_export[2] -SW[3] => nios_system:NiosII.switches_export[3] -SW[4] => nios_system:NiosII.switches_export[4] -SW[5] => nios_system:NiosII.switches_export[5] -SW[6] => nios_system:NiosII.switches_export[6] -SW[7] => nios_system:NiosII.switches_export[7] -SW[8] => nios_system:NiosII.switches_export[8] -SW[9] => nios_system:NiosII.switches_export[9] -SW[10] => nios_system:NiosII.switches_export[10] -SW[11] => nios_system:NiosII.switches_export[11] -SW[12] => nios_system:NiosII.switches_export[12] -SW[13] => nios_system:NiosII.switches_export[13] -SW[14] => nios_system:NiosII.switches_export[14] -SW[15] => nios_system:NiosII.switches_export[15] -SW[16] => nios_system:NiosII.switches_export[16] -SW[17] => nios_system:NiosII.switches_export[17] -LEDG[0] <= nios_system:NiosII.leds_export[0] -LEDG[1] <= nios_system:NiosII.leds_export[1] -LEDG[2] <= nios_system:NiosII.leds_export[2] -LEDG[3] <= nios_system:NiosII.leds_export[3] -LEDG[4] <= nios_system:NiosII.leds_export[4] -LEDG[5] <= nios_system:NiosII.leds_export[5] -LEDG[6] <= nios_system:NiosII.leds_export[6] -LEDG[7] <= nios_system:NiosII.leds_export[7] -LEDR[0] <= nios_system:NiosII.ledrs_export[0] -LEDR[1] <= nios_system:NiosII.ledrs_export[1] -LEDR[2] <= nios_system:NiosII.ledrs_export[2] -LEDR[3] <= nios_system:NiosII.ledrs_export[3] -LEDR[4] <= nios_system:NiosII.ledrs_export[4] -LEDR[5] <= nios_system:NiosII.ledrs_export[5] -LEDR[6] <= nios_system:NiosII.ledrs_export[6] -LEDR[7] <= nios_system:NiosII.ledrs_export[7] -LEDR[8] <= nios_system:NiosII.ledrs_export[8] -LEDR[9] <= nios_system:NiosII.ledrs_export[9] -LEDR[10] <= nios_system:NiosII.ledrs_export[10] -LEDR[11] <= nios_system:NiosII.ledrs_export[11] -LEDR[12] <= nios_system:NiosII.ledrs_export[12] -LEDR[13] <= nios_system:NiosII.ledrs_export[13] -LEDR[14] <= nios_system:NiosII.ledrs_export[14] -LEDR[15] <= nios_system:NiosII.ledrs_export[15] -LEDR[16] <= nios_system:NiosII.ledrs_export[16] -LEDR[17] <= nios_system:NiosII.ledrs_export[17] -HEX0[0] <= nios_system:NiosII.hex0_export[0] -HEX0[1] <= nios_system:NiosII.hex0_export[1] -HEX0[2] <= nios_system:NiosII.hex0_export[2] -HEX0[3] <= nios_system:NiosII.hex0_export[3] -HEX0[4] <= nios_system:NiosII.hex0_export[4] -HEX0[5] <= nios_system:NiosII.hex0_export[5] -HEX0[6] <= nios_system:NiosII.hex0_export[6] -HEX1[0] <= nios_system:NiosII.hex1_export[0] -HEX1[1] <= nios_system:NiosII.hex1_export[1] -HEX1[2] <= nios_system:NiosII.hex1_export[2] -HEX1[3] <= nios_system:NiosII.hex1_export[3] -HEX1[4] <= nios_system:NiosII.hex1_export[4] -HEX1[5] <= nios_system:NiosII.hex1_export[5] -HEX1[6] <= nios_system:NiosII.hex1_export[6] -HEX2[0] <= nios_system:NiosII.hex2_export[0] -HEX2[1] <= nios_system:NiosII.hex2_export[1] -HEX2[2] <= nios_system:NiosII.hex2_export[2] -HEX2[3] <= nios_system:NiosII.hex2_export[3] -HEX2[4] <= nios_system:NiosII.hex2_export[4] -HEX2[5] <= nios_system:NiosII.hex2_export[5] -HEX2[6] <= nios_system:NiosII.hex2_export[6] -HEX3[0] <= nios_system:NiosII.hex3_export[0] -HEX3[1] <= nios_system:NiosII.hex3_export[1] -HEX3[2] <= nios_system:NiosII.hex3_export[2] -HEX3[3] <= nios_system:NiosII.hex3_export[3] -HEX3[4] <= nios_system:NiosII.hex3_export[4] -HEX3[5] <= nios_system:NiosII.hex3_export[5] -HEX3[6] <= nios_system:NiosII.hex3_export[6] -HEX4[0] <= nios_system:NiosII.hex4_export[0] -HEX4[1] <= nios_system:NiosII.hex4_export[1] -HEX4[2] <= nios_system:NiosII.hex4_export[2] -HEX4[3] <= nios_system:NiosII.hex4_export[3] -HEX4[4] <= nios_system:NiosII.hex4_export[4] -HEX4[5] <= nios_system:NiosII.hex4_export[5] -HEX4[6] <= nios_system:NiosII.hex4_export[6] -HEX5[0] <= nios_system:NiosII.hex5_export[0] -HEX5[1] <= nios_system:NiosII.hex5_export[1] -HEX5[2] <= nios_system:NiosII.hex5_export[2] -HEX5[3] <= nios_system:NiosII.hex5_export[3] -HEX5[4] <= nios_system:NiosII.hex5_export[4] -HEX5[5] <= nios_system:NiosII.hex5_export[5] -HEX5[6] <= nios_system:NiosII.hex5_export[6] -HEX6[0] <= nios_system:NiosII.hex6_export[0] -HEX6[1] <= nios_system:NiosII.hex6_export[1] -HEX6[2] <= nios_system:NiosII.hex6_export[2] -HEX6[3] <= nios_system:NiosII.hex6_export[3] -HEX6[4] <= nios_system:NiosII.hex6_export[4] -HEX6[5] <= nios_system:NiosII.hex6_export[5] -HEX6[6] <= nios_system:NiosII.hex6_export[6] -HEX7[0] <= nios_system:NiosII.hex7_export[0] -HEX7[1] <= nios_system:NiosII.hex7_export[1] -HEX7[2] <= nios_system:NiosII.hex7_export[2] -HEX7[3] <= nios_system:NiosII.hex7_export[3] -HEX7[4] <= nios_system:NiosII.hex7_export[4] -HEX7[5] <= nios_system:NiosII.hex7_export[5] -HEX7[6] <= nios_system:NiosII.hex7_export[6] -LCD_RS <= nios_system:NiosII.lcd_16207_0_RS -LCD_RW <= nios_system:NiosII.lcd_16207_0_RW -LCD_data[0] <= nios_system:NiosII.lcd_16207_0_data[0] -LCD_data[1] <= nios_system:NiosII.lcd_16207_0_data[1] -LCD_data[2] <= nios_system:NiosII.lcd_16207_0_data[2] -LCD_data[3] <= nios_system:NiosII.lcd_16207_0_data[3] -LCD_data[4] <= nios_system:NiosII.lcd_16207_0_data[4] -LCD_data[5] <= nios_system:NiosII.lcd_16207_0_data[5] -LCD_data[6] <= nios_system:NiosII.lcd_16207_0_data[6] -LCD_data[7] <= nios_system:NiosII.lcd_16207_0_data[7] -LCD_EN <= nios_system:NiosII.lcd_16207_0_E -LCD_ON <= nios_system:NiosII.lcd_on_export -LCD_BLON <= nios_system:NiosII.lcd_blon_export - - -|lights|nios_system:NiosII -clk_clk => clk_clk.IN122 -leds_export[0] <= nios_system_LEDs:leds.out_port -leds_export[1] <= nios_system_LEDs:leds.out_port -leds_export[2] <= nios_system_LEDs:leds.out_port -leds_export[3] <= nios_system_LEDs:leds.out_port -leds_export[4] <= nios_system_LEDs:leds.out_port -leds_export[5] <= nios_system_LEDs:leds.out_port -leds_export[6] <= nios_system_LEDs:leds.out_port -leds_export[7] <= nios_system_LEDs:leds.out_port -reset_reset_n => _.IN1 -ledrs_export[0] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[1] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[2] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[3] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[4] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[5] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[6] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[7] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[8] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[9] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[10] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[11] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[12] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[13] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[14] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[15] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[16] <= nios_system_LEDRs:ledrs.out_port -ledrs_export[17] <= nios_system_LEDRs:ledrs.out_port -switches_export[0] => switches_export[0].IN1 -switches_export[1] => switches_export[1].IN1 -switches_export[2] => switches_export[2].IN1 -switches_export[3] => switches_export[3].IN1 -switches_export[4] => switches_export[4].IN1 -switches_export[5] => switches_export[5].IN1 -switches_export[6] => switches_export[6].IN1 -switches_export[7] => switches_export[7].IN1 -switches_export[8] => switches_export[8].IN1 -switches_export[9] => switches_export[9].IN1 -switches_export[10] => switches_export[10].IN1 -switches_export[11] => switches_export[11].IN1 -switches_export[12] => switches_export[12].IN1 -switches_export[13] => switches_export[13].IN1 -switches_export[14] => switches_export[14].IN1 -switches_export[15] => switches_export[15].IN1 -switches_export[16] => switches_export[16].IN1 -switches_export[17] => switches_export[17].IN1 -push_switches_export[0] => push_switches_export[0].IN1 -push_switches_export[1] => push_switches_export[1].IN1 -push_switches_export[2] => push_switches_export[2].IN1 -hex0_export[0] <= nios_system_hex0:hex0.out_port -hex0_export[1] <= nios_system_hex0:hex0.out_port -hex0_export[2] <= nios_system_hex0:hex0.out_port -hex0_export[3] <= nios_system_hex0:hex0.out_port -hex0_export[4] <= nios_system_hex0:hex0.out_port -hex0_export[5] <= nios_system_hex0:hex0.out_port -hex0_export[6] <= nios_system_hex0:hex0.out_port -hex1_export[0] <= nios_system_hex0:hex1.out_port -hex1_export[1] <= nios_system_hex0:hex1.out_port -hex1_export[2] <= nios_system_hex0:hex1.out_port -hex1_export[3] <= nios_system_hex0:hex1.out_port -hex1_export[4] <= nios_system_hex0:hex1.out_port -hex1_export[5] <= nios_system_hex0:hex1.out_port -hex1_export[6] <= nios_system_hex0:hex1.out_port -hex2_export[0] <= nios_system_hex0:hex2.out_port -hex2_export[1] <= nios_system_hex0:hex2.out_port -hex2_export[2] <= nios_system_hex0:hex2.out_port -hex2_export[3] <= nios_system_hex0:hex2.out_port -hex2_export[4] <= nios_system_hex0:hex2.out_port -hex2_export[5] <= nios_system_hex0:hex2.out_port -hex2_export[6] <= nios_system_hex0:hex2.out_port -hex3_export[0] <= nios_system_hex0:hex3.out_port -hex3_export[1] <= nios_system_hex0:hex3.out_port -hex3_export[2] <= nios_system_hex0:hex3.out_port -hex3_export[3] <= nios_system_hex0:hex3.out_port -hex3_export[4] <= nios_system_hex0:hex3.out_port -hex3_export[5] <= nios_system_hex0:hex3.out_port -hex3_export[6] <= nios_system_hex0:hex3.out_port -hex4_export[0] <= nios_system_hex0:hex4.out_port -hex4_export[1] <= nios_system_hex0:hex4.out_port -hex4_export[2] <= nios_system_hex0:hex4.out_port -hex4_export[3] <= nios_system_hex0:hex4.out_port -hex4_export[4] <= nios_system_hex0:hex4.out_port -hex4_export[5] <= nios_system_hex0:hex4.out_port -hex4_export[6] <= nios_system_hex0:hex4.out_port -hex5_export[0] <= nios_system_hex0:hex5.out_port -hex5_export[1] <= nios_system_hex0:hex5.out_port -hex5_export[2] <= nios_system_hex0:hex5.out_port -hex5_export[3] <= nios_system_hex0:hex5.out_port -hex5_export[4] <= nios_system_hex0:hex5.out_port -hex5_export[5] <= nios_system_hex0:hex5.out_port -hex5_export[6] <= nios_system_hex0:hex5.out_port -hex6_export[0] <= nios_system_hex0:hex6.out_port -hex6_export[1] <= nios_system_hex0:hex6.out_port -hex6_export[2] <= nios_system_hex0:hex6.out_port -hex6_export[3] <= nios_system_hex0:hex6.out_port -hex6_export[4] <= nios_system_hex0:hex6.out_port -hex6_export[5] <= nios_system_hex0:hex6.out_port -hex6_export[6] <= nios_system_hex0:hex6.out_port -hex7_export[0] <= nios_system_hex0:hex7.out_port -hex7_export[1] <= nios_system_hex0:hex7.out_port -hex7_export[2] <= nios_system_hex0:hex7.out_port -hex7_export[3] <= nios_system_hex0:hex7.out_port -hex7_export[4] <= nios_system_hex0:hex7.out_port -hex7_export[5] <= nios_system_hex0:hex7.out_port -hex7_export[6] <= nios_system_hex0:hex7.out_port -lcd_16207_0_RS <= nios_system_lcd_16207_0:lcd_16207_0.LCD_RS -lcd_16207_0_RW <= nios_system_lcd_16207_0:lcd_16207_0.LCD_RW -lcd_16207_0_data[0] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[1] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[2] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[3] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[4] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[5] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[6] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_data[7] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data -lcd_16207_0_E <= nios_system_lcd_16207_0:lcd_16207_0.LCD_E -lcd_on_export <= nios_system_lcd_on:lcd_on.out_port -lcd_blon_export <= nios_system_lcd_on:lcd_blon.out_port - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor -clk => clk.IN4 -d_irq[0] => ~NO_FANOUT~ -d_irq[1] => ~NO_FANOUT~ -d_irq[2] => ~NO_FANOUT~ -d_irq[3] => ~NO_FANOUT~ -d_irq[4] => ~NO_FANOUT~ -d_irq[5] => W_ipending_reg_nxt.IN1 -d_irq[6] => ~NO_FANOUT~ -d_irq[7] => ~NO_FANOUT~ -d_irq[8] => ~NO_FANOUT~ -d_irq[9] => ~NO_FANOUT~ -d_irq[10] => ~NO_FANOUT~ -d_irq[11] => ~NO_FANOUT~ -d_irq[12] => ~NO_FANOUT~ -d_irq[13] => ~NO_FANOUT~ -d_irq[14] => ~NO_FANOUT~ -d_irq[15] => ~NO_FANOUT~ -d_irq[16] => ~NO_FANOUT~ -d_irq[17] => ~NO_FANOUT~ -d_irq[18] => ~NO_FANOUT~ -d_irq[19] => ~NO_FANOUT~ -d_irq[20] => ~NO_FANOUT~ -d_irq[21] => ~NO_FANOUT~ -d_irq[22] => ~NO_FANOUT~ -d_irq[23] => ~NO_FANOUT~ -d_irq[24] => ~NO_FANOUT~ -d_irq[25] => ~NO_FANOUT~ -d_irq[26] => ~NO_FANOUT~ -d_irq[27] => ~NO_FANOUT~ -d_irq[28] => ~NO_FANOUT~ -d_irq[29] => ~NO_FANOUT~ -d_irq[30] => ~NO_FANOUT~ -d_irq[31] => ~NO_FANOUT~ -d_readdata[0] => av_ld_byte0_data_nxt.DATAA -d_readdata[1] => av_ld_byte0_data_nxt.DATAA -d_readdata[2] => av_ld_byte0_data_nxt.DATAA -d_readdata[3] => av_ld_byte0_data_nxt.DATAA -d_readdata[4] => av_ld_byte0_data_nxt.DATAA -d_readdata[5] => av_ld_byte0_data_nxt.DATAA -d_readdata[6] => av_ld_byte0_data_nxt.DATAA -d_readdata[7] => av_ld_byte0_data_nxt.DATAA -d_readdata[8] => av_ld_byte1_data_nxt.DATAA -d_readdata[9] => av_ld_byte1_data_nxt.DATAA -d_readdata[10] => av_ld_byte1_data_nxt.DATAA -d_readdata[11] => av_ld_byte1_data_nxt.DATAA -d_readdata[12] => av_ld_byte1_data_nxt.DATAA -d_readdata[13] => av_ld_byte1_data_nxt.DATAA -d_readdata[14] => av_ld_byte1_data_nxt.DATAA -d_readdata[15] => av_ld_byte1_data_nxt.DATAA -d_readdata[16] => av_ld_byte2_data_nxt.DATAA -d_readdata[17] => av_ld_byte2_data_nxt.DATAA -d_readdata[18] => av_ld_byte2_data_nxt.DATAA -d_readdata[19] => av_ld_byte2_data_nxt.DATAA -d_readdata[20] => av_ld_byte2_data_nxt.DATAA -d_readdata[21] => av_ld_byte2_data_nxt.DATAA -d_readdata[22] => av_ld_byte2_data_nxt.DATAA -d_readdata[23] => av_ld_byte2_data_nxt.DATAA -d_readdata[24] => av_ld_byte3_data_nxt.DATAA -d_readdata[25] => av_ld_byte3_data_nxt.DATAA -d_readdata[26] => av_ld_byte3_data_nxt.DATAA -d_readdata[27] => av_ld_byte3_data_nxt.DATAA -d_readdata[28] => av_ld_byte3_data_nxt.DATAA -d_readdata[29] => av_ld_byte3_data_nxt.DATAA -d_readdata[30] => av_ld_byte3_data_nxt.DATAA -d_readdata[31] => av_ld_byte3_data_nxt.DATAA -d_waitrequest => d_waitrequest.IN1 -i_readdata[0] => i_readdata[0].IN1 -i_readdata[1] => i_readdata[1].IN1 -i_readdata[2] => i_readdata[2].IN1 -i_readdata[3] => i_readdata[3].IN1 -i_readdata[4] => i_readdata[4].IN1 -i_readdata[5] => i_readdata[5].IN1 -i_readdata[6] => i_readdata[6].IN1 -i_readdata[7] => i_readdata[7].IN1 -i_readdata[8] => i_readdata[8].IN1 -i_readdata[9] => i_readdata[9].IN1 -i_readdata[10] => i_readdata[10].IN1 -i_readdata[11] => i_readdata[11].IN1 -i_readdata[12] => i_readdata[12].IN1 -i_readdata[13] => i_readdata[13].IN1 -i_readdata[14] => i_readdata[14].IN1 -i_readdata[15] => i_readdata[15].IN1 -i_readdata[16] => i_readdata[16].IN1 -i_readdata[17] => i_readdata[17].IN1 -i_readdata[18] => i_readdata[18].IN1 -i_readdata[19] => i_readdata[19].IN1 -i_readdata[20] => i_readdata[20].IN1 -i_readdata[21] => i_readdata[21].IN1 -i_readdata[22] => i_readdata[22].IN1 -i_readdata[23] => i_readdata[23].IN1 -i_readdata[24] => i_readdata[24].IN1 -i_readdata[25] => i_readdata[25].IN1 -i_readdata[26] => i_readdata[26].IN1 -i_readdata[27] => i_readdata[27].IN1 -i_readdata[28] => i_readdata[28].IN1 -i_readdata[29] => i_readdata[29].IN1 -i_readdata[30] => i_readdata[30].IN1 -i_readdata[31] => i_readdata[31].IN1 -i_waitrequest => i_waitrequest.IN1 -jtag_debug_module_address[0] => jtag_debug_module_address[0].IN1 -jtag_debug_module_address[1] => jtag_debug_module_address[1].IN1 -jtag_debug_module_address[2] => jtag_debug_module_address[2].IN1 -jtag_debug_module_address[3] => jtag_debug_module_address[3].IN1 -jtag_debug_module_address[4] => jtag_debug_module_address[4].IN1 -jtag_debug_module_address[5] => jtag_debug_module_address[5].IN1 -jtag_debug_module_address[6] => jtag_debug_module_address[6].IN1 -jtag_debug_module_address[7] => jtag_debug_module_address[7].IN1 -jtag_debug_module_address[8] => jtag_debug_module_address[8].IN1 -jtag_debug_module_byteenable[0] => jtag_debug_module_byteenable[0].IN1 -jtag_debug_module_byteenable[1] => jtag_debug_module_byteenable[1].IN1 -jtag_debug_module_byteenable[2] => jtag_debug_module_byteenable[2].IN1 -jtag_debug_module_byteenable[3] => jtag_debug_module_byteenable[3].IN1 -jtag_debug_module_debugaccess => jtag_debug_module_debugaccess.IN1 -jtag_debug_module_read => jtag_debug_module_read.IN1 -jtag_debug_module_write => jtag_debug_module_write.IN1 -jtag_debug_module_writedata[0] => jtag_debug_module_writedata[0].IN1 -jtag_debug_module_writedata[1] => jtag_debug_module_writedata[1].IN1 -jtag_debug_module_writedata[2] => jtag_debug_module_writedata[2].IN1 -jtag_debug_module_writedata[3] => jtag_debug_module_writedata[3].IN1 -jtag_debug_module_writedata[4] => jtag_debug_module_writedata[4].IN1 -jtag_debug_module_writedata[5] => jtag_debug_module_writedata[5].IN1 -jtag_debug_module_writedata[6] => jtag_debug_module_writedata[6].IN1 -jtag_debug_module_writedata[7] => jtag_debug_module_writedata[7].IN1 -jtag_debug_module_writedata[8] => jtag_debug_module_writedata[8].IN1 -jtag_debug_module_writedata[9] => jtag_debug_module_writedata[9].IN1 -jtag_debug_module_writedata[10] => jtag_debug_module_writedata[10].IN1 -jtag_debug_module_writedata[11] => jtag_debug_module_writedata[11].IN1 -jtag_debug_module_writedata[12] => jtag_debug_module_writedata[12].IN1 -jtag_debug_module_writedata[13] => jtag_debug_module_writedata[13].IN1 -jtag_debug_module_writedata[14] => jtag_debug_module_writedata[14].IN1 -jtag_debug_module_writedata[15] => jtag_debug_module_writedata[15].IN1 -jtag_debug_module_writedata[16] => jtag_debug_module_writedata[16].IN1 -jtag_debug_module_writedata[17] => jtag_debug_module_writedata[17].IN1 -jtag_debug_module_writedata[18] => jtag_debug_module_writedata[18].IN1 -jtag_debug_module_writedata[19] => jtag_debug_module_writedata[19].IN1 -jtag_debug_module_writedata[20] => jtag_debug_module_writedata[20].IN1 -jtag_debug_module_writedata[21] => jtag_debug_module_writedata[21].IN1 -jtag_debug_module_writedata[22] => jtag_debug_module_writedata[22].IN1 -jtag_debug_module_writedata[23] => jtag_debug_module_writedata[23].IN1 -jtag_debug_module_writedata[24] => jtag_debug_module_writedata[24].IN1 -jtag_debug_module_writedata[25] => jtag_debug_module_writedata[25].IN1 -jtag_debug_module_writedata[26] => jtag_debug_module_writedata[26].IN1 -jtag_debug_module_writedata[27] => jtag_debug_module_writedata[27].IN1 -jtag_debug_module_writedata[28] => jtag_debug_module_writedata[28].IN1 -jtag_debug_module_writedata[29] => jtag_debug_module_writedata[29].IN1 -jtag_debug_module_writedata[30] => jtag_debug_module_writedata[30].IN1 -jtag_debug_module_writedata[31] => jtag_debug_module_writedata[31].IN1 -reset_n => reset_n.IN2 -d_address[0] <= d_address[0].DB_MAX_OUTPUT_PORT_TYPE -d_address[1] <= d_address[1].DB_MAX_OUTPUT_PORT_TYPE -d_address[2] <= d_address[2].DB_MAX_OUTPUT_PORT_TYPE -d_address[3] <= d_address[3].DB_MAX_OUTPUT_PORT_TYPE -d_address[4] <= d_address[4].DB_MAX_OUTPUT_PORT_TYPE -d_address[5] <= d_address[5].DB_MAX_OUTPUT_PORT_TYPE -d_address[6] <= d_address[6].DB_MAX_OUTPUT_PORT_TYPE -d_address[7] <= d_address[7].DB_MAX_OUTPUT_PORT_TYPE -d_address[8] <= d_address[8].DB_MAX_OUTPUT_PORT_TYPE -d_address[9] <= d_address[9].DB_MAX_OUTPUT_PORT_TYPE -d_address[10] <= d_address[10].DB_MAX_OUTPUT_PORT_TYPE -d_address[11] <= d_address[11].DB_MAX_OUTPUT_PORT_TYPE -d_address[12] <= d_address[12].DB_MAX_OUTPUT_PORT_TYPE -d_address[13] <= d_address[13].DB_MAX_OUTPUT_PORT_TYPE -d_address[14] <= d_address[14].DB_MAX_OUTPUT_PORT_TYPE -d_address[15] <= d_address[15].DB_MAX_OUTPUT_PORT_TYPE -d_address[16] <= d_address[16].DB_MAX_OUTPUT_PORT_TYPE -d_address[17] <= d_address[17].DB_MAX_OUTPUT_PORT_TYPE -d_address[18] <= d_address[18].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[0] <= d_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[1] <= d_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[2] <= d_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -d_byteenable[3] <= d_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -d_read <= d_read.DB_MAX_OUTPUT_PORT_TYPE -d_write <= d_write.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[0] <= d_writedata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[1] <= d_writedata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[2] <= d_writedata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[3] <= d_writedata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[4] <= d_writedata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[5] <= d_writedata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[6] <= d_writedata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[7] <= d_writedata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[8] <= d_writedata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[9] <= d_writedata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[10] <= d_writedata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[11] <= d_writedata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[12] <= d_writedata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[13] <= d_writedata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[14] <= d_writedata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[15] <= d_writedata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[16] <= d_writedata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[17] <= d_writedata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[18] <= d_writedata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[19] <= d_writedata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[20] <= d_writedata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[21] <= d_writedata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[22] <= d_writedata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[23] <= d_writedata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[24] <= d_writedata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[25] <= d_writedata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[26] <= d_writedata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[27] <= d_writedata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[28] <= d_writedata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[29] <= d_writedata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[30] <= d_writedata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -d_writedata[31] <= d_writedata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -i_address[0] <= i_address[0].DB_MAX_OUTPUT_PORT_TYPE -i_address[1] <= i_address[1].DB_MAX_OUTPUT_PORT_TYPE -i_address[2] <= i_address[2].DB_MAX_OUTPUT_PORT_TYPE -i_address[3] <= i_address[3].DB_MAX_OUTPUT_PORT_TYPE -i_address[4] <= i_address[4].DB_MAX_OUTPUT_PORT_TYPE -i_address[5] <= i_address[5].DB_MAX_OUTPUT_PORT_TYPE -i_address[6] <= i_address[6].DB_MAX_OUTPUT_PORT_TYPE -i_address[7] <= i_address[7].DB_MAX_OUTPUT_PORT_TYPE -i_address[8] <= i_address[8].DB_MAX_OUTPUT_PORT_TYPE -i_address[9] <= i_address[9].DB_MAX_OUTPUT_PORT_TYPE -i_address[10] <= i_address[10].DB_MAX_OUTPUT_PORT_TYPE -i_address[11] <= i_address[11].DB_MAX_OUTPUT_PORT_TYPE -i_address[12] <= i_address[12].DB_MAX_OUTPUT_PORT_TYPE -i_address[13] <= i_address[13].DB_MAX_OUTPUT_PORT_TYPE -i_address[14] <= i_address[14].DB_MAX_OUTPUT_PORT_TYPE -i_address[15] <= i_address[15].DB_MAX_OUTPUT_PORT_TYPE -i_address[16] <= i_address[16].DB_MAX_OUTPUT_PORT_TYPE -i_address[17] <= i_address[17].DB_MAX_OUTPUT_PORT_TYPE -i_address[18] <= i_address[18].DB_MAX_OUTPUT_PORT_TYPE -i_read <= i_read.DB_MAX_OUTPUT_PORT_TYPE -jtag_debug_module_debugaccess_to_roms <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.jtag_debug_module_debugaccess_to_roms -jtag_debug_module_readdata[0] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[1] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[2] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[3] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[4] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[5] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[6] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[7] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[8] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[9] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[10] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[11] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[12] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[13] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[14] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[15] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[16] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[17] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[18] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[19] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[20] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[21] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[22] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[23] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[24] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[25] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[26] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[27] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[28] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[29] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[30] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_readdata[31] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata -jtag_debug_module_resetrequest <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.resetrequest -jtag_debug_module_waitrequest <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.waitrequest -no_ci_readra <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench -D_iw[0] => ~NO_FANOUT~ -D_iw[1] => ~NO_FANOUT~ -D_iw[2] => ~NO_FANOUT~ -D_iw[3] => ~NO_FANOUT~ -D_iw[4] => ~NO_FANOUT~ -D_iw[5] => ~NO_FANOUT~ -D_iw[6] => ~NO_FANOUT~ -D_iw[7] => ~NO_FANOUT~ -D_iw[8] => ~NO_FANOUT~ -D_iw[9] => ~NO_FANOUT~ -D_iw[10] => ~NO_FANOUT~ -D_iw[11] => ~NO_FANOUT~ -D_iw[12] => ~NO_FANOUT~ -D_iw[13] => ~NO_FANOUT~ -D_iw[14] => ~NO_FANOUT~ -D_iw[15] => ~NO_FANOUT~ -D_iw[16] => ~NO_FANOUT~ -D_iw[17] => ~NO_FANOUT~ -D_iw[18] => ~NO_FANOUT~ -D_iw[19] => ~NO_FANOUT~ -D_iw[20] => ~NO_FANOUT~ -D_iw[21] => ~NO_FANOUT~ -D_iw[22] => ~NO_FANOUT~ -D_iw[23] => ~NO_FANOUT~ -D_iw[24] => ~NO_FANOUT~ -D_iw[25] => ~NO_FANOUT~ -D_iw[26] => ~NO_FANOUT~ -D_iw[27] => ~NO_FANOUT~ -D_iw[28] => ~NO_FANOUT~ -D_iw[29] => ~NO_FANOUT~ -D_iw[30] => ~NO_FANOUT~ -D_iw[31] => ~NO_FANOUT~ -D_iw_op[0] => ~NO_FANOUT~ -D_iw_op[1] => ~NO_FANOUT~ -D_iw_op[2] => ~NO_FANOUT~ -D_iw_op[3] => ~NO_FANOUT~ -D_iw_op[4] => ~NO_FANOUT~ -D_iw_op[5] => ~NO_FANOUT~ -D_iw_opx[0] => ~NO_FANOUT~ -D_iw_opx[1] => ~NO_FANOUT~ -D_iw_opx[2] => ~NO_FANOUT~ -D_iw_opx[3] => ~NO_FANOUT~ -D_iw_opx[4] => ~NO_FANOUT~ -D_iw_opx[5] => ~NO_FANOUT~ -D_valid => ~NO_FANOUT~ -E_valid => ~NO_FANOUT~ -F_pcb[0] => ~NO_FANOUT~ -F_pcb[1] => ~NO_FANOUT~ -F_pcb[2] => ~NO_FANOUT~ -F_pcb[3] => ~NO_FANOUT~ -F_pcb[4] => ~NO_FANOUT~ -F_pcb[5] => ~NO_FANOUT~ -F_pcb[6] => ~NO_FANOUT~ -F_pcb[7] => ~NO_FANOUT~ -F_pcb[8] => ~NO_FANOUT~ -F_pcb[9] => ~NO_FANOUT~ -F_pcb[10] => ~NO_FANOUT~ -F_pcb[11] => ~NO_FANOUT~ -F_pcb[12] => ~NO_FANOUT~ -F_pcb[13] => ~NO_FANOUT~ -F_pcb[14] => ~NO_FANOUT~ -F_pcb[15] => ~NO_FANOUT~ -F_pcb[16] => ~NO_FANOUT~ -F_pcb[17] => ~NO_FANOUT~ -F_pcb[18] => ~NO_FANOUT~ -F_valid => ~NO_FANOUT~ -R_ctrl_ld => ~NO_FANOUT~ -R_ctrl_ld_non_io => ~NO_FANOUT~ -R_dst_regnum[0] => ~NO_FANOUT~ -R_dst_regnum[1] => ~NO_FANOUT~ -R_dst_regnum[2] => ~NO_FANOUT~ -R_dst_regnum[3] => ~NO_FANOUT~ -R_dst_regnum[4] => ~NO_FANOUT~ -R_wr_dst_reg => ~NO_FANOUT~ -W_valid => ~NO_FANOUT~ -W_vinst[0] => ~NO_FANOUT~ -W_vinst[1] => ~NO_FANOUT~ -W_vinst[2] => ~NO_FANOUT~ -W_vinst[3] => ~NO_FANOUT~ -W_vinst[4] => ~NO_FANOUT~ -W_vinst[5] => ~NO_FANOUT~ -W_vinst[6] => ~NO_FANOUT~ -W_vinst[7] => ~NO_FANOUT~ -W_vinst[8] => ~NO_FANOUT~ -W_vinst[9] => ~NO_FANOUT~ -W_vinst[10] => ~NO_FANOUT~ -W_vinst[11] => ~NO_FANOUT~ -W_vinst[12] => ~NO_FANOUT~ -W_vinst[13] => ~NO_FANOUT~ -W_vinst[14] => ~NO_FANOUT~ -W_vinst[15] => ~NO_FANOUT~ -W_vinst[16] => ~NO_FANOUT~ -W_vinst[17] => ~NO_FANOUT~ -W_vinst[18] => ~NO_FANOUT~ -W_vinst[19] => ~NO_FANOUT~ -W_vinst[20] => ~NO_FANOUT~ -W_vinst[21] => ~NO_FANOUT~ -W_vinst[22] => ~NO_FANOUT~ -W_vinst[23] => ~NO_FANOUT~ -W_vinst[24] => ~NO_FANOUT~ -W_vinst[25] => ~NO_FANOUT~ -W_vinst[26] => ~NO_FANOUT~ -W_vinst[27] => ~NO_FANOUT~ -W_vinst[28] => ~NO_FANOUT~ -W_vinst[29] => ~NO_FANOUT~ -W_vinst[30] => ~NO_FANOUT~ -W_vinst[31] => ~NO_FANOUT~ -W_vinst[32] => ~NO_FANOUT~ -W_vinst[33] => ~NO_FANOUT~ -W_vinst[34] => ~NO_FANOUT~ -W_vinst[35] => ~NO_FANOUT~ -W_vinst[36] => ~NO_FANOUT~ -W_vinst[37] => ~NO_FANOUT~ -W_vinst[38] => ~NO_FANOUT~ -W_vinst[39] => ~NO_FANOUT~ -W_vinst[40] => ~NO_FANOUT~ -W_vinst[41] => ~NO_FANOUT~ -W_vinst[42] => ~NO_FANOUT~ -W_vinst[43] => ~NO_FANOUT~ -W_vinst[44] => ~NO_FANOUT~ -W_vinst[45] => ~NO_FANOUT~ -W_vinst[46] => ~NO_FANOUT~ -W_vinst[47] => ~NO_FANOUT~ -W_vinst[48] => ~NO_FANOUT~ -W_vinst[49] => ~NO_FANOUT~ -W_vinst[50] => ~NO_FANOUT~ -W_vinst[51] => ~NO_FANOUT~ -W_vinst[52] => ~NO_FANOUT~ -W_vinst[53] => ~NO_FANOUT~ -W_vinst[54] => ~NO_FANOUT~ -W_vinst[55] => ~NO_FANOUT~ -W_wr_data[0] => ~NO_FANOUT~ -W_wr_data[1] => ~NO_FANOUT~ -W_wr_data[2] => ~NO_FANOUT~ -W_wr_data[3] => ~NO_FANOUT~ -W_wr_data[4] => ~NO_FANOUT~ -W_wr_data[5] => ~NO_FANOUT~ -W_wr_data[6] => ~NO_FANOUT~ -W_wr_data[7] => ~NO_FANOUT~ -W_wr_data[8] => ~NO_FANOUT~ -W_wr_data[9] => ~NO_FANOUT~ -W_wr_data[10] => ~NO_FANOUT~ -W_wr_data[11] => ~NO_FANOUT~ -W_wr_data[12] => ~NO_FANOUT~ -W_wr_data[13] => ~NO_FANOUT~ -W_wr_data[14] => ~NO_FANOUT~ -W_wr_data[15] => ~NO_FANOUT~ -W_wr_data[16] => ~NO_FANOUT~ -W_wr_data[17] => ~NO_FANOUT~ -W_wr_data[18] => ~NO_FANOUT~ -W_wr_data[19] => ~NO_FANOUT~ -W_wr_data[20] => ~NO_FANOUT~ -W_wr_data[21] => ~NO_FANOUT~ -W_wr_data[22] => ~NO_FANOUT~ -W_wr_data[23] => ~NO_FANOUT~ -W_wr_data[24] => ~NO_FANOUT~ -W_wr_data[25] => ~NO_FANOUT~ -W_wr_data[26] => ~NO_FANOUT~ -W_wr_data[27] => ~NO_FANOUT~ -W_wr_data[28] => ~NO_FANOUT~ -W_wr_data[29] => ~NO_FANOUT~ -W_wr_data[30] => ~NO_FANOUT~ -W_wr_data[31] => ~NO_FANOUT~ -av_ld_data_aligned_unfiltered[0] => av_ld_data_aligned_filtered[0].DATAIN -av_ld_data_aligned_unfiltered[1] => av_ld_data_aligned_filtered[1].DATAIN -av_ld_data_aligned_unfiltered[2] => av_ld_data_aligned_filtered[2].DATAIN -av_ld_data_aligned_unfiltered[3] => av_ld_data_aligned_filtered[3].DATAIN -av_ld_data_aligned_unfiltered[4] => av_ld_data_aligned_filtered[4].DATAIN -av_ld_data_aligned_unfiltered[5] => av_ld_data_aligned_filtered[5].DATAIN -av_ld_data_aligned_unfiltered[6] => av_ld_data_aligned_filtered[6].DATAIN -av_ld_data_aligned_unfiltered[7] => av_ld_data_aligned_filtered[7].DATAIN -av_ld_data_aligned_unfiltered[8] => av_ld_data_aligned_filtered[8].DATAIN -av_ld_data_aligned_unfiltered[9] => av_ld_data_aligned_filtered[9].DATAIN -av_ld_data_aligned_unfiltered[10] => av_ld_data_aligned_filtered[10].DATAIN -av_ld_data_aligned_unfiltered[11] => av_ld_data_aligned_filtered[11].DATAIN -av_ld_data_aligned_unfiltered[12] => av_ld_data_aligned_filtered[12].DATAIN -av_ld_data_aligned_unfiltered[13] => av_ld_data_aligned_filtered[13].DATAIN -av_ld_data_aligned_unfiltered[14] => av_ld_data_aligned_filtered[14].DATAIN -av_ld_data_aligned_unfiltered[15] => av_ld_data_aligned_filtered[15].DATAIN -av_ld_data_aligned_unfiltered[16] => av_ld_data_aligned_filtered[16].DATAIN -av_ld_data_aligned_unfiltered[17] => av_ld_data_aligned_filtered[17].DATAIN -av_ld_data_aligned_unfiltered[18] => av_ld_data_aligned_filtered[18].DATAIN -av_ld_data_aligned_unfiltered[19] => av_ld_data_aligned_filtered[19].DATAIN -av_ld_data_aligned_unfiltered[20] => av_ld_data_aligned_filtered[20].DATAIN -av_ld_data_aligned_unfiltered[21] => av_ld_data_aligned_filtered[21].DATAIN -av_ld_data_aligned_unfiltered[22] => av_ld_data_aligned_filtered[22].DATAIN -av_ld_data_aligned_unfiltered[23] => av_ld_data_aligned_filtered[23].DATAIN -av_ld_data_aligned_unfiltered[24] => av_ld_data_aligned_filtered[24].DATAIN -av_ld_data_aligned_unfiltered[25] => av_ld_data_aligned_filtered[25].DATAIN -av_ld_data_aligned_unfiltered[26] => av_ld_data_aligned_filtered[26].DATAIN -av_ld_data_aligned_unfiltered[27] => av_ld_data_aligned_filtered[27].DATAIN -av_ld_data_aligned_unfiltered[28] => av_ld_data_aligned_filtered[28].DATAIN -av_ld_data_aligned_unfiltered[29] => av_ld_data_aligned_filtered[29].DATAIN -av_ld_data_aligned_unfiltered[30] => av_ld_data_aligned_filtered[30].DATAIN -av_ld_data_aligned_unfiltered[31] => av_ld_data_aligned_filtered[31].DATAIN -clk => d_write~reg0.CLK -d_address[0] => ~NO_FANOUT~ -d_address[1] => ~NO_FANOUT~ -d_address[2] => ~NO_FANOUT~ -d_address[3] => ~NO_FANOUT~ -d_address[4] => ~NO_FANOUT~ -d_address[5] => ~NO_FANOUT~ -d_address[6] => ~NO_FANOUT~ -d_address[7] => ~NO_FANOUT~ -d_address[8] => ~NO_FANOUT~ -d_address[9] => ~NO_FANOUT~ -d_address[10] => ~NO_FANOUT~ -d_address[11] => ~NO_FANOUT~ -d_address[12] => ~NO_FANOUT~ -d_address[13] => ~NO_FANOUT~ -d_address[14] => ~NO_FANOUT~ -d_address[15] => ~NO_FANOUT~ -d_address[16] => ~NO_FANOUT~ -d_address[17] => ~NO_FANOUT~ -d_address[18] => ~NO_FANOUT~ -d_byteenable[0] => ~NO_FANOUT~ -d_byteenable[1] => ~NO_FANOUT~ -d_byteenable[2] => ~NO_FANOUT~ -d_byteenable[3] => ~NO_FANOUT~ -d_read => ~NO_FANOUT~ -d_write_nxt => d_write~reg0.DATAIN -i_address[0] => ~NO_FANOUT~ -i_address[1] => ~NO_FANOUT~ -i_address[2] => ~NO_FANOUT~ -i_address[3] => ~NO_FANOUT~ -i_address[4] => ~NO_FANOUT~ -i_address[5] => ~NO_FANOUT~ -i_address[6] => ~NO_FANOUT~ -i_address[7] => ~NO_FANOUT~ -i_address[8] => ~NO_FANOUT~ -i_address[9] => ~NO_FANOUT~ -i_address[10] => ~NO_FANOUT~ -i_address[11] => ~NO_FANOUT~ -i_address[12] => ~NO_FANOUT~ -i_address[13] => ~NO_FANOUT~ -i_address[14] => ~NO_FANOUT~ -i_address[15] => ~NO_FANOUT~ -i_address[16] => ~NO_FANOUT~ -i_address[17] => ~NO_FANOUT~ -i_address[18] => ~NO_FANOUT~ -i_read => ~NO_FANOUT~ -i_readdata[0] => ~NO_FANOUT~ -i_readdata[1] => ~NO_FANOUT~ -i_readdata[2] => ~NO_FANOUT~ -i_readdata[3] => ~NO_FANOUT~ -i_readdata[4] => ~NO_FANOUT~ -i_readdata[5] => ~NO_FANOUT~ -i_readdata[6] => ~NO_FANOUT~ -i_readdata[7] => ~NO_FANOUT~ -i_readdata[8] => ~NO_FANOUT~ -i_readdata[9] => ~NO_FANOUT~ -i_readdata[10] => ~NO_FANOUT~ -i_readdata[11] => ~NO_FANOUT~ -i_readdata[12] => ~NO_FANOUT~ -i_readdata[13] => ~NO_FANOUT~ -i_readdata[14] => ~NO_FANOUT~ -i_readdata[15] => ~NO_FANOUT~ -i_readdata[16] => ~NO_FANOUT~ -i_readdata[17] => ~NO_FANOUT~ -i_readdata[18] => ~NO_FANOUT~ -i_readdata[19] => ~NO_FANOUT~ -i_readdata[20] => ~NO_FANOUT~ -i_readdata[21] => ~NO_FANOUT~ -i_readdata[22] => ~NO_FANOUT~ -i_readdata[23] => ~NO_FANOUT~ -i_readdata[24] => ~NO_FANOUT~ -i_readdata[25] => ~NO_FANOUT~ -i_readdata[26] => ~NO_FANOUT~ -i_readdata[27] => ~NO_FANOUT~ -i_readdata[28] => ~NO_FANOUT~ -i_readdata[29] => ~NO_FANOUT~ -i_readdata[30] => ~NO_FANOUT~ -i_readdata[31] => ~NO_FANOUT~ -i_waitrequest => ~NO_FANOUT~ -reset_n => d_write~reg0.ACLR -av_ld_data_aligned_filtered[0] <= av_ld_data_aligned_unfiltered[0].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[1] <= av_ld_data_aligned_unfiltered[1].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[2] <= av_ld_data_aligned_unfiltered[2].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[3] <= av_ld_data_aligned_unfiltered[3].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[4] <= av_ld_data_aligned_unfiltered[4].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[5] <= av_ld_data_aligned_unfiltered[5].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[6] <= av_ld_data_aligned_unfiltered[6].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[7] <= av_ld_data_aligned_unfiltered[7].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[8] <= av_ld_data_aligned_unfiltered[8].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[9] <= av_ld_data_aligned_unfiltered[9].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[10] <= av_ld_data_aligned_unfiltered[10].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[11] <= av_ld_data_aligned_unfiltered[11].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[12] <= av_ld_data_aligned_unfiltered[12].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[13] <= av_ld_data_aligned_unfiltered[13].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[14] <= av_ld_data_aligned_unfiltered[14].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[15] <= av_ld_data_aligned_unfiltered[15].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[16] <= av_ld_data_aligned_unfiltered[16].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[17] <= av_ld_data_aligned_unfiltered[17].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[18] <= av_ld_data_aligned_unfiltered[18].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[19] <= av_ld_data_aligned_unfiltered[19].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[20] <= av_ld_data_aligned_unfiltered[20].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[21] <= av_ld_data_aligned_unfiltered[21].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[22] <= av_ld_data_aligned_unfiltered[22].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[23] <= av_ld_data_aligned_unfiltered[23].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[24] <= av_ld_data_aligned_unfiltered[24].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[25] <= av_ld_data_aligned_unfiltered[25].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[26] <= av_ld_data_aligned_unfiltered[26].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[27] <= av_ld_data_aligned_unfiltered[27].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[28] <= av_ld_data_aligned_unfiltered[28].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[29] <= av_ld_data_aligned_unfiltered[29].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[30] <= av_ld_data_aligned_unfiltered[30].DB_MAX_OUTPUT_PORT_TYPE -av_ld_data_aligned_filtered[31] <= av_ld_data_aligned_unfiltered[31].DB_MAX_OUTPUT_PORT_TYPE -d_write <= d_write~reg0.DB_MAX_OUTPUT_PORT_TYPE -test_has_ended <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a -clock => clock.IN1 -data[0] => data[0].IN1 -data[1] => data[1].IN1 -data[2] => data[2].IN1 -data[3] => data[3].IN1 -data[4] => data[4].IN1 -data[5] => data[5].IN1 -data[6] => data[6].IN1 -data[7] => data[7].IN1 -data[8] => data[8].IN1 -data[9] => data[9].IN1 -data[10] => data[10].IN1 -data[11] => data[11].IN1 -data[12] => data[12].IN1 -data[13] => data[13].IN1 -data[14] => data[14].IN1 -data[15] => data[15].IN1 -data[16] => data[16].IN1 -data[17] => data[17].IN1 -data[18] => data[18].IN1 -data[19] => data[19].IN1 -data[20] => data[20].IN1 -data[21] => data[21].IN1 -data[22] => data[22].IN1 -data[23] => data[23].IN1 -data[24] => data[24].IN1 -data[25] => data[25].IN1 -data[26] => data[26].IN1 -data[27] => data[27].IN1 -data[28] => data[28].IN1 -data[29] => data[29].IN1 -data[30] => data[30].IN1 -data[31] => data[31].IN1 -rdaddress[0] => rdaddress[0].IN1 -rdaddress[1] => rdaddress[1].IN1 -rdaddress[2] => rdaddress[2].IN1 -rdaddress[3] => rdaddress[3].IN1 -rdaddress[4] => rdaddress[4].IN1 -wraddress[0] => wraddress[0].IN1 -wraddress[1] => wraddress[1].IN1 -wraddress[2] => wraddress[2].IN1 -wraddress[3] => wraddress[3].IN1 -wraddress[4] => wraddress[4].IN1 -wren => wren.IN1 -q[0] <= altsyncram:the_altsyncram.q_b -q[1] <= altsyncram:the_altsyncram.q_b -q[2] <= altsyncram:the_altsyncram.q_b -q[3] <= altsyncram:the_altsyncram.q_b -q[4] <= altsyncram:the_altsyncram.q_b -q[5] <= altsyncram:the_altsyncram.q_b -q[6] <= altsyncram:the_altsyncram.q_b -q[7] <= altsyncram:the_altsyncram.q_b -q[8] <= altsyncram:the_altsyncram.q_b -q[9] <= altsyncram:the_altsyncram.q_b -q[10] <= altsyncram:the_altsyncram.q_b -q[11] <= altsyncram:the_altsyncram.q_b -q[12] <= altsyncram:the_altsyncram.q_b -q[13] <= altsyncram:the_altsyncram.q_b -q[14] <= altsyncram:the_altsyncram.q_b -q[15] <= altsyncram:the_altsyncram.q_b -q[16] <= altsyncram:the_altsyncram.q_b -q[17] <= altsyncram:the_altsyncram.q_b -q[18] <= altsyncram:the_altsyncram.q_b -q[19] <= altsyncram:the_altsyncram.q_b -q[20] <= altsyncram:the_altsyncram.q_b -q[21] <= altsyncram:the_altsyncram.q_b -q[22] <= altsyncram:the_altsyncram.q_b -q[23] <= altsyncram:the_altsyncram.q_b -q[24] <= altsyncram:the_altsyncram.q_b -q[25] <= altsyncram:the_altsyncram.q_b -q[26] <= altsyncram:the_altsyncram.q_b -q[27] <= altsyncram:the_altsyncram.q_b -q[28] <= altsyncram:the_altsyncram.q_b -q[29] <= altsyncram:the_altsyncram.q_b -q[30] <= altsyncram:the_altsyncram.q_b -q[31] <= altsyncram:the_altsyncram.q_b - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram -wren_a => altsyncram_0rh1:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_0rh1:auto_generated.data_a[0] -data_a[1] => altsyncram_0rh1:auto_generated.data_a[1] -data_a[2] => altsyncram_0rh1:auto_generated.data_a[2] -data_a[3] => altsyncram_0rh1:auto_generated.data_a[3] -data_a[4] => altsyncram_0rh1:auto_generated.data_a[4] -data_a[5] => altsyncram_0rh1:auto_generated.data_a[5] -data_a[6] => altsyncram_0rh1:auto_generated.data_a[6] -data_a[7] => altsyncram_0rh1:auto_generated.data_a[7] -data_a[8] => altsyncram_0rh1:auto_generated.data_a[8] -data_a[9] => altsyncram_0rh1:auto_generated.data_a[9] -data_a[10] => altsyncram_0rh1:auto_generated.data_a[10] -data_a[11] => altsyncram_0rh1:auto_generated.data_a[11] -data_a[12] => altsyncram_0rh1:auto_generated.data_a[12] -data_a[13] => altsyncram_0rh1:auto_generated.data_a[13] -data_a[14] => altsyncram_0rh1:auto_generated.data_a[14] -data_a[15] => altsyncram_0rh1:auto_generated.data_a[15] -data_a[16] => altsyncram_0rh1:auto_generated.data_a[16] -data_a[17] => altsyncram_0rh1:auto_generated.data_a[17] -data_a[18] => altsyncram_0rh1:auto_generated.data_a[18] -data_a[19] => altsyncram_0rh1:auto_generated.data_a[19] -data_a[20] => altsyncram_0rh1:auto_generated.data_a[20] -data_a[21] => altsyncram_0rh1:auto_generated.data_a[21] -data_a[22] => altsyncram_0rh1:auto_generated.data_a[22] -data_a[23] => altsyncram_0rh1:auto_generated.data_a[23] -data_a[24] => altsyncram_0rh1:auto_generated.data_a[24] -data_a[25] => altsyncram_0rh1:auto_generated.data_a[25] -data_a[26] => altsyncram_0rh1:auto_generated.data_a[26] -data_a[27] => altsyncram_0rh1:auto_generated.data_a[27] -data_a[28] => altsyncram_0rh1:auto_generated.data_a[28] -data_a[29] => altsyncram_0rh1:auto_generated.data_a[29] -data_a[30] => altsyncram_0rh1:auto_generated.data_a[30] -data_a[31] => altsyncram_0rh1:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -data_b[1] => ~NO_FANOUT~ -data_b[2] => ~NO_FANOUT~ -data_b[3] => ~NO_FANOUT~ -data_b[4] => ~NO_FANOUT~ -data_b[5] => ~NO_FANOUT~ -data_b[6] => ~NO_FANOUT~ -data_b[7] => ~NO_FANOUT~ -data_b[8] => ~NO_FANOUT~ -data_b[9] => ~NO_FANOUT~ -data_b[10] => ~NO_FANOUT~ -data_b[11] => ~NO_FANOUT~ -data_b[12] => ~NO_FANOUT~ -data_b[13] => ~NO_FANOUT~ -data_b[14] => ~NO_FANOUT~ -data_b[15] => ~NO_FANOUT~ -data_b[16] => ~NO_FANOUT~ -data_b[17] => ~NO_FANOUT~ -data_b[18] => ~NO_FANOUT~ -data_b[19] => ~NO_FANOUT~ -data_b[20] => ~NO_FANOUT~ -data_b[21] => ~NO_FANOUT~ -data_b[22] => ~NO_FANOUT~ -data_b[23] => ~NO_FANOUT~ -data_b[24] => ~NO_FANOUT~ -data_b[25] => ~NO_FANOUT~ -data_b[26] => ~NO_FANOUT~ -data_b[27] => ~NO_FANOUT~ -data_b[28] => ~NO_FANOUT~ -data_b[29] => ~NO_FANOUT~ -data_b[30] => ~NO_FANOUT~ -data_b[31] => ~NO_FANOUT~ -address_a[0] => altsyncram_0rh1:auto_generated.address_a[0] -address_a[1] => altsyncram_0rh1:auto_generated.address_a[1] -address_a[2] => altsyncram_0rh1:auto_generated.address_a[2] -address_a[3] => altsyncram_0rh1:auto_generated.address_a[3] -address_a[4] => altsyncram_0rh1:auto_generated.address_a[4] -address_b[0] => altsyncram_0rh1:auto_generated.address_b[0] -address_b[1] => altsyncram_0rh1:auto_generated.address_b[1] -address_b[2] => altsyncram_0rh1:auto_generated.address_b[2] -address_b[3] => altsyncram_0rh1:auto_generated.address_b[3] -address_b[4] => altsyncram_0rh1:auto_generated.address_b[4] -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_0rh1:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => ~NO_FANOUT~ -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => ~NO_FANOUT~ -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= -q_a[1] <= -q_a[2] <= -q_a[3] <= -q_a[4] <= -q_a[5] <= -q_a[6] <= -q_a[7] <= -q_a[8] <= -q_a[9] <= -q_a[10] <= -q_a[11] <= -q_a[12] <= -q_a[13] <= -q_a[14] <= -q_a[15] <= -q_a[16] <= -q_a[17] <= -q_a[18] <= -q_a[19] <= -q_a[20] <= -q_a[21] <= -q_a[22] <= -q_a[23] <= -q_a[24] <= -q_a[25] <= -q_a[26] <= -q_a[27] <= -q_a[28] <= -q_a[29] <= -q_a[30] <= -q_a[31] <= -q_b[0] <= altsyncram_0rh1:auto_generated.q_b[0] -q_b[1] <= altsyncram_0rh1:auto_generated.q_b[1] -q_b[2] <= altsyncram_0rh1:auto_generated.q_b[2] -q_b[3] <= altsyncram_0rh1:auto_generated.q_b[3] -q_b[4] <= altsyncram_0rh1:auto_generated.q_b[4] -q_b[5] <= altsyncram_0rh1:auto_generated.q_b[5] -q_b[6] <= altsyncram_0rh1:auto_generated.q_b[6] -q_b[7] <= altsyncram_0rh1:auto_generated.q_b[7] -q_b[8] <= altsyncram_0rh1:auto_generated.q_b[8] -q_b[9] <= altsyncram_0rh1:auto_generated.q_b[9] -q_b[10] <= altsyncram_0rh1:auto_generated.q_b[10] -q_b[11] <= altsyncram_0rh1:auto_generated.q_b[11] -q_b[12] <= altsyncram_0rh1:auto_generated.q_b[12] -q_b[13] <= altsyncram_0rh1:auto_generated.q_b[13] -q_b[14] <= altsyncram_0rh1:auto_generated.q_b[14] -q_b[15] <= altsyncram_0rh1:auto_generated.q_b[15] -q_b[16] <= altsyncram_0rh1:auto_generated.q_b[16] -q_b[17] <= altsyncram_0rh1:auto_generated.q_b[17] -q_b[18] <= altsyncram_0rh1:auto_generated.q_b[18] -q_b[19] <= altsyncram_0rh1:auto_generated.q_b[19] -q_b[20] <= altsyncram_0rh1:auto_generated.q_b[20] -q_b[21] <= altsyncram_0rh1:auto_generated.q_b[21] -q_b[22] <= altsyncram_0rh1:auto_generated.q_b[22] -q_b[23] <= altsyncram_0rh1:auto_generated.q_b[23] -q_b[24] <= altsyncram_0rh1:auto_generated.q_b[24] -q_b[25] <= altsyncram_0rh1:auto_generated.q_b[25] -q_b[26] <= altsyncram_0rh1:auto_generated.q_b[26] -q_b[27] <= altsyncram_0rh1:auto_generated.q_b[27] -q_b[28] <= altsyncram_0rh1:auto_generated.q_b[28] -q_b[29] <= altsyncram_0rh1:auto_generated.q_b[29] -q_b[30] <= altsyncram_0rh1:auto_generated.q_b[30] -q_b[31] <= altsyncram_0rh1:auto_generated.q_b[31] -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_b[0] => ram_block1a0.PORTBADDR -address_b[0] => ram_block1a1.PORTBADDR -address_b[0] => ram_block1a2.PORTBADDR -address_b[0] => ram_block1a3.PORTBADDR -address_b[0] => ram_block1a4.PORTBADDR -address_b[0] => ram_block1a5.PORTBADDR -address_b[0] => ram_block1a6.PORTBADDR -address_b[0] => ram_block1a7.PORTBADDR -address_b[0] => ram_block1a8.PORTBADDR -address_b[0] => ram_block1a9.PORTBADDR -address_b[0] => ram_block1a10.PORTBADDR -address_b[0] => ram_block1a11.PORTBADDR -address_b[0] => ram_block1a12.PORTBADDR -address_b[0] => ram_block1a13.PORTBADDR -address_b[0] => ram_block1a14.PORTBADDR -address_b[0] => ram_block1a15.PORTBADDR -address_b[0] => ram_block1a16.PORTBADDR -address_b[0] => ram_block1a17.PORTBADDR -address_b[0] => ram_block1a18.PORTBADDR -address_b[0] => ram_block1a19.PORTBADDR -address_b[0] => ram_block1a20.PORTBADDR -address_b[0] => ram_block1a21.PORTBADDR -address_b[0] => ram_block1a22.PORTBADDR -address_b[0] => ram_block1a23.PORTBADDR -address_b[0] => ram_block1a24.PORTBADDR -address_b[0] => ram_block1a25.PORTBADDR -address_b[0] => ram_block1a26.PORTBADDR -address_b[0] => ram_block1a27.PORTBADDR -address_b[0] => ram_block1a28.PORTBADDR -address_b[0] => ram_block1a29.PORTBADDR -address_b[0] => ram_block1a30.PORTBADDR -address_b[0] => ram_block1a31.PORTBADDR -address_b[1] => ram_block1a0.PORTBADDR1 -address_b[1] => ram_block1a1.PORTBADDR1 -address_b[1] => ram_block1a2.PORTBADDR1 -address_b[1] => ram_block1a3.PORTBADDR1 -address_b[1] => ram_block1a4.PORTBADDR1 -address_b[1] => ram_block1a5.PORTBADDR1 -address_b[1] => ram_block1a6.PORTBADDR1 -address_b[1] => ram_block1a7.PORTBADDR1 -address_b[1] => ram_block1a8.PORTBADDR1 -address_b[1] => ram_block1a9.PORTBADDR1 -address_b[1] => ram_block1a10.PORTBADDR1 -address_b[1] => ram_block1a11.PORTBADDR1 -address_b[1] => ram_block1a12.PORTBADDR1 -address_b[1] => ram_block1a13.PORTBADDR1 -address_b[1] => ram_block1a14.PORTBADDR1 -address_b[1] => ram_block1a15.PORTBADDR1 -address_b[1] => ram_block1a16.PORTBADDR1 -address_b[1] => ram_block1a17.PORTBADDR1 -address_b[1] => ram_block1a18.PORTBADDR1 -address_b[1] => ram_block1a19.PORTBADDR1 -address_b[1] => ram_block1a20.PORTBADDR1 -address_b[1] => ram_block1a21.PORTBADDR1 -address_b[1] => ram_block1a22.PORTBADDR1 -address_b[1] => ram_block1a23.PORTBADDR1 -address_b[1] => ram_block1a24.PORTBADDR1 -address_b[1] => ram_block1a25.PORTBADDR1 -address_b[1] => ram_block1a26.PORTBADDR1 -address_b[1] => ram_block1a27.PORTBADDR1 -address_b[1] => ram_block1a28.PORTBADDR1 -address_b[1] => ram_block1a29.PORTBADDR1 -address_b[1] => ram_block1a30.PORTBADDR1 -address_b[1] => ram_block1a31.PORTBADDR1 -address_b[2] => ram_block1a0.PORTBADDR2 -address_b[2] => ram_block1a1.PORTBADDR2 -address_b[2] => ram_block1a2.PORTBADDR2 -address_b[2] => ram_block1a3.PORTBADDR2 -address_b[2] => ram_block1a4.PORTBADDR2 -address_b[2] => ram_block1a5.PORTBADDR2 -address_b[2] => ram_block1a6.PORTBADDR2 -address_b[2] => ram_block1a7.PORTBADDR2 -address_b[2] => ram_block1a8.PORTBADDR2 -address_b[2] => ram_block1a9.PORTBADDR2 -address_b[2] => ram_block1a10.PORTBADDR2 -address_b[2] => ram_block1a11.PORTBADDR2 -address_b[2] => ram_block1a12.PORTBADDR2 -address_b[2] => ram_block1a13.PORTBADDR2 -address_b[2] => ram_block1a14.PORTBADDR2 -address_b[2] => ram_block1a15.PORTBADDR2 -address_b[2] => ram_block1a16.PORTBADDR2 -address_b[2] => ram_block1a17.PORTBADDR2 -address_b[2] => ram_block1a18.PORTBADDR2 -address_b[2] => ram_block1a19.PORTBADDR2 -address_b[2] => ram_block1a20.PORTBADDR2 -address_b[2] => ram_block1a21.PORTBADDR2 -address_b[2] => ram_block1a22.PORTBADDR2 -address_b[2] => ram_block1a23.PORTBADDR2 -address_b[2] => ram_block1a24.PORTBADDR2 -address_b[2] => ram_block1a25.PORTBADDR2 -address_b[2] => ram_block1a26.PORTBADDR2 -address_b[2] => ram_block1a27.PORTBADDR2 -address_b[2] => ram_block1a28.PORTBADDR2 -address_b[2] => ram_block1a29.PORTBADDR2 -address_b[2] => ram_block1a30.PORTBADDR2 -address_b[2] => ram_block1a31.PORTBADDR2 -address_b[3] => ram_block1a0.PORTBADDR3 -address_b[3] => ram_block1a1.PORTBADDR3 -address_b[3] => ram_block1a2.PORTBADDR3 -address_b[3] => ram_block1a3.PORTBADDR3 -address_b[3] => ram_block1a4.PORTBADDR3 -address_b[3] => ram_block1a5.PORTBADDR3 -address_b[3] => ram_block1a6.PORTBADDR3 -address_b[3] => ram_block1a7.PORTBADDR3 -address_b[3] => ram_block1a8.PORTBADDR3 -address_b[3] => ram_block1a9.PORTBADDR3 -address_b[3] => ram_block1a10.PORTBADDR3 -address_b[3] => ram_block1a11.PORTBADDR3 -address_b[3] => ram_block1a12.PORTBADDR3 -address_b[3] => ram_block1a13.PORTBADDR3 -address_b[3] => ram_block1a14.PORTBADDR3 -address_b[3] => ram_block1a15.PORTBADDR3 -address_b[3] => ram_block1a16.PORTBADDR3 -address_b[3] => ram_block1a17.PORTBADDR3 -address_b[3] => ram_block1a18.PORTBADDR3 -address_b[3] => ram_block1a19.PORTBADDR3 -address_b[3] => ram_block1a20.PORTBADDR3 -address_b[3] => ram_block1a21.PORTBADDR3 -address_b[3] => ram_block1a22.PORTBADDR3 -address_b[3] => ram_block1a23.PORTBADDR3 -address_b[3] => ram_block1a24.PORTBADDR3 -address_b[3] => ram_block1a25.PORTBADDR3 -address_b[3] => ram_block1a26.PORTBADDR3 -address_b[3] => ram_block1a27.PORTBADDR3 -address_b[3] => ram_block1a28.PORTBADDR3 -address_b[3] => ram_block1a29.PORTBADDR3 -address_b[3] => ram_block1a30.PORTBADDR3 -address_b[3] => ram_block1a31.PORTBADDR3 -address_b[4] => ram_block1a0.PORTBADDR4 -address_b[4] => ram_block1a1.PORTBADDR4 -address_b[4] => ram_block1a2.PORTBADDR4 -address_b[4] => ram_block1a3.PORTBADDR4 -address_b[4] => ram_block1a4.PORTBADDR4 -address_b[4] => ram_block1a5.PORTBADDR4 -address_b[4] => ram_block1a6.PORTBADDR4 -address_b[4] => ram_block1a7.PORTBADDR4 -address_b[4] => ram_block1a8.PORTBADDR4 -address_b[4] => ram_block1a9.PORTBADDR4 -address_b[4] => ram_block1a10.PORTBADDR4 -address_b[4] => ram_block1a11.PORTBADDR4 -address_b[4] => ram_block1a12.PORTBADDR4 -address_b[4] => ram_block1a13.PORTBADDR4 -address_b[4] => ram_block1a14.PORTBADDR4 -address_b[4] => ram_block1a15.PORTBADDR4 -address_b[4] => ram_block1a16.PORTBADDR4 -address_b[4] => ram_block1a17.PORTBADDR4 -address_b[4] => ram_block1a18.PORTBADDR4 -address_b[4] => ram_block1a19.PORTBADDR4 -address_b[4] => ram_block1a20.PORTBADDR4 -address_b[4] => ram_block1a21.PORTBADDR4 -address_b[4] => ram_block1a22.PORTBADDR4 -address_b[4] => ram_block1a23.PORTBADDR4 -address_b[4] => ram_block1a24.PORTBADDR4 -address_b[4] => ram_block1a25.PORTBADDR4 -address_b[4] => ram_block1a26.PORTBADDR4 -address_b[4] => ram_block1a27.PORTBADDR4 -address_b[4] => ram_block1a28.PORTBADDR4 -address_b[4] => ram_block1a29.PORTBADDR4 -address_b[4] => ram_block1a30.PORTBADDR4 -address_b[4] => ram_block1a31.PORTBADDR4 -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -data_a[0] => ram_block1a0.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -q_b[0] <= ram_block1a0.PORTBDATAOUT -q_b[1] <= ram_block1a1.PORTBDATAOUT -q_b[2] <= ram_block1a2.PORTBDATAOUT -q_b[3] <= ram_block1a3.PORTBDATAOUT -q_b[4] <= ram_block1a4.PORTBDATAOUT -q_b[5] <= ram_block1a5.PORTBDATAOUT -q_b[6] <= ram_block1a6.PORTBDATAOUT -q_b[7] <= ram_block1a7.PORTBDATAOUT -q_b[8] <= ram_block1a8.PORTBDATAOUT -q_b[9] <= ram_block1a9.PORTBDATAOUT -q_b[10] <= ram_block1a10.PORTBDATAOUT -q_b[11] <= ram_block1a11.PORTBDATAOUT -q_b[12] <= ram_block1a12.PORTBDATAOUT -q_b[13] <= ram_block1a13.PORTBDATAOUT -q_b[14] <= ram_block1a14.PORTBDATAOUT -q_b[15] <= ram_block1a15.PORTBDATAOUT -q_b[16] <= ram_block1a16.PORTBDATAOUT -q_b[17] <= ram_block1a17.PORTBDATAOUT -q_b[18] <= ram_block1a18.PORTBDATAOUT -q_b[19] <= ram_block1a19.PORTBDATAOUT -q_b[20] <= ram_block1a20.PORTBDATAOUT -q_b[21] <= ram_block1a21.PORTBDATAOUT -q_b[22] <= ram_block1a22.PORTBDATAOUT -q_b[23] <= ram_block1a23.PORTBDATAOUT -q_b[24] <= ram_block1a24.PORTBDATAOUT -q_b[25] <= ram_block1a25.PORTBDATAOUT -q_b[26] <= ram_block1a26.PORTBDATAOUT -q_b[27] <= ram_block1a27.PORTBDATAOUT -q_b[28] <= ram_block1a28.PORTBDATAOUT -q_b[29] <= ram_block1a29.PORTBDATAOUT -q_b[30] <= ram_block1a30.PORTBDATAOUT -q_b[31] <= ram_block1a31.PORTBDATAOUT -wren_a => ram_block1a0.PORTAWE -wren_a => ram_block1a1.PORTAWE -wren_a => ram_block1a2.PORTAWE -wren_a => ram_block1a3.PORTAWE -wren_a => ram_block1a4.PORTAWE -wren_a => ram_block1a5.PORTAWE -wren_a => ram_block1a6.PORTAWE -wren_a => ram_block1a7.PORTAWE -wren_a => ram_block1a8.PORTAWE -wren_a => ram_block1a9.PORTAWE -wren_a => ram_block1a10.PORTAWE -wren_a => ram_block1a11.PORTAWE -wren_a => ram_block1a12.PORTAWE -wren_a => ram_block1a13.PORTAWE -wren_a => ram_block1a14.PORTAWE -wren_a => ram_block1a15.PORTAWE -wren_a => ram_block1a16.PORTAWE -wren_a => ram_block1a17.PORTAWE -wren_a => ram_block1a18.PORTAWE -wren_a => ram_block1a19.PORTAWE -wren_a => ram_block1a20.PORTAWE -wren_a => ram_block1a21.PORTAWE -wren_a => ram_block1a22.PORTAWE -wren_a => ram_block1a23.PORTAWE -wren_a => ram_block1a24.PORTAWE -wren_a => ram_block1a25.PORTAWE -wren_a => ram_block1a26.PORTAWE -wren_a => ram_block1a27.PORTAWE -wren_a => ram_block1a28.PORTAWE -wren_a => ram_block1a29.PORTAWE -wren_a => ram_block1a30.PORTAWE -wren_a => ram_block1a31.PORTAWE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b -clock => clock.IN1 -data[0] => data[0].IN1 -data[1] => data[1].IN1 -data[2] => data[2].IN1 -data[3] => data[3].IN1 -data[4] => data[4].IN1 -data[5] => data[5].IN1 -data[6] => data[6].IN1 -data[7] => data[7].IN1 -data[8] => data[8].IN1 -data[9] => data[9].IN1 -data[10] => data[10].IN1 -data[11] => data[11].IN1 -data[12] => data[12].IN1 -data[13] => data[13].IN1 -data[14] => data[14].IN1 -data[15] => data[15].IN1 -data[16] => data[16].IN1 -data[17] => data[17].IN1 -data[18] => data[18].IN1 -data[19] => data[19].IN1 -data[20] => data[20].IN1 -data[21] => data[21].IN1 -data[22] => data[22].IN1 -data[23] => data[23].IN1 -data[24] => data[24].IN1 -data[25] => data[25].IN1 -data[26] => data[26].IN1 -data[27] => data[27].IN1 -data[28] => data[28].IN1 -data[29] => data[29].IN1 -data[30] => data[30].IN1 -data[31] => data[31].IN1 -rdaddress[0] => rdaddress[0].IN1 -rdaddress[1] => rdaddress[1].IN1 -rdaddress[2] => rdaddress[2].IN1 -rdaddress[3] => rdaddress[3].IN1 -rdaddress[4] => rdaddress[4].IN1 -wraddress[0] => wraddress[0].IN1 -wraddress[1] => wraddress[1].IN1 -wraddress[2] => wraddress[2].IN1 -wraddress[3] => wraddress[3].IN1 -wraddress[4] => wraddress[4].IN1 -wren => wren.IN1 -q[0] <= altsyncram:the_altsyncram.q_b -q[1] <= altsyncram:the_altsyncram.q_b -q[2] <= altsyncram:the_altsyncram.q_b -q[3] <= altsyncram:the_altsyncram.q_b -q[4] <= altsyncram:the_altsyncram.q_b -q[5] <= altsyncram:the_altsyncram.q_b -q[6] <= altsyncram:the_altsyncram.q_b -q[7] <= altsyncram:the_altsyncram.q_b -q[8] <= altsyncram:the_altsyncram.q_b -q[9] <= altsyncram:the_altsyncram.q_b -q[10] <= altsyncram:the_altsyncram.q_b -q[11] <= altsyncram:the_altsyncram.q_b -q[12] <= altsyncram:the_altsyncram.q_b -q[13] <= altsyncram:the_altsyncram.q_b -q[14] <= altsyncram:the_altsyncram.q_b -q[15] <= altsyncram:the_altsyncram.q_b -q[16] <= altsyncram:the_altsyncram.q_b -q[17] <= altsyncram:the_altsyncram.q_b -q[18] <= altsyncram:the_altsyncram.q_b -q[19] <= altsyncram:the_altsyncram.q_b -q[20] <= altsyncram:the_altsyncram.q_b -q[21] <= altsyncram:the_altsyncram.q_b -q[22] <= altsyncram:the_altsyncram.q_b -q[23] <= altsyncram:the_altsyncram.q_b -q[24] <= altsyncram:the_altsyncram.q_b -q[25] <= altsyncram:the_altsyncram.q_b -q[26] <= altsyncram:the_altsyncram.q_b -q[27] <= altsyncram:the_altsyncram.q_b -q[28] <= altsyncram:the_altsyncram.q_b -q[29] <= altsyncram:the_altsyncram.q_b -q[30] <= altsyncram:the_altsyncram.q_b -q[31] <= altsyncram:the_altsyncram.q_b - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram -wren_a => altsyncram_1rh1:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_1rh1:auto_generated.data_a[0] -data_a[1] => altsyncram_1rh1:auto_generated.data_a[1] -data_a[2] => altsyncram_1rh1:auto_generated.data_a[2] -data_a[3] => altsyncram_1rh1:auto_generated.data_a[3] -data_a[4] => altsyncram_1rh1:auto_generated.data_a[4] -data_a[5] => altsyncram_1rh1:auto_generated.data_a[5] -data_a[6] => altsyncram_1rh1:auto_generated.data_a[6] -data_a[7] => altsyncram_1rh1:auto_generated.data_a[7] -data_a[8] => altsyncram_1rh1:auto_generated.data_a[8] -data_a[9] => altsyncram_1rh1:auto_generated.data_a[9] -data_a[10] => altsyncram_1rh1:auto_generated.data_a[10] -data_a[11] => altsyncram_1rh1:auto_generated.data_a[11] -data_a[12] => altsyncram_1rh1:auto_generated.data_a[12] -data_a[13] => altsyncram_1rh1:auto_generated.data_a[13] -data_a[14] => altsyncram_1rh1:auto_generated.data_a[14] -data_a[15] => altsyncram_1rh1:auto_generated.data_a[15] -data_a[16] => altsyncram_1rh1:auto_generated.data_a[16] -data_a[17] => altsyncram_1rh1:auto_generated.data_a[17] -data_a[18] => altsyncram_1rh1:auto_generated.data_a[18] -data_a[19] => altsyncram_1rh1:auto_generated.data_a[19] -data_a[20] => altsyncram_1rh1:auto_generated.data_a[20] -data_a[21] => altsyncram_1rh1:auto_generated.data_a[21] -data_a[22] => altsyncram_1rh1:auto_generated.data_a[22] -data_a[23] => altsyncram_1rh1:auto_generated.data_a[23] -data_a[24] => altsyncram_1rh1:auto_generated.data_a[24] -data_a[25] => altsyncram_1rh1:auto_generated.data_a[25] -data_a[26] => altsyncram_1rh1:auto_generated.data_a[26] -data_a[27] => altsyncram_1rh1:auto_generated.data_a[27] -data_a[28] => altsyncram_1rh1:auto_generated.data_a[28] -data_a[29] => altsyncram_1rh1:auto_generated.data_a[29] -data_a[30] => altsyncram_1rh1:auto_generated.data_a[30] -data_a[31] => altsyncram_1rh1:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -data_b[1] => ~NO_FANOUT~ -data_b[2] => ~NO_FANOUT~ -data_b[3] => ~NO_FANOUT~ -data_b[4] => ~NO_FANOUT~ -data_b[5] => ~NO_FANOUT~ -data_b[6] => ~NO_FANOUT~ -data_b[7] => ~NO_FANOUT~ -data_b[8] => ~NO_FANOUT~ -data_b[9] => ~NO_FANOUT~ -data_b[10] => ~NO_FANOUT~ -data_b[11] => ~NO_FANOUT~ -data_b[12] => ~NO_FANOUT~ -data_b[13] => ~NO_FANOUT~ -data_b[14] => ~NO_FANOUT~ -data_b[15] => ~NO_FANOUT~ -data_b[16] => ~NO_FANOUT~ -data_b[17] => ~NO_FANOUT~ -data_b[18] => ~NO_FANOUT~ -data_b[19] => ~NO_FANOUT~ -data_b[20] => ~NO_FANOUT~ -data_b[21] => ~NO_FANOUT~ -data_b[22] => ~NO_FANOUT~ -data_b[23] => ~NO_FANOUT~ -data_b[24] => ~NO_FANOUT~ -data_b[25] => ~NO_FANOUT~ -data_b[26] => ~NO_FANOUT~ -data_b[27] => ~NO_FANOUT~ -data_b[28] => ~NO_FANOUT~ -data_b[29] => ~NO_FANOUT~ -data_b[30] => ~NO_FANOUT~ -data_b[31] => ~NO_FANOUT~ -address_a[0] => altsyncram_1rh1:auto_generated.address_a[0] -address_a[1] => altsyncram_1rh1:auto_generated.address_a[1] -address_a[2] => altsyncram_1rh1:auto_generated.address_a[2] -address_a[3] => altsyncram_1rh1:auto_generated.address_a[3] -address_a[4] => altsyncram_1rh1:auto_generated.address_a[4] -address_b[0] => altsyncram_1rh1:auto_generated.address_b[0] -address_b[1] => altsyncram_1rh1:auto_generated.address_b[1] -address_b[2] => altsyncram_1rh1:auto_generated.address_b[2] -address_b[3] => altsyncram_1rh1:auto_generated.address_b[3] -address_b[4] => altsyncram_1rh1:auto_generated.address_b[4] -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_1rh1:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => ~NO_FANOUT~ -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => ~NO_FANOUT~ -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= -q_a[1] <= -q_a[2] <= -q_a[3] <= -q_a[4] <= -q_a[5] <= -q_a[6] <= -q_a[7] <= -q_a[8] <= -q_a[9] <= -q_a[10] <= -q_a[11] <= -q_a[12] <= -q_a[13] <= -q_a[14] <= -q_a[15] <= -q_a[16] <= -q_a[17] <= -q_a[18] <= -q_a[19] <= -q_a[20] <= -q_a[21] <= -q_a[22] <= -q_a[23] <= -q_a[24] <= -q_a[25] <= -q_a[26] <= -q_a[27] <= -q_a[28] <= -q_a[29] <= -q_a[30] <= -q_a[31] <= -q_b[0] <= altsyncram_1rh1:auto_generated.q_b[0] -q_b[1] <= altsyncram_1rh1:auto_generated.q_b[1] -q_b[2] <= altsyncram_1rh1:auto_generated.q_b[2] -q_b[3] <= altsyncram_1rh1:auto_generated.q_b[3] -q_b[4] <= altsyncram_1rh1:auto_generated.q_b[4] -q_b[5] <= altsyncram_1rh1:auto_generated.q_b[5] -q_b[6] <= altsyncram_1rh1:auto_generated.q_b[6] -q_b[7] <= altsyncram_1rh1:auto_generated.q_b[7] -q_b[8] <= altsyncram_1rh1:auto_generated.q_b[8] -q_b[9] <= altsyncram_1rh1:auto_generated.q_b[9] -q_b[10] <= altsyncram_1rh1:auto_generated.q_b[10] -q_b[11] <= altsyncram_1rh1:auto_generated.q_b[11] -q_b[12] <= altsyncram_1rh1:auto_generated.q_b[12] -q_b[13] <= altsyncram_1rh1:auto_generated.q_b[13] -q_b[14] <= altsyncram_1rh1:auto_generated.q_b[14] -q_b[15] <= altsyncram_1rh1:auto_generated.q_b[15] -q_b[16] <= altsyncram_1rh1:auto_generated.q_b[16] -q_b[17] <= altsyncram_1rh1:auto_generated.q_b[17] -q_b[18] <= altsyncram_1rh1:auto_generated.q_b[18] -q_b[19] <= altsyncram_1rh1:auto_generated.q_b[19] -q_b[20] <= altsyncram_1rh1:auto_generated.q_b[20] -q_b[21] <= altsyncram_1rh1:auto_generated.q_b[21] -q_b[22] <= altsyncram_1rh1:auto_generated.q_b[22] -q_b[23] <= altsyncram_1rh1:auto_generated.q_b[23] -q_b[24] <= altsyncram_1rh1:auto_generated.q_b[24] -q_b[25] <= altsyncram_1rh1:auto_generated.q_b[25] -q_b[26] <= altsyncram_1rh1:auto_generated.q_b[26] -q_b[27] <= altsyncram_1rh1:auto_generated.q_b[27] -q_b[28] <= altsyncram_1rh1:auto_generated.q_b[28] -q_b[29] <= altsyncram_1rh1:auto_generated.q_b[29] -q_b[30] <= altsyncram_1rh1:auto_generated.q_b[30] -q_b[31] <= altsyncram_1rh1:auto_generated.q_b[31] -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_b[0] => ram_block1a0.PORTBADDR -address_b[0] => ram_block1a1.PORTBADDR -address_b[0] => ram_block1a2.PORTBADDR -address_b[0] => ram_block1a3.PORTBADDR -address_b[0] => ram_block1a4.PORTBADDR -address_b[0] => ram_block1a5.PORTBADDR -address_b[0] => ram_block1a6.PORTBADDR -address_b[0] => ram_block1a7.PORTBADDR -address_b[0] => ram_block1a8.PORTBADDR -address_b[0] => ram_block1a9.PORTBADDR -address_b[0] => ram_block1a10.PORTBADDR -address_b[0] => ram_block1a11.PORTBADDR -address_b[0] => ram_block1a12.PORTBADDR -address_b[0] => ram_block1a13.PORTBADDR -address_b[0] => ram_block1a14.PORTBADDR -address_b[0] => ram_block1a15.PORTBADDR -address_b[0] => ram_block1a16.PORTBADDR -address_b[0] => ram_block1a17.PORTBADDR -address_b[0] => ram_block1a18.PORTBADDR -address_b[0] => ram_block1a19.PORTBADDR -address_b[0] => ram_block1a20.PORTBADDR -address_b[0] => ram_block1a21.PORTBADDR -address_b[0] => ram_block1a22.PORTBADDR -address_b[0] => ram_block1a23.PORTBADDR -address_b[0] => ram_block1a24.PORTBADDR -address_b[0] => ram_block1a25.PORTBADDR -address_b[0] => ram_block1a26.PORTBADDR -address_b[0] => ram_block1a27.PORTBADDR -address_b[0] => ram_block1a28.PORTBADDR -address_b[0] => ram_block1a29.PORTBADDR -address_b[0] => ram_block1a30.PORTBADDR -address_b[0] => ram_block1a31.PORTBADDR -address_b[1] => ram_block1a0.PORTBADDR1 -address_b[1] => ram_block1a1.PORTBADDR1 -address_b[1] => ram_block1a2.PORTBADDR1 -address_b[1] => ram_block1a3.PORTBADDR1 -address_b[1] => ram_block1a4.PORTBADDR1 -address_b[1] => ram_block1a5.PORTBADDR1 -address_b[1] => ram_block1a6.PORTBADDR1 -address_b[1] => ram_block1a7.PORTBADDR1 -address_b[1] => ram_block1a8.PORTBADDR1 -address_b[1] => ram_block1a9.PORTBADDR1 -address_b[1] => ram_block1a10.PORTBADDR1 -address_b[1] => ram_block1a11.PORTBADDR1 -address_b[1] => ram_block1a12.PORTBADDR1 -address_b[1] => ram_block1a13.PORTBADDR1 -address_b[1] => ram_block1a14.PORTBADDR1 -address_b[1] => ram_block1a15.PORTBADDR1 -address_b[1] => ram_block1a16.PORTBADDR1 -address_b[1] => ram_block1a17.PORTBADDR1 -address_b[1] => ram_block1a18.PORTBADDR1 -address_b[1] => ram_block1a19.PORTBADDR1 -address_b[1] => ram_block1a20.PORTBADDR1 -address_b[1] => ram_block1a21.PORTBADDR1 -address_b[1] => ram_block1a22.PORTBADDR1 -address_b[1] => ram_block1a23.PORTBADDR1 -address_b[1] => ram_block1a24.PORTBADDR1 -address_b[1] => ram_block1a25.PORTBADDR1 -address_b[1] => ram_block1a26.PORTBADDR1 -address_b[1] => ram_block1a27.PORTBADDR1 -address_b[1] => ram_block1a28.PORTBADDR1 -address_b[1] => ram_block1a29.PORTBADDR1 -address_b[1] => ram_block1a30.PORTBADDR1 -address_b[1] => ram_block1a31.PORTBADDR1 -address_b[2] => ram_block1a0.PORTBADDR2 -address_b[2] => ram_block1a1.PORTBADDR2 -address_b[2] => ram_block1a2.PORTBADDR2 -address_b[2] => ram_block1a3.PORTBADDR2 -address_b[2] => ram_block1a4.PORTBADDR2 -address_b[2] => ram_block1a5.PORTBADDR2 -address_b[2] => ram_block1a6.PORTBADDR2 -address_b[2] => ram_block1a7.PORTBADDR2 -address_b[2] => ram_block1a8.PORTBADDR2 -address_b[2] => ram_block1a9.PORTBADDR2 -address_b[2] => ram_block1a10.PORTBADDR2 -address_b[2] => ram_block1a11.PORTBADDR2 -address_b[2] => ram_block1a12.PORTBADDR2 -address_b[2] => ram_block1a13.PORTBADDR2 -address_b[2] => ram_block1a14.PORTBADDR2 -address_b[2] => ram_block1a15.PORTBADDR2 -address_b[2] => ram_block1a16.PORTBADDR2 -address_b[2] => ram_block1a17.PORTBADDR2 -address_b[2] => ram_block1a18.PORTBADDR2 -address_b[2] => ram_block1a19.PORTBADDR2 -address_b[2] => ram_block1a20.PORTBADDR2 -address_b[2] => ram_block1a21.PORTBADDR2 -address_b[2] => ram_block1a22.PORTBADDR2 -address_b[2] => ram_block1a23.PORTBADDR2 -address_b[2] => ram_block1a24.PORTBADDR2 -address_b[2] => ram_block1a25.PORTBADDR2 -address_b[2] => ram_block1a26.PORTBADDR2 -address_b[2] => ram_block1a27.PORTBADDR2 -address_b[2] => ram_block1a28.PORTBADDR2 -address_b[2] => ram_block1a29.PORTBADDR2 -address_b[2] => ram_block1a30.PORTBADDR2 -address_b[2] => ram_block1a31.PORTBADDR2 -address_b[3] => ram_block1a0.PORTBADDR3 -address_b[3] => ram_block1a1.PORTBADDR3 -address_b[3] => ram_block1a2.PORTBADDR3 -address_b[3] => ram_block1a3.PORTBADDR3 -address_b[3] => ram_block1a4.PORTBADDR3 -address_b[3] => ram_block1a5.PORTBADDR3 -address_b[3] => ram_block1a6.PORTBADDR3 -address_b[3] => ram_block1a7.PORTBADDR3 -address_b[3] => ram_block1a8.PORTBADDR3 -address_b[3] => ram_block1a9.PORTBADDR3 -address_b[3] => ram_block1a10.PORTBADDR3 -address_b[3] => ram_block1a11.PORTBADDR3 -address_b[3] => ram_block1a12.PORTBADDR3 -address_b[3] => ram_block1a13.PORTBADDR3 -address_b[3] => ram_block1a14.PORTBADDR3 -address_b[3] => ram_block1a15.PORTBADDR3 -address_b[3] => ram_block1a16.PORTBADDR3 -address_b[3] => ram_block1a17.PORTBADDR3 -address_b[3] => ram_block1a18.PORTBADDR3 -address_b[3] => ram_block1a19.PORTBADDR3 -address_b[3] => ram_block1a20.PORTBADDR3 -address_b[3] => ram_block1a21.PORTBADDR3 -address_b[3] => ram_block1a22.PORTBADDR3 -address_b[3] => ram_block1a23.PORTBADDR3 -address_b[3] => ram_block1a24.PORTBADDR3 -address_b[3] => ram_block1a25.PORTBADDR3 -address_b[3] => ram_block1a26.PORTBADDR3 -address_b[3] => ram_block1a27.PORTBADDR3 -address_b[3] => ram_block1a28.PORTBADDR3 -address_b[3] => ram_block1a29.PORTBADDR3 -address_b[3] => ram_block1a30.PORTBADDR3 -address_b[3] => ram_block1a31.PORTBADDR3 -address_b[4] => ram_block1a0.PORTBADDR4 -address_b[4] => ram_block1a1.PORTBADDR4 -address_b[4] => ram_block1a2.PORTBADDR4 -address_b[4] => ram_block1a3.PORTBADDR4 -address_b[4] => ram_block1a4.PORTBADDR4 -address_b[4] => ram_block1a5.PORTBADDR4 -address_b[4] => ram_block1a6.PORTBADDR4 -address_b[4] => ram_block1a7.PORTBADDR4 -address_b[4] => ram_block1a8.PORTBADDR4 -address_b[4] => ram_block1a9.PORTBADDR4 -address_b[4] => ram_block1a10.PORTBADDR4 -address_b[4] => ram_block1a11.PORTBADDR4 -address_b[4] => ram_block1a12.PORTBADDR4 -address_b[4] => ram_block1a13.PORTBADDR4 -address_b[4] => ram_block1a14.PORTBADDR4 -address_b[4] => ram_block1a15.PORTBADDR4 -address_b[4] => ram_block1a16.PORTBADDR4 -address_b[4] => ram_block1a17.PORTBADDR4 -address_b[4] => ram_block1a18.PORTBADDR4 -address_b[4] => ram_block1a19.PORTBADDR4 -address_b[4] => ram_block1a20.PORTBADDR4 -address_b[4] => ram_block1a21.PORTBADDR4 -address_b[4] => ram_block1a22.PORTBADDR4 -address_b[4] => ram_block1a23.PORTBADDR4 -address_b[4] => ram_block1a24.PORTBADDR4 -address_b[4] => ram_block1a25.PORTBADDR4 -address_b[4] => ram_block1a26.PORTBADDR4 -address_b[4] => ram_block1a27.PORTBADDR4 -address_b[4] => ram_block1a28.PORTBADDR4 -address_b[4] => ram_block1a29.PORTBADDR4 -address_b[4] => ram_block1a30.PORTBADDR4 -address_b[4] => ram_block1a31.PORTBADDR4 -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -data_a[0] => ram_block1a0.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -q_b[0] <= ram_block1a0.PORTBDATAOUT -q_b[1] <= ram_block1a1.PORTBDATAOUT -q_b[2] <= ram_block1a2.PORTBDATAOUT -q_b[3] <= ram_block1a3.PORTBDATAOUT -q_b[4] <= ram_block1a4.PORTBDATAOUT -q_b[5] <= ram_block1a5.PORTBDATAOUT -q_b[6] <= ram_block1a6.PORTBDATAOUT -q_b[7] <= ram_block1a7.PORTBDATAOUT -q_b[8] <= ram_block1a8.PORTBDATAOUT -q_b[9] <= ram_block1a9.PORTBDATAOUT -q_b[10] <= ram_block1a10.PORTBDATAOUT -q_b[11] <= ram_block1a11.PORTBDATAOUT -q_b[12] <= ram_block1a12.PORTBDATAOUT -q_b[13] <= ram_block1a13.PORTBDATAOUT -q_b[14] <= ram_block1a14.PORTBDATAOUT -q_b[15] <= ram_block1a15.PORTBDATAOUT -q_b[16] <= ram_block1a16.PORTBDATAOUT -q_b[17] <= ram_block1a17.PORTBDATAOUT -q_b[18] <= ram_block1a18.PORTBDATAOUT -q_b[19] <= ram_block1a19.PORTBDATAOUT -q_b[20] <= ram_block1a20.PORTBDATAOUT -q_b[21] <= ram_block1a21.PORTBDATAOUT -q_b[22] <= ram_block1a22.PORTBDATAOUT -q_b[23] <= ram_block1a23.PORTBDATAOUT -q_b[24] <= ram_block1a24.PORTBDATAOUT -q_b[25] <= ram_block1a25.PORTBDATAOUT -q_b[26] <= ram_block1a26.PORTBDATAOUT -q_b[27] <= ram_block1a27.PORTBDATAOUT -q_b[28] <= ram_block1a28.PORTBDATAOUT -q_b[29] <= ram_block1a29.PORTBDATAOUT -q_b[30] <= ram_block1a30.PORTBDATAOUT -q_b[31] <= ram_block1a31.PORTBDATAOUT -wren_a => ram_block1a0.PORTAWE -wren_a => ram_block1a1.PORTAWE -wren_a => ram_block1a2.PORTAWE -wren_a => ram_block1a3.PORTAWE -wren_a => ram_block1a4.PORTAWE -wren_a => ram_block1a5.PORTAWE -wren_a => ram_block1a6.PORTAWE -wren_a => ram_block1a7.PORTAWE -wren_a => ram_block1a8.PORTAWE -wren_a => ram_block1a9.PORTAWE -wren_a => ram_block1a10.PORTAWE -wren_a => ram_block1a11.PORTAWE -wren_a => ram_block1a12.PORTAWE -wren_a => ram_block1a13.PORTAWE -wren_a => ram_block1a14.PORTAWE -wren_a => ram_block1a15.PORTAWE -wren_a => ram_block1a16.PORTAWE -wren_a => ram_block1a17.PORTAWE -wren_a => ram_block1a18.PORTAWE -wren_a => ram_block1a19.PORTAWE -wren_a => ram_block1a20.PORTAWE -wren_a => ram_block1a21.PORTAWE -wren_a => ram_block1a22.PORTAWE -wren_a => ram_block1a23.PORTAWE -wren_a => ram_block1a24.PORTAWE -wren_a => ram_block1a25.PORTAWE -wren_a => ram_block1a26.PORTAWE -wren_a => ram_block1a27.PORTAWE -wren_a => ram_block1a28.PORTAWE -wren_a => ram_block1a29.PORTAWE -wren_a => ram_block1a30.PORTAWE -wren_a => ram_block1a31.PORTAWE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci -D_valid => D_valid.IN1 -E_st_data[0] => E_st_data[0].IN1 -E_st_data[1] => E_st_data[1].IN1 -E_st_data[2] => E_st_data[2].IN1 -E_st_data[3] => E_st_data[3].IN1 -E_st_data[4] => E_st_data[4].IN1 -E_st_data[5] => E_st_data[5].IN1 -E_st_data[6] => E_st_data[6].IN1 -E_st_data[7] => E_st_data[7].IN1 -E_st_data[8] => E_st_data[8].IN1 -E_st_data[9] => E_st_data[9].IN1 -E_st_data[10] => E_st_data[10].IN1 -E_st_data[11] => E_st_data[11].IN1 -E_st_data[12] => E_st_data[12].IN1 -E_st_data[13] => E_st_data[13].IN1 -E_st_data[14] => E_st_data[14].IN1 -E_st_data[15] => E_st_data[15].IN1 -E_st_data[16] => E_st_data[16].IN1 -E_st_data[17] => E_st_data[17].IN1 -E_st_data[18] => E_st_data[18].IN1 -E_st_data[19] => E_st_data[19].IN1 -E_st_data[20] => E_st_data[20].IN1 -E_st_data[21] => E_st_data[21].IN1 -E_st_data[22] => E_st_data[22].IN1 -E_st_data[23] => E_st_data[23].IN1 -E_st_data[24] => E_st_data[24].IN1 -E_st_data[25] => E_st_data[25].IN1 -E_st_data[26] => E_st_data[26].IN1 -E_st_data[27] => E_st_data[27].IN1 -E_st_data[28] => E_st_data[28].IN1 -E_st_data[29] => E_st_data[29].IN1 -E_st_data[30] => E_st_data[30].IN1 -E_st_data[31] => E_st_data[31].IN1 -E_valid => E_valid.IN1 -F_pc[0] => F_pc[0].IN1 -F_pc[1] => F_pc[1].IN1 -F_pc[2] => F_pc[2].IN1 -F_pc[3] => F_pc[3].IN1 -F_pc[4] => F_pc[4].IN1 -F_pc[5] => F_pc[5].IN1 -F_pc[6] => F_pc[6].IN1 -F_pc[7] => F_pc[7].IN1 -F_pc[8] => F_pc[8].IN1 -F_pc[9] => F_pc[9].IN1 -F_pc[10] => F_pc[10].IN1 -F_pc[11] => F_pc[11].IN1 -F_pc[12] => F_pc[12].IN1 -F_pc[13] => F_pc[13].IN1 -F_pc[14] => F_pc[14].IN1 -F_pc[15] => F_pc[15].IN1 -F_pc[16] => F_pc[16].IN1 -address_nxt[0] => address[0].DATAIN -address_nxt[1] => address[1].DATAIN -address_nxt[2] => address[2].DATAIN -address_nxt[3] => address[3].DATAIN -address_nxt[4] => address[4].DATAIN -address_nxt[5] => address[5].DATAIN -address_nxt[6] => address[6].DATAIN -address_nxt[7] => address[7].DATAIN -address_nxt[8] => address[8].DATAIN -av_ld_data_aligned_filtered[0] => av_ld_data_aligned_filtered[0].IN1 -av_ld_data_aligned_filtered[1] => av_ld_data_aligned_filtered[1].IN1 -av_ld_data_aligned_filtered[2] => av_ld_data_aligned_filtered[2].IN1 -av_ld_data_aligned_filtered[3] => av_ld_data_aligned_filtered[3].IN1 -av_ld_data_aligned_filtered[4] => av_ld_data_aligned_filtered[4].IN1 -av_ld_data_aligned_filtered[5] => av_ld_data_aligned_filtered[5].IN1 -av_ld_data_aligned_filtered[6] => av_ld_data_aligned_filtered[6].IN1 -av_ld_data_aligned_filtered[7] => av_ld_data_aligned_filtered[7].IN1 -av_ld_data_aligned_filtered[8] => av_ld_data_aligned_filtered[8].IN1 -av_ld_data_aligned_filtered[9] => av_ld_data_aligned_filtered[9].IN1 -av_ld_data_aligned_filtered[10] => av_ld_data_aligned_filtered[10].IN1 -av_ld_data_aligned_filtered[11] => av_ld_data_aligned_filtered[11].IN1 -av_ld_data_aligned_filtered[12] => av_ld_data_aligned_filtered[12].IN1 -av_ld_data_aligned_filtered[13] => av_ld_data_aligned_filtered[13].IN1 -av_ld_data_aligned_filtered[14] => av_ld_data_aligned_filtered[14].IN1 -av_ld_data_aligned_filtered[15] => av_ld_data_aligned_filtered[15].IN1 -av_ld_data_aligned_filtered[16] => av_ld_data_aligned_filtered[16].IN1 -av_ld_data_aligned_filtered[17] => av_ld_data_aligned_filtered[17].IN1 -av_ld_data_aligned_filtered[18] => av_ld_data_aligned_filtered[18].IN1 -av_ld_data_aligned_filtered[19] => av_ld_data_aligned_filtered[19].IN1 -av_ld_data_aligned_filtered[20] => av_ld_data_aligned_filtered[20].IN1 -av_ld_data_aligned_filtered[21] => av_ld_data_aligned_filtered[21].IN1 -av_ld_data_aligned_filtered[22] => av_ld_data_aligned_filtered[22].IN1 -av_ld_data_aligned_filtered[23] => av_ld_data_aligned_filtered[23].IN1 -av_ld_data_aligned_filtered[24] => av_ld_data_aligned_filtered[24].IN1 -av_ld_data_aligned_filtered[25] => av_ld_data_aligned_filtered[25].IN1 -av_ld_data_aligned_filtered[26] => av_ld_data_aligned_filtered[26].IN1 -av_ld_data_aligned_filtered[27] => av_ld_data_aligned_filtered[27].IN1 -av_ld_data_aligned_filtered[28] => av_ld_data_aligned_filtered[28].IN1 -av_ld_data_aligned_filtered[29] => av_ld_data_aligned_filtered[29].IN1 -av_ld_data_aligned_filtered[30] => av_ld_data_aligned_filtered[30].IN1 -av_ld_data_aligned_filtered[31] => av_ld_data_aligned_filtered[31].IN1 -byteenable_nxt[0] => byteenable[0].DATAIN -byteenable_nxt[1] => byteenable[1].DATAIN -byteenable_nxt[2] => byteenable[2].DATAIN -byteenable_nxt[3] => byteenable[3].DATAIN -clk => clk.IN12 -d_address[0] => d_address[0].IN1 -d_address[1] => d_address[1].IN1 -d_address[2] => d_address[2].IN1 -d_address[3] => d_address[3].IN1 -d_address[4] => d_address[4].IN1 -d_address[5] => d_address[5].IN1 -d_address[6] => d_address[6].IN1 -d_address[7] => d_address[7].IN1 -d_address[8] => d_address[8].IN1 -d_address[9] => d_address[9].IN1 -d_address[10] => d_address[10].IN1 -d_address[11] => d_address[11].IN1 -d_address[12] => d_address[12].IN1 -d_address[13] => d_address[13].IN1 -d_address[14] => d_address[14].IN1 -d_address[15] => d_address[15].IN1 -d_address[16] => d_address[16].IN1 -d_address[17] => d_address[17].IN1 -d_address[18] => d_address[18].IN1 -d_read => d_read.IN1 -d_waitrequest => d_waitrequest.IN1 -d_write => d_write.IN1 -debugaccess_nxt => debugaccess.DATAIN -hbreak_enabled => hbreak_enabled.IN1 -read_nxt => read.DATAA -reset => reset.IN1 -reset_n => reset_n.IN7 -test_ending => test_ending.IN1 -test_has_ended => test_has_ended.IN1 -write_nxt => write.DATAA -writedata_nxt[0] => writedata[0].DATAIN -writedata_nxt[1] => writedata[1].DATAIN -writedata_nxt[2] => writedata[2].DATAIN -writedata_nxt[3] => writedata[3].DATAIN -writedata_nxt[4] => writedata[4].DATAIN -writedata_nxt[5] => writedata[5].DATAIN -writedata_nxt[6] => writedata[6].DATAIN -writedata_nxt[7] => writedata[7].DATAIN -writedata_nxt[8] => writedata[8].DATAIN -writedata_nxt[9] => writedata[9].DATAIN -writedata_nxt[10] => writedata[10].DATAIN -writedata_nxt[11] => writedata[11].DATAIN -writedata_nxt[12] => writedata[12].DATAIN -writedata_nxt[13] => writedata[13].DATAIN -writedata_nxt[14] => writedata[14].DATAIN -writedata_nxt[15] => writedata[15].DATAIN -writedata_nxt[16] => writedata[16].DATAIN -writedata_nxt[17] => writedata[17].DATAIN -writedata_nxt[18] => writedata[18].DATAIN -writedata_nxt[19] => writedata[19].DATAIN -writedata_nxt[20] => writedata[20].DATAIN -writedata_nxt[21] => writedata[21].DATAIN -writedata_nxt[22] => writedata[22].DATAIN -writedata_nxt[23] => writedata[23].DATAIN -writedata_nxt[24] => writedata[24].DATAIN -writedata_nxt[25] => writedata[25].DATAIN -writedata_nxt[26] => writedata[26].DATAIN -writedata_nxt[27] => writedata[27].DATAIN -writedata_nxt[28] => writedata[28].DATAIN -writedata_nxt[29] => writedata[29].DATAIN -writedata_nxt[30] => writedata[30].DATAIN -writedata_nxt[31] => writedata[31].DATAIN -jtag_debug_module_debugaccess_to_roms <= debugack.DB_MAX_OUTPUT_PORT_TYPE -oci_hbreak_req <= nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug.oci_hbreak_req -oci_ienable[0] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[1] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[2] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[3] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[4] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[5] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[6] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[7] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[8] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[9] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[10] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[11] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[12] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[13] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[14] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[15] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[16] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[17] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[18] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[19] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[20] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[21] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[22] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[23] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[24] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[25] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[26] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[27] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[28] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[29] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[30] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_ienable[31] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable -oci_single_step_mode <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_single_step_mode -readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -resetrequest <= nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug.resetrequest -waitrequest <= nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem.waitrequest - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug -clk => clk.IN1 -dbrk_break => oci_hbreak_req.IN1 -debugreq => always0.IN0 -debugreq => oci_hbreak_req.IN1 -hbreak_enabled => always0.IN1 -hbreak_enabled => debugack.DATAIN -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => ~NO_FANOUT~ -jdo[4] => ~NO_FANOUT~ -jdo[5] => ~NO_FANOUT~ -jdo[6] => ~NO_FANOUT~ -jdo[7] => ~NO_FANOUT~ -jdo[8] => ~NO_FANOUT~ -jdo[9] => ~NO_FANOUT~ -jdo[10] => ~NO_FANOUT~ -jdo[11] => ~NO_FANOUT~ -jdo[12] => ~NO_FANOUT~ -jdo[13] => ~NO_FANOUT~ -jdo[14] => ~NO_FANOUT~ -jdo[15] => ~NO_FANOUT~ -jdo[16] => ~NO_FANOUT~ -jdo[17] => ~NO_FANOUT~ -jdo[18] => break_on_reset.OUTPUTSELECT -jdo[19] => break_on_reset.OUTPUTSELECT -jdo[20] => jtag_break.OUTPUTSELECT -jdo[21] => jtag_break.OUTPUTSELECT -jdo[22] => resetrequest~reg0.DATAIN -jdo[23] => always1.IN0 -jdo[24] => resetlatch.OUTPUTSELECT -jdo[25] => always1.IN0 -jdo[26] => ~NO_FANOUT~ -jdo[27] => ~NO_FANOUT~ -jdo[28] => ~NO_FANOUT~ -jdo[29] => ~NO_FANOUT~ -jdo[30] => ~NO_FANOUT~ -jdo[31] => ~NO_FANOUT~ -jdo[32] => ~NO_FANOUT~ -jdo[33] => ~NO_FANOUT~ -jdo[34] => ~NO_FANOUT~ -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => unxcomplemented_resetxx0.IN1 -ocireg_ers => always1.IN0 -ocireg_mrs => always1.IN0 -reset => reset.IN1 -st_ready_test_idle => monitor_go.OUTPUTSELECT -take_action_ocimem_a => jtag_break.OUTPUTSELECT -take_action_ocimem_a => resetlatch.OUTPUTSELECT -take_action_ocimem_a => always1.IN1 -take_action_ocimem_a => always1.IN1 -take_action_ocimem_a => break_on_reset.ENA -take_action_ocimem_a => resetrequest~reg0.ENA -take_action_ocireg => always1.IN1 -take_action_ocireg => always1.IN1 -xbrk_break => oci_hbreak_req.IN1 -debugack <= hbreak_enabled.DB_MAX_OUTPUT_PORT_TYPE -monitor_error <= monitor_error~reg0.DB_MAX_OUTPUT_PORT_TYPE -monitor_go <= monitor_go~reg0.DB_MAX_OUTPUT_PORT_TYPE -monitor_ready <= monitor_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_hbreak_req <= oci_hbreak_req.DB_MAX_OUTPUT_PORT_TYPE -resetlatch <= resetlatch~reg0.DB_MAX_OUTPUT_PORT_TYPE -resetrequest <= resetrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem -address[0] => ociram_addr.DATAA -address[1] => ociram_addr.DATAA -address[2] => ociram_addr.DATAA -address[3] => ociram_addr.DATAA -address[4] => ociram_addr.DATAA -address[5] => ociram_addr.DATAA -address[6] => ociram_addr.DATAA -address[7] => ociram_addr.DATAA -address[8] => waitrequest.IN1 -address[8] => avalon_ram_wr.IN0 -byteenable[0] => ociram_byteenable.DATAA -byteenable[1] => ociram_byteenable.DATAA -byteenable[2] => ociram_byteenable.DATAA -byteenable[3] => ociram_byteenable.DATAA -clk => clk.IN1 -debugaccess => avalon_ram_wr.IN1 -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => MonDReg.DATAB -jdo[4] => MonDReg.DATAB -jdo[5] => MonDReg.DATAB -jdo[6] => MonDReg.DATAB -jdo[7] => MonDReg.DATAB -jdo[8] => MonDReg.DATAB -jdo[9] => MonDReg.DATAB -jdo[10] => MonDReg.DATAB -jdo[11] => MonDReg.DATAB -jdo[12] => MonDReg.DATAB -jdo[13] => MonDReg.DATAB -jdo[14] => MonDReg.DATAB -jdo[15] => MonDReg.DATAB -jdo[16] => MonDReg.DATAB -jdo[17] => MonDReg.DATAB -jdo[17] => MonAReg.DATAB -jdo[17] => jtag_ram_rd.DATAB -jdo[17] => jtag_ram_access.DATAB -jdo[18] => MonDReg.DATAB -jdo[19] => MonDReg.DATAB -jdo[20] => MonDReg.DATAB -jdo[21] => MonDReg.DATAB -jdo[22] => MonDReg.DATAB -jdo[23] => MonDReg.DATAB -jdo[24] => MonDReg.DATAB -jdo[25] => MonDReg.DATAB -jdo[26] => MonDReg.DATAB -jdo[26] => MonAReg.DATAB -jdo[27] => MonDReg.DATAB -jdo[27] => MonAReg.DATAB -jdo[28] => MonDReg.DATAB -jdo[28] => MonAReg.DATAB -jdo[29] => MonDReg.DATAB -jdo[29] => MonAReg.DATAB -jdo[30] => MonDReg.DATAB -jdo[30] => MonAReg.DATAB -jdo[31] => MonDReg.DATAB -jdo[31] => MonAReg.DATAB -jdo[32] => MonDReg.DATAB -jdo[32] => MonAReg.DATAB -jdo[33] => MonDReg.DATAB -jdo[33] => MonAReg.DATAB -jdo[34] => MonDReg.DATAB -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => avalon_ociram_readdata_ready.ACLR -jrst_n => waitrequest~reg0.PRESET -jrst_n => MonDReg[0]~reg0.ACLR -jrst_n => MonDReg[1]~reg0.ACLR -jrst_n => MonDReg[2]~reg0.ACLR -jrst_n => MonDReg[3]~reg0.ACLR -jrst_n => MonDReg[4]~reg0.ACLR -jrst_n => MonDReg[5]~reg0.ACLR -jrst_n => MonDReg[6]~reg0.ACLR -jrst_n => MonDReg[7]~reg0.ACLR -jrst_n => MonDReg[8]~reg0.ACLR -jrst_n => MonDReg[9]~reg0.ACLR -jrst_n => MonDReg[10]~reg0.ACLR -jrst_n => MonDReg[11]~reg0.ACLR -jrst_n => MonDReg[12]~reg0.ACLR -jrst_n => MonDReg[13]~reg0.ACLR -jrst_n => MonDReg[14]~reg0.ACLR -jrst_n => MonDReg[15]~reg0.ACLR -jrst_n => MonDReg[16]~reg0.ACLR -jrst_n => MonDReg[17]~reg0.ACLR -jrst_n => MonDReg[18]~reg0.ACLR -jrst_n => MonDReg[19]~reg0.ACLR -jrst_n => MonDReg[20]~reg0.ACLR -jrst_n => MonDReg[21]~reg0.ACLR -jrst_n => MonDReg[22]~reg0.ACLR -jrst_n => MonDReg[23]~reg0.ACLR -jrst_n => MonDReg[24]~reg0.ACLR -jrst_n => MonDReg[25]~reg0.ACLR -jrst_n => MonDReg[26]~reg0.ACLR -jrst_n => MonDReg[27]~reg0.ACLR -jrst_n => MonDReg[28]~reg0.ACLR -jrst_n => MonDReg[29]~reg0.ACLR -jrst_n => MonDReg[30]~reg0.ACLR -jrst_n => MonDReg[31]~reg0.ACLR -jrst_n => MonAReg[2].ACLR -jrst_n => MonAReg[3].ACLR -jrst_n => MonAReg[4].ACLR -jrst_n => MonAReg[5].ACLR -jrst_n => MonAReg[6].ACLR -jrst_n => MonAReg[7].ACLR -jrst_n => MonAReg[8].ACLR -jrst_n => MonAReg[9].ACLR -jrst_n => MonAReg[10].ACLR -jrst_n => jtag_ram_access.ACLR -jrst_n => jtag_ram_rd_d1.ACLR -jrst_n => jtag_ram_rd.ACLR -jrst_n => jtag_ram_wr.ACLR -jrst_n => jtag_rd_d1.ACLR -jrst_n => jtag_rd.ACLR -read => avalon_ociram_readdata_ready.OUTPUTSELECT -read => waitrequest.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => MonAReg.OUTPUTSELECT -take_action_ocimem_a => jtag_rd.OUTPUTSELECT -take_action_ocimem_a => jtag_ram_rd.OUTPUTSELECT -take_action_ocimem_a => jtag_ram_access.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => MonDReg.OUTPUTSELECT -take_action_ocimem_a => jtag_ram_wr.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonAReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => MonDReg.OUTPUTSELECT -take_action_ocimem_b => jtag_ram_wr.OUTPUTSELECT -take_action_ocimem_b => jtag_rd.OUTPUTSELECT -take_action_ocimem_b => jtag_ram_rd.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => MonAReg.OUTPUTSELECT -take_no_action_ocimem_a => jtag_rd.OUTPUTSELECT -take_no_action_ocimem_a => jtag_ram_rd.OUTPUTSELECT -take_no_action_ocimem_a => jtag_ram_access.OUTPUTSELECT -take_no_action_ocimem_a => jtag_ram_wr.ENA -take_no_action_ocimem_a => MonDReg[31]~reg0.ENA -take_no_action_ocimem_a => MonDReg[30]~reg0.ENA -take_no_action_ocimem_a => MonDReg[29]~reg0.ENA -take_no_action_ocimem_a => MonDReg[28]~reg0.ENA -take_no_action_ocimem_a => MonDReg[27]~reg0.ENA -take_no_action_ocimem_a => MonDReg[26]~reg0.ENA -take_no_action_ocimem_a => MonDReg[25]~reg0.ENA -take_no_action_ocimem_a => MonDReg[24]~reg0.ENA -take_no_action_ocimem_a => MonDReg[23]~reg0.ENA -take_no_action_ocimem_a => MonDReg[22]~reg0.ENA -take_no_action_ocimem_a => MonDReg[21]~reg0.ENA -take_no_action_ocimem_a => MonDReg[20]~reg0.ENA -take_no_action_ocimem_a => MonDReg[19]~reg0.ENA -take_no_action_ocimem_a => MonDReg[18]~reg0.ENA -take_no_action_ocimem_a => MonDReg[17]~reg0.ENA -take_no_action_ocimem_a => MonDReg[16]~reg0.ENA -take_no_action_ocimem_a => MonDReg[15]~reg0.ENA -take_no_action_ocimem_a => MonDReg[14]~reg0.ENA -take_no_action_ocimem_a => MonDReg[13]~reg0.ENA -take_no_action_ocimem_a => MonDReg[12]~reg0.ENA -take_no_action_ocimem_a => MonDReg[11]~reg0.ENA -take_no_action_ocimem_a => MonDReg[10]~reg0.ENA -take_no_action_ocimem_a => MonDReg[9]~reg0.ENA -take_no_action_ocimem_a => MonDReg[8]~reg0.ENA -take_no_action_ocimem_a => MonDReg[7]~reg0.ENA -take_no_action_ocimem_a => MonDReg[6]~reg0.ENA -take_no_action_ocimem_a => MonDReg[5]~reg0.ENA -take_no_action_ocimem_a => MonDReg[4]~reg0.ENA -take_no_action_ocimem_a => MonDReg[3]~reg0.ENA -take_no_action_ocimem_a => MonDReg[2]~reg0.ENA -take_no_action_ocimem_a => MonDReg[1]~reg0.ENA -take_no_action_ocimem_a => MonDReg[0]~reg0.ENA -write => waitrequest.OUTPUTSELECT -write => avalon_ociram_readdata_ready.OUTPUTSELECT -write => avalon_ram_wr.IN1 -writedata[0] => ociram_wr_data.DATAA -writedata[1] => ociram_wr_data.DATAA -writedata[2] => ociram_wr_data.DATAA -writedata[3] => ociram_wr_data.DATAA -writedata[4] => ociram_wr_data.DATAA -writedata[5] => ociram_wr_data.DATAA -writedata[6] => ociram_wr_data.DATAA -writedata[7] => ociram_wr_data.DATAA -writedata[8] => ociram_wr_data.DATAA -writedata[9] => ociram_wr_data.DATAA -writedata[10] => ociram_wr_data.DATAA -writedata[11] => ociram_wr_data.DATAA -writedata[12] => ociram_wr_data.DATAA -writedata[13] => ociram_wr_data.DATAA -writedata[14] => ociram_wr_data.DATAA -writedata[15] => ociram_wr_data.DATAA -writedata[16] => ociram_wr_data.DATAA -writedata[17] => ociram_wr_data.DATAA -writedata[18] => ociram_wr_data.DATAA -writedata[19] => ociram_wr_data.DATAA -writedata[20] => ociram_wr_data.DATAA -writedata[21] => ociram_wr_data.DATAA -writedata[22] => ociram_wr_data.DATAA -writedata[23] => ociram_wr_data.DATAA -writedata[24] => ociram_wr_data.DATAA -writedata[25] => ociram_wr_data.DATAA -writedata[26] => ociram_wr_data.DATAA -writedata[27] => ociram_wr_data.DATAA -writedata[28] => ociram_wr_data.DATAA -writedata[29] => ociram_wr_data.DATAA -writedata[30] => ociram_wr_data.DATAA -writedata[31] => ociram_wr_data.DATAA -MonDReg[0] <= MonDReg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[1] <= MonDReg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[2] <= MonDReg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[3] <= MonDReg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[4] <= MonDReg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[5] <= MonDReg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[6] <= MonDReg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[7] <= MonDReg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[8] <= MonDReg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[9] <= MonDReg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[10] <= MonDReg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[11] <= MonDReg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[12] <= MonDReg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[13] <= MonDReg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[14] <= MonDReg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[15] <= MonDReg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[16] <= MonDReg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[17] <= MonDReg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[18] <= MonDReg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[19] <= MonDReg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[20] <= MonDReg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[21] <= MonDReg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[22] <= MonDReg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[23] <= MonDReg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[24] <= MonDReg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[25] <= MonDReg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[26] <= MonDReg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[27] <= MonDReg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[28] <= MonDReg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[29] <= MonDReg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[30] <= MonDReg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -MonDReg[31] <= MonDReg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -ociram_readdata[0] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[1] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[2] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[3] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[4] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[5] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[6] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[7] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[8] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[9] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[10] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[11] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[12] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[13] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[14] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[15] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[16] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[17] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[18] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[19] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[20] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[21] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[22] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[23] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[24] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[25] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[26] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[27] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[28] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[29] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[30] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -ociram_readdata[31] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q -waitrequest <= waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram -address[0] => address[0].IN1 -address[1] => address[1].IN1 -address[2] => address[2].IN1 -address[3] => address[3].IN1 -address[4] => address[4].IN1 -address[5] => address[5].IN1 -address[6] => address[6].IN1 -address[7] => address[7].IN1 -byteenable[0] => byteenable[0].IN1 -byteenable[1] => byteenable[1].IN1 -byteenable[2] => byteenable[2].IN1 -byteenable[3] => byteenable[3].IN1 -clock => clock.IN1 -data[0] => data[0].IN1 -data[1] => data[1].IN1 -data[2] => data[2].IN1 -data[3] => data[3].IN1 -data[4] => data[4].IN1 -data[5] => data[5].IN1 -data[6] => data[6].IN1 -data[7] => data[7].IN1 -data[8] => data[8].IN1 -data[9] => data[9].IN1 -data[10] => data[10].IN1 -data[11] => data[11].IN1 -data[12] => data[12].IN1 -data[13] => data[13].IN1 -data[14] => data[14].IN1 -data[15] => data[15].IN1 -data[16] => data[16].IN1 -data[17] => data[17].IN1 -data[18] => data[18].IN1 -data[19] => data[19].IN1 -data[20] => data[20].IN1 -data[21] => data[21].IN1 -data[22] => data[22].IN1 -data[23] => data[23].IN1 -data[24] => data[24].IN1 -data[25] => data[25].IN1 -data[26] => data[26].IN1 -data[27] => data[27].IN1 -data[28] => data[28].IN1 -data[29] => data[29].IN1 -data[30] => data[30].IN1 -data[31] => data[31].IN1 -wren => wren.IN1 -q[0] <= altsyncram:the_altsyncram.q_a -q[1] <= altsyncram:the_altsyncram.q_a -q[2] <= altsyncram:the_altsyncram.q_a -q[3] <= altsyncram:the_altsyncram.q_a -q[4] <= altsyncram:the_altsyncram.q_a -q[5] <= altsyncram:the_altsyncram.q_a -q[6] <= altsyncram:the_altsyncram.q_a -q[7] <= altsyncram:the_altsyncram.q_a -q[8] <= altsyncram:the_altsyncram.q_a -q[9] <= altsyncram:the_altsyncram.q_a -q[10] <= altsyncram:the_altsyncram.q_a -q[11] <= altsyncram:the_altsyncram.q_a -q[12] <= altsyncram:the_altsyncram.q_a -q[13] <= altsyncram:the_altsyncram.q_a -q[14] <= altsyncram:the_altsyncram.q_a -q[15] <= altsyncram:the_altsyncram.q_a -q[16] <= altsyncram:the_altsyncram.q_a -q[17] <= altsyncram:the_altsyncram.q_a -q[18] <= altsyncram:the_altsyncram.q_a -q[19] <= altsyncram:the_altsyncram.q_a -q[20] <= altsyncram:the_altsyncram.q_a -q[21] <= altsyncram:the_altsyncram.q_a -q[22] <= altsyncram:the_altsyncram.q_a -q[23] <= altsyncram:the_altsyncram.q_a -q[24] <= altsyncram:the_altsyncram.q_a -q[25] <= altsyncram:the_altsyncram.q_a -q[26] <= altsyncram:the_altsyncram.q_a -q[27] <= altsyncram:the_altsyncram.q_a -q[28] <= altsyncram:the_altsyncram.q_a -q[29] <= altsyncram:the_altsyncram.q_a -q[30] <= altsyncram:the_altsyncram.q_a -q[31] <= altsyncram:the_altsyncram.q_a - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram -wren_a => altsyncram_4891:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_4891:auto_generated.data_a[0] -data_a[1] => altsyncram_4891:auto_generated.data_a[1] -data_a[2] => altsyncram_4891:auto_generated.data_a[2] -data_a[3] => altsyncram_4891:auto_generated.data_a[3] -data_a[4] => altsyncram_4891:auto_generated.data_a[4] -data_a[5] => altsyncram_4891:auto_generated.data_a[5] -data_a[6] => altsyncram_4891:auto_generated.data_a[6] -data_a[7] => altsyncram_4891:auto_generated.data_a[7] -data_a[8] => altsyncram_4891:auto_generated.data_a[8] -data_a[9] => altsyncram_4891:auto_generated.data_a[9] -data_a[10] => altsyncram_4891:auto_generated.data_a[10] -data_a[11] => altsyncram_4891:auto_generated.data_a[11] -data_a[12] => altsyncram_4891:auto_generated.data_a[12] -data_a[13] => altsyncram_4891:auto_generated.data_a[13] -data_a[14] => altsyncram_4891:auto_generated.data_a[14] -data_a[15] => altsyncram_4891:auto_generated.data_a[15] -data_a[16] => altsyncram_4891:auto_generated.data_a[16] -data_a[17] => altsyncram_4891:auto_generated.data_a[17] -data_a[18] => altsyncram_4891:auto_generated.data_a[18] -data_a[19] => altsyncram_4891:auto_generated.data_a[19] -data_a[20] => altsyncram_4891:auto_generated.data_a[20] -data_a[21] => altsyncram_4891:auto_generated.data_a[21] -data_a[22] => altsyncram_4891:auto_generated.data_a[22] -data_a[23] => altsyncram_4891:auto_generated.data_a[23] -data_a[24] => altsyncram_4891:auto_generated.data_a[24] -data_a[25] => altsyncram_4891:auto_generated.data_a[25] -data_a[26] => altsyncram_4891:auto_generated.data_a[26] -data_a[27] => altsyncram_4891:auto_generated.data_a[27] -data_a[28] => altsyncram_4891:auto_generated.data_a[28] -data_a[29] => altsyncram_4891:auto_generated.data_a[29] -data_a[30] => altsyncram_4891:auto_generated.data_a[30] -data_a[31] => altsyncram_4891:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -address_a[0] => altsyncram_4891:auto_generated.address_a[0] -address_a[1] => altsyncram_4891:auto_generated.address_a[1] -address_a[2] => altsyncram_4891:auto_generated.address_a[2] -address_a[3] => altsyncram_4891:auto_generated.address_a[3] -address_a[4] => altsyncram_4891:auto_generated.address_a[4] -address_a[5] => altsyncram_4891:auto_generated.address_a[5] -address_a[6] => altsyncram_4891:auto_generated.address_a[6] -address_a[7] => altsyncram_4891:auto_generated.address_a[7] -address_b[0] => ~NO_FANOUT~ -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_4891:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => ~NO_FANOUT~ -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => altsyncram_4891:auto_generated.byteena_a[0] -byteena_a[1] => altsyncram_4891:auto_generated.byteena_a[1] -byteena_a[2] => altsyncram_4891:auto_generated.byteena_a[2] -byteena_a[3] => altsyncram_4891:auto_generated.byteena_a[3] -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= altsyncram_4891:auto_generated.q_a[0] -q_a[1] <= altsyncram_4891:auto_generated.q_a[1] -q_a[2] <= altsyncram_4891:auto_generated.q_a[2] -q_a[3] <= altsyncram_4891:auto_generated.q_a[3] -q_a[4] <= altsyncram_4891:auto_generated.q_a[4] -q_a[5] <= altsyncram_4891:auto_generated.q_a[5] -q_a[6] <= altsyncram_4891:auto_generated.q_a[6] -q_a[7] <= altsyncram_4891:auto_generated.q_a[7] -q_a[8] <= altsyncram_4891:auto_generated.q_a[8] -q_a[9] <= altsyncram_4891:auto_generated.q_a[9] -q_a[10] <= altsyncram_4891:auto_generated.q_a[10] -q_a[11] <= altsyncram_4891:auto_generated.q_a[11] -q_a[12] <= altsyncram_4891:auto_generated.q_a[12] -q_a[13] <= altsyncram_4891:auto_generated.q_a[13] -q_a[14] <= altsyncram_4891:auto_generated.q_a[14] -q_a[15] <= altsyncram_4891:auto_generated.q_a[15] -q_a[16] <= altsyncram_4891:auto_generated.q_a[16] -q_a[17] <= altsyncram_4891:auto_generated.q_a[17] -q_a[18] <= altsyncram_4891:auto_generated.q_a[18] -q_a[19] <= altsyncram_4891:auto_generated.q_a[19] -q_a[20] <= altsyncram_4891:auto_generated.q_a[20] -q_a[21] <= altsyncram_4891:auto_generated.q_a[21] -q_a[22] <= altsyncram_4891:auto_generated.q_a[22] -q_a[23] <= altsyncram_4891:auto_generated.q_a[23] -q_a[24] <= altsyncram_4891:auto_generated.q_a[24] -q_a[25] <= altsyncram_4891:auto_generated.q_a[25] -q_a[26] <= altsyncram_4891:auto_generated.q_a[26] -q_a[27] <= altsyncram_4891:auto_generated.q_a[27] -q_a[28] <= altsyncram_4891:auto_generated.q_a[28] -q_a[29] <= altsyncram_4891:auto_generated.q_a[29] -q_a[30] <= altsyncram_4891:auto_generated.q_a[30] -q_a[31] <= altsyncram_4891:auto_generated.q_a[31] -q_b[0] <= -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_a[5] => ram_block1a0.PORTAADDR5 -address_a[5] => ram_block1a1.PORTAADDR5 -address_a[5] => ram_block1a2.PORTAADDR5 -address_a[5] => ram_block1a3.PORTAADDR5 -address_a[5] => ram_block1a4.PORTAADDR5 -address_a[5] => ram_block1a5.PORTAADDR5 -address_a[5] => ram_block1a6.PORTAADDR5 -address_a[5] => ram_block1a7.PORTAADDR5 -address_a[5] => ram_block1a8.PORTAADDR5 -address_a[5] => ram_block1a9.PORTAADDR5 -address_a[5] => ram_block1a10.PORTAADDR5 -address_a[5] => ram_block1a11.PORTAADDR5 -address_a[5] => ram_block1a12.PORTAADDR5 -address_a[5] => ram_block1a13.PORTAADDR5 -address_a[5] => ram_block1a14.PORTAADDR5 -address_a[5] => ram_block1a15.PORTAADDR5 -address_a[5] => ram_block1a16.PORTAADDR5 -address_a[5] => ram_block1a17.PORTAADDR5 -address_a[5] => ram_block1a18.PORTAADDR5 -address_a[5] => ram_block1a19.PORTAADDR5 -address_a[5] => ram_block1a20.PORTAADDR5 -address_a[5] => ram_block1a21.PORTAADDR5 -address_a[5] => ram_block1a22.PORTAADDR5 -address_a[5] => ram_block1a23.PORTAADDR5 -address_a[5] => ram_block1a24.PORTAADDR5 -address_a[5] => ram_block1a25.PORTAADDR5 -address_a[5] => ram_block1a26.PORTAADDR5 -address_a[5] => ram_block1a27.PORTAADDR5 -address_a[5] => ram_block1a28.PORTAADDR5 -address_a[5] => ram_block1a29.PORTAADDR5 -address_a[5] => ram_block1a30.PORTAADDR5 -address_a[5] => ram_block1a31.PORTAADDR5 -address_a[6] => ram_block1a0.PORTAADDR6 -address_a[6] => ram_block1a1.PORTAADDR6 -address_a[6] => ram_block1a2.PORTAADDR6 -address_a[6] => ram_block1a3.PORTAADDR6 -address_a[6] => ram_block1a4.PORTAADDR6 -address_a[6] => ram_block1a5.PORTAADDR6 -address_a[6] => ram_block1a6.PORTAADDR6 -address_a[6] => ram_block1a7.PORTAADDR6 -address_a[6] => ram_block1a8.PORTAADDR6 -address_a[6] => ram_block1a9.PORTAADDR6 -address_a[6] => ram_block1a10.PORTAADDR6 -address_a[6] => ram_block1a11.PORTAADDR6 -address_a[6] => ram_block1a12.PORTAADDR6 -address_a[6] => ram_block1a13.PORTAADDR6 -address_a[6] => ram_block1a14.PORTAADDR6 -address_a[6] => ram_block1a15.PORTAADDR6 -address_a[6] => ram_block1a16.PORTAADDR6 -address_a[6] => ram_block1a17.PORTAADDR6 -address_a[6] => ram_block1a18.PORTAADDR6 -address_a[6] => ram_block1a19.PORTAADDR6 -address_a[6] => ram_block1a20.PORTAADDR6 -address_a[6] => ram_block1a21.PORTAADDR6 -address_a[6] => ram_block1a22.PORTAADDR6 -address_a[6] => ram_block1a23.PORTAADDR6 -address_a[6] => ram_block1a24.PORTAADDR6 -address_a[6] => ram_block1a25.PORTAADDR6 -address_a[6] => ram_block1a26.PORTAADDR6 -address_a[6] => ram_block1a27.PORTAADDR6 -address_a[6] => ram_block1a28.PORTAADDR6 -address_a[6] => ram_block1a29.PORTAADDR6 -address_a[6] => ram_block1a30.PORTAADDR6 -address_a[6] => ram_block1a31.PORTAADDR6 -address_a[7] => ram_block1a0.PORTAADDR7 -address_a[7] => ram_block1a1.PORTAADDR7 -address_a[7] => ram_block1a2.PORTAADDR7 -address_a[7] => ram_block1a3.PORTAADDR7 -address_a[7] => ram_block1a4.PORTAADDR7 -address_a[7] => ram_block1a5.PORTAADDR7 -address_a[7] => ram_block1a6.PORTAADDR7 -address_a[7] => ram_block1a7.PORTAADDR7 -address_a[7] => ram_block1a8.PORTAADDR7 -address_a[7] => ram_block1a9.PORTAADDR7 -address_a[7] => ram_block1a10.PORTAADDR7 -address_a[7] => ram_block1a11.PORTAADDR7 -address_a[7] => ram_block1a12.PORTAADDR7 -address_a[7] => ram_block1a13.PORTAADDR7 -address_a[7] => ram_block1a14.PORTAADDR7 -address_a[7] => ram_block1a15.PORTAADDR7 -address_a[7] => ram_block1a16.PORTAADDR7 -address_a[7] => ram_block1a17.PORTAADDR7 -address_a[7] => ram_block1a18.PORTAADDR7 -address_a[7] => ram_block1a19.PORTAADDR7 -address_a[7] => ram_block1a20.PORTAADDR7 -address_a[7] => ram_block1a21.PORTAADDR7 -address_a[7] => ram_block1a22.PORTAADDR7 -address_a[7] => ram_block1a23.PORTAADDR7 -address_a[7] => ram_block1a24.PORTAADDR7 -address_a[7] => ram_block1a25.PORTAADDR7 -address_a[7] => ram_block1a26.PORTAADDR7 -address_a[7] => ram_block1a27.PORTAADDR7 -address_a[7] => ram_block1a28.PORTAADDR7 -address_a[7] => ram_block1a29.PORTAADDR7 -address_a[7] => ram_block1a30.PORTAADDR7 -address_a[7] => ram_block1a31.PORTAADDR7 -byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -data_a[0] => ram_block1a0.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -q_a[0] <= ram_block1a0.PORTADATAOUT -q_a[1] <= ram_block1a1.PORTADATAOUT -q_a[2] <= ram_block1a2.PORTADATAOUT -q_a[3] <= ram_block1a3.PORTADATAOUT -q_a[4] <= ram_block1a4.PORTADATAOUT -q_a[5] <= ram_block1a5.PORTADATAOUT -q_a[6] <= ram_block1a6.PORTADATAOUT -q_a[7] <= ram_block1a7.PORTADATAOUT -q_a[8] <= ram_block1a8.PORTADATAOUT -q_a[9] <= ram_block1a9.PORTADATAOUT -q_a[10] <= ram_block1a10.PORTADATAOUT -q_a[11] <= ram_block1a11.PORTADATAOUT -q_a[12] <= ram_block1a12.PORTADATAOUT -q_a[13] <= ram_block1a13.PORTADATAOUT -q_a[14] <= ram_block1a14.PORTADATAOUT -q_a[15] <= ram_block1a15.PORTADATAOUT -q_a[16] <= ram_block1a16.PORTADATAOUT -q_a[17] <= ram_block1a17.PORTADATAOUT -q_a[18] <= ram_block1a18.PORTADATAOUT -q_a[19] <= ram_block1a19.PORTADATAOUT -q_a[20] <= ram_block1a20.PORTADATAOUT -q_a[21] <= ram_block1a21.PORTADATAOUT -q_a[22] <= ram_block1a22.PORTADATAOUT -q_a[23] <= ram_block1a23.PORTADATAOUT -q_a[24] <= ram_block1a24.PORTADATAOUT -q_a[25] <= ram_block1a25.PORTADATAOUT -q_a[26] <= ram_block1a26.PORTADATAOUT -q_a[27] <= ram_block1a27.PORTADATAOUT -q_a[28] <= ram_block1a28.PORTADATAOUT -q_a[29] <= ram_block1a29.PORTADATAOUT -q_a[30] <= ram_block1a30.PORTADATAOUT -q_a[31] <= ram_block1a31.PORTADATAOUT -wren_a => ram_block1a0.PORTAWE -wren_a => ram_block1a1.PORTAWE -wren_a => ram_block1a2.PORTAWE -wren_a => ram_block1a3.PORTAWE -wren_a => ram_block1a4.PORTAWE -wren_a => ram_block1a5.PORTAWE -wren_a => ram_block1a6.PORTAWE -wren_a => ram_block1a7.PORTAWE -wren_a => ram_block1a8.PORTAWE -wren_a => ram_block1a9.PORTAWE -wren_a => ram_block1a10.PORTAWE -wren_a => ram_block1a11.PORTAWE -wren_a => ram_block1a12.PORTAWE -wren_a => ram_block1a13.PORTAWE -wren_a => ram_block1a14.PORTAWE -wren_a => ram_block1a15.PORTAWE -wren_a => ram_block1a16.PORTAWE -wren_a => ram_block1a17.PORTAWE -wren_a => ram_block1a18.PORTAWE -wren_a => ram_block1a19.PORTAWE -wren_a => ram_block1a20.PORTAWE -wren_a => ram_block1a21.PORTAWE -wren_a => ram_block1a22.PORTAWE -wren_a => ram_block1a23.PORTAWE -wren_a => ram_block1a24.PORTAWE -wren_a => ram_block1a25.PORTAWE -wren_a => ram_block1a26.PORTAWE -wren_a => ram_block1a27.PORTAWE -wren_a => ram_block1a28.PORTAWE -wren_a => ram_block1a29.PORTAWE -wren_a => ram_block1a30.PORTAWE -wren_a => ram_block1a31.PORTAWE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg -address[0] => Equal0.IN8 -address[0] => Equal1.IN1 -address[1] => Equal0.IN7 -address[1] => Equal1.IN8 -address[2] => Equal0.IN6 -address[2] => Equal1.IN7 -address[3] => Equal0.IN5 -address[3] => Equal1.IN6 -address[4] => Equal0.IN4 -address[4] => Equal1.IN5 -address[5] => Equal0.IN3 -address[5] => Equal1.IN4 -address[6] => Equal0.IN2 -address[6] => Equal1.IN3 -address[7] => Equal0.IN1 -address[7] => Equal1.IN2 -address[8] => Equal0.IN0 -address[8] => Equal1.IN0 -clk => oci_ienable[0]~reg0.CLK -clk => oci_ienable[1]~reg0.CLK -clk => oci_ienable[2]~reg0.CLK -clk => oci_ienable[3]~reg0.CLK -clk => oci_ienable[4]~reg0.CLK -clk => oci_ienable[5]~reg0.CLK -clk => oci_ienable[6]~reg0.CLK -clk => oci_ienable[7]~reg0.CLK -clk => oci_ienable[8]~reg0.CLK -clk => oci_ienable[9]~reg0.CLK -clk => oci_ienable[10]~reg0.CLK -clk => oci_ienable[11]~reg0.CLK -clk => oci_ienable[12]~reg0.CLK -clk => oci_ienable[13]~reg0.CLK -clk => oci_ienable[14]~reg0.CLK -clk => oci_ienable[15]~reg0.CLK -clk => oci_ienable[16]~reg0.CLK -clk => oci_ienable[17]~reg0.CLK -clk => oci_ienable[18]~reg0.CLK -clk => oci_ienable[19]~reg0.CLK -clk => oci_ienable[20]~reg0.CLK -clk => oci_ienable[21]~reg0.CLK -clk => oci_ienable[22]~reg0.CLK -clk => oci_ienable[23]~reg0.CLK -clk => oci_ienable[24]~reg0.CLK -clk => oci_ienable[25]~reg0.CLK -clk => oci_ienable[26]~reg0.CLK -clk => oci_ienable[27]~reg0.CLK -clk => oci_ienable[28]~reg0.CLK -clk => oci_ienable[29]~reg0.CLK -clk => oci_ienable[30]~reg0.CLK -clk => oci_ienable[31]~reg0.CLK -clk => oci_single_step_mode~reg0.CLK -debugaccess => write_strobe.IN0 -monitor_error => oci_reg_readdata.DATAB -monitor_go => oci_reg_readdata.DATAB -monitor_ready => oci_reg_readdata.DATAB -reset_n => oci_ienable[0]~reg0.ACLR -reset_n => oci_ienable[1]~reg0.ACLR -reset_n => oci_ienable[2]~reg0.ACLR -reset_n => oci_ienable[3]~reg0.ACLR -reset_n => oci_ienable[4]~reg0.ACLR -reset_n => oci_ienable[5]~reg0.PRESET -reset_n => oci_ienable[6]~reg0.ACLR -reset_n => oci_ienable[7]~reg0.ACLR -reset_n => oci_ienable[8]~reg0.ACLR -reset_n => oci_ienable[9]~reg0.ACLR -reset_n => oci_ienable[10]~reg0.ACLR -reset_n => oci_ienable[11]~reg0.ACLR -reset_n => oci_ienable[12]~reg0.ACLR -reset_n => oci_ienable[13]~reg0.ACLR -reset_n => oci_ienable[14]~reg0.ACLR -reset_n => oci_ienable[15]~reg0.ACLR -reset_n => oci_ienable[16]~reg0.ACLR -reset_n => oci_ienable[17]~reg0.ACLR -reset_n => oci_ienable[18]~reg0.ACLR -reset_n => oci_ienable[19]~reg0.ACLR -reset_n => oci_ienable[20]~reg0.ACLR -reset_n => oci_ienable[21]~reg0.ACLR -reset_n => oci_ienable[22]~reg0.ACLR -reset_n => oci_ienable[23]~reg0.ACLR -reset_n => oci_ienable[24]~reg0.ACLR -reset_n => oci_ienable[25]~reg0.ACLR -reset_n => oci_ienable[26]~reg0.ACLR -reset_n => oci_ienable[27]~reg0.ACLR -reset_n => oci_ienable[28]~reg0.ACLR -reset_n => oci_ienable[29]~reg0.ACLR -reset_n => oci_ienable[30]~reg0.ACLR -reset_n => oci_ienable[31]~reg0.ACLR -reset_n => oci_single_step_mode~reg0.ACLR -write => write_strobe.IN1 -writedata[0] => ocireg_mrs.DATAIN -writedata[1] => ocireg_ers.DATAIN -writedata[2] => ~NO_FANOUT~ -writedata[3] => oci_single_step_mode~reg0.DATAIN -writedata[4] => ~NO_FANOUT~ -writedata[5] => oci_ienable[5]~reg0.DATAIN -writedata[6] => ~NO_FANOUT~ -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -oci_ienable[0] <= oci_ienable[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[1] <= oci_ienable[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[2] <= oci_ienable[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[3] <= oci_ienable[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[4] <= oci_ienable[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[5] <= oci_ienable[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[6] <= oci_ienable[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[7] <= oci_ienable[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[8] <= oci_ienable[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[9] <= oci_ienable[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[10] <= oci_ienable[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[11] <= oci_ienable[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[12] <= oci_ienable[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[13] <= oci_ienable[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[14] <= oci_ienable[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[15] <= oci_ienable[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[16] <= oci_ienable[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[17] <= oci_ienable[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[18] <= oci_ienable[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[19] <= oci_ienable[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[20] <= oci_ienable[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[21] <= oci_ienable[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[22] <= oci_ienable[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[23] <= oci_ienable[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[24] <= oci_ienable[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[25] <= oci_ienable[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[26] <= oci_ienable[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[27] <= oci_ienable[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[28] <= oci_ienable[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[29] <= oci_ienable[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[30] <= oci_ienable[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_ienable[31] <= oci_ienable[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[0] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[1] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[2] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[3] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[4] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[5] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[6] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[7] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[8] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[9] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[10] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[11] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[12] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[13] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[14] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[15] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[16] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[17] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[18] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[19] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[20] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[21] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[22] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[23] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[24] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[25] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[26] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[27] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[28] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[29] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[30] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_reg_readdata[31] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE -oci_single_step_mode <= oci_single_step_mode~reg0.DB_MAX_OUTPUT_PORT_TYPE -ocireg_ers <= writedata[1].DB_MAX_OUTPUT_PORT_TYPE -ocireg_mrs <= writedata[0].DB_MAX_OUTPUT_PORT_TYPE -take_action_ocireg <= take_action_ocireg.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break -clk => trigger_state.CLK -clk => break_readreg[0]~reg0.CLK -clk => break_readreg[1]~reg0.CLK -clk => break_readreg[2]~reg0.CLK -clk => break_readreg[3]~reg0.CLK -clk => break_readreg[4]~reg0.CLK -clk => break_readreg[5]~reg0.CLK -clk => break_readreg[6]~reg0.CLK -clk => break_readreg[7]~reg0.CLK -clk => break_readreg[8]~reg0.CLK -clk => break_readreg[9]~reg0.CLK -clk => break_readreg[10]~reg0.CLK -clk => break_readreg[11]~reg0.CLK -clk => break_readreg[12]~reg0.CLK -clk => break_readreg[13]~reg0.CLK -clk => break_readreg[14]~reg0.CLK -clk => break_readreg[15]~reg0.CLK -clk => break_readreg[16]~reg0.CLK -clk => break_readreg[17]~reg0.CLK -clk => break_readreg[18]~reg0.CLK -clk => break_readreg[19]~reg0.CLK -clk => break_readreg[20]~reg0.CLK -clk => break_readreg[21]~reg0.CLK -clk => break_readreg[22]~reg0.CLK -clk => break_readreg[23]~reg0.CLK -clk => break_readreg[24]~reg0.CLK -clk => break_readreg[25]~reg0.CLK -clk => break_readreg[26]~reg0.CLK -clk => break_readreg[27]~reg0.CLK -clk => break_readreg[28]~reg0.CLK -clk => break_readreg[29]~reg0.CLK -clk => break_readreg[30]~reg0.CLK -clk => break_readreg[31]~reg0.CLK -clk => trigbrktype~reg0.CLK -dbrk_break => trigbrktype.OUTPUTSELECT -dbrk_goto0 => always2.IN0 -dbrk_goto1 => always2.IN0 -jdo[0] => break_readreg.DATAB -jdo[0] => break_readreg.DATAB -jdo[0] => break_readreg.DATAB -jdo[1] => break_readreg.DATAB -jdo[1] => break_readreg.DATAB -jdo[1] => break_readreg.DATAB -jdo[2] => break_readreg.DATAB -jdo[2] => break_readreg.DATAB -jdo[2] => break_readreg.DATAB -jdo[3] => break_readreg.DATAB -jdo[3] => break_readreg.DATAB -jdo[3] => break_readreg.DATAB -jdo[4] => break_readreg.DATAB -jdo[4] => break_readreg.DATAB -jdo[4] => break_readreg.DATAB -jdo[5] => break_readreg.DATAB -jdo[5] => break_readreg.DATAB -jdo[5] => break_readreg.DATAB -jdo[6] => break_readreg.DATAB -jdo[6] => break_readreg.DATAB -jdo[6] => break_readreg.DATAB -jdo[7] => break_readreg.DATAB -jdo[7] => break_readreg.DATAB -jdo[7] => break_readreg.DATAB -jdo[8] => break_readreg.DATAB -jdo[8] => break_readreg.DATAB -jdo[8] => break_readreg.DATAB -jdo[9] => break_readreg.DATAB -jdo[9] => break_readreg.DATAB -jdo[9] => break_readreg.DATAB -jdo[10] => break_readreg.DATAB -jdo[10] => break_readreg.DATAB -jdo[10] => break_readreg.DATAB -jdo[11] => break_readreg.DATAB -jdo[11] => break_readreg.DATAB -jdo[11] => break_readreg.DATAB -jdo[12] => break_readreg.DATAB -jdo[12] => break_readreg.DATAB -jdo[12] => break_readreg.DATAB -jdo[13] => break_readreg.DATAB -jdo[13] => break_readreg.DATAB -jdo[13] => break_readreg.DATAB -jdo[14] => break_readreg.DATAB -jdo[14] => break_readreg.DATAB -jdo[14] => break_readreg.DATAB -jdo[15] => break_readreg.DATAB -jdo[15] => break_readreg.DATAB -jdo[15] => break_readreg.DATAB -jdo[16] => break_readreg.DATAB -jdo[16] => break_readreg.DATAB -jdo[16] => break_readreg.DATAB -jdo[17] => break_readreg.DATAB -jdo[17] => break_readreg.DATAB -jdo[17] => break_readreg.DATAB -jdo[18] => break_readreg.DATAB -jdo[18] => break_readreg.DATAB -jdo[18] => break_readreg.DATAB -jdo[19] => break_readreg.DATAB -jdo[19] => break_readreg.DATAB -jdo[19] => break_readreg.DATAB -jdo[20] => break_readreg.DATAB -jdo[20] => break_readreg.DATAB -jdo[20] => break_readreg.DATAB -jdo[21] => break_readreg.DATAB -jdo[21] => break_readreg.DATAB -jdo[21] => break_readreg.DATAB -jdo[22] => break_readreg.DATAB -jdo[22] => break_readreg.DATAB -jdo[22] => break_readreg.DATAB -jdo[23] => break_readreg.DATAB -jdo[23] => break_readreg.DATAB -jdo[23] => break_readreg.DATAB -jdo[24] => break_readreg.DATAB -jdo[24] => break_readreg.DATAB -jdo[24] => break_readreg.DATAB -jdo[25] => break_readreg.DATAB -jdo[25] => break_readreg.DATAB -jdo[25] => break_readreg.DATAB -jdo[26] => break_readreg.DATAB -jdo[26] => break_readreg.DATAB -jdo[26] => break_readreg.DATAB -jdo[27] => break_readreg.DATAB -jdo[27] => break_readreg.DATAB -jdo[27] => break_readreg.DATAB -jdo[28] => break_readreg.DATAB -jdo[28] => break_readreg.DATAB -jdo[28] => break_readreg.DATAB -jdo[29] => break_readreg.DATAB -jdo[29] => break_readreg.DATAB -jdo[29] => break_readreg.DATAB -jdo[30] => break_readreg.DATAB -jdo[30] => break_readreg.DATAB -jdo[30] => break_readreg.DATAB -jdo[31] => break_readreg.DATAB -jdo[31] => break_readreg.DATAB -jdo[31] => break_readreg.DATAB -jdo[32] => ~NO_FANOUT~ -jdo[33] => ~NO_FANOUT~ -jdo[34] => ~NO_FANOUT~ -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => break_readreg[0]~reg0.ACLR -jrst_n => break_readreg[1]~reg0.ACLR -jrst_n => break_readreg[2]~reg0.ACLR -jrst_n => break_readreg[3]~reg0.ACLR -jrst_n => break_readreg[4]~reg0.ACLR -jrst_n => break_readreg[5]~reg0.ACLR -jrst_n => break_readreg[6]~reg0.ACLR -jrst_n => break_readreg[7]~reg0.ACLR -jrst_n => break_readreg[8]~reg0.ACLR -jrst_n => break_readreg[9]~reg0.ACLR -jrst_n => break_readreg[10]~reg0.ACLR -jrst_n => break_readreg[11]~reg0.ACLR -jrst_n => break_readreg[12]~reg0.ACLR -jrst_n => break_readreg[13]~reg0.ACLR -jrst_n => break_readreg[14]~reg0.ACLR -jrst_n => break_readreg[15]~reg0.ACLR -jrst_n => break_readreg[16]~reg0.ACLR -jrst_n => break_readreg[17]~reg0.ACLR -jrst_n => break_readreg[18]~reg0.ACLR -jrst_n => break_readreg[19]~reg0.ACLR -jrst_n => break_readreg[20]~reg0.ACLR -jrst_n => break_readreg[21]~reg0.ACLR -jrst_n => break_readreg[22]~reg0.ACLR -jrst_n => break_readreg[23]~reg0.ACLR -jrst_n => break_readreg[24]~reg0.ACLR -jrst_n => break_readreg[25]~reg0.ACLR -jrst_n => break_readreg[26]~reg0.ACLR -jrst_n => break_readreg[27]~reg0.ACLR -jrst_n => break_readreg[28]~reg0.ACLR -jrst_n => break_readreg[29]~reg0.ACLR -jrst_n => break_readreg[30]~reg0.ACLR -jrst_n => break_readreg[31]~reg0.ACLR -jrst_n => trigbrktype~reg0.ACLR -reset_n => trigger_state.ACLR -take_action_break_a => take_action_any_break.IN0 -take_action_break_b => take_action_any_break.IN1 -take_action_break_c => take_action_any_break.IN1 -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_a => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_b => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -take_no_action_break_c => break_readreg.OUTPUTSELECT -xbrk_goto0 => always2.IN1 -xbrk_goto1 => always2.IN1 -break_readreg[0] <= break_readreg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[1] <= break_readreg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[2] <= break_readreg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[3] <= break_readreg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[4] <= break_readreg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[5] <= break_readreg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[6] <= break_readreg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[7] <= break_readreg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[8] <= break_readreg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[9] <= break_readreg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[10] <= break_readreg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[11] <= break_readreg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[12] <= break_readreg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[13] <= break_readreg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[14] <= break_readreg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[15] <= break_readreg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[16] <= break_readreg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[17] <= break_readreg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[18] <= break_readreg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[19] <= break_readreg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[20] <= break_readreg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[21] <= break_readreg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[22] <= break_readreg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[23] <= break_readreg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[24] <= break_readreg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[25] <= break_readreg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[26] <= break_readreg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[27] <= break_readreg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[28] <= break_readreg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[29] <= break_readreg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[30] <= break_readreg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -break_readreg[31] <= break_readreg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_hit0_latch <= -dbrk_hit1_latch <= -dbrk_hit2_latch <= -dbrk_hit3_latch <= -trigbrktype <= trigbrktype~reg0.DB_MAX_OUTPUT_PORT_TYPE -trigger_state_0 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE -trigger_state_1 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE -xbrk_ctrl0[0] <= -xbrk_ctrl0[1] <= -xbrk_ctrl0[2] <= -xbrk_ctrl0[3] <= -xbrk_ctrl0[4] <= -xbrk_ctrl0[5] <= -xbrk_ctrl0[6] <= -xbrk_ctrl0[7] <= -xbrk_ctrl1[0] <= -xbrk_ctrl1[1] <= -xbrk_ctrl1[2] <= -xbrk_ctrl1[3] <= -xbrk_ctrl1[4] <= -xbrk_ctrl1[5] <= -xbrk_ctrl1[6] <= -xbrk_ctrl1[7] <= -xbrk_ctrl2[0] <= -xbrk_ctrl2[1] <= -xbrk_ctrl2[2] <= -xbrk_ctrl2[3] <= -xbrk_ctrl2[4] <= -xbrk_ctrl2[5] <= -xbrk_ctrl2[6] <= -xbrk_ctrl2[7] <= -xbrk_ctrl3[0] <= -xbrk_ctrl3[1] <= -xbrk_ctrl3[2] <= -xbrk_ctrl3[3] <= -xbrk_ctrl3[4] <= -xbrk_ctrl3[5] <= -xbrk_ctrl3[6] <= -xbrk_ctrl3[7] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk -D_valid => ~NO_FANOUT~ -E_valid => xbrk_break~reg0.ENA -F_pc[0] => ~NO_FANOUT~ -F_pc[1] => ~NO_FANOUT~ -F_pc[2] => ~NO_FANOUT~ -F_pc[3] => ~NO_FANOUT~ -F_pc[4] => ~NO_FANOUT~ -F_pc[5] => ~NO_FANOUT~ -F_pc[6] => ~NO_FANOUT~ -F_pc[7] => ~NO_FANOUT~ -F_pc[8] => ~NO_FANOUT~ -F_pc[9] => ~NO_FANOUT~ -F_pc[10] => ~NO_FANOUT~ -F_pc[11] => ~NO_FANOUT~ -F_pc[12] => ~NO_FANOUT~ -F_pc[13] => ~NO_FANOUT~ -F_pc[14] => ~NO_FANOUT~ -F_pc[15] => ~NO_FANOUT~ -F_pc[16] => ~NO_FANOUT~ -clk => xbrk_break~reg0.CLK -reset_n => xbrk_break~reg0.ACLR -trigger_state_0 => ~NO_FANOUT~ -trigger_state_1 => ~NO_FANOUT~ -xbrk_ctrl0[0] => ~NO_FANOUT~ -xbrk_ctrl0[1] => ~NO_FANOUT~ -xbrk_ctrl0[2] => ~NO_FANOUT~ -xbrk_ctrl0[3] => ~NO_FANOUT~ -xbrk_ctrl0[4] => ~NO_FANOUT~ -xbrk_ctrl0[5] => ~NO_FANOUT~ -xbrk_ctrl0[6] => ~NO_FANOUT~ -xbrk_ctrl0[7] => ~NO_FANOUT~ -xbrk_ctrl1[0] => ~NO_FANOUT~ -xbrk_ctrl1[1] => ~NO_FANOUT~ -xbrk_ctrl1[2] => ~NO_FANOUT~ -xbrk_ctrl1[3] => ~NO_FANOUT~ -xbrk_ctrl1[4] => ~NO_FANOUT~ -xbrk_ctrl1[5] => ~NO_FANOUT~ -xbrk_ctrl1[6] => ~NO_FANOUT~ -xbrk_ctrl1[7] => ~NO_FANOUT~ -xbrk_ctrl2[0] => ~NO_FANOUT~ -xbrk_ctrl2[1] => ~NO_FANOUT~ -xbrk_ctrl2[2] => ~NO_FANOUT~ -xbrk_ctrl2[3] => ~NO_FANOUT~ -xbrk_ctrl2[4] => ~NO_FANOUT~ -xbrk_ctrl2[5] => ~NO_FANOUT~ -xbrk_ctrl2[6] => ~NO_FANOUT~ -xbrk_ctrl2[7] => ~NO_FANOUT~ -xbrk_ctrl3[0] => ~NO_FANOUT~ -xbrk_ctrl3[1] => ~NO_FANOUT~ -xbrk_ctrl3[2] => ~NO_FANOUT~ -xbrk_ctrl3[3] => ~NO_FANOUT~ -xbrk_ctrl3[4] => ~NO_FANOUT~ -xbrk_ctrl3[5] => ~NO_FANOUT~ -xbrk_ctrl3[6] => ~NO_FANOUT~ -xbrk_ctrl3[7] => ~NO_FANOUT~ -xbrk_break <= xbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE -xbrk_goto0 <= -xbrk_goto1 <= -xbrk_traceoff <= -xbrk_traceon <= -xbrk_trigout <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk -E_st_data[0] => cpu_d_writedata[0].DATAIN -E_st_data[1] => cpu_d_writedata[1].DATAIN -E_st_data[2] => cpu_d_writedata[2].DATAIN -E_st_data[3] => cpu_d_writedata[3].DATAIN -E_st_data[4] => cpu_d_writedata[4].DATAIN -E_st_data[5] => cpu_d_writedata[5].DATAIN -E_st_data[6] => cpu_d_writedata[6].DATAIN -E_st_data[7] => cpu_d_writedata[7].DATAIN -E_st_data[8] => cpu_d_writedata[8].DATAIN -E_st_data[9] => cpu_d_writedata[9].DATAIN -E_st_data[10] => cpu_d_writedata[10].DATAIN -E_st_data[11] => cpu_d_writedata[11].DATAIN -E_st_data[12] => cpu_d_writedata[12].DATAIN -E_st_data[13] => cpu_d_writedata[13].DATAIN -E_st_data[14] => cpu_d_writedata[14].DATAIN -E_st_data[15] => cpu_d_writedata[15].DATAIN -E_st_data[16] => cpu_d_writedata[16].DATAIN -E_st_data[17] => cpu_d_writedata[17].DATAIN -E_st_data[18] => cpu_d_writedata[18].DATAIN -E_st_data[19] => cpu_d_writedata[19].DATAIN -E_st_data[20] => cpu_d_writedata[20].DATAIN -E_st_data[21] => cpu_d_writedata[21].DATAIN -E_st_data[22] => cpu_d_writedata[22].DATAIN -E_st_data[23] => cpu_d_writedata[23].DATAIN -E_st_data[24] => cpu_d_writedata[24].DATAIN -E_st_data[25] => cpu_d_writedata[25].DATAIN -E_st_data[26] => cpu_d_writedata[26].DATAIN -E_st_data[27] => cpu_d_writedata[27].DATAIN -E_st_data[28] => cpu_d_writedata[28].DATAIN -E_st_data[29] => cpu_d_writedata[29].DATAIN -E_st_data[30] => cpu_d_writedata[30].DATAIN -E_st_data[31] => cpu_d_writedata[31].DATAIN -av_ld_data_aligned_filtered[0] => cpu_d_readdata[0].DATAIN -av_ld_data_aligned_filtered[1] => cpu_d_readdata[1].DATAIN -av_ld_data_aligned_filtered[2] => cpu_d_readdata[2].DATAIN -av_ld_data_aligned_filtered[3] => cpu_d_readdata[3].DATAIN -av_ld_data_aligned_filtered[4] => cpu_d_readdata[4].DATAIN -av_ld_data_aligned_filtered[5] => cpu_d_readdata[5].DATAIN -av_ld_data_aligned_filtered[6] => cpu_d_readdata[6].DATAIN -av_ld_data_aligned_filtered[7] => cpu_d_readdata[7].DATAIN -av_ld_data_aligned_filtered[8] => cpu_d_readdata[8].DATAIN -av_ld_data_aligned_filtered[9] => cpu_d_readdata[9].DATAIN -av_ld_data_aligned_filtered[10] => cpu_d_readdata[10].DATAIN -av_ld_data_aligned_filtered[11] => cpu_d_readdata[11].DATAIN -av_ld_data_aligned_filtered[12] => cpu_d_readdata[12].DATAIN -av_ld_data_aligned_filtered[13] => cpu_d_readdata[13].DATAIN -av_ld_data_aligned_filtered[14] => cpu_d_readdata[14].DATAIN -av_ld_data_aligned_filtered[15] => cpu_d_readdata[15].DATAIN -av_ld_data_aligned_filtered[16] => cpu_d_readdata[16].DATAIN -av_ld_data_aligned_filtered[17] => cpu_d_readdata[17].DATAIN -av_ld_data_aligned_filtered[18] => cpu_d_readdata[18].DATAIN -av_ld_data_aligned_filtered[19] => cpu_d_readdata[19].DATAIN -av_ld_data_aligned_filtered[20] => cpu_d_readdata[20].DATAIN -av_ld_data_aligned_filtered[21] => cpu_d_readdata[21].DATAIN -av_ld_data_aligned_filtered[22] => cpu_d_readdata[22].DATAIN -av_ld_data_aligned_filtered[23] => cpu_d_readdata[23].DATAIN -av_ld_data_aligned_filtered[24] => cpu_d_readdata[24].DATAIN -av_ld_data_aligned_filtered[25] => cpu_d_readdata[25].DATAIN -av_ld_data_aligned_filtered[26] => cpu_d_readdata[26].DATAIN -av_ld_data_aligned_filtered[27] => cpu_d_readdata[27].DATAIN -av_ld_data_aligned_filtered[28] => cpu_d_readdata[28].DATAIN -av_ld_data_aligned_filtered[29] => cpu_d_readdata[29].DATAIN -av_ld_data_aligned_filtered[30] => cpu_d_readdata[30].DATAIN -av_ld_data_aligned_filtered[31] => cpu_d_readdata[31].DATAIN -clk => dbrk_goto1~reg0.CLK -clk => dbrk_goto0~reg0.CLK -clk => dbrk_traceme~reg0.CLK -clk => dbrk_traceon~reg0.CLK -clk => dbrk_traceoff~reg0.CLK -clk => dbrk_break_pulse.CLK -clk => dbrk_trigout~reg0.CLK -clk => dbrk_break~reg0.CLK -d_address[0] => cpu_d_address[0].DATAIN -d_address[1] => cpu_d_address[1].DATAIN -d_address[2] => cpu_d_address[2].DATAIN -d_address[3] => cpu_d_address[3].DATAIN -d_address[4] => cpu_d_address[4].DATAIN -d_address[5] => cpu_d_address[5].DATAIN -d_address[6] => cpu_d_address[6].DATAIN -d_address[7] => cpu_d_address[7].DATAIN -d_address[8] => cpu_d_address[8].DATAIN -d_address[9] => cpu_d_address[9].DATAIN -d_address[10] => cpu_d_address[10].DATAIN -d_address[11] => cpu_d_address[11].DATAIN -d_address[12] => cpu_d_address[12].DATAIN -d_address[13] => cpu_d_address[13].DATAIN -d_address[14] => cpu_d_address[14].DATAIN -d_address[15] => cpu_d_address[15].DATAIN -d_address[16] => cpu_d_address[16].DATAIN -d_address[17] => cpu_d_address[17].DATAIN -d_address[18] => cpu_d_address[18].DATAIN -d_read => cpu_d_read.DATAIN -d_waitrequest => cpu_d_wait.DATAIN -d_write => cpu_d_write.DATAIN -debugack => dbrk_break.DATAB -reset_n => dbrk_goto1~reg0.ACLR -reset_n => dbrk_goto0~reg0.ACLR -reset_n => dbrk_traceme~reg0.ACLR -reset_n => dbrk_traceon~reg0.ACLR -reset_n => dbrk_traceoff~reg0.ACLR -reset_n => dbrk_break_pulse.ACLR -reset_n => dbrk_trigout~reg0.ACLR -reset_n => dbrk_break~reg0.ACLR -cpu_d_address[0] <= d_address[0].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[1] <= d_address[1].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[2] <= d_address[2].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[3] <= d_address[3].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[4] <= d_address[4].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[5] <= d_address[5].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[6] <= d_address[6].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[7] <= d_address[7].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[8] <= d_address[8].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[9] <= d_address[9].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[10] <= d_address[10].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[11] <= d_address[11].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[12] <= d_address[12].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[13] <= d_address[13].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[14] <= d_address[14].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[15] <= d_address[15].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[16] <= d_address[16].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[17] <= d_address[17].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_address[18] <= d_address[18].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_read <= d_read.DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[0] <= av_ld_data_aligned_filtered[0].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[1] <= av_ld_data_aligned_filtered[1].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[2] <= av_ld_data_aligned_filtered[2].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[3] <= av_ld_data_aligned_filtered[3].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[4] <= av_ld_data_aligned_filtered[4].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[5] <= av_ld_data_aligned_filtered[5].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[6] <= av_ld_data_aligned_filtered[6].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[7] <= av_ld_data_aligned_filtered[7].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[8] <= av_ld_data_aligned_filtered[8].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[9] <= av_ld_data_aligned_filtered[9].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[10] <= av_ld_data_aligned_filtered[10].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[11] <= av_ld_data_aligned_filtered[11].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[12] <= av_ld_data_aligned_filtered[12].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[13] <= av_ld_data_aligned_filtered[13].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[14] <= av_ld_data_aligned_filtered[14].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[15] <= av_ld_data_aligned_filtered[15].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[16] <= av_ld_data_aligned_filtered[16].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[17] <= av_ld_data_aligned_filtered[17].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[18] <= av_ld_data_aligned_filtered[18].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[19] <= av_ld_data_aligned_filtered[19].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[20] <= av_ld_data_aligned_filtered[20].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[21] <= av_ld_data_aligned_filtered[21].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[22] <= av_ld_data_aligned_filtered[22].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[23] <= av_ld_data_aligned_filtered[23].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[24] <= av_ld_data_aligned_filtered[24].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[25] <= av_ld_data_aligned_filtered[25].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[26] <= av_ld_data_aligned_filtered[26].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[27] <= av_ld_data_aligned_filtered[27].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[28] <= av_ld_data_aligned_filtered[28].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[29] <= av_ld_data_aligned_filtered[29].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[30] <= av_ld_data_aligned_filtered[30].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_readdata[31] <= av_ld_data_aligned_filtered[31].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_wait <= d_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -cpu_d_write <= d_write.DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[0] <= E_st_data[0].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[1] <= E_st_data[1].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[2] <= E_st_data[2].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[3] <= E_st_data[3].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[4] <= E_st_data[4].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[5] <= E_st_data[5].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[6] <= E_st_data[6].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[7] <= E_st_data[7].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[8] <= E_st_data[8].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[9] <= E_st_data[9].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[10] <= E_st_data[10].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[11] <= E_st_data[11].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[12] <= E_st_data[12].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[13] <= E_st_data[13].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[14] <= E_st_data[14].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[15] <= E_st_data[15].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[16] <= E_st_data[16].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[17] <= E_st_data[17].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[18] <= E_st_data[18].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[19] <= E_st_data[19].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[20] <= E_st_data[20].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[21] <= E_st_data[21].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[22] <= E_st_data[22].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[23] <= E_st_data[23].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[24] <= E_st_data[24].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[25] <= E_st_data[25].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[26] <= E_st_data[26].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[27] <= E_st_data[27].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[28] <= E_st_data[28].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[29] <= E_st_data[29].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[30] <= E_st_data[30].DB_MAX_OUTPUT_PORT_TYPE -cpu_d_writedata[31] <= E_st_data[31].DB_MAX_OUTPUT_PORT_TYPE -dbrk_break <= dbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_goto0 <= dbrk_goto0~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_goto1 <= dbrk_goto1~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_traceme <= dbrk_traceme~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_traceoff <= dbrk_traceoff~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_traceon <= dbrk_traceon~reg0.DB_MAX_OUTPUT_PORT_TYPE -dbrk_trigout <= dbrk_trigout~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace -clk => dct_count[0]~reg0.CLK -clk => dct_count[1]~reg0.CLK -clk => dct_count[2]~reg0.CLK -clk => dct_count[3]~reg0.CLK -clk => dct_buffer[0]~reg0.CLK -clk => dct_buffer[1]~reg0.CLK -clk => dct_buffer[2]~reg0.CLK -clk => dct_buffer[3]~reg0.CLK -clk => dct_buffer[4]~reg0.CLK -clk => dct_buffer[5]~reg0.CLK -clk => dct_buffer[6]~reg0.CLK -clk => dct_buffer[7]~reg0.CLK -clk => dct_buffer[8]~reg0.CLK -clk => dct_buffer[9]~reg0.CLK -clk => dct_buffer[10]~reg0.CLK -clk => dct_buffer[11]~reg0.CLK -clk => dct_buffer[12]~reg0.CLK -clk => dct_buffer[13]~reg0.CLK -clk => dct_buffer[14]~reg0.CLK -clk => dct_buffer[15]~reg0.CLK -clk => dct_buffer[16]~reg0.CLK -clk => dct_buffer[17]~reg0.CLK -clk => dct_buffer[18]~reg0.CLK -clk => dct_buffer[19]~reg0.CLK -clk => dct_buffer[20]~reg0.CLK -clk => dct_buffer[21]~reg0.CLK -clk => dct_buffer[22]~reg0.CLK -clk => dct_buffer[23]~reg0.CLK -clk => dct_buffer[24]~reg0.CLK -clk => dct_buffer[25]~reg0.CLK -clk => dct_buffer[26]~reg0.CLK -clk => dct_buffer[27]~reg0.CLK -clk => dct_buffer[28]~reg0.CLK -clk => dct_buffer[29]~reg0.CLK -clk => itm[0]~reg0.CLK -clk => itm[1]~reg0.CLK -clk => itm[2]~reg0.CLK -clk => itm[3]~reg0.CLK -clk => itm[4]~reg0.CLK -clk => itm[5]~reg0.CLK -clk => itm[6]~reg0.CLK -clk => itm[7]~reg0.CLK -clk => itm[8]~reg0.CLK -clk => itm[9]~reg0.CLK -clk => itm[10]~reg0.CLK -clk => itm[11]~reg0.CLK -clk => itm[12]~reg0.CLK -clk => itm[13]~reg0.CLK -clk => itm[14]~reg0.CLK -clk => itm[15]~reg0.CLK -clk => itm[16]~reg0.CLK -clk => itm[17]~reg0.CLK -clk => itm[18]~reg0.CLK -clk => itm[19]~reg0.CLK -clk => itm[20]~reg0.CLK -clk => itm[21]~reg0.CLK -clk => itm[22]~reg0.CLK -clk => itm[23]~reg0.CLK -clk => itm[24]~reg0.CLK -clk => itm[25]~reg0.CLK -clk => itm[26]~reg0.CLK -clk => itm[27]~reg0.CLK -clk => itm[28]~reg0.CLK -clk => itm[29]~reg0.CLK -clk => itm[30]~reg0.CLK -clk => itm[31]~reg0.CLK -clk => itm[32]~reg0.CLK -clk => itm[33]~reg0.CLK -clk => itm[34]~reg0.CLK -clk => itm[35]~reg0.CLK -dbrk_traceoff => ~NO_FANOUT~ -dbrk_traceon => ~NO_FANOUT~ -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => ~NO_FANOUT~ -jdo[4] => ~NO_FANOUT~ -jdo[5] => ~NO_FANOUT~ -jdo[6] => ~NO_FANOUT~ -jdo[7] => ~NO_FANOUT~ -jdo[8] => ~NO_FANOUT~ -jdo[9] => ~NO_FANOUT~ -jdo[10] => ~NO_FANOUT~ -jdo[11] => ~NO_FANOUT~ -jdo[12] => ~NO_FANOUT~ -jdo[13] => ~NO_FANOUT~ -jdo[14] => ~NO_FANOUT~ -jdo[15] => ~NO_FANOUT~ -jrst_n => dct_count[0]~reg0.ACLR -jrst_n => dct_count[1]~reg0.ACLR -jrst_n => dct_count[2]~reg0.ACLR -jrst_n => dct_count[3]~reg0.ACLR -jrst_n => dct_buffer[0]~reg0.ACLR -jrst_n => dct_buffer[1]~reg0.ACLR -jrst_n => dct_buffer[2]~reg0.ACLR -jrst_n => dct_buffer[3]~reg0.ACLR -jrst_n => dct_buffer[4]~reg0.ACLR -jrst_n => dct_buffer[5]~reg0.ACLR -jrst_n => dct_buffer[6]~reg0.ACLR -jrst_n => dct_buffer[7]~reg0.ACLR -jrst_n => dct_buffer[8]~reg0.ACLR -jrst_n => dct_buffer[9]~reg0.ACLR -jrst_n => dct_buffer[10]~reg0.ACLR -jrst_n => dct_buffer[11]~reg0.ACLR -jrst_n => dct_buffer[12]~reg0.ACLR -jrst_n => dct_buffer[13]~reg0.ACLR -jrst_n => dct_buffer[14]~reg0.ACLR -jrst_n => dct_buffer[15]~reg0.ACLR -jrst_n => dct_buffer[16]~reg0.ACLR -jrst_n => dct_buffer[17]~reg0.ACLR -jrst_n => dct_buffer[18]~reg0.ACLR -jrst_n => dct_buffer[19]~reg0.ACLR -jrst_n => dct_buffer[20]~reg0.ACLR -jrst_n => dct_buffer[21]~reg0.ACLR -jrst_n => dct_buffer[22]~reg0.ACLR -jrst_n => dct_buffer[23]~reg0.ACLR -jrst_n => dct_buffer[24]~reg0.ACLR -jrst_n => dct_buffer[25]~reg0.ACLR -jrst_n => dct_buffer[26]~reg0.ACLR -jrst_n => dct_buffer[27]~reg0.ACLR -jrst_n => dct_buffer[28]~reg0.ACLR -jrst_n => dct_buffer[29]~reg0.ACLR -jrst_n => itm[0]~reg0.ACLR -jrst_n => itm[1]~reg0.ACLR -jrst_n => itm[2]~reg0.ACLR -jrst_n => itm[3]~reg0.ACLR -jrst_n => itm[4]~reg0.ACLR -jrst_n => itm[5]~reg0.ACLR -jrst_n => itm[6]~reg0.ACLR -jrst_n => itm[7]~reg0.ACLR -jrst_n => itm[8]~reg0.ACLR -jrst_n => itm[9]~reg0.ACLR -jrst_n => itm[10]~reg0.ACLR -jrst_n => itm[11]~reg0.ACLR -jrst_n => itm[12]~reg0.ACLR -jrst_n => itm[13]~reg0.ACLR -jrst_n => itm[14]~reg0.ACLR -jrst_n => itm[15]~reg0.ACLR -jrst_n => itm[16]~reg0.ACLR -jrst_n => itm[17]~reg0.ACLR -jrst_n => itm[18]~reg0.ACLR -jrst_n => itm[19]~reg0.ACLR -jrst_n => itm[20]~reg0.ACLR -jrst_n => itm[21]~reg0.ACLR -jrst_n => itm[22]~reg0.ACLR -jrst_n => itm[23]~reg0.ACLR -jrst_n => itm[24]~reg0.ACLR -jrst_n => itm[25]~reg0.ACLR -jrst_n => itm[26]~reg0.ACLR -jrst_n => itm[27]~reg0.ACLR -jrst_n => itm[28]~reg0.ACLR -jrst_n => itm[29]~reg0.ACLR -jrst_n => itm[30]~reg0.ACLR -jrst_n => itm[31]~reg0.ACLR -jrst_n => itm[32]~reg0.ACLR -jrst_n => itm[33]~reg0.ACLR -jrst_n => itm[34]~reg0.ACLR -jrst_n => itm[35]~reg0.ACLR -take_action_tracectrl => ~NO_FANOUT~ -trc_enb => ~NO_FANOUT~ -xbrk_traceoff => ~NO_FANOUT~ -xbrk_traceon => ~NO_FANOUT~ -xbrk_wrap_traceoff => ~NO_FANOUT~ -dct_buffer[0] <= dct_buffer[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[1] <= dct_buffer[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[2] <= dct_buffer[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[3] <= dct_buffer[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[4] <= dct_buffer[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[5] <= dct_buffer[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[6] <= dct_buffer[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[7] <= dct_buffer[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[8] <= dct_buffer[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[9] <= dct_buffer[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[10] <= dct_buffer[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[11] <= dct_buffer[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[12] <= dct_buffer[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[13] <= dct_buffer[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[14] <= dct_buffer[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[15] <= dct_buffer[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[16] <= dct_buffer[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[17] <= dct_buffer[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[18] <= dct_buffer[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[19] <= dct_buffer[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[20] <= dct_buffer[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[21] <= dct_buffer[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[22] <= dct_buffer[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[23] <= dct_buffer[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[24] <= dct_buffer[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[25] <= dct_buffer[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[26] <= dct_buffer[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[27] <= dct_buffer[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[28] <= dct_buffer[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_buffer[29] <= dct_buffer[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[0] <= dct_count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[1] <= dct_count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[2] <= dct_count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dct_count[3] <= dct_count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[0] <= itm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[1] <= itm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[2] <= itm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[3] <= itm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[4] <= itm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[5] <= itm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[6] <= itm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[7] <= itm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[8] <= itm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[9] <= itm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[10] <= itm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[11] <= itm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[12] <= itm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[13] <= itm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[14] <= itm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[15] <= itm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[16] <= itm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[17] <= itm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[18] <= itm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[19] <= itm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[20] <= itm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[21] <= itm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[22] <= itm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[23] <= itm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[24] <= itm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[25] <= itm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[26] <= itm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[27] <= itm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[28] <= itm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[29] <= itm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[30] <= itm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[31] <= itm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[32] <= itm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[33] <= itm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[34] <= itm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -itm[35] <= itm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_ctrl[0] <= -trc_ctrl[1] <= -trc_ctrl[2] <= -trc_ctrl[3] <= -trc_ctrl[4] <= -trc_ctrl[5] <= -trc_ctrl[6] <= -trc_ctrl[7] <= -trc_ctrl[8] <= -trc_ctrl[9] <= -trc_ctrl[10] <= -trc_ctrl[11] <= -trc_ctrl[12] <= -trc_ctrl[13] <= -trc_ctrl[14] <= -trc_ctrl[15] <= -trc_on <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace -clk => dtm[0]~reg0.CLK -clk => dtm[1]~reg0.CLK -clk => dtm[2]~reg0.CLK -clk => dtm[3]~reg0.CLK -clk => dtm[4]~reg0.CLK -clk => dtm[5]~reg0.CLK -clk => dtm[6]~reg0.CLK -clk => dtm[7]~reg0.CLK -clk => dtm[8]~reg0.CLK -clk => dtm[9]~reg0.CLK -clk => dtm[10]~reg0.CLK -clk => dtm[11]~reg0.CLK -clk => dtm[12]~reg0.CLK -clk => dtm[13]~reg0.CLK -clk => dtm[14]~reg0.CLK -clk => dtm[15]~reg0.CLK -clk => dtm[16]~reg0.CLK -clk => dtm[17]~reg0.CLK -clk => dtm[18]~reg0.CLK -clk => dtm[19]~reg0.CLK -clk => dtm[20]~reg0.CLK -clk => dtm[21]~reg0.CLK -clk => dtm[22]~reg0.CLK -clk => dtm[23]~reg0.CLK -clk => dtm[24]~reg0.CLK -clk => dtm[25]~reg0.CLK -clk => dtm[26]~reg0.CLK -clk => dtm[27]~reg0.CLK -clk => dtm[28]~reg0.CLK -clk => dtm[29]~reg0.CLK -clk => dtm[30]~reg0.CLK -clk => dtm[31]~reg0.CLK -clk => dtm[32]~reg0.CLK -clk => dtm[33]~reg0.CLK -clk => dtm[34]~reg0.CLK -clk => dtm[35]~reg0.CLK -clk => atm[0]~reg0.CLK -clk => atm[1]~reg0.CLK -clk => atm[2]~reg0.CLK -clk => atm[3]~reg0.CLK -clk => atm[4]~reg0.CLK -clk => atm[5]~reg0.CLK -clk => atm[6]~reg0.CLK -clk => atm[7]~reg0.CLK -clk => atm[8]~reg0.CLK -clk => atm[9]~reg0.CLK -clk => atm[10]~reg0.CLK -clk => atm[11]~reg0.CLK -clk => atm[12]~reg0.CLK -clk => atm[13]~reg0.CLK -clk => atm[14]~reg0.CLK -clk => atm[15]~reg0.CLK -clk => atm[16]~reg0.CLK -clk => atm[17]~reg0.CLK -clk => atm[18]~reg0.CLK -clk => atm[19]~reg0.CLK -clk => atm[20]~reg0.CLK -clk => atm[21]~reg0.CLK -clk => atm[22]~reg0.CLK -clk => atm[23]~reg0.CLK -clk => atm[24]~reg0.CLK -clk => atm[25]~reg0.CLK -clk => atm[26]~reg0.CLK -clk => atm[27]~reg0.CLK -clk => atm[28]~reg0.CLK -clk => atm[29]~reg0.CLK -clk => atm[30]~reg0.CLK -clk => atm[31]~reg0.CLK -clk => atm[32]~reg0.CLK -clk => atm[33]~reg0.CLK -clk => atm[34]~reg0.CLK -clk => atm[35]~reg0.CLK -cpu_d_address[0] => ~NO_FANOUT~ -cpu_d_address[1] => ~NO_FANOUT~ -cpu_d_address[2] => ~NO_FANOUT~ -cpu_d_address[3] => ~NO_FANOUT~ -cpu_d_address[4] => ~NO_FANOUT~ -cpu_d_address[5] => ~NO_FANOUT~ -cpu_d_address[6] => ~NO_FANOUT~ -cpu_d_address[7] => ~NO_FANOUT~ -cpu_d_address[8] => ~NO_FANOUT~ -cpu_d_address[9] => ~NO_FANOUT~ -cpu_d_address[10] => ~NO_FANOUT~ -cpu_d_address[11] => ~NO_FANOUT~ -cpu_d_address[12] => ~NO_FANOUT~ -cpu_d_address[13] => ~NO_FANOUT~ -cpu_d_address[14] => ~NO_FANOUT~ -cpu_d_address[15] => ~NO_FANOUT~ -cpu_d_address[16] => ~NO_FANOUT~ -cpu_d_address[17] => ~NO_FANOUT~ -cpu_d_address[18] => ~NO_FANOUT~ -cpu_d_read => ~NO_FANOUT~ -cpu_d_readdata[0] => ~NO_FANOUT~ -cpu_d_readdata[1] => ~NO_FANOUT~ -cpu_d_readdata[2] => ~NO_FANOUT~ -cpu_d_readdata[3] => ~NO_FANOUT~ -cpu_d_readdata[4] => ~NO_FANOUT~ -cpu_d_readdata[5] => ~NO_FANOUT~ -cpu_d_readdata[6] => ~NO_FANOUT~ -cpu_d_readdata[7] => ~NO_FANOUT~ -cpu_d_readdata[8] => ~NO_FANOUT~ -cpu_d_readdata[9] => ~NO_FANOUT~ -cpu_d_readdata[10] => ~NO_FANOUT~ -cpu_d_readdata[11] => ~NO_FANOUT~ -cpu_d_readdata[12] => ~NO_FANOUT~ -cpu_d_readdata[13] => ~NO_FANOUT~ -cpu_d_readdata[14] => ~NO_FANOUT~ -cpu_d_readdata[15] => ~NO_FANOUT~ -cpu_d_readdata[16] => ~NO_FANOUT~ -cpu_d_readdata[17] => ~NO_FANOUT~ -cpu_d_readdata[18] => ~NO_FANOUT~ -cpu_d_readdata[19] => ~NO_FANOUT~ -cpu_d_readdata[20] => ~NO_FANOUT~ -cpu_d_readdata[21] => ~NO_FANOUT~ -cpu_d_readdata[22] => ~NO_FANOUT~ -cpu_d_readdata[23] => ~NO_FANOUT~ -cpu_d_readdata[24] => ~NO_FANOUT~ -cpu_d_readdata[25] => ~NO_FANOUT~ -cpu_d_readdata[26] => ~NO_FANOUT~ -cpu_d_readdata[27] => ~NO_FANOUT~ -cpu_d_readdata[28] => ~NO_FANOUT~ -cpu_d_readdata[29] => ~NO_FANOUT~ -cpu_d_readdata[30] => ~NO_FANOUT~ -cpu_d_readdata[31] => ~NO_FANOUT~ -cpu_d_wait => ~NO_FANOUT~ -cpu_d_write => ~NO_FANOUT~ -cpu_d_writedata[0] => ~NO_FANOUT~ -cpu_d_writedata[1] => ~NO_FANOUT~ -cpu_d_writedata[2] => ~NO_FANOUT~ -cpu_d_writedata[3] => ~NO_FANOUT~ -cpu_d_writedata[4] => ~NO_FANOUT~ -cpu_d_writedata[5] => ~NO_FANOUT~ -cpu_d_writedata[6] => ~NO_FANOUT~ -cpu_d_writedata[7] => ~NO_FANOUT~ -cpu_d_writedata[8] => ~NO_FANOUT~ -cpu_d_writedata[9] => ~NO_FANOUT~ -cpu_d_writedata[10] => ~NO_FANOUT~ -cpu_d_writedata[11] => ~NO_FANOUT~ -cpu_d_writedata[12] => ~NO_FANOUT~ -cpu_d_writedata[13] => ~NO_FANOUT~ -cpu_d_writedata[14] => ~NO_FANOUT~ -cpu_d_writedata[15] => ~NO_FANOUT~ -cpu_d_writedata[16] => ~NO_FANOUT~ -cpu_d_writedata[17] => ~NO_FANOUT~ -cpu_d_writedata[18] => ~NO_FANOUT~ -cpu_d_writedata[19] => ~NO_FANOUT~ -cpu_d_writedata[20] => ~NO_FANOUT~ -cpu_d_writedata[21] => ~NO_FANOUT~ -cpu_d_writedata[22] => ~NO_FANOUT~ -cpu_d_writedata[23] => ~NO_FANOUT~ -cpu_d_writedata[24] => ~NO_FANOUT~ -cpu_d_writedata[25] => ~NO_FANOUT~ -cpu_d_writedata[26] => ~NO_FANOUT~ -cpu_d_writedata[27] => ~NO_FANOUT~ -cpu_d_writedata[28] => ~NO_FANOUT~ -cpu_d_writedata[29] => ~NO_FANOUT~ -cpu_d_writedata[30] => ~NO_FANOUT~ -cpu_d_writedata[31] => ~NO_FANOUT~ -jrst_n => dtm[0]~reg0.ACLR -jrst_n => dtm[1]~reg0.ACLR -jrst_n => dtm[2]~reg0.ACLR -jrst_n => dtm[3]~reg0.ACLR -jrst_n => dtm[4]~reg0.ACLR -jrst_n => dtm[5]~reg0.ACLR -jrst_n => dtm[6]~reg0.ACLR -jrst_n => dtm[7]~reg0.ACLR -jrst_n => dtm[8]~reg0.ACLR -jrst_n => dtm[9]~reg0.ACLR -jrst_n => dtm[10]~reg0.ACLR -jrst_n => dtm[11]~reg0.ACLR -jrst_n => dtm[12]~reg0.ACLR -jrst_n => dtm[13]~reg0.ACLR -jrst_n => dtm[14]~reg0.ACLR -jrst_n => dtm[15]~reg0.ACLR -jrst_n => dtm[16]~reg0.ACLR -jrst_n => dtm[17]~reg0.ACLR -jrst_n => dtm[18]~reg0.ACLR -jrst_n => dtm[19]~reg0.ACLR -jrst_n => dtm[20]~reg0.ACLR -jrst_n => dtm[21]~reg0.ACLR -jrst_n => dtm[22]~reg0.ACLR -jrst_n => dtm[23]~reg0.ACLR -jrst_n => dtm[24]~reg0.ACLR -jrst_n => dtm[25]~reg0.ACLR -jrst_n => dtm[26]~reg0.ACLR -jrst_n => dtm[27]~reg0.ACLR -jrst_n => dtm[28]~reg0.ACLR -jrst_n => dtm[29]~reg0.ACLR -jrst_n => dtm[30]~reg0.ACLR -jrst_n => dtm[31]~reg0.ACLR -jrst_n => dtm[32]~reg0.ACLR -jrst_n => dtm[33]~reg0.ACLR -jrst_n => dtm[34]~reg0.ACLR -jrst_n => dtm[35]~reg0.ACLR -jrst_n => atm[0]~reg0.ACLR -jrst_n => atm[1]~reg0.ACLR -jrst_n => atm[2]~reg0.ACLR -jrst_n => atm[3]~reg0.ACLR -jrst_n => atm[4]~reg0.ACLR -jrst_n => atm[5]~reg0.ACLR -jrst_n => atm[6]~reg0.ACLR -jrst_n => atm[7]~reg0.ACLR -jrst_n => atm[8]~reg0.ACLR -jrst_n => atm[9]~reg0.ACLR -jrst_n => atm[10]~reg0.ACLR -jrst_n => atm[11]~reg0.ACLR -jrst_n => atm[12]~reg0.ACLR -jrst_n => atm[13]~reg0.ACLR -jrst_n => atm[14]~reg0.ACLR -jrst_n => atm[15]~reg0.ACLR -jrst_n => atm[16]~reg0.ACLR -jrst_n => atm[17]~reg0.ACLR -jrst_n => atm[18]~reg0.ACLR -jrst_n => atm[19]~reg0.ACLR -jrst_n => atm[20]~reg0.ACLR -jrst_n => atm[21]~reg0.ACLR -jrst_n => atm[22]~reg0.ACLR -jrst_n => atm[23]~reg0.ACLR -jrst_n => atm[24]~reg0.ACLR -jrst_n => atm[25]~reg0.ACLR -jrst_n => atm[26]~reg0.ACLR -jrst_n => atm[27]~reg0.ACLR -jrst_n => atm[28]~reg0.ACLR -jrst_n => atm[29]~reg0.ACLR -jrst_n => atm[30]~reg0.ACLR -jrst_n => atm[31]~reg0.ACLR -jrst_n => atm[32]~reg0.ACLR -jrst_n => atm[33]~reg0.ACLR -jrst_n => atm[34]~reg0.ACLR -jrst_n => atm[35]~reg0.ACLR -trc_ctrl[0] => trc_ctrl[0].IN1 -trc_ctrl[1] => trc_ctrl[1].IN1 -trc_ctrl[2] => trc_ctrl[2].IN1 -trc_ctrl[3] => trc_ctrl[3].IN1 -trc_ctrl[4] => trc_ctrl[4].IN1 -trc_ctrl[5] => trc_ctrl[5].IN1 -trc_ctrl[6] => trc_ctrl[6].IN1 -trc_ctrl[7] => trc_ctrl[7].IN1 -trc_ctrl[8] => trc_ctrl[8].IN1 -trc_ctrl[9] => ~NO_FANOUT~ -trc_ctrl[10] => ~NO_FANOUT~ -trc_ctrl[11] => ~NO_FANOUT~ -trc_ctrl[12] => ~NO_FANOUT~ -trc_ctrl[13] => ~NO_FANOUT~ -trc_ctrl[14] => ~NO_FANOUT~ -trc_ctrl[15] => ~NO_FANOUT~ -atm[0] <= atm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[1] <= atm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[2] <= atm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[3] <= atm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[4] <= atm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[5] <= atm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[6] <= atm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[7] <= atm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[8] <= atm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[9] <= atm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[10] <= atm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[11] <= atm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[12] <= atm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[13] <= atm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[14] <= atm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[15] <= atm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[16] <= atm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[17] <= atm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[18] <= atm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[19] <= atm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[20] <= atm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[21] <= atm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[22] <= atm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[23] <= atm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[24] <= atm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[25] <= atm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[26] <= atm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[27] <= atm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[28] <= atm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[29] <= atm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[30] <= atm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[31] <= atm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[32] <= atm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[33] <= atm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[34] <= atm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -atm[35] <= atm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[0] <= dtm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[1] <= dtm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[2] <= dtm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[3] <= dtm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[4] <= dtm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[5] <= dtm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[6] <= dtm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[7] <= dtm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[8] <= dtm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[9] <= dtm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[10] <= dtm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[11] <= dtm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[12] <= dtm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[13] <= dtm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[14] <= dtm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[15] <= dtm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[16] <= dtm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[17] <= dtm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[18] <= dtm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[19] <= dtm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[20] <= dtm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[21] <= dtm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[22] <= dtm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[23] <= dtm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[24] <= dtm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[25] <= dtm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[26] <= dtm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[27] <= dtm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[28] <= dtm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[29] <= dtm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[30] <= dtm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[31] <= dtm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[32] <= dtm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[33] <= dtm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[34] <= dtm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -dtm[35] <= dtm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode -ctrl[0] => ~NO_FANOUT~ -ctrl[1] => ~NO_FANOUT~ -ctrl[2] => ~NO_FANOUT~ -ctrl[3] => ~NO_FANOUT~ -ctrl[4] => ~NO_FANOUT~ -ctrl[5] => Decoder0.IN2 -ctrl[5] => td_mode[3].DATAIN -ctrl[6] => Decoder0.IN1 -ctrl[6] => Decoder1.IN1 -ctrl[6] => td_mode[2].DATAIN -ctrl[7] => Decoder0.IN0 -ctrl[7] => Decoder1.IN0 -ctrl[8] => ~NO_FANOUT~ -td_mode[0] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE -td_mode[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -td_mode[2] <= ctrl[6].DB_MAX_OUTPUT_PORT_TYPE -td_mode[3] <= ctrl[5].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo -atm[0] => ~NO_FANOUT~ -atm[1] => ~NO_FANOUT~ -atm[2] => ~NO_FANOUT~ -atm[3] => ~NO_FANOUT~ -atm[4] => ~NO_FANOUT~ -atm[5] => ~NO_FANOUT~ -atm[6] => ~NO_FANOUT~ -atm[7] => ~NO_FANOUT~ -atm[8] => ~NO_FANOUT~ -atm[9] => ~NO_FANOUT~ -atm[10] => ~NO_FANOUT~ -atm[11] => ~NO_FANOUT~ -atm[12] => ~NO_FANOUT~ -atm[13] => ~NO_FANOUT~ -atm[14] => ~NO_FANOUT~ -atm[15] => ~NO_FANOUT~ -atm[16] => ~NO_FANOUT~ -atm[17] => ~NO_FANOUT~ -atm[18] => ~NO_FANOUT~ -atm[19] => ~NO_FANOUT~ -atm[20] => ~NO_FANOUT~ -atm[21] => ~NO_FANOUT~ -atm[22] => ~NO_FANOUT~ -atm[23] => ~NO_FANOUT~ -atm[24] => ~NO_FANOUT~ -atm[25] => ~NO_FANOUT~ -atm[26] => ~NO_FANOUT~ -atm[27] => ~NO_FANOUT~ -atm[28] => ~NO_FANOUT~ -atm[29] => ~NO_FANOUT~ -atm[30] => ~NO_FANOUT~ -atm[31] => ~NO_FANOUT~ -atm[32] => WideOr1.IN0 -atm[33] => WideOr1.IN1 -atm[34] => WideOr1.IN2 -atm[35] => WideOr1.IN3 -clk => fifocount[0].CLK -clk => fifocount[1].CLK -clk => fifocount[2].CLK -clk => fifocount[3].CLK -clk => fifocount[4].CLK -dbrk_traceme => trc_this.IN1 -dbrk_traceoff => trc_this.IN0 -dbrk_traceon => trc_this.IN1 -dct_buffer[0] => dct_buffer[0].IN1 -dct_buffer[1] => dct_buffer[1].IN1 -dct_buffer[2] => dct_buffer[2].IN1 -dct_buffer[3] => dct_buffer[3].IN1 -dct_buffer[4] => dct_buffer[4].IN1 -dct_buffer[5] => dct_buffer[5].IN1 -dct_buffer[6] => dct_buffer[6].IN1 -dct_buffer[7] => dct_buffer[7].IN1 -dct_buffer[8] => dct_buffer[8].IN1 -dct_buffer[9] => dct_buffer[9].IN1 -dct_buffer[10] => dct_buffer[10].IN1 -dct_buffer[11] => dct_buffer[11].IN1 -dct_buffer[12] => dct_buffer[12].IN1 -dct_buffer[13] => dct_buffer[13].IN1 -dct_buffer[14] => dct_buffer[14].IN1 -dct_buffer[15] => dct_buffer[15].IN1 -dct_buffer[16] => dct_buffer[16].IN1 -dct_buffer[17] => dct_buffer[17].IN1 -dct_buffer[18] => dct_buffer[18].IN1 -dct_buffer[19] => dct_buffer[19].IN1 -dct_buffer[20] => dct_buffer[20].IN1 -dct_buffer[21] => dct_buffer[21].IN1 -dct_buffer[22] => dct_buffer[22].IN1 -dct_buffer[23] => dct_buffer[23].IN1 -dct_buffer[24] => dct_buffer[24].IN1 -dct_buffer[25] => dct_buffer[25].IN1 -dct_buffer[26] => dct_buffer[26].IN1 -dct_buffer[27] => dct_buffer[27].IN1 -dct_buffer[28] => dct_buffer[28].IN1 -dct_buffer[29] => dct_buffer[29].IN1 -dct_count[0] => dct_count[0].IN1 -dct_count[1] => dct_count[1].IN1 -dct_count[2] => dct_count[2].IN1 -dct_count[3] => dct_count[3].IN1 -dtm[0] => ~NO_FANOUT~ -dtm[1] => ~NO_FANOUT~ -dtm[2] => ~NO_FANOUT~ -dtm[3] => ~NO_FANOUT~ -dtm[4] => ~NO_FANOUT~ -dtm[5] => ~NO_FANOUT~ -dtm[6] => ~NO_FANOUT~ -dtm[7] => ~NO_FANOUT~ -dtm[8] => ~NO_FANOUT~ -dtm[9] => ~NO_FANOUT~ -dtm[10] => ~NO_FANOUT~ -dtm[11] => ~NO_FANOUT~ -dtm[12] => ~NO_FANOUT~ -dtm[13] => ~NO_FANOUT~ -dtm[14] => ~NO_FANOUT~ -dtm[15] => ~NO_FANOUT~ -dtm[16] => ~NO_FANOUT~ -dtm[17] => ~NO_FANOUT~ -dtm[18] => ~NO_FANOUT~ -dtm[19] => ~NO_FANOUT~ -dtm[20] => ~NO_FANOUT~ -dtm[21] => ~NO_FANOUT~ -dtm[22] => ~NO_FANOUT~ -dtm[23] => ~NO_FANOUT~ -dtm[24] => ~NO_FANOUT~ -dtm[25] => ~NO_FANOUT~ -dtm[26] => ~NO_FANOUT~ -dtm[27] => ~NO_FANOUT~ -dtm[28] => ~NO_FANOUT~ -dtm[29] => ~NO_FANOUT~ -dtm[30] => ~NO_FANOUT~ -dtm[31] => ~NO_FANOUT~ -dtm[32] => WideOr2.IN0 -dtm[33] => WideOr2.IN1 -dtm[34] => WideOr2.IN2 -dtm[35] => WideOr2.IN3 -itm[0] => tw[0].DATAIN -itm[1] => tw[1].DATAIN -itm[2] => tw[2].DATAIN -itm[3] => tw[3].DATAIN -itm[4] => tw[4].DATAIN -itm[5] => tw[5].DATAIN -itm[6] => tw[6].DATAIN -itm[7] => tw[7].DATAIN -itm[8] => tw[8].DATAIN -itm[9] => tw[9].DATAIN -itm[10] => tw[10].DATAIN -itm[11] => tw[11].DATAIN -itm[12] => tw[12].DATAIN -itm[13] => tw[13].DATAIN -itm[14] => tw[14].DATAIN -itm[15] => tw[15].DATAIN -itm[16] => tw[16].DATAIN -itm[17] => tw[17].DATAIN -itm[18] => tw[18].DATAIN -itm[19] => tw[19].DATAIN -itm[20] => tw[20].DATAIN -itm[21] => tw[21].DATAIN -itm[22] => tw[22].DATAIN -itm[23] => tw[23].DATAIN -itm[24] => tw[24].DATAIN -itm[25] => tw[25].DATAIN -itm[26] => tw[26].DATAIN -itm[27] => tw[27].DATAIN -itm[28] => tw[28].DATAIN -itm[29] => tw[29].DATAIN -itm[30] => tw[30].DATAIN -itm[31] => tw[31].DATAIN -itm[32] => WideOr0.IN0 -itm[32] => tw[32].DATAIN -itm[33] => WideOr0.IN1 -itm[33] => tw[33].DATAIN -itm[34] => WideOr0.IN2 -itm[34] => tw[34].DATAIN -itm[35] => WideOr0.IN3 -itm[35] => tw[35].DATAIN -jrst_n => fifocount[0].ACLR -jrst_n => fifocount[1].ACLR -jrst_n => fifocount[2].ACLR -jrst_n => fifocount[3].ACLR -jrst_n => fifocount[4].ACLR -reset_n => ~NO_FANOUT~ -test_ending => test_ending.IN1 -test_has_ended => test_has_ended.IN1 -trc_on => trc_this.IN1 -tw[0] <= itm[0].DB_MAX_OUTPUT_PORT_TYPE -tw[1] <= itm[1].DB_MAX_OUTPUT_PORT_TYPE -tw[2] <= itm[2].DB_MAX_OUTPUT_PORT_TYPE -tw[3] <= itm[3].DB_MAX_OUTPUT_PORT_TYPE -tw[4] <= itm[4].DB_MAX_OUTPUT_PORT_TYPE -tw[5] <= itm[5].DB_MAX_OUTPUT_PORT_TYPE -tw[6] <= itm[6].DB_MAX_OUTPUT_PORT_TYPE -tw[7] <= itm[7].DB_MAX_OUTPUT_PORT_TYPE -tw[8] <= itm[8].DB_MAX_OUTPUT_PORT_TYPE -tw[9] <= itm[9].DB_MAX_OUTPUT_PORT_TYPE -tw[10] <= itm[10].DB_MAX_OUTPUT_PORT_TYPE -tw[11] <= itm[11].DB_MAX_OUTPUT_PORT_TYPE -tw[12] <= itm[12].DB_MAX_OUTPUT_PORT_TYPE -tw[13] <= itm[13].DB_MAX_OUTPUT_PORT_TYPE -tw[14] <= itm[14].DB_MAX_OUTPUT_PORT_TYPE -tw[15] <= itm[15].DB_MAX_OUTPUT_PORT_TYPE -tw[16] <= itm[16].DB_MAX_OUTPUT_PORT_TYPE -tw[17] <= itm[17].DB_MAX_OUTPUT_PORT_TYPE -tw[18] <= itm[18].DB_MAX_OUTPUT_PORT_TYPE -tw[19] <= itm[19].DB_MAX_OUTPUT_PORT_TYPE -tw[20] <= itm[20].DB_MAX_OUTPUT_PORT_TYPE -tw[21] <= itm[21].DB_MAX_OUTPUT_PORT_TYPE -tw[22] <= itm[22].DB_MAX_OUTPUT_PORT_TYPE -tw[23] <= itm[23].DB_MAX_OUTPUT_PORT_TYPE -tw[24] <= itm[24].DB_MAX_OUTPUT_PORT_TYPE -tw[25] <= itm[25].DB_MAX_OUTPUT_PORT_TYPE -tw[26] <= itm[26].DB_MAX_OUTPUT_PORT_TYPE -tw[27] <= itm[27].DB_MAX_OUTPUT_PORT_TYPE -tw[28] <= itm[28].DB_MAX_OUTPUT_PORT_TYPE -tw[29] <= itm[29].DB_MAX_OUTPUT_PORT_TYPE -tw[30] <= itm[30].DB_MAX_OUTPUT_PORT_TYPE -tw[31] <= itm[31].DB_MAX_OUTPUT_PORT_TYPE -tw[32] <= itm[32].DB_MAX_OUTPUT_PORT_TYPE -tw[33] <= itm[33].DB_MAX_OUTPUT_PORT_TYPE -tw[34] <= itm[34].DB_MAX_OUTPUT_PORT_TYPE -tw[35] <= itm[35].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count -atm_valid => Decoder0.IN1 -dtm_valid => Decoder0.IN2 -itm_valid => Decoder0.IN0 -compute_tm_count[0] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE -compute_tm_count[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp -free2 => always0.IN1 -free3 => always0.IN1 -tm_count[0] => LessThan0.IN4 -tm_count[0] => LessThan1.IN4 -tm_count[0] => Equal0.IN1 -tm_count[1] => LessThan0.IN3 -tm_count[1] => LessThan1.IN3 -tm_count[1] => Equal0.IN0 -fifowp_inc[0] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE -fifowp_inc[1] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE -fifowp_inc[2] <= -fifowp_inc[3] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -empty => fifocount_inc.OUTPUTSELECT -free2 => always0.IN1 -free3 => always0.IN1 -tm_count[0] => LessThan0.IN4 -tm_count[0] => LessThan1.IN4 -tm_count[0] => fifocount_inc.DATAB -tm_count[0] => Equal0.IN1 -tm_count[1] => LessThan0.IN3 -tm_count[1] => LessThan1.IN3 -tm_count[1] => fifocount_inc.DATAB -tm_count[1] => Equal0.IN0 -fifocount_inc[0] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[1] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[2] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[3] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE -fifocount_inc[4] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench -dct_buffer[0] => ~NO_FANOUT~ -dct_buffer[1] => ~NO_FANOUT~ -dct_buffer[2] => ~NO_FANOUT~ -dct_buffer[3] => ~NO_FANOUT~ -dct_buffer[4] => ~NO_FANOUT~ -dct_buffer[5] => ~NO_FANOUT~ -dct_buffer[6] => ~NO_FANOUT~ -dct_buffer[7] => ~NO_FANOUT~ -dct_buffer[8] => ~NO_FANOUT~ -dct_buffer[9] => ~NO_FANOUT~ -dct_buffer[10] => ~NO_FANOUT~ -dct_buffer[11] => ~NO_FANOUT~ -dct_buffer[12] => ~NO_FANOUT~ -dct_buffer[13] => ~NO_FANOUT~ -dct_buffer[14] => ~NO_FANOUT~ -dct_buffer[15] => ~NO_FANOUT~ -dct_buffer[16] => ~NO_FANOUT~ -dct_buffer[17] => ~NO_FANOUT~ -dct_buffer[18] => ~NO_FANOUT~ -dct_buffer[19] => ~NO_FANOUT~ -dct_buffer[20] => ~NO_FANOUT~ -dct_buffer[21] => ~NO_FANOUT~ -dct_buffer[22] => ~NO_FANOUT~ -dct_buffer[23] => ~NO_FANOUT~ -dct_buffer[24] => ~NO_FANOUT~ -dct_buffer[25] => ~NO_FANOUT~ -dct_buffer[26] => ~NO_FANOUT~ -dct_buffer[27] => ~NO_FANOUT~ -dct_buffer[28] => ~NO_FANOUT~ -dct_buffer[29] => ~NO_FANOUT~ -dct_count[0] => ~NO_FANOUT~ -dct_count[1] => ~NO_FANOUT~ -dct_count[2] => ~NO_FANOUT~ -dct_count[3] => ~NO_FANOUT~ -test_ending => ~NO_FANOUT~ -test_has_ended => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib -clk => ~NO_FANOUT~ -clkx2 => ~NO_FANOUT~ -jrst_n => ~NO_FANOUT~ -tw[0] => ~NO_FANOUT~ -tw[1] => ~NO_FANOUT~ -tw[2] => ~NO_FANOUT~ -tw[3] => ~NO_FANOUT~ -tw[4] => ~NO_FANOUT~ -tw[5] => ~NO_FANOUT~ -tw[6] => ~NO_FANOUT~ -tw[7] => ~NO_FANOUT~ -tw[8] => ~NO_FANOUT~ -tw[9] => ~NO_FANOUT~ -tw[10] => ~NO_FANOUT~ -tw[11] => ~NO_FANOUT~ -tw[12] => ~NO_FANOUT~ -tw[13] => ~NO_FANOUT~ -tw[14] => ~NO_FANOUT~ -tw[15] => ~NO_FANOUT~ -tw[16] => ~NO_FANOUT~ -tw[17] => ~NO_FANOUT~ -tw[18] => ~NO_FANOUT~ -tw[19] => ~NO_FANOUT~ -tw[20] => ~NO_FANOUT~ -tw[21] => ~NO_FANOUT~ -tw[22] => ~NO_FANOUT~ -tw[23] => ~NO_FANOUT~ -tw[24] => ~NO_FANOUT~ -tw[25] => ~NO_FANOUT~ -tw[26] => ~NO_FANOUT~ -tw[27] => ~NO_FANOUT~ -tw[28] => ~NO_FANOUT~ -tw[29] => ~NO_FANOUT~ -tw[30] => ~NO_FANOUT~ -tw[31] => ~NO_FANOUT~ -tw[32] => ~NO_FANOUT~ -tw[33] => ~NO_FANOUT~ -tw[34] => ~NO_FANOUT~ -tw[35] => ~NO_FANOUT~ -tr_clk <= -tr_data[0] <= -tr_data[1] <= -tr_data[2] <= -tr_data[3] <= -tr_data[4] <= -tr_data[5] <= -tr_data[6] <= -tr_data[7] <= -tr_data[8] <= -tr_data[9] <= -tr_data[10] <= -tr_data[11] <= -tr_data[12] <= -tr_data[13] <= -tr_data[14] <= -tr_data[15] <= -tr_data[16] <= -tr_data[17] <= - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im -clk => trc_wrap~reg0.CLK -clk => trc_im_addr[0]~reg0.CLK -clk => trc_im_addr[1]~reg0.CLK -clk => trc_im_addr[2]~reg0.CLK -clk => trc_im_addr[3]~reg0.CLK -clk => trc_im_addr[4]~reg0.CLK -clk => trc_im_addr[5]~reg0.CLK -clk => trc_im_addr[6]~reg0.CLK -jdo[0] => ~NO_FANOUT~ -jdo[1] => ~NO_FANOUT~ -jdo[2] => ~NO_FANOUT~ -jdo[3] => ~NO_FANOUT~ -jdo[4] => ~NO_FANOUT~ -jdo[5] => ~NO_FANOUT~ -jdo[6] => ~NO_FANOUT~ -jdo[7] => ~NO_FANOUT~ -jdo[8] => ~NO_FANOUT~ -jdo[9] => ~NO_FANOUT~ -jdo[10] => ~NO_FANOUT~ -jdo[11] => ~NO_FANOUT~ -jdo[12] => ~NO_FANOUT~ -jdo[13] => ~NO_FANOUT~ -jdo[14] => ~NO_FANOUT~ -jdo[15] => ~NO_FANOUT~ -jdo[16] => ~NO_FANOUT~ -jdo[17] => ~NO_FANOUT~ -jdo[18] => ~NO_FANOUT~ -jdo[19] => ~NO_FANOUT~ -jdo[20] => ~NO_FANOUT~ -jdo[21] => ~NO_FANOUT~ -jdo[22] => ~NO_FANOUT~ -jdo[23] => ~NO_FANOUT~ -jdo[24] => ~NO_FANOUT~ -jdo[25] => ~NO_FANOUT~ -jdo[26] => ~NO_FANOUT~ -jdo[27] => ~NO_FANOUT~ -jdo[28] => ~NO_FANOUT~ -jdo[29] => ~NO_FANOUT~ -jdo[30] => ~NO_FANOUT~ -jdo[31] => ~NO_FANOUT~ -jdo[32] => ~NO_FANOUT~ -jdo[33] => ~NO_FANOUT~ -jdo[34] => ~NO_FANOUT~ -jdo[35] => ~NO_FANOUT~ -jdo[36] => ~NO_FANOUT~ -jdo[37] => ~NO_FANOUT~ -jrst_n => trc_wrap~reg0.ACLR -jrst_n => trc_im_addr[0]~reg0.ACLR -jrst_n => trc_im_addr[1]~reg0.ACLR -jrst_n => trc_im_addr[2]~reg0.ACLR -jrst_n => trc_im_addr[3]~reg0.ACLR -jrst_n => trc_im_addr[4]~reg0.ACLR -jrst_n => trc_im_addr[5]~reg0.ACLR -jrst_n => trc_im_addr[6]~reg0.ACLR -reset_n => ~NO_FANOUT~ -take_action_tracectrl => ~NO_FANOUT~ -take_action_tracemem_a => ~NO_FANOUT~ -take_action_tracemem_b => ~NO_FANOUT~ -take_no_action_tracemem_a => ~NO_FANOUT~ -trc_ctrl[0] => tracemem_on.DATAIN -trc_ctrl[0] => trc_enb.DATAIN -trc_ctrl[1] => ~NO_FANOUT~ -trc_ctrl[2] => ~NO_FANOUT~ -trc_ctrl[3] => ~NO_FANOUT~ -trc_ctrl[4] => ~NO_FANOUT~ -trc_ctrl[5] => ~NO_FANOUT~ -trc_ctrl[6] => ~NO_FANOUT~ -trc_ctrl[7] => ~NO_FANOUT~ -trc_ctrl[8] => ~NO_FANOUT~ -trc_ctrl[9] => ~NO_FANOUT~ -trc_ctrl[10] => xbrk_wrap_traceoff.IN1 -trc_ctrl[11] => ~NO_FANOUT~ -trc_ctrl[12] => ~NO_FANOUT~ -trc_ctrl[13] => ~NO_FANOUT~ -trc_ctrl[14] => ~NO_FANOUT~ -trc_ctrl[15] => ~NO_FANOUT~ -tw[0] => ~NO_FANOUT~ -tw[1] => ~NO_FANOUT~ -tw[2] => ~NO_FANOUT~ -tw[3] => ~NO_FANOUT~ -tw[4] => ~NO_FANOUT~ -tw[5] => ~NO_FANOUT~ -tw[6] => ~NO_FANOUT~ -tw[7] => ~NO_FANOUT~ -tw[8] => ~NO_FANOUT~ -tw[9] => ~NO_FANOUT~ -tw[10] => ~NO_FANOUT~ -tw[11] => ~NO_FANOUT~ -tw[12] => ~NO_FANOUT~ -tw[13] => ~NO_FANOUT~ -tw[14] => ~NO_FANOUT~ -tw[15] => ~NO_FANOUT~ -tw[16] => ~NO_FANOUT~ -tw[17] => ~NO_FANOUT~ -tw[18] => ~NO_FANOUT~ -tw[19] => ~NO_FANOUT~ -tw[20] => ~NO_FANOUT~ -tw[21] => ~NO_FANOUT~ -tw[22] => ~NO_FANOUT~ -tw[23] => ~NO_FANOUT~ -tw[24] => ~NO_FANOUT~ -tw[25] => ~NO_FANOUT~ -tw[26] => ~NO_FANOUT~ -tw[27] => ~NO_FANOUT~ -tw[28] => ~NO_FANOUT~ -tw[29] => ~NO_FANOUT~ -tw[30] => ~NO_FANOUT~ -tw[31] => ~NO_FANOUT~ -tw[32] => ~NO_FANOUT~ -tw[33] => ~NO_FANOUT~ -tw[34] => ~NO_FANOUT~ -tw[35] => ~NO_FANOUT~ -tracemem_on <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE -tracemem_trcdata[0] <= -tracemem_trcdata[1] <= -tracemem_trcdata[2] <= -tracemem_trcdata[3] <= -tracemem_trcdata[4] <= -tracemem_trcdata[5] <= -tracemem_trcdata[6] <= -tracemem_trcdata[7] <= -tracemem_trcdata[8] <= -tracemem_trcdata[9] <= -tracemem_trcdata[10] <= -tracemem_trcdata[11] <= -tracemem_trcdata[12] <= -tracemem_trcdata[13] <= -tracemem_trcdata[14] <= -tracemem_trcdata[15] <= -tracemem_trcdata[16] <= -tracemem_trcdata[17] <= -tracemem_trcdata[18] <= -tracemem_trcdata[19] <= -tracemem_trcdata[20] <= -tracemem_trcdata[21] <= -tracemem_trcdata[22] <= -tracemem_trcdata[23] <= -tracemem_trcdata[24] <= -tracemem_trcdata[25] <= -tracemem_trcdata[26] <= -tracemem_trcdata[27] <= -tracemem_trcdata[28] <= -tracemem_trcdata[29] <= -tracemem_trcdata[30] <= -tracemem_trcdata[31] <= -tracemem_trcdata[32] <= -tracemem_trcdata[33] <= -tracemem_trcdata[34] <= -tracemem_trcdata[35] <= -tracemem_tw <= tracemem_tw.DB_MAX_OUTPUT_PORT_TYPE -trc_enb <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[0] <= trc_im_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[1] <= trc_im_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[2] <= trc_im_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[3] <= trc_im_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[4] <= trc_im_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[5] <= trc_im_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_im_addr[6] <= trc_im_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -trc_wrap <= trc_wrap~reg0.DB_MAX_OUTPUT_PORT_TYPE -xbrk_wrap_traceoff <= xbrk_wrap_traceoff.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper -MonDReg[0] => MonDReg[0].IN1 -MonDReg[1] => MonDReg[1].IN1 -MonDReg[2] => MonDReg[2].IN1 -MonDReg[3] => MonDReg[3].IN1 -MonDReg[4] => MonDReg[4].IN1 -MonDReg[5] => MonDReg[5].IN1 -MonDReg[6] => MonDReg[6].IN1 -MonDReg[7] => MonDReg[7].IN1 -MonDReg[8] => MonDReg[8].IN1 -MonDReg[9] => MonDReg[9].IN1 -MonDReg[10] => MonDReg[10].IN1 -MonDReg[11] => MonDReg[11].IN1 -MonDReg[12] => MonDReg[12].IN1 -MonDReg[13] => MonDReg[13].IN1 -MonDReg[14] => MonDReg[14].IN1 -MonDReg[15] => MonDReg[15].IN1 -MonDReg[16] => MonDReg[16].IN1 -MonDReg[17] => MonDReg[17].IN1 -MonDReg[18] => MonDReg[18].IN1 -MonDReg[19] => MonDReg[19].IN1 -MonDReg[20] => MonDReg[20].IN1 -MonDReg[21] => MonDReg[21].IN1 -MonDReg[22] => MonDReg[22].IN1 -MonDReg[23] => MonDReg[23].IN1 -MonDReg[24] => MonDReg[24].IN1 -MonDReg[25] => MonDReg[25].IN1 -MonDReg[26] => MonDReg[26].IN1 -MonDReg[27] => MonDReg[27].IN1 -MonDReg[28] => MonDReg[28].IN1 -MonDReg[29] => MonDReg[29].IN1 -MonDReg[30] => MonDReg[30].IN1 -MonDReg[31] => MonDReg[31].IN1 -break_readreg[0] => break_readreg[0].IN1 -break_readreg[1] => break_readreg[1].IN1 -break_readreg[2] => break_readreg[2].IN1 -break_readreg[3] => break_readreg[3].IN1 -break_readreg[4] => break_readreg[4].IN1 -break_readreg[5] => break_readreg[5].IN1 -break_readreg[6] => break_readreg[6].IN1 -break_readreg[7] => break_readreg[7].IN1 -break_readreg[8] => break_readreg[8].IN1 -break_readreg[9] => break_readreg[9].IN1 -break_readreg[10] => break_readreg[10].IN1 -break_readreg[11] => break_readreg[11].IN1 -break_readreg[12] => break_readreg[12].IN1 -break_readreg[13] => break_readreg[13].IN1 -break_readreg[14] => break_readreg[14].IN1 -break_readreg[15] => break_readreg[15].IN1 -break_readreg[16] => break_readreg[16].IN1 -break_readreg[17] => break_readreg[17].IN1 -break_readreg[18] => break_readreg[18].IN1 -break_readreg[19] => break_readreg[19].IN1 -break_readreg[20] => break_readreg[20].IN1 -break_readreg[21] => break_readreg[21].IN1 -break_readreg[22] => break_readreg[22].IN1 -break_readreg[23] => break_readreg[23].IN1 -break_readreg[24] => break_readreg[24].IN1 -break_readreg[25] => break_readreg[25].IN1 -break_readreg[26] => break_readreg[26].IN1 -break_readreg[27] => break_readreg[27].IN1 -break_readreg[28] => break_readreg[28].IN1 -break_readreg[29] => break_readreg[29].IN1 -break_readreg[30] => break_readreg[30].IN1 -break_readreg[31] => break_readreg[31].IN1 -clk => clk.IN1 -dbrk_hit0_latch => dbrk_hit0_latch.IN1 -dbrk_hit1_latch => dbrk_hit1_latch.IN1 -dbrk_hit2_latch => dbrk_hit2_latch.IN1 -dbrk_hit3_latch => dbrk_hit3_latch.IN1 -debugack => debugack.IN1 -monitor_error => monitor_error.IN1 -monitor_ready => monitor_ready.IN1 -reset_n => reset_n.IN1 -resetlatch => resetlatch.IN1 -tracemem_on => tracemem_on.IN1 -tracemem_trcdata[0] => tracemem_trcdata[0].IN1 -tracemem_trcdata[1] => tracemem_trcdata[1].IN1 -tracemem_trcdata[2] => tracemem_trcdata[2].IN1 -tracemem_trcdata[3] => tracemem_trcdata[3].IN1 -tracemem_trcdata[4] => tracemem_trcdata[4].IN1 -tracemem_trcdata[5] => tracemem_trcdata[5].IN1 -tracemem_trcdata[6] => tracemem_trcdata[6].IN1 -tracemem_trcdata[7] => tracemem_trcdata[7].IN1 -tracemem_trcdata[8] => tracemem_trcdata[8].IN1 -tracemem_trcdata[9] => tracemem_trcdata[9].IN1 -tracemem_trcdata[10] => tracemem_trcdata[10].IN1 -tracemem_trcdata[11] => tracemem_trcdata[11].IN1 -tracemem_trcdata[12] => tracemem_trcdata[12].IN1 -tracemem_trcdata[13] => tracemem_trcdata[13].IN1 -tracemem_trcdata[14] => tracemem_trcdata[14].IN1 -tracemem_trcdata[15] => tracemem_trcdata[15].IN1 -tracemem_trcdata[16] => tracemem_trcdata[16].IN1 -tracemem_trcdata[17] => tracemem_trcdata[17].IN1 -tracemem_trcdata[18] => tracemem_trcdata[18].IN1 -tracemem_trcdata[19] => tracemem_trcdata[19].IN1 -tracemem_trcdata[20] => tracemem_trcdata[20].IN1 -tracemem_trcdata[21] => tracemem_trcdata[21].IN1 -tracemem_trcdata[22] => tracemem_trcdata[22].IN1 -tracemem_trcdata[23] => tracemem_trcdata[23].IN1 -tracemem_trcdata[24] => tracemem_trcdata[24].IN1 -tracemem_trcdata[25] => tracemem_trcdata[25].IN1 -tracemem_trcdata[26] => tracemem_trcdata[26].IN1 -tracemem_trcdata[27] => tracemem_trcdata[27].IN1 -tracemem_trcdata[28] => tracemem_trcdata[28].IN1 -tracemem_trcdata[29] => tracemem_trcdata[29].IN1 -tracemem_trcdata[30] => tracemem_trcdata[30].IN1 -tracemem_trcdata[31] => tracemem_trcdata[31].IN1 -tracemem_trcdata[32] => tracemem_trcdata[32].IN1 -tracemem_trcdata[33] => tracemem_trcdata[33].IN1 -tracemem_trcdata[34] => tracemem_trcdata[34].IN1 -tracemem_trcdata[35] => tracemem_trcdata[35].IN1 -tracemem_tw => tracemem_tw.IN1 -trc_im_addr[0] => trc_im_addr[0].IN1 -trc_im_addr[1] => trc_im_addr[1].IN1 -trc_im_addr[2] => trc_im_addr[2].IN1 -trc_im_addr[3] => trc_im_addr[3].IN1 -trc_im_addr[4] => trc_im_addr[4].IN1 -trc_im_addr[5] => trc_im_addr[5].IN1 -trc_im_addr[6] => trc_im_addr[6].IN1 -trc_on => trc_on.IN1 -trc_wrap => trc_wrap.IN1 -trigbrktype => trigbrktype.IN1 -trigger_state_1 => trigger_state_1.IN1 -jdo[0] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[1] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[2] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[3] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[4] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[5] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[6] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[7] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[8] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[9] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[10] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[11] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[12] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[13] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[14] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[15] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[16] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[17] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[18] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[19] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[20] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[21] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[22] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[23] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[24] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[25] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[26] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[27] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[28] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[29] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[30] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[31] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[32] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[33] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[34] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[35] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[36] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jdo[37] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo -jrst_n <= nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck.jrst_n -st_ready_test_idle <= nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck.st_ready_test_idle -take_action_break_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_a -take_action_break_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_b -take_action_break_c <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_c -take_action_ocimem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_ocimem_a -take_action_ocimem_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_ocimem_b -take_action_tracectrl <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracectrl -take_action_tracemem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracemem_a -take_action_tracemem_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracemem_b -take_no_action_break_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_a -take_no_action_break_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_b -take_no_action_break_c <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_c -take_no_action_ocimem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_ocimem_a -take_no_action_tracemem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_tracemem_a - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck -MonDReg[0] => Mux36.IN0 -MonDReg[1] => Mux35.IN0 -MonDReg[2] => Mux34.IN0 -MonDReg[3] => Mux33.IN0 -MonDReg[4] => Mux32.IN0 -MonDReg[5] => Mux31.IN0 -MonDReg[6] => Mux30.IN0 -MonDReg[7] => Mux29.IN0 -MonDReg[8] => Mux28.IN1 -MonDReg[9] => Mux27.IN1 -MonDReg[10] => Mux26.IN1 -MonDReg[11] => Mux25.IN1 -MonDReg[12] => Mux24.IN1 -MonDReg[13] => Mux23.IN1 -MonDReg[14] => Mux22.IN1 -MonDReg[15] => Mux21.IN1 -MonDReg[16] => Mux20.IN1 -MonDReg[17] => Mux19.IN1 -MonDReg[18] => Mux18.IN1 -MonDReg[19] => Mux17.IN1 -MonDReg[20] => Mux16.IN1 -MonDReg[21] => Mux15.IN1 -MonDReg[22] => Mux14.IN1 -MonDReg[23] => Mux13.IN1 -MonDReg[24] => Mux12.IN1 -MonDReg[25] => Mux11.IN1 -MonDReg[26] => Mux10.IN1 -MonDReg[27] => Mux9.IN1 -MonDReg[28] => Mux8.IN1 -MonDReg[29] => Mux7.IN1 -MonDReg[30] => Mux6.IN1 -MonDReg[31] => Mux5.IN1 -break_readreg[0] => Mux36.IN1 -break_readreg[1] => Mux35.IN1 -break_readreg[2] => Mux34.IN1 -break_readreg[3] => Mux33.IN1 -break_readreg[4] => Mux32.IN1 -break_readreg[5] => Mux31.IN1 -break_readreg[6] => Mux30.IN1 -break_readreg[7] => Mux29.IN1 -break_readreg[8] => Mux28.IN2 -break_readreg[9] => Mux27.IN2 -break_readreg[10] => Mux26.IN2 -break_readreg[11] => Mux25.IN2 -break_readreg[12] => Mux24.IN2 -break_readreg[13] => Mux23.IN2 -break_readreg[14] => Mux22.IN2 -break_readreg[15] => Mux21.IN2 -break_readreg[16] => Mux20.IN2 -break_readreg[17] => Mux19.IN2 -break_readreg[18] => Mux18.IN2 -break_readreg[19] => Mux17.IN2 -break_readreg[20] => Mux16.IN2 -break_readreg[21] => Mux15.IN2 -break_readreg[22] => Mux14.IN2 -break_readreg[23] => Mux13.IN2 -break_readreg[24] => Mux12.IN2 -break_readreg[25] => Mux11.IN2 -break_readreg[26] => Mux10.IN2 -break_readreg[27] => Mux9.IN2 -break_readreg[28] => Mux8.IN2 -break_readreg[29] => Mux7.IN2 -break_readreg[30] => Mux6.IN2 -break_readreg[31] => Mux5.IN2 -dbrk_hit0_latch => Mux4.IN1 -dbrk_hit1_latch => Mux3.IN1 -dbrk_hit2_latch => Mux2.IN1 -dbrk_hit3_latch => Mux1.IN2 -debugack => debugack.IN1 -ir_in[0] => Mux0.IN3 -ir_in[0] => Mux1.IN4 -ir_in[0] => Mux2.IN3 -ir_in[0] => Mux3.IN3 -ir_in[0] => Mux4.IN3 -ir_in[0] => Mux5.IN4 -ir_in[0] => Mux6.IN4 -ir_in[0] => Mux7.IN4 -ir_in[0] => Mux8.IN4 -ir_in[0] => Mux9.IN4 -ir_in[0] => Mux10.IN4 -ir_in[0] => Mux11.IN4 -ir_in[0] => Mux12.IN4 -ir_in[0] => Mux13.IN4 -ir_in[0] => Mux14.IN4 -ir_in[0] => Mux15.IN4 -ir_in[0] => Mux16.IN4 -ir_in[0] => Mux17.IN4 -ir_in[0] => Mux18.IN4 -ir_in[0] => Mux19.IN4 -ir_in[0] => Mux20.IN4 -ir_in[0] => Mux21.IN4 -ir_in[0] => Mux22.IN4 -ir_in[0] => Mux23.IN4 -ir_in[0] => Mux24.IN4 -ir_in[0] => Mux25.IN4 -ir_in[0] => Mux26.IN4 -ir_in[0] => Mux27.IN4 -ir_in[0] => Mux28.IN4 -ir_in[0] => Mux29.IN3 -ir_in[0] => Mux30.IN3 -ir_in[0] => Mux31.IN3 -ir_in[0] => Mux32.IN3 -ir_in[0] => Mux33.IN3 -ir_in[0] => Mux34.IN3 -ir_in[0] => Mux35.IN3 -ir_in[0] => Mux36.IN3 -ir_in[0] => Mux37.IN1 -ir_in[0] => Decoder0.IN1 -ir_in[1] => Mux0.IN2 -ir_in[1] => Mux1.IN3 -ir_in[1] => Mux2.IN2 -ir_in[1] => Mux3.IN2 -ir_in[1] => Mux4.IN2 -ir_in[1] => Mux5.IN3 -ir_in[1] => Mux6.IN3 -ir_in[1] => Mux7.IN3 -ir_in[1] => Mux8.IN3 -ir_in[1] => Mux9.IN3 -ir_in[1] => Mux10.IN3 -ir_in[1] => Mux11.IN3 -ir_in[1] => Mux12.IN3 -ir_in[1] => Mux13.IN3 -ir_in[1] => Mux14.IN3 -ir_in[1] => Mux15.IN3 -ir_in[1] => Mux16.IN3 -ir_in[1] => Mux17.IN3 -ir_in[1] => Mux18.IN3 -ir_in[1] => Mux19.IN3 -ir_in[1] => Mux20.IN3 -ir_in[1] => Mux21.IN3 -ir_in[1] => Mux22.IN3 -ir_in[1] => Mux23.IN3 -ir_in[1] => Mux24.IN3 -ir_in[1] => Mux25.IN3 -ir_in[1] => Mux26.IN3 -ir_in[1] => Mux27.IN3 -ir_in[1] => Mux28.IN3 -ir_in[1] => Mux29.IN2 -ir_in[1] => Mux30.IN2 -ir_in[1] => Mux31.IN2 -ir_in[1] => Mux32.IN2 -ir_in[1] => Mux33.IN2 -ir_in[1] => Mux34.IN2 -ir_in[1] => Mux35.IN2 -ir_in[1] => Mux36.IN2 -ir_in[1] => Mux37.IN0 -ir_in[1] => Decoder0.IN0 -jtag_state_rti => st_ready_test_idle.DATAIN -monitor_error => Mux3.IN4 -monitor_ready => monitor_ready.IN1 -reset_n => ~NO_FANOUT~ -resetlatch => Mux4.IN4 -tck => tck.IN2 -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tdi => sr.DATAB -tracemem_on => Mux1.IN5 -tracemem_trcdata[0] => Mux37.IN2 -tracemem_trcdata[1] => Mux36.IN4 -tracemem_trcdata[2] => Mux35.IN4 -tracemem_trcdata[3] => Mux34.IN4 -tracemem_trcdata[4] => Mux33.IN4 -tracemem_trcdata[5] => Mux32.IN4 -tracemem_trcdata[6] => Mux31.IN4 -tracemem_trcdata[7] => Mux30.IN4 -tracemem_trcdata[8] => Mux29.IN4 -tracemem_trcdata[9] => Mux28.IN5 -tracemem_trcdata[10] => Mux27.IN5 -tracemem_trcdata[11] => Mux26.IN5 -tracemem_trcdata[12] => Mux25.IN5 -tracemem_trcdata[13] => Mux24.IN5 -tracemem_trcdata[14] => Mux23.IN5 -tracemem_trcdata[15] => Mux22.IN5 -tracemem_trcdata[16] => Mux21.IN5 -tracemem_trcdata[17] => Mux20.IN5 -tracemem_trcdata[18] => Mux19.IN5 -tracemem_trcdata[19] => Mux18.IN5 -tracemem_trcdata[20] => Mux17.IN5 -tracemem_trcdata[21] => Mux16.IN5 -tracemem_trcdata[22] => Mux15.IN5 -tracemem_trcdata[23] => Mux14.IN5 -tracemem_trcdata[24] => Mux13.IN5 -tracemem_trcdata[25] => Mux12.IN5 -tracemem_trcdata[26] => Mux11.IN5 -tracemem_trcdata[27] => Mux10.IN5 -tracemem_trcdata[28] => Mux9.IN5 -tracemem_trcdata[29] => Mux8.IN5 -tracemem_trcdata[30] => Mux7.IN5 -tracemem_trcdata[31] => Mux6.IN5 -tracemem_trcdata[32] => Mux5.IN5 -tracemem_trcdata[33] => Mux4.IN5 -tracemem_trcdata[34] => Mux3.IN5 -tracemem_trcdata[35] => Mux2.IN4 -tracemem_tw => Mux0.IN4 -trc_im_addr[0] => Mux35.IN5 -trc_im_addr[1] => Mux34.IN5 -trc_im_addr[2] => Mux33.IN5 -trc_im_addr[3] => Mux32.IN5 -trc_im_addr[4] => Mux31.IN5 -trc_im_addr[5] => Mux30.IN5 -trc_im_addr[6] => Mux29.IN5 -trc_on => Mux37.IN3 -trc_wrap => Mux36.IN5 -trigbrktype => Mux37.IN4 -trigger_state_1 => Mux0.IN5 -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_cdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_sdr => sr.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -vs_uir => DRsize.OUTPUTSELECT -ir_out[0] <= ir_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -ir_out[1] <= ir_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jrst_n <= unxcomplemented_resetxx2.DB_MAX_OUTPUT_PORT_TYPE -sr[0] <= sr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[1] <= sr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[2] <= sr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[3] <= sr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[4] <= sr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[5] <= sr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[6] <= sr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[7] <= sr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[8] <= sr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[9] <= sr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[10] <= sr[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[11] <= sr[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[12] <= sr[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[13] <= sr[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[14] <= sr[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[15] <= sr[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[16] <= sr[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[17] <= sr[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[18] <= sr[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[19] <= sr[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[20] <= sr[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[21] <= sr[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[22] <= sr[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[23] <= sr[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[24] <= sr[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[25] <= sr[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[26] <= sr[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[27] <= sr[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[28] <= sr[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[29] <= sr[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[30] <= sr[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[31] <= sr[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[32] <= sr[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[33] <= sr[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[34] <= sr[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[35] <= sr[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[36] <= sr[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -sr[37] <= sr[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -st_ready_test_idle <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE -tdo <= tdo.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk -clk => clk.IN2 -ir_in[0] => ir[0].DATAIN -ir_in[1] => ir[1].DATAIN -sr[0] => jdo[0]~reg0.DATAIN -sr[1] => jdo[1]~reg0.DATAIN -sr[2] => jdo[2]~reg0.DATAIN -sr[3] => jdo[3]~reg0.DATAIN -sr[4] => jdo[4]~reg0.DATAIN -sr[5] => jdo[5]~reg0.DATAIN -sr[6] => jdo[6]~reg0.DATAIN -sr[7] => jdo[7]~reg0.DATAIN -sr[8] => jdo[8]~reg0.DATAIN -sr[9] => jdo[9]~reg0.DATAIN -sr[10] => jdo[10]~reg0.DATAIN -sr[11] => jdo[11]~reg0.DATAIN -sr[12] => jdo[12]~reg0.DATAIN -sr[13] => jdo[13]~reg0.DATAIN -sr[14] => jdo[14]~reg0.DATAIN -sr[15] => jdo[15]~reg0.DATAIN -sr[16] => jdo[16]~reg0.DATAIN -sr[17] => jdo[17]~reg0.DATAIN -sr[18] => jdo[18]~reg0.DATAIN -sr[19] => jdo[19]~reg0.DATAIN -sr[20] => jdo[20]~reg0.DATAIN -sr[21] => jdo[21]~reg0.DATAIN -sr[22] => jdo[22]~reg0.DATAIN -sr[23] => jdo[23]~reg0.DATAIN -sr[24] => jdo[24]~reg0.DATAIN -sr[25] => jdo[25]~reg0.DATAIN -sr[26] => jdo[26]~reg0.DATAIN -sr[27] => jdo[27]~reg0.DATAIN -sr[28] => jdo[28]~reg0.DATAIN -sr[29] => jdo[29]~reg0.DATAIN -sr[30] => jdo[30]~reg0.DATAIN -sr[31] => jdo[31]~reg0.DATAIN -sr[32] => jdo[32]~reg0.DATAIN -sr[33] => jdo[33]~reg0.DATAIN -sr[34] => jdo[34]~reg0.DATAIN -sr[35] => jdo[35]~reg0.DATAIN -sr[36] => jdo[36]~reg0.DATAIN -sr[37] => jdo[37]~reg0.DATAIN -vs_udr => vs_udr.IN1 -vs_uir => vs_uir.IN1 -jdo[0] <= jdo[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[1] <= jdo[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[2] <= jdo[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[3] <= jdo[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[4] <= jdo[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[5] <= jdo[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[6] <= jdo[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[7] <= jdo[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[8] <= jdo[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[9] <= jdo[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[10] <= jdo[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[11] <= jdo[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[12] <= jdo[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[13] <= jdo[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[14] <= jdo[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[15] <= jdo[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[16] <= jdo[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[17] <= jdo[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[18] <= jdo[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[19] <= jdo[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[20] <= jdo[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[21] <= jdo[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[22] <= jdo[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[23] <= jdo[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[24] <= jdo[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[25] <= jdo[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[26] <= jdo[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[27] <= jdo[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[28] <= jdo[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[29] <= jdo[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[30] <= jdo[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[31] <= jdo[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[32] <= jdo[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[33] <= jdo[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[34] <= jdo[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[35] <= jdo[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[36] <= jdo[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE -jdo[37] <= jdo[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE -take_action_break_a <= take_action_break_a.DB_MAX_OUTPUT_PORT_TYPE -take_action_break_b <= take_action_break_b.DB_MAX_OUTPUT_PORT_TYPE -take_action_break_c <= take_action_break_c.DB_MAX_OUTPUT_PORT_TYPE -take_action_ocimem_a <= take_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE -take_action_ocimem_b <= take_action_ocimem_b.DB_MAX_OUTPUT_PORT_TYPE -take_action_tracectrl <= take_action_tracectrl.DB_MAX_OUTPUT_PORT_TYPE -take_action_tracemem_a <= take_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE -take_action_tracemem_b <= take_action_tracemem_b.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_break_a <= take_no_action_break_a.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_break_b <= take_no_action_break_b.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_break_c <= take_no_action_break_c.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_ocimem_a <= take_no_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE -take_no_action_tracemem_a <= take_no_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 -clk => dreg[0].CLK -clk => din_s1.CLK -reset_n => dreg[0].ACLR -reset_n => din_s1.ACLR -din => din_s1.DATAIN -dout <= dout.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy -tck <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tck -tdi <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tdi -ir_in[0] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in -ir_in[1] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in -tdo => tdo.IN1 -ir_out[0] => ir_out[0].IN1 -ir_out[1] => ir_out[1].IN1 -virtual_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cdr -virtual_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_sdr -virtual_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e1dr -virtual_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_pdr -virtual_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e2dr -virtual_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_udr -virtual_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cir -virtual_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_uir -tms <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tms -jtag_state_tlr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_tlr -jtag_state_rti <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_rti -jtag_state_sdrs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdrs -jtag_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cdr -jtag_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdr -jtag_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1dr -jtag_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pdr -jtag_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2dr -jtag_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_udr -jtag_state_sirs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sirs -jtag_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cir -jtag_state_sir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sir -jtag_state_e1ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1ir -jtag_state_pir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pir -jtag_state_e2ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2ir -jtag_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_uir - - -|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst -usr_tck <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE -usr_tdi <= tdi.DB_MAX_OUTPUT_PORT_TYPE -usr_ir_in[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE -usr_ir_in[1] <= ir_in[1].DB_MAX_OUTPUT_PORT_TYPE -usr_tdo => tdo.DATAIN -usr_ir_out[0] => ir_out[0].DATAIN -usr_ir_out[1] => ir_out[1].DATAIN -usr_virtual_state_cdr <= virtual_state_cdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_sdr <= virtual_state_sdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_e1dr <= virtual_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_pdr <= virtual_state_pdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_e2dr <= virtual_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_udr <= virtual_state_udr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_cir <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE -usr_virtual_state_uir <= virtual_state_uir.DB_MAX_OUTPUT_PORT_TYPE -usr_tms <= raw_tms.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_tlr <= jtag_state_tlr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_rti <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sdrs <= jtag_state_sdrs.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_cdr <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sdr <= jtag_state_sdr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e1dr <= jtag_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_pdr <= jtag_state_pdr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e2dr <= jtag_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_udr <= jtag_state_udr.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sirs <= jtag_state_sirs.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_cir <= jtag_state_cir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_sir <= jtag_state_sir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e1ir <= jtag_state_e1ir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_pir <= jtag_state_pir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_e2ir <= jtag_state_e2ir.DB_MAX_OUTPUT_PORT_TYPE -usr_jtag_state_uir <= jtag_state_uir.DB_MAX_OUTPUT_PORT_TYPE -raw_tck => usr_tck.DATAIN -raw_tms => usr_tms.DATAIN -tdi => usr_tdi.DATAIN -jtag_state_tlr => usr_jtag_state_tlr.DATAIN -jtag_state_rti => usr_jtag_state_rti.DATAIN -jtag_state_sdrs => usr_jtag_state_sdrs.DATAIN -jtag_state_cdr => virtual_state_cdr.IN1 -jtag_state_cdr => usr_virtual_state_cir.DATAIN -jtag_state_cdr => usr_jtag_state_cdr.DATAIN -jtag_state_sdr => virtual_state_sdr.IN1 -jtag_state_sdr => usr_jtag_state_sdr.DATAIN -jtag_state_e1dr => virtual_state_e1dr.IN1 -jtag_state_e1dr => usr_jtag_state_e1dr.DATAIN -jtag_state_pdr => virtual_state_pdr.IN1 -jtag_state_pdr => usr_jtag_state_pdr.DATAIN -jtag_state_e2dr => virtual_state_e2dr.IN1 -jtag_state_e2dr => usr_jtag_state_e2dr.DATAIN -jtag_state_udr => virtual_state_udr.IN1 -jtag_state_udr => virtual_state_uir.IN1 -jtag_state_udr => usr_jtag_state_udr.DATAIN -jtag_state_sirs => usr_jtag_state_sirs.DATAIN -jtag_state_cir => usr_jtag_state_cir.DATAIN -jtag_state_sir => usr_jtag_state_sir.DATAIN -jtag_state_e1ir => usr_jtag_state_e1ir.DATAIN -jtag_state_pir => usr_jtag_state_pir.DATAIN -jtag_state_e2ir => usr_jtag_state_e2ir.DATAIN -jtag_state_uir => usr_jtag_state_uir.DATAIN -usr1 => virtual_ir_scan.IN0 -usr1 => virtual_dr_scan.IN0 -clr => ~NO_FANOUT~ -ena => virtual_dr_scan.IN1 -ena => virtual_ir_scan.IN1 -ir_in[0] => usr_ir_in[0].DATAIN -ir_in[1] => usr_ir_in[1].DATAIN -tdo <= usr_tdo.DB_MAX_OUTPUT_PORT_TYPE -ir_out[0] <= usr_ir_out[0].DB_MAX_OUTPUT_PORT_TYPE -ir_out[1] <= usr_ir_out[1].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory -address[0] => address[0].IN1 -address[1] => address[1].IN1 -address[2] => address[2].IN1 -address[3] => address[3].IN1 -address[4] => address[4].IN1 -address[5] => address[5].IN1 -address[6] => address[6].IN1 -address[7] => address[7].IN1 -address[8] => address[8].IN1 -address[9] => address[9].IN1 -address[10] => address[10].IN1 -address[11] => address[11].IN1 -address[12] => address[12].IN1 -address[13] => address[13].IN1 -address[14] => address[14].IN1 -address[15] => address[15].IN1 -byteenable[0] => byteenable[0].IN1 -byteenable[1] => byteenable[1].IN1 -byteenable[2] => byteenable[2].IN1 -byteenable[3] => byteenable[3].IN1 -chipselect => wren.IN0 -clk => clk.IN1 -clken => clocken0.IN0 -reset => ~NO_FANOUT~ -reset_req => clocken0.IN1 -write => wren.IN1 -writedata[0] => writedata[0].IN1 -writedata[1] => writedata[1].IN1 -writedata[2] => writedata[2].IN1 -writedata[3] => writedata[3].IN1 -writedata[4] => writedata[4].IN1 -writedata[5] => writedata[5].IN1 -writedata[6] => writedata[6].IN1 -writedata[7] => writedata[7].IN1 -writedata[8] => writedata[8].IN1 -writedata[9] => writedata[9].IN1 -writedata[10] => writedata[10].IN1 -writedata[11] => writedata[11].IN1 -writedata[12] => writedata[12].IN1 -writedata[13] => writedata[13].IN1 -writedata[14] => writedata[14].IN1 -writedata[15] => writedata[15].IN1 -writedata[16] => writedata[16].IN1 -writedata[17] => writedata[17].IN1 -writedata[18] => writedata[18].IN1 -writedata[19] => writedata[19].IN1 -writedata[20] => writedata[20].IN1 -writedata[21] => writedata[21].IN1 -writedata[22] => writedata[22].IN1 -writedata[23] => writedata[23].IN1 -writedata[24] => writedata[24].IN1 -writedata[25] => writedata[25].IN1 -writedata[26] => writedata[26].IN1 -writedata[27] => writedata[27].IN1 -writedata[28] => writedata[28].IN1 -writedata[29] => writedata[29].IN1 -writedata[30] => writedata[30].IN1 -writedata[31] => writedata[31].IN1 -readdata[0] <= altsyncram:the_altsyncram.q_a -readdata[1] <= altsyncram:the_altsyncram.q_a -readdata[2] <= altsyncram:the_altsyncram.q_a -readdata[3] <= altsyncram:the_altsyncram.q_a -readdata[4] <= altsyncram:the_altsyncram.q_a -readdata[5] <= altsyncram:the_altsyncram.q_a -readdata[6] <= altsyncram:the_altsyncram.q_a -readdata[7] <= altsyncram:the_altsyncram.q_a -readdata[8] <= altsyncram:the_altsyncram.q_a -readdata[9] <= altsyncram:the_altsyncram.q_a -readdata[10] <= altsyncram:the_altsyncram.q_a -readdata[11] <= altsyncram:the_altsyncram.q_a -readdata[12] <= altsyncram:the_altsyncram.q_a -readdata[13] <= altsyncram:the_altsyncram.q_a -readdata[14] <= altsyncram:the_altsyncram.q_a -readdata[15] <= altsyncram:the_altsyncram.q_a -readdata[16] <= altsyncram:the_altsyncram.q_a -readdata[17] <= altsyncram:the_altsyncram.q_a -readdata[18] <= altsyncram:the_altsyncram.q_a -readdata[19] <= altsyncram:the_altsyncram.q_a -readdata[20] <= altsyncram:the_altsyncram.q_a -readdata[21] <= altsyncram:the_altsyncram.q_a -readdata[22] <= altsyncram:the_altsyncram.q_a -readdata[23] <= altsyncram:the_altsyncram.q_a -readdata[24] <= altsyncram:the_altsyncram.q_a -readdata[25] <= altsyncram:the_altsyncram.q_a -readdata[26] <= altsyncram:the_altsyncram.q_a -readdata[27] <= altsyncram:the_altsyncram.q_a -readdata[28] <= altsyncram:the_altsyncram.q_a -readdata[29] <= altsyncram:the_altsyncram.q_a -readdata[30] <= altsyncram:the_altsyncram.q_a -readdata[31] <= altsyncram:the_altsyncram.q_a - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram -wren_a => altsyncram_4ed1:auto_generated.wren_a -rden_a => ~NO_FANOUT~ -wren_b => ~NO_FANOUT~ -rden_b => ~NO_FANOUT~ -data_a[0] => altsyncram_4ed1:auto_generated.data_a[0] -data_a[1] => altsyncram_4ed1:auto_generated.data_a[1] -data_a[2] => altsyncram_4ed1:auto_generated.data_a[2] -data_a[3] => altsyncram_4ed1:auto_generated.data_a[3] -data_a[4] => altsyncram_4ed1:auto_generated.data_a[4] -data_a[5] => altsyncram_4ed1:auto_generated.data_a[5] -data_a[6] => altsyncram_4ed1:auto_generated.data_a[6] -data_a[7] => altsyncram_4ed1:auto_generated.data_a[7] -data_a[8] => altsyncram_4ed1:auto_generated.data_a[8] -data_a[9] => altsyncram_4ed1:auto_generated.data_a[9] -data_a[10] => altsyncram_4ed1:auto_generated.data_a[10] -data_a[11] => altsyncram_4ed1:auto_generated.data_a[11] -data_a[12] => altsyncram_4ed1:auto_generated.data_a[12] -data_a[13] => altsyncram_4ed1:auto_generated.data_a[13] -data_a[14] => altsyncram_4ed1:auto_generated.data_a[14] -data_a[15] => altsyncram_4ed1:auto_generated.data_a[15] -data_a[16] => altsyncram_4ed1:auto_generated.data_a[16] -data_a[17] => altsyncram_4ed1:auto_generated.data_a[17] -data_a[18] => altsyncram_4ed1:auto_generated.data_a[18] -data_a[19] => altsyncram_4ed1:auto_generated.data_a[19] -data_a[20] => altsyncram_4ed1:auto_generated.data_a[20] -data_a[21] => altsyncram_4ed1:auto_generated.data_a[21] -data_a[22] => altsyncram_4ed1:auto_generated.data_a[22] -data_a[23] => altsyncram_4ed1:auto_generated.data_a[23] -data_a[24] => altsyncram_4ed1:auto_generated.data_a[24] -data_a[25] => altsyncram_4ed1:auto_generated.data_a[25] -data_a[26] => altsyncram_4ed1:auto_generated.data_a[26] -data_a[27] => altsyncram_4ed1:auto_generated.data_a[27] -data_a[28] => altsyncram_4ed1:auto_generated.data_a[28] -data_a[29] => altsyncram_4ed1:auto_generated.data_a[29] -data_a[30] => altsyncram_4ed1:auto_generated.data_a[30] -data_a[31] => altsyncram_4ed1:auto_generated.data_a[31] -data_b[0] => ~NO_FANOUT~ -address_a[0] => altsyncram_4ed1:auto_generated.address_a[0] -address_a[1] => altsyncram_4ed1:auto_generated.address_a[1] -address_a[2] => altsyncram_4ed1:auto_generated.address_a[2] -address_a[3] => altsyncram_4ed1:auto_generated.address_a[3] -address_a[4] => altsyncram_4ed1:auto_generated.address_a[4] -address_a[5] => altsyncram_4ed1:auto_generated.address_a[5] -address_a[6] => altsyncram_4ed1:auto_generated.address_a[6] -address_a[7] => altsyncram_4ed1:auto_generated.address_a[7] -address_a[8] => altsyncram_4ed1:auto_generated.address_a[8] -address_a[9] => altsyncram_4ed1:auto_generated.address_a[9] -address_a[10] => altsyncram_4ed1:auto_generated.address_a[10] -address_a[11] => altsyncram_4ed1:auto_generated.address_a[11] -address_a[12] => altsyncram_4ed1:auto_generated.address_a[12] -address_a[13] => altsyncram_4ed1:auto_generated.address_a[13] -address_a[14] => altsyncram_4ed1:auto_generated.address_a[14] -address_a[15] => altsyncram_4ed1:auto_generated.address_a[15] -address_b[0] => ~NO_FANOUT~ -addressstall_a => ~NO_FANOUT~ -addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_4ed1:auto_generated.clock0 -clock1 => ~NO_FANOUT~ -clocken0 => altsyncram_4ed1:auto_generated.clocken0 -clocken1 => ~NO_FANOUT~ -clocken2 => ~NO_FANOUT~ -clocken3 => ~NO_FANOUT~ -aclr0 => ~NO_FANOUT~ -aclr1 => ~NO_FANOUT~ -byteena_a[0] => altsyncram_4ed1:auto_generated.byteena_a[0] -byteena_a[1] => altsyncram_4ed1:auto_generated.byteena_a[1] -byteena_a[2] => altsyncram_4ed1:auto_generated.byteena_a[2] -byteena_a[3] => altsyncram_4ed1:auto_generated.byteena_a[3] -byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= altsyncram_4ed1:auto_generated.q_a[0] -q_a[1] <= altsyncram_4ed1:auto_generated.q_a[1] -q_a[2] <= altsyncram_4ed1:auto_generated.q_a[2] -q_a[3] <= altsyncram_4ed1:auto_generated.q_a[3] -q_a[4] <= altsyncram_4ed1:auto_generated.q_a[4] -q_a[5] <= altsyncram_4ed1:auto_generated.q_a[5] -q_a[6] <= altsyncram_4ed1:auto_generated.q_a[6] -q_a[7] <= altsyncram_4ed1:auto_generated.q_a[7] -q_a[8] <= altsyncram_4ed1:auto_generated.q_a[8] -q_a[9] <= altsyncram_4ed1:auto_generated.q_a[9] -q_a[10] <= altsyncram_4ed1:auto_generated.q_a[10] -q_a[11] <= altsyncram_4ed1:auto_generated.q_a[11] -q_a[12] <= altsyncram_4ed1:auto_generated.q_a[12] -q_a[13] <= altsyncram_4ed1:auto_generated.q_a[13] -q_a[14] <= altsyncram_4ed1:auto_generated.q_a[14] -q_a[15] <= altsyncram_4ed1:auto_generated.q_a[15] -q_a[16] <= altsyncram_4ed1:auto_generated.q_a[16] -q_a[17] <= altsyncram_4ed1:auto_generated.q_a[17] -q_a[18] <= altsyncram_4ed1:auto_generated.q_a[18] -q_a[19] <= altsyncram_4ed1:auto_generated.q_a[19] -q_a[20] <= altsyncram_4ed1:auto_generated.q_a[20] -q_a[21] <= altsyncram_4ed1:auto_generated.q_a[21] -q_a[22] <= altsyncram_4ed1:auto_generated.q_a[22] -q_a[23] <= altsyncram_4ed1:auto_generated.q_a[23] -q_a[24] <= altsyncram_4ed1:auto_generated.q_a[24] -q_a[25] <= altsyncram_4ed1:auto_generated.q_a[25] -q_a[26] <= altsyncram_4ed1:auto_generated.q_a[26] -q_a[27] <= altsyncram_4ed1:auto_generated.q_a[27] -q_a[28] <= altsyncram_4ed1:auto_generated.q_a[28] -q_a[29] <= altsyncram_4ed1:auto_generated.q_a[29] -q_a[30] <= altsyncram_4ed1:auto_generated.q_a[30] -q_a[31] <= altsyncram_4ed1:auto_generated.q_a[31] -q_b[0] <= -eccstatus[0] <= -eccstatus[1] <= -eccstatus[2] <= - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated -address_a[0] => ram_block1a0.PORTAADDR -address_a[0] => ram_block1a1.PORTAADDR -address_a[0] => ram_block1a2.PORTAADDR -address_a[0] => ram_block1a3.PORTAADDR -address_a[0] => ram_block1a4.PORTAADDR -address_a[0] => ram_block1a5.PORTAADDR -address_a[0] => ram_block1a6.PORTAADDR -address_a[0] => ram_block1a7.PORTAADDR -address_a[0] => ram_block1a8.PORTAADDR -address_a[0] => ram_block1a9.PORTAADDR -address_a[0] => ram_block1a10.PORTAADDR -address_a[0] => ram_block1a11.PORTAADDR -address_a[0] => ram_block1a12.PORTAADDR -address_a[0] => ram_block1a13.PORTAADDR -address_a[0] => ram_block1a14.PORTAADDR -address_a[0] => ram_block1a15.PORTAADDR -address_a[0] => ram_block1a16.PORTAADDR -address_a[0] => ram_block1a17.PORTAADDR -address_a[0] => ram_block1a18.PORTAADDR -address_a[0] => ram_block1a19.PORTAADDR -address_a[0] => ram_block1a20.PORTAADDR -address_a[0] => ram_block1a21.PORTAADDR -address_a[0] => ram_block1a22.PORTAADDR -address_a[0] => ram_block1a23.PORTAADDR -address_a[0] => ram_block1a24.PORTAADDR -address_a[0] => ram_block1a25.PORTAADDR -address_a[0] => ram_block1a26.PORTAADDR -address_a[0] => ram_block1a27.PORTAADDR -address_a[0] => ram_block1a28.PORTAADDR -address_a[0] => ram_block1a29.PORTAADDR -address_a[0] => ram_block1a30.PORTAADDR -address_a[0] => ram_block1a31.PORTAADDR -address_a[0] => ram_block1a32.PORTAADDR -address_a[0] => ram_block1a33.PORTAADDR -address_a[0] => ram_block1a34.PORTAADDR -address_a[0] => ram_block1a35.PORTAADDR -address_a[0] => ram_block1a36.PORTAADDR -address_a[0] => ram_block1a37.PORTAADDR -address_a[0] => ram_block1a38.PORTAADDR -address_a[0] => ram_block1a39.PORTAADDR -address_a[0] => ram_block1a40.PORTAADDR -address_a[0] => ram_block1a41.PORTAADDR -address_a[0] => ram_block1a42.PORTAADDR -address_a[0] => ram_block1a43.PORTAADDR -address_a[0] => ram_block1a44.PORTAADDR -address_a[0] => ram_block1a45.PORTAADDR -address_a[0] => ram_block1a46.PORTAADDR -address_a[0] => ram_block1a47.PORTAADDR -address_a[0] => ram_block1a48.PORTAADDR -address_a[0] => ram_block1a49.PORTAADDR -address_a[0] => ram_block1a50.PORTAADDR -address_a[0] => ram_block1a51.PORTAADDR -address_a[0] => ram_block1a52.PORTAADDR -address_a[0] => ram_block1a53.PORTAADDR -address_a[0] => ram_block1a54.PORTAADDR -address_a[0] => ram_block1a55.PORTAADDR -address_a[0] => ram_block1a56.PORTAADDR -address_a[0] => ram_block1a57.PORTAADDR -address_a[0] => ram_block1a58.PORTAADDR -address_a[0] => ram_block1a59.PORTAADDR -address_a[0] => ram_block1a60.PORTAADDR -address_a[0] => ram_block1a61.PORTAADDR -address_a[0] => ram_block1a62.PORTAADDR -address_a[0] => ram_block1a63.PORTAADDR -address_a[0] => ram_block1a64.PORTAADDR -address_a[0] => ram_block1a65.PORTAADDR -address_a[0] => ram_block1a66.PORTAADDR -address_a[0] => ram_block1a67.PORTAADDR -address_a[0] => ram_block1a68.PORTAADDR -address_a[0] => ram_block1a69.PORTAADDR -address_a[0] => ram_block1a70.PORTAADDR -address_a[0] => ram_block1a71.PORTAADDR -address_a[0] => ram_block1a72.PORTAADDR -address_a[0] => ram_block1a73.PORTAADDR -address_a[0] => ram_block1a74.PORTAADDR -address_a[0] => ram_block1a75.PORTAADDR -address_a[0] => ram_block1a76.PORTAADDR -address_a[0] => ram_block1a77.PORTAADDR -address_a[0] => ram_block1a78.PORTAADDR -address_a[0] => ram_block1a79.PORTAADDR -address_a[0] => ram_block1a80.PORTAADDR -address_a[0] => ram_block1a81.PORTAADDR -address_a[0] => ram_block1a82.PORTAADDR -address_a[0] => ram_block1a83.PORTAADDR -address_a[0] => ram_block1a84.PORTAADDR -address_a[0] => ram_block1a85.PORTAADDR -address_a[0] => ram_block1a86.PORTAADDR -address_a[0] => ram_block1a87.PORTAADDR -address_a[0] => ram_block1a88.PORTAADDR -address_a[0] => ram_block1a89.PORTAADDR -address_a[0] => ram_block1a90.PORTAADDR -address_a[0] => ram_block1a91.PORTAADDR -address_a[0] => ram_block1a92.PORTAADDR -address_a[0] => ram_block1a93.PORTAADDR -address_a[0] => ram_block1a94.PORTAADDR -address_a[0] => ram_block1a95.PORTAADDR -address_a[0] => ram_block1a96.PORTAADDR -address_a[0] => ram_block1a97.PORTAADDR -address_a[0] => ram_block1a98.PORTAADDR -address_a[0] => ram_block1a99.PORTAADDR -address_a[0] => ram_block1a100.PORTAADDR -address_a[0] => ram_block1a101.PORTAADDR -address_a[0] => ram_block1a102.PORTAADDR -address_a[0] => ram_block1a103.PORTAADDR -address_a[0] => ram_block1a104.PORTAADDR -address_a[0] => ram_block1a105.PORTAADDR -address_a[0] => ram_block1a106.PORTAADDR -address_a[0] => ram_block1a107.PORTAADDR -address_a[0] => ram_block1a108.PORTAADDR -address_a[0] => ram_block1a109.PORTAADDR -address_a[0] => ram_block1a110.PORTAADDR -address_a[0] => ram_block1a111.PORTAADDR -address_a[0] => ram_block1a112.PORTAADDR -address_a[0] => ram_block1a113.PORTAADDR -address_a[0] => ram_block1a114.PORTAADDR -address_a[0] => ram_block1a115.PORTAADDR -address_a[0] => ram_block1a116.PORTAADDR -address_a[0] => ram_block1a117.PORTAADDR -address_a[0] => ram_block1a118.PORTAADDR -address_a[0] => ram_block1a119.PORTAADDR -address_a[0] => ram_block1a120.PORTAADDR -address_a[0] => ram_block1a121.PORTAADDR -address_a[0] => ram_block1a122.PORTAADDR -address_a[0] => ram_block1a123.PORTAADDR -address_a[0] => ram_block1a124.PORTAADDR -address_a[0] => ram_block1a125.PORTAADDR -address_a[0] => ram_block1a126.PORTAADDR -address_a[0] => ram_block1a127.PORTAADDR -address_a[0] => ram_block1a128.PORTAADDR -address_a[0] => ram_block1a129.PORTAADDR -address_a[0] => ram_block1a130.PORTAADDR -address_a[0] => ram_block1a131.PORTAADDR -address_a[0] => ram_block1a132.PORTAADDR -address_a[0] => ram_block1a133.PORTAADDR -address_a[0] => ram_block1a134.PORTAADDR -address_a[0] => ram_block1a135.PORTAADDR -address_a[0] => ram_block1a136.PORTAADDR -address_a[0] => ram_block1a137.PORTAADDR -address_a[0] => ram_block1a138.PORTAADDR -address_a[0] => ram_block1a139.PORTAADDR -address_a[0] => ram_block1a140.PORTAADDR -address_a[0] => ram_block1a141.PORTAADDR -address_a[0] => ram_block1a142.PORTAADDR -address_a[0] => ram_block1a143.PORTAADDR -address_a[0] => ram_block1a144.PORTAADDR -address_a[0] => ram_block1a145.PORTAADDR -address_a[0] => ram_block1a146.PORTAADDR -address_a[0] => ram_block1a147.PORTAADDR -address_a[0] => ram_block1a148.PORTAADDR -address_a[0] => ram_block1a149.PORTAADDR -address_a[0] => ram_block1a150.PORTAADDR -address_a[0] => ram_block1a151.PORTAADDR -address_a[0] => ram_block1a152.PORTAADDR -address_a[0] => ram_block1a153.PORTAADDR -address_a[0] => ram_block1a154.PORTAADDR -address_a[0] => ram_block1a155.PORTAADDR -address_a[0] => ram_block1a156.PORTAADDR -address_a[0] => ram_block1a157.PORTAADDR -address_a[0] => ram_block1a158.PORTAADDR -address_a[0] => ram_block1a159.PORTAADDR -address_a[0] => ram_block1a160.PORTAADDR -address_a[0] => ram_block1a161.PORTAADDR -address_a[0] => ram_block1a162.PORTAADDR -address_a[0] => ram_block1a163.PORTAADDR -address_a[0] => ram_block1a164.PORTAADDR -address_a[0] => ram_block1a165.PORTAADDR -address_a[0] => ram_block1a166.PORTAADDR -address_a[0] => ram_block1a167.PORTAADDR -address_a[0] => ram_block1a168.PORTAADDR -address_a[0] => ram_block1a169.PORTAADDR -address_a[0] => ram_block1a170.PORTAADDR -address_a[0] => ram_block1a171.PORTAADDR -address_a[0] => ram_block1a172.PORTAADDR -address_a[0] => ram_block1a173.PORTAADDR -address_a[0] => ram_block1a174.PORTAADDR -address_a[0] => ram_block1a175.PORTAADDR -address_a[0] => ram_block1a176.PORTAADDR -address_a[0] => ram_block1a177.PORTAADDR -address_a[0] => ram_block1a178.PORTAADDR -address_a[0] => ram_block1a179.PORTAADDR -address_a[0] => ram_block1a180.PORTAADDR -address_a[0] => ram_block1a181.PORTAADDR -address_a[0] => ram_block1a182.PORTAADDR -address_a[0] => ram_block1a183.PORTAADDR -address_a[0] => ram_block1a184.PORTAADDR -address_a[0] => ram_block1a185.PORTAADDR -address_a[0] => ram_block1a186.PORTAADDR -address_a[0] => ram_block1a187.PORTAADDR -address_a[0] => ram_block1a188.PORTAADDR -address_a[0] => ram_block1a189.PORTAADDR -address_a[0] => ram_block1a190.PORTAADDR -address_a[0] => ram_block1a191.PORTAADDR -address_a[0] => ram_block1a192.PORTAADDR -address_a[0] => ram_block1a193.PORTAADDR -address_a[0] => ram_block1a194.PORTAADDR -address_a[0] => ram_block1a195.PORTAADDR -address_a[0] => ram_block1a196.PORTAADDR -address_a[0] => ram_block1a197.PORTAADDR -address_a[0] => ram_block1a198.PORTAADDR -address_a[0] => ram_block1a199.PORTAADDR -address_a[0] => ram_block1a200.PORTAADDR -address_a[0] => ram_block1a201.PORTAADDR -address_a[0] => ram_block1a202.PORTAADDR -address_a[0] => ram_block1a203.PORTAADDR -address_a[0] => ram_block1a204.PORTAADDR -address_a[0] => ram_block1a205.PORTAADDR -address_a[0] => ram_block1a206.PORTAADDR -address_a[0] => ram_block1a207.PORTAADDR -address_a[0] => ram_block1a208.PORTAADDR -address_a[0] => ram_block1a209.PORTAADDR -address_a[0] => ram_block1a210.PORTAADDR -address_a[0] => ram_block1a211.PORTAADDR -address_a[0] => ram_block1a212.PORTAADDR -address_a[0] => ram_block1a213.PORTAADDR -address_a[0] => ram_block1a214.PORTAADDR -address_a[0] => ram_block1a215.PORTAADDR -address_a[0] => ram_block1a216.PORTAADDR -address_a[0] => ram_block1a217.PORTAADDR -address_a[0] => ram_block1a218.PORTAADDR -address_a[0] => ram_block1a219.PORTAADDR -address_a[0] => ram_block1a220.PORTAADDR -address_a[0] => ram_block1a221.PORTAADDR -address_a[0] => ram_block1a222.PORTAADDR -address_a[0] => ram_block1a223.PORTAADDR -address_a[1] => ram_block1a0.PORTAADDR1 -address_a[1] => ram_block1a1.PORTAADDR1 -address_a[1] => ram_block1a2.PORTAADDR1 -address_a[1] => ram_block1a3.PORTAADDR1 -address_a[1] => ram_block1a4.PORTAADDR1 -address_a[1] => ram_block1a5.PORTAADDR1 -address_a[1] => ram_block1a6.PORTAADDR1 -address_a[1] => ram_block1a7.PORTAADDR1 -address_a[1] => ram_block1a8.PORTAADDR1 -address_a[1] => ram_block1a9.PORTAADDR1 -address_a[1] => ram_block1a10.PORTAADDR1 -address_a[1] => ram_block1a11.PORTAADDR1 -address_a[1] => ram_block1a12.PORTAADDR1 -address_a[1] => ram_block1a13.PORTAADDR1 -address_a[1] => ram_block1a14.PORTAADDR1 -address_a[1] => ram_block1a15.PORTAADDR1 -address_a[1] => ram_block1a16.PORTAADDR1 -address_a[1] => ram_block1a17.PORTAADDR1 -address_a[1] => ram_block1a18.PORTAADDR1 -address_a[1] => ram_block1a19.PORTAADDR1 -address_a[1] => ram_block1a20.PORTAADDR1 -address_a[1] => ram_block1a21.PORTAADDR1 -address_a[1] => ram_block1a22.PORTAADDR1 -address_a[1] => ram_block1a23.PORTAADDR1 -address_a[1] => ram_block1a24.PORTAADDR1 -address_a[1] => ram_block1a25.PORTAADDR1 -address_a[1] => ram_block1a26.PORTAADDR1 -address_a[1] => ram_block1a27.PORTAADDR1 -address_a[1] => ram_block1a28.PORTAADDR1 -address_a[1] => ram_block1a29.PORTAADDR1 -address_a[1] => ram_block1a30.PORTAADDR1 -address_a[1] => ram_block1a31.PORTAADDR1 -address_a[1] => ram_block1a32.PORTAADDR1 -address_a[1] => ram_block1a33.PORTAADDR1 -address_a[1] => ram_block1a34.PORTAADDR1 -address_a[1] => ram_block1a35.PORTAADDR1 -address_a[1] => ram_block1a36.PORTAADDR1 -address_a[1] => ram_block1a37.PORTAADDR1 -address_a[1] => ram_block1a38.PORTAADDR1 -address_a[1] => ram_block1a39.PORTAADDR1 -address_a[1] => ram_block1a40.PORTAADDR1 -address_a[1] => ram_block1a41.PORTAADDR1 -address_a[1] => ram_block1a42.PORTAADDR1 -address_a[1] => ram_block1a43.PORTAADDR1 -address_a[1] => ram_block1a44.PORTAADDR1 -address_a[1] => ram_block1a45.PORTAADDR1 -address_a[1] => ram_block1a46.PORTAADDR1 -address_a[1] => ram_block1a47.PORTAADDR1 -address_a[1] => ram_block1a48.PORTAADDR1 -address_a[1] => ram_block1a49.PORTAADDR1 -address_a[1] => ram_block1a50.PORTAADDR1 -address_a[1] => ram_block1a51.PORTAADDR1 -address_a[1] => ram_block1a52.PORTAADDR1 -address_a[1] => ram_block1a53.PORTAADDR1 -address_a[1] => ram_block1a54.PORTAADDR1 -address_a[1] => ram_block1a55.PORTAADDR1 -address_a[1] => ram_block1a56.PORTAADDR1 -address_a[1] => ram_block1a57.PORTAADDR1 -address_a[1] => ram_block1a58.PORTAADDR1 -address_a[1] => ram_block1a59.PORTAADDR1 -address_a[1] => ram_block1a60.PORTAADDR1 -address_a[1] => ram_block1a61.PORTAADDR1 -address_a[1] => ram_block1a62.PORTAADDR1 -address_a[1] => ram_block1a63.PORTAADDR1 -address_a[1] => ram_block1a64.PORTAADDR1 -address_a[1] => ram_block1a65.PORTAADDR1 -address_a[1] => ram_block1a66.PORTAADDR1 -address_a[1] => ram_block1a67.PORTAADDR1 -address_a[1] => ram_block1a68.PORTAADDR1 -address_a[1] => ram_block1a69.PORTAADDR1 -address_a[1] => ram_block1a70.PORTAADDR1 -address_a[1] => ram_block1a71.PORTAADDR1 -address_a[1] => ram_block1a72.PORTAADDR1 -address_a[1] => ram_block1a73.PORTAADDR1 -address_a[1] => ram_block1a74.PORTAADDR1 -address_a[1] => ram_block1a75.PORTAADDR1 -address_a[1] => ram_block1a76.PORTAADDR1 -address_a[1] => ram_block1a77.PORTAADDR1 -address_a[1] => ram_block1a78.PORTAADDR1 -address_a[1] => ram_block1a79.PORTAADDR1 -address_a[1] => ram_block1a80.PORTAADDR1 -address_a[1] => ram_block1a81.PORTAADDR1 -address_a[1] => ram_block1a82.PORTAADDR1 -address_a[1] => ram_block1a83.PORTAADDR1 -address_a[1] => ram_block1a84.PORTAADDR1 -address_a[1] => ram_block1a85.PORTAADDR1 -address_a[1] => ram_block1a86.PORTAADDR1 -address_a[1] => ram_block1a87.PORTAADDR1 -address_a[1] => ram_block1a88.PORTAADDR1 -address_a[1] => ram_block1a89.PORTAADDR1 -address_a[1] => ram_block1a90.PORTAADDR1 -address_a[1] => ram_block1a91.PORTAADDR1 -address_a[1] => ram_block1a92.PORTAADDR1 -address_a[1] => ram_block1a93.PORTAADDR1 -address_a[1] => ram_block1a94.PORTAADDR1 -address_a[1] => ram_block1a95.PORTAADDR1 -address_a[1] => ram_block1a96.PORTAADDR1 -address_a[1] => ram_block1a97.PORTAADDR1 -address_a[1] => ram_block1a98.PORTAADDR1 -address_a[1] => ram_block1a99.PORTAADDR1 -address_a[1] => ram_block1a100.PORTAADDR1 -address_a[1] => ram_block1a101.PORTAADDR1 -address_a[1] => ram_block1a102.PORTAADDR1 -address_a[1] => ram_block1a103.PORTAADDR1 -address_a[1] => ram_block1a104.PORTAADDR1 -address_a[1] => ram_block1a105.PORTAADDR1 -address_a[1] => ram_block1a106.PORTAADDR1 -address_a[1] => ram_block1a107.PORTAADDR1 -address_a[1] => ram_block1a108.PORTAADDR1 -address_a[1] => ram_block1a109.PORTAADDR1 -address_a[1] => ram_block1a110.PORTAADDR1 -address_a[1] => ram_block1a111.PORTAADDR1 -address_a[1] => ram_block1a112.PORTAADDR1 -address_a[1] => ram_block1a113.PORTAADDR1 -address_a[1] => ram_block1a114.PORTAADDR1 -address_a[1] => ram_block1a115.PORTAADDR1 -address_a[1] => ram_block1a116.PORTAADDR1 -address_a[1] => ram_block1a117.PORTAADDR1 -address_a[1] => ram_block1a118.PORTAADDR1 -address_a[1] => ram_block1a119.PORTAADDR1 -address_a[1] => ram_block1a120.PORTAADDR1 -address_a[1] => ram_block1a121.PORTAADDR1 -address_a[1] => ram_block1a122.PORTAADDR1 -address_a[1] => ram_block1a123.PORTAADDR1 -address_a[1] => ram_block1a124.PORTAADDR1 -address_a[1] => ram_block1a125.PORTAADDR1 -address_a[1] => ram_block1a126.PORTAADDR1 -address_a[1] => ram_block1a127.PORTAADDR1 -address_a[1] => ram_block1a128.PORTAADDR1 -address_a[1] => ram_block1a129.PORTAADDR1 -address_a[1] => ram_block1a130.PORTAADDR1 -address_a[1] => ram_block1a131.PORTAADDR1 -address_a[1] => ram_block1a132.PORTAADDR1 -address_a[1] => ram_block1a133.PORTAADDR1 -address_a[1] => ram_block1a134.PORTAADDR1 -address_a[1] => ram_block1a135.PORTAADDR1 -address_a[1] => ram_block1a136.PORTAADDR1 -address_a[1] => ram_block1a137.PORTAADDR1 -address_a[1] => ram_block1a138.PORTAADDR1 -address_a[1] => ram_block1a139.PORTAADDR1 -address_a[1] => ram_block1a140.PORTAADDR1 -address_a[1] => ram_block1a141.PORTAADDR1 -address_a[1] => ram_block1a142.PORTAADDR1 -address_a[1] => ram_block1a143.PORTAADDR1 -address_a[1] => ram_block1a144.PORTAADDR1 -address_a[1] => ram_block1a145.PORTAADDR1 -address_a[1] => ram_block1a146.PORTAADDR1 -address_a[1] => ram_block1a147.PORTAADDR1 -address_a[1] => ram_block1a148.PORTAADDR1 -address_a[1] => ram_block1a149.PORTAADDR1 -address_a[1] => ram_block1a150.PORTAADDR1 -address_a[1] => ram_block1a151.PORTAADDR1 -address_a[1] => ram_block1a152.PORTAADDR1 -address_a[1] => ram_block1a153.PORTAADDR1 -address_a[1] => ram_block1a154.PORTAADDR1 -address_a[1] => ram_block1a155.PORTAADDR1 -address_a[1] => ram_block1a156.PORTAADDR1 -address_a[1] => ram_block1a157.PORTAADDR1 -address_a[1] => ram_block1a158.PORTAADDR1 -address_a[1] => ram_block1a159.PORTAADDR1 -address_a[1] => ram_block1a160.PORTAADDR1 -address_a[1] => ram_block1a161.PORTAADDR1 -address_a[1] => ram_block1a162.PORTAADDR1 -address_a[1] => ram_block1a163.PORTAADDR1 -address_a[1] => ram_block1a164.PORTAADDR1 -address_a[1] => ram_block1a165.PORTAADDR1 -address_a[1] => ram_block1a166.PORTAADDR1 -address_a[1] => ram_block1a167.PORTAADDR1 -address_a[1] => ram_block1a168.PORTAADDR1 -address_a[1] => ram_block1a169.PORTAADDR1 -address_a[1] => ram_block1a170.PORTAADDR1 -address_a[1] => ram_block1a171.PORTAADDR1 -address_a[1] => ram_block1a172.PORTAADDR1 -address_a[1] => ram_block1a173.PORTAADDR1 -address_a[1] => ram_block1a174.PORTAADDR1 -address_a[1] => ram_block1a175.PORTAADDR1 -address_a[1] => ram_block1a176.PORTAADDR1 -address_a[1] => ram_block1a177.PORTAADDR1 -address_a[1] => ram_block1a178.PORTAADDR1 -address_a[1] => ram_block1a179.PORTAADDR1 -address_a[1] => ram_block1a180.PORTAADDR1 -address_a[1] => ram_block1a181.PORTAADDR1 -address_a[1] => ram_block1a182.PORTAADDR1 -address_a[1] => ram_block1a183.PORTAADDR1 -address_a[1] => ram_block1a184.PORTAADDR1 -address_a[1] => ram_block1a185.PORTAADDR1 -address_a[1] => ram_block1a186.PORTAADDR1 -address_a[1] => ram_block1a187.PORTAADDR1 -address_a[1] => ram_block1a188.PORTAADDR1 -address_a[1] => ram_block1a189.PORTAADDR1 -address_a[1] => ram_block1a190.PORTAADDR1 -address_a[1] => ram_block1a191.PORTAADDR1 -address_a[1] => ram_block1a192.PORTAADDR1 -address_a[1] => ram_block1a193.PORTAADDR1 -address_a[1] => ram_block1a194.PORTAADDR1 -address_a[1] => ram_block1a195.PORTAADDR1 -address_a[1] => ram_block1a196.PORTAADDR1 -address_a[1] => ram_block1a197.PORTAADDR1 -address_a[1] => ram_block1a198.PORTAADDR1 -address_a[1] => ram_block1a199.PORTAADDR1 -address_a[1] => ram_block1a200.PORTAADDR1 -address_a[1] => ram_block1a201.PORTAADDR1 -address_a[1] => ram_block1a202.PORTAADDR1 -address_a[1] => ram_block1a203.PORTAADDR1 -address_a[1] => ram_block1a204.PORTAADDR1 -address_a[1] => ram_block1a205.PORTAADDR1 -address_a[1] => ram_block1a206.PORTAADDR1 -address_a[1] => ram_block1a207.PORTAADDR1 -address_a[1] => ram_block1a208.PORTAADDR1 -address_a[1] => ram_block1a209.PORTAADDR1 -address_a[1] => ram_block1a210.PORTAADDR1 -address_a[1] => ram_block1a211.PORTAADDR1 -address_a[1] => ram_block1a212.PORTAADDR1 -address_a[1] => ram_block1a213.PORTAADDR1 -address_a[1] => ram_block1a214.PORTAADDR1 -address_a[1] => ram_block1a215.PORTAADDR1 -address_a[1] => ram_block1a216.PORTAADDR1 -address_a[1] => ram_block1a217.PORTAADDR1 -address_a[1] => ram_block1a218.PORTAADDR1 -address_a[1] => ram_block1a219.PORTAADDR1 -address_a[1] => ram_block1a220.PORTAADDR1 -address_a[1] => ram_block1a221.PORTAADDR1 -address_a[1] => ram_block1a222.PORTAADDR1 -address_a[1] => ram_block1a223.PORTAADDR1 -address_a[2] => ram_block1a0.PORTAADDR2 -address_a[2] => ram_block1a1.PORTAADDR2 -address_a[2] => ram_block1a2.PORTAADDR2 -address_a[2] => ram_block1a3.PORTAADDR2 -address_a[2] => ram_block1a4.PORTAADDR2 -address_a[2] => ram_block1a5.PORTAADDR2 -address_a[2] => ram_block1a6.PORTAADDR2 -address_a[2] => ram_block1a7.PORTAADDR2 -address_a[2] => ram_block1a8.PORTAADDR2 -address_a[2] => ram_block1a9.PORTAADDR2 -address_a[2] => ram_block1a10.PORTAADDR2 -address_a[2] => ram_block1a11.PORTAADDR2 -address_a[2] => ram_block1a12.PORTAADDR2 -address_a[2] => ram_block1a13.PORTAADDR2 -address_a[2] => ram_block1a14.PORTAADDR2 -address_a[2] => ram_block1a15.PORTAADDR2 -address_a[2] => ram_block1a16.PORTAADDR2 -address_a[2] => ram_block1a17.PORTAADDR2 -address_a[2] => ram_block1a18.PORTAADDR2 -address_a[2] => ram_block1a19.PORTAADDR2 -address_a[2] => ram_block1a20.PORTAADDR2 -address_a[2] => ram_block1a21.PORTAADDR2 -address_a[2] => ram_block1a22.PORTAADDR2 -address_a[2] => ram_block1a23.PORTAADDR2 -address_a[2] => ram_block1a24.PORTAADDR2 -address_a[2] => ram_block1a25.PORTAADDR2 -address_a[2] => ram_block1a26.PORTAADDR2 -address_a[2] => ram_block1a27.PORTAADDR2 -address_a[2] => ram_block1a28.PORTAADDR2 -address_a[2] => ram_block1a29.PORTAADDR2 -address_a[2] => ram_block1a30.PORTAADDR2 -address_a[2] => ram_block1a31.PORTAADDR2 -address_a[2] => ram_block1a32.PORTAADDR2 -address_a[2] => ram_block1a33.PORTAADDR2 -address_a[2] => ram_block1a34.PORTAADDR2 -address_a[2] => ram_block1a35.PORTAADDR2 -address_a[2] => ram_block1a36.PORTAADDR2 -address_a[2] => ram_block1a37.PORTAADDR2 -address_a[2] => ram_block1a38.PORTAADDR2 -address_a[2] => ram_block1a39.PORTAADDR2 -address_a[2] => ram_block1a40.PORTAADDR2 -address_a[2] => ram_block1a41.PORTAADDR2 -address_a[2] => ram_block1a42.PORTAADDR2 -address_a[2] => ram_block1a43.PORTAADDR2 -address_a[2] => ram_block1a44.PORTAADDR2 -address_a[2] => ram_block1a45.PORTAADDR2 -address_a[2] => ram_block1a46.PORTAADDR2 -address_a[2] => ram_block1a47.PORTAADDR2 -address_a[2] => ram_block1a48.PORTAADDR2 -address_a[2] => ram_block1a49.PORTAADDR2 -address_a[2] => ram_block1a50.PORTAADDR2 -address_a[2] => ram_block1a51.PORTAADDR2 -address_a[2] => ram_block1a52.PORTAADDR2 -address_a[2] => ram_block1a53.PORTAADDR2 -address_a[2] => ram_block1a54.PORTAADDR2 -address_a[2] => ram_block1a55.PORTAADDR2 -address_a[2] => ram_block1a56.PORTAADDR2 -address_a[2] => ram_block1a57.PORTAADDR2 -address_a[2] => ram_block1a58.PORTAADDR2 -address_a[2] => ram_block1a59.PORTAADDR2 -address_a[2] => ram_block1a60.PORTAADDR2 -address_a[2] => ram_block1a61.PORTAADDR2 -address_a[2] => ram_block1a62.PORTAADDR2 -address_a[2] => ram_block1a63.PORTAADDR2 -address_a[2] => ram_block1a64.PORTAADDR2 -address_a[2] => ram_block1a65.PORTAADDR2 -address_a[2] => ram_block1a66.PORTAADDR2 -address_a[2] => ram_block1a67.PORTAADDR2 -address_a[2] => ram_block1a68.PORTAADDR2 -address_a[2] => ram_block1a69.PORTAADDR2 -address_a[2] => ram_block1a70.PORTAADDR2 -address_a[2] => ram_block1a71.PORTAADDR2 -address_a[2] => ram_block1a72.PORTAADDR2 -address_a[2] => ram_block1a73.PORTAADDR2 -address_a[2] => ram_block1a74.PORTAADDR2 -address_a[2] => ram_block1a75.PORTAADDR2 -address_a[2] => ram_block1a76.PORTAADDR2 -address_a[2] => ram_block1a77.PORTAADDR2 -address_a[2] => ram_block1a78.PORTAADDR2 -address_a[2] => ram_block1a79.PORTAADDR2 -address_a[2] => ram_block1a80.PORTAADDR2 -address_a[2] => ram_block1a81.PORTAADDR2 -address_a[2] => ram_block1a82.PORTAADDR2 -address_a[2] => ram_block1a83.PORTAADDR2 -address_a[2] => ram_block1a84.PORTAADDR2 -address_a[2] => ram_block1a85.PORTAADDR2 -address_a[2] => ram_block1a86.PORTAADDR2 -address_a[2] => ram_block1a87.PORTAADDR2 -address_a[2] => ram_block1a88.PORTAADDR2 -address_a[2] => ram_block1a89.PORTAADDR2 -address_a[2] => ram_block1a90.PORTAADDR2 -address_a[2] => ram_block1a91.PORTAADDR2 -address_a[2] => ram_block1a92.PORTAADDR2 -address_a[2] => ram_block1a93.PORTAADDR2 -address_a[2] => ram_block1a94.PORTAADDR2 -address_a[2] => ram_block1a95.PORTAADDR2 -address_a[2] => ram_block1a96.PORTAADDR2 -address_a[2] => ram_block1a97.PORTAADDR2 -address_a[2] => ram_block1a98.PORTAADDR2 -address_a[2] => ram_block1a99.PORTAADDR2 -address_a[2] => ram_block1a100.PORTAADDR2 -address_a[2] => ram_block1a101.PORTAADDR2 -address_a[2] => ram_block1a102.PORTAADDR2 -address_a[2] => ram_block1a103.PORTAADDR2 -address_a[2] => ram_block1a104.PORTAADDR2 -address_a[2] => ram_block1a105.PORTAADDR2 -address_a[2] => ram_block1a106.PORTAADDR2 -address_a[2] => ram_block1a107.PORTAADDR2 -address_a[2] => ram_block1a108.PORTAADDR2 -address_a[2] => ram_block1a109.PORTAADDR2 -address_a[2] => ram_block1a110.PORTAADDR2 -address_a[2] => ram_block1a111.PORTAADDR2 -address_a[2] => ram_block1a112.PORTAADDR2 -address_a[2] => ram_block1a113.PORTAADDR2 -address_a[2] => ram_block1a114.PORTAADDR2 -address_a[2] => ram_block1a115.PORTAADDR2 -address_a[2] => ram_block1a116.PORTAADDR2 -address_a[2] => ram_block1a117.PORTAADDR2 -address_a[2] => ram_block1a118.PORTAADDR2 -address_a[2] => ram_block1a119.PORTAADDR2 -address_a[2] => ram_block1a120.PORTAADDR2 -address_a[2] => ram_block1a121.PORTAADDR2 -address_a[2] => ram_block1a122.PORTAADDR2 -address_a[2] => ram_block1a123.PORTAADDR2 -address_a[2] => ram_block1a124.PORTAADDR2 -address_a[2] => ram_block1a125.PORTAADDR2 -address_a[2] => ram_block1a126.PORTAADDR2 -address_a[2] => ram_block1a127.PORTAADDR2 -address_a[2] => ram_block1a128.PORTAADDR2 -address_a[2] => ram_block1a129.PORTAADDR2 -address_a[2] => ram_block1a130.PORTAADDR2 -address_a[2] => ram_block1a131.PORTAADDR2 -address_a[2] => ram_block1a132.PORTAADDR2 -address_a[2] => ram_block1a133.PORTAADDR2 -address_a[2] => ram_block1a134.PORTAADDR2 -address_a[2] => ram_block1a135.PORTAADDR2 -address_a[2] => ram_block1a136.PORTAADDR2 -address_a[2] => ram_block1a137.PORTAADDR2 -address_a[2] => ram_block1a138.PORTAADDR2 -address_a[2] => ram_block1a139.PORTAADDR2 -address_a[2] => ram_block1a140.PORTAADDR2 -address_a[2] => ram_block1a141.PORTAADDR2 -address_a[2] => ram_block1a142.PORTAADDR2 -address_a[2] => ram_block1a143.PORTAADDR2 -address_a[2] => ram_block1a144.PORTAADDR2 -address_a[2] => ram_block1a145.PORTAADDR2 -address_a[2] => ram_block1a146.PORTAADDR2 -address_a[2] => ram_block1a147.PORTAADDR2 -address_a[2] => ram_block1a148.PORTAADDR2 -address_a[2] => ram_block1a149.PORTAADDR2 -address_a[2] => ram_block1a150.PORTAADDR2 -address_a[2] => ram_block1a151.PORTAADDR2 -address_a[2] => ram_block1a152.PORTAADDR2 -address_a[2] => ram_block1a153.PORTAADDR2 -address_a[2] => ram_block1a154.PORTAADDR2 -address_a[2] => ram_block1a155.PORTAADDR2 -address_a[2] => ram_block1a156.PORTAADDR2 -address_a[2] => ram_block1a157.PORTAADDR2 -address_a[2] => ram_block1a158.PORTAADDR2 -address_a[2] => ram_block1a159.PORTAADDR2 -address_a[2] => ram_block1a160.PORTAADDR2 -address_a[2] => ram_block1a161.PORTAADDR2 -address_a[2] => ram_block1a162.PORTAADDR2 -address_a[2] => ram_block1a163.PORTAADDR2 -address_a[2] => ram_block1a164.PORTAADDR2 -address_a[2] => ram_block1a165.PORTAADDR2 -address_a[2] => ram_block1a166.PORTAADDR2 -address_a[2] => ram_block1a167.PORTAADDR2 -address_a[2] => ram_block1a168.PORTAADDR2 -address_a[2] => ram_block1a169.PORTAADDR2 -address_a[2] => ram_block1a170.PORTAADDR2 -address_a[2] => ram_block1a171.PORTAADDR2 -address_a[2] => ram_block1a172.PORTAADDR2 -address_a[2] => ram_block1a173.PORTAADDR2 -address_a[2] => ram_block1a174.PORTAADDR2 -address_a[2] => ram_block1a175.PORTAADDR2 -address_a[2] => ram_block1a176.PORTAADDR2 -address_a[2] => ram_block1a177.PORTAADDR2 -address_a[2] => ram_block1a178.PORTAADDR2 -address_a[2] => ram_block1a179.PORTAADDR2 -address_a[2] => ram_block1a180.PORTAADDR2 -address_a[2] => ram_block1a181.PORTAADDR2 -address_a[2] => ram_block1a182.PORTAADDR2 -address_a[2] => ram_block1a183.PORTAADDR2 -address_a[2] => ram_block1a184.PORTAADDR2 -address_a[2] => ram_block1a185.PORTAADDR2 -address_a[2] => ram_block1a186.PORTAADDR2 -address_a[2] => ram_block1a187.PORTAADDR2 -address_a[2] => ram_block1a188.PORTAADDR2 -address_a[2] => ram_block1a189.PORTAADDR2 -address_a[2] => ram_block1a190.PORTAADDR2 -address_a[2] => ram_block1a191.PORTAADDR2 -address_a[2] => ram_block1a192.PORTAADDR2 -address_a[2] => ram_block1a193.PORTAADDR2 -address_a[2] => ram_block1a194.PORTAADDR2 -address_a[2] => ram_block1a195.PORTAADDR2 -address_a[2] => ram_block1a196.PORTAADDR2 -address_a[2] => ram_block1a197.PORTAADDR2 -address_a[2] => ram_block1a198.PORTAADDR2 -address_a[2] => ram_block1a199.PORTAADDR2 -address_a[2] => ram_block1a200.PORTAADDR2 -address_a[2] => ram_block1a201.PORTAADDR2 -address_a[2] => ram_block1a202.PORTAADDR2 -address_a[2] => ram_block1a203.PORTAADDR2 -address_a[2] => ram_block1a204.PORTAADDR2 -address_a[2] => ram_block1a205.PORTAADDR2 -address_a[2] => ram_block1a206.PORTAADDR2 -address_a[2] => ram_block1a207.PORTAADDR2 -address_a[2] => ram_block1a208.PORTAADDR2 -address_a[2] => ram_block1a209.PORTAADDR2 -address_a[2] => ram_block1a210.PORTAADDR2 -address_a[2] => ram_block1a211.PORTAADDR2 -address_a[2] => ram_block1a212.PORTAADDR2 -address_a[2] => ram_block1a213.PORTAADDR2 -address_a[2] => ram_block1a214.PORTAADDR2 -address_a[2] => ram_block1a215.PORTAADDR2 -address_a[2] => ram_block1a216.PORTAADDR2 -address_a[2] => ram_block1a217.PORTAADDR2 -address_a[2] => ram_block1a218.PORTAADDR2 -address_a[2] => ram_block1a219.PORTAADDR2 -address_a[2] => ram_block1a220.PORTAADDR2 -address_a[2] => ram_block1a221.PORTAADDR2 -address_a[2] => ram_block1a222.PORTAADDR2 -address_a[2] => ram_block1a223.PORTAADDR2 -address_a[3] => ram_block1a0.PORTAADDR3 -address_a[3] => ram_block1a1.PORTAADDR3 -address_a[3] => ram_block1a2.PORTAADDR3 -address_a[3] => ram_block1a3.PORTAADDR3 -address_a[3] => ram_block1a4.PORTAADDR3 -address_a[3] => ram_block1a5.PORTAADDR3 -address_a[3] => ram_block1a6.PORTAADDR3 -address_a[3] => ram_block1a7.PORTAADDR3 -address_a[3] => ram_block1a8.PORTAADDR3 -address_a[3] => ram_block1a9.PORTAADDR3 -address_a[3] => ram_block1a10.PORTAADDR3 -address_a[3] => ram_block1a11.PORTAADDR3 -address_a[3] => ram_block1a12.PORTAADDR3 -address_a[3] => ram_block1a13.PORTAADDR3 -address_a[3] => ram_block1a14.PORTAADDR3 -address_a[3] => ram_block1a15.PORTAADDR3 -address_a[3] => ram_block1a16.PORTAADDR3 -address_a[3] => ram_block1a17.PORTAADDR3 -address_a[3] => ram_block1a18.PORTAADDR3 -address_a[3] => ram_block1a19.PORTAADDR3 -address_a[3] => ram_block1a20.PORTAADDR3 -address_a[3] => ram_block1a21.PORTAADDR3 -address_a[3] => ram_block1a22.PORTAADDR3 -address_a[3] => ram_block1a23.PORTAADDR3 -address_a[3] => ram_block1a24.PORTAADDR3 -address_a[3] => ram_block1a25.PORTAADDR3 -address_a[3] => ram_block1a26.PORTAADDR3 -address_a[3] => ram_block1a27.PORTAADDR3 -address_a[3] => ram_block1a28.PORTAADDR3 -address_a[3] => ram_block1a29.PORTAADDR3 -address_a[3] => ram_block1a30.PORTAADDR3 -address_a[3] => ram_block1a31.PORTAADDR3 -address_a[3] => ram_block1a32.PORTAADDR3 -address_a[3] => ram_block1a33.PORTAADDR3 -address_a[3] => ram_block1a34.PORTAADDR3 -address_a[3] => ram_block1a35.PORTAADDR3 -address_a[3] => ram_block1a36.PORTAADDR3 -address_a[3] => ram_block1a37.PORTAADDR3 -address_a[3] => ram_block1a38.PORTAADDR3 -address_a[3] => ram_block1a39.PORTAADDR3 -address_a[3] => ram_block1a40.PORTAADDR3 -address_a[3] => ram_block1a41.PORTAADDR3 -address_a[3] => ram_block1a42.PORTAADDR3 -address_a[3] => ram_block1a43.PORTAADDR3 -address_a[3] => ram_block1a44.PORTAADDR3 -address_a[3] => ram_block1a45.PORTAADDR3 -address_a[3] => ram_block1a46.PORTAADDR3 -address_a[3] => ram_block1a47.PORTAADDR3 -address_a[3] => ram_block1a48.PORTAADDR3 -address_a[3] => ram_block1a49.PORTAADDR3 -address_a[3] => ram_block1a50.PORTAADDR3 -address_a[3] => ram_block1a51.PORTAADDR3 -address_a[3] => ram_block1a52.PORTAADDR3 -address_a[3] => ram_block1a53.PORTAADDR3 -address_a[3] => ram_block1a54.PORTAADDR3 -address_a[3] => ram_block1a55.PORTAADDR3 -address_a[3] => ram_block1a56.PORTAADDR3 -address_a[3] => ram_block1a57.PORTAADDR3 -address_a[3] => ram_block1a58.PORTAADDR3 -address_a[3] => ram_block1a59.PORTAADDR3 -address_a[3] => ram_block1a60.PORTAADDR3 -address_a[3] => ram_block1a61.PORTAADDR3 -address_a[3] => ram_block1a62.PORTAADDR3 -address_a[3] => ram_block1a63.PORTAADDR3 -address_a[3] => ram_block1a64.PORTAADDR3 -address_a[3] => ram_block1a65.PORTAADDR3 -address_a[3] => ram_block1a66.PORTAADDR3 -address_a[3] => ram_block1a67.PORTAADDR3 -address_a[3] => ram_block1a68.PORTAADDR3 -address_a[3] => ram_block1a69.PORTAADDR3 -address_a[3] => ram_block1a70.PORTAADDR3 -address_a[3] => ram_block1a71.PORTAADDR3 -address_a[3] => ram_block1a72.PORTAADDR3 -address_a[3] => ram_block1a73.PORTAADDR3 -address_a[3] => ram_block1a74.PORTAADDR3 -address_a[3] => ram_block1a75.PORTAADDR3 -address_a[3] => ram_block1a76.PORTAADDR3 -address_a[3] => ram_block1a77.PORTAADDR3 -address_a[3] => ram_block1a78.PORTAADDR3 -address_a[3] => ram_block1a79.PORTAADDR3 -address_a[3] => ram_block1a80.PORTAADDR3 -address_a[3] => ram_block1a81.PORTAADDR3 -address_a[3] => ram_block1a82.PORTAADDR3 -address_a[3] => ram_block1a83.PORTAADDR3 -address_a[3] => ram_block1a84.PORTAADDR3 -address_a[3] => ram_block1a85.PORTAADDR3 -address_a[3] => ram_block1a86.PORTAADDR3 -address_a[3] => ram_block1a87.PORTAADDR3 -address_a[3] => ram_block1a88.PORTAADDR3 -address_a[3] => ram_block1a89.PORTAADDR3 -address_a[3] => ram_block1a90.PORTAADDR3 -address_a[3] => ram_block1a91.PORTAADDR3 -address_a[3] => ram_block1a92.PORTAADDR3 -address_a[3] => ram_block1a93.PORTAADDR3 -address_a[3] => ram_block1a94.PORTAADDR3 -address_a[3] => ram_block1a95.PORTAADDR3 -address_a[3] => ram_block1a96.PORTAADDR3 -address_a[3] => ram_block1a97.PORTAADDR3 -address_a[3] => ram_block1a98.PORTAADDR3 -address_a[3] => ram_block1a99.PORTAADDR3 -address_a[3] => ram_block1a100.PORTAADDR3 -address_a[3] => ram_block1a101.PORTAADDR3 -address_a[3] => ram_block1a102.PORTAADDR3 -address_a[3] => ram_block1a103.PORTAADDR3 -address_a[3] => ram_block1a104.PORTAADDR3 -address_a[3] => ram_block1a105.PORTAADDR3 -address_a[3] => ram_block1a106.PORTAADDR3 -address_a[3] => ram_block1a107.PORTAADDR3 -address_a[3] => ram_block1a108.PORTAADDR3 -address_a[3] => ram_block1a109.PORTAADDR3 -address_a[3] => ram_block1a110.PORTAADDR3 -address_a[3] => ram_block1a111.PORTAADDR3 -address_a[3] => ram_block1a112.PORTAADDR3 -address_a[3] => ram_block1a113.PORTAADDR3 -address_a[3] => ram_block1a114.PORTAADDR3 -address_a[3] => ram_block1a115.PORTAADDR3 -address_a[3] => ram_block1a116.PORTAADDR3 -address_a[3] => ram_block1a117.PORTAADDR3 -address_a[3] => ram_block1a118.PORTAADDR3 -address_a[3] => ram_block1a119.PORTAADDR3 -address_a[3] => ram_block1a120.PORTAADDR3 -address_a[3] => ram_block1a121.PORTAADDR3 -address_a[3] => ram_block1a122.PORTAADDR3 -address_a[3] => ram_block1a123.PORTAADDR3 -address_a[3] => ram_block1a124.PORTAADDR3 -address_a[3] => ram_block1a125.PORTAADDR3 -address_a[3] => ram_block1a126.PORTAADDR3 -address_a[3] => ram_block1a127.PORTAADDR3 -address_a[3] => ram_block1a128.PORTAADDR3 -address_a[3] => ram_block1a129.PORTAADDR3 -address_a[3] => ram_block1a130.PORTAADDR3 -address_a[3] => ram_block1a131.PORTAADDR3 -address_a[3] => ram_block1a132.PORTAADDR3 -address_a[3] => ram_block1a133.PORTAADDR3 -address_a[3] => ram_block1a134.PORTAADDR3 -address_a[3] => ram_block1a135.PORTAADDR3 -address_a[3] => ram_block1a136.PORTAADDR3 -address_a[3] => ram_block1a137.PORTAADDR3 -address_a[3] => ram_block1a138.PORTAADDR3 -address_a[3] => ram_block1a139.PORTAADDR3 -address_a[3] => ram_block1a140.PORTAADDR3 -address_a[3] => ram_block1a141.PORTAADDR3 -address_a[3] => ram_block1a142.PORTAADDR3 -address_a[3] => ram_block1a143.PORTAADDR3 -address_a[3] => ram_block1a144.PORTAADDR3 -address_a[3] => ram_block1a145.PORTAADDR3 -address_a[3] => ram_block1a146.PORTAADDR3 -address_a[3] => ram_block1a147.PORTAADDR3 -address_a[3] => ram_block1a148.PORTAADDR3 -address_a[3] => ram_block1a149.PORTAADDR3 -address_a[3] => ram_block1a150.PORTAADDR3 -address_a[3] => ram_block1a151.PORTAADDR3 -address_a[3] => ram_block1a152.PORTAADDR3 -address_a[3] => ram_block1a153.PORTAADDR3 -address_a[3] => ram_block1a154.PORTAADDR3 -address_a[3] => ram_block1a155.PORTAADDR3 -address_a[3] => ram_block1a156.PORTAADDR3 -address_a[3] => ram_block1a157.PORTAADDR3 -address_a[3] => ram_block1a158.PORTAADDR3 -address_a[3] => ram_block1a159.PORTAADDR3 -address_a[3] => ram_block1a160.PORTAADDR3 -address_a[3] => ram_block1a161.PORTAADDR3 -address_a[3] => ram_block1a162.PORTAADDR3 -address_a[3] => ram_block1a163.PORTAADDR3 -address_a[3] => ram_block1a164.PORTAADDR3 -address_a[3] => ram_block1a165.PORTAADDR3 -address_a[3] => ram_block1a166.PORTAADDR3 -address_a[3] => ram_block1a167.PORTAADDR3 -address_a[3] => ram_block1a168.PORTAADDR3 -address_a[3] => ram_block1a169.PORTAADDR3 -address_a[3] => ram_block1a170.PORTAADDR3 -address_a[3] => ram_block1a171.PORTAADDR3 -address_a[3] => ram_block1a172.PORTAADDR3 -address_a[3] => ram_block1a173.PORTAADDR3 -address_a[3] => ram_block1a174.PORTAADDR3 -address_a[3] => ram_block1a175.PORTAADDR3 -address_a[3] => ram_block1a176.PORTAADDR3 -address_a[3] => ram_block1a177.PORTAADDR3 -address_a[3] => ram_block1a178.PORTAADDR3 -address_a[3] => ram_block1a179.PORTAADDR3 -address_a[3] => ram_block1a180.PORTAADDR3 -address_a[3] => ram_block1a181.PORTAADDR3 -address_a[3] => ram_block1a182.PORTAADDR3 -address_a[3] => ram_block1a183.PORTAADDR3 -address_a[3] => ram_block1a184.PORTAADDR3 -address_a[3] => ram_block1a185.PORTAADDR3 -address_a[3] => ram_block1a186.PORTAADDR3 -address_a[3] => ram_block1a187.PORTAADDR3 -address_a[3] => ram_block1a188.PORTAADDR3 -address_a[3] => ram_block1a189.PORTAADDR3 -address_a[3] => ram_block1a190.PORTAADDR3 -address_a[3] => ram_block1a191.PORTAADDR3 -address_a[3] => ram_block1a192.PORTAADDR3 -address_a[3] => ram_block1a193.PORTAADDR3 -address_a[3] => ram_block1a194.PORTAADDR3 -address_a[3] => ram_block1a195.PORTAADDR3 -address_a[3] => ram_block1a196.PORTAADDR3 -address_a[3] => ram_block1a197.PORTAADDR3 -address_a[3] => ram_block1a198.PORTAADDR3 -address_a[3] => ram_block1a199.PORTAADDR3 -address_a[3] => ram_block1a200.PORTAADDR3 -address_a[3] => ram_block1a201.PORTAADDR3 -address_a[3] => ram_block1a202.PORTAADDR3 -address_a[3] => ram_block1a203.PORTAADDR3 -address_a[3] => ram_block1a204.PORTAADDR3 -address_a[3] => ram_block1a205.PORTAADDR3 -address_a[3] => ram_block1a206.PORTAADDR3 -address_a[3] => ram_block1a207.PORTAADDR3 -address_a[3] => ram_block1a208.PORTAADDR3 -address_a[3] => ram_block1a209.PORTAADDR3 -address_a[3] => ram_block1a210.PORTAADDR3 -address_a[3] => ram_block1a211.PORTAADDR3 -address_a[3] => ram_block1a212.PORTAADDR3 -address_a[3] => ram_block1a213.PORTAADDR3 -address_a[3] => ram_block1a214.PORTAADDR3 -address_a[3] => ram_block1a215.PORTAADDR3 -address_a[3] => ram_block1a216.PORTAADDR3 -address_a[3] => ram_block1a217.PORTAADDR3 -address_a[3] => ram_block1a218.PORTAADDR3 -address_a[3] => ram_block1a219.PORTAADDR3 -address_a[3] => ram_block1a220.PORTAADDR3 -address_a[3] => ram_block1a221.PORTAADDR3 -address_a[3] => ram_block1a222.PORTAADDR3 -address_a[3] => ram_block1a223.PORTAADDR3 -address_a[4] => ram_block1a0.PORTAADDR4 -address_a[4] => ram_block1a1.PORTAADDR4 -address_a[4] => ram_block1a2.PORTAADDR4 -address_a[4] => ram_block1a3.PORTAADDR4 -address_a[4] => ram_block1a4.PORTAADDR4 -address_a[4] => ram_block1a5.PORTAADDR4 -address_a[4] => ram_block1a6.PORTAADDR4 -address_a[4] => ram_block1a7.PORTAADDR4 -address_a[4] => ram_block1a8.PORTAADDR4 -address_a[4] => ram_block1a9.PORTAADDR4 -address_a[4] => ram_block1a10.PORTAADDR4 -address_a[4] => ram_block1a11.PORTAADDR4 -address_a[4] => ram_block1a12.PORTAADDR4 -address_a[4] => ram_block1a13.PORTAADDR4 -address_a[4] => ram_block1a14.PORTAADDR4 -address_a[4] => ram_block1a15.PORTAADDR4 -address_a[4] => ram_block1a16.PORTAADDR4 -address_a[4] => ram_block1a17.PORTAADDR4 -address_a[4] => ram_block1a18.PORTAADDR4 -address_a[4] => ram_block1a19.PORTAADDR4 -address_a[4] => ram_block1a20.PORTAADDR4 -address_a[4] => ram_block1a21.PORTAADDR4 -address_a[4] => ram_block1a22.PORTAADDR4 -address_a[4] => ram_block1a23.PORTAADDR4 -address_a[4] => ram_block1a24.PORTAADDR4 -address_a[4] => ram_block1a25.PORTAADDR4 -address_a[4] => ram_block1a26.PORTAADDR4 -address_a[4] => ram_block1a27.PORTAADDR4 -address_a[4] => ram_block1a28.PORTAADDR4 -address_a[4] => ram_block1a29.PORTAADDR4 -address_a[4] => ram_block1a30.PORTAADDR4 -address_a[4] => ram_block1a31.PORTAADDR4 -address_a[4] => ram_block1a32.PORTAADDR4 -address_a[4] => ram_block1a33.PORTAADDR4 -address_a[4] => ram_block1a34.PORTAADDR4 -address_a[4] => ram_block1a35.PORTAADDR4 -address_a[4] => ram_block1a36.PORTAADDR4 -address_a[4] => ram_block1a37.PORTAADDR4 -address_a[4] => ram_block1a38.PORTAADDR4 -address_a[4] => ram_block1a39.PORTAADDR4 -address_a[4] => ram_block1a40.PORTAADDR4 -address_a[4] => ram_block1a41.PORTAADDR4 -address_a[4] => ram_block1a42.PORTAADDR4 -address_a[4] => ram_block1a43.PORTAADDR4 -address_a[4] => ram_block1a44.PORTAADDR4 -address_a[4] => ram_block1a45.PORTAADDR4 -address_a[4] => ram_block1a46.PORTAADDR4 -address_a[4] => ram_block1a47.PORTAADDR4 -address_a[4] => ram_block1a48.PORTAADDR4 -address_a[4] => ram_block1a49.PORTAADDR4 -address_a[4] => ram_block1a50.PORTAADDR4 -address_a[4] => ram_block1a51.PORTAADDR4 -address_a[4] => ram_block1a52.PORTAADDR4 -address_a[4] => ram_block1a53.PORTAADDR4 -address_a[4] => ram_block1a54.PORTAADDR4 -address_a[4] => ram_block1a55.PORTAADDR4 -address_a[4] => ram_block1a56.PORTAADDR4 -address_a[4] => ram_block1a57.PORTAADDR4 -address_a[4] => ram_block1a58.PORTAADDR4 -address_a[4] => ram_block1a59.PORTAADDR4 -address_a[4] => ram_block1a60.PORTAADDR4 -address_a[4] => ram_block1a61.PORTAADDR4 -address_a[4] => ram_block1a62.PORTAADDR4 -address_a[4] => ram_block1a63.PORTAADDR4 -address_a[4] => ram_block1a64.PORTAADDR4 -address_a[4] => ram_block1a65.PORTAADDR4 -address_a[4] => ram_block1a66.PORTAADDR4 -address_a[4] => ram_block1a67.PORTAADDR4 -address_a[4] => ram_block1a68.PORTAADDR4 -address_a[4] => ram_block1a69.PORTAADDR4 -address_a[4] => ram_block1a70.PORTAADDR4 -address_a[4] => ram_block1a71.PORTAADDR4 -address_a[4] => ram_block1a72.PORTAADDR4 -address_a[4] => ram_block1a73.PORTAADDR4 -address_a[4] => ram_block1a74.PORTAADDR4 -address_a[4] => ram_block1a75.PORTAADDR4 -address_a[4] => ram_block1a76.PORTAADDR4 -address_a[4] => ram_block1a77.PORTAADDR4 -address_a[4] => ram_block1a78.PORTAADDR4 -address_a[4] => ram_block1a79.PORTAADDR4 -address_a[4] => ram_block1a80.PORTAADDR4 -address_a[4] => ram_block1a81.PORTAADDR4 -address_a[4] => ram_block1a82.PORTAADDR4 -address_a[4] => ram_block1a83.PORTAADDR4 -address_a[4] => ram_block1a84.PORTAADDR4 -address_a[4] => ram_block1a85.PORTAADDR4 -address_a[4] => ram_block1a86.PORTAADDR4 -address_a[4] => ram_block1a87.PORTAADDR4 -address_a[4] => ram_block1a88.PORTAADDR4 -address_a[4] => ram_block1a89.PORTAADDR4 -address_a[4] => ram_block1a90.PORTAADDR4 -address_a[4] => ram_block1a91.PORTAADDR4 -address_a[4] => ram_block1a92.PORTAADDR4 -address_a[4] => ram_block1a93.PORTAADDR4 -address_a[4] => ram_block1a94.PORTAADDR4 -address_a[4] => ram_block1a95.PORTAADDR4 -address_a[4] => ram_block1a96.PORTAADDR4 -address_a[4] => ram_block1a97.PORTAADDR4 -address_a[4] => ram_block1a98.PORTAADDR4 -address_a[4] => ram_block1a99.PORTAADDR4 -address_a[4] => ram_block1a100.PORTAADDR4 -address_a[4] => ram_block1a101.PORTAADDR4 -address_a[4] => ram_block1a102.PORTAADDR4 -address_a[4] => ram_block1a103.PORTAADDR4 -address_a[4] => ram_block1a104.PORTAADDR4 -address_a[4] => ram_block1a105.PORTAADDR4 -address_a[4] => ram_block1a106.PORTAADDR4 -address_a[4] => ram_block1a107.PORTAADDR4 -address_a[4] => ram_block1a108.PORTAADDR4 -address_a[4] => ram_block1a109.PORTAADDR4 -address_a[4] => ram_block1a110.PORTAADDR4 -address_a[4] => ram_block1a111.PORTAADDR4 -address_a[4] => ram_block1a112.PORTAADDR4 -address_a[4] => ram_block1a113.PORTAADDR4 -address_a[4] => ram_block1a114.PORTAADDR4 -address_a[4] => ram_block1a115.PORTAADDR4 -address_a[4] => ram_block1a116.PORTAADDR4 -address_a[4] => ram_block1a117.PORTAADDR4 -address_a[4] => ram_block1a118.PORTAADDR4 -address_a[4] => ram_block1a119.PORTAADDR4 -address_a[4] => ram_block1a120.PORTAADDR4 -address_a[4] => ram_block1a121.PORTAADDR4 -address_a[4] => ram_block1a122.PORTAADDR4 -address_a[4] => ram_block1a123.PORTAADDR4 -address_a[4] => ram_block1a124.PORTAADDR4 -address_a[4] => ram_block1a125.PORTAADDR4 -address_a[4] => ram_block1a126.PORTAADDR4 -address_a[4] => ram_block1a127.PORTAADDR4 -address_a[4] => ram_block1a128.PORTAADDR4 -address_a[4] => ram_block1a129.PORTAADDR4 -address_a[4] => ram_block1a130.PORTAADDR4 -address_a[4] => ram_block1a131.PORTAADDR4 -address_a[4] => ram_block1a132.PORTAADDR4 -address_a[4] => ram_block1a133.PORTAADDR4 -address_a[4] => ram_block1a134.PORTAADDR4 -address_a[4] => ram_block1a135.PORTAADDR4 -address_a[4] => ram_block1a136.PORTAADDR4 -address_a[4] => ram_block1a137.PORTAADDR4 -address_a[4] => ram_block1a138.PORTAADDR4 -address_a[4] => ram_block1a139.PORTAADDR4 -address_a[4] => ram_block1a140.PORTAADDR4 -address_a[4] => ram_block1a141.PORTAADDR4 -address_a[4] => ram_block1a142.PORTAADDR4 -address_a[4] => ram_block1a143.PORTAADDR4 -address_a[4] => ram_block1a144.PORTAADDR4 -address_a[4] => ram_block1a145.PORTAADDR4 -address_a[4] => ram_block1a146.PORTAADDR4 -address_a[4] => ram_block1a147.PORTAADDR4 -address_a[4] => ram_block1a148.PORTAADDR4 -address_a[4] => ram_block1a149.PORTAADDR4 -address_a[4] => ram_block1a150.PORTAADDR4 -address_a[4] => ram_block1a151.PORTAADDR4 -address_a[4] => ram_block1a152.PORTAADDR4 -address_a[4] => ram_block1a153.PORTAADDR4 -address_a[4] => ram_block1a154.PORTAADDR4 -address_a[4] => ram_block1a155.PORTAADDR4 -address_a[4] => ram_block1a156.PORTAADDR4 -address_a[4] => ram_block1a157.PORTAADDR4 -address_a[4] => ram_block1a158.PORTAADDR4 -address_a[4] => ram_block1a159.PORTAADDR4 -address_a[4] => ram_block1a160.PORTAADDR4 -address_a[4] => ram_block1a161.PORTAADDR4 -address_a[4] => ram_block1a162.PORTAADDR4 -address_a[4] => ram_block1a163.PORTAADDR4 -address_a[4] => ram_block1a164.PORTAADDR4 -address_a[4] => ram_block1a165.PORTAADDR4 -address_a[4] => ram_block1a166.PORTAADDR4 -address_a[4] => ram_block1a167.PORTAADDR4 -address_a[4] => ram_block1a168.PORTAADDR4 -address_a[4] => ram_block1a169.PORTAADDR4 -address_a[4] => ram_block1a170.PORTAADDR4 -address_a[4] => ram_block1a171.PORTAADDR4 -address_a[4] => ram_block1a172.PORTAADDR4 -address_a[4] => ram_block1a173.PORTAADDR4 -address_a[4] => ram_block1a174.PORTAADDR4 -address_a[4] => ram_block1a175.PORTAADDR4 -address_a[4] => ram_block1a176.PORTAADDR4 -address_a[4] => ram_block1a177.PORTAADDR4 -address_a[4] => ram_block1a178.PORTAADDR4 -address_a[4] => ram_block1a179.PORTAADDR4 -address_a[4] => ram_block1a180.PORTAADDR4 -address_a[4] => ram_block1a181.PORTAADDR4 -address_a[4] => ram_block1a182.PORTAADDR4 -address_a[4] => ram_block1a183.PORTAADDR4 -address_a[4] => ram_block1a184.PORTAADDR4 -address_a[4] => ram_block1a185.PORTAADDR4 -address_a[4] => ram_block1a186.PORTAADDR4 -address_a[4] => ram_block1a187.PORTAADDR4 -address_a[4] => ram_block1a188.PORTAADDR4 -address_a[4] => ram_block1a189.PORTAADDR4 -address_a[4] => ram_block1a190.PORTAADDR4 -address_a[4] => ram_block1a191.PORTAADDR4 -address_a[4] => ram_block1a192.PORTAADDR4 -address_a[4] => ram_block1a193.PORTAADDR4 -address_a[4] => ram_block1a194.PORTAADDR4 -address_a[4] => ram_block1a195.PORTAADDR4 -address_a[4] => ram_block1a196.PORTAADDR4 -address_a[4] => ram_block1a197.PORTAADDR4 -address_a[4] => ram_block1a198.PORTAADDR4 -address_a[4] => ram_block1a199.PORTAADDR4 -address_a[4] => ram_block1a200.PORTAADDR4 -address_a[4] => ram_block1a201.PORTAADDR4 -address_a[4] => ram_block1a202.PORTAADDR4 -address_a[4] => ram_block1a203.PORTAADDR4 -address_a[4] => ram_block1a204.PORTAADDR4 -address_a[4] => ram_block1a205.PORTAADDR4 -address_a[4] => ram_block1a206.PORTAADDR4 -address_a[4] => ram_block1a207.PORTAADDR4 -address_a[4] => ram_block1a208.PORTAADDR4 -address_a[4] => ram_block1a209.PORTAADDR4 -address_a[4] => ram_block1a210.PORTAADDR4 -address_a[4] => ram_block1a211.PORTAADDR4 -address_a[4] => ram_block1a212.PORTAADDR4 -address_a[4] => ram_block1a213.PORTAADDR4 -address_a[4] => ram_block1a214.PORTAADDR4 -address_a[4] => ram_block1a215.PORTAADDR4 -address_a[4] => ram_block1a216.PORTAADDR4 -address_a[4] => ram_block1a217.PORTAADDR4 -address_a[4] => ram_block1a218.PORTAADDR4 -address_a[4] => ram_block1a219.PORTAADDR4 -address_a[4] => ram_block1a220.PORTAADDR4 -address_a[4] => ram_block1a221.PORTAADDR4 -address_a[4] => ram_block1a222.PORTAADDR4 -address_a[4] => ram_block1a223.PORTAADDR4 -address_a[5] => ram_block1a0.PORTAADDR5 -address_a[5] => ram_block1a1.PORTAADDR5 -address_a[5] => ram_block1a2.PORTAADDR5 -address_a[5] => ram_block1a3.PORTAADDR5 -address_a[5] => ram_block1a4.PORTAADDR5 -address_a[5] => ram_block1a5.PORTAADDR5 -address_a[5] => ram_block1a6.PORTAADDR5 -address_a[5] => ram_block1a7.PORTAADDR5 -address_a[5] => ram_block1a8.PORTAADDR5 -address_a[5] => ram_block1a9.PORTAADDR5 -address_a[5] => ram_block1a10.PORTAADDR5 -address_a[5] => ram_block1a11.PORTAADDR5 -address_a[5] => ram_block1a12.PORTAADDR5 -address_a[5] => ram_block1a13.PORTAADDR5 -address_a[5] => ram_block1a14.PORTAADDR5 -address_a[5] => ram_block1a15.PORTAADDR5 -address_a[5] => ram_block1a16.PORTAADDR5 -address_a[5] => ram_block1a17.PORTAADDR5 -address_a[5] => ram_block1a18.PORTAADDR5 -address_a[5] => ram_block1a19.PORTAADDR5 -address_a[5] => ram_block1a20.PORTAADDR5 -address_a[5] => ram_block1a21.PORTAADDR5 -address_a[5] => ram_block1a22.PORTAADDR5 -address_a[5] => ram_block1a23.PORTAADDR5 -address_a[5] => ram_block1a24.PORTAADDR5 -address_a[5] => ram_block1a25.PORTAADDR5 -address_a[5] => ram_block1a26.PORTAADDR5 -address_a[5] => ram_block1a27.PORTAADDR5 -address_a[5] => ram_block1a28.PORTAADDR5 -address_a[5] => ram_block1a29.PORTAADDR5 -address_a[5] => ram_block1a30.PORTAADDR5 -address_a[5] => ram_block1a31.PORTAADDR5 -address_a[5] => ram_block1a32.PORTAADDR5 -address_a[5] => ram_block1a33.PORTAADDR5 -address_a[5] => ram_block1a34.PORTAADDR5 -address_a[5] => ram_block1a35.PORTAADDR5 -address_a[5] => ram_block1a36.PORTAADDR5 -address_a[5] => ram_block1a37.PORTAADDR5 -address_a[5] => ram_block1a38.PORTAADDR5 -address_a[5] => ram_block1a39.PORTAADDR5 -address_a[5] => ram_block1a40.PORTAADDR5 -address_a[5] => ram_block1a41.PORTAADDR5 -address_a[5] => ram_block1a42.PORTAADDR5 -address_a[5] => ram_block1a43.PORTAADDR5 -address_a[5] => ram_block1a44.PORTAADDR5 -address_a[5] => ram_block1a45.PORTAADDR5 -address_a[5] => ram_block1a46.PORTAADDR5 -address_a[5] => ram_block1a47.PORTAADDR5 -address_a[5] => ram_block1a48.PORTAADDR5 -address_a[5] => ram_block1a49.PORTAADDR5 -address_a[5] => ram_block1a50.PORTAADDR5 -address_a[5] => ram_block1a51.PORTAADDR5 -address_a[5] => ram_block1a52.PORTAADDR5 -address_a[5] => ram_block1a53.PORTAADDR5 -address_a[5] => ram_block1a54.PORTAADDR5 -address_a[5] => ram_block1a55.PORTAADDR5 -address_a[5] => ram_block1a56.PORTAADDR5 -address_a[5] => ram_block1a57.PORTAADDR5 -address_a[5] => ram_block1a58.PORTAADDR5 -address_a[5] => ram_block1a59.PORTAADDR5 -address_a[5] => ram_block1a60.PORTAADDR5 -address_a[5] => ram_block1a61.PORTAADDR5 -address_a[5] => ram_block1a62.PORTAADDR5 -address_a[5] => ram_block1a63.PORTAADDR5 -address_a[5] => ram_block1a64.PORTAADDR5 -address_a[5] => ram_block1a65.PORTAADDR5 -address_a[5] => ram_block1a66.PORTAADDR5 -address_a[5] => ram_block1a67.PORTAADDR5 -address_a[5] => ram_block1a68.PORTAADDR5 -address_a[5] => ram_block1a69.PORTAADDR5 -address_a[5] => ram_block1a70.PORTAADDR5 -address_a[5] => ram_block1a71.PORTAADDR5 -address_a[5] => ram_block1a72.PORTAADDR5 -address_a[5] => ram_block1a73.PORTAADDR5 -address_a[5] => ram_block1a74.PORTAADDR5 -address_a[5] => ram_block1a75.PORTAADDR5 -address_a[5] => ram_block1a76.PORTAADDR5 -address_a[5] => ram_block1a77.PORTAADDR5 -address_a[5] => ram_block1a78.PORTAADDR5 -address_a[5] => ram_block1a79.PORTAADDR5 -address_a[5] => ram_block1a80.PORTAADDR5 -address_a[5] => ram_block1a81.PORTAADDR5 -address_a[5] => ram_block1a82.PORTAADDR5 -address_a[5] => ram_block1a83.PORTAADDR5 -address_a[5] => ram_block1a84.PORTAADDR5 -address_a[5] => ram_block1a85.PORTAADDR5 -address_a[5] => ram_block1a86.PORTAADDR5 -address_a[5] => ram_block1a87.PORTAADDR5 -address_a[5] => ram_block1a88.PORTAADDR5 -address_a[5] => ram_block1a89.PORTAADDR5 -address_a[5] => ram_block1a90.PORTAADDR5 -address_a[5] => ram_block1a91.PORTAADDR5 -address_a[5] => ram_block1a92.PORTAADDR5 -address_a[5] => ram_block1a93.PORTAADDR5 -address_a[5] => ram_block1a94.PORTAADDR5 -address_a[5] => ram_block1a95.PORTAADDR5 -address_a[5] => ram_block1a96.PORTAADDR5 -address_a[5] => ram_block1a97.PORTAADDR5 -address_a[5] => ram_block1a98.PORTAADDR5 -address_a[5] => ram_block1a99.PORTAADDR5 -address_a[5] => ram_block1a100.PORTAADDR5 -address_a[5] => ram_block1a101.PORTAADDR5 -address_a[5] => ram_block1a102.PORTAADDR5 -address_a[5] => ram_block1a103.PORTAADDR5 -address_a[5] => ram_block1a104.PORTAADDR5 -address_a[5] => ram_block1a105.PORTAADDR5 -address_a[5] => ram_block1a106.PORTAADDR5 -address_a[5] => ram_block1a107.PORTAADDR5 -address_a[5] => ram_block1a108.PORTAADDR5 -address_a[5] => ram_block1a109.PORTAADDR5 -address_a[5] => ram_block1a110.PORTAADDR5 -address_a[5] => ram_block1a111.PORTAADDR5 -address_a[5] => ram_block1a112.PORTAADDR5 -address_a[5] => ram_block1a113.PORTAADDR5 -address_a[5] => ram_block1a114.PORTAADDR5 -address_a[5] => ram_block1a115.PORTAADDR5 -address_a[5] => ram_block1a116.PORTAADDR5 -address_a[5] => ram_block1a117.PORTAADDR5 -address_a[5] => ram_block1a118.PORTAADDR5 -address_a[5] => ram_block1a119.PORTAADDR5 -address_a[5] => ram_block1a120.PORTAADDR5 -address_a[5] => ram_block1a121.PORTAADDR5 -address_a[5] => ram_block1a122.PORTAADDR5 -address_a[5] => ram_block1a123.PORTAADDR5 -address_a[5] => ram_block1a124.PORTAADDR5 -address_a[5] => ram_block1a125.PORTAADDR5 -address_a[5] => ram_block1a126.PORTAADDR5 -address_a[5] => ram_block1a127.PORTAADDR5 -address_a[5] => ram_block1a128.PORTAADDR5 -address_a[5] => ram_block1a129.PORTAADDR5 -address_a[5] => ram_block1a130.PORTAADDR5 -address_a[5] => ram_block1a131.PORTAADDR5 -address_a[5] => ram_block1a132.PORTAADDR5 -address_a[5] => ram_block1a133.PORTAADDR5 -address_a[5] => ram_block1a134.PORTAADDR5 -address_a[5] => ram_block1a135.PORTAADDR5 -address_a[5] => ram_block1a136.PORTAADDR5 -address_a[5] => ram_block1a137.PORTAADDR5 -address_a[5] => ram_block1a138.PORTAADDR5 -address_a[5] => ram_block1a139.PORTAADDR5 -address_a[5] => ram_block1a140.PORTAADDR5 -address_a[5] => ram_block1a141.PORTAADDR5 -address_a[5] => ram_block1a142.PORTAADDR5 -address_a[5] => ram_block1a143.PORTAADDR5 -address_a[5] => ram_block1a144.PORTAADDR5 -address_a[5] => ram_block1a145.PORTAADDR5 -address_a[5] => ram_block1a146.PORTAADDR5 -address_a[5] => ram_block1a147.PORTAADDR5 -address_a[5] => ram_block1a148.PORTAADDR5 -address_a[5] => ram_block1a149.PORTAADDR5 -address_a[5] => ram_block1a150.PORTAADDR5 -address_a[5] => ram_block1a151.PORTAADDR5 -address_a[5] => ram_block1a152.PORTAADDR5 -address_a[5] => ram_block1a153.PORTAADDR5 -address_a[5] => ram_block1a154.PORTAADDR5 -address_a[5] => ram_block1a155.PORTAADDR5 -address_a[5] => ram_block1a156.PORTAADDR5 -address_a[5] => ram_block1a157.PORTAADDR5 -address_a[5] => ram_block1a158.PORTAADDR5 -address_a[5] => ram_block1a159.PORTAADDR5 -address_a[5] => ram_block1a160.PORTAADDR5 -address_a[5] => ram_block1a161.PORTAADDR5 -address_a[5] => ram_block1a162.PORTAADDR5 -address_a[5] => ram_block1a163.PORTAADDR5 -address_a[5] => ram_block1a164.PORTAADDR5 -address_a[5] => ram_block1a165.PORTAADDR5 -address_a[5] => ram_block1a166.PORTAADDR5 -address_a[5] => ram_block1a167.PORTAADDR5 -address_a[5] => ram_block1a168.PORTAADDR5 -address_a[5] => ram_block1a169.PORTAADDR5 -address_a[5] => ram_block1a170.PORTAADDR5 -address_a[5] => ram_block1a171.PORTAADDR5 -address_a[5] => ram_block1a172.PORTAADDR5 -address_a[5] => ram_block1a173.PORTAADDR5 -address_a[5] => ram_block1a174.PORTAADDR5 -address_a[5] => ram_block1a175.PORTAADDR5 -address_a[5] => ram_block1a176.PORTAADDR5 -address_a[5] => ram_block1a177.PORTAADDR5 -address_a[5] => ram_block1a178.PORTAADDR5 -address_a[5] => ram_block1a179.PORTAADDR5 -address_a[5] => ram_block1a180.PORTAADDR5 -address_a[5] => ram_block1a181.PORTAADDR5 -address_a[5] => ram_block1a182.PORTAADDR5 -address_a[5] => ram_block1a183.PORTAADDR5 -address_a[5] => ram_block1a184.PORTAADDR5 -address_a[5] => ram_block1a185.PORTAADDR5 -address_a[5] => ram_block1a186.PORTAADDR5 -address_a[5] => ram_block1a187.PORTAADDR5 -address_a[5] => ram_block1a188.PORTAADDR5 -address_a[5] => ram_block1a189.PORTAADDR5 -address_a[5] => ram_block1a190.PORTAADDR5 -address_a[5] => ram_block1a191.PORTAADDR5 -address_a[5] => ram_block1a192.PORTAADDR5 -address_a[5] => ram_block1a193.PORTAADDR5 -address_a[5] => ram_block1a194.PORTAADDR5 -address_a[5] => ram_block1a195.PORTAADDR5 -address_a[5] => ram_block1a196.PORTAADDR5 -address_a[5] => ram_block1a197.PORTAADDR5 -address_a[5] => ram_block1a198.PORTAADDR5 -address_a[5] => ram_block1a199.PORTAADDR5 -address_a[5] => ram_block1a200.PORTAADDR5 -address_a[5] => ram_block1a201.PORTAADDR5 -address_a[5] => ram_block1a202.PORTAADDR5 -address_a[5] => ram_block1a203.PORTAADDR5 -address_a[5] => ram_block1a204.PORTAADDR5 -address_a[5] => ram_block1a205.PORTAADDR5 -address_a[5] => ram_block1a206.PORTAADDR5 -address_a[5] => ram_block1a207.PORTAADDR5 -address_a[5] => ram_block1a208.PORTAADDR5 -address_a[5] => ram_block1a209.PORTAADDR5 -address_a[5] => ram_block1a210.PORTAADDR5 -address_a[5] => ram_block1a211.PORTAADDR5 -address_a[5] => ram_block1a212.PORTAADDR5 -address_a[5] => ram_block1a213.PORTAADDR5 -address_a[5] => ram_block1a214.PORTAADDR5 -address_a[5] => ram_block1a215.PORTAADDR5 -address_a[5] => ram_block1a216.PORTAADDR5 -address_a[5] => ram_block1a217.PORTAADDR5 -address_a[5] => ram_block1a218.PORTAADDR5 -address_a[5] => ram_block1a219.PORTAADDR5 -address_a[5] => ram_block1a220.PORTAADDR5 -address_a[5] => ram_block1a221.PORTAADDR5 -address_a[5] => ram_block1a222.PORTAADDR5 -address_a[5] => ram_block1a223.PORTAADDR5 -address_a[6] => ram_block1a0.PORTAADDR6 -address_a[6] => ram_block1a1.PORTAADDR6 -address_a[6] => ram_block1a2.PORTAADDR6 -address_a[6] => ram_block1a3.PORTAADDR6 -address_a[6] => ram_block1a4.PORTAADDR6 -address_a[6] => ram_block1a5.PORTAADDR6 -address_a[6] => ram_block1a6.PORTAADDR6 -address_a[6] => ram_block1a7.PORTAADDR6 -address_a[6] => ram_block1a8.PORTAADDR6 -address_a[6] => ram_block1a9.PORTAADDR6 -address_a[6] => ram_block1a10.PORTAADDR6 -address_a[6] => ram_block1a11.PORTAADDR6 -address_a[6] => ram_block1a12.PORTAADDR6 -address_a[6] => ram_block1a13.PORTAADDR6 -address_a[6] => ram_block1a14.PORTAADDR6 -address_a[6] => ram_block1a15.PORTAADDR6 -address_a[6] => ram_block1a16.PORTAADDR6 -address_a[6] => ram_block1a17.PORTAADDR6 -address_a[6] => ram_block1a18.PORTAADDR6 -address_a[6] => ram_block1a19.PORTAADDR6 -address_a[6] => ram_block1a20.PORTAADDR6 -address_a[6] => ram_block1a21.PORTAADDR6 -address_a[6] => ram_block1a22.PORTAADDR6 -address_a[6] => ram_block1a23.PORTAADDR6 -address_a[6] => ram_block1a24.PORTAADDR6 -address_a[6] => ram_block1a25.PORTAADDR6 -address_a[6] => ram_block1a26.PORTAADDR6 -address_a[6] => ram_block1a27.PORTAADDR6 -address_a[6] => ram_block1a28.PORTAADDR6 -address_a[6] => ram_block1a29.PORTAADDR6 -address_a[6] => ram_block1a30.PORTAADDR6 -address_a[6] => ram_block1a31.PORTAADDR6 -address_a[6] => ram_block1a32.PORTAADDR6 -address_a[6] => ram_block1a33.PORTAADDR6 -address_a[6] => ram_block1a34.PORTAADDR6 -address_a[6] => ram_block1a35.PORTAADDR6 -address_a[6] => ram_block1a36.PORTAADDR6 -address_a[6] => ram_block1a37.PORTAADDR6 -address_a[6] => ram_block1a38.PORTAADDR6 -address_a[6] => ram_block1a39.PORTAADDR6 -address_a[6] => ram_block1a40.PORTAADDR6 -address_a[6] => ram_block1a41.PORTAADDR6 -address_a[6] => ram_block1a42.PORTAADDR6 -address_a[6] => ram_block1a43.PORTAADDR6 -address_a[6] => ram_block1a44.PORTAADDR6 -address_a[6] => ram_block1a45.PORTAADDR6 -address_a[6] => ram_block1a46.PORTAADDR6 -address_a[6] => ram_block1a47.PORTAADDR6 -address_a[6] => ram_block1a48.PORTAADDR6 -address_a[6] => ram_block1a49.PORTAADDR6 -address_a[6] => ram_block1a50.PORTAADDR6 -address_a[6] => ram_block1a51.PORTAADDR6 -address_a[6] => ram_block1a52.PORTAADDR6 -address_a[6] => ram_block1a53.PORTAADDR6 -address_a[6] => ram_block1a54.PORTAADDR6 -address_a[6] => ram_block1a55.PORTAADDR6 -address_a[6] => ram_block1a56.PORTAADDR6 -address_a[6] => ram_block1a57.PORTAADDR6 -address_a[6] => ram_block1a58.PORTAADDR6 -address_a[6] => ram_block1a59.PORTAADDR6 -address_a[6] => ram_block1a60.PORTAADDR6 -address_a[6] => ram_block1a61.PORTAADDR6 -address_a[6] => ram_block1a62.PORTAADDR6 -address_a[6] => ram_block1a63.PORTAADDR6 -address_a[6] => ram_block1a64.PORTAADDR6 -address_a[6] => ram_block1a65.PORTAADDR6 -address_a[6] => ram_block1a66.PORTAADDR6 -address_a[6] => ram_block1a67.PORTAADDR6 -address_a[6] => ram_block1a68.PORTAADDR6 -address_a[6] => ram_block1a69.PORTAADDR6 -address_a[6] => ram_block1a70.PORTAADDR6 -address_a[6] => ram_block1a71.PORTAADDR6 -address_a[6] => ram_block1a72.PORTAADDR6 -address_a[6] => ram_block1a73.PORTAADDR6 -address_a[6] => ram_block1a74.PORTAADDR6 -address_a[6] => ram_block1a75.PORTAADDR6 -address_a[6] => ram_block1a76.PORTAADDR6 -address_a[6] => ram_block1a77.PORTAADDR6 -address_a[6] => ram_block1a78.PORTAADDR6 -address_a[6] => ram_block1a79.PORTAADDR6 -address_a[6] => ram_block1a80.PORTAADDR6 -address_a[6] => ram_block1a81.PORTAADDR6 -address_a[6] => ram_block1a82.PORTAADDR6 -address_a[6] => ram_block1a83.PORTAADDR6 -address_a[6] => ram_block1a84.PORTAADDR6 -address_a[6] => ram_block1a85.PORTAADDR6 -address_a[6] => ram_block1a86.PORTAADDR6 -address_a[6] => ram_block1a87.PORTAADDR6 -address_a[6] => ram_block1a88.PORTAADDR6 -address_a[6] => ram_block1a89.PORTAADDR6 -address_a[6] => ram_block1a90.PORTAADDR6 -address_a[6] => ram_block1a91.PORTAADDR6 -address_a[6] => ram_block1a92.PORTAADDR6 -address_a[6] => ram_block1a93.PORTAADDR6 -address_a[6] => ram_block1a94.PORTAADDR6 -address_a[6] => ram_block1a95.PORTAADDR6 -address_a[6] => ram_block1a96.PORTAADDR6 -address_a[6] => ram_block1a97.PORTAADDR6 -address_a[6] => ram_block1a98.PORTAADDR6 -address_a[6] => ram_block1a99.PORTAADDR6 -address_a[6] => ram_block1a100.PORTAADDR6 -address_a[6] => ram_block1a101.PORTAADDR6 -address_a[6] => ram_block1a102.PORTAADDR6 -address_a[6] => ram_block1a103.PORTAADDR6 -address_a[6] => ram_block1a104.PORTAADDR6 -address_a[6] => ram_block1a105.PORTAADDR6 -address_a[6] => ram_block1a106.PORTAADDR6 -address_a[6] => ram_block1a107.PORTAADDR6 -address_a[6] => ram_block1a108.PORTAADDR6 -address_a[6] => ram_block1a109.PORTAADDR6 -address_a[6] => ram_block1a110.PORTAADDR6 -address_a[6] => ram_block1a111.PORTAADDR6 -address_a[6] => ram_block1a112.PORTAADDR6 -address_a[6] => ram_block1a113.PORTAADDR6 -address_a[6] => ram_block1a114.PORTAADDR6 -address_a[6] => ram_block1a115.PORTAADDR6 -address_a[6] => ram_block1a116.PORTAADDR6 -address_a[6] => ram_block1a117.PORTAADDR6 -address_a[6] => ram_block1a118.PORTAADDR6 -address_a[6] => ram_block1a119.PORTAADDR6 -address_a[6] => ram_block1a120.PORTAADDR6 -address_a[6] => ram_block1a121.PORTAADDR6 -address_a[6] => ram_block1a122.PORTAADDR6 -address_a[6] => ram_block1a123.PORTAADDR6 -address_a[6] => ram_block1a124.PORTAADDR6 -address_a[6] => ram_block1a125.PORTAADDR6 -address_a[6] => ram_block1a126.PORTAADDR6 -address_a[6] => ram_block1a127.PORTAADDR6 -address_a[6] => ram_block1a128.PORTAADDR6 -address_a[6] => ram_block1a129.PORTAADDR6 -address_a[6] => ram_block1a130.PORTAADDR6 -address_a[6] => ram_block1a131.PORTAADDR6 -address_a[6] => ram_block1a132.PORTAADDR6 -address_a[6] => ram_block1a133.PORTAADDR6 -address_a[6] => ram_block1a134.PORTAADDR6 -address_a[6] => ram_block1a135.PORTAADDR6 -address_a[6] => ram_block1a136.PORTAADDR6 -address_a[6] => ram_block1a137.PORTAADDR6 -address_a[6] => ram_block1a138.PORTAADDR6 -address_a[6] => ram_block1a139.PORTAADDR6 -address_a[6] => ram_block1a140.PORTAADDR6 -address_a[6] => ram_block1a141.PORTAADDR6 -address_a[6] => ram_block1a142.PORTAADDR6 -address_a[6] => ram_block1a143.PORTAADDR6 -address_a[6] => ram_block1a144.PORTAADDR6 -address_a[6] => ram_block1a145.PORTAADDR6 -address_a[6] => ram_block1a146.PORTAADDR6 -address_a[6] => ram_block1a147.PORTAADDR6 -address_a[6] => ram_block1a148.PORTAADDR6 -address_a[6] => ram_block1a149.PORTAADDR6 -address_a[6] => ram_block1a150.PORTAADDR6 -address_a[6] => ram_block1a151.PORTAADDR6 -address_a[6] => ram_block1a152.PORTAADDR6 -address_a[6] => ram_block1a153.PORTAADDR6 -address_a[6] => ram_block1a154.PORTAADDR6 -address_a[6] => ram_block1a155.PORTAADDR6 -address_a[6] => ram_block1a156.PORTAADDR6 -address_a[6] => ram_block1a157.PORTAADDR6 -address_a[6] => ram_block1a158.PORTAADDR6 -address_a[6] => ram_block1a159.PORTAADDR6 -address_a[6] => ram_block1a160.PORTAADDR6 -address_a[6] => ram_block1a161.PORTAADDR6 -address_a[6] => ram_block1a162.PORTAADDR6 -address_a[6] => ram_block1a163.PORTAADDR6 -address_a[6] => ram_block1a164.PORTAADDR6 -address_a[6] => ram_block1a165.PORTAADDR6 -address_a[6] => ram_block1a166.PORTAADDR6 -address_a[6] => ram_block1a167.PORTAADDR6 -address_a[6] => ram_block1a168.PORTAADDR6 -address_a[6] => ram_block1a169.PORTAADDR6 -address_a[6] => ram_block1a170.PORTAADDR6 -address_a[6] => ram_block1a171.PORTAADDR6 -address_a[6] => ram_block1a172.PORTAADDR6 -address_a[6] => ram_block1a173.PORTAADDR6 -address_a[6] => ram_block1a174.PORTAADDR6 -address_a[6] => ram_block1a175.PORTAADDR6 -address_a[6] => ram_block1a176.PORTAADDR6 -address_a[6] => ram_block1a177.PORTAADDR6 -address_a[6] => ram_block1a178.PORTAADDR6 -address_a[6] => ram_block1a179.PORTAADDR6 -address_a[6] => ram_block1a180.PORTAADDR6 -address_a[6] => ram_block1a181.PORTAADDR6 -address_a[6] => ram_block1a182.PORTAADDR6 -address_a[6] => ram_block1a183.PORTAADDR6 -address_a[6] => ram_block1a184.PORTAADDR6 -address_a[6] => ram_block1a185.PORTAADDR6 -address_a[6] => ram_block1a186.PORTAADDR6 -address_a[6] => ram_block1a187.PORTAADDR6 -address_a[6] => ram_block1a188.PORTAADDR6 -address_a[6] => ram_block1a189.PORTAADDR6 -address_a[6] => ram_block1a190.PORTAADDR6 -address_a[6] => ram_block1a191.PORTAADDR6 -address_a[6] => ram_block1a192.PORTAADDR6 -address_a[6] => ram_block1a193.PORTAADDR6 -address_a[6] => ram_block1a194.PORTAADDR6 -address_a[6] => ram_block1a195.PORTAADDR6 -address_a[6] => ram_block1a196.PORTAADDR6 -address_a[6] => ram_block1a197.PORTAADDR6 -address_a[6] => ram_block1a198.PORTAADDR6 -address_a[6] => ram_block1a199.PORTAADDR6 -address_a[6] => ram_block1a200.PORTAADDR6 -address_a[6] => ram_block1a201.PORTAADDR6 -address_a[6] => ram_block1a202.PORTAADDR6 -address_a[6] => ram_block1a203.PORTAADDR6 -address_a[6] => ram_block1a204.PORTAADDR6 -address_a[6] => ram_block1a205.PORTAADDR6 -address_a[6] => ram_block1a206.PORTAADDR6 -address_a[6] => ram_block1a207.PORTAADDR6 -address_a[6] => ram_block1a208.PORTAADDR6 -address_a[6] => ram_block1a209.PORTAADDR6 -address_a[6] => ram_block1a210.PORTAADDR6 -address_a[6] => ram_block1a211.PORTAADDR6 -address_a[6] => ram_block1a212.PORTAADDR6 -address_a[6] => ram_block1a213.PORTAADDR6 -address_a[6] => ram_block1a214.PORTAADDR6 -address_a[6] => ram_block1a215.PORTAADDR6 -address_a[6] => ram_block1a216.PORTAADDR6 -address_a[6] => ram_block1a217.PORTAADDR6 -address_a[6] => ram_block1a218.PORTAADDR6 -address_a[6] => ram_block1a219.PORTAADDR6 -address_a[6] => ram_block1a220.PORTAADDR6 -address_a[6] => ram_block1a221.PORTAADDR6 -address_a[6] => ram_block1a222.PORTAADDR6 -address_a[6] => ram_block1a223.PORTAADDR6 -address_a[7] => ram_block1a0.PORTAADDR7 -address_a[7] => ram_block1a1.PORTAADDR7 -address_a[7] => ram_block1a2.PORTAADDR7 -address_a[7] => ram_block1a3.PORTAADDR7 -address_a[7] => ram_block1a4.PORTAADDR7 -address_a[7] => ram_block1a5.PORTAADDR7 -address_a[7] => ram_block1a6.PORTAADDR7 -address_a[7] => ram_block1a7.PORTAADDR7 -address_a[7] => ram_block1a8.PORTAADDR7 -address_a[7] => ram_block1a9.PORTAADDR7 -address_a[7] => ram_block1a10.PORTAADDR7 -address_a[7] => ram_block1a11.PORTAADDR7 -address_a[7] => ram_block1a12.PORTAADDR7 -address_a[7] => ram_block1a13.PORTAADDR7 -address_a[7] => ram_block1a14.PORTAADDR7 -address_a[7] => ram_block1a15.PORTAADDR7 -address_a[7] => ram_block1a16.PORTAADDR7 -address_a[7] => ram_block1a17.PORTAADDR7 -address_a[7] => ram_block1a18.PORTAADDR7 -address_a[7] => ram_block1a19.PORTAADDR7 -address_a[7] => ram_block1a20.PORTAADDR7 -address_a[7] => ram_block1a21.PORTAADDR7 -address_a[7] => ram_block1a22.PORTAADDR7 -address_a[7] => ram_block1a23.PORTAADDR7 -address_a[7] => ram_block1a24.PORTAADDR7 -address_a[7] => ram_block1a25.PORTAADDR7 -address_a[7] => ram_block1a26.PORTAADDR7 -address_a[7] => ram_block1a27.PORTAADDR7 -address_a[7] => ram_block1a28.PORTAADDR7 -address_a[7] => ram_block1a29.PORTAADDR7 -address_a[7] => ram_block1a30.PORTAADDR7 -address_a[7] => ram_block1a31.PORTAADDR7 -address_a[7] => ram_block1a32.PORTAADDR7 -address_a[7] => ram_block1a33.PORTAADDR7 -address_a[7] => ram_block1a34.PORTAADDR7 -address_a[7] => ram_block1a35.PORTAADDR7 -address_a[7] => ram_block1a36.PORTAADDR7 -address_a[7] => ram_block1a37.PORTAADDR7 -address_a[7] => ram_block1a38.PORTAADDR7 -address_a[7] => ram_block1a39.PORTAADDR7 -address_a[7] => ram_block1a40.PORTAADDR7 -address_a[7] => ram_block1a41.PORTAADDR7 -address_a[7] => ram_block1a42.PORTAADDR7 -address_a[7] => ram_block1a43.PORTAADDR7 -address_a[7] => ram_block1a44.PORTAADDR7 -address_a[7] => ram_block1a45.PORTAADDR7 -address_a[7] => ram_block1a46.PORTAADDR7 -address_a[7] => ram_block1a47.PORTAADDR7 -address_a[7] => ram_block1a48.PORTAADDR7 -address_a[7] => ram_block1a49.PORTAADDR7 -address_a[7] => ram_block1a50.PORTAADDR7 -address_a[7] => ram_block1a51.PORTAADDR7 -address_a[7] => ram_block1a52.PORTAADDR7 -address_a[7] => ram_block1a53.PORTAADDR7 -address_a[7] => ram_block1a54.PORTAADDR7 -address_a[7] => ram_block1a55.PORTAADDR7 -address_a[7] => ram_block1a56.PORTAADDR7 -address_a[7] => ram_block1a57.PORTAADDR7 -address_a[7] => ram_block1a58.PORTAADDR7 -address_a[7] => ram_block1a59.PORTAADDR7 -address_a[7] => ram_block1a60.PORTAADDR7 -address_a[7] => ram_block1a61.PORTAADDR7 -address_a[7] => ram_block1a62.PORTAADDR7 -address_a[7] => ram_block1a63.PORTAADDR7 -address_a[7] => ram_block1a64.PORTAADDR7 -address_a[7] => ram_block1a65.PORTAADDR7 -address_a[7] => ram_block1a66.PORTAADDR7 -address_a[7] => ram_block1a67.PORTAADDR7 -address_a[7] => ram_block1a68.PORTAADDR7 -address_a[7] => ram_block1a69.PORTAADDR7 -address_a[7] => ram_block1a70.PORTAADDR7 -address_a[7] => ram_block1a71.PORTAADDR7 -address_a[7] => ram_block1a72.PORTAADDR7 -address_a[7] => ram_block1a73.PORTAADDR7 -address_a[7] => ram_block1a74.PORTAADDR7 -address_a[7] => ram_block1a75.PORTAADDR7 -address_a[7] => ram_block1a76.PORTAADDR7 -address_a[7] => ram_block1a77.PORTAADDR7 -address_a[7] => ram_block1a78.PORTAADDR7 -address_a[7] => ram_block1a79.PORTAADDR7 -address_a[7] => ram_block1a80.PORTAADDR7 -address_a[7] => ram_block1a81.PORTAADDR7 -address_a[7] => ram_block1a82.PORTAADDR7 -address_a[7] => ram_block1a83.PORTAADDR7 -address_a[7] => ram_block1a84.PORTAADDR7 -address_a[7] => ram_block1a85.PORTAADDR7 -address_a[7] => ram_block1a86.PORTAADDR7 -address_a[7] => ram_block1a87.PORTAADDR7 -address_a[7] => ram_block1a88.PORTAADDR7 -address_a[7] => ram_block1a89.PORTAADDR7 -address_a[7] => ram_block1a90.PORTAADDR7 -address_a[7] => ram_block1a91.PORTAADDR7 -address_a[7] => ram_block1a92.PORTAADDR7 -address_a[7] => ram_block1a93.PORTAADDR7 -address_a[7] => ram_block1a94.PORTAADDR7 -address_a[7] => ram_block1a95.PORTAADDR7 -address_a[7] => ram_block1a96.PORTAADDR7 -address_a[7] => ram_block1a97.PORTAADDR7 -address_a[7] => ram_block1a98.PORTAADDR7 -address_a[7] => ram_block1a99.PORTAADDR7 -address_a[7] => ram_block1a100.PORTAADDR7 -address_a[7] => ram_block1a101.PORTAADDR7 -address_a[7] => ram_block1a102.PORTAADDR7 -address_a[7] => ram_block1a103.PORTAADDR7 -address_a[7] => ram_block1a104.PORTAADDR7 -address_a[7] => ram_block1a105.PORTAADDR7 -address_a[7] => ram_block1a106.PORTAADDR7 -address_a[7] => ram_block1a107.PORTAADDR7 -address_a[7] => ram_block1a108.PORTAADDR7 -address_a[7] => ram_block1a109.PORTAADDR7 -address_a[7] => ram_block1a110.PORTAADDR7 -address_a[7] => ram_block1a111.PORTAADDR7 -address_a[7] => ram_block1a112.PORTAADDR7 -address_a[7] => ram_block1a113.PORTAADDR7 -address_a[7] => ram_block1a114.PORTAADDR7 -address_a[7] => ram_block1a115.PORTAADDR7 -address_a[7] => ram_block1a116.PORTAADDR7 -address_a[7] => ram_block1a117.PORTAADDR7 -address_a[7] => ram_block1a118.PORTAADDR7 -address_a[7] => ram_block1a119.PORTAADDR7 -address_a[7] => ram_block1a120.PORTAADDR7 -address_a[7] => ram_block1a121.PORTAADDR7 -address_a[7] => ram_block1a122.PORTAADDR7 -address_a[7] => ram_block1a123.PORTAADDR7 -address_a[7] => ram_block1a124.PORTAADDR7 -address_a[7] => ram_block1a125.PORTAADDR7 -address_a[7] => ram_block1a126.PORTAADDR7 -address_a[7] => ram_block1a127.PORTAADDR7 -address_a[7] => ram_block1a128.PORTAADDR7 -address_a[7] => ram_block1a129.PORTAADDR7 -address_a[7] => ram_block1a130.PORTAADDR7 -address_a[7] => ram_block1a131.PORTAADDR7 -address_a[7] => ram_block1a132.PORTAADDR7 -address_a[7] => ram_block1a133.PORTAADDR7 -address_a[7] => ram_block1a134.PORTAADDR7 -address_a[7] => ram_block1a135.PORTAADDR7 -address_a[7] => ram_block1a136.PORTAADDR7 -address_a[7] => ram_block1a137.PORTAADDR7 -address_a[7] => ram_block1a138.PORTAADDR7 -address_a[7] => ram_block1a139.PORTAADDR7 -address_a[7] => ram_block1a140.PORTAADDR7 -address_a[7] => ram_block1a141.PORTAADDR7 -address_a[7] => ram_block1a142.PORTAADDR7 -address_a[7] => ram_block1a143.PORTAADDR7 -address_a[7] => ram_block1a144.PORTAADDR7 -address_a[7] => ram_block1a145.PORTAADDR7 -address_a[7] => ram_block1a146.PORTAADDR7 -address_a[7] => ram_block1a147.PORTAADDR7 -address_a[7] => ram_block1a148.PORTAADDR7 -address_a[7] => ram_block1a149.PORTAADDR7 -address_a[7] => ram_block1a150.PORTAADDR7 -address_a[7] => ram_block1a151.PORTAADDR7 -address_a[7] => ram_block1a152.PORTAADDR7 -address_a[7] => ram_block1a153.PORTAADDR7 -address_a[7] => ram_block1a154.PORTAADDR7 -address_a[7] => ram_block1a155.PORTAADDR7 -address_a[7] => ram_block1a156.PORTAADDR7 -address_a[7] => ram_block1a157.PORTAADDR7 -address_a[7] => ram_block1a158.PORTAADDR7 -address_a[7] => ram_block1a159.PORTAADDR7 -address_a[7] => ram_block1a160.PORTAADDR7 -address_a[7] => ram_block1a161.PORTAADDR7 -address_a[7] => ram_block1a162.PORTAADDR7 -address_a[7] => ram_block1a163.PORTAADDR7 -address_a[7] => ram_block1a164.PORTAADDR7 -address_a[7] => ram_block1a165.PORTAADDR7 -address_a[7] => ram_block1a166.PORTAADDR7 -address_a[7] => ram_block1a167.PORTAADDR7 -address_a[7] => ram_block1a168.PORTAADDR7 -address_a[7] => ram_block1a169.PORTAADDR7 -address_a[7] => ram_block1a170.PORTAADDR7 -address_a[7] => ram_block1a171.PORTAADDR7 -address_a[7] => ram_block1a172.PORTAADDR7 -address_a[7] => ram_block1a173.PORTAADDR7 -address_a[7] => ram_block1a174.PORTAADDR7 -address_a[7] => ram_block1a175.PORTAADDR7 -address_a[7] => ram_block1a176.PORTAADDR7 -address_a[7] => ram_block1a177.PORTAADDR7 -address_a[7] => ram_block1a178.PORTAADDR7 -address_a[7] => ram_block1a179.PORTAADDR7 -address_a[7] => ram_block1a180.PORTAADDR7 -address_a[7] => ram_block1a181.PORTAADDR7 -address_a[7] => ram_block1a182.PORTAADDR7 -address_a[7] => ram_block1a183.PORTAADDR7 -address_a[7] => ram_block1a184.PORTAADDR7 -address_a[7] => ram_block1a185.PORTAADDR7 -address_a[7] => ram_block1a186.PORTAADDR7 -address_a[7] => ram_block1a187.PORTAADDR7 -address_a[7] => ram_block1a188.PORTAADDR7 -address_a[7] => ram_block1a189.PORTAADDR7 -address_a[7] => ram_block1a190.PORTAADDR7 -address_a[7] => ram_block1a191.PORTAADDR7 -address_a[7] => ram_block1a192.PORTAADDR7 -address_a[7] => ram_block1a193.PORTAADDR7 -address_a[7] => ram_block1a194.PORTAADDR7 -address_a[7] => ram_block1a195.PORTAADDR7 -address_a[7] => ram_block1a196.PORTAADDR7 -address_a[7] => ram_block1a197.PORTAADDR7 -address_a[7] => ram_block1a198.PORTAADDR7 -address_a[7] => ram_block1a199.PORTAADDR7 -address_a[7] => ram_block1a200.PORTAADDR7 -address_a[7] => ram_block1a201.PORTAADDR7 -address_a[7] => ram_block1a202.PORTAADDR7 -address_a[7] => ram_block1a203.PORTAADDR7 -address_a[7] => ram_block1a204.PORTAADDR7 -address_a[7] => ram_block1a205.PORTAADDR7 -address_a[7] => ram_block1a206.PORTAADDR7 -address_a[7] => ram_block1a207.PORTAADDR7 -address_a[7] => ram_block1a208.PORTAADDR7 -address_a[7] => ram_block1a209.PORTAADDR7 -address_a[7] => ram_block1a210.PORTAADDR7 -address_a[7] => ram_block1a211.PORTAADDR7 -address_a[7] => ram_block1a212.PORTAADDR7 -address_a[7] => ram_block1a213.PORTAADDR7 -address_a[7] => ram_block1a214.PORTAADDR7 -address_a[7] => ram_block1a215.PORTAADDR7 -address_a[7] => ram_block1a216.PORTAADDR7 -address_a[7] => ram_block1a217.PORTAADDR7 -address_a[7] => ram_block1a218.PORTAADDR7 -address_a[7] => ram_block1a219.PORTAADDR7 -address_a[7] => ram_block1a220.PORTAADDR7 -address_a[7] => ram_block1a221.PORTAADDR7 -address_a[7] => ram_block1a222.PORTAADDR7 -address_a[7] => ram_block1a223.PORTAADDR7 -address_a[8] => ram_block1a0.PORTAADDR8 -address_a[8] => ram_block1a1.PORTAADDR8 -address_a[8] => ram_block1a2.PORTAADDR8 -address_a[8] => ram_block1a3.PORTAADDR8 -address_a[8] => ram_block1a4.PORTAADDR8 -address_a[8] => ram_block1a5.PORTAADDR8 -address_a[8] => ram_block1a6.PORTAADDR8 -address_a[8] => ram_block1a7.PORTAADDR8 -address_a[8] => ram_block1a8.PORTAADDR8 -address_a[8] => ram_block1a9.PORTAADDR8 -address_a[8] => ram_block1a10.PORTAADDR8 -address_a[8] => ram_block1a11.PORTAADDR8 -address_a[8] => ram_block1a12.PORTAADDR8 -address_a[8] => ram_block1a13.PORTAADDR8 -address_a[8] => ram_block1a14.PORTAADDR8 -address_a[8] => ram_block1a15.PORTAADDR8 -address_a[8] => ram_block1a16.PORTAADDR8 -address_a[8] => ram_block1a17.PORTAADDR8 -address_a[8] => ram_block1a18.PORTAADDR8 -address_a[8] => ram_block1a19.PORTAADDR8 -address_a[8] => ram_block1a20.PORTAADDR8 -address_a[8] => ram_block1a21.PORTAADDR8 -address_a[8] => ram_block1a22.PORTAADDR8 -address_a[8] => ram_block1a23.PORTAADDR8 -address_a[8] => ram_block1a24.PORTAADDR8 -address_a[8] => ram_block1a25.PORTAADDR8 -address_a[8] => ram_block1a26.PORTAADDR8 -address_a[8] => ram_block1a27.PORTAADDR8 -address_a[8] => ram_block1a28.PORTAADDR8 -address_a[8] => ram_block1a29.PORTAADDR8 -address_a[8] => ram_block1a30.PORTAADDR8 -address_a[8] => ram_block1a31.PORTAADDR8 -address_a[8] => ram_block1a32.PORTAADDR8 -address_a[8] => ram_block1a33.PORTAADDR8 -address_a[8] => ram_block1a34.PORTAADDR8 -address_a[8] => ram_block1a35.PORTAADDR8 -address_a[8] => ram_block1a36.PORTAADDR8 -address_a[8] => ram_block1a37.PORTAADDR8 -address_a[8] => ram_block1a38.PORTAADDR8 -address_a[8] => ram_block1a39.PORTAADDR8 -address_a[8] => ram_block1a40.PORTAADDR8 -address_a[8] => ram_block1a41.PORTAADDR8 -address_a[8] => ram_block1a42.PORTAADDR8 -address_a[8] => ram_block1a43.PORTAADDR8 -address_a[8] => ram_block1a44.PORTAADDR8 -address_a[8] => ram_block1a45.PORTAADDR8 -address_a[8] => ram_block1a46.PORTAADDR8 -address_a[8] => ram_block1a47.PORTAADDR8 -address_a[8] => ram_block1a48.PORTAADDR8 -address_a[8] => ram_block1a49.PORTAADDR8 -address_a[8] => ram_block1a50.PORTAADDR8 -address_a[8] => ram_block1a51.PORTAADDR8 -address_a[8] => ram_block1a52.PORTAADDR8 -address_a[8] => ram_block1a53.PORTAADDR8 -address_a[8] => ram_block1a54.PORTAADDR8 -address_a[8] => ram_block1a55.PORTAADDR8 -address_a[8] => ram_block1a56.PORTAADDR8 -address_a[8] => ram_block1a57.PORTAADDR8 -address_a[8] => ram_block1a58.PORTAADDR8 -address_a[8] => ram_block1a59.PORTAADDR8 -address_a[8] => ram_block1a60.PORTAADDR8 -address_a[8] => ram_block1a61.PORTAADDR8 -address_a[8] => ram_block1a62.PORTAADDR8 -address_a[8] => ram_block1a63.PORTAADDR8 -address_a[8] => ram_block1a64.PORTAADDR8 -address_a[8] => ram_block1a65.PORTAADDR8 -address_a[8] => ram_block1a66.PORTAADDR8 -address_a[8] => ram_block1a67.PORTAADDR8 -address_a[8] => ram_block1a68.PORTAADDR8 -address_a[8] => ram_block1a69.PORTAADDR8 -address_a[8] => ram_block1a70.PORTAADDR8 -address_a[8] => ram_block1a71.PORTAADDR8 -address_a[8] => ram_block1a72.PORTAADDR8 -address_a[8] => ram_block1a73.PORTAADDR8 -address_a[8] => ram_block1a74.PORTAADDR8 -address_a[8] => ram_block1a75.PORTAADDR8 -address_a[8] => ram_block1a76.PORTAADDR8 -address_a[8] => ram_block1a77.PORTAADDR8 -address_a[8] => ram_block1a78.PORTAADDR8 -address_a[8] => ram_block1a79.PORTAADDR8 -address_a[8] => ram_block1a80.PORTAADDR8 -address_a[8] => ram_block1a81.PORTAADDR8 -address_a[8] => ram_block1a82.PORTAADDR8 -address_a[8] => ram_block1a83.PORTAADDR8 -address_a[8] => ram_block1a84.PORTAADDR8 -address_a[8] => ram_block1a85.PORTAADDR8 -address_a[8] => ram_block1a86.PORTAADDR8 -address_a[8] => ram_block1a87.PORTAADDR8 -address_a[8] => ram_block1a88.PORTAADDR8 -address_a[8] => ram_block1a89.PORTAADDR8 -address_a[8] => ram_block1a90.PORTAADDR8 -address_a[8] => ram_block1a91.PORTAADDR8 -address_a[8] => ram_block1a92.PORTAADDR8 -address_a[8] => ram_block1a93.PORTAADDR8 -address_a[8] => ram_block1a94.PORTAADDR8 -address_a[8] => ram_block1a95.PORTAADDR8 -address_a[8] => ram_block1a96.PORTAADDR8 -address_a[8] => ram_block1a97.PORTAADDR8 -address_a[8] => ram_block1a98.PORTAADDR8 -address_a[8] => ram_block1a99.PORTAADDR8 -address_a[8] => ram_block1a100.PORTAADDR8 -address_a[8] => ram_block1a101.PORTAADDR8 -address_a[8] => ram_block1a102.PORTAADDR8 -address_a[8] => ram_block1a103.PORTAADDR8 -address_a[8] => ram_block1a104.PORTAADDR8 -address_a[8] => ram_block1a105.PORTAADDR8 -address_a[8] => ram_block1a106.PORTAADDR8 -address_a[8] => ram_block1a107.PORTAADDR8 -address_a[8] => ram_block1a108.PORTAADDR8 -address_a[8] => ram_block1a109.PORTAADDR8 -address_a[8] => ram_block1a110.PORTAADDR8 -address_a[8] => ram_block1a111.PORTAADDR8 -address_a[8] => ram_block1a112.PORTAADDR8 -address_a[8] => ram_block1a113.PORTAADDR8 -address_a[8] => ram_block1a114.PORTAADDR8 -address_a[8] => ram_block1a115.PORTAADDR8 -address_a[8] => ram_block1a116.PORTAADDR8 -address_a[8] => ram_block1a117.PORTAADDR8 -address_a[8] => ram_block1a118.PORTAADDR8 -address_a[8] => ram_block1a119.PORTAADDR8 -address_a[8] => ram_block1a120.PORTAADDR8 -address_a[8] => ram_block1a121.PORTAADDR8 -address_a[8] => ram_block1a122.PORTAADDR8 -address_a[8] => ram_block1a123.PORTAADDR8 -address_a[8] => ram_block1a124.PORTAADDR8 -address_a[8] => ram_block1a125.PORTAADDR8 -address_a[8] => ram_block1a126.PORTAADDR8 -address_a[8] => ram_block1a127.PORTAADDR8 -address_a[8] => ram_block1a128.PORTAADDR8 -address_a[8] => ram_block1a129.PORTAADDR8 -address_a[8] => ram_block1a130.PORTAADDR8 -address_a[8] => ram_block1a131.PORTAADDR8 -address_a[8] => ram_block1a132.PORTAADDR8 -address_a[8] => ram_block1a133.PORTAADDR8 -address_a[8] => ram_block1a134.PORTAADDR8 -address_a[8] => ram_block1a135.PORTAADDR8 -address_a[8] => ram_block1a136.PORTAADDR8 -address_a[8] => ram_block1a137.PORTAADDR8 -address_a[8] => ram_block1a138.PORTAADDR8 -address_a[8] => ram_block1a139.PORTAADDR8 -address_a[8] => ram_block1a140.PORTAADDR8 -address_a[8] => ram_block1a141.PORTAADDR8 -address_a[8] => ram_block1a142.PORTAADDR8 -address_a[8] => ram_block1a143.PORTAADDR8 -address_a[8] => ram_block1a144.PORTAADDR8 -address_a[8] => ram_block1a145.PORTAADDR8 -address_a[8] => ram_block1a146.PORTAADDR8 -address_a[8] => ram_block1a147.PORTAADDR8 -address_a[8] => ram_block1a148.PORTAADDR8 -address_a[8] => ram_block1a149.PORTAADDR8 -address_a[8] => ram_block1a150.PORTAADDR8 -address_a[8] => ram_block1a151.PORTAADDR8 -address_a[8] => ram_block1a152.PORTAADDR8 -address_a[8] => ram_block1a153.PORTAADDR8 -address_a[8] => ram_block1a154.PORTAADDR8 -address_a[8] => ram_block1a155.PORTAADDR8 -address_a[8] => ram_block1a156.PORTAADDR8 -address_a[8] => ram_block1a157.PORTAADDR8 -address_a[8] => ram_block1a158.PORTAADDR8 -address_a[8] => ram_block1a159.PORTAADDR8 -address_a[8] => ram_block1a160.PORTAADDR8 -address_a[8] => ram_block1a161.PORTAADDR8 -address_a[8] => ram_block1a162.PORTAADDR8 -address_a[8] => ram_block1a163.PORTAADDR8 -address_a[8] => ram_block1a164.PORTAADDR8 -address_a[8] => ram_block1a165.PORTAADDR8 -address_a[8] => ram_block1a166.PORTAADDR8 -address_a[8] => ram_block1a167.PORTAADDR8 -address_a[8] => ram_block1a168.PORTAADDR8 -address_a[8] => ram_block1a169.PORTAADDR8 -address_a[8] => ram_block1a170.PORTAADDR8 -address_a[8] => ram_block1a171.PORTAADDR8 -address_a[8] => ram_block1a172.PORTAADDR8 -address_a[8] => ram_block1a173.PORTAADDR8 -address_a[8] => ram_block1a174.PORTAADDR8 -address_a[8] => ram_block1a175.PORTAADDR8 -address_a[8] => ram_block1a176.PORTAADDR8 -address_a[8] => ram_block1a177.PORTAADDR8 -address_a[8] => ram_block1a178.PORTAADDR8 -address_a[8] => ram_block1a179.PORTAADDR8 -address_a[8] => ram_block1a180.PORTAADDR8 -address_a[8] => ram_block1a181.PORTAADDR8 -address_a[8] => ram_block1a182.PORTAADDR8 -address_a[8] => ram_block1a183.PORTAADDR8 -address_a[8] => ram_block1a184.PORTAADDR8 -address_a[8] => ram_block1a185.PORTAADDR8 -address_a[8] => ram_block1a186.PORTAADDR8 -address_a[8] => ram_block1a187.PORTAADDR8 -address_a[8] => ram_block1a188.PORTAADDR8 -address_a[8] => ram_block1a189.PORTAADDR8 -address_a[8] => ram_block1a190.PORTAADDR8 -address_a[8] => ram_block1a191.PORTAADDR8 -address_a[8] => ram_block1a192.PORTAADDR8 -address_a[8] => ram_block1a193.PORTAADDR8 -address_a[8] => ram_block1a194.PORTAADDR8 -address_a[8] => ram_block1a195.PORTAADDR8 -address_a[8] => ram_block1a196.PORTAADDR8 -address_a[8] => ram_block1a197.PORTAADDR8 -address_a[8] => ram_block1a198.PORTAADDR8 -address_a[8] => ram_block1a199.PORTAADDR8 -address_a[8] => ram_block1a200.PORTAADDR8 -address_a[8] => ram_block1a201.PORTAADDR8 -address_a[8] => ram_block1a202.PORTAADDR8 -address_a[8] => ram_block1a203.PORTAADDR8 -address_a[8] => ram_block1a204.PORTAADDR8 -address_a[8] => ram_block1a205.PORTAADDR8 -address_a[8] => ram_block1a206.PORTAADDR8 -address_a[8] => ram_block1a207.PORTAADDR8 -address_a[8] => ram_block1a208.PORTAADDR8 -address_a[8] => ram_block1a209.PORTAADDR8 -address_a[8] => ram_block1a210.PORTAADDR8 -address_a[8] => ram_block1a211.PORTAADDR8 -address_a[8] => ram_block1a212.PORTAADDR8 -address_a[8] => ram_block1a213.PORTAADDR8 -address_a[8] => ram_block1a214.PORTAADDR8 -address_a[8] => ram_block1a215.PORTAADDR8 -address_a[8] => ram_block1a216.PORTAADDR8 -address_a[8] => ram_block1a217.PORTAADDR8 -address_a[8] => ram_block1a218.PORTAADDR8 -address_a[8] => ram_block1a219.PORTAADDR8 -address_a[8] => ram_block1a220.PORTAADDR8 -address_a[8] => ram_block1a221.PORTAADDR8 -address_a[8] => ram_block1a222.PORTAADDR8 -address_a[8] => ram_block1a223.PORTAADDR8 -address_a[9] => ram_block1a0.PORTAADDR9 -address_a[9] => ram_block1a1.PORTAADDR9 -address_a[9] => ram_block1a2.PORTAADDR9 -address_a[9] => ram_block1a3.PORTAADDR9 -address_a[9] => ram_block1a4.PORTAADDR9 -address_a[9] => ram_block1a5.PORTAADDR9 -address_a[9] => ram_block1a6.PORTAADDR9 -address_a[9] => ram_block1a7.PORTAADDR9 -address_a[9] => ram_block1a8.PORTAADDR9 -address_a[9] => ram_block1a9.PORTAADDR9 -address_a[9] => ram_block1a10.PORTAADDR9 -address_a[9] => ram_block1a11.PORTAADDR9 -address_a[9] => ram_block1a12.PORTAADDR9 -address_a[9] => ram_block1a13.PORTAADDR9 -address_a[9] => ram_block1a14.PORTAADDR9 -address_a[9] => ram_block1a15.PORTAADDR9 -address_a[9] => ram_block1a16.PORTAADDR9 -address_a[9] => ram_block1a17.PORTAADDR9 -address_a[9] => ram_block1a18.PORTAADDR9 -address_a[9] => ram_block1a19.PORTAADDR9 -address_a[9] => ram_block1a20.PORTAADDR9 -address_a[9] => ram_block1a21.PORTAADDR9 -address_a[9] => ram_block1a22.PORTAADDR9 -address_a[9] => ram_block1a23.PORTAADDR9 -address_a[9] => ram_block1a24.PORTAADDR9 -address_a[9] => ram_block1a25.PORTAADDR9 -address_a[9] => ram_block1a26.PORTAADDR9 -address_a[9] => ram_block1a27.PORTAADDR9 -address_a[9] => ram_block1a28.PORTAADDR9 -address_a[9] => ram_block1a29.PORTAADDR9 -address_a[9] => ram_block1a30.PORTAADDR9 -address_a[9] => ram_block1a31.PORTAADDR9 -address_a[9] => ram_block1a32.PORTAADDR9 -address_a[9] => ram_block1a33.PORTAADDR9 -address_a[9] => ram_block1a34.PORTAADDR9 -address_a[9] => ram_block1a35.PORTAADDR9 -address_a[9] => ram_block1a36.PORTAADDR9 -address_a[9] => ram_block1a37.PORTAADDR9 -address_a[9] => ram_block1a38.PORTAADDR9 -address_a[9] => ram_block1a39.PORTAADDR9 -address_a[9] => ram_block1a40.PORTAADDR9 -address_a[9] => ram_block1a41.PORTAADDR9 -address_a[9] => ram_block1a42.PORTAADDR9 -address_a[9] => ram_block1a43.PORTAADDR9 -address_a[9] => ram_block1a44.PORTAADDR9 -address_a[9] => ram_block1a45.PORTAADDR9 -address_a[9] => ram_block1a46.PORTAADDR9 -address_a[9] => ram_block1a47.PORTAADDR9 -address_a[9] => ram_block1a48.PORTAADDR9 -address_a[9] => ram_block1a49.PORTAADDR9 -address_a[9] => ram_block1a50.PORTAADDR9 -address_a[9] => ram_block1a51.PORTAADDR9 -address_a[9] => ram_block1a52.PORTAADDR9 -address_a[9] => ram_block1a53.PORTAADDR9 -address_a[9] => ram_block1a54.PORTAADDR9 -address_a[9] => ram_block1a55.PORTAADDR9 -address_a[9] => ram_block1a56.PORTAADDR9 -address_a[9] => ram_block1a57.PORTAADDR9 -address_a[9] => ram_block1a58.PORTAADDR9 -address_a[9] => ram_block1a59.PORTAADDR9 -address_a[9] => ram_block1a60.PORTAADDR9 -address_a[9] => ram_block1a61.PORTAADDR9 -address_a[9] => ram_block1a62.PORTAADDR9 -address_a[9] => ram_block1a63.PORTAADDR9 -address_a[9] => ram_block1a64.PORTAADDR9 -address_a[9] => ram_block1a65.PORTAADDR9 -address_a[9] => ram_block1a66.PORTAADDR9 -address_a[9] => ram_block1a67.PORTAADDR9 -address_a[9] => ram_block1a68.PORTAADDR9 -address_a[9] => ram_block1a69.PORTAADDR9 -address_a[9] => ram_block1a70.PORTAADDR9 -address_a[9] => ram_block1a71.PORTAADDR9 -address_a[9] => ram_block1a72.PORTAADDR9 -address_a[9] => ram_block1a73.PORTAADDR9 -address_a[9] => ram_block1a74.PORTAADDR9 -address_a[9] => ram_block1a75.PORTAADDR9 -address_a[9] => ram_block1a76.PORTAADDR9 -address_a[9] => ram_block1a77.PORTAADDR9 -address_a[9] => ram_block1a78.PORTAADDR9 -address_a[9] => ram_block1a79.PORTAADDR9 -address_a[9] => ram_block1a80.PORTAADDR9 -address_a[9] => ram_block1a81.PORTAADDR9 -address_a[9] => ram_block1a82.PORTAADDR9 -address_a[9] => ram_block1a83.PORTAADDR9 -address_a[9] => ram_block1a84.PORTAADDR9 -address_a[9] => ram_block1a85.PORTAADDR9 -address_a[9] => ram_block1a86.PORTAADDR9 -address_a[9] => ram_block1a87.PORTAADDR9 -address_a[9] => ram_block1a88.PORTAADDR9 -address_a[9] => ram_block1a89.PORTAADDR9 -address_a[9] => ram_block1a90.PORTAADDR9 -address_a[9] => ram_block1a91.PORTAADDR9 -address_a[9] => ram_block1a92.PORTAADDR9 -address_a[9] => ram_block1a93.PORTAADDR9 -address_a[9] => ram_block1a94.PORTAADDR9 -address_a[9] => ram_block1a95.PORTAADDR9 -address_a[9] => ram_block1a96.PORTAADDR9 -address_a[9] => ram_block1a97.PORTAADDR9 -address_a[9] => ram_block1a98.PORTAADDR9 -address_a[9] => ram_block1a99.PORTAADDR9 -address_a[9] => ram_block1a100.PORTAADDR9 -address_a[9] => ram_block1a101.PORTAADDR9 -address_a[9] => ram_block1a102.PORTAADDR9 -address_a[9] => ram_block1a103.PORTAADDR9 -address_a[9] => ram_block1a104.PORTAADDR9 -address_a[9] => ram_block1a105.PORTAADDR9 -address_a[9] => ram_block1a106.PORTAADDR9 -address_a[9] => ram_block1a107.PORTAADDR9 -address_a[9] => ram_block1a108.PORTAADDR9 -address_a[9] => ram_block1a109.PORTAADDR9 -address_a[9] => ram_block1a110.PORTAADDR9 -address_a[9] => ram_block1a111.PORTAADDR9 -address_a[9] => ram_block1a112.PORTAADDR9 -address_a[9] => ram_block1a113.PORTAADDR9 -address_a[9] => ram_block1a114.PORTAADDR9 -address_a[9] => ram_block1a115.PORTAADDR9 -address_a[9] => ram_block1a116.PORTAADDR9 -address_a[9] => ram_block1a117.PORTAADDR9 -address_a[9] => ram_block1a118.PORTAADDR9 -address_a[9] => ram_block1a119.PORTAADDR9 -address_a[9] => ram_block1a120.PORTAADDR9 -address_a[9] => ram_block1a121.PORTAADDR9 -address_a[9] => ram_block1a122.PORTAADDR9 -address_a[9] => ram_block1a123.PORTAADDR9 -address_a[9] => ram_block1a124.PORTAADDR9 -address_a[9] => ram_block1a125.PORTAADDR9 -address_a[9] => ram_block1a126.PORTAADDR9 -address_a[9] => ram_block1a127.PORTAADDR9 -address_a[9] => ram_block1a128.PORTAADDR9 -address_a[9] => ram_block1a129.PORTAADDR9 -address_a[9] => ram_block1a130.PORTAADDR9 -address_a[9] => ram_block1a131.PORTAADDR9 -address_a[9] => ram_block1a132.PORTAADDR9 -address_a[9] => ram_block1a133.PORTAADDR9 -address_a[9] => ram_block1a134.PORTAADDR9 -address_a[9] => ram_block1a135.PORTAADDR9 -address_a[9] => ram_block1a136.PORTAADDR9 -address_a[9] => ram_block1a137.PORTAADDR9 -address_a[9] => ram_block1a138.PORTAADDR9 -address_a[9] => ram_block1a139.PORTAADDR9 -address_a[9] => ram_block1a140.PORTAADDR9 -address_a[9] => ram_block1a141.PORTAADDR9 -address_a[9] => ram_block1a142.PORTAADDR9 -address_a[9] => ram_block1a143.PORTAADDR9 -address_a[9] => ram_block1a144.PORTAADDR9 -address_a[9] => ram_block1a145.PORTAADDR9 -address_a[9] => ram_block1a146.PORTAADDR9 -address_a[9] => ram_block1a147.PORTAADDR9 -address_a[9] => ram_block1a148.PORTAADDR9 -address_a[9] => ram_block1a149.PORTAADDR9 -address_a[9] => ram_block1a150.PORTAADDR9 -address_a[9] => ram_block1a151.PORTAADDR9 -address_a[9] => ram_block1a152.PORTAADDR9 -address_a[9] => ram_block1a153.PORTAADDR9 -address_a[9] => ram_block1a154.PORTAADDR9 -address_a[9] => ram_block1a155.PORTAADDR9 -address_a[9] => ram_block1a156.PORTAADDR9 -address_a[9] => ram_block1a157.PORTAADDR9 -address_a[9] => ram_block1a158.PORTAADDR9 -address_a[9] => ram_block1a159.PORTAADDR9 -address_a[9] => ram_block1a160.PORTAADDR9 -address_a[9] => ram_block1a161.PORTAADDR9 -address_a[9] => ram_block1a162.PORTAADDR9 -address_a[9] => ram_block1a163.PORTAADDR9 -address_a[9] => ram_block1a164.PORTAADDR9 -address_a[9] => ram_block1a165.PORTAADDR9 -address_a[9] => ram_block1a166.PORTAADDR9 -address_a[9] => ram_block1a167.PORTAADDR9 -address_a[9] => ram_block1a168.PORTAADDR9 -address_a[9] => ram_block1a169.PORTAADDR9 -address_a[9] => ram_block1a170.PORTAADDR9 -address_a[9] => ram_block1a171.PORTAADDR9 -address_a[9] => ram_block1a172.PORTAADDR9 -address_a[9] => ram_block1a173.PORTAADDR9 -address_a[9] => ram_block1a174.PORTAADDR9 -address_a[9] => ram_block1a175.PORTAADDR9 -address_a[9] => ram_block1a176.PORTAADDR9 -address_a[9] => ram_block1a177.PORTAADDR9 -address_a[9] => ram_block1a178.PORTAADDR9 -address_a[9] => ram_block1a179.PORTAADDR9 -address_a[9] => ram_block1a180.PORTAADDR9 -address_a[9] => ram_block1a181.PORTAADDR9 -address_a[9] => ram_block1a182.PORTAADDR9 -address_a[9] => ram_block1a183.PORTAADDR9 -address_a[9] => ram_block1a184.PORTAADDR9 -address_a[9] => ram_block1a185.PORTAADDR9 -address_a[9] => ram_block1a186.PORTAADDR9 -address_a[9] => ram_block1a187.PORTAADDR9 -address_a[9] => ram_block1a188.PORTAADDR9 -address_a[9] => ram_block1a189.PORTAADDR9 -address_a[9] => ram_block1a190.PORTAADDR9 -address_a[9] => ram_block1a191.PORTAADDR9 -address_a[9] => ram_block1a192.PORTAADDR9 -address_a[9] => ram_block1a193.PORTAADDR9 -address_a[9] => ram_block1a194.PORTAADDR9 -address_a[9] => ram_block1a195.PORTAADDR9 -address_a[9] => ram_block1a196.PORTAADDR9 -address_a[9] => ram_block1a197.PORTAADDR9 -address_a[9] => ram_block1a198.PORTAADDR9 -address_a[9] => ram_block1a199.PORTAADDR9 -address_a[9] => ram_block1a200.PORTAADDR9 -address_a[9] => ram_block1a201.PORTAADDR9 -address_a[9] => ram_block1a202.PORTAADDR9 -address_a[9] => ram_block1a203.PORTAADDR9 -address_a[9] => ram_block1a204.PORTAADDR9 -address_a[9] => ram_block1a205.PORTAADDR9 -address_a[9] => ram_block1a206.PORTAADDR9 -address_a[9] => ram_block1a207.PORTAADDR9 -address_a[9] => ram_block1a208.PORTAADDR9 -address_a[9] => ram_block1a209.PORTAADDR9 -address_a[9] => ram_block1a210.PORTAADDR9 -address_a[9] => ram_block1a211.PORTAADDR9 -address_a[9] => ram_block1a212.PORTAADDR9 -address_a[9] => ram_block1a213.PORTAADDR9 -address_a[9] => ram_block1a214.PORTAADDR9 -address_a[9] => ram_block1a215.PORTAADDR9 -address_a[9] => ram_block1a216.PORTAADDR9 -address_a[9] => ram_block1a217.PORTAADDR9 -address_a[9] => ram_block1a218.PORTAADDR9 -address_a[9] => ram_block1a219.PORTAADDR9 -address_a[9] => ram_block1a220.PORTAADDR9 -address_a[9] => ram_block1a221.PORTAADDR9 -address_a[9] => ram_block1a222.PORTAADDR9 -address_a[9] => ram_block1a223.PORTAADDR9 -address_a[10] => ram_block1a0.PORTAADDR10 -address_a[10] => ram_block1a1.PORTAADDR10 -address_a[10] => ram_block1a2.PORTAADDR10 -address_a[10] => ram_block1a3.PORTAADDR10 -address_a[10] => ram_block1a4.PORTAADDR10 -address_a[10] => ram_block1a5.PORTAADDR10 -address_a[10] => ram_block1a6.PORTAADDR10 -address_a[10] => ram_block1a7.PORTAADDR10 -address_a[10] => ram_block1a8.PORTAADDR10 -address_a[10] => ram_block1a9.PORTAADDR10 -address_a[10] => ram_block1a10.PORTAADDR10 -address_a[10] => ram_block1a11.PORTAADDR10 -address_a[10] => ram_block1a12.PORTAADDR10 -address_a[10] => ram_block1a13.PORTAADDR10 -address_a[10] => ram_block1a14.PORTAADDR10 -address_a[10] => ram_block1a15.PORTAADDR10 -address_a[10] => ram_block1a16.PORTAADDR10 -address_a[10] => ram_block1a17.PORTAADDR10 -address_a[10] => ram_block1a18.PORTAADDR10 -address_a[10] => ram_block1a19.PORTAADDR10 -address_a[10] => ram_block1a20.PORTAADDR10 -address_a[10] => ram_block1a21.PORTAADDR10 -address_a[10] => ram_block1a22.PORTAADDR10 -address_a[10] => ram_block1a23.PORTAADDR10 -address_a[10] => ram_block1a24.PORTAADDR10 -address_a[10] => ram_block1a25.PORTAADDR10 -address_a[10] => ram_block1a26.PORTAADDR10 -address_a[10] => ram_block1a27.PORTAADDR10 -address_a[10] => ram_block1a28.PORTAADDR10 -address_a[10] => ram_block1a29.PORTAADDR10 -address_a[10] => ram_block1a30.PORTAADDR10 -address_a[10] => ram_block1a31.PORTAADDR10 -address_a[10] => ram_block1a32.PORTAADDR10 -address_a[10] => ram_block1a33.PORTAADDR10 -address_a[10] => ram_block1a34.PORTAADDR10 -address_a[10] => ram_block1a35.PORTAADDR10 -address_a[10] => ram_block1a36.PORTAADDR10 -address_a[10] => ram_block1a37.PORTAADDR10 -address_a[10] => ram_block1a38.PORTAADDR10 -address_a[10] => ram_block1a39.PORTAADDR10 -address_a[10] => ram_block1a40.PORTAADDR10 -address_a[10] => ram_block1a41.PORTAADDR10 -address_a[10] => ram_block1a42.PORTAADDR10 -address_a[10] => ram_block1a43.PORTAADDR10 -address_a[10] => ram_block1a44.PORTAADDR10 -address_a[10] => ram_block1a45.PORTAADDR10 -address_a[10] => ram_block1a46.PORTAADDR10 -address_a[10] => ram_block1a47.PORTAADDR10 -address_a[10] => ram_block1a48.PORTAADDR10 -address_a[10] => ram_block1a49.PORTAADDR10 -address_a[10] => ram_block1a50.PORTAADDR10 -address_a[10] => ram_block1a51.PORTAADDR10 -address_a[10] => ram_block1a52.PORTAADDR10 -address_a[10] => ram_block1a53.PORTAADDR10 -address_a[10] => ram_block1a54.PORTAADDR10 -address_a[10] => ram_block1a55.PORTAADDR10 -address_a[10] => ram_block1a56.PORTAADDR10 -address_a[10] => ram_block1a57.PORTAADDR10 -address_a[10] => ram_block1a58.PORTAADDR10 -address_a[10] => ram_block1a59.PORTAADDR10 -address_a[10] => ram_block1a60.PORTAADDR10 -address_a[10] => ram_block1a61.PORTAADDR10 -address_a[10] => ram_block1a62.PORTAADDR10 -address_a[10] => ram_block1a63.PORTAADDR10 -address_a[10] => ram_block1a64.PORTAADDR10 -address_a[10] => ram_block1a65.PORTAADDR10 -address_a[10] => ram_block1a66.PORTAADDR10 -address_a[10] => ram_block1a67.PORTAADDR10 -address_a[10] => ram_block1a68.PORTAADDR10 -address_a[10] => ram_block1a69.PORTAADDR10 -address_a[10] => ram_block1a70.PORTAADDR10 -address_a[10] => ram_block1a71.PORTAADDR10 -address_a[10] => ram_block1a72.PORTAADDR10 -address_a[10] => ram_block1a73.PORTAADDR10 -address_a[10] => ram_block1a74.PORTAADDR10 -address_a[10] => ram_block1a75.PORTAADDR10 -address_a[10] => ram_block1a76.PORTAADDR10 -address_a[10] => ram_block1a77.PORTAADDR10 -address_a[10] => ram_block1a78.PORTAADDR10 -address_a[10] => ram_block1a79.PORTAADDR10 -address_a[10] => ram_block1a80.PORTAADDR10 -address_a[10] => ram_block1a81.PORTAADDR10 -address_a[10] => ram_block1a82.PORTAADDR10 -address_a[10] => ram_block1a83.PORTAADDR10 -address_a[10] => ram_block1a84.PORTAADDR10 -address_a[10] => ram_block1a85.PORTAADDR10 -address_a[10] => ram_block1a86.PORTAADDR10 -address_a[10] => ram_block1a87.PORTAADDR10 -address_a[10] => ram_block1a88.PORTAADDR10 -address_a[10] => ram_block1a89.PORTAADDR10 -address_a[10] => ram_block1a90.PORTAADDR10 -address_a[10] => ram_block1a91.PORTAADDR10 -address_a[10] => ram_block1a92.PORTAADDR10 -address_a[10] => ram_block1a93.PORTAADDR10 -address_a[10] => ram_block1a94.PORTAADDR10 -address_a[10] => ram_block1a95.PORTAADDR10 -address_a[10] => ram_block1a96.PORTAADDR10 -address_a[10] => ram_block1a97.PORTAADDR10 -address_a[10] => ram_block1a98.PORTAADDR10 -address_a[10] => ram_block1a99.PORTAADDR10 -address_a[10] => ram_block1a100.PORTAADDR10 -address_a[10] => ram_block1a101.PORTAADDR10 -address_a[10] => ram_block1a102.PORTAADDR10 -address_a[10] => ram_block1a103.PORTAADDR10 -address_a[10] => ram_block1a104.PORTAADDR10 -address_a[10] => ram_block1a105.PORTAADDR10 -address_a[10] => ram_block1a106.PORTAADDR10 -address_a[10] => ram_block1a107.PORTAADDR10 -address_a[10] => ram_block1a108.PORTAADDR10 -address_a[10] => ram_block1a109.PORTAADDR10 -address_a[10] => ram_block1a110.PORTAADDR10 -address_a[10] => ram_block1a111.PORTAADDR10 -address_a[10] => ram_block1a112.PORTAADDR10 -address_a[10] => ram_block1a113.PORTAADDR10 -address_a[10] => ram_block1a114.PORTAADDR10 -address_a[10] => ram_block1a115.PORTAADDR10 -address_a[10] => ram_block1a116.PORTAADDR10 -address_a[10] => ram_block1a117.PORTAADDR10 -address_a[10] => ram_block1a118.PORTAADDR10 -address_a[10] => ram_block1a119.PORTAADDR10 -address_a[10] => ram_block1a120.PORTAADDR10 -address_a[10] => ram_block1a121.PORTAADDR10 -address_a[10] => ram_block1a122.PORTAADDR10 -address_a[10] => ram_block1a123.PORTAADDR10 -address_a[10] => ram_block1a124.PORTAADDR10 -address_a[10] => ram_block1a125.PORTAADDR10 -address_a[10] => ram_block1a126.PORTAADDR10 -address_a[10] => ram_block1a127.PORTAADDR10 -address_a[10] => ram_block1a128.PORTAADDR10 -address_a[10] => ram_block1a129.PORTAADDR10 -address_a[10] => ram_block1a130.PORTAADDR10 -address_a[10] => ram_block1a131.PORTAADDR10 -address_a[10] => ram_block1a132.PORTAADDR10 -address_a[10] => ram_block1a133.PORTAADDR10 -address_a[10] => ram_block1a134.PORTAADDR10 -address_a[10] => ram_block1a135.PORTAADDR10 -address_a[10] => ram_block1a136.PORTAADDR10 -address_a[10] => ram_block1a137.PORTAADDR10 -address_a[10] => ram_block1a138.PORTAADDR10 -address_a[10] => ram_block1a139.PORTAADDR10 -address_a[10] => ram_block1a140.PORTAADDR10 -address_a[10] => ram_block1a141.PORTAADDR10 -address_a[10] => ram_block1a142.PORTAADDR10 -address_a[10] => ram_block1a143.PORTAADDR10 -address_a[10] => ram_block1a144.PORTAADDR10 -address_a[10] => ram_block1a145.PORTAADDR10 -address_a[10] => ram_block1a146.PORTAADDR10 -address_a[10] => ram_block1a147.PORTAADDR10 -address_a[10] => ram_block1a148.PORTAADDR10 -address_a[10] => ram_block1a149.PORTAADDR10 -address_a[10] => ram_block1a150.PORTAADDR10 -address_a[10] => ram_block1a151.PORTAADDR10 -address_a[10] => ram_block1a152.PORTAADDR10 -address_a[10] => ram_block1a153.PORTAADDR10 -address_a[10] => ram_block1a154.PORTAADDR10 -address_a[10] => ram_block1a155.PORTAADDR10 -address_a[10] => ram_block1a156.PORTAADDR10 -address_a[10] => ram_block1a157.PORTAADDR10 -address_a[10] => ram_block1a158.PORTAADDR10 -address_a[10] => ram_block1a159.PORTAADDR10 -address_a[10] => ram_block1a160.PORTAADDR10 -address_a[10] => ram_block1a161.PORTAADDR10 -address_a[10] => ram_block1a162.PORTAADDR10 -address_a[10] => ram_block1a163.PORTAADDR10 -address_a[10] => ram_block1a164.PORTAADDR10 -address_a[10] => ram_block1a165.PORTAADDR10 -address_a[10] => ram_block1a166.PORTAADDR10 -address_a[10] => ram_block1a167.PORTAADDR10 -address_a[10] => ram_block1a168.PORTAADDR10 -address_a[10] => ram_block1a169.PORTAADDR10 -address_a[10] => ram_block1a170.PORTAADDR10 -address_a[10] => ram_block1a171.PORTAADDR10 -address_a[10] => ram_block1a172.PORTAADDR10 -address_a[10] => ram_block1a173.PORTAADDR10 -address_a[10] => ram_block1a174.PORTAADDR10 -address_a[10] => ram_block1a175.PORTAADDR10 -address_a[10] => ram_block1a176.PORTAADDR10 -address_a[10] => ram_block1a177.PORTAADDR10 -address_a[10] => ram_block1a178.PORTAADDR10 -address_a[10] => ram_block1a179.PORTAADDR10 -address_a[10] => ram_block1a180.PORTAADDR10 -address_a[10] => ram_block1a181.PORTAADDR10 -address_a[10] => ram_block1a182.PORTAADDR10 -address_a[10] => ram_block1a183.PORTAADDR10 -address_a[10] => ram_block1a184.PORTAADDR10 -address_a[10] => ram_block1a185.PORTAADDR10 -address_a[10] => ram_block1a186.PORTAADDR10 -address_a[10] => ram_block1a187.PORTAADDR10 -address_a[10] => ram_block1a188.PORTAADDR10 -address_a[10] => ram_block1a189.PORTAADDR10 -address_a[10] => ram_block1a190.PORTAADDR10 -address_a[10] => ram_block1a191.PORTAADDR10 -address_a[10] => ram_block1a192.PORTAADDR10 -address_a[10] => ram_block1a193.PORTAADDR10 -address_a[10] => ram_block1a194.PORTAADDR10 -address_a[10] => ram_block1a195.PORTAADDR10 -address_a[10] => ram_block1a196.PORTAADDR10 -address_a[10] => ram_block1a197.PORTAADDR10 -address_a[10] => ram_block1a198.PORTAADDR10 -address_a[10] => ram_block1a199.PORTAADDR10 -address_a[10] => ram_block1a200.PORTAADDR10 -address_a[10] => ram_block1a201.PORTAADDR10 -address_a[10] => ram_block1a202.PORTAADDR10 -address_a[10] => ram_block1a203.PORTAADDR10 -address_a[10] => ram_block1a204.PORTAADDR10 -address_a[10] => ram_block1a205.PORTAADDR10 -address_a[10] => ram_block1a206.PORTAADDR10 -address_a[10] => ram_block1a207.PORTAADDR10 -address_a[10] => ram_block1a208.PORTAADDR10 -address_a[10] => ram_block1a209.PORTAADDR10 -address_a[10] => ram_block1a210.PORTAADDR10 -address_a[10] => ram_block1a211.PORTAADDR10 -address_a[10] => ram_block1a212.PORTAADDR10 -address_a[10] => ram_block1a213.PORTAADDR10 -address_a[10] => ram_block1a214.PORTAADDR10 -address_a[10] => ram_block1a215.PORTAADDR10 -address_a[10] => ram_block1a216.PORTAADDR10 -address_a[10] => ram_block1a217.PORTAADDR10 -address_a[10] => ram_block1a218.PORTAADDR10 -address_a[10] => ram_block1a219.PORTAADDR10 -address_a[10] => ram_block1a220.PORTAADDR10 -address_a[10] => ram_block1a221.PORTAADDR10 -address_a[10] => ram_block1a222.PORTAADDR10 -address_a[10] => ram_block1a223.PORTAADDR10 -address_a[11] => ram_block1a0.PORTAADDR11 -address_a[11] => ram_block1a1.PORTAADDR11 -address_a[11] => ram_block1a2.PORTAADDR11 -address_a[11] => ram_block1a3.PORTAADDR11 -address_a[11] => ram_block1a4.PORTAADDR11 -address_a[11] => ram_block1a5.PORTAADDR11 -address_a[11] => ram_block1a6.PORTAADDR11 -address_a[11] => ram_block1a7.PORTAADDR11 -address_a[11] => ram_block1a8.PORTAADDR11 -address_a[11] => ram_block1a9.PORTAADDR11 -address_a[11] => ram_block1a10.PORTAADDR11 -address_a[11] => ram_block1a11.PORTAADDR11 -address_a[11] => ram_block1a12.PORTAADDR11 -address_a[11] => ram_block1a13.PORTAADDR11 -address_a[11] => ram_block1a14.PORTAADDR11 -address_a[11] => ram_block1a15.PORTAADDR11 -address_a[11] => ram_block1a16.PORTAADDR11 -address_a[11] => ram_block1a17.PORTAADDR11 -address_a[11] => ram_block1a18.PORTAADDR11 -address_a[11] => ram_block1a19.PORTAADDR11 -address_a[11] => ram_block1a20.PORTAADDR11 -address_a[11] => ram_block1a21.PORTAADDR11 -address_a[11] => ram_block1a22.PORTAADDR11 -address_a[11] => ram_block1a23.PORTAADDR11 -address_a[11] => ram_block1a24.PORTAADDR11 -address_a[11] => ram_block1a25.PORTAADDR11 -address_a[11] => ram_block1a26.PORTAADDR11 -address_a[11] => ram_block1a27.PORTAADDR11 -address_a[11] => ram_block1a28.PORTAADDR11 -address_a[11] => ram_block1a29.PORTAADDR11 -address_a[11] => ram_block1a30.PORTAADDR11 -address_a[11] => ram_block1a31.PORTAADDR11 -address_a[11] => ram_block1a32.PORTAADDR11 -address_a[11] => ram_block1a33.PORTAADDR11 -address_a[11] => ram_block1a34.PORTAADDR11 -address_a[11] => ram_block1a35.PORTAADDR11 -address_a[11] => ram_block1a36.PORTAADDR11 -address_a[11] => ram_block1a37.PORTAADDR11 -address_a[11] => ram_block1a38.PORTAADDR11 -address_a[11] => ram_block1a39.PORTAADDR11 -address_a[11] => ram_block1a40.PORTAADDR11 -address_a[11] => ram_block1a41.PORTAADDR11 -address_a[11] => ram_block1a42.PORTAADDR11 -address_a[11] => ram_block1a43.PORTAADDR11 -address_a[11] => ram_block1a44.PORTAADDR11 -address_a[11] => ram_block1a45.PORTAADDR11 -address_a[11] => ram_block1a46.PORTAADDR11 -address_a[11] => ram_block1a47.PORTAADDR11 -address_a[11] => ram_block1a48.PORTAADDR11 -address_a[11] => ram_block1a49.PORTAADDR11 -address_a[11] => ram_block1a50.PORTAADDR11 -address_a[11] => ram_block1a51.PORTAADDR11 -address_a[11] => ram_block1a52.PORTAADDR11 -address_a[11] => ram_block1a53.PORTAADDR11 -address_a[11] => ram_block1a54.PORTAADDR11 -address_a[11] => ram_block1a55.PORTAADDR11 -address_a[11] => ram_block1a56.PORTAADDR11 -address_a[11] => ram_block1a57.PORTAADDR11 -address_a[11] => ram_block1a58.PORTAADDR11 -address_a[11] => ram_block1a59.PORTAADDR11 -address_a[11] => ram_block1a60.PORTAADDR11 -address_a[11] => ram_block1a61.PORTAADDR11 -address_a[11] => ram_block1a62.PORTAADDR11 -address_a[11] => ram_block1a63.PORTAADDR11 -address_a[11] => ram_block1a64.PORTAADDR11 -address_a[11] => ram_block1a65.PORTAADDR11 -address_a[11] => ram_block1a66.PORTAADDR11 -address_a[11] => ram_block1a67.PORTAADDR11 -address_a[11] => ram_block1a68.PORTAADDR11 -address_a[11] => ram_block1a69.PORTAADDR11 -address_a[11] => ram_block1a70.PORTAADDR11 -address_a[11] => ram_block1a71.PORTAADDR11 -address_a[11] => ram_block1a72.PORTAADDR11 -address_a[11] => ram_block1a73.PORTAADDR11 -address_a[11] => ram_block1a74.PORTAADDR11 -address_a[11] => ram_block1a75.PORTAADDR11 -address_a[11] => ram_block1a76.PORTAADDR11 -address_a[11] => ram_block1a77.PORTAADDR11 -address_a[11] => ram_block1a78.PORTAADDR11 -address_a[11] => ram_block1a79.PORTAADDR11 -address_a[11] => ram_block1a80.PORTAADDR11 -address_a[11] => ram_block1a81.PORTAADDR11 -address_a[11] => ram_block1a82.PORTAADDR11 -address_a[11] => ram_block1a83.PORTAADDR11 -address_a[11] => ram_block1a84.PORTAADDR11 -address_a[11] => ram_block1a85.PORTAADDR11 -address_a[11] => ram_block1a86.PORTAADDR11 -address_a[11] => ram_block1a87.PORTAADDR11 -address_a[11] => ram_block1a88.PORTAADDR11 -address_a[11] => ram_block1a89.PORTAADDR11 -address_a[11] => ram_block1a90.PORTAADDR11 -address_a[11] => ram_block1a91.PORTAADDR11 -address_a[11] => ram_block1a92.PORTAADDR11 -address_a[11] => ram_block1a93.PORTAADDR11 -address_a[11] => ram_block1a94.PORTAADDR11 -address_a[11] => ram_block1a95.PORTAADDR11 -address_a[11] => ram_block1a96.PORTAADDR11 -address_a[11] => ram_block1a97.PORTAADDR11 -address_a[11] => ram_block1a98.PORTAADDR11 -address_a[11] => ram_block1a99.PORTAADDR11 -address_a[11] => ram_block1a100.PORTAADDR11 -address_a[11] => ram_block1a101.PORTAADDR11 -address_a[11] => ram_block1a102.PORTAADDR11 -address_a[11] => ram_block1a103.PORTAADDR11 -address_a[11] => ram_block1a104.PORTAADDR11 -address_a[11] => ram_block1a105.PORTAADDR11 -address_a[11] => ram_block1a106.PORTAADDR11 -address_a[11] => ram_block1a107.PORTAADDR11 -address_a[11] => ram_block1a108.PORTAADDR11 -address_a[11] => ram_block1a109.PORTAADDR11 -address_a[11] => ram_block1a110.PORTAADDR11 -address_a[11] => ram_block1a111.PORTAADDR11 -address_a[11] => ram_block1a112.PORTAADDR11 -address_a[11] => ram_block1a113.PORTAADDR11 -address_a[11] => ram_block1a114.PORTAADDR11 -address_a[11] => ram_block1a115.PORTAADDR11 -address_a[11] => ram_block1a116.PORTAADDR11 -address_a[11] => ram_block1a117.PORTAADDR11 -address_a[11] => ram_block1a118.PORTAADDR11 -address_a[11] => ram_block1a119.PORTAADDR11 -address_a[11] => ram_block1a120.PORTAADDR11 -address_a[11] => ram_block1a121.PORTAADDR11 -address_a[11] => ram_block1a122.PORTAADDR11 -address_a[11] => ram_block1a123.PORTAADDR11 -address_a[11] => ram_block1a124.PORTAADDR11 -address_a[11] => ram_block1a125.PORTAADDR11 -address_a[11] => ram_block1a126.PORTAADDR11 -address_a[11] => ram_block1a127.PORTAADDR11 -address_a[11] => ram_block1a128.PORTAADDR11 -address_a[11] => ram_block1a129.PORTAADDR11 -address_a[11] => ram_block1a130.PORTAADDR11 -address_a[11] => ram_block1a131.PORTAADDR11 -address_a[11] => ram_block1a132.PORTAADDR11 -address_a[11] => ram_block1a133.PORTAADDR11 -address_a[11] => ram_block1a134.PORTAADDR11 -address_a[11] => ram_block1a135.PORTAADDR11 -address_a[11] => ram_block1a136.PORTAADDR11 -address_a[11] => ram_block1a137.PORTAADDR11 -address_a[11] => ram_block1a138.PORTAADDR11 -address_a[11] => ram_block1a139.PORTAADDR11 -address_a[11] => ram_block1a140.PORTAADDR11 -address_a[11] => ram_block1a141.PORTAADDR11 -address_a[11] => ram_block1a142.PORTAADDR11 -address_a[11] => ram_block1a143.PORTAADDR11 -address_a[11] => ram_block1a144.PORTAADDR11 -address_a[11] => ram_block1a145.PORTAADDR11 -address_a[11] => ram_block1a146.PORTAADDR11 -address_a[11] => ram_block1a147.PORTAADDR11 -address_a[11] => ram_block1a148.PORTAADDR11 -address_a[11] => ram_block1a149.PORTAADDR11 -address_a[11] => ram_block1a150.PORTAADDR11 -address_a[11] => ram_block1a151.PORTAADDR11 -address_a[11] => ram_block1a152.PORTAADDR11 -address_a[11] => ram_block1a153.PORTAADDR11 -address_a[11] => ram_block1a154.PORTAADDR11 -address_a[11] => ram_block1a155.PORTAADDR11 -address_a[11] => ram_block1a156.PORTAADDR11 -address_a[11] => ram_block1a157.PORTAADDR11 -address_a[11] => ram_block1a158.PORTAADDR11 -address_a[11] => ram_block1a159.PORTAADDR11 -address_a[11] => ram_block1a160.PORTAADDR11 -address_a[11] => ram_block1a161.PORTAADDR11 -address_a[11] => ram_block1a162.PORTAADDR11 -address_a[11] => ram_block1a163.PORTAADDR11 -address_a[11] => ram_block1a164.PORTAADDR11 -address_a[11] => ram_block1a165.PORTAADDR11 -address_a[11] => ram_block1a166.PORTAADDR11 -address_a[11] => ram_block1a167.PORTAADDR11 -address_a[11] => ram_block1a168.PORTAADDR11 -address_a[11] => ram_block1a169.PORTAADDR11 -address_a[11] => ram_block1a170.PORTAADDR11 -address_a[11] => ram_block1a171.PORTAADDR11 -address_a[11] => ram_block1a172.PORTAADDR11 -address_a[11] => ram_block1a173.PORTAADDR11 -address_a[11] => ram_block1a174.PORTAADDR11 -address_a[11] => ram_block1a175.PORTAADDR11 -address_a[11] => ram_block1a176.PORTAADDR11 -address_a[11] => ram_block1a177.PORTAADDR11 -address_a[11] => ram_block1a178.PORTAADDR11 -address_a[11] => ram_block1a179.PORTAADDR11 -address_a[11] => ram_block1a180.PORTAADDR11 -address_a[11] => ram_block1a181.PORTAADDR11 -address_a[11] => ram_block1a182.PORTAADDR11 -address_a[11] => ram_block1a183.PORTAADDR11 -address_a[11] => ram_block1a184.PORTAADDR11 -address_a[11] => ram_block1a185.PORTAADDR11 -address_a[11] => ram_block1a186.PORTAADDR11 -address_a[11] => ram_block1a187.PORTAADDR11 -address_a[11] => ram_block1a188.PORTAADDR11 -address_a[11] => ram_block1a189.PORTAADDR11 -address_a[11] => ram_block1a190.PORTAADDR11 -address_a[11] => ram_block1a191.PORTAADDR11 -address_a[12] => ram_block1a0.PORTAADDR12 -address_a[12] => ram_block1a1.PORTAADDR12 -address_a[12] => ram_block1a2.PORTAADDR12 -address_a[12] => ram_block1a3.PORTAADDR12 -address_a[12] => ram_block1a4.PORTAADDR12 -address_a[12] => ram_block1a5.PORTAADDR12 -address_a[12] => ram_block1a6.PORTAADDR12 -address_a[12] => ram_block1a7.PORTAADDR12 -address_a[12] => ram_block1a8.PORTAADDR12 -address_a[12] => ram_block1a9.PORTAADDR12 -address_a[12] => ram_block1a10.PORTAADDR12 -address_a[12] => ram_block1a11.PORTAADDR12 -address_a[12] => ram_block1a12.PORTAADDR12 -address_a[12] => ram_block1a13.PORTAADDR12 -address_a[12] => ram_block1a14.PORTAADDR12 -address_a[12] => ram_block1a15.PORTAADDR12 -address_a[12] => ram_block1a16.PORTAADDR12 -address_a[12] => ram_block1a17.PORTAADDR12 -address_a[12] => ram_block1a18.PORTAADDR12 -address_a[12] => ram_block1a19.PORTAADDR12 -address_a[12] => ram_block1a20.PORTAADDR12 -address_a[12] => ram_block1a21.PORTAADDR12 -address_a[12] => ram_block1a22.PORTAADDR12 -address_a[12] => ram_block1a23.PORTAADDR12 -address_a[12] => ram_block1a24.PORTAADDR12 -address_a[12] => ram_block1a25.PORTAADDR12 -address_a[12] => ram_block1a26.PORTAADDR12 -address_a[12] => ram_block1a27.PORTAADDR12 -address_a[12] => ram_block1a28.PORTAADDR12 -address_a[12] => ram_block1a29.PORTAADDR12 -address_a[12] => ram_block1a30.PORTAADDR12 -address_a[12] => ram_block1a31.PORTAADDR12 -address_a[12] => ram_block1a32.PORTAADDR12 -address_a[12] => ram_block1a33.PORTAADDR12 -address_a[12] => ram_block1a34.PORTAADDR12 -address_a[12] => ram_block1a35.PORTAADDR12 -address_a[12] => ram_block1a36.PORTAADDR12 -address_a[12] => ram_block1a37.PORTAADDR12 -address_a[12] => ram_block1a38.PORTAADDR12 -address_a[12] => ram_block1a39.PORTAADDR12 -address_a[12] => ram_block1a40.PORTAADDR12 -address_a[12] => ram_block1a41.PORTAADDR12 -address_a[12] => ram_block1a42.PORTAADDR12 -address_a[12] => ram_block1a43.PORTAADDR12 -address_a[12] => ram_block1a44.PORTAADDR12 -address_a[12] => ram_block1a45.PORTAADDR12 -address_a[12] => ram_block1a46.PORTAADDR12 -address_a[12] => ram_block1a47.PORTAADDR12 -address_a[12] => ram_block1a48.PORTAADDR12 -address_a[12] => ram_block1a49.PORTAADDR12 -address_a[12] => ram_block1a50.PORTAADDR12 -address_a[12] => ram_block1a51.PORTAADDR12 -address_a[12] => ram_block1a52.PORTAADDR12 -address_a[12] => ram_block1a53.PORTAADDR12 -address_a[12] => ram_block1a54.PORTAADDR12 -address_a[12] => ram_block1a55.PORTAADDR12 -address_a[12] => ram_block1a56.PORTAADDR12 -address_a[12] => ram_block1a57.PORTAADDR12 -address_a[12] => ram_block1a58.PORTAADDR12 -address_a[12] => ram_block1a59.PORTAADDR12 -address_a[12] => ram_block1a60.PORTAADDR12 -address_a[12] => ram_block1a61.PORTAADDR12 -address_a[12] => ram_block1a62.PORTAADDR12 -address_a[12] => ram_block1a63.PORTAADDR12 -address_a[12] => ram_block1a64.PORTAADDR12 -address_a[12] => ram_block1a65.PORTAADDR12 -address_a[12] => ram_block1a66.PORTAADDR12 -address_a[12] => ram_block1a67.PORTAADDR12 -address_a[12] => ram_block1a68.PORTAADDR12 -address_a[12] => ram_block1a69.PORTAADDR12 -address_a[12] => ram_block1a70.PORTAADDR12 -address_a[12] => ram_block1a71.PORTAADDR12 -address_a[12] => ram_block1a72.PORTAADDR12 -address_a[12] => ram_block1a73.PORTAADDR12 -address_a[12] => ram_block1a74.PORTAADDR12 -address_a[12] => ram_block1a75.PORTAADDR12 -address_a[12] => ram_block1a76.PORTAADDR12 -address_a[12] => ram_block1a77.PORTAADDR12 -address_a[12] => ram_block1a78.PORTAADDR12 -address_a[12] => ram_block1a79.PORTAADDR12 -address_a[12] => ram_block1a80.PORTAADDR12 -address_a[12] => ram_block1a81.PORTAADDR12 -address_a[12] => ram_block1a82.PORTAADDR12 -address_a[12] => ram_block1a83.PORTAADDR12 -address_a[12] => ram_block1a84.PORTAADDR12 -address_a[12] => ram_block1a85.PORTAADDR12 -address_a[12] => ram_block1a86.PORTAADDR12 -address_a[12] => ram_block1a87.PORTAADDR12 -address_a[12] => ram_block1a88.PORTAADDR12 -address_a[12] => ram_block1a89.PORTAADDR12 -address_a[12] => ram_block1a90.PORTAADDR12 -address_a[12] => ram_block1a91.PORTAADDR12 -address_a[12] => ram_block1a92.PORTAADDR12 -address_a[12] => ram_block1a93.PORTAADDR12 -address_a[12] => ram_block1a94.PORTAADDR12 -address_a[12] => ram_block1a95.PORTAADDR12 -address_a[12] => ram_block1a96.PORTAADDR12 -address_a[12] => ram_block1a97.PORTAADDR12 -address_a[12] => ram_block1a98.PORTAADDR12 -address_a[12] => ram_block1a99.PORTAADDR12 -address_a[12] => ram_block1a100.PORTAADDR12 -address_a[12] => ram_block1a101.PORTAADDR12 -address_a[12] => ram_block1a102.PORTAADDR12 -address_a[12] => ram_block1a103.PORTAADDR12 -address_a[12] => ram_block1a104.PORTAADDR12 -address_a[12] => ram_block1a105.PORTAADDR12 -address_a[12] => ram_block1a106.PORTAADDR12 -address_a[12] => ram_block1a107.PORTAADDR12 -address_a[12] => ram_block1a108.PORTAADDR12 -address_a[12] => ram_block1a109.PORTAADDR12 -address_a[12] => ram_block1a110.PORTAADDR12 -address_a[12] => ram_block1a111.PORTAADDR12 -address_a[12] => ram_block1a112.PORTAADDR12 -address_a[12] => ram_block1a113.PORTAADDR12 -address_a[12] => ram_block1a114.PORTAADDR12 -address_a[12] => ram_block1a115.PORTAADDR12 -address_a[12] => ram_block1a116.PORTAADDR12 -address_a[12] => ram_block1a117.PORTAADDR12 -address_a[12] => ram_block1a118.PORTAADDR12 -address_a[12] => ram_block1a119.PORTAADDR12 -address_a[12] => ram_block1a120.PORTAADDR12 -address_a[12] => ram_block1a121.PORTAADDR12 -address_a[12] => ram_block1a122.PORTAADDR12 -address_a[12] => ram_block1a123.PORTAADDR12 -address_a[12] => ram_block1a124.PORTAADDR12 -address_a[12] => ram_block1a125.PORTAADDR12 -address_a[12] => ram_block1a126.PORTAADDR12 -address_a[12] => ram_block1a127.PORTAADDR12 -address_a[12] => ram_block1a128.PORTAADDR12 -address_a[12] => ram_block1a129.PORTAADDR12 -address_a[12] => ram_block1a130.PORTAADDR12 -address_a[12] => ram_block1a131.PORTAADDR12 -address_a[12] => ram_block1a132.PORTAADDR12 -address_a[12] => ram_block1a133.PORTAADDR12 -address_a[12] => ram_block1a134.PORTAADDR12 -address_a[12] => ram_block1a135.PORTAADDR12 -address_a[12] => ram_block1a136.PORTAADDR12 -address_a[12] => ram_block1a137.PORTAADDR12 -address_a[12] => ram_block1a138.PORTAADDR12 -address_a[12] => ram_block1a139.PORTAADDR12 -address_a[12] => ram_block1a140.PORTAADDR12 -address_a[12] => ram_block1a141.PORTAADDR12 -address_a[12] => ram_block1a142.PORTAADDR12 -address_a[12] => ram_block1a143.PORTAADDR12 -address_a[12] => ram_block1a144.PORTAADDR12 -address_a[12] => ram_block1a145.PORTAADDR12 -address_a[12] => ram_block1a146.PORTAADDR12 -address_a[12] => ram_block1a147.PORTAADDR12 -address_a[12] => ram_block1a148.PORTAADDR12 -address_a[12] => ram_block1a149.PORTAADDR12 -address_a[12] => ram_block1a150.PORTAADDR12 -address_a[12] => ram_block1a151.PORTAADDR12 -address_a[12] => ram_block1a152.PORTAADDR12 -address_a[12] => ram_block1a153.PORTAADDR12 -address_a[12] => ram_block1a154.PORTAADDR12 -address_a[12] => ram_block1a155.PORTAADDR12 -address_a[12] => ram_block1a156.PORTAADDR12 -address_a[12] => ram_block1a157.PORTAADDR12 -address_a[12] => ram_block1a158.PORTAADDR12 -address_a[12] => ram_block1a159.PORTAADDR12 -address_a[12] => ram_block1a160.PORTAADDR12 -address_a[12] => ram_block1a161.PORTAADDR12 -address_a[12] => ram_block1a162.PORTAADDR12 -address_a[12] => ram_block1a163.PORTAADDR12 -address_a[12] => ram_block1a164.PORTAADDR12 -address_a[12] => ram_block1a165.PORTAADDR12 -address_a[12] => ram_block1a166.PORTAADDR12 -address_a[12] => ram_block1a167.PORTAADDR12 -address_a[12] => ram_block1a168.PORTAADDR12 -address_a[12] => ram_block1a169.PORTAADDR12 -address_a[12] => ram_block1a170.PORTAADDR12 -address_a[12] => ram_block1a171.PORTAADDR12 -address_a[12] => ram_block1a172.PORTAADDR12 -address_a[12] => ram_block1a173.PORTAADDR12 -address_a[12] => ram_block1a174.PORTAADDR12 -address_a[12] => ram_block1a175.PORTAADDR12 -address_a[12] => ram_block1a176.PORTAADDR12 -address_a[12] => ram_block1a177.PORTAADDR12 -address_a[12] => ram_block1a178.PORTAADDR12 -address_a[12] => ram_block1a179.PORTAADDR12 -address_a[12] => ram_block1a180.PORTAADDR12 -address_a[12] => ram_block1a181.PORTAADDR12 -address_a[12] => ram_block1a182.PORTAADDR12 -address_a[12] => ram_block1a183.PORTAADDR12 -address_a[12] => ram_block1a184.PORTAADDR12 -address_a[12] => ram_block1a185.PORTAADDR12 -address_a[12] => ram_block1a186.PORTAADDR12 -address_a[12] => ram_block1a187.PORTAADDR12 -address_a[12] => ram_block1a188.PORTAADDR12 -address_a[12] => ram_block1a189.PORTAADDR12 -address_a[12] => ram_block1a190.PORTAADDR12 -address_a[12] => ram_block1a191.PORTAADDR12 -address_a[13] => address_reg_a[0].DATAIN -address_a[13] => decode_qsa:decode3.data[0] -address_a[14] => address_reg_a[1].DATAIN -address_a[14] => decode_qsa:decode3.data[1] -address_a[15] => address_reg_a[2].DATAIN -address_a[15] => decode_qsa:decode3.data[2] -byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a32.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a33.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a34.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a35.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a36.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a37.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a38.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a39.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a64.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a65.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a66.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a67.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a68.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a69.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a70.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a71.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a96.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a97.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a98.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a99.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a100.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a101.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a102.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a103.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a128.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a129.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a130.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a131.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a132.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a133.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a134.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a135.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a160.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a161.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a162.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a163.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a164.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a165.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a166.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a167.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a192.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a193.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a194.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a195.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a196.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a197.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a198.PORTABYTEENAMASKS -byteena_a[0] => ram_block1a199.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a40.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a41.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a42.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a43.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a44.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a45.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a46.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a47.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a72.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a73.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a74.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a75.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a76.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a77.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a78.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a79.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a104.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a105.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a106.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a107.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a108.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a109.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a110.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a111.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a136.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a137.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a138.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a139.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a140.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a141.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a142.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a143.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a168.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a169.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a170.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a171.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a172.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a173.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a174.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a175.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a200.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a201.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a202.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a203.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a204.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a205.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a206.PORTABYTEENAMASKS -byteena_a[1] => ram_block1a207.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a48.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a49.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a50.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a51.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a52.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a53.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a54.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a55.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a80.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a81.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a82.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a83.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a84.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a85.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a86.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a87.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a112.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a113.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a114.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a115.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a116.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a117.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a118.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a119.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a144.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a145.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a146.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a147.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a148.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a149.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a150.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a151.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a176.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a177.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a178.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a179.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a180.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a181.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a182.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a183.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a208.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a209.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a210.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a211.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a212.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a213.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a214.PORTABYTEENAMASKS -byteena_a[2] => ram_block1a215.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a56.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a57.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a58.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a59.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a60.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a61.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a62.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a63.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a88.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a89.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a90.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a91.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a92.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a93.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a94.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a95.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a120.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a121.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a122.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a123.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a124.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a125.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a126.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a127.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a152.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a153.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a154.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a155.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a156.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a157.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a158.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a159.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a184.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a185.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a186.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a187.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a188.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a189.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a190.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a191.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a216.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a217.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a218.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a219.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a220.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a221.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a222.PORTABYTEENAMASKS -byteena_a[3] => ram_block1a223.PORTABYTEENAMASKS -clock0 => ram_block1a0.CLK0 -clock0 => ram_block1a1.CLK0 -clock0 => ram_block1a2.CLK0 -clock0 => ram_block1a3.CLK0 -clock0 => ram_block1a4.CLK0 -clock0 => ram_block1a5.CLK0 -clock0 => ram_block1a6.CLK0 -clock0 => ram_block1a7.CLK0 -clock0 => ram_block1a8.CLK0 -clock0 => ram_block1a9.CLK0 -clock0 => ram_block1a10.CLK0 -clock0 => ram_block1a11.CLK0 -clock0 => ram_block1a12.CLK0 -clock0 => ram_block1a13.CLK0 -clock0 => ram_block1a14.CLK0 -clock0 => ram_block1a15.CLK0 -clock0 => ram_block1a16.CLK0 -clock0 => ram_block1a17.CLK0 -clock0 => ram_block1a18.CLK0 -clock0 => ram_block1a19.CLK0 -clock0 => ram_block1a20.CLK0 -clock0 => ram_block1a21.CLK0 -clock0 => ram_block1a22.CLK0 -clock0 => ram_block1a23.CLK0 -clock0 => ram_block1a24.CLK0 -clock0 => ram_block1a25.CLK0 -clock0 => ram_block1a26.CLK0 -clock0 => ram_block1a27.CLK0 -clock0 => ram_block1a28.CLK0 -clock0 => ram_block1a29.CLK0 -clock0 => ram_block1a30.CLK0 -clock0 => ram_block1a31.CLK0 -clock0 => ram_block1a32.CLK0 -clock0 => ram_block1a33.CLK0 -clock0 => ram_block1a34.CLK0 -clock0 => ram_block1a35.CLK0 -clock0 => ram_block1a36.CLK0 -clock0 => ram_block1a37.CLK0 -clock0 => ram_block1a38.CLK0 -clock0 => ram_block1a39.CLK0 -clock0 => ram_block1a40.CLK0 -clock0 => ram_block1a41.CLK0 -clock0 => ram_block1a42.CLK0 -clock0 => ram_block1a43.CLK0 -clock0 => ram_block1a44.CLK0 -clock0 => ram_block1a45.CLK0 -clock0 => ram_block1a46.CLK0 -clock0 => ram_block1a47.CLK0 -clock0 => ram_block1a48.CLK0 -clock0 => ram_block1a49.CLK0 -clock0 => ram_block1a50.CLK0 -clock0 => ram_block1a51.CLK0 -clock0 => ram_block1a52.CLK0 -clock0 => ram_block1a53.CLK0 -clock0 => ram_block1a54.CLK0 -clock0 => ram_block1a55.CLK0 -clock0 => ram_block1a56.CLK0 -clock0 => ram_block1a57.CLK0 -clock0 => ram_block1a58.CLK0 -clock0 => ram_block1a59.CLK0 -clock0 => ram_block1a60.CLK0 -clock0 => ram_block1a61.CLK0 -clock0 => ram_block1a62.CLK0 -clock0 => ram_block1a63.CLK0 -clock0 => ram_block1a64.CLK0 -clock0 => ram_block1a65.CLK0 -clock0 => ram_block1a66.CLK0 -clock0 => ram_block1a67.CLK0 -clock0 => ram_block1a68.CLK0 -clock0 => ram_block1a69.CLK0 -clock0 => ram_block1a70.CLK0 -clock0 => ram_block1a71.CLK0 -clock0 => ram_block1a72.CLK0 -clock0 => ram_block1a73.CLK0 -clock0 => ram_block1a74.CLK0 -clock0 => ram_block1a75.CLK0 -clock0 => ram_block1a76.CLK0 -clock0 => ram_block1a77.CLK0 -clock0 => ram_block1a78.CLK0 -clock0 => ram_block1a79.CLK0 -clock0 => ram_block1a80.CLK0 -clock0 => ram_block1a81.CLK0 -clock0 => ram_block1a82.CLK0 -clock0 => ram_block1a83.CLK0 -clock0 => ram_block1a84.CLK0 -clock0 => ram_block1a85.CLK0 -clock0 => ram_block1a86.CLK0 -clock0 => ram_block1a87.CLK0 -clock0 => ram_block1a88.CLK0 -clock0 => ram_block1a89.CLK0 -clock0 => ram_block1a90.CLK0 -clock0 => ram_block1a91.CLK0 -clock0 => ram_block1a92.CLK0 -clock0 => ram_block1a93.CLK0 -clock0 => ram_block1a94.CLK0 -clock0 => ram_block1a95.CLK0 -clock0 => ram_block1a96.CLK0 -clock0 => ram_block1a97.CLK0 -clock0 => ram_block1a98.CLK0 -clock0 => ram_block1a99.CLK0 -clock0 => ram_block1a100.CLK0 -clock0 => ram_block1a101.CLK0 -clock0 => ram_block1a102.CLK0 -clock0 => ram_block1a103.CLK0 -clock0 => ram_block1a104.CLK0 -clock0 => ram_block1a105.CLK0 -clock0 => ram_block1a106.CLK0 -clock0 => ram_block1a107.CLK0 -clock0 => ram_block1a108.CLK0 -clock0 => ram_block1a109.CLK0 -clock0 => ram_block1a110.CLK0 -clock0 => ram_block1a111.CLK0 -clock0 => ram_block1a112.CLK0 -clock0 => ram_block1a113.CLK0 -clock0 => ram_block1a114.CLK0 -clock0 => ram_block1a115.CLK0 -clock0 => ram_block1a116.CLK0 -clock0 => ram_block1a117.CLK0 -clock0 => ram_block1a118.CLK0 -clock0 => ram_block1a119.CLK0 -clock0 => ram_block1a120.CLK0 -clock0 => ram_block1a121.CLK0 -clock0 => ram_block1a122.CLK0 -clock0 => ram_block1a123.CLK0 -clock0 => ram_block1a124.CLK0 -clock0 => ram_block1a125.CLK0 -clock0 => ram_block1a126.CLK0 -clock0 => ram_block1a127.CLK0 -clock0 => ram_block1a128.CLK0 -clock0 => ram_block1a129.CLK0 -clock0 => ram_block1a130.CLK0 -clock0 => ram_block1a131.CLK0 -clock0 => ram_block1a132.CLK0 -clock0 => ram_block1a133.CLK0 -clock0 => ram_block1a134.CLK0 -clock0 => ram_block1a135.CLK0 -clock0 => ram_block1a136.CLK0 -clock0 => ram_block1a137.CLK0 -clock0 => ram_block1a138.CLK0 -clock0 => ram_block1a139.CLK0 -clock0 => ram_block1a140.CLK0 -clock0 => ram_block1a141.CLK0 -clock0 => ram_block1a142.CLK0 -clock0 => ram_block1a143.CLK0 -clock0 => ram_block1a144.CLK0 -clock0 => ram_block1a145.CLK0 -clock0 => ram_block1a146.CLK0 -clock0 => ram_block1a147.CLK0 -clock0 => ram_block1a148.CLK0 -clock0 => ram_block1a149.CLK0 -clock0 => ram_block1a150.CLK0 -clock0 => ram_block1a151.CLK0 -clock0 => ram_block1a152.CLK0 -clock0 => ram_block1a153.CLK0 -clock0 => ram_block1a154.CLK0 -clock0 => ram_block1a155.CLK0 -clock0 => ram_block1a156.CLK0 -clock0 => ram_block1a157.CLK0 -clock0 => ram_block1a158.CLK0 -clock0 => ram_block1a159.CLK0 -clock0 => ram_block1a160.CLK0 -clock0 => ram_block1a161.CLK0 -clock0 => ram_block1a162.CLK0 -clock0 => ram_block1a163.CLK0 -clock0 => ram_block1a164.CLK0 -clock0 => ram_block1a165.CLK0 -clock0 => ram_block1a166.CLK0 -clock0 => ram_block1a167.CLK0 -clock0 => ram_block1a168.CLK0 -clock0 => ram_block1a169.CLK0 -clock0 => ram_block1a170.CLK0 -clock0 => ram_block1a171.CLK0 -clock0 => ram_block1a172.CLK0 -clock0 => ram_block1a173.CLK0 -clock0 => ram_block1a174.CLK0 -clock0 => ram_block1a175.CLK0 -clock0 => ram_block1a176.CLK0 -clock0 => ram_block1a177.CLK0 -clock0 => ram_block1a178.CLK0 -clock0 => ram_block1a179.CLK0 -clock0 => ram_block1a180.CLK0 -clock0 => ram_block1a181.CLK0 -clock0 => ram_block1a182.CLK0 -clock0 => ram_block1a183.CLK0 -clock0 => ram_block1a184.CLK0 -clock0 => ram_block1a185.CLK0 -clock0 => ram_block1a186.CLK0 -clock0 => ram_block1a187.CLK0 -clock0 => ram_block1a188.CLK0 -clock0 => ram_block1a189.CLK0 -clock0 => ram_block1a190.CLK0 -clock0 => ram_block1a191.CLK0 -clock0 => ram_block1a192.CLK0 -clock0 => ram_block1a193.CLK0 -clock0 => ram_block1a194.CLK0 -clock0 => ram_block1a195.CLK0 -clock0 => ram_block1a196.CLK0 -clock0 => ram_block1a197.CLK0 -clock0 => ram_block1a198.CLK0 -clock0 => ram_block1a199.CLK0 -clock0 => ram_block1a200.CLK0 -clock0 => ram_block1a201.CLK0 -clock0 => ram_block1a202.CLK0 -clock0 => ram_block1a203.CLK0 -clock0 => ram_block1a204.CLK0 -clock0 => ram_block1a205.CLK0 -clock0 => ram_block1a206.CLK0 -clock0 => ram_block1a207.CLK0 -clock0 => ram_block1a208.CLK0 -clock0 => ram_block1a209.CLK0 -clock0 => ram_block1a210.CLK0 -clock0 => ram_block1a211.CLK0 -clock0 => ram_block1a212.CLK0 -clock0 => ram_block1a213.CLK0 -clock0 => ram_block1a214.CLK0 -clock0 => ram_block1a215.CLK0 -clock0 => ram_block1a216.CLK0 -clock0 => ram_block1a217.CLK0 -clock0 => ram_block1a218.CLK0 -clock0 => ram_block1a219.CLK0 -clock0 => ram_block1a220.CLK0 -clock0 => ram_block1a221.CLK0 -clock0 => ram_block1a222.CLK0 -clock0 => ram_block1a223.CLK0 -clock0 => address_reg_a[2].CLK -clock0 => address_reg_a[1].CLK -clock0 => address_reg_a[0].CLK -clocken0 => ram_block1a0.ENA0 -clocken0 => ram_block1a1.ENA0 -clocken0 => ram_block1a2.ENA0 -clocken0 => ram_block1a3.ENA0 -clocken0 => ram_block1a4.ENA0 -clocken0 => ram_block1a5.ENA0 -clocken0 => ram_block1a6.ENA0 -clocken0 => ram_block1a7.ENA0 -clocken0 => ram_block1a8.ENA0 -clocken0 => ram_block1a9.ENA0 -clocken0 => ram_block1a10.ENA0 -clocken0 => ram_block1a11.ENA0 -clocken0 => ram_block1a12.ENA0 -clocken0 => ram_block1a13.ENA0 -clocken0 => ram_block1a14.ENA0 -clocken0 => ram_block1a15.ENA0 -clocken0 => ram_block1a16.ENA0 -clocken0 => ram_block1a17.ENA0 -clocken0 => ram_block1a18.ENA0 -clocken0 => ram_block1a19.ENA0 -clocken0 => ram_block1a20.ENA0 -clocken0 => ram_block1a21.ENA0 -clocken0 => ram_block1a22.ENA0 -clocken0 => ram_block1a23.ENA0 -clocken0 => ram_block1a24.ENA0 -clocken0 => ram_block1a25.ENA0 -clocken0 => ram_block1a26.ENA0 -clocken0 => ram_block1a27.ENA0 -clocken0 => ram_block1a28.ENA0 -clocken0 => ram_block1a29.ENA0 -clocken0 => ram_block1a30.ENA0 -clocken0 => ram_block1a31.ENA0 -clocken0 => ram_block1a32.ENA0 -clocken0 => ram_block1a33.ENA0 -clocken0 => ram_block1a34.ENA0 -clocken0 => ram_block1a35.ENA0 -clocken0 => ram_block1a36.ENA0 -clocken0 => ram_block1a37.ENA0 -clocken0 => ram_block1a38.ENA0 -clocken0 => ram_block1a39.ENA0 -clocken0 => ram_block1a40.ENA0 -clocken0 => ram_block1a41.ENA0 -clocken0 => ram_block1a42.ENA0 -clocken0 => ram_block1a43.ENA0 -clocken0 => ram_block1a44.ENA0 -clocken0 => ram_block1a45.ENA0 -clocken0 => ram_block1a46.ENA0 -clocken0 => ram_block1a47.ENA0 -clocken0 => ram_block1a48.ENA0 -clocken0 => ram_block1a49.ENA0 -clocken0 => ram_block1a50.ENA0 -clocken0 => ram_block1a51.ENA0 -clocken0 => ram_block1a52.ENA0 -clocken0 => ram_block1a53.ENA0 -clocken0 => ram_block1a54.ENA0 -clocken0 => ram_block1a55.ENA0 -clocken0 => ram_block1a56.ENA0 -clocken0 => ram_block1a57.ENA0 -clocken0 => ram_block1a58.ENA0 -clocken0 => ram_block1a59.ENA0 -clocken0 => ram_block1a60.ENA0 -clocken0 => ram_block1a61.ENA0 -clocken0 => ram_block1a62.ENA0 -clocken0 => ram_block1a63.ENA0 -clocken0 => ram_block1a64.ENA0 -clocken0 => ram_block1a65.ENA0 -clocken0 => ram_block1a66.ENA0 -clocken0 => ram_block1a67.ENA0 -clocken0 => ram_block1a68.ENA0 -clocken0 => ram_block1a69.ENA0 -clocken0 => ram_block1a70.ENA0 -clocken0 => ram_block1a71.ENA0 -clocken0 => ram_block1a72.ENA0 -clocken0 => ram_block1a73.ENA0 -clocken0 => ram_block1a74.ENA0 -clocken0 => ram_block1a75.ENA0 -clocken0 => ram_block1a76.ENA0 -clocken0 => ram_block1a77.ENA0 -clocken0 => ram_block1a78.ENA0 -clocken0 => ram_block1a79.ENA0 -clocken0 => ram_block1a80.ENA0 -clocken0 => ram_block1a81.ENA0 -clocken0 => ram_block1a82.ENA0 -clocken0 => ram_block1a83.ENA0 -clocken0 => ram_block1a84.ENA0 -clocken0 => ram_block1a85.ENA0 -clocken0 => ram_block1a86.ENA0 -clocken0 => ram_block1a87.ENA0 -clocken0 => ram_block1a88.ENA0 -clocken0 => ram_block1a89.ENA0 -clocken0 => ram_block1a90.ENA0 -clocken0 => ram_block1a91.ENA0 -clocken0 => ram_block1a92.ENA0 -clocken0 => ram_block1a93.ENA0 -clocken0 => ram_block1a94.ENA0 -clocken0 => ram_block1a95.ENA0 -clocken0 => ram_block1a96.ENA0 -clocken0 => ram_block1a97.ENA0 -clocken0 => ram_block1a98.ENA0 -clocken0 => ram_block1a99.ENA0 -clocken0 => ram_block1a100.ENA0 -clocken0 => ram_block1a101.ENA0 -clocken0 => ram_block1a102.ENA0 -clocken0 => ram_block1a103.ENA0 -clocken0 => ram_block1a104.ENA0 -clocken0 => ram_block1a105.ENA0 -clocken0 => ram_block1a106.ENA0 -clocken0 => ram_block1a107.ENA0 -clocken0 => ram_block1a108.ENA0 -clocken0 => ram_block1a109.ENA0 -clocken0 => ram_block1a110.ENA0 -clocken0 => ram_block1a111.ENA0 -clocken0 => ram_block1a112.ENA0 -clocken0 => ram_block1a113.ENA0 -clocken0 => ram_block1a114.ENA0 -clocken0 => ram_block1a115.ENA0 -clocken0 => ram_block1a116.ENA0 -clocken0 => ram_block1a117.ENA0 -clocken0 => ram_block1a118.ENA0 -clocken0 => ram_block1a119.ENA0 -clocken0 => ram_block1a120.ENA0 -clocken0 => ram_block1a121.ENA0 -clocken0 => ram_block1a122.ENA0 -clocken0 => ram_block1a123.ENA0 -clocken0 => ram_block1a124.ENA0 -clocken0 => ram_block1a125.ENA0 -clocken0 => ram_block1a126.ENA0 -clocken0 => ram_block1a127.ENA0 -clocken0 => ram_block1a128.ENA0 -clocken0 => ram_block1a129.ENA0 -clocken0 => ram_block1a130.ENA0 -clocken0 => ram_block1a131.ENA0 -clocken0 => ram_block1a132.ENA0 -clocken0 => ram_block1a133.ENA0 -clocken0 => ram_block1a134.ENA0 -clocken0 => ram_block1a135.ENA0 -clocken0 => ram_block1a136.ENA0 -clocken0 => ram_block1a137.ENA0 -clocken0 => ram_block1a138.ENA0 -clocken0 => ram_block1a139.ENA0 -clocken0 => ram_block1a140.ENA0 -clocken0 => ram_block1a141.ENA0 -clocken0 => ram_block1a142.ENA0 -clocken0 => ram_block1a143.ENA0 -clocken0 => ram_block1a144.ENA0 -clocken0 => ram_block1a145.ENA0 -clocken0 => ram_block1a146.ENA0 -clocken0 => ram_block1a147.ENA0 -clocken0 => ram_block1a148.ENA0 -clocken0 => ram_block1a149.ENA0 -clocken0 => ram_block1a150.ENA0 -clocken0 => ram_block1a151.ENA0 -clocken0 => ram_block1a152.ENA0 -clocken0 => ram_block1a153.ENA0 -clocken0 => ram_block1a154.ENA0 -clocken0 => ram_block1a155.ENA0 -clocken0 => ram_block1a156.ENA0 -clocken0 => ram_block1a157.ENA0 -clocken0 => ram_block1a158.ENA0 -clocken0 => ram_block1a159.ENA0 -clocken0 => ram_block1a160.ENA0 -clocken0 => ram_block1a161.ENA0 -clocken0 => ram_block1a162.ENA0 -clocken0 => ram_block1a163.ENA0 -clocken0 => ram_block1a164.ENA0 -clocken0 => ram_block1a165.ENA0 -clocken0 => ram_block1a166.ENA0 -clocken0 => ram_block1a167.ENA0 -clocken0 => ram_block1a168.ENA0 -clocken0 => ram_block1a169.ENA0 -clocken0 => ram_block1a170.ENA0 -clocken0 => ram_block1a171.ENA0 -clocken0 => ram_block1a172.ENA0 -clocken0 => ram_block1a173.ENA0 -clocken0 => ram_block1a174.ENA0 -clocken0 => ram_block1a175.ENA0 -clocken0 => ram_block1a176.ENA0 -clocken0 => ram_block1a177.ENA0 -clocken0 => ram_block1a178.ENA0 -clocken0 => ram_block1a179.ENA0 -clocken0 => ram_block1a180.ENA0 -clocken0 => ram_block1a181.ENA0 -clocken0 => ram_block1a182.ENA0 -clocken0 => ram_block1a183.ENA0 -clocken0 => ram_block1a184.ENA0 -clocken0 => ram_block1a185.ENA0 -clocken0 => ram_block1a186.ENA0 -clocken0 => ram_block1a187.ENA0 -clocken0 => ram_block1a188.ENA0 -clocken0 => ram_block1a189.ENA0 -clocken0 => ram_block1a190.ENA0 -clocken0 => ram_block1a191.ENA0 -clocken0 => ram_block1a192.ENA0 -clocken0 => ram_block1a193.ENA0 -clocken0 => ram_block1a194.ENA0 -clocken0 => ram_block1a195.ENA0 -clocken0 => ram_block1a196.ENA0 -clocken0 => ram_block1a197.ENA0 -clocken0 => ram_block1a198.ENA0 -clocken0 => ram_block1a199.ENA0 -clocken0 => ram_block1a200.ENA0 -clocken0 => ram_block1a201.ENA0 -clocken0 => ram_block1a202.ENA0 -clocken0 => ram_block1a203.ENA0 -clocken0 => ram_block1a204.ENA0 -clocken0 => ram_block1a205.ENA0 -clocken0 => ram_block1a206.ENA0 -clocken0 => ram_block1a207.ENA0 -clocken0 => ram_block1a208.ENA0 -clocken0 => ram_block1a209.ENA0 -clocken0 => ram_block1a210.ENA0 -clocken0 => ram_block1a211.ENA0 -clocken0 => ram_block1a212.ENA0 -clocken0 => ram_block1a213.ENA0 -clocken0 => ram_block1a214.ENA0 -clocken0 => ram_block1a215.ENA0 -clocken0 => ram_block1a216.ENA0 -clocken0 => ram_block1a217.ENA0 -clocken0 => ram_block1a218.ENA0 -clocken0 => ram_block1a219.ENA0 -clocken0 => ram_block1a220.ENA0 -clocken0 => ram_block1a221.ENA0 -clocken0 => ram_block1a222.ENA0 -clocken0 => ram_block1a223.ENA0 -clocken0 => address_reg_a[2].ENA -clocken0 => address_reg_a[1].ENA -clocken0 => address_reg_a[0].ENA -data_a[0] => ram_block1a0.PORTADATAIN -data_a[0] => ram_block1a32.PORTADATAIN -data_a[0] => ram_block1a64.PORTADATAIN -data_a[0] => ram_block1a96.PORTADATAIN -data_a[0] => ram_block1a128.PORTADATAIN -data_a[0] => ram_block1a160.PORTADATAIN -data_a[0] => ram_block1a192.PORTADATAIN -data_a[1] => ram_block1a1.PORTADATAIN -data_a[1] => ram_block1a33.PORTADATAIN -data_a[1] => ram_block1a65.PORTADATAIN -data_a[1] => ram_block1a97.PORTADATAIN -data_a[1] => ram_block1a129.PORTADATAIN -data_a[1] => ram_block1a161.PORTADATAIN -data_a[1] => ram_block1a193.PORTADATAIN -data_a[2] => ram_block1a2.PORTADATAIN -data_a[2] => ram_block1a34.PORTADATAIN -data_a[2] => ram_block1a66.PORTADATAIN -data_a[2] => ram_block1a98.PORTADATAIN -data_a[2] => ram_block1a130.PORTADATAIN -data_a[2] => ram_block1a162.PORTADATAIN -data_a[2] => ram_block1a194.PORTADATAIN -data_a[3] => ram_block1a3.PORTADATAIN -data_a[3] => ram_block1a35.PORTADATAIN -data_a[3] => ram_block1a67.PORTADATAIN -data_a[3] => ram_block1a99.PORTADATAIN -data_a[3] => ram_block1a131.PORTADATAIN -data_a[3] => ram_block1a163.PORTADATAIN -data_a[3] => ram_block1a195.PORTADATAIN -data_a[4] => ram_block1a4.PORTADATAIN -data_a[4] => ram_block1a36.PORTADATAIN -data_a[4] => ram_block1a68.PORTADATAIN -data_a[4] => ram_block1a100.PORTADATAIN -data_a[4] => ram_block1a132.PORTADATAIN -data_a[4] => ram_block1a164.PORTADATAIN -data_a[4] => ram_block1a196.PORTADATAIN -data_a[5] => ram_block1a5.PORTADATAIN -data_a[5] => ram_block1a37.PORTADATAIN -data_a[5] => ram_block1a69.PORTADATAIN -data_a[5] => ram_block1a101.PORTADATAIN -data_a[5] => ram_block1a133.PORTADATAIN -data_a[5] => ram_block1a165.PORTADATAIN -data_a[5] => ram_block1a197.PORTADATAIN -data_a[6] => ram_block1a6.PORTADATAIN -data_a[6] => ram_block1a38.PORTADATAIN -data_a[6] => ram_block1a70.PORTADATAIN -data_a[6] => ram_block1a102.PORTADATAIN -data_a[6] => ram_block1a134.PORTADATAIN -data_a[6] => ram_block1a166.PORTADATAIN -data_a[6] => ram_block1a198.PORTADATAIN -data_a[7] => ram_block1a7.PORTADATAIN -data_a[7] => ram_block1a39.PORTADATAIN -data_a[7] => ram_block1a71.PORTADATAIN -data_a[7] => ram_block1a103.PORTADATAIN -data_a[7] => ram_block1a135.PORTADATAIN -data_a[7] => ram_block1a167.PORTADATAIN -data_a[7] => ram_block1a199.PORTADATAIN -data_a[8] => ram_block1a8.PORTADATAIN -data_a[8] => ram_block1a40.PORTADATAIN -data_a[8] => ram_block1a72.PORTADATAIN -data_a[8] => ram_block1a104.PORTADATAIN -data_a[8] => ram_block1a136.PORTADATAIN -data_a[8] => ram_block1a168.PORTADATAIN -data_a[8] => ram_block1a200.PORTADATAIN -data_a[9] => ram_block1a9.PORTADATAIN -data_a[9] => ram_block1a41.PORTADATAIN -data_a[9] => ram_block1a73.PORTADATAIN -data_a[9] => ram_block1a105.PORTADATAIN -data_a[9] => ram_block1a137.PORTADATAIN -data_a[9] => ram_block1a169.PORTADATAIN -data_a[9] => ram_block1a201.PORTADATAIN -data_a[10] => ram_block1a10.PORTADATAIN -data_a[10] => ram_block1a42.PORTADATAIN -data_a[10] => ram_block1a74.PORTADATAIN -data_a[10] => ram_block1a106.PORTADATAIN -data_a[10] => ram_block1a138.PORTADATAIN -data_a[10] => ram_block1a170.PORTADATAIN -data_a[10] => ram_block1a202.PORTADATAIN -data_a[11] => ram_block1a11.PORTADATAIN -data_a[11] => ram_block1a43.PORTADATAIN -data_a[11] => ram_block1a75.PORTADATAIN -data_a[11] => ram_block1a107.PORTADATAIN -data_a[11] => ram_block1a139.PORTADATAIN -data_a[11] => ram_block1a171.PORTADATAIN -data_a[11] => ram_block1a203.PORTADATAIN -data_a[12] => ram_block1a12.PORTADATAIN -data_a[12] => ram_block1a44.PORTADATAIN -data_a[12] => ram_block1a76.PORTADATAIN -data_a[12] => ram_block1a108.PORTADATAIN -data_a[12] => ram_block1a140.PORTADATAIN -data_a[12] => ram_block1a172.PORTADATAIN -data_a[12] => ram_block1a204.PORTADATAIN -data_a[13] => ram_block1a13.PORTADATAIN -data_a[13] => ram_block1a45.PORTADATAIN -data_a[13] => ram_block1a77.PORTADATAIN -data_a[13] => ram_block1a109.PORTADATAIN -data_a[13] => ram_block1a141.PORTADATAIN -data_a[13] => ram_block1a173.PORTADATAIN -data_a[13] => ram_block1a205.PORTADATAIN -data_a[14] => ram_block1a14.PORTADATAIN -data_a[14] => ram_block1a46.PORTADATAIN -data_a[14] => ram_block1a78.PORTADATAIN -data_a[14] => ram_block1a110.PORTADATAIN -data_a[14] => ram_block1a142.PORTADATAIN -data_a[14] => ram_block1a174.PORTADATAIN -data_a[14] => ram_block1a206.PORTADATAIN -data_a[15] => ram_block1a15.PORTADATAIN -data_a[15] => ram_block1a47.PORTADATAIN -data_a[15] => ram_block1a79.PORTADATAIN -data_a[15] => ram_block1a111.PORTADATAIN -data_a[15] => ram_block1a143.PORTADATAIN -data_a[15] => ram_block1a175.PORTADATAIN -data_a[15] => ram_block1a207.PORTADATAIN -data_a[16] => ram_block1a16.PORTADATAIN -data_a[16] => ram_block1a48.PORTADATAIN -data_a[16] => ram_block1a80.PORTADATAIN -data_a[16] => ram_block1a112.PORTADATAIN -data_a[16] => ram_block1a144.PORTADATAIN -data_a[16] => ram_block1a176.PORTADATAIN -data_a[16] => ram_block1a208.PORTADATAIN -data_a[17] => ram_block1a17.PORTADATAIN -data_a[17] => ram_block1a49.PORTADATAIN -data_a[17] => ram_block1a81.PORTADATAIN -data_a[17] => ram_block1a113.PORTADATAIN -data_a[17] => ram_block1a145.PORTADATAIN -data_a[17] => ram_block1a177.PORTADATAIN -data_a[17] => ram_block1a209.PORTADATAIN -data_a[18] => ram_block1a18.PORTADATAIN -data_a[18] => ram_block1a50.PORTADATAIN -data_a[18] => ram_block1a82.PORTADATAIN -data_a[18] => ram_block1a114.PORTADATAIN -data_a[18] => ram_block1a146.PORTADATAIN -data_a[18] => ram_block1a178.PORTADATAIN -data_a[18] => ram_block1a210.PORTADATAIN -data_a[19] => ram_block1a19.PORTADATAIN -data_a[19] => ram_block1a51.PORTADATAIN -data_a[19] => ram_block1a83.PORTADATAIN -data_a[19] => ram_block1a115.PORTADATAIN -data_a[19] => ram_block1a147.PORTADATAIN -data_a[19] => ram_block1a179.PORTADATAIN -data_a[19] => ram_block1a211.PORTADATAIN -data_a[20] => ram_block1a20.PORTADATAIN -data_a[20] => ram_block1a52.PORTADATAIN -data_a[20] => ram_block1a84.PORTADATAIN -data_a[20] => ram_block1a116.PORTADATAIN -data_a[20] => ram_block1a148.PORTADATAIN -data_a[20] => ram_block1a180.PORTADATAIN -data_a[20] => ram_block1a212.PORTADATAIN -data_a[21] => ram_block1a21.PORTADATAIN -data_a[21] => ram_block1a53.PORTADATAIN -data_a[21] => ram_block1a85.PORTADATAIN -data_a[21] => ram_block1a117.PORTADATAIN -data_a[21] => ram_block1a149.PORTADATAIN -data_a[21] => ram_block1a181.PORTADATAIN -data_a[21] => ram_block1a213.PORTADATAIN -data_a[22] => ram_block1a22.PORTADATAIN -data_a[22] => ram_block1a54.PORTADATAIN -data_a[22] => ram_block1a86.PORTADATAIN -data_a[22] => ram_block1a118.PORTADATAIN -data_a[22] => ram_block1a150.PORTADATAIN -data_a[22] => ram_block1a182.PORTADATAIN -data_a[22] => ram_block1a214.PORTADATAIN -data_a[23] => ram_block1a23.PORTADATAIN -data_a[23] => ram_block1a55.PORTADATAIN -data_a[23] => ram_block1a87.PORTADATAIN -data_a[23] => ram_block1a119.PORTADATAIN -data_a[23] => ram_block1a151.PORTADATAIN -data_a[23] => ram_block1a183.PORTADATAIN -data_a[23] => ram_block1a215.PORTADATAIN -data_a[24] => ram_block1a24.PORTADATAIN -data_a[24] => ram_block1a56.PORTADATAIN -data_a[24] => ram_block1a88.PORTADATAIN -data_a[24] => ram_block1a120.PORTADATAIN -data_a[24] => ram_block1a152.PORTADATAIN -data_a[24] => ram_block1a184.PORTADATAIN -data_a[24] => ram_block1a216.PORTADATAIN -data_a[25] => ram_block1a25.PORTADATAIN -data_a[25] => ram_block1a57.PORTADATAIN -data_a[25] => ram_block1a89.PORTADATAIN -data_a[25] => ram_block1a121.PORTADATAIN -data_a[25] => ram_block1a153.PORTADATAIN -data_a[25] => ram_block1a185.PORTADATAIN -data_a[25] => ram_block1a217.PORTADATAIN -data_a[26] => ram_block1a26.PORTADATAIN -data_a[26] => ram_block1a58.PORTADATAIN -data_a[26] => ram_block1a90.PORTADATAIN -data_a[26] => ram_block1a122.PORTADATAIN -data_a[26] => ram_block1a154.PORTADATAIN -data_a[26] => ram_block1a186.PORTADATAIN -data_a[26] => ram_block1a218.PORTADATAIN -data_a[27] => ram_block1a27.PORTADATAIN -data_a[27] => ram_block1a59.PORTADATAIN -data_a[27] => ram_block1a91.PORTADATAIN -data_a[27] => ram_block1a123.PORTADATAIN -data_a[27] => ram_block1a155.PORTADATAIN -data_a[27] => ram_block1a187.PORTADATAIN -data_a[27] => ram_block1a219.PORTADATAIN -data_a[28] => ram_block1a28.PORTADATAIN -data_a[28] => ram_block1a60.PORTADATAIN -data_a[28] => ram_block1a92.PORTADATAIN -data_a[28] => ram_block1a124.PORTADATAIN -data_a[28] => ram_block1a156.PORTADATAIN -data_a[28] => ram_block1a188.PORTADATAIN -data_a[28] => ram_block1a220.PORTADATAIN -data_a[29] => ram_block1a29.PORTADATAIN -data_a[29] => ram_block1a61.PORTADATAIN -data_a[29] => ram_block1a93.PORTADATAIN -data_a[29] => ram_block1a125.PORTADATAIN -data_a[29] => ram_block1a157.PORTADATAIN -data_a[29] => ram_block1a189.PORTADATAIN -data_a[29] => ram_block1a221.PORTADATAIN -data_a[30] => ram_block1a30.PORTADATAIN -data_a[30] => ram_block1a62.PORTADATAIN -data_a[30] => ram_block1a94.PORTADATAIN -data_a[30] => ram_block1a126.PORTADATAIN -data_a[30] => ram_block1a158.PORTADATAIN -data_a[30] => ram_block1a190.PORTADATAIN -data_a[30] => ram_block1a222.PORTADATAIN -data_a[31] => ram_block1a31.PORTADATAIN -data_a[31] => ram_block1a63.PORTADATAIN -data_a[31] => ram_block1a95.PORTADATAIN -data_a[31] => ram_block1a127.PORTADATAIN -data_a[31] => ram_block1a159.PORTADATAIN -data_a[31] => ram_block1a191.PORTADATAIN -data_a[31] => ram_block1a223.PORTADATAIN -q_a[0] <= mux_nob:mux2.result[0] -q_a[1] <= mux_nob:mux2.result[1] -q_a[2] <= mux_nob:mux2.result[2] -q_a[3] <= mux_nob:mux2.result[3] -q_a[4] <= mux_nob:mux2.result[4] -q_a[5] <= mux_nob:mux2.result[5] -q_a[6] <= mux_nob:mux2.result[6] -q_a[7] <= mux_nob:mux2.result[7] -q_a[8] <= mux_nob:mux2.result[8] -q_a[9] <= mux_nob:mux2.result[9] -q_a[10] <= mux_nob:mux2.result[10] -q_a[11] <= mux_nob:mux2.result[11] -q_a[12] <= mux_nob:mux2.result[12] -q_a[13] <= mux_nob:mux2.result[13] -q_a[14] <= mux_nob:mux2.result[14] -q_a[15] <= mux_nob:mux2.result[15] -q_a[16] <= mux_nob:mux2.result[16] -q_a[17] <= mux_nob:mux2.result[17] -q_a[18] <= mux_nob:mux2.result[18] -q_a[19] <= mux_nob:mux2.result[19] -q_a[20] <= mux_nob:mux2.result[20] -q_a[21] <= mux_nob:mux2.result[21] -q_a[22] <= mux_nob:mux2.result[22] -q_a[23] <= mux_nob:mux2.result[23] -q_a[24] <= mux_nob:mux2.result[24] -q_a[25] <= mux_nob:mux2.result[25] -q_a[26] <= mux_nob:mux2.result[26] -q_a[27] <= mux_nob:mux2.result[27] -q_a[28] <= mux_nob:mux2.result[28] -q_a[29] <= mux_nob:mux2.result[29] -q_a[30] <= mux_nob:mux2.result[30] -q_a[31] <= mux_nob:mux2.result[31] -wren_a => decode_qsa:decode3.enable - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 -data[0] => w_anode1849w[1].IN0 -data[0] => w_anode1866w[1].IN1 -data[0] => w_anode1876w[1].IN0 -data[0] => w_anode1886w[1].IN1 -data[0] => w_anode1896w[1].IN0 -data[0] => w_anode1906w[1].IN1 -data[0] => w_anode1916w[1].IN0 -data[0] => w_anode1926w[1].IN1 -data[1] => w_anode1849w[2].IN0 -data[1] => w_anode1866w[2].IN0 -data[1] => w_anode1876w[2].IN1 -data[1] => w_anode1886w[2].IN1 -data[1] => w_anode1896w[2].IN0 -data[1] => w_anode1906w[2].IN0 -data[1] => w_anode1916w[2].IN1 -data[1] => w_anode1926w[2].IN1 -data[2] => w_anode1849w[3].IN0 -data[2] => w_anode1866w[3].IN0 -data[2] => w_anode1876w[3].IN0 -data[2] => w_anode1886w[3].IN0 -data[2] => w_anode1896w[3].IN1 -data[2] => w_anode1906w[3].IN1 -data[2] => w_anode1916w[3].IN1 -data[2] => w_anode1926w[3].IN1 -enable => w_anode1849w[1].IN0 -enable => w_anode1866w[1].IN0 -enable => w_anode1876w[1].IN0 -enable => w_anode1886w[1].IN0 -enable => w_anode1896w[1].IN0 -enable => w_anode1906w[1].IN0 -enable => w_anode1916w[1].IN0 -enable => w_anode1926w[1].IN0 -eq[0] <= w_anode1849w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[1] <= w_anode1866w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[2] <= w_anode1876w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[3] <= w_anode1886w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[4] <= w_anode1896w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[5] <= w_anode1906w[3].DB_MAX_OUTPUT_PORT_TYPE -eq[6] <= w_anode1916w[3].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 -data[0] => _.IN0 -data[0] => _.IN0 -data[1] => _.IN0 -data[1] => _.IN0 -data[2] => _.IN0 -data[2] => _.IN0 -data[3] => _.IN0 -data[3] => _.IN0 -data[4] => _.IN0 -data[4] => _.IN0 -data[5] => _.IN0 -data[5] => _.IN0 -data[6] => _.IN0 -data[6] => _.IN0 -data[7] => _.IN0 -data[7] => _.IN0 -data[8] => _.IN0 -data[8] => _.IN0 -data[9] => _.IN0 -data[9] => _.IN0 -data[10] => _.IN0 -data[10] => _.IN0 -data[11] => _.IN0 -data[11] => _.IN0 -data[12] => _.IN0 -data[12] => _.IN0 -data[13] => _.IN0 -data[13] => _.IN0 -data[14] => _.IN0 -data[14] => _.IN0 -data[15] => _.IN0 -data[15] => _.IN0 -data[16] => _.IN0 -data[16] => _.IN0 -data[17] => _.IN0 -data[17] => _.IN0 -data[18] => _.IN0 -data[18] => _.IN0 -data[19] => _.IN0 -data[19] => _.IN0 -data[20] => _.IN0 -data[20] => _.IN0 -data[21] => _.IN0 -data[21] => _.IN0 -data[22] => _.IN0 -data[22] => _.IN0 -data[23] => _.IN0 -data[23] => _.IN0 -data[24] => _.IN0 -data[24] => _.IN0 -data[25] => _.IN0 -data[25] => _.IN0 -data[26] => _.IN0 -data[26] => _.IN0 -data[27] => _.IN0 -data[27] => _.IN0 -data[28] => _.IN0 -data[28] => _.IN0 -data[29] => _.IN0 -data[29] => _.IN0 -data[30] => _.IN0 -data[30] => _.IN0 -data[31] => _.IN0 -data[31] => _.IN0 -data[32] => _.IN0 -data[33] => _.IN0 -data[34] => _.IN0 -data[35] => _.IN0 -data[36] => _.IN0 -data[37] => _.IN0 -data[38] => _.IN0 -data[39] => _.IN0 -data[40] => _.IN0 -data[41] => _.IN0 -data[42] => _.IN0 -data[43] => _.IN0 -data[44] => _.IN0 -data[45] => _.IN0 -data[46] => _.IN0 -data[47] => _.IN0 -data[48] => _.IN0 -data[49] => _.IN0 -data[50] => _.IN0 -data[51] => _.IN0 -data[52] => _.IN0 -data[53] => _.IN0 -data[54] => _.IN0 -data[55] => _.IN0 -data[56] => _.IN0 -data[57] => _.IN0 -data[58] => _.IN0 -data[59] => _.IN0 -data[60] => _.IN0 -data[61] => _.IN0 -data[62] => _.IN0 -data[63] => _.IN0 -data[64] => _.IN1 -data[64] => _.IN1 -data[65] => _.IN1 -data[65] => _.IN1 -data[66] => _.IN1 -data[66] => _.IN1 -data[67] => _.IN1 -data[67] => _.IN1 -data[68] => _.IN1 -data[68] => _.IN1 -data[69] => _.IN1 -data[69] => _.IN1 -data[70] => _.IN1 -data[70] => _.IN1 -data[71] => _.IN1 -data[71] => _.IN1 -data[72] => _.IN1 -data[72] => _.IN1 -data[73] => _.IN1 -data[73] => _.IN1 -data[74] => _.IN1 -data[74] => _.IN1 -data[75] => _.IN1 -data[75] => _.IN1 -data[76] => _.IN1 -data[76] => _.IN1 -data[77] => _.IN1 -data[77] => _.IN1 -data[78] => _.IN1 -data[78] => _.IN1 -data[79] => _.IN1 -data[79] => _.IN1 -data[80] => _.IN1 -data[80] => _.IN1 -data[81] => _.IN1 -data[81] => _.IN1 -data[82] => _.IN1 -data[82] => _.IN1 -data[83] => _.IN1 -data[83] => _.IN1 -data[84] => _.IN1 -data[84] => _.IN1 -data[85] => _.IN1 -data[85] => _.IN1 -data[86] => _.IN1 -data[86] => _.IN1 -data[87] => _.IN1 -data[87] => _.IN1 -data[88] => _.IN1 -data[88] => _.IN1 -data[89] => _.IN1 -data[89] => _.IN1 -data[90] => _.IN1 -data[90] => _.IN1 -data[91] => _.IN1 -data[91] => _.IN1 -data[92] => _.IN1 -data[92] => _.IN1 -data[93] => _.IN1 -data[93] => _.IN1 -data[94] => _.IN1 -data[94] => _.IN1 -data[95] => _.IN1 -data[95] => _.IN1 -data[96] => _.IN0 -data[97] => _.IN0 -data[98] => _.IN0 -data[99] => _.IN0 -data[100] => _.IN0 -data[101] => _.IN0 -data[102] => _.IN0 -data[103] => _.IN0 -data[104] => _.IN0 -data[105] => _.IN0 -data[106] => _.IN0 -data[107] => _.IN0 -data[108] => _.IN0 -data[109] => _.IN0 -data[110] => _.IN0 -data[111] => _.IN0 -data[112] => _.IN0 -data[113] => _.IN0 -data[114] => _.IN0 -data[115] => _.IN0 -data[116] => _.IN0 -data[117] => _.IN0 -data[118] => _.IN0 -data[119] => _.IN0 -data[120] => _.IN0 -data[121] => _.IN0 -data[122] => _.IN0 -data[123] => _.IN0 -data[124] => _.IN0 -data[125] => _.IN0 -data[126] => _.IN0 -data[127] => _.IN0 -data[128] => _.IN0 -data[128] => _.IN0 -data[129] => _.IN0 -data[129] => _.IN0 -data[130] => _.IN0 -data[130] => _.IN0 -data[131] => _.IN0 -data[131] => _.IN0 -data[132] => _.IN0 -data[132] => _.IN0 -data[133] => _.IN0 -data[133] => _.IN0 -data[134] => _.IN0 -data[134] => _.IN0 -data[135] => _.IN0 -data[135] => _.IN0 -data[136] => _.IN0 -data[136] => _.IN0 -data[137] => _.IN0 -data[137] => _.IN0 -data[138] => _.IN0 -data[138] => _.IN0 -data[139] => _.IN0 -data[139] => _.IN0 -data[140] => _.IN0 -data[140] => _.IN0 -data[141] => _.IN0 -data[141] => _.IN0 -data[142] => _.IN0 -data[142] => _.IN0 -data[143] => _.IN0 -data[143] => _.IN0 -data[144] => _.IN0 -data[144] => _.IN0 -data[145] => _.IN0 -data[145] => _.IN0 -data[146] => _.IN0 -data[146] => _.IN0 -data[147] => _.IN0 -data[147] => _.IN0 -data[148] => _.IN0 -data[148] => _.IN0 -data[149] => _.IN0 -data[149] => _.IN0 -data[150] => _.IN0 -data[150] => _.IN0 -data[151] => _.IN0 -data[151] => _.IN0 -data[152] => _.IN0 -data[152] => _.IN0 -data[153] => _.IN0 -data[153] => _.IN0 -data[154] => _.IN0 -data[154] => _.IN0 -data[155] => _.IN0 -data[155] => _.IN0 -data[156] => _.IN0 -data[156] => _.IN0 -data[157] => _.IN0 -data[157] => _.IN0 -data[158] => _.IN0 -data[158] => _.IN0 -data[159] => _.IN0 -data[159] => _.IN0 -data[160] => _.IN0 -data[161] => _.IN0 -data[162] => _.IN0 -data[163] => _.IN0 -data[164] => _.IN0 -data[165] => _.IN0 -data[166] => _.IN0 -data[167] => _.IN0 -data[168] => _.IN0 -data[169] => _.IN0 -data[170] => _.IN0 -data[171] => _.IN0 -data[172] => _.IN0 -data[173] => _.IN0 -data[174] => _.IN0 -data[175] => _.IN0 -data[176] => _.IN0 -data[177] => _.IN0 -data[178] => _.IN0 -data[179] => _.IN0 -data[180] => _.IN0 -data[181] => _.IN0 -data[182] => _.IN0 -data[183] => _.IN0 -data[184] => _.IN0 -data[185] => _.IN0 -data[186] => _.IN0 -data[187] => _.IN0 -data[188] => _.IN0 -data[189] => _.IN0 -data[190] => _.IN0 -data[191] => _.IN0 -data[192] => _.IN1 -data[192] => _.IN1 -data[193] => _.IN1 -data[193] => _.IN1 -data[194] => _.IN1 -data[194] => _.IN1 -data[195] => _.IN1 -data[195] => _.IN1 -data[196] => _.IN1 -data[196] => _.IN1 -data[197] => _.IN1 -data[197] => _.IN1 -data[198] => _.IN1 -data[198] => _.IN1 -data[199] => _.IN1 -data[199] => _.IN1 -data[200] => _.IN1 -data[200] => _.IN1 -data[201] => _.IN1 -data[201] => _.IN1 -data[202] => _.IN1 -data[202] => _.IN1 -data[203] => _.IN1 -data[203] => _.IN1 -data[204] => _.IN1 -data[204] => _.IN1 -data[205] => _.IN1 -data[205] => _.IN1 -data[206] => _.IN1 -data[206] => _.IN1 -data[207] => _.IN1 -data[207] => _.IN1 -data[208] => _.IN1 -data[208] => _.IN1 -data[209] => _.IN1 -data[209] => _.IN1 -data[210] => _.IN1 -data[210] => _.IN1 -data[211] => _.IN1 -data[211] => _.IN1 -data[212] => _.IN1 -data[212] => _.IN1 -data[213] => _.IN1 -data[213] => _.IN1 -data[214] => _.IN1 -data[214] => _.IN1 -data[215] => _.IN1 -data[215] => _.IN1 -data[216] => _.IN1 -data[216] => _.IN1 -data[217] => _.IN1 -data[217] => _.IN1 -data[218] => _.IN1 -data[218] => _.IN1 -data[219] => _.IN1 -data[219] => _.IN1 -data[220] => _.IN1 -data[220] => _.IN1 -data[221] => _.IN1 -data[221] => _.IN1 -data[222] => _.IN1 -data[222] => _.IN1 -data[223] => _.IN1 -data[223] => _.IN1 -result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE -result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE -result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE -result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE -result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE -result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE -result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE -result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE -result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE -result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE -result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE -result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE -result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE -result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE -result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE -result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE -result[16] <= result_node[16].DB_MAX_OUTPUT_PORT_TYPE -result[17] <= result_node[17].DB_MAX_OUTPUT_PORT_TYPE -result[18] <= result_node[18].DB_MAX_OUTPUT_PORT_TYPE -result[19] <= result_node[19].DB_MAX_OUTPUT_PORT_TYPE -result[20] <= result_node[20].DB_MAX_OUTPUT_PORT_TYPE -result[21] <= result_node[21].DB_MAX_OUTPUT_PORT_TYPE -result[22] <= result_node[22].DB_MAX_OUTPUT_PORT_TYPE -result[23] <= result_node[23].DB_MAX_OUTPUT_PORT_TYPE -result[24] <= result_node[24].DB_MAX_OUTPUT_PORT_TYPE -result[25] <= result_node[25].DB_MAX_OUTPUT_PORT_TYPE -result[26] <= result_node[26].DB_MAX_OUTPUT_PORT_TYPE -result[27] <= result_node[27].DB_MAX_OUTPUT_PORT_TYPE -result[28] <= result_node[28].DB_MAX_OUTPUT_PORT_TYPE -result[29] <= result_node[29].DB_MAX_OUTPUT_PORT_TYPE -result[30] <= result_node[30].DB_MAX_OUTPUT_PORT_TYPE -result[31] <= result_node[31].DB_MAX_OUTPUT_PORT_TYPE -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN0 -sel[0] => _.IN1 -sel[0] => _.IN0 -sel[0] => _.IN0 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_.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[1] => _.IN0 -sel[2] => result_node[31].IN0 -sel[2] => _.IN0 -sel[2] => result_node[30].IN0 -sel[2] => _.IN0 -sel[2] => result_node[29].IN0 -sel[2] => _.IN0 -sel[2] => result_node[28].IN0 -sel[2] => _.IN0 -sel[2] => result_node[27].IN0 -sel[2] => _.IN0 -sel[2] => result_node[26].IN0 -sel[2] => _.IN0 -sel[2] => result_node[25].IN0 -sel[2] => _.IN0 -sel[2] => result_node[24].IN0 -sel[2] => _.IN0 -sel[2] => result_node[23].IN0 -sel[2] => _.IN0 -sel[2] => result_node[22].IN0 -sel[2] => _.IN0 -sel[2] => result_node[21].IN0 -sel[2] => _.IN0 -sel[2] => result_node[20].IN0 -sel[2] => _.IN0 -sel[2] => result_node[19].IN0 -sel[2] => _.IN0 -sel[2] => result_node[18].IN0 -sel[2] => _.IN0 -sel[2] => result_node[17].IN0 -sel[2] => _.IN0 -sel[2] => result_node[16].IN0 -sel[2] => _.IN0 -sel[2] => result_node[15].IN0 -sel[2] => _.IN0 -sel[2] => result_node[14].IN0 -sel[2] => _.IN0 -sel[2] => result_node[13].IN0 -sel[2] => _.IN0 -sel[2] => result_node[12].IN0 -sel[2] => _.IN0 -sel[2] => result_node[11].IN0 -sel[2] => _.IN0 -sel[2] => result_node[10].IN0 -sel[2] => _.IN0 -sel[2] => result_node[9].IN0 -sel[2] => _.IN0 -sel[2] => result_node[8].IN0 -sel[2] => _.IN0 -sel[2] => result_node[7].IN0 -sel[2] => _.IN0 -sel[2] => result_node[6].IN0 -sel[2] => _.IN0 -sel[2] => result_node[5].IN0 -sel[2] => _.IN0 -sel[2] => result_node[4].IN0 -sel[2] => _.IN0 -sel[2] => result_node[3].IN0 -sel[2] => _.IN0 -sel[2] => result_node[2].IN0 -sel[2] => _.IN0 -sel[2] => result_node[1].IN0 -sel[2] => _.IN0 -sel[2] => result_node[0].IN0 -sel[2] => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart -av_address => ien_AF.OUTPUTSELECT -av_address => ien_AE.OUTPUTSELECT -av_address => ac.OUTPUTSELECT -av_address => fifo_wr.OUTPUTSELECT -av_address => woverflow.OUTPUTSELECT -av_address => rvalid.OUTPUTSELECT -av_address => read_0.DATAB -av_address => fifo_rd.IN1 -av_chipselect => av_waitrequest.IN1 -av_chipselect => always2.IN0 -av_chipselect => always2.IN0 -av_chipselect => fifo_rd.IN0 -av_read_n => always2.IN1 -av_read_n => av_waitrequest.IN0 -av_read_n => fifo_rd.IN1 -av_write_n => always2.IN1 -av_write_n => av_waitrequest.IN1 -av_writedata[0] => fifo_wdata[0].IN1 -av_writedata[1] => fifo_wdata[1].IN1 -av_writedata[2] => fifo_wdata[2].IN1 -av_writedata[3] => fifo_wdata[3].IN1 -av_writedata[4] => fifo_wdata[4].IN1 -av_writedata[5] => fifo_wdata[5].IN1 -av_writedata[6] => fifo_wdata[6].IN1 -av_writedata[7] => fifo_wdata[7].IN1 -av_writedata[8] => ~NO_FANOUT~ -av_writedata[9] => ~NO_FANOUT~ -av_writedata[10] => always2.IN1 -av_writedata[11] => ~NO_FANOUT~ -av_writedata[12] => ~NO_FANOUT~ -av_writedata[13] => ~NO_FANOUT~ -av_writedata[14] => ~NO_FANOUT~ -av_writedata[15] => ~NO_FANOUT~ -av_writedata[16] => ~NO_FANOUT~ -av_writedata[17] => ~NO_FANOUT~ -av_writedata[18] => ~NO_FANOUT~ -av_writedata[19] => ~NO_FANOUT~ -av_writedata[20] => ~NO_FANOUT~ -av_writedata[21] => ~NO_FANOUT~ -av_writedata[22] => ~NO_FANOUT~ -av_writedata[23] => ~NO_FANOUT~ -av_writedata[24] => ~NO_FANOUT~ -av_writedata[25] => ~NO_FANOUT~ -av_writedata[26] => ~NO_FANOUT~ -av_writedata[27] => ~NO_FANOUT~ -av_writedata[28] => ~NO_FANOUT~ -av_writedata[29] => ~NO_FANOUT~ -av_writedata[30] => ~NO_FANOUT~ -av_writedata[31] => ~NO_FANOUT~ -clk => clk.IN3 -rst_n => rst_n.IN2 -av_irq <= av_irq.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= ipen_AF.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= ipen_AE.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= ac.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= -av_readdata[12] <= nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r.fifo_EF -av_readdata[13] <= nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w.fifo_FF -av_readdata[14] <= woverflow.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= rvalid.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= -av_readdata[24] <= -av_readdata[25] <= -av_readdata[26] <= -av_readdata[27] <= -av_readdata[28] <= -av_readdata[29] <= -av_readdata[30] <= -av_readdata[31] <= -av_waitrequest <= av_waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE -dataavailable <= dataavailable~reg0.DB_MAX_OUTPUT_PORT_TYPE -readyfordata <= readyfordata~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w -clk => clk.IN1 -fifo_clear => fifo_clear.IN1 -fifo_wdata[0] => fifo_wdata[0].IN1 -fifo_wdata[1] => fifo_wdata[1].IN1 -fifo_wdata[2] => fifo_wdata[2].IN1 -fifo_wdata[3] => fifo_wdata[3].IN1 -fifo_wdata[4] => fifo_wdata[4].IN1 -fifo_wdata[5] => fifo_wdata[5].IN1 -fifo_wdata[6] => fifo_wdata[6].IN1 -fifo_wdata[7] => fifo_wdata[7].IN1 -fifo_wr => fifo_wr.IN1 -rd_wfifo => rd_wfifo.IN1 -fifo_FF <= scfifo:wfifo.full -r_dat[0] <= scfifo:wfifo.q -r_dat[1] <= scfifo:wfifo.q -r_dat[2] <= scfifo:wfifo.q -r_dat[3] <= scfifo:wfifo.q -r_dat[4] <= scfifo:wfifo.q -r_dat[5] <= scfifo:wfifo.q -r_dat[6] <= scfifo:wfifo.q -r_dat[7] <= scfifo:wfifo.q -wfifo_empty <= scfifo:wfifo.empty -wfifo_used[0] <= scfifo:wfifo.usedw -wfifo_used[1] <= scfifo:wfifo.usedw -wfifo_used[2] <= scfifo:wfifo.usedw -wfifo_used[3] <= scfifo:wfifo.usedw -wfifo_used[4] <= scfifo:wfifo.usedw -wfifo_used[5] <= scfifo:wfifo.usedw - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo -data[0] => scfifo_jr21:auto_generated.data[0] -data[1] => scfifo_jr21:auto_generated.data[1] -data[2] => scfifo_jr21:auto_generated.data[2] -data[3] => scfifo_jr21:auto_generated.data[3] -data[4] => scfifo_jr21:auto_generated.data[4] -data[5] => scfifo_jr21:auto_generated.data[5] -data[6] => scfifo_jr21:auto_generated.data[6] -data[7] => scfifo_jr21:auto_generated.data[7] -q[0] <= scfifo_jr21:auto_generated.q[0] -q[1] <= scfifo_jr21:auto_generated.q[1] -q[2] <= scfifo_jr21:auto_generated.q[2] -q[3] <= scfifo_jr21:auto_generated.q[3] -q[4] <= scfifo_jr21:auto_generated.q[4] -q[5] <= scfifo_jr21:auto_generated.q[5] -q[6] <= scfifo_jr21:auto_generated.q[6] -q[7] <= scfifo_jr21:auto_generated.q[7] -wrreq => scfifo_jr21:auto_generated.wrreq -rdreq => scfifo_jr21:auto_generated.rdreq -clock => scfifo_jr21:auto_generated.clock -aclr => scfifo_jr21:auto_generated.aclr -sclr => ~NO_FANOUT~ -empty <= scfifo_jr21:auto_generated.empty -full <= scfifo_jr21:auto_generated.full -almost_full <= -almost_empty <= -usedw[0] <= scfifo_jr21:auto_generated.usedw[0] -usedw[1] <= scfifo_jr21:auto_generated.usedw[1] -usedw[2] <= scfifo_jr21:auto_generated.usedw[2] -usedw[3] <= scfifo_jr21:auto_generated.usedw[3] -usedw[4] <= scfifo_jr21:auto_generated.usedw[4] -usedw[5] <= scfifo_jr21:auto_generated.usedw[5] - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated -aclr => a_dpfifo_q131:dpfifo.aclr -clock => a_dpfifo_q131:dpfifo.clock -data[0] => a_dpfifo_q131:dpfifo.data[0] -data[1] => a_dpfifo_q131:dpfifo.data[1] -data[2] => a_dpfifo_q131:dpfifo.data[2] -data[3] => a_dpfifo_q131:dpfifo.data[3] -data[4] => a_dpfifo_q131:dpfifo.data[4] -data[5] => a_dpfifo_q131:dpfifo.data[5] -data[6] => a_dpfifo_q131:dpfifo.data[6] -data[7] => a_dpfifo_q131:dpfifo.data[7] -empty <= a_dpfifo_q131:dpfifo.empty -full <= a_dpfifo_q131:dpfifo.full -q[0] <= a_dpfifo_q131:dpfifo.q[0] -q[1] <= a_dpfifo_q131:dpfifo.q[1] -q[2] <= a_dpfifo_q131:dpfifo.q[2] -q[3] <= a_dpfifo_q131:dpfifo.q[3] -q[4] <= a_dpfifo_q131:dpfifo.q[4] -q[5] <= a_dpfifo_q131:dpfifo.q[5] -q[6] <= a_dpfifo_q131:dpfifo.q[6] -q[7] <= a_dpfifo_q131:dpfifo.q[7] -rdreq => a_dpfifo_q131:dpfifo.rreq -usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] -usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] -usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] -usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] -usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] -usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] -wrreq => a_dpfifo_q131:dpfifo.wreq - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo -aclr => a_fefifo_7cf:fifo_state.aclr -aclr => cntr_1ob:rd_ptr_count.aclr -aclr => cntr_1ob:wr_ptr.aclr -clock => a_fefifo_7cf:fifo_state.clock -clock => dpram_nl21:FIFOram.inclock -clock => dpram_nl21:FIFOram.outclock -clock => cntr_1ob:rd_ptr_count.clock -clock => cntr_1ob:wr_ptr.clock -data[0] => dpram_nl21:FIFOram.data[0] -data[1] => dpram_nl21:FIFOram.data[1] -data[2] => dpram_nl21:FIFOram.data[2] -data[3] => dpram_nl21:FIFOram.data[3] -data[4] => dpram_nl21:FIFOram.data[4] -data[5] => dpram_nl21:FIFOram.data[5] -data[6] => dpram_nl21:FIFOram.data[6] -data[7] => dpram_nl21:FIFOram.data[7] -empty <= a_fefifo_7cf:fifo_state.empty -full <= a_fefifo_7cf:fifo_state.full -q[0] <= dpram_nl21:FIFOram.q[0] -q[1] <= dpram_nl21:FIFOram.q[1] -q[2] <= dpram_nl21:FIFOram.q[2] -q[3] <= dpram_nl21:FIFOram.q[3] -q[4] <= dpram_nl21:FIFOram.q[4] -q[5] <= dpram_nl21:FIFOram.q[5] -q[6] <= dpram_nl21:FIFOram.q[6] -q[7] <= dpram_nl21:FIFOram.q[7] -rreq => a_fefifo_7cf:fifo_state.rreq -rreq => _.IN0 -rreq => cntr_1ob:rd_ptr_count.cnt_en -sclr => a_fefifo_7cf:fifo_state.sclr -sclr => _.IN1 -sclr => _.IN0 -sclr => cntr_1ob:rd_ptr_count.sclr -sclr => cntr_1ob:wr_ptr.sclr -usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] -usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] -usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] -usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] -usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] -usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] -wreq => a_fefifo_7cf:fifo_state.wreq -wreq => dpram_nl21:FIFOram.wren -wreq => cntr_1ob:wr_ptr.cnt_en - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state -aclr => b_full.IN0 -aclr => b_non_empty.IN0 -aclr => cntr_do7:count_usedw.aclr -clock => cntr_do7:count_usedw.clock -clock => b_full.CLK -clock => b_non_empty.CLK -empty <= empty.DB_MAX_OUTPUT_PORT_TYPE -full <= b_full.DB_MAX_OUTPUT_PORT_TYPE -rreq => _.IN1 -rreq => _.IN0 -rreq => _.IN1 -rreq => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => cntr_do7:count_usedw.sclr -usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE -wreq => _.IN1 -wreq => _.IN1 -wreq => _.IN0 -wreq => _.IN0 -wreq => cntr_do7:count_usedw.updown - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 -updown => counter_comb_bita0.DATAB -updown => counter_comb_bita1.DATAB -updown => counter_comb_bita2.DATAB -updown => counter_comb_bita3.DATAB -updown => counter_comb_bita4.DATAB -updown => counter_comb_bita5.DATAB - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram -data[0] => altsyncram_r1m1:altsyncram1.data_a[0] -data[1] => altsyncram_r1m1:altsyncram1.data_a[1] -data[2] => altsyncram_r1m1:altsyncram1.data_a[2] -data[3] => altsyncram_r1m1:altsyncram1.data_a[3] -data[4] => altsyncram_r1m1:altsyncram1.data_a[4] -data[5] => altsyncram_r1m1:altsyncram1.data_a[5] -data[6] => altsyncram_r1m1:altsyncram1.data_a[6] -data[7] => altsyncram_r1m1:altsyncram1.data_a[7] -inclock => altsyncram_r1m1:altsyncram1.clock0 -outclock => altsyncram_r1m1:altsyncram1.clock1 -outclocken => altsyncram_r1m1:altsyncram1.clocken1 -q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] -q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] -q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] -q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] -q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] -q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] -q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] -q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] -rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] -rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] -rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] -rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] -rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] -rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] -wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] -wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] -wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] -wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] -wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] -wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] -wren => altsyncram_r1m1:altsyncram1.wren_a - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 -address_a[0] => ram_block2a0.PORTAADDR -address_a[0] => ram_block2a1.PORTAADDR -address_a[0] => ram_block2a2.PORTAADDR -address_a[0] => ram_block2a3.PORTAADDR -address_a[0] => ram_block2a4.PORTAADDR -address_a[0] => ram_block2a5.PORTAADDR -address_a[0] => ram_block2a6.PORTAADDR -address_a[0] => ram_block2a7.PORTAADDR -address_a[1] => ram_block2a0.PORTAADDR1 -address_a[1] => ram_block2a1.PORTAADDR1 -address_a[1] => ram_block2a2.PORTAADDR1 -address_a[1] => ram_block2a3.PORTAADDR1 -address_a[1] => ram_block2a4.PORTAADDR1 -address_a[1] => ram_block2a5.PORTAADDR1 -address_a[1] => ram_block2a6.PORTAADDR1 -address_a[1] => ram_block2a7.PORTAADDR1 -address_a[2] => ram_block2a0.PORTAADDR2 -address_a[2] => ram_block2a1.PORTAADDR2 -address_a[2] => ram_block2a2.PORTAADDR2 -address_a[2] => ram_block2a3.PORTAADDR2 -address_a[2] => ram_block2a4.PORTAADDR2 -address_a[2] => ram_block2a5.PORTAADDR2 -address_a[2] => ram_block2a6.PORTAADDR2 -address_a[2] => ram_block2a7.PORTAADDR2 -address_a[3] => ram_block2a0.PORTAADDR3 -address_a[3] => ram_block2a1.PORTAADDR3 -address_a[3] => ram_block2a2.PORTAADDR3 -address_a[3] => ram_block2a3.PORTAADDR3 -address_a[3] => ram_block2a4.PORTAADDR3 -address_a[3] => ram_block2a5.PORTAADDR3 -address_a[3] => ram_block2a6.PORTAADDR3 -address_a[3] => ram_block2a7.PORTAADDR3 -address_a[4] => ram_block2a0.PORTAADDR4 -address_a[4] => ram_block2a1.PORTAADDR4 -address_a[4] => ram_block2a2.PORTAADDR4 -address_a[4] => ram_block2a3.PORTAADDR4 -address_a[4] => ram_block2a4.PORTAADDR4 -address_a[4] => ram_block2a5.PORTAADDR4 -address_a[4] => ram_block2a6.PORTAADDR4 -address_a[4] => ram_block2a7.PORTAADDR4 -address_a[5] => ram_block2a0.PORTAADDR5 -address_a[5] => ram_block2a1.PORTAADDR5 -address_a[5] => ram_block2a2.PORTAADDR5 -address_a[5] => ram_block2a3.PORTAADDR5 -address_a[5] => ram_block2a4.PORTAADDR5 -address_a[5] => ram_block2a5.PORTAADDR5 -address_a[5] => ram_block2a6.PORTAADDR5 -address_a[5] => ram_block2a7.PORTAADDR5 -address_b[0] => ram_block2a0.PORTBADDR -address_b[0] => ram_block2a1.PORTBADDR -address_b[0] => ram_block2a2.PORTBADDR -address_b[0] => ram_block2a3.PORTBADDR -address_b[0] => ram_block2a4.PORTBADDR -address_b[0] => ram_block2a5.PORTBADDR -address_b[0] => ram_block2a6.PORTBADDR -address_b[0] => ram_block2a7.PORTBADDR -address_b[1] => ram_block2a0.PORTBADDR1 -address_b[1] => ram_block2a1.PORTBADDR1 -address_b[1] => ram_block2a2.PORTBADDR1 -address_b[1] => ram_block2a3.PORTBADDR1 -address_b[1] => ram_block2a4.PORTBADDR1 -address_b[1] => ram_block2a5.PORTBADDR1 -address_b[1] => ram_block2a6.PORTBADDR1 -address_b[1] => ram_block2a7.PORTBADDR1 -address_b[2] => ram_block2a0.PORTBADDR2 -address_b[2] => ram_block2a1.PORTBADDR2 -address_b[2] => ram_block2a2.PORTBADDR2 -address_b[2] => ram_block2a3.PORTBADDR2 -address_b[2] => ram_block2a4.PORTBADDR2 -address_b[2] => ram_block2a5.PORTBADDR2 -address_b[2] => ram_block2a6.PORTBADDR2 -address_b[2] => ram_block2a7.PORTBADDR2 -address_b[3] => ram_block2a0.PORTBADDR3 -address_b[3] => ram_block2a1.PORTBADDR3 -address_b[3] => ram_block2a2.PORTBADDR3 -address_b[3] => ram_block2a3.PORTBADDR3 -address_b[3] => ram_block2a4.PORTBADDR3 -address_b[3] => ram_block2a5.PORTBADDR3 -address_b[3] => ram_block2a6.PORTBADDR3 -address_b[3] => ram_block2a7.PORTBADDR3 -address_b[4] => ram_block2a0.PORTBADDR4 -address_b[4] => ram_block2a1.PORTBADDR4 -address_b[4] => ram_block2a2.PORTBADDR4 -address_b[4] => ram_block2a3.PORTBADDR4 -address_b[4] => ram_block2a4.PORTBADDR4 -address_b[4] => ram_block2a5.PORTBADDR4 -address_b[4] => ram_block2a6.PORTBADDR4 -address_b[4] => ram_block2a7.PORTBADDR4 -address_b[5] => ram_block2a0.PORTBADDR5 -address_b[5] => ram_block2a1.PORTBADDR5 -address_b[5] => ram_block2a2.PORTBADDR5 -address_b[5] => ram_block2a3.PORTBADDR5 -address_b[5] => ram_block2a4.PORTBADDR5 -address_b[5] => ram_block2a5.PORTBADDR5 -address_b[5] => ram_block2a6.PORTBADDR5 -address_b[5] => ram_block2a7.PORTBADDR5 -clock0 => ram_block2a0.CLK0 -clock0 => ram_block2a1.CLK0 -clock0 => ram_block2a2.CLK0 -clock0 => ram_block2a3.CLK0 -clock0 => ram_block2a4.CLK0 -clock0 => ram_block2a5.CLK0 -clock0 => ram_block2a6.CLK0 -clock0 => ram_block2a7.CLK0 -clock1 => ram_block2a0.CLK1 -clock1 => ram_block2a1.CLK1 -clock1 => ram_block2a2.CLK1 -clock1 => ram_block2a3.CLK1 -clock1 => ram_block2a4.CLK1 -clock1 => ram_block2a5.CLK1 -clock1 => ram_block2a6.CLK1 -clock1 => ram_block2a7.CLK1 -clocken1 => ram_block2a0.ENA1 -clocken1 => ram_block2a1.ENA1 -clocken1 => ram_block2a2.ENA1 -clocken1 => ram_block2a3.ENA1 -clocken1 => ram_block2a4.ENA1 -clocken1 => ram_block2a5.ENA1 -clocken1 => ram_block2a6.ENA1 -clocken1 => ram_block2a7.ENA1 -data_a[0] => ram_block2a0.PORTADATAIN -data_a[1] => ram_block2a1.PORTADATAIN -data_a[2] => ram_block2a2.PORTADATAIN -data_a[3] => ram_block2a3.PORTADATAIN -data_a[4] => ram_block2a4.PORTADATAIN -data_a[5] => ram_block2a5.PORTADATAIN -data_a[6] => ram_block2a6.PORTADATAIN -data_a[7] => ram_block2a7.PORTADATAIN -q_b[0] <= ram_block2a0.PORTBDATAOUT -q_b[1] <= ram_block2a1.PORTBDATAOUT -q_b[2] <= ram_block2a2.PORTBDATAOUT -q_b[3] <= ram_block2a3.PORTBDATAOUT -q_b[4] <= ram_block2a4.PORTBDATAOUT -q_b[5] <= ram_block2a5.PORTBDATAOUT -q_b[6] <= ram_block2a6.PORTBDATAOUT -q_b[7] <= ram_block2a7.PORTBDATAOUT -wren_a => ram_block2a0.PORTAWE -wren_a => ram_block2a0.ENA0 -wren_a => ram_block2a1.PORTAWE -wren_a => ram_block2a1.ENA0 -wren_a => ram_block2a2.PORTAWE -wren_a => ram_block2a2.ENA0 -wren_a => ram_block2a3.PORTAWE -wren_a => ram_block2a3.ENA0 -wren_a => ram_block2a4.PORTAWE -wren_a => ram_block2a4.ENA0 -wren_a => ram_block2a5.PORTAWE -wren_a => ram_block2a5.ENA0 -wren_a => ram_block2a6.PORTAWE -wren_a => ram_block2a6.ENA0 -wren_a => ram_block2a7.PORTAWE -wren_a => ram_block2a7.ENA0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r -clk => clk.IN1 -fifo_clear => fifo_clear.IN1 -fifo_rd => fifo_rd.IN1 -rst_n => ~NO_FANOUT~ -t_dat[0] => t_dat[0].IN1 -t_dat[1] => t_dat[1].IN1 -t_dat[2] => t_dat[2].IN1 -t_dat[3] => t_dat[3].IN1 -t_dat[4] => t_dat[4].IN1 -t_dat[5] => t_dat[5].IN1 -t_dat[6] => t_dat[6].IN1 -t_dat[7] => t_dat[7].IN1 -wr_rfifo => wr_rfifo.IN1 -fifo_EF <= scfifo:rfifo.empty -fifo_rdata[0] <= scfifo:rfifo.q -fifo_rdata[1] <= scfifo:rfifo.q -fifo_rdata[2] <= scfifo:rfifo.q -fifo_rdata[3] <= scfifo:rfifo.q -fifo_rdata[4] <= scfifo:rfifo.q -fifo_rdata[5] <= scfifo:rfifo.q -fifo_rdata[6] <= scfifo:rfifo.q -fifo_rdata[7] <= scfifo:rfifo.q -rfifo_full <= scfifo:rfifo.full -rfifo_used[0] <= scfifo:rfifo.usedw -rfifo_used[1] <= scfifo:rfifo.usedw -rfifo_used[2] <= scfifo:rfifo.usedw -rfifo_used[3] <= scfifo:rfifo.usedw -rfifo_used[4] <= scfifo:rfifo.usedw -rfifo_used[5] <= scfifo:rfifo.usedw - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo -data[0] => scfifo_jr21:auto_generated.data[0] -data[1] => scfifo_jr21:auto_generated.data[1] -data[2] => scfifo_jr21:auto_generated.data[2] -data[3] => scfifo_jr21:auto_generated.data[3] -data[4] => scfifo_jr21:auto_generated.data[4] -data[5] => scfifo_jr21:auto_generated.data[5] -data[6] => scfifo_jr21:auto_generated.data[6] -data[7] => scfifo_jr21:auto_generated.data[7] -q[0] <= scfifo_jr21:auto_generated.q[0] -q[1] <= scfifo_jr21:auto_generated.q[1] -q[2] <= scfifo_jr21:auto_generated.q[2] -q[3] <= scfifo_jr21:auto_generated.q[3] -q[4] <= scfifo_jr21:auto_generated.q[4] -q[5] <= scfifo_jr21:auto_generated.q[5] -q[6] <= scfifo_jr21:auto_generated.q[6] -q[7] <= scfifo_jr21:auto_generated.q[7] -wrreq => scfifo_jr21:auto_generated.wrreq -rdreq => scfifo_jr21:auto_generated.rdreq -clock => scfifo_jr21:auto_generated.clock -aclr => scfifo_jr21:auto_generated.aclr -sclr => ~NO_FANOUT~ -empty <= scfifo_jr21:auto_generated.empty -full <= scfifo_jr21:auto_generated.full -almost_full <= -almost_empty <= -usedw[0] <= scfifo_jr21:auto_generated.usedw[0] -usedw[1] <= scfifo_jr21:auto_generated.usedw[1] -usedw[2] <= scfifo_jr21:auto_generated.usedw[2] -usedw[3] <= scfifo_jr21:auto_generated.usedw[3] -usedw[4] <= scfifo_jr21:auto_generated.usedw[4] -usedw[5] <= scfifo_jr21:auto_generated.usedw[5] - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated -aclr => a_dpfifo_q131:dpfifo.aclr -clock => a_dpfifo_q131:dpfifo.clock -data[0] => a_dpfifo_q131:dpfifo.data[0] -data[1] => a_dpfifo_q131:dpfifo.data[1] -data[2] => a_dpfifo_q131:dpfifo.data[2] -data[3] => a_dpfifo_q131:dpfifo.data[3] -data[4] => a_dpfifo_q131:dpfifo.data[4] -data[5] => a_dpfifo_q131:dpfifo.data[5] -data[6] => a_dpfifo_q131:dpfifo.data[6] -data[7] => a_dpfifo_q131:dpfifo.data[7] -empty <= a_dpfifo_q131:dpfifo.empty -full <= a_dpfifo_q131:dpfifo.full -q[0] <= a_dpfifo_q131:dpfifo.q[0] -q[1] <= a_dpfifo_q131:dpfifo.q[1] -q[2] <= a_dpfifo_q131:dpfifo.q[2] -q[3] <= a_dpfifo_q131:dpfifo.q[3] -q[4] <= a_dpfifo_q131:dpfifo.q[4] -q[5] <= a_dpfifo_q131:dpfifo.q[5] -q[6] <= a_dpfifo_q131:dpfifo.q[6] -q[7] <= a_dpfifo_q131:dpfifo.q[7] -rdreq => a_dpfifo_q131:dpfifo.rreq -usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] -usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] -usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] -usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] -usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] -usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] -wrreq => a_dpfifo_q131:dpfifo.wreq - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo -aclr => a_fefifo_7cf:fifo_state.aclr -aclr => cntr_1ob:rd_ptr_count.aclr -aclr => cntr_1ob:wr_ptr.aclr -clock => a_fefifo_7cf:fifo_state.clock -clock => dpram_nl21:FIFOram.inclock -clock => dpram_nl21:FIFOram.outclock -clock => cntr_1ob:rd_ptr_count.clock -clock => cntr_1ob:wr_ptr.clock -data[0] => dpram_nl21:FIFOram.data[0] -data[1] => dpram_nl21:FIFOram.data[1] -data[2] => dpram_nl21:FIFOram.data[2] -data[3] => dpram_nl21:FIFOram.data[3] -data[4] => dpram_nl21:FIFOram.data[4] -data[5] => dpram_nl21:FIFOram.data[5] -data[6] => dpram_nl21:FIFOram.data[6] -data[7] => dpram_nl21:FIFOram.data[7] -empty <= a_fefifo_7cf:fifo_state.empty -full <= a_fefifo_7cf:fifo_state.full -q[0] <= dpram_nl21:FIFOram.q[0] -q[1] <= dpram_nl21:FIFOram.q[1] -q[2] <= dpram_nl21:FIFOram.q[2] -q[3] <= dpram_nl21:FIFOram.q[3] -q[4] <= dpram_nl21:FIFOram.q[4] -q[5] <= dpram_nl21:FIFOram.q[5] -q[6] <= dpram_nl21:FIFOram.q[6] -q[7] <= dpram_nl21:FIFOram.q[7] -rreq => a_fefifo_7cf:fifo_state.rreq -rreq => _.IN0 -rreq => cntr_1ob:rd_ptr_count.cnt_en -sclr => a_fefifo_7cf:fifo_state.sclr -sclr => _.IN1 -sclr => _.IN0 -sclr => cntr_1ob:rd_ptr_count.sclr -sclr => cntr_1ob:wr_ptr.sclr -usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] -usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] -usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] -usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] -usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] -usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] -wreq => a_fefifo_7cf:fifo_state.wreq -wreq => dpram_nl21:FIFOram.wren -wreq => cntr_1ob:wr_ptr.cnt_en - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state -aclr => b_full.IN0 -aclr => b_non_empty.IN0 -aclr => cntr_do7:count_usedw.aclr -clock => cntr_do7:count_usedw.clock -clock => b_full.CLK -clock => b_non_empty.CLK -empty <= empty.DB_MAX_OUTPUT_PORT_TYPE -full <= b_full.DB_MAX_OUTPUT_PORT_TYPE -rreq => _.IN1 -rreq => _.IN0 -rreq => _.IN1 -rreq => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN1 -sclr => _.IN0 -sclr => _.IN0 -sclr => cntr_do7:count_usedw.sclr -usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE -usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE -wreq => _.IN1 -wreq => _.IN1 -wreq => _.IN0 -wreq => _.IN0 -wreq => cntr_do7:count_usedw.updown - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 -updown => counter_comb_bita0.DATAB -updown => counter_comb_bita1.DATAB -updown => counter_comb_bita2.DATAB -updown => counter_comb_bita3.DATAB -updown => counter_comb_bita4.DATAB -updown => counter_comb_bita5.DATAB - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram -data[0] => altsyncram_r1m1:altsyncram1.data_a[0] -data[1] => altsyncram_r1m1:altsyncram1.data_a[1] -data[2] => altsyncram_r1m1:altsyncram1.data_a[2] -data[3] => altsyncram_r1m1:altsyncram1.data_a[3] -data[4] => altsyncram_r1m1:altsyncram1.data_a[4] -data[5] => altsyncram_r1m1:altsyncram1.data_a[5] -data[6] => altsyncram_r1m1:altsyncram1.data_a[6] -data[7] => altsyncram_r1m1:altsyncram1.data_a[7] -inclock => altsyncram_r1m1:altsyncram1.clock0 -outclock => altsyncram_r1m1:altsyncram1.clock1 -outclocken => altsyncram_r1m1:altsyncram1.clocken1 -q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] -q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] -q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] -q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] -q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] -q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] -q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] -q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] -rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] -rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] -rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] -rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] -rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] -rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] -wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] -wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] -wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] -wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] -wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] -wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] -wren => altsyncram_r1m1:altsyncram1.wren_a - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 -address_a[0] => ram_block2a0.PORTAADDR -address_a[0] => ram_block2a1.PORTAADDR -address_a[0] => ram_block2a2.PORTAADDR -address_a[0] => ram_block2a3.PORTAADDR -address_a[0] => ram_block2a4.PORTAADDR -address_a[0] => ram_block2a5.PORTAADDR -address_a[0] => ram_block2a6.PORTAADDR -address_a[0] => ram_block2a7.PORTAADDR -address_a[1] => ram_block2a0.PORTAADDR1 -address_a[1] => ram_block2a1.PORTAADDR1 -address_a[1] => ram_block2a2.PORTAADDR1 -address_a[1] => ram_block2a3.PORTAADDR1 -address_a[1] => ram_block2a4.PORTAADDR1 -address_a[1] => ram_block2a5.PORTAADDR1 -address_a[1] => ram_block2a6.PORTAADDR1 -address_a[1] => ram_block2a7.PORTAADDR1 -address_a[2] => ram_block2a0.PORTAADDR2 -address_a[2] => ram_block2a1.PORTAADDR2 -address_a[2] => ram_block2a2.PORTAADDR2 -address_a[2] => ram_block2a3.PORTAADDR2 -address_a[2] => ram_block2a4.PORTAADDR2 -address_a[2] => ram_block2a5.PORTAADDR2 -address_a[2] => ram_block2a6.PORTAADDR2 -address_a[2] => ram_block2a7.PORTAADDR2 -address_a[3] => ram_block2a0.PORTAADDR3 -address_a[3] => ram_block2a1.PORTAADDR3 -address_a[3] => ram_block2a2.PORTAADDR3 -address_a[3] => ram_block2a3.PORTAADDR3 -address_a[3] => ram_block2a4.PORTAADDR3 -address_a[3] => ram_block2a5.PORTAADDR3 -address_a[3] => ram_block2a6.PORTAADDR3 -address_a[3] => ram_block2a7.PORTAADDR3 -address_a[4] => ram_block2a0.PORTAADDR4 -address_a[4] => ram_block2a1.PORTAADDR4 -address_a[4] => ram_block2a2.PORTAADDR4 -address_a[4] => ram_block2a3.PORTAADDR4 -address_a[4] => ram_block2a4.PORTAADDR4 -address_a[4] => ram_block2a5.PORTAADDR4 -address_a[4] => ram_block2a6.PORTAADDR4 -address_a[4] => ram_block2a7.PORTAADDR4 -address_a[5] => ram_block2a0.PORTAADDR5 -address_a[5] => ram_block2a1.PORTAADDR5 -address_a[5] => ram_block2a2.PORTAADDR5 -address_a[5] => ram_block2a3.PORTAADDR5 -address_a[5] => ram_block2a4.PORTAADDR5 -address_a[5] => ram_block2a5.PORTAADDR5 -address_a[5] => ram_block2a6.PORTAADDR5 -address_a[5] => ram_block2a7.PORTAADDR5 -address_b[0] => ram_block2a0.PORTBADDR -address_b[0] => ram_block2a1.PORTBADDR -address_b[0] => ram_block2a2.PORTBADDR -address_b[0] => ram_block2a3.PORTBADDR -address_b[0] => ram_block2a4.PORTBADDR -address_b[0] => ram_block2a5.PORTBADDR -address_b[0] => ram_block2a6.PORTBADDR -address_b[0] => ram_block2a7.PORTBADDR -address_b[1] => ram_block2a0.PORTBADDR1 -address_b[1] => ram_block2a1.PORTBADDR1 -address_b[1] => ram_block2a2.PORTBADDR1 -address_b[1] => ram_block2a3.PORTBADDR1 -address_b[1] => ram_block2a4.PORTBADDR1 -address_b[1] => ram_block2a5.PORTBADDR1 -address_b[1] => ram_block2a6.PORTBADDR1 -address_b[1] => ram_block2a7.PORTBADDR1 -address_b[2] => ram_block2a0.PORTBADDR2 -address_b[2] => ram_block2a1.PORTBADDR2 -address_b[2] => ram_block2a2.PORTBADDR2 -address_b[2] => ram_block2a3.PORTBADDR2 -address_b[2] => ram_block2a4.PORTBADDR2 -address_b[2] => ram_block2a5.PORTBADDR2 -address_b[2] => ram_block2a6.PORTBADDR2 -address_b[2] => ram_block2a7.PORTBADDR2 -address_b[3] => ram_block2a0.PORTBADDR3 -address_b[3] => ram_block2a1.PORTBADDR3 -address_b[3] => ram_block2a2.PORTBADDR3 -address_b[3] => ram_block2a3.PORTBADDR3 -address_b[3] => ram_block2a4.PORTBADDR3 -address_b[3] => ram_block2a5.PORTBADDR3 -address_b[3] => ram_block2a6.PORTBADDR3 -address_b[3] => ram_block2a7.PORTBADDR3 -address_b[4] => ram_block2a0.PORTBADDR4 -address_b[4] => ram_block2a1.PORTBADDR4 -address_b[4] => ram_block2a2.PORTBADDR4 -address_b[4] => ram_block2a3.PORTBADDR4 -address_b[4] => ram_block2a4.PORTBADDR4 -address_b[4] => ram_block2a5.PORTBADDR4 -address_b[4] => ram_block2a6.PORTBADDR4 -address_b[4] => ram_block2a7.PORTBADDR4 -address_b[5] => ram_block2a0.PORTBADDR5 -address_b[5] => ram_block2a1.PORTBADDR5 -address_b[5] => ram_block2a2.PORTBADDR5 -address_b[5] => ram_block2a3.PORTBADDR5 -address_b[5] => ram_block2a4.PORTBADDR5 -address_b[5] => ram_block2a5.PORTBADDR5 -address_b[5] => ram_block2a6.PORTBADDR5 -address_b[5] => ram_block2a7.PORTBADDR5 -clock0 => ram_block2a0.CLK0 -clock0 => ram_block2a1.CLK0 -clock0 => ram_block2a2.CLK0 -clock0 => ram_block2a3.CLK0 -clock0 => ram_block2a4.CLK0 -clock0 => ram_block2a5.CLK0 -clock0 => ram_block2a6.CLK0 -clock0 => ram_block2a7.CLK0 -clock1 => ram_block2a0.CLK1 -clock1 => ram_block2a1.CLK1 -clock1 => ram_block2a2.CLK1 -clock1 => ram_block2a3.CLK1 -clock1 => ram_block2a4.CLK1 -clock1 => ram_block2a5.CLK1 -clock1 => ram_block2a6.CLK1 -clock1 => ram_block2a7.CLK1 -clocken1 => ram_block2a0.ENA1 -clocken1 => ram_block2a1.ENA1 -clocken1 => ram_block2a2.ENA1 -clocken1 => ram_block2a3.ENA1 -clocken1 => ram_block2a4.ENA1 -clocken1 => ram_block2a5.ENA1 -clocken1 => ram_block2a6.ENA1 -clocken1 => ram_block2a7.ENA1 -data_a[0] => ram_block2a0.PORTADATAIN -data_a[1] => ram_block2a1.PORTADATAIN -data_a[2] => ram_block2a2.PORTADATAIN -data_a[3] => ram_block2a3.PORTADATAIN -data_a[4] => ram_block2a4.PORTADATAIN -data_a[5] => ram_block2a5.PORTADATAIN -data_a[6] => ram_block2a6.PORTADATAIN -data_a[7] => ram_block2a7.PORTADATAIN -q_b[0] <= ram_block2a0.PORTBDATAOUT -q_b[1] <= ram_block2a1.PORTBDATAOUT -q_b[2] <= ram_block2a2.PORTBDATAOUT -q_b[3] <= ram_block2a3.PORTBDATAOUT -q_b[4] <= ram_block2a4.PORTBDATAOUT -q_b[5] <= ram_block2a5.PORTBDATAOUT -q_b[6] <= ram_block2a6.PORTBDATAOUT -q_b[7] <= ram_block2a7.PORTBDATAOUT -wren_a => ram_block2a0.PORTAWE -wren_a => ram_block2a0.ENA0 -wren_a => ram_block2a1.PORTAWE -wren_a => ram_block2a1.ENA0 -wren_a => ram_block2a2.PORTAWE -wren_a => ram_block2a2.ENA0 -wren_a => ram_block2a3.PORTAWE -wren_a => ram_block2a3.ENA0 -wren_a => ram_block2a4.PORTAWE -wren_a => ram_block2a4.ENA0 -wren_a => ram_block2a5.PORTAWE -wren_a => ram_block2a5.ENA0 -wren_a => ram_block2a6.PORTAWE -wren_a => ram_block2a6.ENA0 -wren_a => ram_block2a7.PORTAWE -wren_a => ram_block2a7.ENA0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr -aclr => counter_reg_bit[5].IN0 -clock => counter_reg_bit[5].CLK -clock => counter_reg_bit[4].CLK -clock => counter_reg_bit[3].CLK -clock => counter_reg_bit[2].CLK -clock => counter_reg_bit[1].CLK -clock => counter_reg_bit[0].CLK -cnt_en => _.IN1 -q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE -q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE -q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE -q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE -q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE -q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE -sclr => _.IN0 -sclr => _.IN0 -sclr => _.IN0 - - -|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic -raw_tck => write_stalled.CLK -raw_tck => wdata[0].CLK -raw_tck => wdata[1].CLK -raw_tck => wdata[2].CLK -raw_tck => wdata[3].CLK -raw_tck => wdata[4].CLK -raw_tck => wdata[5].CLK -raw_tck => wdata[6].CLK -raw_tck => wdata[7].CLK -raw_tck => write.CLK -raw_tck => read.CLK -raw_tck => read_req.CLK -raw_tck => write_valid.CLK -raw_tck => count[0].CLK -raw_tck => count[1].CLK -raw_tck => count[2].CLK -raw_tck => count[3].CLK -raw_tck => count[4].CLK -raw_tck => count[5].CLK -raw_tck => count[6].CLK -raw_tck => count[7].CLK -raw_tck => count[8].CLK -raw_tck => count[9].CLK -raw_tck => state.CLK -raw_tck => user_saw_rvalid.CLK -raw_tck => td_shift[0].CLK -raw_tck => td_shift[1].CLK -raw_tck => td_shift[2].CLK -raw_tck => td_shift[3].CLK -raw_tck => td_shift[4].CLK -raw_tck => td_shift[5].CLK -raw_tck => td_shift[6].CLK -raw_tck => td_shift[7].CLK -raw_tck => td_shift[8].CLK -raw_tck => td_shift[9].CLK -raw_tck => td_shift[10].CLK -raw_tck => tck_t_dav.CLK -raw_tck => jupdate.CLK -raw_tck => tdo~reg0.CLK -tck => ~NO_FANOUT~ -tdi => td_shift.OUTPUTSELECT -tdi => count.OUTPUTSELECT -tdi => state.OUTPUTSELECT -tdi => wdata.DATAB -tdi => always0.IN1 -tdi => wdata.DATAB -tdi => td_shift.DATAB -rti => ~NO_FANOUT~ -shift => ~NO_FANOUT~ -update => ~NO_FANOUT~ -usr1 => always0.IN0 -clr => jupdate.ACLR -clr => tdo~reg0.ACLR -clr => write_stalled.ACLR -clr => wdata[0].ACLR -clr => wdata[1].ACLR -clr => wdata[2].ACLR -clr => wdata[3].ACLR -clr => wdata[4].ACLR -clr => wdata[5].ACLR -clr => wdata[6].ACLR -clr => wdata[7].ACLR -clr => write.ACLR -clr => read.ACLR -clr => read_req.ACLR -clr => write_valid.ACLR -clr => count[0].ACLR -clr => count[1].ACLR -clr => count[2].ACLR -clr => count[3].ACLR -clr => count[4].ACLR -clr => count[5].ACLR -clr => count[6].ACLR -clr => count[7].ACLR -clr => count[8].ACLR -clr => count[9].PRESET -clr => state.ACLR -clr => user_saw_rvalid.ACLR -clr => td_shift[0].ACLR -clr => td_shift[1].ACLR -clr => td_shift[2].ACLR -clr => td_shift[3].ACLR -clr => td_shift[4].ACLR -clr => td_shift[5].ACLR -clr => td_shift[6].ACLR -clr => td_shift[7].ACLR -clr => td_shift[8].ACLR -clr => td_shift[9].ACLR -clr => td_shift[10].ACLR -clr => tck_t_dav.ACLR -ena => always0.IN1 -ir_in[0] => Decoder1.IN0 -ir_in[0] => ir_out[0].DATAIN -tdo <= tdo~reg0.DB_MAX_OUTPUT_PORT_TYPE -irq <= -ir_out[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE -jtag_state_cdr => state.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => count.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_cdr => td_shift.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => count.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => td_shift.OUTPUTSELECT -jtag_state_sdr => write.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => wdata.OUTPUTSELECT -jtag_state_sdr => user_saw_rvalid.OUTPUTSELECT -jtag_state_sdr => read.OUTPUTSELECT -jtag_state_sdr => write_valid.OUTPUTSELECT -jtag_state_sdr => read_req.OUTPUTSELECT -jtag_state_sdr => write_stalled.OUTPUTSELECT -jtag_state_sdr => state.OUTPUTSELECT -jtag_state_udr => jupdate.OUTPUTSELECT -clk => t_pause~reg0.CLK -clk => t_ena~reg0.CLK -clk => rdata[0].CLK -clk => rdata[1].CLK -clk => rdata[2].CLK -clk => rdata[3].CLK -clk => rdata[4].CLK -clk => rdata[5].CLK -clk => rdata[6].CLK -clk => rdata[7].CLK -clk => rvalid.CLK -clk => rvalid0.CLK -clk => r_ena1.CLK -clk => jupdate2.CLK -clk => jupdate1.CLK -clk => write2.CLK -clk => write1.CLK -clk => read2.CLK -clk => read1.CLK -clk => rst2.CLK -clk => rst1.CLK -rst_n => t_pause~reg0.ACLR -rst_n => t_ena~reg0.ACLR -rst_n => rdata[0].ACLR -rst_n => rdata[1].ACLR -rst_n => rdata[2].ACLR -rst_n => rdata[3].ACLR -rst_n => rdata[4].ACLR -rst_n => rdata[5].ACLR -rst_n => rdata[6].ACLR -rst_n => rdata[7].ACLR -rst_n => rvalid.ACLR -rst_n => rvalid0.ACLR -rst_n => r_ena1.ACLR -rst_n => jupdate2.ACLR -rst_n => jupdate1.ACLR -rst_n => write2.ACLR -rst_n => write1.ACLR -rst_n => read2.ACLR -rst_n => read1.ACLR -rst_n => rst2.PRESET -rst_n => rst1.PRESET -r_ena <= r_ena.DB_MAX_OUTPUT_PORT_TYPE -r_val => r_ena.IN1 -r_dat[0] => rdata[0].DATAIN -r_dat[1] => rdata[1].DATAIN -r_dat[2] => rdata[2].DATAIN -r_dat[3] => rdata[3].DATAIN -r_dat[4] => rdata[4].DATAIN -r_dat[5] => rdata[5].DATAIN -r_dat[6] => rdata[6].DATAIN -r_dat[7] => rdata[7].DATAIN -t_dav => always2.IN1 -t_dav => tck_t_dav.DATAIN -t_ena <= t_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE -t_dat[0] <= t_dat[0].DB_MAX_OUTPUT_PORT_TYPE -t_dat[1] <= t_dat[1].DB_MAX_OUTPUT_PORT_TYPE -t_dat[2] <= t_dat[2].DB_MAX_OUTPUT_PORT_TYPE -t_dat[3] <= t_dat[3].DB_MAX_OUTPUT_PORT_TYPE -t_dat[4] <= t_dat[4].DB_MAX_OUTPUT_PORT_TYPE -t_dat[5] <= t_dat[5].DB_MAX_OUTPUT_PORT_TYPE -t_dat[6] <= t_dat[6].DB_MAX_OUTPUT_PORT_TYPE -t_dat[7] <= t_dat[7].DB_MAX_OUTPUT_PORT_TYPE -t_pause <= t_pause~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_LEDs:leds -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -clk => data_out[7].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -reset_n => data_out[7].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => data_out[7].DATAIN -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_LEDRs:ledrs -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -clk => data_out[7].CLK -clk => data_out[8].CLK -clk => data_out[9].CLK -clk => data_out[10].CLK -clk => data_out[11].CLK -clk => data_out[12].CLK -clk => data_out[13].CLK -clk => data_out[14].CLK -clk => data_out[15].CLK -clk => data_out[16].CLK -clk => data_out[17].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -reset_n => data_out[7].ACLR -reset_n => data_out[8].ACLR -reset_n => data_out[9].ACLR -reset_n => data_out[10].ACLR -reset_n => data_out[11].ACLR -reset_n => data_out[12].ACLR -reset_n => data_out[13].ACLR -reset_n => data_out[14].ACLR -reset_n => data_out[15].ACLR -reset_n => data_out[16].ACLR -reset_n => data_out[17].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => data_out[7].DATAIN -writedata[8] => data_out[8].DATAIN -writedata[9] => data_out[9].DATAIN -writedata[10] => data_out[10].DATAIN -writedata[11] => data_out[11].DATAIN -writedata[12] => data_out[12].DATAIN -writedata[13] => data_out[13].DATAIN -writedata[14] => data_out[14].DATAIN -writedata[15] => data_out[15].DATAIN -writedata[16] => data_out[16].DATAIN -writedata[17] => data_out[17].DATAIN -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE -out_port[8] <= data_out[8].DB_MAX_OUTPUT_PORT_TYPE -out_port[9] <= data_out[9].DB_MAX_OUTPUT_PORT_TYPE -out_port[10] <= data_out[10].DB_MAX_OUTPUT_PORT_TYPE -out_port[11] <= data_out[11].DB_MAX_OUTPUT_PORT_TYPE -out_port[12] <= data_out[12].DB_MAX_OUTPUT_PORT_TYPE -out_port[13] <= data_out[13].DB_MAX_OUTPUT_PORT_TYPE -out_port[14] <= data_out[14].DB_MAX_OUTPUT_PORT_TYPE -out_port[15] <= data_out[15].DB_MAX_OUTPUT_PORT_TYPE -out_port[16] <= data_out[16].DB_MAX_OUTPUT_PORT_TYPE -out_port[17] <= data_out[17].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_switches:switches -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -clk => readdata[0]~reg0.CLK -clk => readdata[1]~reg0.CLK -clk => readdata[2]~reg0.CLK -clk => readdata[3]~reg0.CLK -clk => readdata[4]~reg0.CLK -clk => readdata[5]~reg0.CLK -clk => readdata[6]~reg0.CLK -clk => readdata[7]~reg0.CLK -clk => readdata[8]~reg0.CLK -clk => readdata[9]~reg0.CLK -clk => readdata[10]~reg0.CLK -clk => readdata[11]~reg0.CLK -clk => readdata[12]~reg0.CLK -clk => readdata[13]~reg0.CLK -clk => readdata[14]~reg0.CLK -clk => readdata[15]~reg0.CLK -clk => readdata[16]~reg0.CLK -clk => readdata[17]~reg0.CLK -clk => readdata[18]~reg0.CLK -clk => readdata[19]~reg0.CLK -clk => readdata[20]~reg0.CLK -clk => readdata[21]~reg0.CLK -clk => readdata[22]~reg0.CLK -clk => readdata[23]~reg0.CLK -clk => readdata[24]~reg0.CLK -clk => readdata[25]~reg0.CLK -clk => readdata[26]~reg0.CLK -clk => readdata[27]~reg0.CLK -clk => readdata[28]~reg0.CLK -clk => readdata[29]~reg0.CLK -clk => readdata[30]~reg0.CLK -clk => readdata[31]~reg0.CLK -in_port[0] => read_mux_out[0].IN1 -in_port[1] => read_mux_out[1].IN1 -in_port[2] => read_mux_out[2].IN1 -in_port[3] => read_mux_out[3].IN1 -in_port[4] => read_mux_out[4].IN1 -in_port[5] => read_mux_out[5].IN1 -in_port[6] => read_mux_out[6].IN1 -in_port[7] => read_mux_out[7].IN1 -in_port[8] => read_mux_out[8].IN1 -in_port[9] => read_mux_out[9].IN1 -in_port[10] => read_mux_out[10].IN1 -in_port[11] => read_mux_out[11].IN1 -in_port[12] => read_mux_out[12].IN1 -in_port[13] => read_mux_out[13].IN1 -in_port[14] => read_mux_out[14].IN1 -in_port[15] => read_mux_out[15].IN1 -in_port[16] => read_mux_out[16].IN1 -in_port[17] => read_mux_out[17].IN1 -reset_n => readdata[0]~reg0.ACLR -reset_n => readdata[1]~reg0.ACLR -reset_n => readdata[2]~reg0.ACLR -reset_n => readdata[3]~reg0.ACLR -reset_n => readdata[4]~reg0.ACLR -reset_n => readdata[5]~reg0.ACLR -reset_n => readdata[6]~reg0.ACLR -reset_n => readdata[7]~reg0.ACLR -reset_n => readdata[8]~reg0.ACLR -reset_n => readdata[9]~reg0.ACLR -reset_n => readdata[10]~reg0.ACLR -reset_n => readdata[11]~reg0.ACLR -reset_n => readdata[12]~reg0.ACLR -reset_n => readdata[13]~reg0.ACLR -reset_n => readdata[14]~reg0.ACLR -reset_n => readdata[15]~reg0.ACLR -reset_n => readdata[16]~reg0.ACLR -reset_n => readdata[17]~reg0.ACLR -reset_n => readdata[18]~reg0.ACLR -reset_n => readdata[19]~reg0.ACLR -reset_n => readdata[20]~reg0.ACLR -reset_n => readdata[21]~reg0.ACLR -reset_n => readdata[22]~reg0.ACLR -reset_n => readdata[23]~reg0.ACLR -reset_n => readdata[24]~reg0.ACLR -reset_n => readdata[25]~reg0.ACLR -reset_n => readdata[26]~reg0.ACLR -reset_n => readdata[27]~reg0.ACLR -reset_n => readdata[28]~reg0.ACLR -reset_n => readdata[29]~reg0.ACLR -reset_n => readdata[30]~reg0.ACLR -reset_n => readdata[31]~reg0.ACLR -readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_push_switches:push_switches -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -clk => readdata[0]~reg0.CLK -clk => readdata[1]~reg0.CLK -clk => readdata[2]~reg0.CLK -clk => readdata[3]~reg0.CLK -clk => readdata[4]~reg0.CLK -clk => readdata[5]~reg0.CLK -clk => readdata[6]~reg0.CLK -clk => readdata[7]~reg0.CLK -clk => readdata[8]~reg0.CLK -clk => readdata[9]~reg0.CLK -clk => readdata[10]~reg0.CLK -clk => readdata[11]~reg0.CLK -clk => readdata[12]~reg0.CLK -clk => readdata[13]~reg0.CLK -clk => readdata[14]~reg0.CLK -clk => readdata[15]~reg0.CLK -clk => readdata[16]~reg0.CLK -clk => readdata[17]~reg0.CLK -clk => readdata[18]~reg0.CLK -clk => readdata[19]~reg0.CLK -clk => readdata[20]~reg0.CLK -clk => readdata[21]~reg0.CLK -clk => readdata[22]~reg0.CLK -clk => readdata[23]~reg0.CLK -clk => readdata[24]~reg0.CLK -clk => readdata[25]~reg0.CLK -clk => readdata[26]~reg0.CLK -clk => readdata[27]~reg0.CLK -clk => readdata[28]~reg0.CLK -clk => readdata[29]~reg0.CLK -clk => readdata[30]~reg0.CLK -clk => readdata[31]~reg0.CLK -in_port[0] => read_mux_out[0].IN1 -in_port[1] => read_mux_out[1].IN1 -in_port[2] => read_mux_out[2].IN1 -reset_n => readdata[0]~reg0.ACLR -reset_n => readdata[1]~reg0.ACLR -reset_n => readdata[2]~reg0.ACLR -reset_n => readdata[3]~reg0.ACLR -reset_n => readdata[4]~reg0.ACLR -reset_n => readdata[5]~reg0.ACLR -reset_n => readdata[6]~reg0.ACLR -reset_n => readdata[7]~reg0.ACLR -reset_n => readdata[8]~reg0.ACLR -reset_n => readdata[9]~reg0.ACLR -reset_n => readdata[10]~reg0.ACLR -reset_n => readdata[11]~reg0.ACLR -reset_n => readdata[12]~reg0.ACLR -reset_n => readdata[13]~reg0.ACLR -reset_n => readdata[14]~reg0.ACLR -reset_n => readdata[15]~reg0.ACLR -reset_n => readdata[16]~reg0.ACLR -reset_n => readdata[17]~reg0.ACLR -reset_n => readdata[18]~reg0.ACLR -reset_n => readdata[19]~reg0.ACLR -reset_n => readdata[20]~reg0.ACLR -reset_n => readdata[21]~reg0.ACLR -reset_n => readdata[22]~reg0.ACLR -reset_n => readdata[23]~reg0.ACLR -reset_n => readdata[24]~reg0.ACLR -reset_n => readdata[25]~reg0.ACLR -reset_n => readdata[26]~reg0.ACLR -reset_n => readdata[27]~reg0.ACLR -reset_n => readdata[28]~reg0.ACLR -reset_n => readdata[29]~reg0.ACLR -reset_n => readdata[30]~reg0.ACLR -reset_n => readdata[31]~reg0.ACLR -readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_hex0:hex0 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex1 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex2 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex3 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex4 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex5 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex6 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_hex0:hex7 -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out[0].CLK -clk => data_out[1].CLK -clk => data_out[2].CLK -clk => data_out[3].CLK -clk => data_out[4].CLK -clk => data_out[5].CLK -clk => data_out[6].CLK -reset_n => data_out[0].ACLR -reset_n => data_out[1].ACLR -reset_n => data_out[2].ACLR -reset_n => data_out[3].ACLR -reset_n => data_out[4].ACLR -reset_n => data_out[5].ACLR -reset_n => data_out[6].ACLR -write_n => always0.IN1 -writedata[0] => data_out[0].DATAIN -writedata[1] => data_out[1].DATAIN -writedata[2] => data_out[2].DATAIN -writedata[3] => data_out[3].DATAIN -writedata[4] => data_out[4].DATAIN -writedata[5] => data_out[5].DATAIN -writedata[6] => data_out[6].DATAIN -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE -out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE -out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE -out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE -out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE -out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE -out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 -address[0] => LCD_RW.DATAIN -address[0] => LCD_data[7].OE -address[0] => LCD_data[6].OE -address[0] => LCD_data[5].OE -address[0] => LCD_data[4].OE -address[0] => LCD_data[3].OE -address[0] => LCD_data[2].OE -address[0] => LCD_data[1].OE -address[0] => LCD_data[0].OE -address[1] => LCD_RS.DATAIN -begintransfer => ~NO_FANOUT~ -clk => ~NO_FANOUT~ -read => LCD_E.IN0 -reset_n => ~NO_FANOUT~ -write => LCD_E.IN1 -writedata[0] => LCD_data[0].DATAIN -writedata[1] => LCD_data[1].DATAIN -writedata[2] => LCD_data[2].DATAIN -writedata[3] => LCD_data[3].DATAIN -writedata[4] => LCD_data[4].DATAIN -writedata[5] => LCD_data[5].DATAIN -writedata[6] => LCD_data[6].DATAIN -writedata[7] => LCD_data[7].DATAIN -LCD_E <= LCD_E.DB_MAX_OUTPUT_PORT_TYPE -LCD_RS <= address[1].DB_MAX_OUTPUT_PORT_TYPE -LCD_RW <= address[0].DB_MAX_OUTPUT_PORT_TYPE -LCD_data[0] <> LCD_data[0] -LCD_data[1] <> LCD_data[1] -LCD_data[2] <> LCD_data[2] -LCD_data[3] <> LCD_data[3] -LCD_data[4] <> LCD_data[4] -LCD_data[5] <> LCD_data[5] -LCD_data[6] <> LCD_data[6] -LCD_data[7] <> LCD_data[7] -readdata[0] <= readdata[0].DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= readdata[1].DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= readdata[2].DB_MAX_OUTPUT_PORT_TYPE -readdata[3] <= readdata[3].DB_MAX_OUTPUT_PORT_TYPE -readdata[4] <= readdata[4].DB_MAX_OUTPUT_PORT_TYPE -readdata[5] <= readdata[5].DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= readdata[6].DB_MAX_OUTPUT_PORT_TYPE -readdata[7] <= readdata[7].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_lcd_on:lcd_on -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out.CLK -reset_n => data_out.ACLR -write_n => always0.IN1 -writedata[0] => data_out.DATAIN -writedata[1] => ~NO_FANOUT~ -writedata[2] => ~NO_FANOUT~ -writedata[3] => ~NO_FANOUT~ -writedata[4] => ~NO_FANOUT~ -writedata[5] => ~NO_FANOUT~ -writedata[6] => ~NO_FANOUT~ -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= -readdata[2] <= -readdata[3] <= -readdata[4] <= -readdata[5] <= -readdata[6] <= -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon -address[0] => Equal0.IN31 -address[1] => Equal0.IN30 -chipselect => always0.IN0 -clk => data_out.CLK -reset_n => data_out.ACLR -write_n => always0.IN1 -writedata[0] => data_out.DATAIN -writedata[1] => ~NO_FANOUT~ -writedata[2] => ~NO_FANOUT~ -writedata[3] => ~NO_FANOUT~ -writedata[4] => ~NO_FANOUT~ -writedata[5] => ~NO_FANOUT~ -writedata[6] => ~NO_FANOUT~ -writedata[7] => ~NO_FANOUT~ -writedata[8] => ~NO_FANOUT~ -writedata[9] => ~NO_FANOUT~ -writedata[10] => ~NO_FANOUT~ -writedata[11] => ~NO_FANOUT~ -writedata[12] => ~NO_FANOUT~ -writedata[13] => ~NO_FANOUT~ -writedata[14] => ~NO_FANOUT~ -writedata[15] => ~NO_FANOUT~ -writedata[16] => ~NO_FANOUT~ -writedata[17] => ~NO_FANOUT~ -writedata[18] => ~NO_FANOUT~ -writedata[19] => ~NO_FANOUT~ -writedata[20] => ~NO_FANOUT~ -writedata[21] => ~NO_FANOUT~ -writedata[22] => ~NO_FANOUT~ -writedata[23] => ~NO_FANOUT~ -writedata[24] => ~NO_FANOUT~ -writedata[25] => ~NO_FANOUT~ -writedata[26] => ~NO_FANOUT~ -writedata[27] => ~NO_FANOUT~ -writedata[28] => ~NO_FANOUT~ -writedata[29] => ~NO_FANOUT~ -writedata[30] => ~NO_FANOUT~ -writedata[31] => ~NO_FANOUT~ -out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= -readdata[2] <= -readdata[3] <= -readdata[4] <= -readdata[5] <= -readdata[6] <= -readdata[7] <= -readdata[8] <= -readdata[9] <= -readdata[10] <= -readdata[11] <= -readdata[12] <= -readdata[13] <= -readdata[14] <= -readdata[15] <= -readdata[16] <= -readdata[17] <= -readdata[18] <= -readdata[19] <= -readdata[20] <= -readdata[21] <= -readdata[22] <= -readdata[23] <= -readdata[24] <= -readdata[25] <= -readdata[26] <= -readdata[27] <= -readdata[28] <= -readdata[29] <= -readdata[30] <= -readdata[31] <= - - -|lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator -clk => read_accepted.CLK -reset => read_accepted.ACLR -uav_write <= -uav_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE -uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE -uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -uav_burstcount[0] <= -uav_burstcount[1] <= -uav_burstcount[2] <= -uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] => av_readdata[0].DATAIN -uav_readdata[1] => av_readdata[1].DATAIN -uav_readdata[2] => av_readdata[2].DATAIN -uav_readdata[3] => av_readdata[3].DATAIN -uav_readdata[4] => av_readdata[4].DATAIN -uav_readdata[5] => av_readdata[5].DATAIN -uav_readdata[6] => av_readdata[6].DATAIN -uav_readdata[7] => av_readdata[7].DATAIN -uav_readdata[8] => av_readdata[8].DATAIN -uav_readdata[9] => av_readdata[9].DATAIN -uav_readdata[10] => av_readdata[10].DATAIN -uav_readdata[11] => av_readdata[11].DATAIN -uav_readdata[12] => av_readdata[12].DATAIN -uav_readdata[13] => av_readdata[13].DATAIN -uav_readdata[14] => av_readdata[14].DATAIN -uav_readdata[15] => av_readdata[15].DATAIN -uav_readdata[16] => av_readdata[16].DATAIN -uav_readdata[17] => av_readdata[17].DATAIN -uav_readdata[18] => av_readdata[18].DATAIN -uav_readdata[19] => av_readdata[19].DATAIN -uav_readdata[20] => av_readdata[20].DATAIN -uav_readdata[21] => av_readdata[21].DATAIN -uav_readdata[22] => av_readdata[22].DATAIN -uav_readdata[23] => av_readdata[23].DATAIN -uav_readdata[24] => av_readdata[24].DATAIN -uav_readdata[25] => av_readdata[25].DATAIN -uav_readdata[26] => av_readdata[26].DATAIN -uav_readdata[27] => av_readdata[27].DATAIN -uav_readdata[28] => av_readdata[28].DATAIN -uav_readdata[29] => av_readdata[29].DATAIN -uav_readdata[30] => av_readdata[30].DATAIN -uav_readdata[31] => av_readdata[31].DATAIN -uav_readdatavalid => always5.IN1 -uav_readdatavalid => av_readdatavalid.DATAIN -uav_readdatavalid => av_waitrequest.DATAB -uav_waitrequest => av_waitrequest.DATAA -uav_waitrequest => read_accepted.IN0 -uav_response[0] => ~NO_FANOUT~ -uav_response[1] => ~NO_FANOUT~ -uav_writeresponserequest <= -uav_writeresponsevalid => ~NO_FANOUT~ -av_write => ~NO_FANOUT~ -av_read => read_accepted.IN1 -av_read => av_waitrequest.OUTPUTSELECT -av_read => uav_read.IN1 -av_address[0] => uav_address[0].DATAIN -av_address[1] => uav_address[1].DATAIN -av_address[2] => uav_address[2].DATAIN -av_address[3] => uav_address[3].DATAIN -av_address[4] => uav_address[4].DATAIN -av_address[5] => uav_address[5].DATAIN -av_address[6] => uav_address[6].DATAIN -av_address[7] => uav_address[7].DATAIN -av_address[8] => uav_address[8].DATAIN -av_address[9] => uav_address[9].DATAIN -av_address[10] => uav_address[10].DATAIN -av_address[11] => uav_address[11].DATAIN -av_address[12] => uav_address[12].DATAIN -av_address[13] => uav_address[13].DATAIN -av_address[14] => uav_address[14].DATAIN -av_address[15] => uav_address[15].DATAIN -av_address[16] => uav_address[16].DATAIN -av_address[17] => uav_address[17].DATAIN -av_address[18] => uav_address[18].DATAIN -av_byteenable[0] => uav_byteenable[0].DATAIN -av_byteenable[1] => uav_byteenable[1].DATAIN -av_byteenable[2] => uav_byteenable[2].DATAIN -av_byteenable[3] => uav_byteenable[3].DATAIN -av_burstcount[0] => ~NO_FANOUT~ -av_writedata[0] => uav_writedata[0].DATAIN -av_writedata[1] => uav_writedata[1].DATAIN -av_writedata[2] => uav_writedata[2].DATAIN -av_writedata[3] => uav_writedata[3].DATAIN -av_writedata[4] => uav_writedata[4].DATAIN -av_writedata[5] => uav_writedata[5].DATAIN -av_writedata[6] => uav_writedata[6].DATAIN -av_writedata[7] => uav_writedata[7].DATAIN -av_writedata[8] => uav_writedata[8].DATAIN -av_writedata[9] => uav_writedata[9].DATAIN -av_writedata[10] => uav_writedata[10].DATAIN -av_writedata[11] => uav_writedata[11].DATAIN -av_writedata[12] => uav_writedata[12].DATAIN -av_writedata[13] => uav_writedata[13].DATAIN -av_writedata[14] => uav_writedata[14].DATAIN -av_writedata[15] => uav_writedata[15].DATAIN -av_writedata[16] => uav_writedata[16].DATAIN -av_writedata[17] => uav_writedata[17].DATAIN -av_writedata[18] => uav_writedata[18].DATAIN -av_writedata[19] => uav_writedata[19].DATAIN -av_writedata[20] => uav_writedata[20].DATAIN -av_writedata[21] => uav_writedata[21].DATAIN -av_writedata[22] => uav_writedata[22].DATAIN -av_writedata[23] => uav_writedata[23].DATAIN -av_writedata[24] => uav_writedata[24].DATAIN -av_writedata[25] => uav_writedata[25].DATAIN -av_writedata[26] => uav_writedata[26].DATAIN -av_writedata[27] => uav_writedata[27].DATAIN -av_writedata[28] => uav_writedata[28].DATAIN -av_writedata[29] => uav_writedata[29].DATAIN -av_writedata[30] => uav_writedata[30].DATAIN -av_writedata[31] => uav_writedata[31].DATAIN -av_begintransfer => ~NO_FANOUT~ -av_beginbursttransfer => ~NO_FANOUT~ -av_lock => uav_lock.DATAIN -av_chipselect => ~NO_FANOUT~ -av_debugaccess => uav_debugaccess.DATAIN -av_clken => uav_clken.DATAIN -av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_response[0] <= -av_response[1] <= -av_writeresponserequest => ~NO_FANOUT~ -av_writeresponsevalid <= - - -|lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator -clk => end_begintransfer.CLK -clk => write_accepted.CLK -clk => read_accepted.CLK -reset => end_begintransfer.ACLR -reset => write_accepted.ACLR -reset => read_accepted.ACLR -uav_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -uav_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE -uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE -uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -uav_burstcount[0] <= -uav_burstcount[1] <= -uav_burstcount[2] <= -uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] => av_readdata[0].DATAIN -uav_readdata[1] => av_readdata[1].DATAIN -uav_readdata[2] => av_readdata[2].DATAIN -uav_readdata[3] => av_readdata[3].DATAIN -uav_readdata[4] => av_readdata[4].DATAIN -uav_readdata[5] => av_readdata[5].DATAIN -uav_readdata[6] => av_readdata[6].DATAIN -uav_readdata[7] => av_readdata[7].DATAIN -uav_readdata[8] => av_readdata[8].DATAIN -uav_readdata[9] => av_readdata[9].DATAIN -uav_readdata[10] => av_readdata[10].DATAIN -uav_readdata[11] => av_readdata[11].DATAIN -uav_readdata[12] => av_readdata[12].DATAIN -uav_readdata[13] => av_readdata[13].DATAIN -uav_readdata[14] => av_readdata[14].DATAIN -uav_readdata[15] => av_readdata[15].DATAIN -uav_readdata[16] => av_readdata[16].DATAIN -uav_readdata[17] => av_readdata[17].DATAIN -uav_readdata[18] => av_readdata[18].DATAIN -uav_readdata[19] => av_readdata[19].DATAIN -uav_readdata[20] => av_readdata[20].DATAIN -uav_readdata[21] => av_readdata[21].DATAIN -uav_readdata[22] => av_readdata[22].DATAIN -uav_readdata[23] => av_readdata[23].DATAIN -uav_readdata[24] => av_readdata[24].DATAIN -uav_readdata[25] => av_readdata[25].DATAIN -uav_readdata[26] => av_readdata[26].DATAIN -uav_readdata[27] => av_readdata[27].DATAIN -uav_readdata[28] => av_readdata[28].DATAIN -uav_readdata[29] => av_readdata[29].DATAIN -uav_readdata[30] => av_readdata[30].DATAIN -uav_readdata[31] => av_readdata[31].DATAIN -uav_readdatavalid => always5.IN1 -uav_readdatavalid => av_readdatavalid.DATAIN -uav_readdatavalid => av_waitrequest.DATAB -uav_waitrequest => av_waitrequest.IN1 -uav_waitrequest => always10.IN1 -uav_waitrequest => end_begintransfer.OUTPUTSELECT -uav_waitrequest => read_accepted.IN0 -uav_waitrequest => write_accepted.IN1 -uav_response[0] => ~NO_FANOUT~ -uav_response[1] => ~NO_FANOUT~ -uav_writeresponserequest <= -uav_writeresponsevalid => ~NO_FANOUT~ -av_write => av_waitrequest.OUTPUTSELECT -av_write => uav_write.IN1 -av_read => read_accepted.IN1 -av_read => av_waitrequest.OUTPUTSELECT -av_read => uav_read.IN1 -av_address[0] => uav_address[0].DATAIN -av_address[1] => uav_address[1].DATAIN -av_address[2] => uav_address[2].DATAIN -av_address[3] => uav_address[3].DATAIN -av_address[4] => uav_address[4].DATAIN -av_address[5] => uav_address[5].DATAIN -av_address[6] => uav_address[6].DATAIN -av_address[7] => uav_address[7].DATAIN -av_address[8] => uav_address[8].DATAIN -av_address[9] => uav_address[9].DATAIN -av_address[10] => uav_address[10].DATAIN -av_address[11] => uav_address[11].DATAIN -av_address[12] => uav_address[12].DATAIN -av_address[13] => uav_address[13].DATAIN -av_address[14] => uav_address[14].DATAIN -av_address[15] => uav_address[15].DATAIN -av_address[16] => uav_address[16].DATAIN -av_address[17] => uav_address[17].DATAIN -av_address[18] => uav_address[18].DATAIN -av_byteenable[0] => uav_byteenable[0].DATAIN -av_byteenable[1] => uav_byteenable[1].DATAIN -av_byteenable[2] => uav_byteenable[2].DATAIN -av_byteenable[3] => uav_byteenable[3].DATAIN -av_burstcount[0] => ~NO_FANOUT~ -av_writedata[0] => uav_writedata[0].DATAIN -av_writedata[1] => uav_writedata[1].DATAIN -av_writedata[2] => uav_writedata[2].DATAIN -av_writedata[3] => uav_writedata[3].DATAIN -av_writedata[4] => uav_writedata[4].DATAIN -av_writedata[5] => uav_writedata[5].DATAIN -av_writedata[6] => uav_writedata[6].DATAIN -av_writedata[7] => uav_writedata[7].DATAIN -av_writedata[8] => uav_writedata[8].DATAIN -av_writedata[9] => uav_writedata[9].DATAIN -av_writedata[10] => uav_writedata[10].DATAIN -av_writedata[11] => uav_writedata[11].DATAIN -av_writedata[12] => uav_writedata[12].DATAIN -av_writedata[13] => uav_writedata[13].DATAIN -av_writedata[14] => uav_writedata[14].DATAIN -av_writedata[15] => uav_writedata[15].DATAIN -av_writedata[16] => uav_writedata[16].DATAIN -av_writedata[17] => uav_writedata[17].DATAIN -av_writedata[18] => uav_writedata[18].DATAIN -av_writedata[19] => uav_writedata[19].DATAIN -av_writedata[20] => uav_writedata[20].DATAIN -av_writedata[21] => uav_writedata[21].DATAIN -av_writedata[22] => uav_writedata[22].DATAIN -av_writedata[23] => uav_writedata[23].DATAIN -av_writedata[24] => uav_writedata[24].DATAIN -av_writedata[25] => uav_writedata[25].DATAIN -av_writedata[26] => uav_writedata[26].DATAIN -av_writedata[27] => uav_writedata[27].DATAIN -av_writedata[28] => uav_writedata[28].DATAIN -av_writedata[29] => uav_writedata[29].DATAIN -av_writedata[30] => uav_writedata[30].DATAIN -av_writedata[31] => uav_writedata[31].DATAIN -av_begintransfer => ~NO_FANOUT~ -av_beginbursttransfer => ~NO_FANOUT~ -av_lock => uav_lock.DATAIN -av_chipselect => ~NO_FANOUT~ -av_debugaccess => uav_debugaccess.DATAIN -av_clken => uav_clken.DATAIN -av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_response[0] <= -av_response[1] <= -av_writeresponserequest => ~NO_FANOUT~ -av_writeresponsevalid <= - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => av_address[2].DATAIN -uav_address[5] => av_address[3].DATAIN -uav_address[6] => av_address[4].DATAIN -uav_address[7] => av_address[5].DATAIN -uav_address[8] => av_address[6].DATAIN -uav_address[9] => av_address[7].DATAIN -uav_address[10] => av_address[8].DATAIN -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_write => av_write.DATAIN -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_read => av_read.DATAIN -uav_burstcount[0] => Equal0.IN3 -uav_burstcount[1] => Equal0.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal0.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => av_writebyteenable.IN1 -uav_byteenable[1] => av_byteenable[1].DATAIN -uav_byteenable[2] => av_writebyteenable.IN1 -uav_byteenable[2] => av_byteenable[2].DATAIN -uav_byteenable[3] => av_writebyteenable.IN1 -uav_byteenable[3] => av_byteenable[3].DATAIN -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE -av_address[3] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE -av_address[4] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE -av_address[5] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE -av_address[6] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE -av_address[7] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE -av_address[8] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => always18.IN1 -av_waitrequest => end_begintransfer.OUTPUTSELECT -av_waitrequest => uav_waitrequest.DATAIN -av_waitrequest => read_latency_shift_reg.IN1 -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => waitrequest_reset_override.CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => waitrequest_reset_override.PRESET -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => av_address[2].DATAIN -uav_address[5] => av_address[3].DATAIN -uav_address[6] => av_address[4].DATAIN -uav_address[7] => av_address[5].DATAIN -uav_address[8] => av_address[6].DATAIN -uav_address[9] => av_address[7].DATAIN -uav_address[10] => av_address[8].DATAIN -uav_address[11] => av_address[9].DATAIN -uav_address[12] => av_address[10].DATAIN -uav_address[13] => av_address[11].DATAIN -uav_address[14] => av_address[12].DATAIN -uav_address[15] => av_address[13].DATAIN -uav_address[16] => av_address[14].DATAIN -uav_address[17] => av_address[15].DATAIN -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_writebyteenable.IN0 -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_write => av_write.DATAIN -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_read => av_read.DATAIN -uav_read => av_outputenable_pre.DATAIN -uav_burstcount[0] => Equal0.IN3 -uav_burstcount[1] => Equal0.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal0.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => av_writebyteenable.IN1 -uav_byteenable[1] => av_byteenable[1].DATAIN -uav_byteenable[2] => av_writebyteenable.IN1 -uav_byteenable[2] => av_byteenable[2].DATAIN -uav_byteenable[3] => av_writebyteenable.IN1 -uav_byteenable[3] => av_byteenable[3].DATAIN -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= waitrequest_reset_override.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE -av_address[3] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE -av_address[4] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE -av_address[5] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE -av_address[6] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE -av_address[7] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE -av_address[8] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE -av_address[9] <= uav_address[11].DB_MAX_OUTPUT_PORT_TYPE -av_address[10] <= uav_address[12].DB_MAX_OUTPUT_PORT_TYPE -av_address[11] <= uav_address[13].DB_MAX_OUTPUT_PORT_TYPE -av_address[12] <= uav_address[14].DB_MAX_OUTPUT_PORT_TYPE -av_address[13] <= uav_address[15].DB_MAX_OUTPUT_PORT_TYPE -av_address[14] <= uav_address[16].DB_MAX_OUTPUT_PORT_TYPE -av_address[15] <= uav_address[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => uav_readdata[0].DATAIN -av_readdata[1] => uav_readdata[1].DATAIN -av_readdata[2] => uav_readdata[2].DATAIN -av_readdata[3] => uav_readdata[3].DATAIN -av_readdata[4] => uav_readdata[4].DATAIN -av_readdata[5] => uav_readdata[5].DATAIN -av_readdata[6] => uav_readdata[6].DATAIN -av_readdata[7] => uav_readdata[7].DATAIN -av_readdata[8] => uav_readdata[8].DATAIN -av_readdata[9] => uav_readdata[9].DATAIN -av_readdata[10] => uav_readdata[10].DATAIN -av_readdata[11] => uav_readdata[11].DATAIN -av_readdata[12] => uav_readdata[12].DATAIN -av_readdata[13] => uav_readdata[13].DATAIN -av_readdata[14] => uav_readdata[14].DATAIN -av_readdata[15] => uav_readdata[15].DATAIN -av_readdata[16] => uav_readdata[16].DATAIN -av_readdata[17] => uav_readdata[17].DATAIN -av_readdata[18] => uav_readdata[18].DATAIN -av_readdata[19] => uav_readdata[19].DATAIN -av_readdata[20] => uav_readdata[20].DATAIN -av_readdata[21] => uav_readdata[21].DATAIN -av_readdata[22] => uav_readdata[22].DATAIN -av_readdata[23] => uav_readdata[23].DATAIN -av_readdata[24] => uav_readdata[24].DATAIN -av_readdata[25] => uav_readdata[25].DATAIN -av_readdata[26] => uav_readdata[26].DATAIN -av_readdata[27] => uav_readdata[27].DATAIN -av_readdata[28] => uav_readdata[28].DATAIN -av_readdata[29] => uav_readdata[29].DATAIN -av_readdata[30] => uav_readdata[30].DATAIN -av_readdata[31] => uav_readdata[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => ~NO_FANOUT~ -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_write => av_write.DATAIN -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_read => av_read.DATAIN -uav_burstcount[0] => Equal0.IN3 -uav_burstcount[1] => Equal0.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal0.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => always18.IN1 -av_waitrequest => end_begintransfer.OUTPUTSELECT -av_waitrequest => uav_waitrequest.DATAIN -av_waitrequest => read_latency_shift_reg.IN1 -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -clk => wait_latency_counter[2].CLK -clk => wait_latency_counter[3].CLK -clk => wait_latency_counter[4].CLK -clk => wait_latency_counter[5].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -reset => wait_latency_counter[2].ACLR -reset => wait_latency_counter[3].ACLR -reset => wait_latency_counter[4].ACLR -reset => wait_latency_counter[5].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => ~NO_FANOUT~ -uav_writedata[9] => ~NO_FANOUT~ -uav_writedata[10] => ~NO_FANOUT~ -uav_writedata[11] => ~NO_FANOUT~ -uav_writedata[12] => ~NO_FANOUT~ -uav_writedata[13] => ~NO_FANOUT~ -uav_writedata[14] => ~NO_FANOUT~ -uav_writedata[15] => ~NO_FANOUT~ -uav_writedata[16] => ~NO_FANOUT~ -uav_writedata[17] => ~NO_FANOUT~ -uav_writedata[18] => ~NO_FANOUT~ -uav_writedata[19] => ~NO_FANOUT~ -uav_writedata[20] => ~NO_FANOUT~ -uav_writedata[21] => ~NO_FANOUT~ -uav_writedata[22] => ~NO_FANOUT~ -uav_writedata[23] => ~NO_FANOUT~ -uav_writedata[24] => ~NO_FANOUT~ -uav_writedata[25] => ~NO_FANOUT~ -uav_writedata[26] => ~NO_FANOUT~ -uav_writedata[27] => ~NO_FANOUT~ -uav_writedata[28] => ~NO_FANOUT~ -uav_writedata[29] => ~NO_FANOUT~ -uav_writedata[30] => ~NO_FANOUT~ -uav_writedata[31] => ~NO_FANOUT~ -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= -uav_readdata[9] <= -uav_readdata[10] <= -uav_readdata[11] <= -uav_readdata[12] <= -uav_readdata[13] <= -uav_readdata[14] <= -uav_readdata[15] <= -uav_readdata[16] <= -uav_readdata[17] <= -uav_readdata[18] <= -uav_readdata[19] <= -uav_readdata[20] <= -uav_readdata[21] <= -uav_readdata[22] <= -uav_readdata[23] <= -uav_readdata[24] <= -uav_readdata[25] <= -uav_readdata[26] <= -uav_readdata[27] <= -uav_readdata[28] <= -uav_readdata[29] <= -uav_readdata[30] <= -uav_readdata[31] <= -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator -clk => in_transfer.CLK -clk => end_beginbursttransfer.CLK -clk => end_begintransfer.CLK -clk => av_chipselect_pre.CLK -clk => av_outputenable_pre.CLK -clk => read_latency_shift_reg[0].CLK -clk => av_readdata_pre[0].CLK -clk => av_readdata_pre[1].CLK -clk => av_readdata_pre[2].CLK -clk => av_readdata_pre[3].CLK -clk => av_readdata_pre[4].CLK -clk => av_readdata_pre[5].CLK -clk => av_readdata_pre[6].CLK -clk => av_readdata_pre[7].CLK -clk => av_readdata_pre[8].CLK -clk => av_readdata_pre[9].CLK -clk => av_readdata_pre[10].CLK -clk => av_readdata_pre[11].CLK -clk => av_readdata_pre[12].CLK -clk => av_readdata_pre[13].CLK -clk => av_readdata_pre[14].CLK -clk => av_readdata_pre[15].CLK -clk => av_readdata_pre[16].CLK -clk => av_readdata_pre[17].CLK -clk => av_readdata_pre[18].CLK -clk => av_readdata_pre[19].CLK -clk => av_readdata_pre[20].CLK -clk => av_readdata_pre[21].CLK -clk => av_readdata_pre[22].CLK -clk => av_readdata_pre[23].CLK -clk => av_readdata_pre[24].CLK -clk => av_readdata_pre[25].CLK -clk => av_readdata_pre[26].CLK -clk => av_readdata_pre[27].CLK -clk => av_readdata_pre[28].CLK -clk => av_readdata_pre[29].CLK -clk => av_readdata_pre[30].CLK -clk => av_readdata_pre[31].CLK -clk => waitrequest_reset_override.CLK -clk => wait_latency_counter[0].CLK -clk => wait_latency_counter[1].CLK -reset => in_transfer.ACLR -reset => end_beginbursttransfer.ACLR -reset => end_begintransfer.ACLR -reset => av_chipselect_pre.ACLR -reset => av_outputenable_pre.ACLR -reset => read_latency_shift_reg[0].ACLR -reset => av_readdata_pre[0].ACLR -reset => av_readdata_pre[1].ACLR -reset => av_readdata_pre[2].ACLR -reset => av_readdata_pre[3].ACLR -reset => av_readdata_pre[4].ACLR -reset => av_readdata_pre[5].ACLR -reset => av_readdata_pre[6].ACLR -reset => av_readdata_pre[7].ACLR -reset => av_readdata_pre[8].ACLR -reset => av_readdata_pre[9].ACLR -reset => av_readdata_pre[10].ACLR -reset => av_readdata_pre[11].ACLR -reset => av_readdata_pre[12].ACLR -reset => av_readdata_pre[13].ACLR -reset => av_readdata_pre[14].ACLR -reset => av_readdata_pre[15].ACLR -reset => av_readdata_pre[16].ACLR -reset => av_readdata_pre[17].ACLR -reset => av_readdata_pre[18].ACLR -reset => av_readdata_pre[19].ACLR -reset => av_readdata_pre[20].ACLR -reset => av_readdata_pre[21].ACLR -reset => av_readdata_pre[22].ACLR -reset => av_readdata_pre[23].ACLR -reset => av_readdata_pre[24].ACLR -reset => av_readdata_pre[25].ACLR -reset => av_readdata_pre[26].ACLR -reset => av_readdata_pre[27].ACLR -reset => av_readdata_pre[28].ACLR -reset => av_readdata_pre[29].ACLR -reset => av_readdata_pre[30].ACLR -reset => av_readdata_pre[31].ACLR -reset => waitrequest_reset_override.PRESET -reset => wait_latency_counter[0].ACLR -reset => wait_latency_counter[1].ACLR -uav_address[0] => ~NO_FANOUT~ -uav_address[1] => ~NO_FANOUT~ -uav_address[2] => av_address[0].DATAIN -uav_address[3] => av_address[1].DATAIN -uav_address[4] => ~NO_FANOUT~ -uav_address[5] => ~NO_FANOUT~ -uav_address[6] => ~NO_FANOUT~ -uav_address[7] => ~NO_FANOUT~ -uav_address[8] => ~NO_FANOUT~ -uav_address[9] => ~NO_FANOUT~ -uav_address[10] => ~NO_FANOUT~ -uav_address[11] => ~NO_FANOUT~ -uav_address[12] => ~NO_FANOUT~ -uav_address[13] => ~NO_FANOUT~ -uav_address[14] => ~NO_FANOUT~ -uav_address[15] => ~NO_FANOUT~ -uav_address[16] => ~NO_FANOUT~ -uav_address[17] => ~NO_FANOUT~ -uav_address[18] => ~NO_FANOUT~ -uav_writedata[0] => av_writedata[0].DATAIN -uav_writedata[1] => av_writedata[1].DATAIN -uav_writedata[2] => av_writedata[2].DATAIN -uav_writedata[3] => av_writedata[3].DATAIN -uav_writedata[4] => av_writedata[4].DATAIN -uav_writedata[5] => av_writedata[5].DATAIN -uav_writedata[6] => av_writedata[6].DATAIN -uav_writedata[7] => av_writedata[7].DATAIN -uav_writedata[8] => av_writedata[8].DATAIN -uav_writedata[9] => av_writedata[9].DATAIN -uav_writedata[10] => av_writedata[10].DATAIN -uav_writedata[11] => av_writedata[11].DATAIN -uav_writedata[12] => av_writedata[12].DATAIN -uav_writedata[13] => av_writedata[13].DATAIN -uav_writedata[14] => av_writedata[14].DATAIN -uav_writedata[15] => av_writedata[15].DATAIN -uav_writedata[16] => av_writedata[16].DATAIN -uav_writedata[17] => av_writedata[17].DATAIN -uav_writedata[18] => av_writedata[18].DATAIN -uav_writedata[19] => av_writedata[19].DATAIN -uav_writedata[20] => av_writedata[20].DATAIN -uav_writedata[21] => av_writedata[21].DATAIN -uav_writedata[22] => av_writedata[22].DATAIN -uav_writedata[23] => av_writedata[23].DATAIN -uav_writedata[24] => av_writedata[24].DATAIN -uav_writedata[25] => av_writedata[25].DATAIN -uav_writedata[26] => av_writedata[26].DATAIN -uav_writedata[27] => av_writedata[27].DATAIN -uav_writedata[28] => av_writedata[28].DATAIN -uav_writedata[29] => av_writedata[29].DATAIN -uav_writedata[30] => av_writedata[30].DATAIN -uav_writedata[31] => av_writedata[31].DATAIN -uav_write => av_writebyteenable.IN0 -uav_write => av_write.IN1 -uav_write => av_waitrequest_generated.OUTPUTSELECT -uav_write => av_begintransfer.IN0 -uav_write => end_beginbursttransfer.IN1 -uav_write => always20.IN1 -uav_write => in_transfer.OUTPUTSELECT -uav_read => av_read.IN1 -uav_read => read_latency_shift_reg.IN1 -uav_read => av_outputenable.OUTPUTSELECT -uav_read => av_begintransfer.IN1 -uav_read => av_beginbursttransfer.OUTPUTSELECT -uav_burstcount[0] => Equal2.IN3 -uav_burstcount[1] => Equal2.IN2 -uav_burstcount[2] => av_burstcount[0].DATAIN -uav_burstcount[2] => Equal2.IN4 -uav_byteenable[0] => av_writebyteenable.IN1 -uav_byteenable[0] => av_byteenable[0].DATAIN -uav_byteenable[1] => ~NO_FANOUT~ -uav_byteenable[2] => ~NO_FANOUT~ -uav_byteenable[3] => ~NO_FANOUT~ -uav_lock => av_lock.DATAIN -uav_debugaccess => av_debugaccess.DATAIN -uav_clken => ~NO_FANOUT~ -uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE -uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE -uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE -uav_response[0] <= -uav_response[1] <= -uav_writeresponserequest => av_writeresponserequest.DATAIN -uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE -av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE -av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE -av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE -av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE -av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE -av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE -av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE -av_clken <= -av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE -av_readdata[0] => av_readdata_pre[0].DATAIN -av_readdata[1] => av_readdata_pre[1].DATAIN -av_readdata[2] => av_readdata_pre[2].DATAIN -av_readdata[3] => av_readdata_pre[3].DATAIN -av_readdata[4] => av_readdata_pre[4].DATAIN -av_readdata[5] => av_readdata_pre[5].DATAIN -av_readdata[6] => av_readdata_pre[6].DATAIN -av_readdata[7] => av_readdata_pre[7].DATAIN -av_readdata[8] => av_readdata_pre[8].DATAIN -av_readdata[9] => av_readdata_pre[9].DATAIN -av_readdata[10] => av_readdata_pre[10].DATAIN -av_readdata[11] => av_readdata_pre[11].DATAIN -av_readdata[12] => av_readdata_pre[12].DATAIN -av_readdata[13] => av_readdata_pre[13].DATAIN -av_readdata[14] => av_readdata_pre[14].DATAIN -av_readdata[15] => av_readdata_pre[15].DATAIN -av_readdata[16] => av_readdata_pre[16].DATAIN -av_readdata[17] => av_readdata_pre[17].DATAIN -av_readdata[18] => av_readdata_pre[18].DATAIN -av_readdata[19] => av_readdata_pre[19].DATAIN -av_readdata[20] => av_readdata_pre[20].DATAIN -av_readdata[21] => av_readdata_pre[21].DATAIN -av_readdata[22] => av_readdata_pre[22].DATAIN -av_readdata[23] => av_readdata_pre[23].DATAIN -av_readdata[24] => av_readdata_pre[24].DATAIN -av_readdata[25] => av_readdata_pre[25].DATAIN -av_readdata[26] => av_readdata_pre[26].DATAIN -av_readdata[27] => av_readdata_pre[27].DATAIN -av_readdata[28] => av_readdata_pre[28].DATAIN -av_readdata[29] => av_readdata_pre[29].DATAIN -av_readdata[30] => av_readdata_pre[30].DATAIN -av_readdata[31] => av_readdata_pre[31].DATAIN -av_readdatavalid => ~NO_FANOUT~ -av_waitrequest => ~NO_FANOUT~ -av_response[0] => ~NO_FANOUT~ -av_response[1] => ~NO_FANOUT~ -av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -av_writeresponsevalid => uav_writeresponsevalid.DATAIN - - -|lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent -clk => hold_waitrequest.CLK -reset => hold_waitrequest.PRESET -av_address[0] => ~NO_FANOUT~ -av_address[1] => ~NO_FANOUT~ -av_address[2] => cp_data[38].DATAIN -av_address[3] => cp_data[39].DATAIN -av_address[4] => cp_data[40].DATAIN -av_address[5] => cp_data[41].DATAIN -av_address[6] => cp_data[42].DATAIN -av_address[7] => cp_data[43].DATAIN -av_address[8] => cp_data[44].DATAIN -av_address[9] => cp_data[45].DATAIN -av_address[10] => cp_data[46].DATAIN -av_address[11] => cp_data[47].DATAIN -av_address[12] => cp_data[48].DATAIN -av_address[13] => cp_data[49].DATAIN -av_address[14] => cp_data[50].DATAIN -av_address[15] => cp_data[51].DATAIN -av_address[16] => cp_data[52].DATAIN -av_address[17] => cp_data[53].DATAIN -av_address[18] => cp_data[54].DATAIN -av_write => cp_data.IN0 -av_write => always1.IN0 -av_write => cp_data[57].DATAIN -av_read => always1.IN1 -av_read => cp_data[58].DATAIN -av_writedata[0] => cp_data[0].DATAIN -av_writedata[1] => cp_data[1].DATAIN -av_writedata[2] => cp_data[2].DATAIN -av_writedata[3] => cp_data[3].DATAIN -av_writedata[4] => cp_data[4].DATAIN -av_writedata[5] => cp_data[5].DATAIN -av_writedata[6] => cp_data[6].DATAIN -av_writedata[7] => cp_data[7].DATAIN -av_writedata[8] => cp_data[8].DATAIN -av_writedata[9] => cp_data[9].DATAIN -av_writedata[10] => cp_data[10].DATAIN -av_writedata[11] => cp_data[11].DATAIN -av_writedata[12] => cp_data[12].DATAIN -av_writedata[13] => cp_data[13].DATAIN -av_writedata[14] => cp_data[14].DATAIN -av_writedata[15] => cp_data[15].DATAIN -av_writedata[16] => cp_data[16].DATAIN -av_writedata[17] => cp_data[17].DATAIN -av_writedata[18] => cp_data[18].DATAIN -av_writedata[19] => cp_data[19].DATAIN -av_writedata[20] => cp_data[20].DATAIN -av_writedata[21] => cp_data[21].DATAIN -av_writedata[22] => cp_data[22].DATAIN -av_writedata[23] => cp_data[23].DATAIN -av_writedata[24] => cp_data[24].DATAIN -av_writedata[25] => cp_data[25].DATAIN -av_writedata[26] => cp_data[26].DATAIN -av_writedata[27] => cp_data[27].DATAIN -av_writedata[28] => cp_data[28].DATAIN -av_writedata[29] => cp_data[29].DATAIN -av_writedata[30] => cp_data[30].DATAIN -av_writedata[31] => cp_data[31].DATAIN -av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= av_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] => cp_data[32].DATAIN -av_byteenable[1] => cp_data[33].DATAIN -av_byteenable[2] => cp_data[34].DATAIN -av_byteenable[3] => cp_data[35].DATAIN -av_burstcount[0] => cp_data[61].DATAIN -av_burstcount[1] => cp_data[62].DATAIN -av_burstcount[2] => cp_data[63].DATAIN -av_debugaccess => cp_data[87].DATAIN -av_lock => cp_data[59].DATAIN -av_response[0] <= -av_response[1] <= -av_writeresponserequest => cp_data.IN1 -av_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE -cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[36] <= -cp_data[37] <= -cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[55] <= -cp_data[56] <= cp_data.DB_MAX_OUTPUT_PORT_TYPE -cp_data[57] <= av_write.DB_MAX_OUTPUT_PORT_TYPE -cp_data[58] <= av_read.DB_MAX_OUTPUT_PORT_TYPE -cp_data[59] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -cp_data[60] <= -cp_data[61] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[62] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[63] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[64] <= -cp_data[65] <= -cp_data[66] <= -cp_data[67] <= -cp_data[68] <= -cp_data[69] <= -cp_data[70] <= -cp_data[71] <= -cp_data[72] <= -cp_data[73] <= -cp_data[74] <= -cp_data[75] <= -cp_data[76] <= -cp_data[77] <= -cp_data[78] <= -cp_data[79] <= -cp_data[80] <= -cp_data[81] <= -cp_data[82] <= -cp_data[83] <= -cp_data[84] <= -cp_data[85] <= -cp_data[86] <= -cp_data[87] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -cp_data[88] <= -cp_data[89] <= -cp_data[90] <= -cp_data[91] <= -cp_data[92] <= -cp_data[93] <= -cp_data[94] <= -cp_data[95] <= -cp_startofpacket <= -cp_endofpacket <= -cp_ready => av_waitrequest.IN1 -rp_valid => av_writeresponsevalid.DATAB -rp_valid => av_readdatavalid.DATAA -rp_data[0] => av_readdata[0].DATAIN -rp_data[1] => av_readdata[1].DATAIN -rp_data[2] => av_readdata[2].DATAIN -rp_data[3] => av_readdata[3].DATAIN -rp_data[4] => av_readdata[4].DATAIN -rp_data[5] => av_readdata[5].DATAIN -rp_data[6] => av_readdata[6].DATAIN -rp_data[7] => av_readdata[7].DATAIN -rp_data[8] => av_readdata[8].DATAIN -rp_data[9] => av_readdata[9].DATAIN -rp_data[10] => av_readdata[10].DATAIN -rp_data[11] => av_readdata[11].DATAIN -rp_data[12] => av_readdata[12].DATAIN -rp_data[13] => av_readdata[13].DATAIN -rp_data[14] => av_readdata[14].DATAIN -rp_data[15] => av_readdata[15].DATAIN -rp_data[16] => av_readdata[16].DATAIN -rp_data[17] => av_readdata[17].DATAIN -rp_data[18] => av_readdata[18].DATAIN -rp_data[19] => av_readdata[19].DATAIN -rp_data[20] => av_readdata[20].DATAIN -rp_data[21] => av_readdata[21].DATAIN -rp_data[22] => av_readdata[22].DATAIN -rp_data[23] => av_readdata[23].DATAIN -rp_data[24] => av_readdata[24].DATAIN -rp_data[25] => av_readdata[25].DATAIN -rp_data[26] => av_readdata[26].DATAIN -rp_data[27] => av_readdata[27].DATAIN -rp_data[28] => av_readdata[28].DATAIN -rp_data[29] => av_readdata[29].DATAIN -rp_data[30] => av_readdata[30].DATAIN -rp_data[31] => av_readdata[31].DATAIN -rp_data[32] => ~NO_FANOUT~ -rp_data[33] => ~NO_FANOUT~ -rp_data[34] => ~NO_FANOUT~ -rp_data[35] => ~NO_FANOUT~ -rp_data[36] => ~NO_FANOUT~ -rp_data[37] => ~NO_FANOUT~ -rp_data[38] => ~NO_FANOUT~ -rp_data[39] => ~NO_FANOUT~ -rp_data[40] => ~NO_FANOUT~ -rp_data[41] => ~NO_FANOUT~ -rp_data[42] => ~NO_FANOUT~ -rp_data[43] => ~NO_FANOUT~ -rp_data[44] => ~NO_FANOUT~ -rp_data[45] => ~NO_FANOUT~ -rp_data[46] => ~NO_FANOUT~ -rp_data[47] => ~NO_FANOUT~ -rp_data[48] => ~NO_FANOUT~ -rp_data[49] => ~NO_FANOUT~ -rp_data[50] => ~NO_FANOUT~ -rp_data[51] => ~NO_FANOUT~ -rp_data[52] => ~NO_FANOUT~ -rp_data[53] => ~NO_FANOUT~ -rp_data[54] => ~NO_FANOUT~ -rp_data[55] => ~NO_FANOUT~ -rp_data[56] => ~NO_FANOUT~ -rp_data[57] => av_writeresponsevalid.OUTPUTSELECT -rp_data[57] => av_readdatavalid.OUTPUTSELECT -rp_data[58] => ~NO_FANOUT~ -rp_data[59] => ~NO_FANOUT~ -rp_data[60] => ~NO_FANOUT~ -rp_data[61] => ~NO_FANOUT~ -rp_data[62] => ~NO_FANOUT~ -rp_data[63] => ~NO_FANOUT~ -rp_data[64] => ~NO_FANOUT~ -rp_data[65] => ~NO_FANOUT~ -rp_data[66] => ~NO_FANOUT~ -rp_data[67] => ~NO_FANOUT~ -rp_data[68] => ~NO_FANOUT~ -rp_data[69] => ~NO_FANOUT~ -rp_data[70] => ~NO_FANOUT~ -rp_data[71] => ~NO_FANOUT~ -rp_data[72] => ~NO_FANOUT~ -rp_data[73] => ~NO_FANOUT~ -rp_data[74] => ~NO_FANOUT~ -rp_data[75] => ~NO_FANOUT~ -rp_data[76] => ~NO_FANOUT~ -rp_data[77] => ~NO_FANOUT~ -rp_data[78] => ~NO_FANOUT~ -rp_data[79] => ~NO_FANOUT~ -rp_data[80] => ~NO_FANOUT~ -rp_data[81] => ~NO_FANOUT~ -rp_data[82] => ~NO_FANOUT~ -rp_data[83] => ~NO_FANOUT~ -rp_data[84] => ~NO_FANOUT~ -rp_data[85] => ~NO_FANOUT~ -rp_data[86] => ~NO_FANOUT~ -rp_data[87] => ~NO_FANOUT~ -rp_data[88] => ~NO_FANOUT~ -rp_data[89] => ~NO_FANOUT~ -rp_data[90] => ~NO_FANOUT~ -rp_data[91] => ~NO_FANOUT~ -rp_data[92] => ~NO_FANOUT~ -rp_data[93] => ~NO_FANOUT~ -rp_data[94] => ~NO_FANOUT~ -rp_data[95] => ~NO_FANOUT~ -rp_channel[0] => ~NO_FANOUT~ -rp_channel[1] => ~NO_FANOUT~ -rp_channel[2] => ~NO_FANOUT~ -rp_channel[3] => ~NO_FANOUT~ -rp_channel[4] => ~NO_FANOUT~ -rp_channel[5] => ~NO_FANOUT~ -rp_channel[6] => ~NO_FANOUT~ -rp_channel[7] => ~NO_FANOUT~ -rp_channel[8] => ~NO_FANOUT~ -rp_channel[9] => ~NO_FANOUT~ -rp_channel[10] => ~NO_FANOUT~ -rp_channel[11] => ~NO_FANOUT~ -rp_channel[12] => ~NO_FANOUT~ -rp_channel[13] => ~NO_FANOUT~ -rp_channel[14] => ~NO_FANOUT~ -rp_channel[15] => ~NO_FANOUT~ -rp_channel[16] => ~NO_FANOUT~ -rp_channel[17] => ~NO_FANOUT~ -rp_startofpacket => ~NO_FANOUT~ -rp_endofpacket => ~NO_FANOUT~ -rp_ready <= - - -|lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent -clk => hold_waitrequest.CLK -reset => hold_waitrequest.PRESET -av_address[0] => ~NO_FANOUT~ -av_address[1] => ~NO_FANOUT~ -av_address[2] => cp_data[38].DATAIN -av_address[3] => cp_data[39].DATAIN -av_address[4] => cp_data[40].DATAIN -av_address[5] => cp_data[41].DATAIN -av_address[6] => cp_data[42].DATAIN -av_address[7] => cp_data[43].DATAIN -av_address[8] => cp_data[44].DATAIN -av_address[9] => cp_data[45].DATAIN -av_address[10] => cp_data[46].DATAIN -av_address[11] => cp_data[47].DATAIN -av_address[12] => cp_data[48].DATAIN -av_address[13] => cp_data[49].DATAIN -av_address[14] => cp_data[50].DATAIN -av_address[15] => cp_data[51].DATAIN -av_address[16] => cp_data[52].DATAIN -av_address[17] => cp_data[53].DATAIN -av_address[18] => cp_data[54].DATAIN -av_write => cp_data.IN0 -av_write => always1.IN0 -av_write => cp_data[57].DATAIN -av_read => always1.IN1 -av_read => cp_data[58].DATAIN -av_writedata[0] => cp_data[0].DATAIN -av_writedata[1] => cp_data[1].DATAIN -av_writedata[2] => cp_data[2].DATAIN -av_writedata[3] => cp_data[3].DATAIN -av_writedata[4] => cp_data[4].DATAIN -av_writedata[5] => cp_data[5].DATAIN -av_writedata[6] => cp_data[6].DATAIN -av_writedata[7] => cp_data[7].DATAIN -av_writedata[8] => cp_data[8].DATAIN -av_writedata[9] => cp_data[9].DATAIN -av_writedata[10] => cp_data[10].DATAIN -av_writedata[11] => cp_data[11].DATAIN -av_writedata[12] => cp_data[12].DATAIN -av_writedata[13] => cp_data[13].DATAIN -av_writedata[14] => cp_data[14].DATAIN -av_writedata[15] => cp_data[15].DATAIN -av_writedata[16] => cp_data[16].DATAIN -av_writedata[17] => cp_data[17].DATAIN -av_writedata[18] => cp_data[18].DATAIN -av_writedata[19] => cp_data[19].DATAIN -av_writedata[20] => cp_data[20].DATAIN -av_writedata[21] => cp_data[21].DATAIN -av_writedata[22] => cp_data[22].DATAIN -av_writedata[23] => cp_data[23].DATAIN -av_writedata[24] => cp_data[24].DATAIN -av_writedata[25] => cp_data[25].DATAIN -av_writedata[26] => cp_data[26].DATAIN -av_writedata[27] => cp_data[27].DATAIN -av_writedata[28] => cp_data[28].DATAIN -av_writedata[29] => cp_data[29].DATAIN -av_writedata[30] => cp_data[30].DATAIN -av_writedata[31] => cp_data[31].DATAIN -av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE -av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE -av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE -av_readdatavalid <= av_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE -av_byteenable[0] => cp_data[32].DATAIN -av_byteenable[1] => cp_data[33].DATAIN -av_byteenable[2] => cp_data[34].DATAIN -av_byteenable[3] => cp_data[35].DATAIN -av_burstcount[0] => cp_data[61].DATAIN -av_burstcount[1] => cp_data[62].DATAIN -av_burstcount[2] => cp_data[63].DATAIN -av_debugaccess => cp_data[87].DATAIN -av_lock => cp_data[59].DATAIN -av_response[0] <= -av_response[1] <= -av_writeresponserequest => cp_data.IN1 -av_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE -cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE -cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE -cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE -cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE -cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE -cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE -cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE -cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE -cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE -cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE -cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE -cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE -cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE -cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE -cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[36] <= -cp_data[37] <= -cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE -cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE -cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE -cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE -cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE -cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE -cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE -cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE -cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE -cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE -cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE -cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE -cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE -cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE -cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE -cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE -cp_data[55] <= -cp_data[56] <= cp_data.DB_MAX_OUTPUT_PORT_TYPE -cp_data[57] <= av_write.DB_MAX_OUTPUT_PORT_TYPE -cp_data[58] <= av_read.DB_MAX_OUTPUT_PORT_TYPE -cp_data[59] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE -cp_data[60] <= -cp_data[61] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE -cp_data[62] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE -cp_data[63] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE -cp_data[64] <= -cp_data[65] <= -cp_data[66] <= -cp_data[67] <= -cp_data[68] <= -cp_data[69] <= -cp_data[70] <= -cp_data[71] <= -cp_data[72] <= -cp_data[73] <= -cp_data[74] <= -cp_data[75] <= -cp_data[76] <= -cp_data[77] <= -cp_data[78] <= -cp_data[79] <= -cp_data[80] <= -cp_data[81] <= -cp_data[82] <= -cp_data[83] <= -cp_data[84] <= -cp_data[85] <= -cp_data[86] <= -cp_data[87] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE -cp_data[88] <= -cp_data[89] <= -cp_data[90] <= -cp_data[91] <= -cp_data[92] <= -cp_data[93] <= -cp_data[94] <= -cp_data[95] <= -cp_startofpacket <= -cp_endofpacket <= -cp_ready => av_waitrequest.IN1 -rp_valid => av_writeresponsevalid.DATAB -rp_valid => av_readdatavalid.DATAA -rp_data[0] => av_readdata[0].DATAIN -rp_data[1] => av_readdata[1].DATAIN -rp_data[2] => av_readdata[2].DATAIN -rp_data[3] => av_readdata[3].DATAIN -rp_data[4] => av_readdata[4].DATAIN -rp_data[5] => av_readdata[5].DATAIN -rp_data[6] => av_readdata[6].DATAIN -rp_data[7] => av_readdata[7].DATAIN -rp_data[8] => av_readdata[8].DATAIN -rp_data[9] => av_readdata[9].DATAIN -rp_data[10] => av_readdata[10].DATAIN -rp_data[11] => av_readdata[11].DATAIN -rp_data[12] => av_readdata[12].DATAIN -rp_data[13] => av_readdata[13].DATAIN -rp_data[14] => av_readdata[14].DATAIN -rp_data[15] => av_readdata[15].DATAIN -rp_data[16] => av_readdata[16].DATAIN -rp_data[17] => av_readdata[17].DATAIN -rp_data[18] => av_readdata[18].DATAIN -rp_data[19] => av_readdata[19].DATAIN -rp_data[20] => av_readdata[20].DATAIN -rp_data[21] => av_readdata[21].DATAIN -rp_data[22] => av_readdata[22].DATAIN -rp_data[23] => av_readdata[23].DATAIN -rp_data[24] => av_readdata[24].DATAIN -rp_data[25] => av_readdata[25].DATAIN -rp_data[26] => av_readdata[26].DATAIN -rp_data[27] => av_readdata[27].DATAIN -rp_data[28] => av_readdata[28].DATAIN -rp_data[29] => av_readdata[29].DATAIN -rp_data[30] => av_readdata[30].DATAIN -rp_data[31] => av_readdata[31].DATAIN -rp_data[32] => ~NO_FANOUT~ -rp_data[33] => ~NO_FANOUT~ -rp_data[34] => ~NO_FANOUT~ -rp_data[35] => ~NO_FANOUT~ -rp_data[36] => ~NO_FANOUT~ -rp_data[37] => ~NO_FANOUT~ -rp_data[38] => ~NO_FANOUT~ -rp_data[39] => ~NO_FANOUT~ -rp_data[40] => ~NO_FANOUT~ -rp_data[41] => ~NO_FANOUT~ -rp_data[42] => ~NO_FANOUT~ -rp_data[43] => ~NO_FANOUT~ -rp_data[44] => ~NO_FANOUT~ -rp_data[45] => ~NO_FANOUT~ -rp_data[46] => ~NO_FANOUT~ -rp_data[47] => ~NO_FANOUT~ -rp_data[48] => ~NO_FANOUT~ -rp_data[49] => ~NO_FANOUT~ -rp_data[50] => ~NO_FANOUT~ -rp_data[51] => ~NO_FANOUT~ -rp_data[52] => ~NO_FANOUT~ -rp_data[53] => ~NO_FANOUT~ -rp_data[54] => ~NO_FANOUT~ -rp_data[55] => ~NO_FANOUT~ -rp_data[56] => ~NO_FANOUT~ -rp_data[57] => av_writeresponsevalid.OUTPUTSELECT -rp_data[57] => av_readdatavalid.OUTPUTSELECT -rp_data[58] => ~NO_FANOUT~ -rp_data[59] => ~NO_FANOUT~ -rp_data[60] => ~NO_FANOUT~ -rp_data[61] => ~NO_FANOUT~ -rp_data[62] => ~NO_FANOUT~ -rp_data[63] => ~NO_FANOUT~ -rp_data[64] => ~NO_FANOUT~ -rp_data[65] => ~NO_FANOUT~ -rp_data[66] => ~NO_FANOUT~ -rp_data[67] => ~NO_FANOUT~ -rp_data[68] => ~NO_FANOUT~ -rp_data[69] => ~NO_FANOUT~ -rp_data[70] => ~NO_FANOUT~ -rp_data[71] => ~NO_FANOUT~ -rp_data[72] => ~NO_FANOUT~ -rp_data[73] => ~NO_FANOUT~ -rp_data[74] => ~NO_FANOUT~ -rp_data[75] => ~NO_FANOUT~ -rp_data[76] => ~NO_FANOUT~ -rp_data[77] => ~NO_FANOUT~ -rp_data[78] => ~NO_FANOUT~ -rp_data[79] => ~NO_FANOUT~ -rp_data[80] => ~NO_FANOUT~ -rp_data[81] => ~NO_FANOUT~ -rp_data[82] => ~NO_FANOUT~ -rp_data[83] => ~NO_FANOUT~ -rp_data[84] => ~NO_FANOUT~ -rp_data[85] => ~NO_FANOUT~ -rp_data[86] => ~NO_FANOUT~ -rp_data[87] => ~NO_FANOUT~ -rp_data[88] => ~NO_FANOUT~ -rp_data[89] => ~NO_FANOUT~ -rp_data[90] => ~NO_FANOUT~ -rp_data[91] => ~NO_FANOUT~ -rp_data[92] => ~NO_FANOUT~ -rp_data[93] => ~NO_FANOUT~ -rp_data[94] => ~NO_FANOUT~ -rp_data[95] => ~NO_FANOUT~ -rp_channel[0] => ~NO_FANOUT~ -rp_channel[1] => ~NO_FANOUT~ -rp_channel[2] => ~NO_FANOUT~ -rp_channel[3] => ~NO_FANOUT~ -rp_channel[4] => ~NO_FANOUT~ -rp_channel[5] => ~NO_FANOUT~ -rp_channel[6] => ~NO_FANOUT~ -rp_channel[7] => ~NO_FANOUT~ -rp_channel[8] => ~NO_FANOUT~ -rp_channel[9] => ~NO_FANOUT~ -rp_channel[10] => ~NO_FANOUT~ -rp_channel[11] => ~NO_FANOUT~ -rp_channel[12] => ~NO_FANOUT~ -rp_channel[13] => ~NO_FANOUT~ -rp_channel[14] => ~NO_FANOUT~ -rp_channel[15] => ~NO_FANOUT~ -rp_channel[16] => ~NO_FANOUT~ -rp_channel[17] => ~NO_FANOUT~ -rp_startofpacket => ~NO_FANOUT~ -rp_endofpacket => ~NO_FANOUT~ -rp_ready <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent -clk => clk.IN1 -reset => reset.IN1 -m0_address[0] <= -m0_address[1] <= -m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE -m0_readdata[0] => rdata_fifo_src_data[0].DATAIN -m0_readdata[1] => rdata_fifo_src_data[1].DATAIN -m0_readdata[2] => rdata_fifo_src_data[2].DATAIN -m0_readdata[3] => rdata_fifo_src_data[3].DATAIN -m0_readdata[4] => rdata_fifo_src_data[4].DATAIN -m0_readdata[5] => rdata_fifo_src_data[5].DATAIN -m0_readdata[6] => rdata_fifo_src_data[6].DATAIN -m0_readdata[7] => rdata_fifo_src_data[7].DATAIN -m0_readdata[8] => rdata_fifo_src_data[8].DATAIN -m0_readdata[9] => rdata_fifo_src_data[9].DATAIN -m0_readdata[10] => rdata_fifo_src_data[10].DATAIN -m0_readdata[11] => rdata_fifo_src_data[11].DATAIN -m0_readdata[12] => rdata_fifo_src_data[12].DATAIN -m0_readdata[13] => rdata_fifo_src_data[13].DATAIN -m0_readdata[14] => rdata_fifo_src_data[14].DATAIN -m0_readdata[15] => rdata_fifo_src_data[15].DATAIN -m0_readdata[16] => rdata_fifo_src_data[16].DATAIN -m0_readdata[17] => rdata_fifo_src_data[17].DATAIN -m0_readdata[18] => rdata_fifo_src_data[18].DATAIN -m0_readdata[19] => rdata_fifo_src_data[19].DATAIN -m0_readdata[20] => rdata_fifo_src_data[20].DATAIN -m0_readdata[21] => rdata_fifo_src_data[21].DATAIN -m0_readdata[22] => rdata_fifo_src_data[22].DATAIN -m0_readdata[23] => rdata_fifo_src_data[23].DATAIN -m0_readdata[24] => rdata_fifo_src_data[24].DATAIN -m0_readdata[25] => rdata_fifo_src_data[25].DATAIN -m0_readdata[26] => rdata_fifo_src_data[26].DATAIN -m0_readdata[27] => rdata_fifo_src_data[27].DATAIN -m0_readdata[28] => rdata_fifo_src_data[28].DATAIN -m0_readdata[29] => rdata_fifo_src_data[29].DATAIN -m0_readdata[30] => rdata_fifo_src_data[30].DATAIN -m0_readdata[31] => rdata_fifo_src_data[31].DATAIN -m0_waitrequest => cp_ready.IN0 -m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE -m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE -m0_readdatavalid => rdata_fifo_src_valid.IN0 -m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE -m0_response[0] => rdata_fifo_src_data[32].DATAIN -m0_response[1] => rdata_fifo_src_data[33].DATAIN -m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE -m0_writeresponsevalid => rdata_fifo_src_valid.IN1 -rf_source_data[0] <= -rf_source_data[1] <= -rf_source_data[2] <= -rf_source_data[3] <= -rf_source_data[4] <= -rf_source_data[5] <= -rf_source_data[6] <= -rf_source_data[7] <= -rf_source_data[8] <= -rf_source_data[9] <= -rf_source_data[10] <= -rf_source_data[11] <= -rf_source_data[12] <= -rf_source_data[13] <= -rf_source_data[14] <= -rf_source_data[15] <= -rf_source_data[16] <= -rf_source_data[17] <= -rf_source_data[18] <= -rf_source_data[19] <= -rf_source_data[20] <= -rf_source_data[21] <= -rf_source_data[22] <= -rf_source_data[23] <= -rf_source_data[24] <= -rf_source_data[25] <= -rf_source_data[26] <= -rf_source_data[27] <= -rf_source_data[28] <= -rf_source_data[29] <= -rf_source_data[30] <= -rf_source_data[31] <= -rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[88] <= -rf_source_data[89] <= -rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE -rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE -rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -rf_source_ready => cp_ready.IN1 -rf_source_ready => m0_write.IN1 -rf_source_ready => m0_lock.IN1 -rf_source_ready => rf_source_valid.IN1 -rf_source_ready => m0_read.IN1 -rf_sink_data[0] => ~NO_FANOUT~ -rf_sink_data[1] => ~NO_FANOUT~ -rf_sink_data[2] => ~NO_FANOUT~ -rf_sink_data[3] => ~NO_FANOUT~ -rf_sink_data[4] => ~NO_FANOUT~ -rf_sink_data[5] => ~NO_FANOUT~ -rf_sink_data[6] => ~NO_FANOUT~ -rf_sink_data[7] => ~NO_FANOUT~ -rf_sink_data[8] => ~NO_FANOUT~ -rf_sink_data[9] => ~NO_FANOUT~ -rf_sink_data[10] => ~NO_FANOUT~ -rf_sink_data[11] => ~NO_FANOUT~ -rf_sink_data[12] => ~NO_FANOUT~ -rf_sink_data[13] => ~NO_FANOUT~ -rf_sink_data[14] => ~NO_FANOUT~ -rf_sink_data[15] => ~NO_FANOUT~ -rf_sink_data[16] => ~NO_FANOUT~ -rf_sink_data[17] => ~NO_FANOUT~ -rf_sink_data[18] => ~NO_FANOUT~ -rf_sink_data[19] => ~NO_FANOUT~ -rf_sink_data[20] => ~NO_FANOUT~ -rf_sink_data[21] => ~NO_FANOUT~ -rf_sink_data[22] => ~NO_FANOUT~ -rf_sink_data[23] => ~NO_FANOUT~ -rf_sink_data[24] => ~NO_FANOUT~ -rf_sink_data[25] => ~NO_FANOUT~ -rf_sink_data[26] => ~NO_FANOUT~ -rf_sink_data[27] => ~NO_FANOUT~ -rf_sink_data[28] => ~NO_FANOUT~ -rf_sink_data[29] => ~NO_FANOUT~ -rf_sink_data[30] => ~NO_FANOUT~ -rf_sink_data[31] => ~NO_FANOUT~ -rf_sink_data[32] => rp_data[32].DATAIN -rf_sink_data[33] => rp_data[33].DATAIN -rf_sink_data[34] => rp_data[34].DATAIN -rf_sink_data[35] => rp_data[35].DATAIN -rf_sink_data[36] => rf_sink_addr[0].IN1 -rf_sink_data[37] => rf_sink_addr[1].IN1 -rf_sink_data[38] => rf_sink_addr[2].IN1 -rf_sink_data[39] => rf_sink_addr[3].IN1 -rf_sink_data[40] => rf_sink_addr[4].IN1 -rf_sink_data[41] => rf_sink_addr[5].IN1 -rf_sink_data[42] => rf_sink_addr[6].IN1 -rf_sink_data[43] => rf_sink_addr[7].IN1 -rf_sink_data[44] => rf_sink_addr[8].IN1 -rf_sink_data[45] => rf_sink_addr[9].IN1 -rf_sink_data[46] => rf_sink_addr[10].IN1 -rf_sink_data[47] => rf_sink_addr[11].IN1 -rf_sink_data[48] => rf_sink_addr[12].IN1 -rf_sink_data[49] => rf_sink_addr[13].IN1 -rf_sink_data[50] => rf_sink_addr[14].IN1 -rf_sink_data[51] => rf_sink_addr[15].IN1 -rf_sink_data[52] => rf_sink_addr[16].IN1 -rf_sink_data[53] => rf_sink_addr[17].IN1 -rf_sink_data[54] => rf_sink_addr[18].IN1 -rf_sink_data[55] => rf_sink_compressed.IN1 -rf_sink_data[56] => rp_data[56].DATAIN -rf_sink_data[57] => comb.OUTPUTSELECT -rf_sink_data[57] => rp_data[57].DATAIN -rf_sink_data[58] => rp_data.IN0 -rf_sink_data[59] => rp_data[59].DATAIN -rf_sink_data[60] => rp_data[60].DATAIN -rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 -rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 -rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 -rf_sink_data[64] => rf_sink_burstwrap[0].IN1 -rf_sink_data[65] => rf_sink_burstwrap[1].IN1 -rf_sink_data[66] => rf_sink_burstwrap[2].IN1 -rf_sink_data[67] => rf_sink_burstsize[0].IN1 -rf_sink_data[68] => rf_sink_burstsize[1].IN1 -rf_sink_data[69] => rf_sink_burstsize[2].IN1 -rf_sink_data[70] => rp_data[70].DATAIN -rf_sink_data[71] => rp_data[71].DATAIN -rf_sink_data[72] => rp_data[72].DATAIN -rf_sink_data[73] => rp_data[73].DATAIN -rf_sink_data[74] => rp_data[74].DATAIN -rf_sink_data[75] => rp_data[75].DATAIN -rf_sink_data[76] => rp_data[81].DATAIN -rf_sink_data[77] => rp_data[82].DATAIN -rf_sink_data[78] => rp_data[83].DATAIN -rf_sink_data[79] => rp_data[84].DATAIN -rf_sink_data[80] => rp_data[85].DATAIN -rf_sink_data[81] => rp_data[76].DATAIN -rf_sink_data[82] => rp_data[77].DATAIN -rf_sink_data[83] => rp_data[78].DATAIN -rf_sink_data[84] => rp_data[79].DATAIN -rf_sink_data[85] => rp_data[80].DATAIN -rf_sink_data[86] => rp_data[86].DATAIN -rf_sink_data[87] => rp_data[87].DATAIN -rf_sink_data[88] => rp_data[88].DATAIN -rf_sink_data[89] => rp_data[89].DATAIN -rf_sink_data[90] => rp_data[90].DATAIN -rf_sink_data[91] => rp_data[91].DATAIN -rf_sink_data[92] => rp_data[92].DATAIN -rf_sink_data[93] => rp_data[93].DATAIN -rf_sink_data[94] => ~NO_FANOUT~ -rf_sink_data[95] => ~NO_FANOUT~ -rf_sink_data[96] => rdata_fifo_sink_ready.IN0 -rf_sink_data[96] => comb.IN0 -rf_sink_valid => rdata_fifo_sink_ready.IN1 -rf_sink_valid => comb.IN1 -rf_sink_startofpacket => comb.DATAA -rf_sink_endofpacket => rf_sink_endofpacket.IN1 -rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready -rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE -rdata_fifo_src_ready => ~NO_FANOUT~ -rdata_fifo_sink_data[0] => rp_data[0].DATAIN -rdata_fifo_sink_data[1] => rp_data[1].DATAIN -rdata_fifo_sink_data[2] => rp_data[2].DATAIN -rdata_fifo_sink_data[3] => rp_data[3].DATAIN -rdata_fifo_sink_data[4] => rp_data[4].DATAIN -rdata_fifo_sink_data[5] => rp_data[5].DATAIN -rdata_fifo_sink_data[6] => rp_data[6].DATAIN -rdata_fifo_sink_data[7] => rp_data[7].DATAIN -rdata_fifo_sink_data[8] => rp_data[8].DATAIN -rdata_fifo_sink_data[9] => rp_data[9].DATAIN -rdata_fifo_sink_data[10] => rp_data[10].DATAIN -rdata_fifo_sink_data[11] => rp_data[11].DATAIN -rdata_fifo_sink_data[12] => rp_data[12].DATAIN -rdata_fifo_sink_data[13] => rp_data[13].DATAIN -rdata_fifo_sink_data[14] => rp_data[14].DATAIN -rdata_fifo_sink_data[15] => rp_data[15].DATAIN -rdata_fifo_sink_data[16] => rp_data[16].DATAIN -rdata_fifo_sink_data[17] => rp_data[17].DATAIN -rdata_fifo_sink_data[18] => rp_data[18].DATAIN -rdata_fifo_sink_data[19] => rp_data[19].DATAIN -rdata_fifo_sink_data[20] => rp_data[20].DATAIN -rdata_fifo_sink_data[21] => rp_data[21].DATAIN -rdata_fifo_sink_data[22] => rp_data[22].DATAIN -rdata_fifo_sink_data[23] => rp_data[23].DATAIN -rdata_fifo_sink_data[24] => rp_data[24].DATAIN -rdata_fifo_sink_data[25] => rp_data[25].DATAIN -rdata_fifo_sink_data[26] => rp_data[26].DATAIN -rdata_fifo_sink_data[27] => rp_data[27].DATAIN -rdata_fifo_sink_data[28] => rp_data[28].DATAIN -rdata_fifo_sink_data[29] => rp_data[29].DATAIN -rdata_fifo_sink_data[30] => rp_data[30].DATAIN -rdata_fifo_sink_data[31] => rp_data[31].DATAIN -rdata_fifo_sink_data[32] => rp_data[94].DATAIN -rdata_fifo_sink_data[33] => rp_data[95].DATAIN -rdata_fifo_sink_valid => rp_valid.IN1 -rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 -rdata_fifo_sink_valid => comb.IN1 -rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE -cp_valid => local_lock.IN0 -cp_valid => local_write.IN0 -cp_valid => local_read.IN0 -cp_valid => local_compressed_read.IN0 -cp_data[0] => m0_writedata[0].DATAIN -cp_data[1] => m0_writedata[1].DATAIN -cp_data[2] => m0_writedata[2].DATAIN -cp_data[3] => m0_writedata[3].DATAIN -cp_data[4] => m0_writedata[4].DATAIN -cp_data[5] => m0_writedata[5].DATAIN -cp_data[6] => m0_writedata[6].DATAIN -cp_data[7] => m0_writedata[7].DATAIN -cp_data[8] => m0_writedata[8].DATAIN -cp_data[9] => m0_writedata[9].DATAIN -cp_data[10] => m0_writedata[10].DATAIN -cp_data[11] => m0_writedata[11].DATAIN -cp_data[12] => m0_writedata[12].DATAIN -cp_data[13] => m0_writedata[13].DATAIN -cp_data[14] => m0_writedata[14].DATAIN -cp_data[15] => m0_writedata[15].DATAIN -cp_data[16] => m0_writedata[16].DATAIN -cp_data[17] => m0_writedata[17].DATAIN -cp_data[18] => m0_writedata[18].DATAIN -cp_data[19] => m0_writedata[19].DATAIN -cp_data[20] => m0_writedata[20].DATAIN -cp_data[21] => m0_writedata[21].DATAIN -cp_data[22] => m0_writedata[22].DATAIN -cp_data[23] => m0_writedata[23].DATAIN -cp_data[24] => m0_writedata[24].DATAIN -cp_data[25] => m0_writedata[25].DATAIN -cp_data[26] => m0_writedata[26].DATAIN -cp_data[27] => m0_writedata[27].DATAIN -cp_data[28] => m0_writedata[28].DATAIN -cp_data[29] => m0_writedata[29].DATAIN -cp_data[30] => m0_writedata[30].DATAIN -cp_data[31] => m0_writedata[31].DATAIN -cp_data[32] => rf_source_data[32].DATAIN -cp_data[32] => m0_byteenable[0].DATAIN -cp_data[33] => rf_source_data[33].DATAIN -cp_data[33] => m0_byteenable[1].DATAIN -cp_data[34] => rf_source_data[34].DATAIN -cp_data[34] => m0_byteenable[2].DATAIN -cp_data[35] => rf_source_data[35].DATAIN -cp_data[35] => m0_byteenable[3].DATAIN -cp_data[36] => rf_source_data[36].DATAIN -cp_data[37] => rf_source_data[37].DATAIN -cp_data[38] => rf_source_data[38].DATAIN -cp_data[38] => m0_address[2].DATAIN -cp_data[39] => rf_source_data[39].DATAIN -cp_data[39] => m0_address[3].DATAIN -cp_data[40] => rf_source_data[40].DATAIN -cp_data[40] => m0_address[4].DATAIN -cp_data[41] => rf_source_data[41].DATAIN -cp_data[41] => m0_address[5].DATAIN -cp_data[42] => rf_source_data[42].DATAIN -cp_data[42] => m0_address[6].DATAIN -cp_data[43] => rf_source_data[43].DATAIN -cp_data[43] => m0_address[7].DATAIN -cp_data[44] => rf_source_data[44].DATAIN -cp_data[44] => m0_address[8].DATAIN -cp_data[45] => rf_source_data[45].DATAIN -cp_data[45] => m0_address[9].DATAIN -cp_data[46] => rf_source_data[46].DATAIN -cp_data[46] => m0_address[10].DATAIN -cp_data[47] => rf_source_data[47].DATAIN -cp_data[47] => m0_address[11].DATAIN -cp_data[48] => rf_source_data[48].DATAIN -cp_data[48] => m0_address[12].DATAIN -cp_data[49] => rf_source_data[49].DATAIN -cp_data[49] => m0_address[13].DATAIN -cp_data[50] => rf_source_data[50].DATAIN -cp_data[50] => m0_address[14].DATAIN -cp_data[51] => rf_source_data[51].DATAIN -cp_data[51] => m0_address[15].DATAIN -cp_data[52] => rf_source_data[52].DATAIN -cp_data[52] => m0_address[16].DATAIN -cp_data[53] => rf_source_data[53].DATAIN -cp_data[53] => m0_address[17].DATAIN -cp_data[54] => rf_source_data[54].DATAIN -cp_data[54] => m0_address[18].DATAIN -cp_data[55] => local_compressed_read.IN1 -cp_data[55] => rf_source_data[55].DATAIN -cp_data[56] => rf_source_data[56].DATAIN -cp_data[56] => m0_writeresponserequest.IN1 -cp_data[56] => comb.IN1 -cp_data[57] => local_write.IN1 -cp_data[57] => rf_source_data[57].DATAIN -cp_data[58] => local_read.IN1 -cp_data[58] => rf_source_data[58].DATAIN -cp_data[59] => local_lock.IN1 -cp_data[59] => rf_source_data[59].DATAIN -cp_data[60] => rf_source_data[60].DATAIN -cp_data[61] => m0_burstcount.DATAA -cp_data[61] => rf_source_data[61].DATAIN -cp_data[62] => m0_burstcount.DATAA -cp_data[62] => rf_source_data[62].DATAIN -cp_data[63] => m0_burstcount.DATAA -cp_data[63] => rf_source_data[63].DATAIN -cp_data[64] => rf_source_data[64].DATAIN -cp_data[65] => rf_source_data[65].DATAIN -cp_data[66] => rf_source_data[66].DATAIN -cp_data[67] => rf_source_data[67].DATAIN -cp_data[68] => rf_source_data[68].DATAIN -cp_data[69] => rf_source_data[69].DATAIN -cp_data[70] => rf_source_data[70].DATAIN -cp_data[71] => rf_source_data[71].DATAIN -cp_data[72] => rf_source_data[72].DATAIN -cp_data[73] => rf_source_data[73].DATAIN -cp_data[74] => rf_source_data[74].DATAIN -cp_data[75] => rf_source_data[75].DATAIN -cp_data[76] => rf_source_data[76].DATAIN -cp_data[77] => rf_source_data[77].DATAIN -cp_data[78] => rf_source_data[78].DATAIN -cp_data[79] => rf_source_data[79].DATAIN -cp_data[80] => rf_source_data[80].DATAIN -cp_data[81] => rf_source_data[81].DATAIN -cp_data[82] => rf_source_data[82].DATAIN -cp_data[83] => rf_source_data[83].DATAIN -cp_data[84] => rf_source_data[84].DATAIN -cp_data[85] => rf_source_data[85].DATAIN -cp_data[86] => rf_source_data[86].DATAIN -cp_data[87] => rf_source_data[87].DATAIN -cp_data[87] => m0_debugaccess.DATAIN -cp_data[88] => ~NO_FANOUT~ -cp_data[89] => ~NO_FANOUT~ -cp_data[90] => rf_source_data[90].DATAIN -cp_data[91] => rf_source_data[91].DATAIN -cp_data[92] => rf_source_data[92].DATAIN -cp_data[93] => rf_source_data[93].DATAIN -cp_data[94] => rf_source_data[94].DATAIN -cp_data[95] => rf_source_data[95].DATAIN -cp_channel[0] => ~NO_FANOUT~ -cp_channel[1] => ~NO_FANOUT~ -cp_channel[2] => ~NO_FANOUT~ -cp_channel[3] => ~NO_FANOUT~ -cp_channel[4] => ~NO_FANOUT~ -cp_channel[5] => ~NO_FANOUT~ -cp_channel[6] => ~NO_FANOUT~ -cp_channel[7] => ~NO_FANOUT~ -cp_channel[8] => ~NO_FANOUT~ -cp_channel[9] => ~NO_FANOUT~ -cp_channel[10] => ~NO_FANOUT~ -cp_channel[11] => ~NO_FANOUT~ -cp_channel[12] => ~NO_FANOUT~ -cp_channel[13] => ~NO_FANOUT~ -cp_channel[14] => ~NO_FANOUT~ -cp_channel[15] => ~NO_FANOUT~ -cp_channel[16] => ~NO_FANOUT~ -cp_channel[17] => ~NO_FANOUT~ -cp_startofpacket => rf_source_startofpacket.DATAIN -cp_endofpacket => nonposted_write_endofpacket.IN1 -cp_endofpacket => rf_source_endofpacket.DATAIN -rp_ready => rp_ready.IN1 -rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE -rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr -rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed -rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE -rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt -rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap -rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize -rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket -rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket - - -|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -clk => burst_uncompress_address_offset[0].CLK -clk => burst_uncompress_address_offset[1].CLK -clk => burst_uncompress_address_offset[2].CLK -clk => burst_uncompress_address_offset[3].CLK -clk => burst_uncompress_address_offset[4].CLK -clk => burst_uncompress_address_offset[5].CLK -clk => burst_uncompress_address_offset[6].CLK -clk => burst_uncompress_address_offset[7].CLK -clk => burst_uncompress_address_offset[8].CLK -clk => burst_uncompress_address_offset[9].CLK -clk => burst_uncompress_address_offset[10].CLK -clk => burst_uncompress_address_offset[11].CLK -clk => burst_uncompress_address_offset[12].CLK -clk => burst_uncompress_address_offset[13].CLK -clk => burst_uncompress_address_offset[14].CLK -clk => burst_uncompress_address_offset[15].CLK -clk => burst_uncompress_address_offset[16].CLK -clk => burst_uncompress_address_offset[17].CLK -clk => burst_uncompress_address_offset[18].CLK -clk => burst_uncompress_address_base[0].CLK -clk => burst_uncompress_address_base[1].CLK -clk => burst_uncompress_address_base[2].CLK -clk => burst_uncompress_address_base[3].CLK -clk => burst_uncompress_address_base[4].CLK -clk => burst_uncompress_address_base[5].CLK -clk => burst_uncompress_address_base[6].CLK -clk => burst_uncompress_address_base[7].CLK -clk => burst_uncompress_address_base[8].CLK -clk => burst_uncompress_address_base[9].CLK -clk => burst_uncompress_address_base[10].CLK -clk => burst_uncompress_address_base[11].CLK -clk => burst_uncompress_address_base[12].CLK -clk => burst_uncompress_address_base[13].CLK -clk => burst_uncompress_address_base[14].CLK -clk => burst_uncompress_address_base[15].CLK -clk => burst_uncompress_address_base[16].CLK -clk => burst_uncompress_address_base[17].CLK -clk => burst_uncompress_address_base[18].CLK -clk => burst_uncompress_byte_counter[0].CLK -clk => burst_uncompress_byte_counter[1].CLK -clk => burst_uncompress_byte_counter[2].CLK -clk => burst_uncompress_busy.CLK -reset => burst_uncompress_address_offset[0].ACLR -reset => burst_uncompress_address_offset[1].ACLR -reset => burst_uncompress_address_offset[2].ACLR -reset => burst_uncompress_address_offset[3].ACLR -reset => burst_uncompress_address_offset[4].ACLR -reset => burst_uncompress_address_offset[5].ACLR -reset => burst_uncompress_address_offset[6].ACLR -reset => burst_uncompress_address_offset[7].ACLR -reset => burst_uncompress_address_offset[8].ACLR -reset => burst_uncompress_address_offset[9].ACLR -reset => burst_uncompress_address_offset[10].ACLR -reset => burst_uncompress_address_offset[11].ACLR -reset => burst_uncompress_address_offset[12].ACLR -reset => burst_uncompress_address_offset[13].ACLR -reset => burst_uncompress_address_offset[14].ACLR -reset => burst_uncompress_address_offset[15].ACLR -reset => burst_uncompress_address_offset[16].ACLR -reset => burst_uncompress_address_offset[17].ACLR -reset => burst_uncompress_address_offset[18].ACLR -reset => burst_uncompress_address_base[0].ACLR -reset => burst_uncompress_address_base[1].ACLR -reset => burst_uncompress_address_base[2].ACLR -reset => burst_uncompress_address_base[3].ACLR -reset => burst_uncompress_address_base[4].ACLR -reset => burst_uncompress_address_base[5].ACLR -reset => burst_uncompress_address_base[6].ACLR -reset => burst_uncompress_address_base[7].ACLR -reset => burst_uncompress_address_base[8].ACLR -reset => burst_uncompress_address_base[9].ACLR -reset => burst_uncompress_address_base[10].ACLR -reset => burst_uncompress_address_base[11].ACLR -reset => burst_uncompress_address_base[12].ACLR -reset => burst_uncompress_address_base[13].ACLR -reset => burst_uncompress_address_base[14].ACLR -reset => burst_uncompress_address_base[15].ACLR -reset => burst_uncompress_address_base[16].ACLR -reset => burst_uncompress_address_base[17].ACLR -reset => burst_uncompress_address_base[18].ACLR -reset => burst_uncompress_byte_counter[0].ACLR -reset => burst_uncompress_byte_counter[1].ACLR -reset => burst_uncompress_byte_counter[2].ACLR -reset => burst_uncompress_busy.ACLR -sink_startofpacket => source_startofpacket.IN1 -sink_endofpacket => source_endofpacket.IN1 -sink_valid => first_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => last_packet_beat.IN1 -sink_valid => always0.IN1 -sink_valid => sink_ready.IN0 -sink_valid => source_valid.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -sink_addr[0] => burst_uncompress_address_base.IN0 -sink_addr[0] => comb.DATAB -sink_addr[0] => source_addr.DATAB -sink_addr[1] => burst_uncompress_address_base.IN0 -sink_addr[1] => comb.DATAB -sink_addr[1] => source_addr.DATAB -sink_addr[2] => burst_uncompress_address_base.IN0 -sink_addr[2] => comb.DATAB -sink_addr[2] => source_addr.DATAB -sink_addr[3] => burst_uncompress_address_base.IN0 -sink_addr[3] => comb.DATAB -sink_addr[3] => source_addr.DATAB -sink_addr[4] => burst_uncompress_address_base.IN0 -sink_addr[4] => comb.DATAB -sink_addr[4] => source_addr.DATAB -sink_addr[5] => burst_uncompress_address_base.IN0 -sink_addr[5] => comb.DATAB -sink_addr[5] => source_addr.DATAB -sink_addr[6] => burst_uncompress_address_base.IN0 -sink_addr[6] => comb.DATAB -sink_addr[6] => source_addr.DATAB -sink_addr[7] => burst_uncompress_address_base.IN0 -sink_addr[7] => comb.DATAB -sink_addr[7] => source_addr.DATAB -sink_addr[8] => burst_uncompress_address_base.IN0 -sink_addr[8] => comb.DATAB -sink_addr[8] => source_addr.DATAB -sink_addr[9] => burst_uncompress_address_base.IN0 -sink_addr[9] => comb.DATAB -sink_addr[9] => source_addr.DATAB -sink_addr[10] => burst_uncompress_address_base.IN0 -sink_addr[10] => comb.DATAB -sink_addr[10] => source_addr.DATAB -sink_addr[11] => burst_uncompress_address_base.IN0 -sink_addr[11] => comb.DATAB -sink_addr[11] => source_addr.DATAB -sink_addr[12] => burst_uncompress_address_base.IN0 -sink_addr[12] => comb.DATAB -sink_addr[12] => source_addr.DATAB -sink_addr[13] => burst_uncompress_address_base.IN0 -sink_addr[13] => comb.DATAB -sink_addr[13] => source_addr.DATAB -sink_addr[14] => burst_uncompress_address_base.IN0 -sink_addr[14] => comb.DATAB -sink_addr[14] => source_addr.DATAB -sink_addr[15] => burst_uncompress_address_base.IN0 -sink_addr[15] => comb.DATAB -sink_addr[15] => source_addr.DATAB -sink_addr[16] => burst_uncompress_address_base.IN0 -sink_addr[16] => comb.DATAB -sink_addr[16] => source_addr.DATAB -sink_addr[17] => burst_uncompress_address_base.IN0 -sink_addr[17] => comb.DATAB -sink_addr[17] => source_addr.DATAB -sink_addr[18] => burst_uncompress_address_base.IN0 -sink_addr[18] => comb.DATAB -sink_addr[18] => source_addr.DATAB -sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 -sink_burstwrap[0] => source_burstwrap[0].DATAIN -sink_burstwrap[0] => burst_uncompress_address_base.IN1 -sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 -sink_burstwrap[1] => source_burstwrap[1].DATAIN -sink_burstwrap[1] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 -sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 -sink_burstwrap[2] => source_burstwrap[2].DATAIN -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_burstwrap[2] => burst_uncompress_address_base.IN1 -sink_byte_cnt[0] => source_byte_cnt.DATAB -sink_byte_cnt[0] => Add1.IN6 -sink_byte_cnt[0] => Equal1.IN2 -sink_byte_cnt[1] => source_byte_cnt.DATAB -sink_byte_cnt[1] => Add1.IN5 -sink_byte_cnt[1] => Equal1.IN1 -sink_byte_cnt[2] => source_byte_cnt.DATAB -sink_byte_cnt[2] => Add1.IN4 -sink_byte_cnt[2] => Equal1.IN0 -sink_is_compressed => last_packet_beat.IN1 -sink_burstsize[0] => Decoder0.IN2 -sink_burstsize[0] => source_burstsize[0].DATAIN -sink_burstsize[1] => Decoder0.IN1 -sink_burstsize[1] => source_burstsize[1].DATAIN -sink_burstsize[2] => Decoder0.IN0 -sink_burstsize[2] => source_burstsize[2].DATAIN -source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -source_ready => always1.IN1 -source_ready => sink_ready.IN1 -source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE -source_is_compressed <= -source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE -source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -clk => csr_readdata[0]~reg0.CLK -clk => csr_readdata[1]~reg0.CLK -clk => csr_readdata[2]~reg0.CLK -clk => csr_readdata[3]~reg0.CLK -clk => csr_readdata[4]~reg0.CLK -clk => csr_readdata[5]~reg0.CLK -clk => csr_readdata[6]~reg0.CLK -clk => csr_readdata[7]~reg0.CLK -clk => csr_readdata[8]~reg0.CLK -clk => csr_readdata[9]~reg0.CLK -clk => csr_readdata[10]~reg0.CLK -clk => csr_readdata[11]~reg0.CLK -clk => csr_readdata[12]~reg0.CLK -clk => csr_readdata[13]~reg0.CLK -clk => csr_readdata[14]~reg0.CLK -clk => csr_readdata[15]~reg0.CLK -clk => csr_readdata[16]~reg0.CLK -clk => csr_readdata[17]~reg0.CLK -clk => csr_readdata[18]~reg0.CLK -clk => csr_readdata[19]~reg0.CLK -clk => csr_readdata[20]~reg0.CLK -clk => csr_readdata[21]~reg0.CLK -clk => csr_readdata[22]~reg0.CLK -clk => csr_readdata[23]~reg0.CLK -clk => csr_readdata[24]~reg0.CLK -clk => csr_readdata[25]~reg0.CLK -clk => csr_readdata[26]~reg0.CLK -clk => csr_readdata[27]~reg0.CLK -clk => csr_readdata[28]~reg0.CLK -clk => csr_readdata[29]~reg0.CLK -clk => csr_readdata[30]~reg0.CLK -clk => csr_readdata[31]~reg0.CLK -clk => mem_used[1].CLK -clk => mem_used[0].CLK -clk => mem[1][0].CLK -clk => mem[1][1].CLK -clk => mem[1][2].CLK -clk => mem[1][3].CLK -clk => mem[1][4].CLK -clk => mem[1][5].CLK -clk => mem[1][6].CLK -clk => mem[1][7].CLK -clk => mem[1][8].CLK -clk => mem[1][9].CLK -clk => mem[1][10].CLK -clk => mem[1][11].CLK -clk => mem[1][12].CLK -clk => mem[1][13].CLK -clk => mem[1][14].CLK -clk => mem[1][15].CLK -clk => mem[1][16].CLK -clk => mem[1][17].CLK -clk => mem[1][18].CLK -clk => mem[1][19].CLK -clk => mem[1][20].CLK -clk => mem[1][21].CLK -clk => mem[1][22].CLK -clk => mem[1][23].CLK -clk => mem[1][24].CLK -clk => mem[1][25].CLK -clk => mem[1][26].CLK -clk => mem[1][27].CLK -clk => mem[1][28].CLK -clk => mem[1][29].CLK -clk => mem[1][30].CLK -clk => mem[1][31].CLK -clk => mem[1][32].CLK -clk => mem[1][33].CLK -clk => mem[1][34].CLK -clk => mem[1][35].CLK -clk => mem[1][36].CLK -clk => mem[1][37].CLK -clk => mem[1][38].CLK -clk => mem[1][39].CLK -clk => mem[1][40].CLK -clk => mem[1][41].CLK -clk => mem[1][42].CLK -clk => mem[1][43].CLK -clk => mem[1][44].CLK -clk => mem[1][45].CLK -clk => mem[1][46].CLK -clk => mem[1][47].CLK -clk => mem[1][48].CLK -clk => mem[1][49].CLK -clk => mem[1][50].CLK -clk => mem[1][51].CLK -clk => mem[1][52].CLK -clk => mem[1][53].CLK -clk => mem[1][54].CLK -clk => mem[1][55].CLK -clk => mem[1][56].CLK -clk => mem[1][57].CLK -clk => mem[1][58].CLK -clk => mem[1][59].CLK -clk => mem[1][60].CLK -clk => mem[1][61].CLK -clk => mem[1][62].CLK -clk => mem[1][63].CLK -clk => mem[1][64].CLK -clk => mem[1][65].CLK -clk => mem[1][66].CLK -clk => mem[1][67].CLK -clk => mem[1][68].CLK -clk => mem[1][69].CLK -clk => mem[1][70].CLK -clk => mem[1][71].CLK -clk => mem[1][72].CLK -clk => mem[1][73].CLK -clk => mem[1][74].CLK -clk => mem[1][75].CLK -clk => mem[1][76].CLK -clk => mem[1][77].CLK -clk => mem[1][78].CLK -clk => mem[1][79].CLK -clk => mem[1][80].CLK -clk => mem[1][81].CLK -clk => mem[1][82].CLK -clk => mem[1][83].CLK -clk => mem[1][84].CLK -clk => mem[1][85].CLK -clk => mem[1][86].CLK -clk => mem[1][87].CLK -clk => mem[1][88].CLK -clk => mem[1][89].CLK -clk => mem[1][90].CLK -clk => mem[1][91].CLK -clk => mem[1][92].CLK -clk => mem[1][93].CLK -clk => mem[1][94].CLK -clk => mem[1][95].CLK -clk => mem[1][96].CLK -clk => mem[1][97].CLK -clk => mem[1][98].CLK -clk => mem[0][0].CLK -clk => mem[0][1].CLK -clk => mem[0][2].CLK -clk => mem[0][3].CLK -clk => mem[0][4].CLK -clk => mem[0][5].CLK -clk => mem[0][6].CLK -clk => mem[0][7].CLK -clk => mem[0][8].CLK -clk => mem[0][9].CLK -clk => mem[0][10].CLK -clk => mem[0][11].CLK -clk => mem[0][12].CLK -clk => mem[0][13].CLK -clk => mem[0][14].CLK -clk => mem[0][15].CLK -clk => mem[0][16].CLK -clk => mem[0][17].CLK -clk => mem[0][18].CLK -clk => mem[0][19].CLK -clk => mem[0][20].CLK -clk => mem[0][21].CLK -clk => mem[0][22].CLK -clk => mem[0][23].CLK -clk => mem[0][24].CLK -clk => mem[0][25].CLK -clk => mem[0][26].CLK -clk => mem[0][27].CLK -clk => mem[0][28].CLK -clk => mem[0][29].CLK -clk => mem[0][30].CLK -clk => mem[0][31].CLK -clk => mem[0][32].CLK -clk => mem[0][33].CLK -clk => mem[0][34].CLK -clk => mem[0][35].CLK -clk => mem[0][36].CLK -clk => mem[0][37].CLK -clk => mem[0][38].CLK -clk => mem[0][39].CLK -clk => mem[0][40].CLK -clk => mem[0][41].CLK -clk => mem[0][42].CLK -clk => mem[0][43].CLK -clk => mem[0][44].CLK -clk => mem[0][45].CLK -clk => mem[0][46].CLK -clk => mem[0][47].CLK -clk => mem[0][48].CLK -clk => mem[0][49].CLK -clk => mem[0][50].CLK -clk => mem[0][51].CLK -clk => mem[0][52].CLK -clk => mem[0][53].CLK -clk => mem[0][54].CLK -clk => mem[0][55].CLK -clk => mem[0][56].CLK -clk => mem[0][57].CLK -clk => mem[0][58].CLK -clk => mem[0][59].CLK -clk => mem[0][60].CLK -clk => mem[0][61].CLK -clk => mem[0][62].CLK -clk => mem[0][63].CLK -clk => mem[0][64].CLK -clk => mem[0][65].CLK -clk => mem[0][66].CLK -clk => mem[0][67].CLK -clk => mem[0][68].CLK -clk => mem[0][69].CLK -clk => mem[0][70].CLK -clk => mem[0][71].CLK -clk => mem[0][72].CLK -clk => mem[0][73].CLK -clk => mem[0][74].CLK -clk => mem[0][75].CLK -clk => mem[0][76].CLK -clk => mem[0][77].CLK -clk => mem[0][78].CLK -clk => mem[0][79].CLK -clk => mem[0][80].CLK -clk => mem[0][81].CLK -clk => mem[0][82].CLK -clk => mem[0][83].CLK -clk => mem[0][84].CLK -clk => mem[0][85].CLK -clk => mem[0][86].CLK -clk => mem[0][87].CLK -clk => mem[0][88].CLK -clk => mem[0][89].CLK -clk => mem[0][90].CLK -clk => mem[0][91].CLK -clk => mem[0][92].CLK -clk => mem[0][93].CLK -clk => mem[0][94].CLK -clk => mem[0][95].CLK -clk => mem[0][96].CLK -clk => mem[0][97].CLK -clk => mem[0][98].CLK -reset => csr_readdata[0]~reg0.ACLR -reset => csr_readdata[1]~reg0.ACLR -reset => csr_readdata[2]~reg0.ACLR -reset => csr_readdata[3]~reg0.ACLR -reset => csr_readdata[4]~reg0.ACLR -reset => csr_readdata[5]~reg0.ACLR -reset => csr_readdata[6]~reg0.ACLR -reset => csr_readdata[7]~reg0.ACLR -reset => csr_readdata[8]~reg0.ACLR -reset => csr_readdata[9]~reg0.ACLR -reset => csr_readdata[10]~reg0.ACLR -reset => csr_readdata[11]~reg0.ACLR -reset => csr_readdata[12]~reg0.ACLR -reset => csr_readdata[13]~reg0.ACLR -reset => csr_readdata[14]~reg0.ACLR -reset => csr_readdata[15]~reg0.ACLR -reset => csr_readdata[16]~reg0.ACLR -reset => csr_readdata[17]~reg0.ACLR -reset => csr_readdata[18]~reg0.ACLR -reset => csr_readdata[19]~reg0.ACLR -reset => csr_readdata[20]~reg0.ACLR -reset => csr_readdata[21]~reg0.ACLR -reset => csr_readdata[22]~reg0.ACLR -reset => csr_readdata[23]~reg0.ACLR -reset => csr_readdata[24]~reg0.ACLR -reset => csr_readdata[25]~reg0.ACLR -reset => csr_readdata[26]~reg0.ACLR -reset => csr_readdata[27]~reg0.ACLR -reset => csr_readdata[28]~reg0.ACLR -reset => csr_readdata[29]~reg0.ACLR -reset => csr_readdata[30]~reg0.ACLR -reset => csr_readdata[31]~reg0.ACLR -reset => mem_used[1].ACLR -reset => mem_used[0].ACLR -reset => mem[1][0].ACLR -reset => mem[1][1].ACLR -reset => mem[1][2].ACLR -reset => mem[1][3].ACLR -reset => mem[1][4].ACLR -reset => mem[1][5].ACLR -reset => mem[1][6].ACLR -reset => mem[1][7].ACLR -reset => mem[1][8].ACLR -reset => mem[1][9].ACLR -reset => mem[1][10].ACLR -reset => mem[1][11].ACLR -reset => mem[1][12].ACLR -reset => mem[1][13].ACLR -reset => mem[1][14].ACLR -reset => mem[1][15].ACLR -reset => mem[1][16].ACLR -reset => mem[1][17].ACLR -reset => mem[1][18].ACLR -reset => mem[1][19].ACLR -reset => mem[1][20].ACLR -reset => mem[1][21].ACLR -reset => mem[1][22].ACLR -reset => mem[1][23].ACLR -reset => mem[1][24].ACLR -reset => mem[1][25].ACLR -reset => mem[1][26].ACLR -reset => mem[1][27].ACLR -reset => mem[1][28].ACLR -reset => mem[1][29].ACLR -reset => mem[1][30].ACLR -reset => mem[1][31].ACLR -reset => mem[1][32].ACLR -reset => mem[1][33].ACLR -reset => mem[1][34].ACLR -reset => mem[1][35].ACLR -reset => mem[1][36].ACLR -reset => mem[1][37].ACLR -reset => mem[1][38].ACLR -reset => mem[1][39].ACLR -reset => mem[1][40].ACLR -reset => mem[1][41].ACLR -reset => mem[1][42].ACLR -reset => mem[1][43].ACLR -reset => mem[1][44].ACLR -reset => mem[1][45].ACLR -reset => mem[1][46].ACLR -reset => mem[1][47].ACLR -reset => mem[1][48].ACLR -reset => mem[1][49].ACLR -reset => mem[1][50].ACLR -reset => mem[1][51].ACLR -reset => mem[1][52].ACLR -reset => mem[1][53].ACLR -reset => mem[1][54].ACLR -reset => mem[1][55].ACLR -reset => mem[1][56].ACLR -reset => mem[1][57].ACLR -reset => mem[1][58].ACLR -reset => mem[1][59].ACLR -reset => mem[1][60].ACLR -reset => mem[1][61].ACLR -reset => mem[1][62].ACLR -reset => mem[1][63].ACLR -reset => mem[1][64].ACLR -reset => mem[1][65].ACLR -reset => mem[1][66].ACLR -reset => mem[1][67].ACLR -reset => mem[1][68].ACLR -reset => mem[1][69].ACLR -reset => mem[1][70].ACLR -reset => mem[1][71].ACLR -reset => mem[1][72].ACLR -reset => mem[1][73].ACLR -reset => mem[1][74].ACLR -reset => mem[1][75].ACLR -reset => mem[1][76].ACLR -reset => mem[1][77].ACLR -reset => mem[1][78].ACLR -reset => mem[1][79].ACLR -reset => mem[1][80].ACLR -reset => mem[1][81].ACLR -reset => mem[1][82].ACLR -reset => mem[1][83].ACLR -reset => mem[1][84].ACLR -reset => mem[1][85].ACLR -reset => mem[1][86].ACLR -reset => mem[1][87].ACLR -reset => mem[1][88].ACLR -reset => mem[1][89].ACLR -reset => mem[1][90].ACLR -reset => mem[1][91].ACLR -reset => mem[1][92].ACLR -reset => mem[1][93].ACLR -reset => mem[1][94].ACLR -reset => mem[1][95].ACLR -reset => mem[1][96].ACLR -reset => mem[1][97].ACLR -reset => mem[1][98].ACLR -reset => mem[0][0].ACLR -reset => mem[0][1].ACLR -reset => mem[0][2].ACLR -reset => mem[0][3].ACLR -reset => mem[0][4].ACLR -reset => mem[0][5].ACLR -reset => mem[0][6].ACLR -reset => mem[0][7].ACLR -reset => mem[0][8].ACLR -reset => mem[0][9].ACLR -reset => mem[0][10].ACLR -reset => mem[0][11].ACLR -reset => mem[0][12].ACLR -reset => mem[0][13].ACLR -reset => mem[0][14].ACLR -reset => mem[0][15].ACLR -reset => mem[0][16].ACLR -reset => mem[0][17].ACLR -reset => mem[0][18].ACLR -reset => mem[0][19].ACLR -reset => mem[0][20].ACLR -reset => mem[0][21].ACLR -reset => mem[0][22].ACLR -reset => mem[0][23].ACLR -reset => mem[0][24].ACLR -reset => mem[0][25].ACLR -reset => mem[0][26].ACLR -reset => mem[0][27].ACLR -reset => mem[0][28].ACLR -reset => mem[0][29].ACLR -reset => mem[0][30].ACLR -reset => mem[0][31].ACLR -reset => mem[0][32].ACLR -reset => mem[0][33].ACLR -reset => mem[0][34].ACLR -reset => mem[0][35].ACLR -reset => mem[0][36].ACLR -reset => mem[0][37].ACLR -reset => mem[0][38].ACLR -reset => mem[0][39].ACLR -reset => mem[0][40].ACLR -reset => mem[0][41].ACLR -reset => mem[0][42].ACLR -reset => mem[0][43].ACLR -reset => mem[0][44].ACLR -reset => mem[0][45].ACLR -reset => mem[0][46].ACLR -reset => mem[0][47].ACLR -reset => mem[0][48].ACLR -reset => mem[0][49].ACLR -reset => mem[0][50].ACLR -reset => mem[0][51].ACLR -reset => mem[0][52].ACLR -reset => mem[0][53].ACLR -reset => mem[0][54].ACLR -reset => mem[0][55].ACLR -reset => mem[0][56].ACLR -reset => mem[0][57].ACLR -reset => mem[0][58].ACLR -reset => mem[0][59].ACLR -reset => mem[0][60].ACLR -reset => mem[0][61].ACLR -reset => mem[0][62].ACLR -reset => mem[0][63].ACLR -reset => mem[0][64].ACLR -reset => mem[0][65].ACLR -reset => mem[0][66].ACLR -reset => mem[0][67].ACLR -reset => mem[0][68].ACLR -reset => mem[0][69].ACLR -reset => mem[0][70].ACLR -reset => mem[0][71].ACLR -reset => mem[0][72].ACLR -reset => mem[0][73].ACLR -reset => mem[0][74].ACLR -reset => mem[0][75].ACLR -reset => mem[0][76].ACLR -reset => mem[0][77].ACLR -reset => mem[0][78].ACLR -reset => mem[0][79].ACLR -reset => mem[0][80].ACLR -reset => mem[0][81].ACLR -reset => mem[0][82].ACLR -reset => mem[0][83].ACLR -reset => mem[0][84].ACLR -reset => mem[0][85].ACLR -reset => mem[0][86].ACLR -reset => mem[0][87].ACLR -reset => mem[0][88].ACLR -reset => mem[0][89].ACLR -reset => mem[0][90].ACLR -reset => mem[0][91].ACLR -reset => mem[0][92].ACLR -reset => mem[0][93].ACLR -reset => mem[0][94].ACLR -reset => mem[0][95].ACLR -reset => mem[0][96].ACLR -reset => mem[0][97].ACLR -reset => mem[0][98].ACLR -in_data[0] => mem.DATAB -in_data[1] => mem.DATAB -in_data[2] => mem.DATAB -in_data[3] => mem.DATAB -in_data[4] => mem.DATAB -in_data[5] => mem.DATAB -in_data[6] => mem.DATAB -in_data[7] => mem.DATAB -in_data[8] => mem.DATAB -in_data[9] => mem.DATAB -in_data[10] => mem.DATAB -in_data[11] => mem.DATAB -in_data[12] => mem.DATAB -in_data[13] => mem.DATAB -in_data[14] => mem.DATAB -in_data[15] => mem.DATAB -in_data[16] => mem.DATAB -in_data[17] => mem.DATAB -in_data[18] => mem.DATAB -in_data[19] => mem.DATAB -in_data[20] => mem.DATAB -in_data[21] => mem.DATAB -in_data[22] => mem.DATAB -in_data[23] => mem.DATAB -in_data[24] => mem.DATAB -in_data[25] => mem.DATAB -in_data[26] => mem.DATAB -in_data[27] => mem.DATAB -in_data[28] => mem.DATAB -in_data[29] => mem.DATAB -in_data[30] => mem.DATAB -in_data[31] => mem.DATAB -in_data[32] => mem.DATAB -in_data[33] => mem.DATAB -in_data[34] => mem.DATAB -in_data[35] => mem.DATAB -in_data[36] => mem.DATAB -in_data[37] => mem.DATAB -in_data[38] => mem.DATAB -in_data[39] => mem.DATAB -in_data[40] => mem.DATAB -in_data[41] => mem.DATAB -in_data[42] => mem.DATAB -in_data[43] => mem.DATAB -in_data[44] => mem.DATAB -in_data[45] => mem.DATAB -in_data[46] => mem.DATAB -in_data[47] => mem.DATAB -in_data[48] => mem.DATAB -in_data[49] => mem.DATAB -in_data[50] => mem.DATAB -in_data[51] => mem.DATAB -in_data[52] => mem.DATAB -in_data[53] => mem.DATAB -in_data[54] => mem.DATAB -in_data[55] => mem.DATAB -in_data[56] => mem.DATAB -in_data[57] => mem.DATAB -in_data[58] => mem.DATAB -in_data[59] => mem.DATAB -in_data[60] => mem.DATAB -in_data[61] => mem.DATAB -in_data[62] => mem.DATAB -in_data[63] => mem.DATAB -in_data[64] => mem.DATAB -in_data[65] => mem.DATAB -in_data[66] => mem.DATAB -in_data[67] => mem.DATAB -in_data[68] => mem.DATAB -in_data[69] => mem.DATAB -in_data[70] => mem.DATAB -in_data[71] => mem.DATAB -in_data[72] => mem.DATAB -in_data[73] => mem.DATAB -in_data[74] => mem.DATAB -in_data[75] => mem.DATAB -in_data[76] => mem.DATAB -in_data[77] => mem.DATAB -in_data[78] => mem.DATAB -in_data[79] => mem.DATAB -in_data[80] => mem.DATAB -in_data[81] => mem.DATAB -in_data[82] => mem.DATAB -in_data[83] => mem.DATAB -in_data[84] => mem.DATAB -in_data[85] => mem.DATAB -in_data[86] => mem.DATAB -in_data[87] => mem.DATAB -in_data[88] => mem.DATAB -in_data[89] => mem.DATAB -in_data[90] => mem.DATAB -in_data[91] => mem.DATAB -in_data[92] => mem.DATAB -in_data[93] => mem.DATAB -in_data[94] => mem.DATAB -in_data[95] => mem.DATAB -in_data[96] => mem.DATAB -in_valid => write.IN1 -in_startofpacket => mem.DATAB -in_endofpacket => mem.DATAB -in_empty[0] => ~NO_FANOUT~ -in_error[0] => out_error[0].DATAIN -in_error[0] => out_empty[0].DATAIN -in_channel[0] => out_channel[0].DATAIN -in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE -out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE -out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE -out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE -out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE -out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE -out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE -out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE -out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE -out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE -out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE -out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE -out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE -out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE -out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE -out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE -out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE -out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE -out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE -out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE -out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE -out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE -out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE -out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE -out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE -out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE -out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE -out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE -out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE -out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE -out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE -out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE -out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE -out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE -out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE -out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE -out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE -out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE -out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE -out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE -out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE -out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE -out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE -out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE -out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE -out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE -out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE -out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE -out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE -out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE -out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE -out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE -out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE -out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE -out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE -out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE -out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE -out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE -out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE -out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE -out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE -out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE -out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE -out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE -out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE -out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE -out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE -out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE -out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE -out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE -out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE -out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE -out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE -out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE -out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE -out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE -out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE -out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE -out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE -out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE -out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE -out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE -out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE -out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE -out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE -out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE -out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE -out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE -out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE -out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE -out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE -out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE -out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE -out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE -out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE -out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE -out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE -out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE -out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE -out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE -out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE -out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE -out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE -out_ready => internal_out_ready.IN1 -csr_address[0] => ~NO_FANOUT~ -csr_address[1] => ~NO_FANOUT~ -csr_write => ~NO_FANOUT~ -csr_read => csr_readdata[31]~reg0.ENA -csr_read => csr_readdata[30]~reg0.ENA -csr_read => csr_readdata[29]~reg0.ENA -csr_read => csr_readdata[28]~reg0.ENA -csr_read => csr_readdata[27]~reg0.ENA -csr_read => csr_readdata[26]~reg0.ENA -csr_read => csr_readdata[25]~reg0.ENA -csr_read => csr_readdata[24]~reg0.ENA -csr_read => csr_readdata[23]~reg0.ENA -csr_read => csr_readdata[22]~reg0.ENA -csr_read => csr_readdata[21]~reg0.ENA -csr_read => csr_readdata[20]~reg0.ENA -csr_read => csr_readdata[19]~reg0.ENA -csr_read => csr_readdata[18]~reg0.ENA -csr_read => csr_readdata[17]~reg0.ENA -csr_read => csr_readdata[16]~reg0.ENA -csr_read => csr_readdata[15]~reg0.ENA -csr_read => csr_readdata[14]~reg0.ENA -csr_read => csr_readdata[13]~reg0.ENA -csr_read => csr_readdata[12]~reg0.ENA -csr_read => csr_readdata[11]~reg0.ENA -csr_read => csr_readdata[10]~reg0.ENA -csr_read => csr_readdata[9]~reg0.ENA -csr_read => csr_readdata[8]~reg0.ENA -csr_read => csr_readdata[7]~reg0.ENA -csr_read => csr_readdata[6]~reg0.ENA -csr_read => csr_readdata[5]~reg0.ENA -csr_read => csr_readdata[4]~reg0.ENA -csr_read => csr_readdata[3]~reg0.ENA -csr_read => csr_readdata[2]~reg0.ENA -csr_read => csr_readdata[1]~reg0.ENA -csr_read => csr_readdata[0]~reg0.ENA -csr_writedata[0] => ~NO_FANOUT~ -csr_writedata[1] => ~NO_FANOUT~ -csr_writedata[2] => ~NO_FANOUT~ -csr_writedata[3] => ~NO_FANOUT~ -csr_writedata[4] => ~NO_FANOUT~ -csr_writedata[5] => ~NO_FANOUT~ -csr_writedata[6] => ~NO_FANOUT~ -csr_writedata[7] => ~NO_FANOUT~ -csr_writedata[8] => ~NO_FANOUT~ -csr_writedata[9] => ~NO_FANOUT~ -csr_writedata[10] => ~NO_FANOUT~ -csr_writedata[11] => ~NO_FANOUT~ -csr_writedata[12] => ~NO_FANOUT~ -csr_writedata[13] => ~NO_FANOUT~ -csr_writedata[14] => ~NO_FANOUT~ -csr_writedata[15] => ~NO_FANOUT~ -csr_writedata[16] => ~NO_FANOUT~ -csr_writedata[17] => ~NO_FANOUT~ -csr_writedata[18] => ~NO_FANOUT~ -csr_writedata[19] => ~NO_FANOUT~ -csr_writedata[20] => ~NO_FANOUT~ -csr_writedata[21] => ~NO_FANOUT~ -csr_writedata[22] => ~NO_FANOUT~ -csr_writedata[23] => ~NO_FANOUT~ -csr_writedata[24] => ~NO_FANOUT~ -csr_writedata[25] => ~NO_FANOUT~ -csr_writedata[26] => ~NO_FANOUT~ -csr_writedata[27] => ~NO_FANOUT~ -csr_writedata[28] => ~NO_FANOUT~ -csr_writedata[29] => ~NO_FANOUT~ -csr_writedata[30] => ~NO_FANOUT~ -csr_writedata[31] => ~NO_FANOUT~ -csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE -csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE -almost_full_data <= -almost_empty_data <= - - -|lights|nios_system:NiosII|nios_system_addr_router:addr_router -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[47] => Equal0.IN1 -sink_data[48] => src_data[48].DATAIN -sink_data[48] => Equal0.IN7 -sink_data[49] => src_data[49].DATAIN -sink_data[49] => Equal0.IN6 -sink_data[50] => src_data[50].DATAIN -sink_data[50] => Equal0.IN5 -sink_data[51] => src_data[51].DATAIN -sink_data[51] => Equal0.IN4 -sink_data[52] => src_data[52].DATAIN -sink_data[52] => Equal0.IN3 -sink_data[53] => src_data[53].DATAIN -sink_data[53] => Equal0.IN2 -sink_data[54] => src_data[54].DATAIN -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => Equal0.IN0 -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => ~NO_FANOUT~ -sink_data[82] => ~NO_FANOUT~ -sink_data[83] => ~NO_FANOUT~ -sink_data[84] => ~NO_FANOUT~ -sink_data[85] => ~NO_FANOUT~ -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[39] => Equal16.IN15 -sink_data[40] => src_data[40].DATAIN -sink_data[40] => Equal1.IN2 -sink_data[40] => Equal2.IN14 -sink_data[40] => Equal3.IN3 -sink_data[40] => Equal4.IN14 -sink_data[40] => Equal5.IN3 -sink_data[40] => Equal6.IN14 -sink_data[40] => Equal7.IN4 -sink_data[40] => Equal8.IN14 -sink_data[40] => Equal9.IN3 -sink_data[40] => Equal10.IN14 -sink_data[40] => Equal11.IN4 -sink_data[40] => Equal12.IN14 -sink_data[40] => Equal13.IN4 -sink_data[40] => Equal14.IN14 -sink_data[40] => Equal15.IN5 -sink_data[40] => Equal16.IN14 -sink_data[41] => src_data[41].DATAIN -sink_data[41] => Equal1.IN14 -sink_data[41] => Equal2.IN2 -sink_data[41] => Equal3.IN2 -sink_data[41] => Equal4.IN13 -sink_data[41] => Equal5.IN14 -sink_data[41] => Equal6.IN3 -sink_data[41] => Equal7.IN3 -sink_data[41] => Equal8.IN13 -sink_data[41] => Equal9.IN14 -sink_data[41] => Equal10.IN3 -sink_data[41] => Equal11.IN3 -sink_data[41] => Equal12.IN13 -sink_data[41] => Equal13.IN14 -sink_data[41] => Equal14.IN4 -sink_data[41] => Equal15.IN4 -sink_data[41] => Equal16.IN13 -sink_data[42] => src_data[42].DATAIN -sink_data[42] => Equal1.IN13 -sink_data[42] => Equal2.IN13 -sink_data[42] => Equal3.IN14 -sink_data[42] => Equal4.IN2 -sink_data[42] => Equal5.IN2 -sink_data[42] => Equal6.IN2 -sink_data[42] => Equal7.IN2 -sink_data[42] => Equal8.IN12 -sink_data[42] => Equal9.IN13 -sink_data[42] => Equal10.IN13 -sink_data[42] => Equal11.IN14 -sink_data[42] => Equal12.IN3 -sink_data[42] => Equal13.IN3 -sink_data[42] => Equal14.IN3 -sink_data[42] => Equal15.IN3 -sink_data[42] => Equal16.IN12 -sink_data[43] => src_data[43].DATAIN -sink_data[43] => Equal1.IN12 -sink_data[43] => Equal2.IN12 -sink_data[43] => Equal3.IN13 -sink_data[43] => Equal4.IN12 -sink_data[43] => Equal5.IN13 -sink_data[43] => Equal6.IN13 -sink_data[43] => Equal7.IN14 -sink_data[43] => Equal8.IN2 -sink_data[43] => Equal9.IN2 -sink_data[43] => Equal10.IN2 -sink_data[43] => Equal11.IN2 -sink_data[43] => Equal12.IN2 -sink_data[43] => Equal13.IN2 -sink_data[43] => Equal14.IN2 -sink_data[43] => Equal15.IN2 -sink_data[43] => Equal16.IN11 -sink_data[44] => src_data[44].DATAIN -sink_data[44] => Equal1.IN11 -sink_data[44] => Equal2.IN11 -sink_data[44] => Equal3.IN12 -sink_data[44] => Equal4.IN11 -sink_data[44] => Equal5.IN12 -sink_data[44] => Equal6.IN12 -sink_data[44] => Equal7.IN13 -sink_data[44] => Equal8.IN11 -sink_data[44] => Equal9.IN12 -sink_data[44] => Equal10.IN12 -sink_data[44] => Equal11.IN13 -sink_data[44] => Equal12.IN12 -sink_data[44] => Equal13.IN13 -sink_data[44] => Equal14.IN13 -sink_data[44] => Equal15.IN14 -sink_data[44] => Equal16.IN2 -sink_data[45] => src_data[45].DATAIN -sink_data[45] => Equal1.IN10 -sink_data[45] => Equal2.IN10 -sink_data[45] => Equal3.IN11 -sink_data[45] => Equal4.IN10 -sink_data[45] => Equal5.IN11 -sink_data[45] => Equal6.IN11 -sink_data[45] => Equal7.IN12 -sink_data[45] => Equal8.IN10 -sink_data[45] => Equal9.IN11 -sink_data[45] => Equal10.IN11 -sink_data[45] => Equal11.IN12 -sink_data[45] => Equal12.IN11 -sink_data[45] => Equal13.IN12 -sink_data[45] => Equal14.IN12 -sink_data[45] => Equal15.IN13 -sink_data[45] => Equal16.IN10 -sink_data[46] => src_data[46].DATAIN -sink_data[46] => Equal1.IN9 -sink_data[46] => Equal2.IN9 -sink_data[46] => Equal3.IN10 -sink_data[46] => Equal4.IN9 -sink_data[46] => Equal5.IN10 -sink_data[46] => Equal6.IN10 -sink_data[46] => Equal7.IN11 -sink_data[46] => Equal8.IN9 -sink_data[46] => Equal9.IN10 -sink_data[46] => Equal10.IN10 -sink_data[46] => Equal11.IN11 -sink_data[46] => Equal12.IN10 -sink_data[46] => Equal13.IN11 -sink_data[46] => Equal14.IN11 -sink_data[46] => Equal15.IN12 -sink_data[46] => Equal16.IN9 -sink_data[47] => src_data[47].DATAIN -sink_data[47] => Equal0.IN1 -sink_data[47] => Equal1.IN8 -sink_data[47] => Equal2.IN8 -sink_data[47] => Equal3.IN9 -sink_data[47] => Equal4.IN8 -sink_data[47] => Equal5.IN9 -sink_data[47] => Equal6.IN9 -sink_data[47] => Equal7.IN10 -sink_data[47] => Equal8.IN8 -sink_data[47] => Equal9.IN9 -sink_data[47] => Equal10.IN9 -sink_data[47] => Equal11.IN10 -sink_data[47] => Equal12.IN9 -sink_data[47] => Equal13.IN10 -sink_data[47] => Equal14.IN10 -sink_data[47] => Equal15.IN11 -sink_data[47] => Equal16.IN8 -sink_data[48] => src_data[48].DATAIN -sink_data[48] => Equal0.IN7 -sink_data[48] => Equal1.IN1 -sink_data[48] => Equal2.IN1 -sink_data[48] => Equal3.IN1 -sink_data[48] => Equal4.IN1 -sink_data[48] => Equal5.IN1 -sink_data[48] => Equal6.IN1 -sink_data[48] => Equal7.IN1 -sink_data[48] => Equal8.IN1 -sink_data[48] => Equal9.IN1 -sink_data[48] => Equal10.IN1 -sink_data[48] => Equal11.IN1 -sink_data[48] => Equal12.IN1 -sink_data[48] => Equal13.IN1 -sink_data[48] => Equal14.IN1 -sink_data[48] => Equal15.IN1 -sink_data[48] => Equal16.IN1 -sink_data[49] => src_data[49].DATAIN -sink_data[49] => Equal0.IN6 -sink_data[49] => Equal1.IN7 -sink_data[49] => Equal2.IN7 -sink_data[49] => Equal3.IN8 -sink_data[49] => Equal4.IN7 -sink_data[49] => Equal5.IN8 -sink_data[49] => Equal6.IN8 -sink_data[49] => Equal7.IN9 -sink_data[49] => Equal8.IN7 -sink_data[49] => Equal9.IN8 -sink_data[49] => Equal10.IN8 -sink_data[49] => Equal11.IN9 -sink_data[49] => Equal12.IN8 -sink_data[49] => Equal13.IN9 -sink_data[49] => Equal14.IN9 -sink_data[49] => Equal15.IN10 -sink_data[49] => Equal16.IN7 -sink_data[50] => src_data[50].DATAIN -sink_data[50] => Equal0.IN5 -sink_data[50] => Equal1.IN6 -sink_data[50] => Equal2.IN6 -sink_data[50] => Equal3.IN7 -sink_data[50] => Equal4.IN6 -sink_data[50] => Equal5.IN7 -sink_data[50] => Equal6.IN7 -sink_data[50] => Equal7.IN8 -sink_data[50] => Equal8.IN6 -sink_data[50] => Equal9.IN7 -sink_data[50] => Equal10.IN7 -sink_data[50] => Equal11.IN8 -sink_data[50] => Equal12.IN7 -sink_data[50] => Equal13.IN8 -sink_data[50] => Equal14.IN8 -sink_data[50] => Equal15.IN9 -sink_data[50] => Equal16.IN6 -sink_data[51] => src_data[51].DATAIN -sink_data[51] => Equal0.IN4 -sink_data[51] => Equal1.IN5 -sink_data[51] => Equal2.IN5 -sink_data[51] => Equal3.IN6 -sink_data[51] => Equal4.IN5 -sink_data[51] => Equal5.IN6 -sink_data[51] => Equal6.IN6 -sink_data[51] => Equal7.IN7 -sink_data[51] => Equal8.IN5 -sink_data[51] => Equal9.IN6 -sink_data[51] => Equal10.IN6 -sink_data[51] => Equal11.IN7 -sink_data[51] => Equal12.IN6 -sink_data[51] => Equal13.IN7 -sink_data[51] => Equal14.IN7 -sink_data[51] => Equal15.IN8 -sink_data[51] => Equal16.IN5 -sink_data[52] => src_data[52].DATAIN -sink_data[52] => Equal0.IN3 -sink_data[52] => Equal1.IN4 -sink_data[52] => Equal2.IN4 -sink_data[52] => Equal3.IN5 -sink_data[52] => Equal4.IN4 -sink_data[52] => Equal5.IN5 -sink_data[52] => Equal6.IN5 -sink_data[52] => Equal7.IN6 -sink_data[52] => Equal8.IN4 -sink_data[52] => Equal9.IN5 -sink_data[52] => Equal10.IN5 -sink_data[52] => Equal11.IN6 -sink_data[52] => Equal12.IN5 -sink_data[52] => Equal13.IN6 -sink_data[52] => Equal14.IN6 -sink_data[52] => Equal15.IN7 -sink_data[52] => Equal16.IN4 -sink_data[53] => src_data[53].DATAIN -sink_data[53] => Equal0.IN2 -sink_data[53] => Equal1.IN3 -sink_data[53] => Equal2.IN3 -sink_data[53] => Equal3.IN4 -sink_data[53] => Equal4.IN3 -sink_data[53] => Equal5.IN4 -sink_data[53] => Equal6.IN4 -sink_data[53] => Equal7.IN5 -sink_data[53] => Equal8.IN3 -sink_data[53] => Equal9.IN4 -sink_data[53] => Equal10.IN4 -sink_data[53] => Equal11.IN5 -sink_data[53] => Equal12.IN4 -sink_data[53] => Equal13.IN5 -sink_data[53] => Equal14.IN5 -sink_data[53] => Equal15.IN6 -sink_data[53] => Equal16.IN3 -sink_data[54] => src_data[54].DATAIN -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_channel.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => src_data.OUTPUTSELECT -sink_data[54] => Equal0.IN0 -sink_data[54] => Equal1.IN0 -sink_data[54] => Equal2.IN0 -sink_data[54] => Equal3.IN0 -sink_data[54] => Equal4.IN0 -sink_data[54] => Equal5.IN0 -sink_data[54] => Equal6.IN0 -sink_data[54] => Equal7.IN0 -sink_data[54] => Equal8.IN0 -sink_data[54] => Equal9.IN0 -sink_data[54] => Equal10.IN0 -sink_data[54] => Equal11.IN0 -sink_data[54] => Equal12.IN0 -sink_data[54] => Equal13.IN0 -sink_data[54] => Equal14.IN0 -sink_data[54] => Equal15.IN0 -sink_data[54] => Equal16.IN0 -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => ~NO_FANOUT~ -sink_data[82] => ~NO_FANOUT~ -sink_data[83] => ~NO_FANOUT~ -sink_data[84] => ~NO_FANOUT~ -sink_data[85] => ~NO_FANOUT~ -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_data.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router:id_router -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN0 -sink_data[81] => Equal1.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN31 -sink_data[82] => Equal1.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN30 -sink_data[83] => Equal1.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN29 -sink_data[84] => Equal1.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN28 -sink_data[85] => Equal1.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router:id_router_001 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN0 -sink_data[81] => Equal1.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN31 -sink_data[82] => Equal1.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN30 -sink_data[83] => Equal1.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN29 -sink_data[84] => Equal1.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN28 -sink_data[85] => Equal1.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_002 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_003 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_004 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_005 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_006 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_007 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_008 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_009 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_010 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_011 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_012 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_013 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_014 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_015 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_016 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_017 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -sink_valid => src_valid.DATAIN -sink_data[0] => src_data[0].DATAIN -sink_data[1] => src_data[1].DATAIN -sink_data[2] => src_data[2].DATAIN -sink_data[3] => src_data[3].DATAIN -sink_data[4] => src_data[4].DATAIN -sink_data[5] => src_data[5].DATAIN -sink_data[6] => src_data[6].DATAIN -sink_data[7] => src_data[7].DATAIN -sink_data[8] => src_data[8].DATAIN -sink_data[9] => src_data[9].DATAIN -sink_data[10] => src_data[10].DATAIN -sink_data[11] => src_data[11].DATAIN -sink_data[12] => src_data[12].DATAIN -sink_data[13] => src_data[13].DATAIN -sink_data[14] => src_data[14].DATAIN -sink_data[15] => src_data[15].DATAIN -sink_data[16] => src_data[16].DATAIN -sink_data[17] => src_data[17].DATAIN -sink_data[18] => src_data[18].DATAIN -sink_data[19] => src_data[19].DATAIN -sink_data[20] => src_data[20].DATAIN -sink_data[21] => src_data[21].DATAIN -sink_data[22] => src_data[22].DATAIN -sink_data[23] => src_data[23].DATAIN -sink_data[24] => src_data[24].DATAIN -sink_data[25] => src_data[25].DATAIN -sink_data[26] => src_data[26].DATAIN -sink_data[27] => src_data[27].DATAIN -sink_data[28] => src_data[28].DATAIN -sink_data[29] => src_data[29].DATAIN -sink_data[30] => src_data[30].DATAIN -sink_data[31] => src_data[31].DATAIN -sink_data[32] => src_data[32].DATAIN -sink_data[33] => src_data[33].DATAIN -sink_data[34] => src_data[34].DATAIN -sink_data[35] => src_data[35].DATAIN -sink_data[36] => src_data[36].DATAIN -sink_data[37] => src_data[37].DATAIN -sink_data[38] => src_data[38].DATAIN -sink_data[39] => src_data[39].DATAIN -sink_data[40] => src_data[40].DATAIN -sink_data[41] => src_data[41].DATAIN -sink_data[42] => src_data[42].DATAIN -sink_data[43] => src_data[43].DATAIN -sink_data[44] => src_data[44].DATAIN -sink_data[45] => src_data[45].DATAIN -sink_data[46] => src_data[46].DATAIN -sink_data[47] => src_data[47].DATAIN -sink_data[48] => src_data[48].DATAIN -sink_data[49] => src_data[49].DATAIN -sink_data[50] => src_data[50].DATAIN -sink_data[51] => src_data[51].DATAIN -sink_data[52] => src_data[52].DATAIN -sink_data[53] => src_data[53].DATAIN -sink_data[54] => src_data[54].DATAIN -sink_data[55] => src_data[55].DATAIN -sink_data[56] => src_data[56].DATAIN -sink_data[57] => src_data[57].DATAIN -sink_data[58] => src_data[58].DATAIN -sink_data[59] => src_data[59].DATAIN -sink_data[60] => src_data[60].DATAIN -sink_data[61] => src_data[61].DATAIN -sink_data[62] => src_data[62].DATAIN -sink_data[63] => src_data[63].DATAIN -sink_data[64] => src_data[64].DATAIN -sink_data[65] => src_data[65].DATAIN -sink_data[66] => src_data[66].DATAIN -sink_data[67] => src_data[67].DATAIN -sink_data[68] => src_data[68].DATAIN -sink_data[69] => src_data[69].DATAIN -sink_data[70] => src_data[70].DATAIN -sink_data[71] => src_data[71].DATAIN -sink_data[72] => src_data[72].DATAIN -sink_data[73] => src_data[73].DATAIN -sink_data[74] => src_data[74].DATAIN -sink_data[75] => src_data[75].DATAIN -sink_data[76] => src_data[76].DATAIN -sink_data[77] => src_data[77].DATAIN -sink_data[78] => src_data[78].DATAIN -sink_data[79] => src_data[79].DATAIN -sink_data[80] => src_data[80].DATAIN -sink_data[81] => src_data[81].DATAIN -sink_data[81] => Equal0.IN31 -sink_data[82] => src_data[82].DATAIN -sink_data[82] => Equal0.IN30 -sink_data[83] => src_data[83].DATAIN -sink_data[83] => Equal0.IN29 -sink_data[84] => src_data[84].DATAIN -sink_data[84] => Equal0.IN28 -sink_data[85] => src_data[85].DATAIN -sink_data[85] => Equal0.IN27 -sink_data[86] => src_data[86].DATAIN -sink_data[87] => src_data[87].DATAIN -sink_data[88] => src_data[88].DATAIN -sink_data[89] => src_data[89].DATAIN -sink_data[90] => src_data[90].DATAIN -sink_data[91] => src_data[91].DATAIN -sink_data[92] => src_data[92].DATAIN -sink_data[93] => src_data[93].DATAIN -sink_data[94] => src_data[94].DATAIN -sink_data[95] => src_data[95].DATAIN -sink_startofpacket => src_startofpacket.DATAIN -sink_endofpacket => src_endofpacket.DATAIN -sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src_ready => sink_ready.DATAIN - - -|lights|nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode -default_destination_id[0] <= -default_destination_id[1] <= -default_destination_id[2] <= -default_destination_id[3] <= -default_destination_id[4] <= -default_wr_channel[0] <= -default_wr_channel[1] <= -default_wr_channel[2] <= -default_wr_channel[3] <= -default_wr_channel[4] <= -default_wr_channel[5] <= -default_wr_channel[6] <= -default_wr_channel[7] <= -default_wr_channel[8] <= -default_wr_channel[9] <= -default_wr_channel[10] <= -default_wr_channel[11] <= -default_wr_channel[12] <= -default_wr_channel[13] <= -default_wr_channel[14] <= -default_wr_channel[15] <= -default_wr_channel[16] <= -default_wr_channel[17] <= -default_rd_channel[0] <= -default_rd_channel[1] <= -default_rd_channel[2] <= -default_rd_channel[3] <= -default_rd_channel[4] <= -default_rd_channel[5] <= -default_rd_channel[6] <= -default_rd_channel[7] <= -default_rd_channel[8] <= -default_rd_channel[9] <= -default_rd_channel[10] <= -default_rd_channel[11] <= -default_rd_channel[12] <= -default_rd_channel[13] <= -default_rd_channel[14] <= -default_rd_channel[15] <= -default_rd_channel[16] <= -default_rd_channel[17] <= -default_src_channel[0] <= -default_src_channel[1] <= -default_src_channel[2] <= -default_src_channel[3] <= -default_src_channel[4] <= -default_src_channel[5] <= -default_src_channel[6] <= -default_src_channel[7] <= -default_src_channel[8] <= -default_src_channel[9] <= -default_src_channel[10] <= -default_src_channel[11] <= -default_src_channel[12] <= -default_src_channel[13] <= -default_src_channel[14] <= -default_src_channel[15] <= -default_src_channel[16] <= -default_src_channel[17] <= - - -|lights|nios_system:NiosII|altera_reset_controller:rst_controller -reset_in0 => merged_reset.IN0 -reset_in1 => merged_reset.IN1 -reset_in2 => merged_reset.IN1 -reset_in3 => merged_reset.IN1 -reset_in4 => merged_reset.IN1 -reset_in5 => merged_reset.IN1 -reset_in6 => merged_reset.IN1 -reset_in7 => merged_reset.IN1 -reset_in8 => merged_reset.IN1 -reset_in9 => merged_reset.IN1 -reset_in10 => merged_reset.IN1 -reset_in11 => merged_reset.IN1 -reset_in12 => merged_reset.IN1 -reset_in13 => merged_reset.IN1 -reset_in14 => merged_reset.IN1 -reset_in15 => merged_reset.IN1 -clk => clk.IN1 -reset_out <= r_sync_rst.DB_MAX_OUTPUT_PORT_TYPE -reset_req <= r_early_rst.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -reset_in => altera_reset_synchronizer_int_chain_out.PRESET -reset_in => altera_reset_synchronizer_int_chain[0].PRESET -reset_in => altera_reset_synchronizer_int_chain[1].PRESET -clk => altera_reset_synchronizer_int_chain_out.CLK -clk => altera_reset_synchronizer_int_chain[0].CLK -clk => altera_reset_synchronizer_int_chain[1].CLK -reset_out <= altera_reset_synchronizer_int_chain_out.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src1_channel[0].DATAIN -sink_channel[2] => src0_channel[0].DATAIN -sink_channel[3] => src1_channel[1].DATAIN -sink_channel[3] => src0_channel[1].DATAIN -sink_channel[4] => src1_channel[2].DATAIN -sink_channel[4] => src0_channel[2].DATAIN -sink_channel[5] => src1_channel[3].DATAIN -sink_channel[5] => src0_channel[3].DATAIN -sink_channel[6] => src1_channel[4].DATAIN -sink_channel[6] => src0_channel[4].DATAIN -sink_channel[7] => src1_channel[5].DATAIN -sink_channel[7] => src0_channel[5].DATAIN -sink_channel[8] => src1_channel[6].DATAIN -sink_channel[8] => src0_channel[6].DATAIN -sink_channel[9] => src1_channel[7].DATAIN -sink_channel[9] => src0_channel[7].DATAIN -sink_channel[10] => src1_channel[8].DATAIN -sink_channel[10] => src0_channel[8].DATAIN -sink_channel[11] => src1_channel[9].DATAIN -sink_channel[11] => src0_channel[9].DATAIN -sink_channel[12] => src1_channel[10].DATAIN -sink_channel[12] => src0_channel[10].DATAIN -sink_channel[13] => src1_channel[11].DATAIN -sink_channel[13] => src0_channel[11].DATAIN -sink_channel[14] => src1_channel[12].DATAIN -sink_channel[14] => src0_channel[12].DATAIN -sink_channel[15] => src1_channel[13].DATAIN -sink_channel[15] => src0_channel[13].DATAIN -sink_channel[16] => src1_channel[14].DATAIN -sink_channel[16] => src0_channel[14].DATAIN -sink_channel[17] => src1_channel[15].DATAIN -sink_channel[17] => src0_channel[15].DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_valid[0] => src2_valid.IN0 -sink_valid[0] => src3_valid.IN0 -sink_valid[0] => src4_valid.IN0 -sink_valid[0] => src5_valid.IN0 -sink_valid[0] => src6_valid.IN0 -sink_valid[0] => src7_valid.IN0 -sink_valid[0] => src8_valid.IN0 -sink_valid[0] => src9_valid.IN0 -sink_valid[0] => src10_valid.IN0 -sink_valid[0] => src11_valid.IN0 -sink_valid[0] => src12_valid.IN0 -sink_valid[0] => src13_valid.IN0 -sink_valid[0] => src14_valid.IN0 -sink_valid[0] => src15_valid.IN0 -sink_valid[0] => src16_valid.IN0 -sink_valid[0] => src17_valid.IN0 -sink_data[0] => src17_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src2_data[0].DATAIN -sink_data[0] => src3_data[0].DATAIN -sink_data[0] => src4_data[0].DATAIN -sink_data[0] => src5_data[0].DATAIN -sink_data[0] => src6_data[0].DATAIN -sink_data[0] => src7_data[0].DATAIN -sink_data[0] => src8_data[0].DATAIN -sink_data[0] => src9_data[0].DATAIN -sink_data[0] => src10_data[0].DATAIN -sink_data[0] => src11_data[0].DATAIN -sink_data[0] => src12_data[0].DATAIN -sink_data[0] => src13_data[0].DATAIN -sink_data[0] => src14_data[0].DATAIN -sink_data[0] => src15_data[0].DATAIN -sink_data[0] => src16_data[0].DATAIN -sink_data[1] => src17_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src2_data[1].DATAIN -sink_data[1] => src3_data[1].DATAIN -sink_data[1] => src4_data[1].DATAIN -sink_data[1] => src5_data[1].DATAIN -sink_data[1] => src6_data[1].DATAIN -sink_data[1] => src7_data[1].DATAIN -sink_data[1] => src8_data[1].DATAIN -sink_data[1] => src9_data[1].DATAIN -sink_data[1] => src10_data[1].DATAIN -sink_data[1] => src11_data[1].DATAIN -sink_data[1] => src12_data[1].DATAIN -sink_data[1] => src13_data[1].DATAIN -sink_data[1] => src14_data[1].DATAIN -sink_data[1] => src15_data[1].DATAIN -sink_data[1] => src16_data[1].DATAIN -sink_data[2] => src17_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src2_data[2].DATAIN -sink_data[2] => src3_data[2].DATAIN -sink_data[2] => src4_data[2].DATAIN -sink_data[2] => src5_data[2].DATAIN -sink_data[2] => src6_data[2].DATAIN -sink_data[2] => src7_data[2].DATAIN -sink_data[2] => src8_data[2].DATAIN -sink_data[2] => src9_data[2].DATAIN -sink_data[2] => src10_data[2].DATAIN -sink_data[2] => src11_data[2].DATAIN -sink_data[2] => src12_data[2].DATAIN -sink_data[2] => src13_data[2].DATAIN -sink_data[2] => src14_data[2].DATAIN -sink_data[2] => src15_data[2].DATAIN -sink_data[2] => src16_data[2].DATAIN -sink_data[3] => src17_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src2_data[3].DATAIN -sink_data[3] => src3_data[3].DATAIN -sink_data[3] => src4_data[3].DATAIN -sink_data[3] => src5_data[3].DATAIN -sink_data[3] => src6_data[3].DATAIN -sink_data[3] => src7_data[3].DATAIN -sink_data[3] => src8_data[3].DATAIN -sink_data[3] => src9_data[3].DATAIN -sink_data[3] => src10_data[3].DATAIN -sink_data[3] => src11_data[3].DATAIN -sink_data[3] => src12_data[3].DATAIN -sink_data[3] => src13_data[3].DATAIN -sink_data[3] => src14_data[3].DATAIN -sink_data[3] => src15_data[3].DATAIN -sink_data[3] => src16_data[3].DATAIN -sink_data[4] => src17_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src2_data[4].DATAIN -sink_data[4] => src3_data[4].DATAIN -sink_data[4] => src4_data[4].DATAIN -sink_data[4] => src5_data[4].DATAIN -sink_data[4] => src6_data[4].DATAIN -sink_data[4] => src7_data[4].DATAIN -sink_data[4] => src8_data[4].DATAIN -sink_data[4] => src9_data[4].DATAIN -sink_data[4] => src10_data[4].DATAIN -sink_data[4] => src11_data[4].DATAIN -sink_data[4] => src12_data[4].DATAIN -sink_data[4] => src13_data[4].DATAIN -sink_data[4] => src14_data[4].DATAIN -sink_data[4] => src15_data[4].DATAIN -sink_data[4] => src16_data[4].DATAIN -sink_data[5] => src17_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src2_data[5].DATAIN -sink_data[5] => src3_data[5].DATAIN -sink_data[5] => src4_data[5].DATAIN -sink_data[5] => src5_data[5].DATAIN -sink_data[5] => src6_data[5].DATAIN -sink_data[5] => src7_data[5].DATAIN -sink_data[5] => src8_data[5].DATAIN -sink_data[5] => src9_data[5].DATAIN -sink_data[5] => src10_data[5].DATAIN -sink_data[5] => src11_data[5].DATAIN -sink_data[5] => src12_data[5].DATAIN -sink_data[5] => src13_data[5].DATAIN -sink_data[5] => src14_data[5].DATAIN -sink_data[5] => src15_data[5].DATAIN -sink_data[5] => src16_data[5].DATAIN -sink_data[6] => src17_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src2_data[6].DATAIN -sink_data[6] => src3_data[6].DATAIN -sink_data[6] => src4_data[6].DATAIN -sink_data[6] => src5_data[6].DATAIN -sink_data[6] => src6_data[6].DATAIN -sink_data[6] => src7_data[6].DATAIN -sink_data[6] => src8_data[6].DATAIN -sink_data[6] => src9_data[6].DATAIN -sink_data[6] => src10_data[6].DATAIN -sink_data[6] => src11_data[6].DATAIN -sink_data[6] => src12_data[6].DATAIN -sink_data[6] => src13_data[6].DATAIN -sink_data[6] => src14_data[6].DATAIN -sink_data[6] => src15_data[6].DATAIN -sink_data[6] => src16_data[6].DATAIN -sink_data[7] => src17_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src2_data[7].DATAIN -sink_data[7] => src3_data[7].DATAIN -sink_data[7] => src4_data[7].DATAIN -sink_data[7] => src5_data[7].DATAIN -sink_data[7] => src6_data[7].DATAIN -sink_data[7] => src7_data[7].DATAIN -sink_data[7] => src8_data[7].DATAIN -sink_data[7] => src9_data[7].DATAIN -sink_data[7] => src10_data[7].DATAIN -sink_data[7] => src11_data[7].DATAIN -sink_data[7] => src12_data[7].DATAIN -sink_data[7] => src13_data[7].DATAIN -sink_data[7] => src14_data[7].DATAIN -sink_data[7] => src15_data[7].DATAIN -sink_data[7] => src16_data[7].DATAIN -sink_data[8] => src17_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src2_data[8].DATAIN -sink_data[8] => src3_data[8].DATAIN -sink_data[8] => src4_data[8].DATAIN -sink_data[8] => src5_data[8].DATAIN -sink_data[8] => src6_data[8].DATAIN -sink_data[8] => src7_data[8].DATAIN -sink_data[8] => src8_data[8].DATAIN -sink_data[8] => src9_data[8].DATAIN -sink_data[8] => src10_data[8].DATAIN -sink_data[8] => src11_data[8].DATAIN -sink_data[8] => src12_data[8].DATAIN -sink_data[8] => src13_data[8].DATAIN -sink_data[8] => src14_data[8].DATAIN -sink_data[8] => src15_data[8].DATAIN -sink_data[8] => src16_data[8].DATAIN -sink_data[9] => src17_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src2_data[9].DATAIN -sink_data[9] => src3_data[9].DATAIN -sink_data[9] => src4_data[9].DATAIN -sink_data[9] => src5_data[9].DATAIN -sink_data[9] => src6_data[9].DATAIN -sink_data[9] => src7_data[9].DATAIN -sink_data[9] => src8_data[9].DATAIN -sink_data[9] => src9_data[9].DATAIN -sink_data[9] => src10_data[9].DATAIN -sink_data[9] => src11_data[9].DATAIN -sink_data[9] => src12_data[9].DATAIN -sink_data[9] => src13_data[9].DATAIN -sink_data[9] => src14_data[9].DATAIN -sink_data[9] => src15_data[9].DATAIN -sink_data[9] => src16_data[9].DATAIN -sink_data[10] => src17_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src2_data[10].DATAIN -sink_data[10] => src3_data[10].DATAIN -sink_data[10] => src4_data[10].DATAIN -sink_data[10] => src5_data[10].DATAIN -sink_data[10] => src6_data[10].DATAIN -sink_data[10] => src7_data[10].DATAIN -sink_data[10] => src8_data[10].DATAIN -sink_data[10] => src9_data[10].DATAIN -sink_data[10] => src10_data[10].DATAIN -sink_data[10] => src11_data[10].DATAIN -sink_data[10] => src12_data[10].DATAIN -sink_data[10] => src13_data[10].DATAIN -sink_data[10] => src14_data[10].DATAIN -sink_data[10] => src15_data[10].DATAIN -sink_data[10] => src16_data[10].DATAIN -sink_data[11] => src17_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src2_data[11].DATAIN -sink_data[11] => src3_data[11].DATAIN -sink_data[11] => src4_data[11].DATAIN -sink_data[11] => src5_data[11].DATAIN -sink_data[11] => src6_data[11].DATAIN -sink_data[11] => src7_data[11].DATAIN -sink_data[11] => src8_data[11].DATAIN -sink_data[11] => src9_data[11].DATAIN -sink_data[11] => src10_data[11].DATAIN -sink_data[11] => src11_data[11].DATAIN -sink_data[11] => src12_data[11].DATAIN -sink_data[11] => src13_data[11].DATAIN -sink_data[11] => src14_data[11].DATAIN -sink_data[11] => src15_data[11].DATAIN -sink_data[11] => src16_data[11].DATAIN -sink_data[12] => src17_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src2_data[12].DATAIN -sink_data[12] => src3_data[12].DATAIN -sink_data[12] => src4_data[12].DATAIN -sink_data[12] => src5_data[12].DATAIN -sink_data[12] => src6_data[12].DATAIN -sink_data[12] => src7_data[12].DATAIN -sink_data[12] => src8_data[12].DATAIN -sink_data[12] => src9_data[12].DATAIN -sink_data[12] => src10_data[12].DATAIN -sink_data[12] => src11_data[12].DATAIN -sink_data[12] => src12_data[12].DATAIN -sink_data[12] => src13_data[12].DATAIN -sink_data[12] => src14_data[12].DATAIN -sink_data[12] => src15_data[12].DATAIN -sink_data[12] => src16_data[12].DATAIN -sink_data[13] => src17_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src2_data[13].DATAIN -sink_data[13] => src3_data[13].DATAIN -sink_data[13] => src4_data[13].DATAIN -sink_data[13] => src5_data[13].DATAIN -sink_data[13] => src6_data[13].DATAIN -sink_data[13] => src7_data[13].DATAIN -sink_data[13] => src8_data[13].DATAIN -sink_data[13] => src9_data[13].DATAIN -sink_data[13] => src10_data[13].DATAIN -sink_data[13] => src11_data[13].DATAIN -sink_data[13] => src12_data[13].DATAIN -sink_data[13] => src13_data[13].DATAIN -sink_data[13] => src14_data[13].DATAIN -sink_data[13] => src15_data[13].DATAIN -sink_data[13] => src16_data[13].DATAIN -sink_data[14] => src17_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src2_data[14].DATAIN -sink_data[14] => src3_data[14].DATAIN -sink_data[14] => src4_data[14].DATAIN -sink_data[14] => src5_data[14].DATAIN -sink_data[14] => src6_data[14].DATAIN -sink_data[14] => src7_data[14].DATAIN -sink_data[14] => src8_data[14].DATAIN -sink_data[14] => src9_data[14].DATAIN -sink_data[14] => src10_data[14].DATAIN -sink_data[14] => src11_data[14].DATAIN -sink_data[14] => src12_data[14].DATAIN -sink_data[14] => src13_data[14].DATAIN -sink_data[14] => src14_data[14].DATAIN -sink_data[14] => src15_data[14].DATAIN -sink_data[14] => src16_data[14].DATAIN -sink_data[15] => src17_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src2_data[15].DATAIN -sink_data[15] => src3_data[15].DATAIN -sink_data[15] => src4_data[15].DATAIN -sink_data[15] => src5_data[15].DATAIN -sink_data[15] => src6_data[15].DATAIN -sink_data[15] => src7_data[15].DATAIN -sink_data[15] => src8_data[15].DATAIN -sink_data[15] => src9_data[15].DATAIN -sink_data[15] => src10_data[15].DATAIN -sink_data[15] => src11_data[15].DATAIN -sink_data[15] => src12_data[15].DATAIN -sink_data[15] => src13_data[15].DATAIN -sink_data[15] => src14_data[15].DATAIN -sink_data[15] => src15_data[15].DATAIN -sink_data[15] => src16_data[15].DATAIN -sink_data[16] => src17_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src2_data[16].DATAIN -sink_data[16] => src3_data[16].DATAIN -sink_data[16] => src4_data[16].DATAIN -sink_data[16] => src5_data[16].DATAIN -sink_data[16] => src6_data[16].DATAIN -sink_data[16] => src7_data[16].DATAIN -sink_data[16] => src8_data[16].DATAIN -sink_data[16] => src9_data[16].DATAIN -sink_data[16] => src10_data[16].DATAIN -sink_data[16] => src11_data[16].DATAIN -sink_data[16] => src12_data[16].DATAIN -sink_data[16] => src13_data[16].DATAIN -sink_data[16] => src14_data[16].DATAIN -sink_data[16] => src15_data[16].DATAIN -sink_data[16] => src16_data[16].DATAIN -sink_data[17] => src17_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src2_data[17].DATAIN -sink_data[17] => src3_data[17].DATAIN -sink_data[17] => src4_data[17].DATAIN -sink_data[17] => src5_data[17].DATAIN -sink_data[17] => src6_data[17].DATAIN -sink_data[17] => src7_data[17].DATAIN -sink_data[17] => src8_data[17].DATAIN -sink_data[17] => src9_data[17].DATAIN -sink_data[17] => src10_data[17].DATAIN -sink_data[17] => src11_data[17].DATAIN -sink_data[17] => src12_data[17].DATAIN -sink_data[17] => src13_data[17].DATAIN -sink_data[17] => src14_data[17].DATAIN -sink_data[17] => src15_data[17].DATAIN -sink_data[17] => src16_data[17].DATAIN -sink_data[18] => src17_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src2_data[18].DATAIN -sink_data[18] => src3_data[18].DATAIN -sink_data[18] => src4_data[18].DATAIN -sink_data[18] => src5_data[18].DATAIN -sink_data[18] => src6_data[18].DATAIN -sink_data[18] => src7_data[18].DATAIN -sink_data[18] => src8_data[18].DATAIN -sink_data[18] => src9_data[18].DATAIN -sink_data[18] => src10_data[18].DATAIN -sink_data[18] => src11_data[18].DATAIN -sink_data[18] => src12_data[18].DATAIN -sink_data[18] => src13_data[18].DATAIN -sink_data[18] => src14_data[18].DATAIN -sink_data[18] => src15_data[18].DATAIN -sink_data[18] => src16_data[18].DATAIN -sink_data[19] => src17_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src2_data[19].DATAIN -sink_data[19] => src3_data[19].DATAIN -sink_data[19] => src4_data[19].DATAIN -sink_data[19] => src5_data[19].DATAIN -sink_data[19] => src6_data[19].DATAIN -sink_data[19] => src7_data[19].DATAIN -sink_data[19] => src8_data[19].DATAIN -sink_data[19] => src9_data[19].DATAIN -sink_data[19] => src10_data[19].DATAIN -sink_data[19] => src11_data[19].DATAIN -sink_data[19] => src12_data[19].DATAIN -sink_data[19] => src13_data[19].DATAIN -sink_data[19] => src14_data[19].DATAIN -sink_data[19] => src15_data[19].DATAIN -sink_data[19] => src16_data[19].DATAIN -sink_data[20] => src17_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src2_data[20].DATAIN -sink_data[20] => src3_data[20].DATAIN -sink_data[20] => src4_data[20].DATAIN -sink_data[20] => src5_data[20].DATAIN -sink_data[20] => src6_data[20].DATAIN -sink_data[20] => src7_data[20].DATAIN -sink_data[20] => src8_data[20].DATAIN -sink_data[20] => src9_data[20].DATAIN -sink_data[20] => src10_data[20].DATAIN -sink_data[20] => src11_data[20].DATAIN -sink_data[20] => src12_data[20].DATAIN -sink_data[20] => src13_data[20].DATAIN -sink_data[20] => src14_data[20].DATAIN -sink_data[20] => src15_data[20].DATAIN -sink_data[20] => src16_data[20].DATAIN -sink_data[21] => src17_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src2_data[21].DATAIN -sink_data[21] => src3_data[21].DATAIN -sink_data[21] => src4_data[21].DATAIN -sink_data[21] => src5_data[21].DATAIN -sink_data[21] => src6_data[21].DATAIN -sink_data[21] => src7_data[21].DATAIN -sink_data[21] => src8_data[21].DATAIN -sink_data[21] => src9_data[21].DATAIN -sink_data[21] => src10_data[21].DATAIN -sink_data[21] => src11_data[21].DATAIN -sink_data[21] => src12_data[21].DATAIN -sink_data[21] => src13_data[21].DATAIN -sink_data[21] => src14_data[21].DATAIN -sink_data[21] => src15_data[21].DATAIN -sink_data[21] => src16_data[21].DATAIN -sink_data[22] => src17_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src2_data[22].DATAIN -sink_data[22] => src3_data[22].DATAIN -sink_data[22] => src4_data[22].DATAIN -sink_data[22] => src5_data[22].DATAIN -sink_data[22] => src6_data[22].DATAIN -sink_data[22] => src7_data[22].DATAIN -sink_data[22] => src8_data[22].DATAIN -sink_data[22] => src9_data[22].DATAIN -sink_data[22] => src10_data[22].DATAIN -sink_data[22] => src11_data[22].DATAIN -sink_data[22] => src12_data[22].DATAIN -sink_data[22] => src13_data[22].DATAIN -sink_data[22] => src14_data[22].DATAIN -sink_data[22] => src15_data[22].DATAIN -sink_data[22] => src16_data[22].DATAIN -sink_data[23] => src17_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src2_data[23].DATAIN -sink_data[23] => src3_data[23].DATAIN -sink_data[23] => src4_data[23].DATAIN -sink_data[23] => src5_data[23].DATAIN -sink_data[23] => src6_data[23].DATAIN -sink_data[23] => src7_data[23].DATAIN -sink_data[23] => src8_data[23].DATAIN -sink_data[23] => src9_data[23].DATAIN -sink_data[23] => src10_data[23].DATAIN -sink_data[23] => src11_data[23].DATAIN -sink_data[23] => src12_data[23].DATAIN -sink_data[23] => src13_data[23].DATAIN -sink_data[23] => src14_data[23].DATAIN -sink_data[23] => src15_data[23].DATAIN -sink_data[23] => src16_data[23].DATAIN -sink_data[24] => src17_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src2_data[24].DATAIN -sink_data[24] => src3_data[24].DATAIN -sink_data[24] => src4_data[24].DATAIN -sink_data[24] => src5_data[24].DATAIN -sink_data[24] => src6_data[24].DATAIN -sink_data[24] => src7_data[24].DATAIN -sink_data[24] => src8_data[24].DATAIN -sink_data[24] => src9_data[24].DATAIN -sink_data[24] => src10_data[24].DATAIN -sink_data[24] => src11_data[24].DATAIN -sink_data[24] => src12_data[24].DATAIN -sink_data[24] => src13_data[24].DATAIN -sink_data[24] => src14_data[24].DATAIN -sink_data[24] => src15_data[24].DATAIN -sink_data[24] => src16_data[24].DATAIN -sink_data[25] => src17_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src2_data[25].DATAIN -sink_data[25] => src3_data[25].DATAIN -sink_data[25] => src4_data[25].DATAIN -sink_data[25] => src5_data[25].DATAIN -sink_data[25] => src6_data[25].DATAIN -sink_data[25] => src7_data[25].DATAIN -sink_data[25] => src8_data[25].DATAIN -sink_data[25] => src9_data[25].DATAIN -sink_data[25] => src10_data[25].DATAIN -sink_data[25] => src11_data[25].DATAIN -sink_data[25] => src12_data[25].DATAIN -sink_data[25] => src13_data[25].DATAIN -sink_data[25] => src14_data[25].DATAIN -sink_data[25] => src15_data[25].DATAIN -sink_data[25] => src16_data[25].DATAIN -sink_data[26] => src17_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src2_data[26].DATAIN -sink_data[26] => src3_data[26].DATAIN -sink_data[26] => src4_data[26].DATAIN -sink_data[26] => src5_data[26].DATAIN -sink_data[26] => src6_data[26].DATAIN -sink_data[26] => src7_data[26].DATAIN -sink_data[26] => src8_data[26].DATAIN -sink_data[26] => src9_data[26].DATAIN -sink_data[26] => src10_data[26].DATAIN -sink_data[26] => src11_data[26].DATAIN -sink_data[26] => src12_data[26].DATAIN -sink_data[26] => src13_data[26].DATAIN -sink_data[26] => src14_data[26].DATAIN -sink_data[26] => src15_data[26].DATAIN -sink_data[26] => src16_data[26].DATAIN -sink_data[27] => src17_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src2_data[27].DATAIN -sink_data[27] => src3_data[27].DATAIN -sink_data[27] => src4_data[27].DATAIN -sink_data[27] => src5_data[27].DATAIN -sink_data[27] => src6_data[27].DATAIN -sink_data[27] => src7_data[27].DATAIN -sink_data[27] => src8_data[27].DATAIN -sink_data[27] => src9_data[27].DATAIN -sink_data[27] => src10_data[27].DATAIN -sink_data[27] => src11_data[27].DATAIN -sink_data[27] => src12_data[27].DATAIN -sink_data[27] => src13_data[27].DATAIN -sink_data[27] => src14_data[27].DATAIN -sink_data[27] => src15_data[27].DATAIN -sink_data[27] => src16_data[27].DATAIN -sink_data[28] => src17_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src2_data[28].DATAIN -sink_data[28] => src3_data[28].DATAIN -sink_data[28] => src4_data[28].DATAIN -sink_data[28] => src5_data[28].DATAIN -sink_data[28] => src6_data[28].DATAIN -sink_data[28] => src7_data[28].DATAIN -sink_data[28] => src8_data[28].DATAIN -sink_data[28] => src9_data[28].DATAIN -sink_data[28] => src10_data[28].DATAIN -sink_data[28] => src11_data[28].DATAIN -sink_data[28] => src12_data[28].DATAIN -sink_data[28] => src13_data[28].DATAIN -sink_data[28] => src14_data[28].DATAIN -sink_data[28] => src15_data[28].DATAIN -sink_data[28] => src16_data[28].DATAIN -sink_data[29] => src17_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src2_data[29].DATAIN -sink_data[29] => src3_data[29].DATAIN -sink_data[29] => src4_data[29].DATAIN -sink_data[29] => src5_data[29].DATAIN -sink_data[29] => src6_data[29].DATAIN -sink_data[29] => src7_data[29].DATAIN -sink_data[29] => src8_data[29].DATAIN -sink_data[29] => src9_data[29].DATAIN -sink_data[29] => src10_data[29].DATAIN -sink_data[29] => src11_data[29].DATAIN -sink_data[29] => src12_data[29].DATAIN -sink_data[29] => src13_data[29].DATAIN -sink_data[29] => src14_data[29].DATAIN -sink_data[29] => src15_data[29].DATAIN -sink_data[29] => src16_data[29].DATAIN -sink_data[30] => src17_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src2_data[30].DATAIN -sink_data[30] => src3_data[30].DATAIN -sink_data[30] => src4_data[30].DATAIN -sink_data[30] => src5_data[30].DATAIN -sink_data[30] => src6_data[30].DATAIN -sink_data[30] => src7_data[30].DATAIN -sink_data[30] => src8_data[30].DATAIN -sink_data[30] => src9_data[30].DATAIN -sink_data[30] => src10_data[30].DATAIN -sink_data[30] => src11_data[30].DATAIN -sink_data[30] => src12_data[30].DATAIN -sink_data[30] => src13_data[30].DATAIN -sink_data[30] => src14_data[30].DATAIN -sink_data[30] => src15_data[30].DATAIN -sink_data[30] => src16_data[30].DATAIN -sink_data[31] => src17_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src2_data[31].DATAIN -sink_data[31] => src3_data[31].DATAIN -sink_data[31] => src4_data[31].DATAIN -sink_data[31] => src5_data[31].DATAIN -sink_data[31] => src6_data[31].DATAIN -sink_data[31] => src7_data[31].DATAIN -sink_data[31] => src8_data[31].DATAIN -sink_data[31] => src9_data[31].DATAIN -sink_data[31] => src10_data[31].DATAIN -sink_data[31] => src11_data[31].DATAIN -sink_data[31] => src12_data[31].DATAIN -sink_data[31] => src13_data[31].DATAIN -sink_data[31] => src14_data[31].DATAIN -sink_data[31] => src15_data[31].DATAIN -sink_data[31] => src16_data[31].DATAIN -sink_data[32] => src17_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src2_data[32].DATAIN -sink_data[32] => src3_data[32].DATAIN -sink_data[32] => src4_data[32].DATAIN -sink_data[32] => src5_data[32].DATAIN -sink_data[32] => src6_data[32].DATAIN -sink_data[32] => src7_data[32].DATAIN -sink_data[32] => src8_data[32].DATAIN -sink_data[32] => src9_data[32].DATAIN -sink_data[32] => src10_data[32].DATAIN -sink_data[32] => src11_data[32].DATAIN -sink_data[32] => src12_data[32].DATAIN -sink_data[32] => src13_data[32].DATAIN -sink_data[32] => src14_data[32].DATAIN -sink_data[32] => src15_data[32].DATAIN -sink_data[32] => src16_data[32].DATAIN -sink_data[33] => src17_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src2_data[33].DATAIN -sink_data[33] => src3_data[33].DATAIN -sink_data[33] => src4_data[33].DATAIN -sink_data[33] => src5_data[33].DATAIN -sink_data[33] => src6_data[33].DATAIN -sink_data[33] => src7_data[33].DATAIN -sink_data[33] => src8_data[33].DATAIN -sink_data[33] => src9_data[33].DATAIN -sink_data[33] => src10_data[33].DATAIN -sink_data[33] => src11_data[33].DATAIN -sink_data[33] => src12_data[33].DATAIN -sink_data[33] => src13_data[33].DATAIN -sink_data[33] => src14_data[33].DATAIN -sink_data[33] => src15_data[33].DATAIN -sink_data[33] => src16_data[33].DATAIN -sink_data[34] => src17_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src2_data[34].DATAIN -sink_data[34] => src3_data[34].DATAIN -sink_data[34] => src4_data[34].DATAIN -sink_data[34] => src5_data[34].DATAIN -sink_data[34] => src6_data[34].DATAIN -sink_data[34] => src7_data[34].DATAIN -sink_data[34] => src8_data[34].DATAIN -sink_data[34] => src9_data[34].DATAIN -sink_data[34] => src10_data[34].DATAIN -sink_data[34] => src11_data[34].DATAIN -sink_data[34] => src12_data[34].DATAIN -sink_data[34] => src13_data[34].DATAIN -sink_data[34] => src14_data[34].DATAIN -sink_data[34] => src15_data[34].DATAIN -sink_data[34] => src16_data[34].DATAIN -sink_data[35] => src17_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src2_data[35].DATAIN -sink_data[35] => src3_data[35].DATAIN -sink_data[35] => src4_data[35].DATAIN -sink_data[35] => src5_data[35].DATAIN -sink_data[35] => src6_data[35].DATAIN -sink_data[35] => src7_data[35].DATAIN -sink_data[35] => src8_data[35].DATAIN -sink_data[35] => src9_data[35].DATAIN -sink_data[35] => src10_data[35].DATAIN -sink_data[35] => src11_data[35].DATAIN -sink_data[35] => src12_data[35].DATAIN -sink_data[35] => src13_data[35].DATAIN -sink_data[35] => src14_data[35].DATAIN -sink_data[35] => src15_data[35].DATAIN -sink_data[35] => src16_data[35].DATAIN -sink_data[36] => src17_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src2_data[36].DATAIN -sink_data[36] => src3_data[36].DATAIN -sink_data[36] => src4_data[36].DATAIN -sink_data[36] => src5_data[36].DATAIN -sink_data[36] => src6_data[36].DATAIN -sink_data[36] => src7_data[36].DATAIN -sink_data[36] => src8_data[36].DATAIN -sink_data[36] => src9_data[36].DATAIN -sink_data[36] => src10_data[36].DATAIN -sink_data[36] => src11_data[36].DATAIN -sink_data[36] => src12_data[36].DATAIN -sink_data[36] => src13_data[36].DATAIN -sink_data[36] => src14_data[36].DATAIN -sink_data[36] => src15_data[36].DATAIN -sink_data[36] => src16_data[36].DATAIN -sink_data[37] => src17_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src2_data[37].DATAIN -sink_data[37] => src3_data[37].DATAIN -sink_data[37] => src4_data[37].DATAIN -sink_data[37] => src5_data[37].DATAIN -sink_data[37] => src6_data[37].DATAIN -sink_data[37] => src7_data[37].DATAIN -sink_data[37] => src8_data[37].DATAIN -sink_data[37] => src9_data[37].DATAIN -sink_data[37] => src10_data[37].DATAIN -sink_data[37] => src11_data[37].DATAIN -sink_data[37] => src12_data[37].DATAIN -sink_data[37] => src13_data[37].DATAIN -sink_data[37] => src14_data[37].DATAIN -sink_data[37] => src15_data[37].DATAIN -sink_data[37] => src16_data[37].DATAIN -sink_data[38] => src17_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src2_data[38].DATAIN -sink_data[38] => src3_data[38].DATAIN -sink_data[38] => src4_data[38].DATAIN -sink_data[38] => src5_data[38].DATAIN -sink_data[38] => src6_data[38].DATAIN -sink_data[38] => src7_data[38].DATAIN -sink_data[38] => src8_data[38].DATAIN -sink_data[38] => src9_data[38].DATAIN -sink_data[38] => src10_data[38].DATAIN -sink_data[38] => src11_data[38].DATAIN -sink_data[38] => src12_data[38].DATAIN -sink_data[38] => src13_data[38].DATAIN -sink_data[38] => src14_data[38].DATAIN -sink_data[38] => src15_data[38].DATAIN -sink_data[38] => src16_data[38].DATAIN -sink_data[39] => src17_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src2_data[39].DATAIN -sink_data[39] => src3_data[39].DATAIN -sink_data[39] => src4_data[39].DATAIN -sink_data[39] => src5_data[39].DATAIN -sink_data[39] => src6_data[39].DATAIN -sink_data[39] => src7_data[39].DATAIN -sink_data[39] => src8_data[39].DATAIN -sink_data[39] => src9_data[39].DATAIN -sink_data[39] => src10_data[39].DATAIN -sink_data[39] => src11_data[39].DATAIN -sink_data[39] => src12_data[39].DATAIN -sink_data[39] => src13_data[39].DATAIN -sink_data[39] => src14_data[39].DATAIN -sink_data[39] => src15_data[39].DATAIN -sink_data[39] => src16_data[39].DATAIN -sink_data[40] => src17_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src2_data[40].DATAIN -sink_data[40] => src3_data[40].DATAIN -sink_data[40] => src4_data[40].DATAIN -sink_data[40] => src5_data[40].DATAIN -sink_data[40] => src6_data[40].DATAIN -sink_data[40] => src7_data[40].DATAIN -sink_data[40] => src8_data[40].DATAIN -sink_data[40] => src9_data[40].DATAIN -sink_data[40] => src10_data[40].DATAIN -sink_data[40] => src11_data[40].DATAIN -sink_data[40] => src12_data[40].DATAIN -sink_data[40] => src13_data[40].DATAIN -sink_data[40] => src14_data[40].DATAIN -sink_data[40] => src15_data[40].DATAIN -sink_data[40] => src16_data[40].DATAIN -sink_data[41] => src17_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src2_data[41].DATAIN -sink_data[41] => src3_data[41].DATAIN -sink_data[41] => src4_data[41].DATAIN -sink_data[41] => src5_data[41].DATAIN -sink_data[41] => src6_data[41].DATAIN -sink_data[41] => src7_data[41].DATAIN -sink_data[41] => src8_data[41].DATAIN -sink_data[41] => src9_data[41].DATAIN -sink_data[41] => src10_data[41].DATAIN -sink_data[41] => src11_data[41].DATAIN -sink_data[41] => src12_data[41].DATAIN -sink_data[41] => src13_data[41].DATAIN -sink_data[41] => src14_data[41].DATAIN -sink_data[41] => src15_data[41].DATAIN -sink_data[41] => src16_data[41].DATAIN -sink_data[42] => src17_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src2_data[42].DATAIN -sink_data[42] => src3_data[42].DATAIN -sink_data[42] => src4_data[42].DATAIN -sink_data[42] => src5_data[42].DATAIN -sink_data[42] => src6_data[42].DATAIN -sink_data[42] => src7_data[42].DATAIN -sink_data[42] => src8_data[42].DATAIN -sink_data[42] => src9_data[42].DATAIN -sink_data[42] => src10_data[42].DATAIN -sink_data[42] => src11_data[42].DATAIN -sink_data[42] => src12_data[42].DATAIN -sink_data[42] => src13_data[42].DATAIN -sink_data[42] => src14_data[42].DATAIN -sink_data[42] => src15_data[42].DATAIN -sink_data[42] => src16_data[42].DATAIN -sink_data[43] => src17_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src2_data[43].DATAIN -sink_data[43] => src3_data[43].DATAIN -sink_data[43] => src4_data[43].DATAIN -sink_data[43] => src5_data[43].DATAIN -sink_data[43] => src6_data[43].DATAIN -sink_data[43] => src7_data[43].DATAIN -sink_data[43] => src8_data[43].DATAIN -sink_data[43] => src9_data[43].DATAIN -sink_data[43] => src10_data[43].DATAIN -sink_data[43] => src11_data[43].DATAIN -sink_data[43] => src12_data[43].DATAIN -sink_data[43] => src13_data[43].DATAIN -sink_data[43] => src14_data[43].DATAIN -sink_data[43] => src15_data[43].DATAIN -sink_data[43] => src16_data[43].DATAIN -sink_data[44] => src17_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src2_data[44].DATAIN -sink_data[44] => src3_data[44].DATAIN -sink_data[44] => src4_data[44].DATAIN -sink_data[44] => src5_data[44].DATAIN -sink_data[44] => src6_data[44].DATAIN -sink_data[44] => src7_data[44].DATAIN -sink_data[44] => src8_data[44].DATAIN -sink_data[44] => src9_data[44].DATAIN -sink_data[44] => src10_data[44].DATAIN -sink_data[44] => src11_data[44].DATAIN -sink_data[44] => src12_data[44].DATAIN -sink_data[44] => src13_data[44].DATAIN -sink_data[44] => src14_data[44].DATAIN -sink_data[44] => src15_data[44].DATAIN -sink_data[44] => src16_data[44].DATAIN -sink_data[45] => src17_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src2_data[45].DATAIN -sink_data[45] => src3_data[45].DATAIN -sink_data[45] => src4_data[45].DATAIN -sink_data[45] => src5_data[45].DATAIN -sink_data[45] => src6_data[45].DATAIN -sink_data[45] => src7_data[45].DATAIN -sink_data[45] => src8_data[45].DATAIN -sink_data[45] => src9_data[45].DATAIN -sink_data[45] => src10_data[45].DATAIN -sink_data[45] => src11_data[45].DATAIN -sink_data[45] => src12_data[45].DATAIN -sink_data[45] => src13_data[45].DATAIN -sink_data[45] => src14_data[45].DATAIN -sink_data[45] => src15_data[45].DATAIN -sink_data[45] => src16_data[45].DATAIN -sink_data[46] => src17_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src2_data[46].DATAIN -sink_data[46] => src3_data[46].DATAIN -sink_data[46] => src4_data[46].DATAIN -sink_data[46] => src5_data[46].DATAIN -sink_data[46] => src6_data[46].DATAIN -sink_data[46] => src7_data[46].DATAIN -sink_data[46] => src8_data[46].DATAIN -sink_data[46] => src9_data[46].DATAIN -sink_data[46] => src10_data[46].DATAIN -sink_data[46] => src11_data[46].DATAIN -sink_data[46] => src12_data[46].DATAIN -sink_data[46] => src13_data[46].DATAIN -sink_data[46] => src14_data[46].DATAIN -sink_data[46] => src15_data[46].DATAIN -sink_data[46] => src16_data[46].DATAIN -sink_data[47] => src17_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src2_data[47].DATAIN -sink_data[47] => src3_data[47].DATAIN -sink_data[47] => src4_data[47].DATAIN -sink_data[47] => src5_data[47].DATAIN -sink_data[47] => src6_data[47].DATAIN -sink_data[47] => src7_data[47].DATAIN -sink_data[47] => src8_data[47].DATAIN -sink_data[47] => src9_data[47].DATAIN -sink_data[47] => src10_data[47].DATAIN -sink_data[47] => src11_data[47].DATAIN -sink_data[47] => src12_data[47].DATAIN -sink_data[47] => src13_data[47].DATAIN -sink_data[47] => src14_data[47].DATAIN -sink_data[47] => src15_data[47].DATAIN -sink_data[47] => src16_data[47].DATAIN -sink_data[48] => src17_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src2_data[48].DATAIN -sink_data[48] => src3_data[48].DATAIN -sink_data[48] => src4_data[48].DATAIN -sink_data[48] => src5_data[48].DATAIN -sink_data[48] => src6_data[48].DATAIN -sink_data[48] => src7_data[48].DATAIN -sink_data[48] => src8_data[48].DATAIN -sink_data[48] => src9_data[48].DATAIN -sink_data[48] => src10_data[48].DATAIN -sink_data[48] => src11_data[48].DATAIN -sink_data[48] => src12_data[48].DATAIN -sink_data[48] => src13_data[48].DATAIN -sink_data[48] => src14_data[48].DATAIN -sink_data[48] => src15_data[48].DATAIN -sink_data[48] => src16_data[48].DATAIN -sink_data[49] => src17_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src2_data[49].DATAIN -sink_data[49] => src3_data[49].DATAIN -sink_data[49] => src4_data[49].DATAIN -sink_data[49] => src5_data[49].DATAIN -sink_data[49] => src6_data[49].DATAIN -sink_data[49] => src7_data[49].DATAIN -sink_data[49] => src8_data[49].DATAIN -sink_data[49] => src9_data[49].DATAIN -sink_data[49] => src10_data[49].DATAIN -sink_data[49] => src11_data[49].DATAIN -sink_data[49] => src12_data[49].DATAIN -sink_data[49] => src13_data[49].DATAIN -sink_data[49] => src14_data[49].DATAIN -sink_data[49] => src15_data[49].DATAIN -sink_data[49] => src16_data[49].DATAIN -sink_data[50] => src17_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src2_data[50].DATAIN -sink_data[50] => src3_data[50].DATAIN -sink_data[50] => src4_data[50].DATAIN -sink_data[50] => src5_data[50].DATAIN -sink_data[50] => src6_data[50].DATAIN -sink_data[50] => src7_data[50].DATAIN -sink_data[50] => src8_data[50].DATAIN -sink_data[50] => src9_data[50].DATAIN -sink_data[50] => src10_data[50].DATAIN -sink_data[50] => src11_data[50].DATAIN -sink_data[50] => src12_data[50].DATAIN -sink_data[50] => src13_data[50].DATAIN -sink_data[50] => src14_data[50].DATAIN -sink_data[50] => src15_data[50].DATAIN -sink_data[50] => src16_data[50].DATAIN -sink_data[51] => src17_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src2_data[51].DATAIN -sink_data[51] => src3_data[51].DATAIN -sink_data[51] => src4_data[51].DATAIN -sink_data[51] => src5_data[51].DATAIN -sink_data[51] => src6_data[51].DATAIN -sink_data[51] => src7_data[51].DATAIN -sink_data[51] => src8_data[51].DATAIN -sink_data[51] => src9_data[51].DATAIN -sink_data[51] => src10_data[51].DATAIN -sink_data[51] => src11_data[51].DATAIN -sink_data[51] => src12_data[51].DATAIN -sink_data[51] => src13_data[51].DATAIN -sink_data[51] => src14_data[51].DATAIN -sink_data[51] => src15_data[51].DATAIN -sink_data[51] => src16_data[51].DATAIN -sink_data[52] => src17_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src2_data[52].DATAIN -sink_data[52] => src3_data[52].DATAIN -sink_data[52] => src4_data[52].DATAIN -sink_data[52] => src5_data[52].DATAIN -sink_data[52] => src6_data[52].DATAIN -sink_data[52] => src7_data[52].DATAIN -sink_data[52] => src8_data[52].DATAIN -sink_data[52] => src9_data[52].DATAIN -sink_data[52] => src10_data[52].DATAIN -sink_data[52] => src11_data[52].DATAIN -sink_data[52] => src12_data[52].DATAIN -sink_data[52] => src13_data[52].DATAIN -sink_data[52] => src14_data[52].DATAIN -sink_data[52] => src15_data[52].DATAIN -sink_data[52] => src16_data[52].DATAIN -sink_data[53] => src17_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src2_data[53].DATAIN -sink_data[53] => src3_data[53].DATAIN -sink_data[53] => src4_data[53].DATAIN -sink_data[53] => src5_data[53].DATAIN -sink_data[53] => src6_data[53].DATAIN -sink_data[53] => src7_data[53].DATAIN -sink_data[53] => src8_data[53].DATAIN -sink_data[53] => src9_data[53].DATAIN -sink_data[53] => src10_data[53].DATAIN -sink_data[53] => src11_data[53].DATAIN -sink_data[53] => src12_data[53].DATAIN -sink_data[53] => src13_data[53].DATAIN -sink_data[53] => src14_data[53].DATAIN -sink_data[53] => src15_data[53].DATAIN -sink_data[53] => src16_data[53].DATAIN -sink_data[54] => src17_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src2_data[54].DATAIN -sink_data[54] => src3_data[54].DATAIN -sink_data[54] => src4_data[54].DATAIN -sink_data[54] => src5_data[54].DATAIN -sink_data[54] => src6_data[54].DATAIN -sink_data[54] => src7_data[54].DATAIN -sink_data[54] => src8_data[54].DATAIN -sink_data[54] => src9_data[54].DATAIN -sink_data[54] => src10_data[54].DATAIN -sink_data[54] => src11_data[54].DATAIN -sink_data[54] => src12_data[54].DATAIN -sink_data[54] => src13_data[54].DATAIN -sink_data[54] => src14_data[54].DATAIN -sink_data[54] => src15_data[54].DATAIN -sink_data[54] => src16_data[54].DATAIN -sink_data[55] => src17_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src2_data[55].DATAIN -sink_data[55] => src3_data[55].DATAIN -sink_data[55] => src4_data[55].DATAIN -sink_data[55] => src5_data[55].DATAIN -sink_data[55] => src6_data[55].DATAIN -sink_data[55] => src7_data[55].DATAIN -sink_data[55] => src8_data[55].DATAIN -sink_data[55] => src9_data[55].DATAIN -sink_data[55] => src10_data[55].DATAIN -sink_data[55] => src11_data[55].DATAIN -sink_data[55] => src12_data[55].DATAIN -sink_data[55] => src13_data[55].DATAIN -sink_data[55] => src14_data[55].DATAIN -sink_data[55] => src15_data[55].DATAIN -sink_data[55] => src16_data[55].DATAIN -sink_data[56] => src17_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src2_data[56].DATAIN -sink_data[56] => src3_data[56].DATAIN -sink_data[56] => src4_data[56].DATAIN -sink_data[56] => src5_data[56].DATAIN -sink_data[56] => src6_data[56].DATAIN -sink_data[56] => src7_data[56].DATAIN -sink_data[56] => src8_data[56].DATAIN -sink_data[56] => src9_data[56].DATAIN -sink_data[56] => src10_data[56].DATAIN -sink_data[56] => src11_data[56].DATAIN -sink_data[56] => src12_data[56].DATAIN -sink_data[56] => src13_data[56].DATAIN -sink_data[56] => src14_data[56].DATAIN -sink_data[56] => src15_data[56].DATAIN -sink_data[56] => src16_data[56].DATAIN -sink_data[57] => src17_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src2_data[57].DATAIN -sink_data[57] => src3_data[57].DATAIN -sink_data[57] => src4_data[57].DATAIN -sink_data[57] => src5_data[57].DATAIN -sink_data[57] => src6_data[57].DATAIN -sink_data[57] => src7_data[57].DATAIN -sink_data[57] => src8_data[57].DATAIN -sink_data[57] => src9_data[57].DATAIN -sink_data[57] => src10_data[57].DATAIN -sink_data[57] => src11_data[57].DATAIN -sink_data[57] => src12_data[57].DATAIN -sink_data[57] => src13_data[57].DATAIN -sink_data[57] => src14_data[57].DATAIN -sink_data[57] => src15_data[57].DATAIN -sink_data[57] => src16_data[57].DATAIN -sink_data[58] => src17_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src2_data[58].DATAIN -sink_data[58] => src3_data[58].DATAIN -sink_data[58] => src4_data[58].DATAIN -sink_data[58] => src5_data[58].DATAIN -sink_data[58] => src6_data[58].DATAIN -sink_data[58] => src7_data[58].DATAIN -sink_data[58] => src8_data[58].DATAIN -sink_data[58] => src9_data[58].DATAIN -sink_data[58] => src10_data[58].DATAIN -sink_data[58] => src11_data[58].DATAIN -sink_data[58] => src12_data[58].DATAIN -sink_data[58] => src13_data[58].DATAIN -sink_data[58] => src14_data[58].DATAIN -sink_data[58] => src15_data[58].DATAIN -sink_data[58] => src16_data[58].DATAIN -sink_data[59] => src17_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src2_data[59].DATAIN -sink_data[59] => src3_data[59].DATAIN -sink_data[59] => src4_data[59].DATAIN -sink_data[59] => src5_data[59].DATAIN -sink_data[59] => src6_data[59].DATAIN -sink_data[59] => src7_data[59].DATAIN -sink_data[59] => src8_data[59].DATAIN -sink_data[59] => src9_data[59].DATAIN -sink_data[59] => src10_data[59].DATAIN -sink_data[59] => src11_data[59].DATAIN -sink_data[59] => src12_data[59].DATAIN -sink_data[59] => src13_data[59].DATAIN -sink_data[59] => src14_data[59].DATAIN -sink_data[59] => src15_data[59].DATAIN -sink_data[59] => src16_data[59].DATAIN -sink_data[60] => src17_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src2_data[60].DATAIN -sink_data[60] => src3_data[60].DATAIN -sink_data[60] => src4_data[60].DATAIN -sink_data[60] => src5_data[60].DATAIN -sink_data[60] => src6_data[60].DATAIN -sink_data[60] => src7_data[60].DATAIN -sink_data[60] => src8_data[60].DATAIN -sink_data[60] => src9_data[60].DATAIN -sink_data[60] => src10_data[60].DATAIN -sink_data[60] => src11_data[60].DATAIN -sink_data[60] => src12_data[60].DATAIN -sink_data[60] => src13_data[60].DATAIN -sink_data[60] => src14_data[60].DATAIN -sink_data[60] => src15_data[60].DATAIN -sink_data[60] => src16_data[60].DATAIN -sink_data[61] => src17_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src2_data[61].DATAIN -sink_data[61] => src3_data[61].DATAIN -sink_data[61] => src4_data[61].DATAIN -sink_data[61] => src5_data[61].DATAIN -sink_data[61] => src6_data[61].DATAIN -sink_data[61] => src7_data[61].DATAIN -sink_data[61] => src8_data[61].DATAIN -sink_data[61] => src9_data[61].DATAIN -sink_data[61] => src10_data[61].DATAIN -sink_data[61] => src11_data[61].DATAIN -sink_data[61] => src12_data[61].DATAIN -sink_data[61] => src13_data[61].DATAIN -sink_data[61] => src14_data[61].DATAIN -sink_data[61] => src15_data[61].DATAIN -sink_data[61] => src16_data[61].DATAIN -sink_data[62] => src17_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src2_data[62].DATAIN -sink_data[62] => src3_data[62].DATAIN -sink_data[62] => src4_data[62].DATAIN -sink_data[62] => src5_data[62].DATAIN -sink_data[62] => src6_data[62].DATAIN -sink_data[62] => src7_data[62].DATAIN -sink_data[62] => src8_data[62].DATAIN -sink_data[62] => src9_data[62].DATAIN -sink_data[62] => src10_data[62].DATAIN -sink_data[62] => src11_data[62].DATAIN -sink_data[62] => src12_data[62].DATAIN -sink_data[62] => src13_data[62].DATAIN -sink_data[62] => src14_data[62].DATAIN -sink_data[62] => src15_data[62].DATAIN -sink_data[62] => src16_data[62].DATAIN -sink_data[63] => src17_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src2_data[63].DATAIN -sink_data[63] => src3_data[63].DATAIN -sink_data[63] => src4_data[63].DATAIN -sink_data[63] => src5_data[63].DATAIN -sink_data[63] => src6_data[63].DATAIN -sink_data[63] => src7_data[63].DATAIN -sink_data[63] => src8_data[63].DATAIN -sink_data[63] => src9_data[63].DATAIN -sink_data[63] => src10_data[63].DATAIN -sink_data[63] => src11_data[63].DATAIN -sink_data[63] => src12_data[63].DATAIN -sink_data[63] => src13_data[63].DATAIN -sink_data[63] => src14_data[63].DATAIN -sink_data[63] => src15_data[63].DATAIN -sink_data[63] => src16_data[63].DATAIN -sink_data[64] => src17_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src2_data[64].DATAIN -sink_data[64] => src3_data[64].DATAIN -sink_data[64] => src4_data[64].DATAIN -sink_data[64] => src5_data[64].DATAIN -sink_data[64] => src6_data[64].DATAIN -sink_data[64] => src7_data[64].DATAIN -sink_data[64] => src8_data[64].DATAIN -sink_data[64] => src9_data[64].DATAIN -sink_data[64] => src10_data[64].DATAIN -sink_data[64] => src11_data[64].DATAIN -sink_data[64] => src12_data[64].DATAIN -sink_data[64] => src13_data[64].DATAIN -sink_data[64] => src14_data[64].DATAIN -sink_data[64] => src15_data[64].DATAIN -sink_data[64] => src16_data[64].DATAIN -sink_data[65] => src17_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src2_data[65].DATAIN -sink_data[65] => src3_data[65].DATAIN -sink_data[65] => src4_data[65].DATAIN -sink_data[65] => src5_data[65].DATAIN -sink_data[65] => src6_data[65].DATAIN -sink_data[65] => src7_data[65].DATAIN -sink_data[65] => src8_data[65].DATAIN -sink_data[65] => src9_data[65].DATAIN -sink_data[65] => src10_data[65].DATAIN -sink_data[65] => src11_data[65].DATAIN -sink_data[65] => src12_data[65].DATAIN -sink_data[65] => src13_data[65].DATAIN -sink_data[65] => src14_data[65].DATAIN -sink_data[65] => src15_data[65].DATAIN -sink_data[65] => src16_data[65].DATAIN -sink_data[66] => src17_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src2_data[66].DATAIN -sink_data[66] => src3_data[66].DATAIN -sink_data[66] => src4_data[66].DATAIN -sink_data[66] => src5_data[66].DATAIN -sink_data[66] => src6_data[66].DATAIN -sink_data[66] => src7_data[66].DATAIN -sink_data[66] => src8_data[66].DATAIN -sink_data[66] => src9_data[66].DATAIN -sink_data[66] => src10_data[66].DATAIN -sink_data[66] => src11_data[66].DATAIN -sink_data[66] => src12_data[66].DATAIN -sink_data[66] => src13_data[66].DATAIN -sink_data[66] => src14_data[66].DATAIN -sink_data[66] => src15_data[66].DATAIN -sink_data[66] => src16_data[66].DATAIN -sink_data[67] => src17_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src2_data[67].DATAIN -sink_data[67] => src3_data[67].DATAIN -sink_data[67] => src4_data[67].DATAIN -sink_data[67] => src5_data[67].DATAIN -sink_data[67] => src6_data[67].DATAIN -sink_data[67] => src7_data[67].DATAIN -sink_data[67] => src8_data[67].DATAIN -sink_data[67] => src9_data[67].DATAIN -sink_data[67] => src10_data[67].DATAIN -sink_data[67] => src11_data[67].DATAIN -sink_data[67] => src12_data[67].DATAIN -sink_data[67] => src13_data[67].DATAIN -sink_data[67] => src14_data[67].DATAIN -sink_data[67] => src15_data[67].DATAIN -sink_data[67] => src16_data[67].DATAIN -sink_data[68] => src17_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src2_data[68].DATAIN -sink_data[68] => src3_data[68].DATAIN -sink_data[68] => src4_data[68].DATAIN -sink_data[68] => src5_data[68].DATAIN -sink_data[68] => src6_data[68].DATAIN -sink_data[68] => src7_data[68].DATAIN -sink_data[68] => src8_data[68].DATAIN -sink_data[68] => src9_data[68].DATAIN -sink_data[68] => src10_data[68].DATAIN -sink_data[68] => src11_data[68].DATAIN -sink_data[68] => src12_data[68].DATAIN -sink_data[68] => src13_data[68].DATAIN -sink_data[68] => src14_data[68].DATAIN -sink_data[68] => src15_data[68].DATAIN -sink_data[68] => src16_data[68].DATAIN -sink_data[69] => src17_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src2_data[69].DATAIN -sink_data[69] => src3_data[69].DATAIN -sink_data[69] => src4_data[69].DATAIN -sink_data[69] => src5_data[69].DATAIN -sink_data[69] => src6_data[69].DATAIN -sink_data[69] => src7_data[69].DATAIN -sink_data[69] => src8_data[69].DATAIN -sink_data[69] => src9_data[69].DATAIN -sink_data[69] => src10_data[69].DATAIN -sink_data[69] => src11_data[69].DATAIN -sink_data[69] => src12_data[69].DATAIN -sink_data[69] => src13_data[69].DATAIN -sink_data[69] => src14_data[69].DATAIN -sink_data[69] => src15_data[69].DATAIN -sink_data[69] => src16_data[69].DATAIN -sink_data[70] => src17_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src2_data[70].DATAIN -sink_data[70] => src3_data[70].DATAIN -sink_data[70] => src4_data[70].DATAIN -sink_data[70] => src5_data[70].DATAIN -sink_data[70] => src6_data[70].DATAIN -sink_data[70] => src7_data[70].DATAIN -sink_data[70] => src8_data[70].DATAIN -sink_data[70] => src9_data[70].DATAIN -sink_data[70] => src10_data[70].DATAIN -sink_data[70] => src11_data[70].DATAIN -sink_data[70] => src12_data[70].DATAIN -sink_data[70] => src13_data[70].DATAIN -sink_data[70] => src14_data[70].DATAIN -sink_data[70] => src15_data[70].DATAIN -sink_data[70] => src16_data[70].DATAIN -sink_data[71] => src17_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src2_data[71].DATAIN -sink_data[71] => src3_data[71].DATAIN -sink_data[71] => src4_data[71].DATAIN -sink_data[71] => src5_data[71].DATAIN -sink_data[71] => src6_data[71].DATAIN -sink_data[71] => src7_data[71].DATAIN -sink_data[71] => src8_data[71].DATAIN -sink_data[71] => src9_data[71].DATAIN -sink_data[71] => src10_data[71].DATAIN -sink_data[71] => src11_data[71].DATAIN -sink_data[71] => src12_data[71].DATAIN -sink_data[71] => src13_data[71].DATAIN -sink_data[71] => src14_data[71].DATAIN -sink_data[71] => src15_data[71].DATAIN -sink_data[71] => src16_data[71].DATAIN -sink_data[72] => src17_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src2_data[72].DATAIN -sink_data[72] => src3_data[72].DATAIN -sink_data[72] => src4_data[72].DATAIN -sink_data[72] => src5_data[72].DATAIN -sink_data[72] => src6_data[72].DATAIN -sink_data[72] => src7_data[72].DATAIN -sink_data[72] => src8_data[72].DATAIN -sink_data[72] => src9_data[72].DATAIN -sink_data[72] => src10_data[72].DATAIN -sink_data[72] => src11_data[72].DATAIN -sink_data[72] => src12_data[72].DATAIN -sink_data[72] => src13_data[72].DATAIN -sink_data[72] => src14_data[72].DATAIN -sink_data[72] => src15_data[72].DATAIN -sink_data[72] => src16_data[72].DATAIN -sink_data[73] => src17_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src2_data[73].DATAIN -sink_data[73] => src3_data[73].DATAIN -sink_data[73] => src4_data[73].DATAIN -sink_data[73] => src5_data[73].DATAIN -sink_data[73] => src6_data[73].DATAIN -sink_data[73] => src7_data[73].DATAIN -sink_data[73] => src8_data[73].DATAIN -sink_data[73] => src9_data[73].DATAIN -sink_data[73] => src10_data[73].DATAIN -sink_data[73] => src11_data[73].DATAIN -sink_data[73] => src12_data[73].DATAIN -sink_data[73] => src13_data[73].DATAIN -sink_data[73] => src14_data[73].DATAIN -sink_data[73] => src15_data[73].DATAIN -sink_data[73] => src16_data[73].DATAIN -sink_data[74] => src17_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src2_data[74].DATAIN -sink_data[74] => src3_data[74].DATAIN -sink_data[74] => src4_data[74].DATAIN -sink_data[74] => src5_data[74].DATAIN -sink_data[74] => src6_data[74].DATAIN -sink_data[74] => src7_data[74].DATAIN -sink_data[74] => src8_data[74].DATAIN -sink_data[74] => src9_data[74].DATAIN -sink_data[74] => src10_data[74].DATAIN -sink_data[74] => src11_data[74].DATAIN -sink_data[74] => src12_data[74].DATAIN -sink_data[74] => src13_data[74].DATAIN -sink_data[74] => src14_data[74].DATAIN -sink_data[74] => src15_data[74].DATAIN -sink_data[74] => src16_data[74].DATAIN -sink_data[75] => src17_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src2_data[75].DATAIN -sink_data[75] => src3_data[75].DATAIN -sink_data[75] => src4_data[75].DATAIN -sink_data[75] => src5_data[75].DATAIN -sink_data[75] => src6_data[75].DATAIN -sink_data[75] => src7_data[75].DATAIN -sink_data[75] => src8_data[75].DATAIN -sink_data[75] => src9_data[75].DATAIN -sink_data[75] => src10_data[75].DATAIN -sink_data[75] => src11_data[75].DATAIN -sink_data[75] => src12_data[75].DATAIN -sink_data[75] => src13_data[75].DATAIN -sink_data[75] => src14_data[75].DATAIN -sink_data[75] => src15_data[75].DATAIN -sink_data[75] => src16_data[75].DATAIN -sink_data[76] => src17_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src2_data[76].DATAIN -sink_data[76] => src3_data[76].DATAIN -sink_data[76] => src4_data[76].DATAIN -sink_data[76] => src5_data[76].DATAIN -sink_data[76] => src6_data[76].DATAIN -sink_data[76] => src7_data[76].DATAIN -sink_data[76] => src8_data[76].DATAIN -sink_data[76] => src9_data[76].DATAIN -sink_data[76] => src10_data[76].DATAIN -sink_data[76] => src11_data[76].DATAIN -sink_data[76] => src12_data[76].DATAIN -sink_data[76] => src13_data[76].DATAIN -sink_data[76] => src14_data[76].DATAIN -sink_data[76] => src15_data[76].DATAIN -sink_data[76] => src16_data[76].DATAIN -sink_data[77] => src17_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src2_data[77].DATAIN -sink_data[77] => src3_data[77].DATAIN -sink_data[77] => src4_data[77].DATAIN -sink_data[77] => src5_data[77].DATAIN -sink_data[77] => src6_data[77].DATAIN -sink_data[77] => src7_data[77].DATAIN -sink_data[77] => src8_data[77].DATAIN -sink_data[77] => src9_data[77].DATAIN -sink_data[77] => src10_data[77].DATAIN -sink_data[77] => src11_data[77].DATAIN -sink_data[77] => src12_data[77].DATAIN -sink_data[77] => src13_data[77].DATAIN -sink_data[77] => src14_data[77].DATAIN -sink_data[77] => src15_data[77].DATAIN -sink_data[77] => src16_data[77].DATAIN -sink_data[78] => src17_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src2_data[78].DATAIN -sink_data[78] => src3_data[78].DATAIN -sink_data[78] => src4_data[78].DATAIN -sink_data[78] => src5_data[78].DATAIN -sink_data[78] => src6_data[78].DATAIN -sink_data[78] => src7_data[78].DATAIN -sink_data[78] => src8_data[78].DATAIN -sink_data[78] => src9_data[78].DATAIN -sink_data[78] => src10_data[78].DATAIN -sink_data[78] => src11_data[78].DATAIN -sink_data[78] => src12_data[78].DATAIN -sink_data[78] => src13_data[78].DATAIN -sink_data[78] => src14_data[78].DATAIN -sink_data[78] => src15_data[78].DATAIN -sink_data[78] => src16_data[78].DATAIN -sink_data[79] => src17_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src2_data[79].DATAIN -sink_data[79] => src3_data[79].DATAIN -sink_data[79] => src4_data[79].DATAIN -sink_data[79] => src5_data[79].DATAIN -sink_data[79] => src6_data[79].DATAIN -sink_data[79] => src7_data[79].DATAIN -sink_data[79] => src8_data[79].DATAIN -sink_data[79] => src9_data[79].DATAIN -sink_data[79] => src10_data[79].DATAIN -sink_data[79] => src11_data[79].DATAIN -sink_data[79] => src12_data[79].DATAIN -sink_data[79] => src13_data[79].DATAIN -sink_data[79] => src14_data[79].DATAIN -sink_data[79] => src15_data[79].DATAIN -sink_data[79] => src16_data[79].DATAIN -sink_data[80] => src17_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src2_data[80].DATAIN -sink_data[80] => src3_data[80].DATAIN -sink_data[80] => src4_data[80].DATAIN -sink_data[80] => src5_data[80].DATAIN -sink_data[80] => src6_data[80].DATAIN -sink_data[80] => src7_data[80].DATAIN -sink_data[80] => src8_data[80].DATAIN -sink_data[80] => src9_data[80].DATAIN -sink_data[80] => src10_data[80].DATAIN -sink_data[80] => src11_data[80].DATAIN -sink_data[80] => src12_data[80].DATAIN -sink_data[80] => src13_data[80].DATAIN -sink_data[80] => src14_data[80].DATAIN -sink_data[80] => src15_data[80].DATAIN -sink_data[80] => src16_data[80].DATAIN -sink_data[81] => src17_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src2_data[81].DATAIN -sink_data[81] => src3_data[81].DATAIN -sink_data[81] => src4_data[81].DATAIN -sink_data[81] => src5_data[81].DATAIN -sink_data[81] => src6_data[81].DATAIN -sink_data[81] => src7_data[81].DATAIN -sink_data[81] => src8_data[81].DATAIN -sink_data[81] => src9_data[81].DATAIN -sink_data[81] => src10_data[81].DATAIN -sink_data[81] => src11_data[81].DATAIN -sink_data[81] => src12_data[81].DATAIN -sink_data[81] => src13_data[81].DATAIN -sink_data[81] => src14_data[81].DATAIN -sink_data[81] => src15_data[81].DATAIN -sink_data[81] => src16_data[81].DATAIN -sink_data[82] => src17_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src2_data[82].DATAIN -sink_data[82] => src3_data[82].DATAIN -sink_data[82] => src4_data[82].DATAIN -sink_data[82] => src5_data[82].DATAIN -sink_data[82] => src6_data[82].DATAIN -sink_data[82] => src7_data[82].DATAIN -sink_data[82] => src8_data[82].DATAIN -sink_data[82] => src9_data[82].DATAIN -sink_data[82] => src10_data[82].DATAIN -sink_data[82] => src11_data[82].DATAIN -sink_data[82] => src12_data[82].DATAIN -sink_data[82] => src13_data[82].DATAIN -sink_data[82] => src14_data[82].DATAIN -sink_data[82] => src15_data[82].DATAIN -sink_data[82] => src16_data[82].DATAIN -sink_data[83] => src17_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src2_data[83].DATAIN -sink_data[83] => src3_data[83].DATAIN -sink_data[83] => src4_data[83].DATAIN -sink_data[83] => src5_data[83].DATAIN -sink_data[83] => src6_data[83].DATAIN -sink_data[83] => src7_data[83].DATAIN -sink_data[83] => src8_data[83].DATAIN -sink_data[83] => src9_data[83].DATAIN -sink_data[83] => src10_data[83].DATAIN -sink_data[83] => src11_data[83].DATAIN -sink_data[83] => src12_data[83].DATAIN -sink_data[83] => src13_data[83].DATAIN -sink_data[83] => src14_data[83].DATAIN -sink_data[83] => src15_data[83].DATAIN -sink_data[83] => src16_data[83].DATAIN -sink_data[84] => src17_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src2_data[84].DATAIN -sink_data[84] => src3_data[84].DATAIN -sink_data[84] => src4_data[84].DATAIN -sink_data[84] => src5_data[84].DATAIN -sink_data[84] => src6_data[84].DATAIN -sink_data[84] => src7_data[84].DATAIN -sink_data[84] => src8_data[84].DATAIN -sink_data[84] => src9_data[84].DATAIN -sink_data[84] => src10_data[84].DATAIN -sink_data[84] => src11_data[84].DATAIN -sink_data[84] => src12_data[84].DATAIN -sink_data[84] => src13_data[84].DATAIN -sink_data[84] => src14_data[84].DATAIN -sink_data[84] => src15_data[84].DATAIN -sink_data[84] => src16_data[84].DATAIN -sink_data[85] => src17_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src2_data[85].DATAIN -sink_data[85] => src3_data[85].DATAIN -sink_data[85] => src4_data[85].DATAIN -sink_data[85] => src5_data[85].DATAIN -sink_data[85] => src6_data[85].DATAIN -sink_data[85] => src7_data[85].DATAIN -sink_data[85] => src8_data[85].DATAIN -sink_data[85] => src9_data[85].DATAIN -sink_data[85] => src10_data[85].DATAIN -sink_data[85] => src11_data[85].DATAIN -sink_data[85] => src12_data[85].DATAIN -sink_data[85] => src13_data[85].DATAIN -sink_data[85] => src14_data[85].DATAIN -sink_data[85] => src15_data[85].DATAIN -sink_data[85] => src16_data[85].DATAIN -sink_data[86] => src17_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src2_data[86].DATAIN -sink_data[86] => src3_data[86].DATAIN -sink_data[86] => src4_data[86].DATAIN -sink_data[86] => src5_data[86].DATAIN -sink_data[86] => src6_data[86].DATAIN -sink_data[86] => src7_data[86].DATAIN -sink_data[86] => src8_data[86].DATAIN -sink_data[86] => src9_data[86].DATAIN -sink_data[86] => src10_data[86].DATAIN -sink_data[86] => src11_data[86].DATAIN -sink_data[86] => src12_data[86].DATAIN -sink_data[86] => src13_data[86].DATAIN -sink_data[86] => src14_data[86].DATAIN -sink_data[86] => src15_data[86].DATAIN -sink_data[86] => src16_data[86].DATAIN -sink_data[87] => src17_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src2_data[87].DATAIN -sink_data[87] => src3_data[87].DATAIN -sink_data[87] => src4_data[87].DATAIN -sink_data[87] => src5_data[87].DATAIN -sink_data[87] => src6_data[87].DATAIN -sink_data[87] => src7_data[87].DATAIN -sink_data[87] => src8_data[87].DATAIN -sink_data[87] => src9_data[87].DATAIN -sink_data[87] => src10_data[87].DATAIN -sink_data[87] => src11_data[87].DATAIN -sink_data[87] => src12_data[87].DATAIN -sink_data[87] => src13_data[87].DATAIN -sink_data[87] => src14_data[87].DATAIN -sink_data[87] => src15_data[87].DATAIN -sink_data[87] => src16_data[87].DATAIN -sink_data[88] => src17_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src2_data[88].DATAIN -sink_data[88] => src3_data[88].DATAIN -sink_data[88] => src4_data[88].DATAIN -sink_data[88] => src5_data[88].DATAIN -sink_data[88] => src6_data[88].DATAIN -sink_data[88] => src7_data[88].DATAIN -sink_data[88] => src8_data[88].DATAIN -sink_data[88] => src9_data[88].DATAIN -sink_data[88] => src10_data[88].DATAIN -sink_data[88] => src11_data[88].DATAIN -sink_data[88] => src12_data[88].DATAIN -sink_data[88] => src13_data[88].DATAIN -sink_data[88] => src14_data[88].DATAIN -sink_data[88] => src15_data[88].DATAIN -sink_data[88] => src16_data[88].DATAIN -sink_data[89] => src17_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src2_data[89].DATAIN -sink_data[89] => src3_data[89].DATAIN -sink_data[89] => src4_data[89].DATAIN -sink_data[89] => src5_data[89].DATAIN -sink_data[89] => src6_data[89].DATAIN -sink_data[89] => src7_data[89].DATAIN -sink_data[89] => src8_data[89].DATAIN -sink_data[89] => src9_data[89].DATAIN -sink_data[89] => src10_data[89].DATAIN -sink_data[89] => src11_data[89].DATAIN -sink_data[89] => src12_data[89].DATAIN -sink_data[89] => src13_data[89].DATAIN -sink_data[89] => src14_data[89].DATAIN -sink_data[89] => src15_data[89].DATAIN -sink_data[89] => src16_data[89].DATAIN -sink_data[90] => src17_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src2_data[90].DATAIN -sink_data[90] => src3_data[90].DATAIN -sink_data[90] => src4_data[90].DATAIN -sink_data[90] => src5_data[90].DATAIN -sink_data[90] => src6_data[90].DATAIN -sink_data[90] => src7_data[90].DATAIN -sink_data[90] => src8_data[90].DATAIN -sink_data[90] => src9_data[90].DATAIN -sink_data[90] => src10_data[90].DATAIN -sink_data[90] => src11_data[90].DATAIN -sink_data[90] => src12_data[90].DATAIN -sink_data[90] => src13_data[90].DATAIN -sink_data[90] => src14_data[90].DATAIN -sink_data[90] => src15_data[90].DATAIN -sink_data[90] => src16_data[90].DATAIN -sink_data[91] => src17_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src2_data[91].DATAIN -sink_data[91] => src3_data[91].DATAIN -sink_data[91] => src4_data[91].DATAIN -sink_data[91] => src5_data[91].DATAIN -sink_data[91] => src6_data[91].DATAIN -sink_data[91] => src7_data[91].DATAIN -sink_data[91] => src8_data[91].DATAIN -sink_data[91] => src9_data[91].DATAIN -sink_data[91] => src10_data[91].DATAIN -sink_data[91] => src11_data[91].DATAIN -sink_data[91] => src12_data[91].DATAIN -sink_data[91] => src13_data[91].DATAIN -sink_data[91] => src14_data[91].DATAIN -sink_data[91] => src15_data[91].DATAIN -sink_data[91] => src16_data[91].DATAIN -sink_data[92] => src17_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src2_data[92].DATAIN -sink_data[92] => src3_data[92].DATAIN -sink_data[92] => src4_data[92].DATAIN -sink_data[92] => src5_data[92].DATAIN -sink_data[92] => src6_data[92].DATAIN -sink_data[92] => src7_data[92].DATAIN -sink_data[92] => src8_data[92].DATAIN -sink_data[92] => src9_data[92].DATAIN -sink_data[92] => src10_data[92].DATAIN -sink_data[92] => src11_data[92].DATAIN -sink_data[92] => src12_data[92].DATAIN -sink_data[92] => src13_data[92].DATAIN -sink_data[92] => src14_data[92].DATAIN -sink_data[92] => src15_data[92].DATAIN -sink_data[92] => src16_data[92].DATAIN -sink_data[93] => src17_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src2_data[93].DATAIN -sink_data[93] => src3_data[93].DATAIN -sink_data[93] => src4_data[93].DATAIN -sink_data[93] => src5_data[93].DATAIN -sink_data[93] => src6_data[93].DATAIN -sink_data[93] => src7_data[93].DATAIN -sink_data[93] => src8_data[93].DATAIN -sink_data[93] => src9_data[93].DATAIN -sink_data[93] => src10_data[93].DATAIN -sink_data[93] => src11_data[93].DATAIN -sink_data[93] => src12_data[93].DATAIN -sink_data[93] => src13_data[93].DATAIN -sink_data[93] => src14_data[93].DATAIN -sink_data[93] => src15_data[93].DATAIN -sink_data[93] => src16_data[93].DATAIN -sink_data[94] => src17_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src2_data[94].DATAIN -sink_data[94] => src3_data[94].DATAIN -sink_data[94] => src4_data[94].DATAIN -sink_data[94] => src5_data[94].DATAIN -sink_data[94] => src6_data[94].DATAIN -sink_data[94] => src7_data[94].DATAIN -sink_data[94] => src8_data[94].DATAIN -sink_data[94] => src9_data[94].DATAIN -sink_data[94] => src10_data[94].DATAIN -sink_data[94] => src11_data[94].DATAIN -sink_data[94] => src12_data[94].DATAIN -sink_data[94] => src13_data[94].DATAIN -sink_data[94] => src14_data[94].DATAIN -sink_data[94] => src15_data[94].DATAIN -sink_data[94] => src16_data[94].DATAIN -sink_data[95] => src17_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src2_data[95].DATAIN -sink_data[95] => src3_data[95].DATAIN -sink_data[95] => src4_data[95].DATAIN -sink_data[95] => src5_data[95].DATAIN -sink_data[95] => src6_data[95].DATAIN -sink_data[95] => src7_data[95].DATAIN -sink_data[95] => src8_data[95].DATAIN -sink_data[95] => src9_data[95].DATAIN -sink_data[95] => src10_data[95].DATAIN -sink_data[95] => src11_data[95].DATAIN -sink_data[95] => src12_data[95].DATAIN -sink_data[95] => src13_data[95].DATAIN -sink_data[95] => src14_data[95].DATAIN -sink_data[95] => src15_data[95].DATAIN -sink_data[95] => src16_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src2_valid.IN1 -sink_channel[2] => sink_ready.IN0 -sink_channel[3] => src3_valid.IN1 -sink_channel[3] => sink_ready.IN0 -sink_channel[4] => src4_valid.IN1 -sink_channel[4] => sink_ready.IN0 -sink_channel[5] => src5_valid.IN1 -sink_channel[5] => sink_ready.IN0 -sink_channel[6] => src6_valid.IN1 -sink_channel[6] => sink_ready.IN0 -sink_channel[7] => src7_valid.IN1 -sink_channel[7] => sink_ready.IN0 -sink_channel[8] => src8_valid.IN1 -sink_channel[8] => sink_ready.IN0 -sink_channel[9] => src9_valid.IN1 -sink_channel[9] => sink_ready.IN0 -sink_channel[10] => src10_valid.IN1 -sink_channel[10] => sink_ready.IN0 -sink_channel[11] => src11_valid.IN1 -sink_channel[11] => sink_ready.IN0 -sink_channel[12] => src12_valid.IN1 -sink_channel[12] => sink_ready.IN0 -sink_channel[13] => src13_valid.IN1 -sink_channel[13] => sink_ready.IN0 -sink_channel[14] => src14_valid.IN1 -sink_channel[14] => sink_ready.IN0 -sink_channel[15] => src15_valid.IN1 -sink_channel[15] => sink_ready.IN0 -sink_channel[16] => src16_valid.IN1 -sink_channel[16] => sink_ready.IN0 -sink_channel[17] => src17_valid.IN1 -sink_channel[17] => sink_ready.IN0 -sink_startofpacket => src17_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src2_startofpacket.DATAIN -sink_startofpacket => src3_startofpacket.DATAIN -sink_startofpacket => src4_startofpacket.DATAIN -sink_startofpacket => src5_startofpacket.DATAIN -sink_startofpacket => src6_startofpacket.DATAIN -sink_startofpacket => src7_startofpacket.DATAIN -sink_startofpacket => src8_startofpacket.DATAIN -sink_startofpacket => src9_startofpacket.DATAIN -sink_startofpacket => src10_startofpacket.DATAIN -sink_startofpacket => src11_startofpacket.DATAIN -sink_startofpacket => src12_startofpacket.DATAIN -sink_startofpacket => src13_startofpacket.DATAIN -sink_startofpacket => src14_startofpacket.DATAIN -sink_startofpacket => src15_startofpacket.DATAIN -sink_startofpacket => src16_startofpacket.DATAIN -sink_endofpacket => src17_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src2_endofpacket.DATAIN -sink_endofpacket => src3_endofpacket.DATAIN -sink_endofpacket => src4_endofpacket.DATAIN -sink_endofpacket => src5_endofpacket.DATAIN -sink_endofpacket => src6_endofpacket.DATAIN -sink_endofpacket => src7_endofpacket.DATAIN -sink_endofpacket => src8_endofpacket.DATAIN -sink_endofpacket => src9_endofpacket.DATAIN -sink_endofpacket => src10_endofpacket.DATAIN -sink_endofpacket => src11_endofpacket.DATAIN -sink_endofpacket => src12_endofpacket.DATAIN -sink_endofpacket => src13_endofpacket.DATAIN -sink_endofpacket => src14_endofpacket.DATAIN -sink_endofpacket => src15_endofpacket.DATAIN -sink_endofpacket => src16_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= -src0_channel[1] <= -src0_channel[2] <= -src0_channel[3] <= -src0_channel[4] <= -src0_channel[5] <= -src0_channel[6] <= -src0_channel[7] <= -src0_channel[8] <= -src0_channel[9] <= -src0_channel[10] <= -src0_channel[11] <= -src0_channel[12] <= -src0_channel[13] <= -src0_channel[14] <= -src0_channel[15] <= -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= -src1_channel[1] <= -src1_channel[2] <= -src1_channel[3] <= -src1_channel[4] <= -src1_channel[5] <= -src1_channel[6] <= -src1_channel[7] <= -src1_channel[8] <= -src1_channel[9] <= -src1_channel[10] <= -src1_channel[11] <= -src1_channel[12] <= -src1_channel[13] <= -src1_channel[14] <= -src1_channel[15] <= -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -src2_valid <= src2_valid.DB_MAX_OUTPUT_PORT_TYPE -src2_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src2_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src2_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src2_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src2_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src2_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src2_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src2_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src2_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src2_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src2_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src2_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src2_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src2_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src2_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src2_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src2_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src2_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src2_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src2_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src2_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src2_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src2_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src2_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src2_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src2_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src2_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src2_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src2_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src2_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src2_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src2_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src2_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src2_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src2_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src2_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src2_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src2_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src2_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src2_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src2_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src2_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src2_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src2_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src2_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src2_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src2_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src2_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src2_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src2_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src2_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src2_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src2_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src2_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src2_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src2_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src2_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src2_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src2_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src2_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src2_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src2_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src2_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src2_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src2_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src2_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src2_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src2_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src2_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src2_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src2_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src2_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src2_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src2_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src2_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src2_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src2_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src2_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src2_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src2_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src2_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src2_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src2_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src2_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src2_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src2_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src2_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src2_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src2_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src2_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src2_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src2_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src2_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src2_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src2_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src2_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src2_channel[0] <= -src2_channel[1] <= -src2_channel[2] <= -src2_channel[3] <= -src2_channel[4] <= -src2_channel[5] <= -src2_channel[6] <= -src2_channel[7] <= -src2_channel[8] <= -src2_channel[9] <= -src2_channel[10] <= -src2_channel[11] <= -src2_channel[12] <= -src2_channel[13] <= -src2_channel[14] <= -src2_channel[15] <= -src2_channel[16] <= -src2_channel[17] <= -src2_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src2_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src2_ready => sink_ready.IN1 -src3_valid <= src3_valid.DB_MAX_OUTPUT_PORT_TYPE -src3_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src3_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src3_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src3_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src3_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src3_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src3_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src3_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src3_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src3_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src3_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src3_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src3_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src3_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src3_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src3_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src3_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src3_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src3_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src3_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src3_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src3_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src3_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src3_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src3_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src3_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src3_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src3_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src3_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src3_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src3_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src3_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src3_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src3_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src3_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src3_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src3_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src3_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src3_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src3_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src3_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src3_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src3_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src3_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src3_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src3_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src3_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src3_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src3_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src3_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src3_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src3_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src3_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src3_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src3_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src3_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src3_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src3_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src3_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src3_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src3_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src3_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src3_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src3_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src3_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src3_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src3_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src3_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src3_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src3_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src3_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src3_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src3_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src3_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src3_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src3_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src3_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src3_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src3_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src3_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src3_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src3_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src3_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src3_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src3_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src3_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src3_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src3_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src3_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src3_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src3_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src3_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src3_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src3_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src3_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src3_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src3_channel[0] <= -src3_channel[1] <= -src3_channel[2] <= -src3_channel[3] <= -src3_channel[4] <= -src3_channel[5] <= -src3_channel[6] <= -src3_channel[7] <= -src3_channel[8] <= -src3_channel[9] <= -src3_channel[10] <= -src3_channel[11] <= -src3_channel[12] <= -src3_channel[13] <= -src3_channel[14] <= -src3_channel[15] <= -src3_channel[16] <= -src3_channel[17] <= -src3_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src3_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src3_ready => sink_ready.IN1 -src4_valid <= src4_valid.DB_MAX_OUTPUT_PORT_TYPE -src4_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src4_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src4_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src4_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src4_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src4_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src4_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src4_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src4_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src4_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src4_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src4_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src4_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src4_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src4_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src4_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src4_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src4_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src4_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src4_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src4_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src4_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src4_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src4_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src4_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src4_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src4_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src4_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src4_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src4_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src4_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src4_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src4_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src4_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src4_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src4_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src4_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src4_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src4_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src4_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src4_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src4_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src4_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src4_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src4_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src4_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src4_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src4_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src4_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src4_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src4_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src4_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src4_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src4_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src4_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src4_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src4_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src4_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src4_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src4_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src4_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src4_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src4_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src4_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src4_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src4_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src4_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src4_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src4_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src4_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src4_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src4_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src4_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src4_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src4_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src4_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src4_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src4_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src4_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src4_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src4_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src4_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src4_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src4_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src4_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src4_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src4_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src4_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src4_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src4_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src4_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src4_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src4_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src4_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src4_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src4_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src4_channel[0] <= -src4_channel[1] <= -src4_channel[2] <= -src4_channel[3] <= -src4_channel[4] <= -src4_channel[5] <= -src4_channel[6] <= -src4_channel[7] <= -src4_channel[8] <= -src4_channel[9] <= -src4_channel[10] <= -src4_channel[11] <= -src4_channel[12] <= -src4_channel[13] <= -src4_channel[14] <= -src4_channel[15] <= -src4_channel[16] <= -src4_channel[17] <= -src4_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src4_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src4_ready => sink_ready.IN1 -src5_valid <= src5_valid.DB_MAX_OUTPUT_PORT_TYPE -src5_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src5_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src5_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src5_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src5_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src5_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src5_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src5_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src5_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src5_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src5_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src5_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src5_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src5_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src5_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src5_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src5_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src5_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src5_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src5_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src5_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src5_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src5_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src5_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src5_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src5_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src5_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src5_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src5_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src5_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src5_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src5_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src5_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src5_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src5_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src5_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src5_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src5_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src5_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src5_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src5_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src5_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src5_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src5_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src5_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src5_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src5_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src5_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src5_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src5_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src5_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src5_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src5_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src5_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src5_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src5_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src5_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src5_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src5_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src5_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src5_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src5_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src5_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src5_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src5_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src5_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src5_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src5_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src5_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src5_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src5_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src5_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src5_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src5_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src5_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src5_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src5_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src5_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src5_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src5_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src5_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src5_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src5_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src5_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src5_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src5_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src5_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src5_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src5_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src5_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src5_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src5_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src5_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src5_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src5_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src5_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src5_channel[0] <= -src5_channel[1] <= -src5_channel[2] <= -src5_channel[3] <= -src5_channel[4] <= -src5_channel[5] <= -src5_channel[6] <= -src5_channel[7] <= -src5_channel[8] <= -src5_channel[9] <= -src5_channel[10] <= -src5_channel[11] <= -src5_channel[12] <= -src5_channel[13] <= -src5_channel[14] <= -src5_channel[15] <= -src5_channel[16] <= -src5_channel[17] <= -src5_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src5_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src5_ready => sink_ready.IN1 -src6_valid <= src6_valid.DB_MAX_OUTPUT_PORT_TYPE -src6_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src6_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src6_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src6_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src6_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src6_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src6_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src6_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src6_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src6_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src6_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src6_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src6_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src6_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src6_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src6_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src6_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src6_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src6_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src6_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src6_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src6_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src6_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src6_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src6_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src6_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src6_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src6_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src6_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src6_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src6_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src6_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src6_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src6_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src6_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src6_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src6_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src6_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src6_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src6_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src6_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src6_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src6_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src6_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src6_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src6_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src6_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src6_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src6_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src6_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src6_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src6_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src6_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src6_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src6_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src6_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src6_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src6_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src6_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src6_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src6_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src6_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src6_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src6_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src6_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src6_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src6_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src6_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src6_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src6_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src6_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src6_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src6_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src6_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src6_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src6_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src6_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src6_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src6_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src6_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src6_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src6_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src6_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src6_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src6_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src6_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src6_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src6_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src6_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src6_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src6_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src6_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src6_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src6_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src6_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src6_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src6_channel[0] <= -src6_channel[1] <= -src6_channel[2] <= -src6_channel[3] <= -src6_channel[4] <= -src6_channel[5] <= -src6_channel[6] <= -src6_channel[7] <= -src6_channel[8] <= -src6_channel[9] <= -src6_channel[10] <= -src6_channel[11] <= -src6_channel[12] <= -src6_channel[13] <= -src6_channel[14] <= -src6_channel[15] <= -src6_channel[16] <= -src6_channel[17] <= -src6_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src6_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src6_ready => sink_ready.IN1 -src7_valid <= src7_valid.DB_MAX_OUTPUT_PORT_TYPE -src7_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src7_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src7_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src7_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src7_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src7_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src7_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src7_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src7_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src7_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src7_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src7_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src7_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src7_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src7_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src7_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src7_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src7_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src7_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src7_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src7_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src7_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src7_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src7_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src7_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src7_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src7_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src7_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src7_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src7_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src7_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src7_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src7_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src7_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src7_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src7_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src7_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src7_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src7_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src7_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src7_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src7_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src7_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src7_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src7_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src7_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src7_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src7_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src7_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src7_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src7_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src7_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src7_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src7_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src7_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src7_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src7_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src7_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src7_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src7_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src7_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src7_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src7_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src7_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src7_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src7_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src7_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src7_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src7_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src7_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src7_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src7_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src7_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src7_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src7_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src7_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src7_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src7_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src7_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src7_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src7_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src7_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src7_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src7_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src7_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src7_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src7_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src7_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src7_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src7_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src7_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src7_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src7_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src7_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src7_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src7_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src7_channel[0] <= -src7_channel[1] <= -src7_channel[2] <= -src7_channel[3] <= -src7_channel[4] <= -src7_channel[5] <= -src7_channel[6] <= -src7_channel[7] <= -src7_channel[8] <= -src7_channel[9] <= -src7_channel[10] <= -src7_channel[11] <= -src7_channel[12] <= -src7_channel[13] <= -src7_channel[14] <= -src7_channel[15] <= -src7_channel[16] <= -src7_channel[17] <= -src7_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src7_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src7_ready => sink_ready.IN1 -src8_valid <= src8_valid.DB_MAX_OUTPUT_PORT_TYPE -src8_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src8_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src8_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src8_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src8_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src8_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src8_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src8_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src8_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src8_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src8_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src8_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src8_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src8_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src8_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src8_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src8_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src8_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src8_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src8_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src8_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src8_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src8_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src8_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src8_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src8_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src8_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src8_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src8_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src8_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src8_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src8_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src8_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src8_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src8_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src8_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src8_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src8_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src8_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src8_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src8_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src8_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src8_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src8_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src8_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src8_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src8_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src8_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src8_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src8_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src8_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src8_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src8_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src8_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src8_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src8_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src8_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src8_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src8_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src8_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src8_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src8_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src8_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src8_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src8_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src8_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src8_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src8_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src8_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src8_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src8_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src8_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src8_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src8_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src8_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src8_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src8_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src8_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src8_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src8_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src8_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src8_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src8_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src8_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src8_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src8_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src8_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src8_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src8_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src8_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src8_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src8_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src8_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src8_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src8_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src8_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src8_channel[0] <= -src8_channel[1] <= -src8_channel[2] <= -src8_channel[3] <= -src8_channel[4] <= -src8_channel[5] <= -src8_channel[6] <= -src8_channel[7] <= -src8_channel[8] <= -src8_channel[9] <= -src8_channel[10] <= -src8_channel[11] <= -src8_channel[12] <= -src8_channel[13] <= -src8_channel[14] <= -src8_channel[15] <= -src8_channel[16] <= -src8_channel[17] <= -src8_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src8_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src8_ready => sink_ready.IN1 -src9_valid <= src9_valid.DB_MAX_OUTPUT_PORT_TYPE -src9_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src9_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src9_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src9_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src9_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src9_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src9_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src9_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src9_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src9_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src9_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src9_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src9_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src9_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src9_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src9_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src9_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src9_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src9_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src9_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src9_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src9_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src9_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src9_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src9_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src9_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src9_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src9_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src9_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src9_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src9_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src9_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src9_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src9_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src9_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src9_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src9_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src9_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src9_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src9_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src9_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src9_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src9_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src9_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src9_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src9_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src9_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src9_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src9_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src9_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src9_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src9_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src9_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src9_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src9_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src9_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src9_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src9_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src9_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src9_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src9_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src9_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src9_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src9_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src9_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src9_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src9_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src9_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src9_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src9_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src9_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src9_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src9_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src9_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src9_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src9_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src9_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src9_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src9_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src9_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src9_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src9_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src9_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src9_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src9_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src9_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src9_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src9_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src9_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src9_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src9_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src9_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src9_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src9_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src9_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src9_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src9_channel[0] <= -src9_channel[1] <= -src9_channel[2] <= -src9_channel[3] <= -src9_channel[4] <= -src9_channel[5] <= -src9_channel[6] <= -src9_channel[7] <= -src9_channel[8] <= -src9_channel[9] <= -src9_channel[10] <= -src9_channel[11] <= -src9_channel[12] <= -src9_channel[13] <= -src9_channel[14] <= -src9_channel[15] <= -src9_channel[16] <= -src9_channel[17] <= -src9_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src9_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src9_ready => sink_ready.IN1 -src10_valid <= src10_valid.DB_MAX_OUTPUT_PORT_TYPE -src10_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src10_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src10_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src10_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src10_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src10_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src10_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src10_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src10_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src10_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src10_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src10_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src10_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src10_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src10_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src10_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src10_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src10_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src10_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src10_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src10_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src10_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src10_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src10_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src10_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src10_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src10_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src10_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src10_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src10_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src10_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src10_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src10_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src10_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src10_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src10_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src10_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src10_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src10_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src10_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src10_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src10_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src10_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src10_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src10_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src10_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src10_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src10_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src10_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src10_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src10_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src10_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src10_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src10_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src10_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src10_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src10_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src10_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src10_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src10_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src10_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src10_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src10_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src10_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src10_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src10_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src10_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src10_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src10_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src10_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src10_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src10_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src10_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src10_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src10_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src10_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src10_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src10_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src10_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src10_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src10_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src10_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src10_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src10_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src10_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src10_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src10_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src10_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src10_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src10_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src10_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src10_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src10_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src10_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src10_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src10_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src10_channel[0] <= -src10_channel[1] <= -src10_channel[2] <= -src10_channel[3] <= -src10_channel[4] <= -src10_channel[5] <= -src10_channel[6] <= -src10_channel[7] <= -src10_channel[8] <= -src10_channel[9] <= -src10_channel[10] <= -src10_channel[11] <= -src10_channel[12] <= -src10_channel[13] <= -src10_channel[14] <= -src10_channel[15] <= -src10_channel[16] <= -src10_channel[17] <= -src10_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src10_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src10_ready => sink_ready.IN1 -src11_valid <= src11_valid.DB_MAX_OUTPUT_PORT_TYPE -src11_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src11_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src11_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src11_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src11_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src11_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src11_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src11_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src11_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src11_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src11_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src11_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src11_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src11_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src11_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src11_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src11_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src11_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src11_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src11_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src11_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src11_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src11_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src11_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src11_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src11_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src11_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src11_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src11_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src11_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src11_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src11_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src11_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src11_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src11_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src11_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src11_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src11_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src11_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src11_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src11_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src11_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src11_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src11_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src11_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src11_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src11_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src11_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src11_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src11_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src11_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src11_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src11_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src11_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src11_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src11_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src11_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src11_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src11_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src11_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src11_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src11_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src11_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src11_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src11_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src11_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src11_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src11_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src11_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src11_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src11_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src11_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src11_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src11_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src11_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src11_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src11_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src11_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src11_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src11_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src11_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src11_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src11_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src11_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src11_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src11_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src11_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src11_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src11_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src11_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src11_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src11_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src11_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src11_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src11_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src11_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src11_channel[0] <= -src11_channel[1] <= -src11_channel[2] <= -src11_channel[3] <= -src11_channel[4] <= -src11_channel[5] <= -src11_channel[6] <= -src11_channel[7] <= -src11_channel[8] <= -src11_channel[9] <= -src11_channel[10] <= -src11_channel[11] <= -src11_channel[12] <= -src11_channel[13] <= -src11_channel[14] <= -src11_channel[15] <= -src11_channel[16] <= -src11_channel[17] <= -src11_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src11_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src11_ready => sink_ready.IN1 -src12_valid <= src12_valid.DB_MAX_OUTPUT_PORT_TYPE -src12_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src12_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src12_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src12_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src12_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src12_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src12_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src12_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src12_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src12_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src12_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src12_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src12_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src12_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src12_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src12_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src12_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src12_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src12_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src12_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src12_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src12_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src12_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src12_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src12_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src12_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src12_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src12_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src12_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src12_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src12_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src12_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src12_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src12_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src12_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src12_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src12_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src12_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src12_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src12_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src12_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src12_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src12_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src12_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src12_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src12_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src12_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src12_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src12_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src12_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src12_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src12_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src12_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src12_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src12_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src12_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src12_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src12_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src12_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src12_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src12_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src12_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src12_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src12_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src12_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src12_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src12_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src12_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src12_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src12_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src12_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src12_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src12_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src12_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src12_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src12_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src12_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src12_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src12_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src12_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src12_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src12_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src12_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src12_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src12_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src12_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src12_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src12_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src12_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src12_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src12_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src12_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src12_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src12_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src12_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src12_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src12_channel[0] <= -src12_channel[1] <= -src12_channel[2] <= -src12_channel[3] <= -src12_channel[4] <= -src12_channel[5] <= -src12_channel[6] <= -src12_channel[7] <= -src12_channel[8] <= -src12_channel[9] <= -src12_channel[10] <= -src12_channel[11] <= -src12_channel[12] <= -src12_channel[13] <= -src12_channel[14] <= -src12_channel[15] <= -src12_channel[16] <= -src12_channel[17] <= -src12_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src12_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src12_ready => sink_ready.IN1 -src13_valid <= src13_valid.DB_MAX_OUTPUT_PORT_TYPE -src13_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src13_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src13_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src13_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src13_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src13_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src13_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src13_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src13_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src13_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src13_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src13_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src13_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src13_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src13_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src13_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src13_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src13_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src13_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src13_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src13_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src13_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src13_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src13_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src13_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src13_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src13_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src13_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src13_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src13_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src13_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src13_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src13_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src13_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src13_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src13_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src13_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src13_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src13_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src13_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src13_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src13_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src13_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src13_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src13_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src13_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src13_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src13_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src13_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src13_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src13_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src13_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src13_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src13_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src13_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src13_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src13_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src13_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src13_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src13_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src13_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src13_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src13_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src13_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src13_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src13_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src13_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src13_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src13_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src13_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src13_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src13_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src13_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src13_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src13_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src13_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src13_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src13_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src13_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src13_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src13_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src13_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src13_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src13_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src13_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src13_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src13_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src13_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src13_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src13_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src13_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src13_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src13_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src13_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src13_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src13_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src13_channel[0] <= -src13_channel[1] <= -src13_channel[2] <= -src13_channel[3] <= -src13_channel[4] <= -src13_channel[5] <= -src13_channel[6] <= -src13_channel[7] <= -src13_channel[8] <= -src13_channel[9] <= -src13_channel[10] <= -src13_channel[11] <= -src13_channel[12] <= -src13_channel[13] <= -src13_channel[14] <= -src13_channel[15] <= -src13_channel[16] <= -src13_channel[17] <= -src13_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src13_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src13_ready => sink_ready.IN1 -src14_valid <= src14_valid.DB_MAX_OUTPUT_PORT_TYPE -src14_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src14_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src14_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src14_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src14_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src14_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src14_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src14_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src14_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src14_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src14_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src14_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src14_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src14_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src14_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src14_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src14_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src14_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src14_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src14_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src14_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src14_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src14_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src14_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src14_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src14_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src14_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src14_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src14_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src14_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src14_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src14_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src14_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src14_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src14_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src14_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src14_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src14_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src14_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src14_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src14_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src14_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src14_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src14_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src14_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src14_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src14_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src14_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src14_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src14_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src14_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src14_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src14_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src14_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src14_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src14_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src14_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src14_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src14_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src14_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src14_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src14_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src14_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src14_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src14_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src14_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src14_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src14_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src14_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src14_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src14_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src14_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src14_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src14_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src14_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src14_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src14_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src14_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src14_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src14_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src14_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src14_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src14_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src14_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src14_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src14_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src14_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src14_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src14_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src14_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src14_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src14_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src14_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src14_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src14_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src14_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src14_channel[0] <= -src14_channel[1] <= -src14_channel[2] <= -src14_channel[3] <= -src14_channel[4] <= -src14_channel[5] <= -src14_channel[6] <= -src14_channel[7] <= -src14_channel[8] <= -src14_channel[9] <= -src14_channel[10] <= -src14_channel[11] <= -src14_channel[12] <= -src14_channel[13] <= -src14_channel[14] <= -src14_channel[15] <= -src14_channel[16] <= -src14_channel[17] <= -src14_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src14_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src14_ready => sink_ready.IN1 -src15_valid <= src15_valid.DB_MAX_OUTPUT_PORT_TYPE -src15_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src15_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src15_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src15_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src15_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src15_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src15_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src15_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src15_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src15_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src15_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src15_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src15_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src15_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src15_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src15_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src15_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src15_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src15_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src15_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src15_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src15_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src15_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src15_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src15_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src15_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src15_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src15_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src15_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src15_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src15_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src15_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src15_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src15_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src15_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src15_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src15_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src15_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src15_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src15_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src15_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src15_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src15_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src15_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src15_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src15_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src15_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src15_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src15_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src15_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src15_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src15_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src15_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src15_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src15_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src15_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src15_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src15_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src15_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src15_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src15_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src15_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src15_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src15_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src15_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src15_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src15_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src15_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src15_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src15_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src15_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src15_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src15_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src15_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src15_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src15_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src15_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src15_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src15_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src15_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src15_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src15_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src15_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src15_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src15_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src15_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src15_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src15_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src15_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src15_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src15_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src15_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src15_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src15_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src15_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src15_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src15_channel[0] <= -src15_channel[1] <= -src15_channel[2] <= -src15_channel[3] <= -src15_channel[4] <= -src15_channel[5] <= -src15_channel[6] <= -src15_channel[7] <= -src15_channel[8] <= -src15_channel[9] <= -src15_channel[10] <= -src15_channel[11] <= -src15_channel[12] <= -src15_channel[13] <= -src15_channel[14] <= -src15_channel[15] <= -src15_channel[16] <= -src15_channel[17] <= -src15_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src15_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src15_ready => sink_ready.IN1 -src16_valid <= src16_valid.DB_MAX_OUTPUT_PORT_TYPE -src16_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src16_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src16_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src16_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src16_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src16_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src16_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src16_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src16_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src16_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src16_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src16_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src16_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src16_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src16_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src16_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src16_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src16_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src16_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src16_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src16_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src16_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src16_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src16_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src16_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src16_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src16_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src16_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src16_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src16_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src16_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src16_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src16_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src16_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src16_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src16_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src16_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src16_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src16_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src16_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src16_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src16_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src16_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src16_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src16_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src16_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src16_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src16_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src16_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src16_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src16_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src16_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src16_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src16_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src16_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src16_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src16_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src16_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src16_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src16_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src16_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src16_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src16_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src16_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src16_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src16_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src16_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src16_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src16_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src16_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src16_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src16_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src16_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src16_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src16_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src16_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src16_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src16_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src16_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src16_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src16_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src16_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src16_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src16_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src16_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src16_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src16_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src16_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src16_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src16_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src16_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src16_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src16_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src16_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src16_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src16_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src16_channel[0] <= -src16_channel[1] <= -src16_channel[2] <= -src16_channel[3] <= -src16_channel[4] <= -src16_channel[5] <= -src16_channel[6] <= -src16_channel[7] <= -src16_channel[8] <= -src16_channel[9] <= -src16_channel[10] <= -src16_channel[11] <= -src16_channel[12] <= -src16_channel[13] <= -src16_channel[14] <= -src16_channel[15] <= -src16_channel[16] <= -src16_channel[17] <= -src16_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src16_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src16_ready => sink_ready.IN1 -src17_valid <= src17_valid.DB_MAX_OUTPUT_PORT_TYPE -src17_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src17_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src17_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src17_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src17_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src17_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src17_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src17_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src17_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src17_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src17_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src17_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src17_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src17_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src17_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src17_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src17_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src17_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src17_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src17_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src17_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src17_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src17_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src17_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src17_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src17_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src17_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src17_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src17_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src17_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src17_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src17_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src17_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src17_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src17_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src17_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src17_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src17_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src17_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src17_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src17_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src17_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src17_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src17_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src17_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src17_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src17_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src17_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src17_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src17_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src17_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src17_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src17_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src17_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src17_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src17_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src17_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src17_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src17_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src17_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src17_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src17_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src17_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src17_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src17_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src17_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src17_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src17_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src17_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src17_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src17_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src17_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src17_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src17_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src17_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src17_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src17_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src17_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src17_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src17_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src17_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src17_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src17_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src17_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src17_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src17_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src17_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src17_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src17_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src17_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src17_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src17_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src17_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src17_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src17_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src17_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src17_channel[0] <= -src17_channel[1] <= -src17_channel[2] <= -src17_channel[3] <= -src17_channel[4] <= -src17_channel[5] <= -src17_channel[6] <= -src17_channel[7] <= -src17_channel[8] <= -src17_channel[9] <= -src17_channel[10] <= -src17_channel[11] <= -src17_channel[12] <= -src17_channel[13] <= -src17_channel[14] <= -src17_channel[15] <= -src17_channel[16] <= -src17_channel[17] <= -src17_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src17_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src17_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux -sink0_valid => request.IN1 -sink0_valid => src_valid.IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => locked.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request.IN1 -sink1_valid => src_valid.IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => locked.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb -clk => top_priority_reg[0].CLK -clk => top_priority_reg[1].CLK -reset => top_priority_reg[0].PRESET -reset => top_priority_reg[1].ACLR -request[0] => grant_double_vector[0].IN1 -request[0] => grant_double_vector[2].IN1 -request[0] => WideOr0.IN0 -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant_double_vector[1].IN1 -request[1] => grant_double_vector[3].IN1 -request[1] => WideOr0.IN1 -request[1] => _.IN1 -request[1] => _.IN1 -grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => top_priority_reg.OUTPUTSELECT -increment_top_priority => top_priority_reg.OUTPUTSELECT -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => sum.IN0 -a[0] => full_adder.cout[0].IN0 -a[1] => cout.IN0 -a[1] => cout.IN0 -a[2] => cout.IN0 -a[2] => cout.IN0 -a[3] => sum.IN0 -b[0] => sum.IN1 -b[0] => full_adder.cout[0].IN1 -b[1] => cout.IN1 -b[1] => cout.IN1 -b[2] => cout.IN1 -b[2] => cout.IN1 -b[3] => sum.IN1 -sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 -sink0_valid => request.IN1 -sink0_valid => src_valid.IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => locked.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request.IN1 -sink1_valid => src_valid.IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => locked.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb -clk => top_priority_reg[0].CLK -clk => top_priority_reg[1].CLK -reset => top_priority_reg[0].PRESET -reset => top_priority_reg[1].ACLR -request[0] => grant_double_vector[0].IN1 -request[0] => grant_double_vector[2].IN1 -request[0] => WideOr0.IN0 -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant_double_vector[1].IN1 -request[1] => grant_double_vector[3].IN1 -request[1] => WideOr0.IN1 -request[1] => _.IN1 -request[1] => _.IN1 -grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => top_priority_reg.OUTPUTSELECT -increment_top_priority => top_priority_reg.OUTPUTSELECT -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => sum.IN0 -a[0] => full_adder.cout[0].IN0 -a[1] => cout.IN0 -a[1] => cout.IN0 -a[2] => cout.IN0 -a[2] => cout.IN0 -a[3] => sum.IN0 -b[0] => sum.IN1 -b[0] => full_adder.cout[0].IN1 -b[1] => cout.IN1 -b[1] => cout.IN1 -b[2] => cout.IN1 -b[2] => cout.IN1 -b[3] => sum.IN1 -sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src1_channel[0].DATAIN -sink_channel[2] => src0_channel[0].DATAIN -sink_channel[3] => src1_channel[1].DATAIN -sink_channel[3] => src0_channel[1].DATAIN -sink_channel[4] => src1_channel[2].DATAIN -sink_channel[4] => src0_channel[2].DATAIN -sink_channel[5] => src1_channel[3].DATAIN -sink_channel[5] => src0_channel[3].DATAIN -sink_channel[6] => src1_channel[4].DATAIN -sink_channel[6] => src0_channel[4].DATAIN -sink_channel[7] => src1_channel[5].DATAIN -sink_channel[7] => src0_channel[5].DATAIN -sink_channel[8] => src1_channel[6].DATAIN -sink_channel[8] => src0_channel[6].DATAIN -sink_channel[9] => src1_channel[7].DATAIN -sink_channel[9] => src0_channel[7].DATAIN -sink_channel[10] => src1_channel[8].DATAIN -sink_channel[10] => src0_channel[8].DATAIN -sink_channel[11] => src1_channel[9].DATAIN -sink_channel[11] => src0_channel[9].DATAIN -sink_channel[12] => src1_channel[10].DATAIN -sink_channel[12] => src0_channel[10].DATAIN -sink_channel[13] => src1_channel[11].DATAIN -sink_channel[13] => src0_channel[11].DATAIN -sink_channel[14] => src1_channel[12].DATAIN -sink_channel[14] => src0_channel[12].DATAIN -sink_channel[15] => src1_channel[13].DATAIN -sink_channel[15] => src0_channel[13].DATAIN -sink_channel[16] => src1_channel[14].DATAIN -sink_channel[16] => src0_channel[14].DATAIN -sink_channel[17] => src1_channel[15].DATAIN -sink_channel[17] => src0_channel[15].DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 -sink_valid[0] => src0_valid.IN0 -sink_valid[0] => src1_valid.IN0 -sink_data[0] => src1_data[0].DATAIN -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src1_data[1].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src1_data[2].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src1_data[3].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src1_data[4].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src1_data[5].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src1_data[6].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src1_data[7].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src1_data[8].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src1_data[9].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src1_data[10].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src1_data[11].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src1_data[12].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src1_data[13].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src1_data[14].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src1_data[15].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src1_data[16].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src1_data[17].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src1_data[18].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src1_data[19].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src1_data[20].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src1_data[21].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src1_data[22].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src1_data[23].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src1_data[24].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src1_data[25].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src1_data[26].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src1_data[27].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src1_data[28].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src1_data[29].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src1_data[30].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src1_data[31].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src1_data[32].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src1_data[33].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src1_data[34].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src1_data[35].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src1_data[36].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src1_data[37].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src1_data[38].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src1_data[39].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src1_data[40].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src1_data[41].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src1_data[42].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src1_data[43].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src1_data[44].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src1_data[45].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src1_data[46].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src1_data[47].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src1_data[48].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src1_data[49].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src1_data[50].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src1_data[51].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src1_data[52].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src1_data[53].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src1_data[54].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src1_data[55].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src1_data[56].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src1_data[57].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src1_data[58].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src1_data[59].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src1_data[60].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src1_data[61].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src1_data[62].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src1_data[63].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src1_data[64].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src1_data[65].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src1_data[66].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src1_data[67].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src1_data[68].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src1_data[69].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src1_data[70].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src1_data[71].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src1_data[72].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src1_data[73].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src1_data[74].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src1_data[75].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src1_data[76].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src1_data[77].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src1_data[78].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src1_data[79].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src1_data[80].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src1_data[81].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src1_data[82].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src1_data[83].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src1_data[84].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src1_data[85].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src1_data[86].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src1_data[87].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src1_data[88].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src1_data[89].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src1_data[90].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src1_data[91].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src1_data[92].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src1_data[93].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src1_data[94].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src1_data[95].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src1_valid.IN1 -sink_channel[1] => sink_ready.IN0 -sink_channel[2] => src1_channel[0].DATAIN -sink_channel[2] => src0_channel[0].DATAIN -sink_channel[3] => src1_channel[1].DATAIN -sink_channel[3] => src0_channel[1].DATAIN -sink_channel[4] => src1_channel[2].DATAIN -sink_channel[4] => src0_channel[2].DATAIN -sink_channel[5] => src1_channel[3].DATAIN -sink_channel[5] => src0_channel[3].DATAIN -sink_channel[6] => src1_channel[4].DATAIN -sink_channel[6] => src0_channel[4].DATAIN -sink_channel[7] => src1_channel[5].DATAIN -sink_channel[7] => src0_channel[5].DATAIN -sink_channel[8] => src1_channel[6].DATAIN -sink_channel[8] => src0_channel[6].DATAIN -sink_channel[9] => src1_channel[7].DATAIN -sink_channel[9] => src0_channel[7].DATAIN -sink_channel[10] => src1_channel[8].DATAIN -sink_channel[10] => src0_channel[8].DATAIN -sink_channel[11] => src1_channel[9].DATAIN -sink_channel[11] => src0_channel[9].DATAIN -sink_channel[12] => src1_channel[10].DATAIN -sink_channel[12] => src0_channel[10].DATAIN -sink_channel[13] => src1_channel[11].DATAIN -sink_channel[13] => src0_channel[11].DATAIN -sink_channel[14] => src1_channel[12].DATAIN -sink_channel[14] => src0_channel[12].DATAIN -sink_channel[15] => src1_channel[13].DATAIN -sink_channel[15] => src0_channel[13].DATAIN -sink_channel[16] => src1_channel[14].DATAIN -sink_channel[16] => src0_channel[14].DATAIN -sink_channel[17] => src1_channel[15].DATAIN -sink_channel[17] => src0_channel[15].DATAIN -sink_startofpacket => src1_startofpacket.DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src1_endofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE -src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src1_channel[16] <= -src1_channel[17] <= -src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src1_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 -sink_valid[0] => src0_valid.IN0 -sink_data[0] => src0_data[0].DATAIN -sink_data[1] => src0_data[1].DATAIN -sink_data[2] => src0_data[2].DATAIN -sink_data[3] => src0_data[3].DATAIN -sink_data[4] => src0_data[4].DATAIN -sink_data[5] => src0_data[5].DATAIN -sink_data[6] => src0_data[6].DATAIN -sink_data[7] => src0_data[7].DATAIN -sink_data[8] => src0_data[8].DATAIN -sink_data[9] => src0_data[9].DATAIN -sink_data[10] => src0_data[10].DATAIN -sink_data[11] => src0_data[11].DATAIN -sink_data[12] => src0_data[12].DATAIN -sink_data[13] => src0_data[13].DATAIN -sink_data[14] => src0_data[14].DATAIN -sink_data[15] => src0_data[15].DATAIN -sink_data[16] => src0_data[16].DATAIN -sink_data[17] => src0_data[17].DATAIN -sink_data[18] => src0_data[18].DATAIN -sink_data[19] => src0_data[19].DATAIN -sink_data[20] => src0_data[20].DATAIN -sink_data[21] => src0_data[21].DATAIN -sink_data[22] => src0_data[22].DATAIN -sink_data[23] => src0_data[23].DATAIN -sink_data[24] => src0_data[24].DATAIN -sink_data[25] => src0_data[25].DATAIN -sink_data[26] => src0_data[26].DATAIN -sink_data[27] => src0_data[27].DATAIN -sink_data[28] => src0_data[28].DATAIN -sink_data[29] => src0_data[29].DATAIN -sink_data[30] => src0_data[30].DATAIN -sink_data[31] => src0_data[31].DATAIN -sink_data[32] => src0_data[32].DATAIN -sink_data[33] => src0_data[33].DATAIN -sink_data[34] => src0_data[34].DATAIN -sink_data[35] => src0_data[35].DATAIN -sink_data[36] => src0_data[36].DATAIN -sink_data[37] => src0_data[37].DATAIN -sink_data[38] => src0_data[38].DATAIN -sink_data[39] => src0_data[39].DATAIN -sink_data[40] => src0_data[40].DATAIN -sink_data[41] => src0_data[41].DATAIN -sink_data[42] => src0_data[42].DATAIN -sink_data[43] => src0_data[43].DATAIN -sink_data[44] => src0_data[44].DATAIN -sink_data[45] => src0_data[45].DATAIN -sink_data[46] => src0_data[46].DATAIN -sink_data[47] => src0_data[47].DATAIN -sink_data[48] => src0_data[48].DATAIN -sink_data[49] => src0_data[49].DATAIN -sink_data[50] => src0_data[50].DATAIN -sink_data[51] => src0_data[51].DATAIN -sink_data[52] => src0_data[52].DATAIN -sink_data[53] => src0_data[53].DATAIN -sink_data[54] => src0_data[54].DATAIN -sink_data[55] => src0_data[55].DATAIN -sink_data[56] => src0_data[56].DATAIN -sink_data[57] => src0_data[57].DATAIN -sink_data[58] => src0_data[58].DATAIN -sink_data[59] => src0_data[59].DATAIN -sink_data[60] => src0_data[60].DATAIN -sink_data[61] => src0_data[61].DATAIN -sink_data[62] => src0_data[62].DATAIN -sink_data[63] => src0_data[63].DATAIN -sink_data[64] => src0_data[64].DATAIN -sink_data[65] => src0_data[65].DATAIN -sink_data[66] => src0_data[66].DATAIN -sink_data[67] => src0_data[67].DATAIN -sink_data[68] => src0_data[68].DATAIN -sink_data[69] => src0_data[69].DATAIN -sink_data[70] => src0_data[70].DATAIN -sink_data[71] => src0_data[71].DATAIN -sink_data[72] => src0_data[72].DATAIN -sink_data[73] => src0_data[73].DATAIN -sink_data[74] => src0_data[74].DATAIN -sink_data[75] => src0_data[75].DATAIN -sink_data[76] => src0_data[76].DATAIN -sink_data[77] => src0_data[77].DATAIN -sink_data[78] => src0_data[78].DATAIN -sink_data[79] => src0_data[79].DATAIN -sink_data[80] => src0_data[80].DATAIN -sink_data[81] => src0_data[81].DATAIN -sink_data[82] => src0_data[82].DATAIN -sink_data[83] => src0_data[83].DATAIN -sink_data[84] => src0_data[84].DATAIN -sink_data[85] => src0_data[85].DATAIN -sink_data[86] => src0_data[86].DATAIN -sink_data[87] => src0_data[87].DATAIN -sink_data[88] => src0_data[88].DATAIN -sink_data[89] => src0_data[89].DATAIN -sink_data[90] => src0_data[90].DATAIN -sink_data[91] => src0_data[91].DATAIN -sink_data[92] => src0_data[92].DATAIN -sink_data[93] => src0_data[93].DATAIN -sink_data[94] => src0_data[94].DATAIN -sink_data[95] => src0_data[95].DATAIN -sink_channel[0] => src0_valid.IN1 -sink_channel[0] => sink_ready.IN0 -sink_channel[1] => src0_channel[0].DATAIN -sink_channel[2] => src0_channel[1].DATAIN -sink_channel[3] => src0_channel[2].DATAIN -sink_channel[4] => src0_channel[3].DATAIN -sink_channel[5] => src0_channel[4].DATAIN -sink_channel[6] => src0_channel[5].DATAIN -sink_channel[7] => src0_channel[6].DATAIN -sink_channel[8] => src0_channel[7].DATAIN -sink_channel[9] => src0_channel[8].DATAIN -sink_channel[10] => src0_channel[9].DATAIN -sink_channel[11] => src0_channel[10].DATAIN -sink_channel[12] => src0_channel[11].DATAIN -sink_channel[13] => src0_channel[12].DATAIN -sink_channel[14] => src0_channel[13].DATAIN -sink_channel[15] => src0_channel[14].DATAIN -sink_channel[16] => src0_channel[15].DATAIN -sink_channel[17] => src0_channel[16].DATAIN -sink_startofpacket => src0_startofpacket.DATAIN -sink_endofpacket => src0_endofpacket.DATAIN -sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE -src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE -src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE -src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE -src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE -src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE -src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE -src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE -src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE -src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE -src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE -src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE -src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE -src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE -src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE -src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE -src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE -src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE -src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE -src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE -src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE -src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE -src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE -src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE -src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE -src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE -src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE -src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE -src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE -src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE -src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE -src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE -src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE -src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE -src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE -src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE -src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE -src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE -src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE -src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE -src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE -src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE -src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE -src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE -src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE -src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE -src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE -src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE -src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE -src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE -src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE -src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE -src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE -src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE -src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE -src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE -src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE -src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE -src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE -src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE -src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE -src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE -src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE -src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE -src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE -src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE -src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE -src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE -src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE -src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE -src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE -src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE -src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE -src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE -src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE -src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE -src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE -src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE -src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE -src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE -src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE -src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE -src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE -src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE -src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE -src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE -src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE -src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE -src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE -src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE -src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE -src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE -src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE -src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE -src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE -src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE -src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE -src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE -src0_channel[17] <= -src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE -src0_ready => sink_ready.IN1 -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux -sink0_valid => request[0].IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[59] => last_cycle.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request[1].IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[59] => last_cycle.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -request[0] => grant[0].DATAIN -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant[1].DATAIN -request[1] => _.IN1 -request[1] => _.IN1 -grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => ~NO_FANOUT~ -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => sum.IN0 -a[0] => full_adder.cout[0].IN0 -a[1] => cout.IN0 -a[1] => cout.IN0 -a[2] => cout.IN0 -a[2] => cout.IN0 -a[3] => sum.IN0 -b[0] => sum.IN1 -b[0] => full_adder.cout[0].IN1 -b[1] => cout.IN1 -b[1] => cout.IN1 -b[2] => cout.IN1 -b[2] => cout.IN1 -b[3] => sum.IN1 -sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 -sink0_valid => request[0].IN1 -sink0_data[0] => src_payload.IN1 -sink0_data[1] => src_payload.IN1 -sink0_data[2] => src_payload.IN1 -sink0_data[3] => src_payload.IN1 -sink0_data[4] => src_payload.IN1 -sink0_data[5] => src_payload.IN1 -sink0_data[6] => src_payload.IN1 -sink0_data[7] => src_payload.IN1 -sink0_data[8] => src_payload.IN1 -sink0_data[9] => src_payload.IN1 -sink0_data[10] => src_payload.IN1 -sink0_data[11] => src_payload.IN1 -sink0_data[12] => src_payload.IN1 -sink0_data[13] => src_payload.IN1 -sink0_data[14] => src_payload.IN1 -sink0_data[15] => src_payload.IN1 -sink0_data[16] => src_payload.IN1 -sink0_data[17] => src_payload.IN1 -sink0_data[18] => src_payload.IN1 -sink0_data[19] => src_payload.IN1 -sink0_data[20] => src_payload.IN1 -sink0_data[21] => src_payload.IN1 -sink0_data[22] => src_payload.IN1 -sink0_data[23] => src_payload.IN1 -sink0_data[24] => src_payload.IN1 -sink0_data[25] => src_payload.IN1 -sink0_data[26] => src_payload.IN1 -sink0_data[27] => src_payload.IN1 -sink0_data[28] => src_payload.IN1 -sink0_data[29] => src_payload.IN1 -sink0_data[30] => src_payload.IN1 -sink0_data[31] => src_payload.IN1 -sink0_data[32] => src_payload.IN1 -sink0_data[33] => src_payload.IN1 -sink0_data[34] => src_payload.IN1 -sink0_data[35] => src_payload.IN1 -sink0_data[36] => src_payload.IN1 -sink0_data[37] => src_payload.IN1 -sink0_data[38] => src_payload.IN1 -sink0_data[39] => src_payload.IN1 -sink0_data[40] => src_payload.IN1 -sink0_data[41] => src_payload.IN1 -sink0_data[42] => src_payload.IN1 -sink0_data[43] => src_payload.IN1 -sink0_data[44] => src_payload.IN1 -sink0_data[45] => src_payload.IN1 -sink0_data[46] => src_payload.IN1 -sink0_data[47] => src_payload.IN1 -sink0_data[48] => src_payload.IN1 -sink0_data[49] => src_payload.IN1 -sink0_data[50] => src_payload.IN1 -sink0_data[51] => src_payload.IN1 -sink0_data[52] => src_payload.IN1 -sink0_data[53] => src_payload.IN1 -sink0_data[54] => src_payload.IN1 -sink0_data[55] => src_payload.IN1 -sink0_data[56] => src_payload.IN1 -sink0_data[57] => src_payload.IN1 -sink0_data[58] => src_payload.IN1 -sink0_data[59] => src_payload.IN1 -sink0_data[59] => last_cycle.IN1 -sink0_data[60] => src_payload.IN1 -sink0_data[61] => src_payload.IN1 -sink0_data[62] => src_payload.IN1 -sink0_data[63] => src_payload.IN1 -sink0_data[64] => src_payload.IN1 -sink0_data[65] => src_payload.IN1 -sink0_data[66] => src_payload.IN1 -sink0_data[67] => src_payload.IN1 -sink0_data[68] => src_payload.IN1 -sink0_data[69] => src_payload.IN1 -sink0_data[70] => src_payload.IN1 -sink0_data[71] => src_payload.IN1 -sink0_data[72] => src_payload.IN1 -sink0_data[73] => src_payload.IN1 -sink0_data[74] => src_payload.IN1 -sink0_data[75] => src_payload.IN1 -sink0_data[76] => src_payload.IN1 -sink0_data[77] => src_payload.IN1 -sink0_data[78] => src_payload.IN1 -sink0_data[79] => src_payload.IN1 -sink0_data[80] => src_payload.IN1 -sink0_data[81] => src_payload.IN1 -sink0_data[82] => src_payload.IN1 -sink0_data[83] => src_payload.IN1 -sink0_data[84] => src_payload.IN1 -sink0_data[85] => src_payload.IN1 -sink0_data[86] => src_payload.IN1 -sink0_data[87] => src_payload.IN1 -sink0_data[88] => src_payload.IN1 -sink0_data[89] => src_payload.IN1 -sink0_data[90] => src_payload.IN1 -sink0_data[91] => src_payload.IN1 -sink0_data[92] => src_payload.IN1 -sink0_data[93] => src_payload.IN1 -sink0_data[94] => src_payload.IN1 -sink0_data[95] => src_payload.IN1 -sink0_channel[0] => src_payload.IN1 -sink0_channel[1] => src_payload.IN1 -sink0_channel[2] => src_payload.IN1 -sink0_channel[3] => src_payload.IN1 -sink0_channel[4] => src_payload.IN1 -sink0_channel[5] => src_payload.IN1 -sink0_channel[6] => src_payload.IN1 -sink0_channel[7] => src_payload.IN1 -sink0_channel[8] => src_payload.IN1 -sink0_channel[9] => src_payload.IN1 -sink0_channel[10] => src_payload.IN1 -sink0_channel[11] => src_payload.IN1 -sink0_channel[12] => src_payload.IN1 -sink0_channel[13] => src_payload.IN1 -sink0_channel[14] => src_payload.IN1 -sink0_channel[15] => src_payload.IN1 -sink0_channel[16] => src_payload.IN1 -sink0_channel[17] => src_payload.IN1 -sink0_startofpacket => src_payload.IN1 -sink0_endofpacket => src_payload.IN1 -sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE -sink1_valid => request[1].IN1 -sink1_data[0] => src_payload.IN1 -sink1_data[1] => src_payload.IN1 -sink1_data[2] => src_payload.IN1 -sink1_data[3] => src_payload.IN1 -sink1_data[4] => src_payload.IN1 -sink1_data[5] => src_payload.IN1 -sink1_data[6] => src_payload.IN1 -sink1_data[7] => src_payload.IN1 -sink1_data[8] => src_payload.IN1 -sink1_data[9] => src_payload.IN1 -sink1_data[10] => src_payload.IN1 -sink1_data[11] => src_payload.IN1 -sink1_data[12] => src_payload.IN1 -sink1_data[13] => src_payload.IN1 -sink1_data[14] => src_payload.IN1 -sink1_data[15] => src_payload.IN1 -sink1_data[16] => src_payload.IN1 -sink1_data[17] => src_payload.IN1 -sink1_data[18] => src_payload.IN1 -sink1_data[19] => src_payload.IN1 -sink1_data[20] => src_payload.IN1 -sink1_data[21] => src_payload.IN1 -sink1_data[22] => src_payload.IN1 -sink1_data[23] => src_payload.IN1 -sink1_data[24] => src_payload.IN1 -sink1_data[25] => src_payload.IN1 -sink1_data[26] => src_payload.IN1 -sink1_data[27] => src_payload.IN1 -sink1_data[28] => src_payload.IN1 -sink1_data[29] => src_payload.IN1 -sink1_data[30] => src_payload.IN1 -sink1_data[31] => src_payload.IN1 -sink1_data[32] => src_payload.IN1 -sink1_data[33] => src_payload.IN1 -sink1_data[34] => src_payload.IN1 -sink1_data[35] => src_payload.IN1 -sink1_data[36] => src_payload.IN1 -sink1_data[37] => src_payload.IN1 -sink1_data[38] => src_payload.IN1 -sink1_data[39] => src_payload.IN1 -sink1_data[40] => src_payload.IN1 -sink1_data[41] => src_payload.IN1 -sink1_data[42] => src_payload.IN1 -sink1_data[43] => src_payload.IN1 -sink1_data[44] => src_payload.IN1 -sink1_data[45] => src_payload.IN1 -sink1_data[46] => src_payload.IN1 -sink1_data[47] => src_payload.IN1 -sink1_data[48] => src_payload.IN1 -sink1_data[49] => src_payload.IN1 -sink1_data[50] => src_payload.IN1 -sink1_data[51] => src_payload.IN1 -sink1_data[52] => src_payload.IN1 -sink1_data[53] => src_payload.IN1 -sink1_data[54] => src_payload.IN1 -sink1_data[55] => src_payload.IN1 -sink1_data[56] => src_payload.IN1 -sink1_data[57] => src_payload.IN1 -sink1_data[58] => src_payload.IN1 -sink1_data[59] => src_payload.IN1 -sink1_data[59] => last_cycle.IN1 -sink1_data[60] => src_payload.IN1 -sink1_data[61] => src_payload.IN1 -sink1_data[62] => src_payload.IN1 -sink1_data[63] => src_payload.IN1 -sink1_data[64] => src_payload.IN1 -sink1_data[65] => src_payload.IN1 -sink1_data[66] => src_payload.IN1 -sink1_data[67] => src_payload.IN1 -sink1_data[68] => src_payload.IN1 -sink1_data[69] => src_payload.IN1 -sink1_data[70] => src_payload.IN1 -sink1_data[71] => src_payload.IN1 -sink1_data[72] => src_payload.IN1 -sink1_data[73] => src_payload.IN1 -sink1_data[74] => src_payload.IN1 -sink1_data[75] => src_payload.IN1 -sink1_data[76] => src_payload.IN1 -sink1_data[77] => src_payload.IN1 -sink1_data[78] => src_payload.IN1 -sink1_data[79] => src_payload.IN1 -sink1_data[80] => src_payload.IN1 -sink1_data[81] => src_payload.IN1 -sink1_data[82] => src_payload.IN1 -sink1_data[83] => src_payload.IN1 -sink1_data[84] => src_payload.IN1 -sink1_data[85] => src_payload.IN1 -sink1_data[86] => src_payload.IN1 -sink1_data[87] => src_payload.IN1 -sink1_data[88] => src_payload.IN1 -sink1_data[89] => src_payload.IN1 -sink1_data[90] => src_payload.IN1 -sink1_data[91] => src_payload.IN1 -sink1_data[92] => src_payload.IN1 -sink1_data[93] => src_payload.IN1 -sink1_data[94] => src_payload.IN1 -sink1_data[95] => src_payload.IN1 -sink1_channel[0] => src_payload.IN1 -sink1_channel[1] => src_payload.IN1 -sink1_channel[2] => src_payload.IN1 -sink1_channel[3] => src_payload.IN1 -sink1_channel[4] => src_payload.IN1 -sink1_channel[5] => src_payload.IN1 -sink1_channel[6] => src_payload.IN1 -sink1_channel[7] => src_payload.IN1 -sink1_channel[8] => src_payload.IN1 -sink1_channel[9] => src_payload.IN1 -sink1_channel[10] => src_payload.IN1 -sink1_channel[11] => src_payload.IN1 -sink1_channel[12] => src_payload.IN1 -sink1_channel[13] => src_payload.IN1 -sink1_channel[14] => src_payload.IN1 -sink1_channel[15] => src_payload.IN1 -sink1_channel[16] => src_payload.IN1 -sink1_channel[17] => src_payload.IN1 -sink1_startofpacket => src_payload.IN1 -sink1_endofpacket => src_payload.IN1 -sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE -sink2_valid => request[2].IN1 -sink2_data[0] => src_payload.IN1 -sink2_data[1] => src_payload.IN1 -sink2_data[2] => src_payload.IN1 -sink2_data[3] => src_payload.IN1 -sink2_data[4] => src_payload.IN1 -sink2_data[5] => src_payload.IN1 -sink2_data[6] => src_payload.IN1 -sink2_data[7] => src_payload.IN1 -sink2_data[8] => src_payload.IN1 -sink2_data[9] => src_payload.IN1 -sink2_data[10] => src_payload.IN1 -sink2_data[11] => src_payload.IN1 -sink2_data[12] => src_payload.IN1 -sink2_data[13] => src_payload.IN1 -sink2_data[14] => src_payload.IN1 -sink2_data[15] => src_payload.IN1 -sink2_data[16] => src_payload.IN1 -sink2_data[17] => src_payload.IN1 -sink2_data[18] => src_payload.IN1 -sink2_data[19] => src_payload.IN1 -sink2_data[20] => src_payload.IN1 -sink2_data[21] => src_payload.IN1 -sink2_data[22] => src_payload.IN1 -sink2_data[23] => src_payload.IN1 -sink2_data[24] => src_payload.IN1 -sink2_data[25] => src_payload.IN1 -sink2_data[26] => src_payload.IN1 -sink2_data[27] => src_payload.IN1 -sink2_data[28] => src_payload.IN1 -sink2_data[29] => src_payload.IN1 -sink2_data[30] => src_payload.IN1 -sink2_data[31] => src_payload.IN1 -sink2_data[32] => src_payload.IN1 -sink2_data[33] => src_payload.IN1 -sink2_data[34] => src_payload.IN1 -sink2_data[35] => src_payload.IN1 -sink2_data[36] => src_payload.IN1 -sink2_data[37] => src_payload.IN1 -sink2_data[38] => src_payload.IN1 -sink2_data[39] => src_payload.IN1 -sink2_data[40] => src_payload.IN1 -sink2_data[41] => src_payload.IN1 -sink2_data[42] => src_payload.IN1 -sink2_data[43] => src_payload.IN1 -sink2_data[44] => src_payload.IN1 -sink2_data[45] => src_payload.IN1 -sink2_data[46] => src_payload.IN1 -sink2_data[47] => src_payload.IN1 -sink2_data[48] => src_payload.IN1 -sink2_data[49] => src_payload.IN1 -sink2_data[50] => src_payload.IN1 -sink2_data[51] => src_payload.IN1 -sink2_data[52] => src_payload.IN1 -sink2_data[53] => src_payload.IN1 -sink2_data[54] => src_payload.IN1 -sink2_data[55] => src_payload.IN1 -sink2_data[56] => src_payload.IN1 -sink2_data[57] => src_payload.IN1 -sink2_data[58] => src_payload.IN1 -sink2_data[59] => src_payload.IN1 -sink2_data[59] => last_cycle.IN1 -sink2_data[60] => src_payload.IN1 -sink2_data[61] => src_payload.IN1 -sink2_data[62] => src_payload.IN1 -sink2_data[63] => src_payload.IN1 -sink2_data[64] => src_payload.IN1 -sink2_data[65] => src_payload.IN1 -sink2_data[66] => src_payload.IN1 -sink2_data[67] => src_payload.IN1 -sink2_data[68] => src_payload.IN1 -sink2_data[69] => src_payload.IN1 -sink2_data[70] => src_payload.IN1 -sink2_data[71] => src_payload.IN1 -sink2_data[72] => src_payload.IN1 -sink2_data[73] => src_payload.IN1 -sink2_data[74] => src_payload.IN1 -sink2_data[75] => src_payload.IN1 -sink2_data[76] => src_payload.IN1 -sink2_data[77] => src_payload.IN1 -sink2_data[78] => src_payload.IN1 -sink2_data[79] => src_payload.IN1 -sink2_data[80] => src_payload.IN1 -sink2_data[81] => src_payload.IN1 -sink2_data[82] => src_payload.IN1 -sink2_data[83] => src_payload.IN1 -sink2_data[84] => src_payload.IN1 -sink2_data[85] => src_payload.IN1 -sink2_data[86] => src_payload.IN1 -sink2_data[87] => src_payload.IN1 -sink2_data[88] => src_payload.IN1 -sink2_data[89] => src_payload.IN1 -sink2_data[90] => src_payload.IN1 -sink2_data[91] => src_payload.IN1 -sink2_data[92] => src_payload.IN1 -sink2_data[93] => src_payload.IN1 -sink2_data[94] => src_payload.IN1 -sink2_data[95] => src_payload.IN1 -sink2_channel[0] => src_payload.IN1 -sink2_channel[1] => src_payload.IN1 -sink2_channel[2] => src_payload.IN1 -sink2_channel[3] => src_payload.IN1 -sink2_channel[4] => src_payload.IN1 -sink2_channel[5] => src_payload.IN1 -sink2_channel[6] => src_payload.IN1 -sink2_channel[7] => src_payload.IN1 -sink2_channel[8] => src_payload.IN1 -sink2_channel[9] => src_payload.IN1 -sink2_channel[10] => src_payload.IN1 -sink2_channel[11] => src_payload.IN1 -sink2_channel[12] => src_payload.IN1 -sink2_channel[13] => src_payload.IN1 -sink2_channel[14] => src_payload.IN1 -sink2_channel[15] => src_payload.IN1 -sink2_channel[16] => src_payload.IN1 -sink2_channel[17] => src_payload.IN1 -sink2_startofpacket => src_payload.IN1 -sink2_endofpacket => src_payload.IN1 -sink2_ready <= sink2_ready.DB_MAX_OUTPUT_PORT_TYPE -sink3_valid => request[3].IN1 -sink3_data[0] => src_payload.IN1 -sink3_data[1] => src_payload.IN1 -sink3_data[2] => src_payload.IN1 -sink3_data[3] => src_payload.IN1 -sink3_data[4] => src_payload.IN1 -sink3_data[5] => src_payload.IN1 -sink3_data[6] => src_payload.IN1 -sink3_data[7] => src_payload.IN1 -sink3_data[8] => src_payload.IN1 -sink3_data[9] => src_payload.IN1 -sink3_data[10] => src_payload.IN1 -sink3_data[11] => src_payload.IN1 -sink3_data[12] => src_payload.IN1 -sink3_data[13] => src_payload.IN1 -sink3_data[14] => src_payload.IN1 -sink3_data[15] => src_payload.IN1 -sink3_data[16] => src_payload.IN1 -sink3_data[17] => src_payload.IN1 -sink3_data[18] => src_payload.IN1 -sink3_data[19] => src_payload.IN1 -sink3_data[20] => src_payload.IN1 -sink3_data[21] => src_payload.IN1 -sink3_data[22] => src_payload.IN1 -sink3_data[23] => src_payload.IN1 -sink3_data[24] => src_payload.IN1 -sink3_data[25] => src_payload.IN1 -sink3_data[26] => src_payload.IN1 -sink3_data[27] => src_payload.IN1 -sink3_data[28] => src_payload.IN1 -sink3_data[29] => src_payload.IN1 -sink3_data[30] => src_payload.IN1 -sink3_data[31] => src_payload.IN1 -sink3_data[32] => src_payload.IN1 -sink3_data[33] => src_payload.IN1 -sink3_data[34] => src_payload.IN1 -sink3_data[35] => src_payload.IN1 -sink3_data[36] => src_payload.IN1 -sink3_data[37] => src_payload.IN1 -sink3_data[38] => src_payload.IN1 -sink3_data[39] => src_payload.IN1 -sink3_data[40] => src_payload.IN1 -sink3_data[41] => src_payload.IN1 -sink3_data[42] => src_payload.IN1 -sink3_data[43] => src_payload.IN1 -sink3_data[44] => src_payload.IN1 -sink3_data[45] => src_payload.IN1 -sink3_data[46] => src_payload.IN1 -sink3_data[47] => src_payload.IN1 -sink3_data[48] => src_payload.IN1 -sink3_data[49] => src_payload.IN1 -sink3_data[50] => src_payload.IN1 -sink3_data[51] => src_payload.IN1 -sink3_data[52] => src_payload.IN1 -sink3_data[53] => src_payload.IN1 -sink3_data[54] => src_payload.IN1 -sink3_data[55] => src_payload.IN1 -sink3_data[56] => src_payload.IN1 -sink3_data[57] => src_payload.IN1 -sink3_data[58] => src_payload.IN1 -sink3_data[59] => src_payload.IN1 -sink3_data[59] => last_cycle.IN1 -sink3_data[60] => src_payload.IN1 -sink3_data[61] => src_payload.IN1 -sink3_data[62] => src_payload.IN1 -sink3_data[63] => src_payload.IN1 -sink3_data[64] => src_payload.IN1 -sink3_data[65] => src_payload.IN1 -sink3_data[66] => src_payload.IN1 -sink3_data[67] => src_payload.IN1 -sink3_data[68] => src_payload.IN1 -sink3_data[69] => src_payload.IN1 -sink3_data[70] => src_payload.IN1 -sink3_data[71] => src_payload.IN1 -sink3_data[72] => src_payload.IN1 -sink3_data[73] => src_payload.IN1 -sink3_data[74] => src_payload.IN1 -sink3_data[75] => src_payload.IN1 -sink3_data[76] => src_payload.IN1 -sink3_data[77] => src_payload.IN1 -sink3_data[78] => src_payload.IN1 -sink3_data[79] => src_payload.IN1 -sink3_data[80] => src_payload.IN1 -sink3_data[81] => src_payload.IN1 -sink3_data[82] => src_payload.IN1 -sink3_data[83] => src_payload.IN1 -sink3_data[84] => src_payload.IN1 -sink3_data[85] => src_payload.IN1 -sink3_data[86] => src_payload.IN1 -sink3_data[87] => src_payload.IN1 -sink3_data[88] => src_payload.IN1 -sink3_data[89] => src_payload.IN1 -sink3_data[90] => src_payload.IN1 -sink3_data[91] => src_payload.IN1 -sink3_data[92] => src_payload.IN1 -sink3_data[93] => src_payload.IN1 -sink3_data[94] => src_payload.IN1 -sink3_data[95] => src_payload.IN1 -sink3_channel[0] => src_payload.IN1 -sink3_channel[1] => src_payload.IN1 -sink3_channel[2] => src_payload.IN1 -sink3_channel[3] => src_payload.IN1 -sink3_channel[4] => src_payload.IN1 -sink3_channel[5] => src_payload.IN1 -sink3_channel[6] => src_payload.IN1 -sink3_channel[7] => src_payload.IN1 -sink3_channel[8] => src_payload.IN1 -sink3_channel[9] => src_payload.IN1 -sink3_channel[10] => src_payload.IN1 -sink3_channel[11] => src_payload.IN1 -sink3_channel[12] => src_payload.IN1 -sink3_channel[13] => src_payload.IN1 -sink3_channel[14] => src_payload.IN1 -sink3_channel[15] => src_payload.IN1 -sink3_channel[16] => src_payload.IN1 -sink3_channel[17] => src_payload.IN1 -sink3_startofpacket => src_payload.IN1 -sink3_endofpacket => src_payload.IN1 -sink3_ready <= sink3_ready.DB_MAX_OUTPUT_PORT_TYPE -sink4_valid => request[4].IN1 -sink4_data[0] => src_payload.IN1 -sink4_data[1] => src_payload.IN1 -sink4_data[2] => src_payload.IN1 -sink4_data[3] => src_payload.IN1 -sink4_data[4] => src_payload.IN1 -sink4_data[5] => src_payload.IN1 -sink4_data[6] => src_payload.IN1 -sink4_data[7] => src_payload.IN1 -sink4_data[8] => src_payload.IN1 -sink4_data[9] => src_payload.IN1 -sink4_data[10] => src_payload.IN1 -sink4_data[11] => src_payload.IN1 -sink4_data[12] => src_payload.IN1 -sink4_data[13] => src_payload.IN1 -sink4_data[14] => src_payload.IN1 -sink4_data[15] => src_payload.IN1 -sink4_data[16] => src_payload.IN1 -sink4_data[17] => src_payload.IN1 -sink4_data[18] => src_payload.IN1 -sink4_data[19] => src_payload.IN1 -sink4_data[20] => src_payload.IN1 -sink4_data[21] => src_payload.IN1 -sink4_data[22] => src_payload.IN1 -sink4_data[23] => src_payload.IN1 -sink4_data[24] => src_payload.IN1 -sink4_data[25] => src_payload.IN1 -sink4_data[26] => src_payload.IN1 -sink4_data[27] => src_payload.IN1 -sink4_data[28] => src_payload.IN1 -sink4_data[29] => src_payload.IN1 -sink4_data[30] => src_payload.IN1 -sink4_data[31] => src_payload.IN1 -sink4_data[32] => src_payload.IN1 -sink4_data[33] => src_payload.IN1 -sink4_data[34] => src_payload.IN1 -sink4_data[35] => src_payload.IN1 -sink4_data[36] => src_payload.IN1 -sink4_data[37] => src_payload.IN1 -sink4_data[38] => src_payload.IN1 -sink4_data[39] => src_payload.IN1 -sink4_data[40] => src_payload.IN1 -sink4_data[41] => src_payload.IN1 -sink4_data[42] => src_payload.IN1 -sink4_data[43] => src_payload.IN1 -sink4_data[44] => src_payload.IN1 -sink4_data[45] => src_payload.IN1 -sink4_data[46] => src_payload.IN1 -sink4_data[47] => src_payload.IN1 -sink4_data[48] => src_payload.IN1 -sink4_data[49] => src_payload.IN1 -sink4_data[50] => src_payload.IN1 -sink4_data[51] => src_payload.IN1 -sink4_data[52] => src_payload.IN1 -sink4_data[53] => src_payload.IN1 -sink4_data[54] => src_payload.IN1 -sink4_data[55] => src_payload.IN1 -sink4_data[56] => src_payload.IN1 -sink4_data[57] => src_payload.IN1 -sink4_data[58] => src_payload.IN1 -sink4_data[59] => src_payload.IN1 -sink4_data[59] => last_cycle.IN1 -sink4_data[60] => src_payload.IN1 -sink4_data[61] => src_payload.IN1 -sink4_data[62] => src_payload.IN1 -sink4_data[63] => src_payload.IN1 -sink4_data[64] => src_payload.IN1 -sink4_data[65] => src_payload.IN1 -sink4_data[66] => src_payload.IN1 -sink4_data[67] => src_payload.IN1 -sink4_data[68] => src_payload.IN1 -sink4_data[69] => src_payload.IN1 -sink4_data[70] => src_payload.IN1 -sink4_data[71] => src_payload.IN1 -sink4_data[72] => src_payload.IN1 -sink4_data[73] => src_payload.IN1 -sink4_data[74] => src_payload.IN1 -sink4_data[75] => src_payload.IN1 -sink4_data[76] => src_payload.IN1 -sink4_data[77] => src_payload.IN1 -sink4_data[78] => src_payload.IN1 -sink4_data[79] => src_payload.IN1 -sink4_data[80] => src_payload.IN1 -sink4_data[81] => src_payload.IN1 -sink4_data[82] => src_payload.IN1 -sink4_data[83] => src_payload.IN1 -sink4_data[84] => src_payload.IN1 -sink4_data[85] => src_payload.IN1 -sink4_data[86] => src_payload.IN1 -sink4_data[87] => src_payload.IN1 -sink4_data[88] => src_payload.IN1 -sink4_data[89] => src_payload.IN1 -sink4_data[90] => src_payload.IN1 -sink4_data[91] => src_payload.IN1 -sink4_data[92] => src_payload.IN1 -sink4_data[93] => src_payload.IN1 -sink4_data[94] => src_payload.IN1 -sink4_data[95] => src_payload.IN1 -sink4_channel[0] => src_payload.IN1 -sink4_channel[1] => src_payload.IN1 -sink4_channel[2] => src_payload.IN1 -sink4_channel[3] => src_payload.IN1 -sink4_channel[4] => src_payload.IN1 -sink4_channel[5] => src_payload.IN1 -sink4_channel[6] => src_payload.IN1 -sink4_channel[7] => src_payload.IN1 -sink4_channel[8] => src_payload.IN1 -sink4_channel[9] => src_payload.IN1 -sink4_channel[10] => src_payload.IN1 -sink4_channel[11] => src_payload.IN1 -sink4_channel[12] => src_payload.IN1 -sink4_channel[13] => src_payload.IN1 -sink4_channel[14] => src_payload.IN1 -sink4_channel[15] => src_payload.IN1 -sink4_channel[16] => src_payload.IN1 -sink4_channel[17] => src_payload.IN1 -sink4_startofpacket => src_payload.IN1 -sink4_endofpacket => src_payload.IN1 -sink4_ready <= sink4_ready.DB_MAX_OUTPUT_PORT_TYPE -sink5_valid => request[5].IN1 -sink5_data[0] => src_payload.IN1 -sink5_data[1] => src_payload.IN1 -sink5_data[2] => src_payload.IN1 -sink5_data[3] => src_payload.IN1 -sink5_data[4] => src_payload.IN1 -sink5_data[5] => src_payload.IN1 -sink5_data[6] => src_payload.IN1 -sink5_data[7] => src_payload.IN1 -sink5_data[8] => src_payload.IN1 -sink5_data[9] => src_payload.IN1 -sink5_data[10] => src_payload.IN1 -sink5_data[11] => src_payload.IN1 -sink5_data[12] => src_payload.IN1 -sink5_data[13] => src_payload.IN1 -sink5_data[14] => src_payload.IN1 -sink5_data[15] => src_payload.IN1 -sink5_data[16] => src_payload.IN1 -sink5_data[17] => src_payload.IN1 -sink5_data[18] => src_payload.IN1 -sink5_data[19] => src_payload.IN1 -sink5_data[20] => src_payload.IN1 -sink5_data[21] => src_payload.IN1 -sink5_data[22] => src_payload.IN1 -sink5_data[23] => src_payload.IN1 -sink5_data[24] => src_payload.IN1 -sink5_data[25] => src_payload.IN1 -sink5_data[26] => src_payload.IN1 -sink5_data[27] => src_payload.IN1 -sink5_data[28] => src_payload.IN1 -sink5_data[29] => src_payload.IN1 -sink5_data[30] => src_payload.IN1 -sink5_data[31] => src_payload.IN1 -sink5_data[32] => src_payload.IN1 -sink5_data[33] => src_payload.IN1 -sink5_data[34] => src_payload.IN1 -sink5_data[35] => src_payload.IN1 -sink5_data[36] => src_payload.IN1 -sink5_data[37] => src_payload.IN1 -sink5_data[38] => src_payload.IN1 -sink5_data[39] => src_payload.IN1 -sink5_data[40] => src_payload.IN1 -sink5_data[41] => src_payload.IN1 -sink5_data[42] => src_payload.IN1 -sink5_data[43] => src_payload.IN1 -sink5_data[44] => src_payload.IN1 -sink5_data[45] => src_payload.IN1 -sink5_data[46] => src_payload.IN1 -sink5_data[47] => src_payload.IN1 -sink5_data[48] => src_payload.IN1 -sink5_data[49] => src_payload.IN1 -sink5_data[50] => src_payload.IN1 -sink5_data[51] => src_payload.IN1 -sink5_data[52] => src_payload.IN1 -sink5_data[53] => src_payload.IN1 -sink5_data[54] => src_payload.IN1 -sink5_data[55] => src_payload.IN1 -sink5_data[56] => src_payload.IN1 -sink5_data[57] => src_payload.IN1 -sink5_data[58] => src_payload.IN1 -sink5_data[59] => src_payload.IN1 -sink5_data[59] => last_cycle.IN1 -sink5_data[60] => src_payload.IN1 -sink5_data[61] => src_payload.IN1 -sink5_data[62] => src_payload.IN1 -sink5_data[63] => src_payload.IN1 -sink5_data[64] => src_payload.IN1 -sink5_data[65] => src_payload.IN1 -sink5_data[66] => src_payload.IN1 -sink5_data[67] => src_payload.IN1 -sink5_data[68] => src_payload.IN1 -sink5_data[69] => src_payload.IN1 -sink5_data[70] => src_payload.IN1 -sink5_data[71] => src_payload.IN1 -sink5_data[72] => src_payload.IN1 -sink5_data[73] => src_payload.IN1 -sink5_data[74] => src_payload.IN1 -sink5_data[75] => src_payload.IN1 -sink5_data[76] => src_payload.IN1 -sink5_data[77] => src_payload.IN1 -sink5_data[78] => src_payload.IN1 -sink5_data[79] => src_payload.IN1 -sink5_data[80] => src_payload.IN1 -sink5_data[81] => src_payload.IN1 -sink5_data[82] => src_payload.IN1 -sink5_data[83] => src_payload.IN1 -sink5_data[84] => src_payload.IN1 -sink5_data[85] => src_payload.IN1 -sink5_data[86] => src_payload.IN1 -sink5_data[87] => src_payload.IN1 -sink5_data[88] => src_payload.IN1 -sink5_data[89] => src_payload.IN1 -sink5_data[90] => src_payload.IN1 -sink5_data[91] => src_payload.IN1 -sink5_data[92] => src_payload.IN1 -sink5_data[93] => src_payload.IN1 -sink5_data[94] => src_payload.IN1 -sink5_data[95] => src_payload.IN1 -sink5_channel[0] => src_payload.IN1 -sink5_channel[1] => src_payload.IN1 -sink5_channel[2] => src_payload.IN1 -sink5_channel[3] => src_payload.IN1 -sink5_channel[4] => src_payload.IN1 -sink5_channel[5] => src_payload.IN1 -sink5_channel[6] => src_payload.IN1 -sink5_channel[7] => src_payload.IN1 -sink5_channel[8] => src_payload.IN1 -sink5_channel[9] => src_payload.IN1 -sink5_channel[10] => src_payload.IN1 -sink5_channel[11] => src_payload.IN1 -sink5_channel[12] => src_payload.IN1 -sink5_channel[13] => src_payload.IN1 -sink5_channel[14] => src_payload.IN1 -sink5_channel[15] => src_payload.IN1 -sink5_channel[16] => src_payload.IN1 -sink5_channel[17] => src_payload.IN1 -sink5_startofpacket => src_payload.IN1 -sink5_endofpacket => src_payload.IN1 -sink5_ready <= sink5_ready.DB_MAX_OUTPUT_PORT_TYPE -sink6_valid => request[6].IN1 -sink6_data[0] => src_payload.IN1 -sink6_data[1] => src_payload.IN1 -sink6_data[2] => src_payload.IN1 -sink6_data[3] => src_payload.IN1 -sink6_data[4] => src_payload.IN1 -sink6_data[5] => src_payload.IN1 -sink6_data[6] => src_payload.IN1 -sink6_data[7] => src_payload.IN1 -sink6_data[8] => src_payload.IN1 -sink6_data[9] => src_payload.IN1 -sink6_data[10] => src_payload.IN1 -sink6_data[11] => src_payload.IN1 -sink6_data[12] => src_payload.IN1 -sink6_data[13] => src_payload.IN1 -sink6_data[14] => src_payload.IN1 -sink6_data[15] => src_payload.IN1 -sink6_data[16] => src_payload.IN1 -sink6_data[17] => src_payload.IN1 -sink6_data[18] => src_payload.IN1 -sink6_data[19] => src_payload.IN1 -sink6_data[20] => src_payload.IN1 -sink6_data[21] => src_payload.IN1 -sink6_data[22] => src_payload.IN1 -sink6_data[23] => src_payload.IN1 -sink6_data[24] => src_payload.IN1 -sink6_data[25] => src_payload.IN1 -sink6_data[26] => src_payload.IN1 -sink6_data[27] => src_payload.IN1 -sink6_data[28] => src_payload.IN1 -sink6_data[29] => src_payload.IN1 -sink6_data[30] => src_payload.IN1 -sink6_data[31] => src_payload.IN1 -sink6_data[32] => src_payload.IN1 -sink6_data[33] => src_payload.IN1 -sink6_data[34] => src_payload.IN1 -sink6_data[35] => src_payload.IN1 -sink6_data[36] => src_payload.IN1 -sink6_data[37] => src_payload.IN1 -sink6_data[38] => src_payload.IN1 -sink6_data[39] => src_payload.IN1 -sink6_data[40] => src_payload.IN1 -sink6_data[41] => src_payload.IN1 -sink6_data[42] => src_payload.IN1 -sink6_data[43] => src_payload.IN1 -sink6_data[44] => src_payload.IN1 -sink6_data[45] => src_payload.IN1 -sink6_data[46] => src_payload.IN1 -sink6_data[47] => src_payload.IN1 -sink6_data[48] => src_payload.IN1 -sink6_data[49] => src_payload.IN1 -sink6_data[50] => src_payload.IN1 -sink6_data[51] => src_payload.IN1 -sink6_data[52] => src_payload.IN1 -sink6_data[53] => src_payload.IN1 -sink6_data[54] => src_payload.IN1 -sink6_data[55] => src_payload.IN1 -sink6_data[56] => src_payload.IN1 -sink6_data[57] => src_payload.IN1 -sink6_data[58] => src_payload.IN1 -sink6_data[59] => src_payload.IN1 -sink6_data[59] => last_cycle.IN1 -sink6_data[60] => src_payload.IN1 -sink6_data[61] => src_payload.IN1 -sink6_data[62] => src_payload.IN1 -sink6_data[63] => src_payload.IN1 -sink6_data[64] => src_payload.IN1 -sink6_data[65] => src_payload.IN1 -sink6_data[66] => src_payload.IN1 -sink6_data[67] => src_payload.IN1 -sink6_data[68] => src_payload.IN1 -sink6_data[69] => src_payload.IN1 -sink6_data[70] => src_payload.IN1 -sink6_data[71] => src_payload.IN1 -sink6_data[72] => src_payload.IN1 -sink6_data[73] => src_payload.IN1 -sink6_data[74] => src_payload.IN1 -sink6_data[75] => src_payload.IN1 -sink6_data[76] => src_payload.IN1 -sink6_data[77] => src_payload.IN1 -sink6_data[78] => src_payload.IN1 -sink6_data[79] => src_payload.IN1 -sink6_data[80] => src_payload.IN1 -sink6_data[81] => src_payload.IN1 -sink6_data[82] => src_payload.IN1 -sink6_data[83] => src_payload.IN1 -sink6_data[84] => src_payload.IN1 -sink6_data[85] => src_payload.IN1 -sink6_data[86] => src_payload.IN1 -sink6_data[87] => src_payload.IN1 -sink6_data[88] => src_payload.IN1 -sink6_data[89] => src_payload.IN1 -sink6_data[90] => src_payload.IN1 -sink6_data[91] => src_payload.IN1 -sink6_data[92] => src_payload.IN1 -sink6_data[93] => src_payload.IN1 -sink6_data[94] => src_payload.IN1 -sink6_data[95] => src_payload.IN1 -sink6_channel[0] => src_payload.IN1 -sink6_channel[1] => src_payload.IN1 -sink6_channel[2] => src_payload.IN1 -sink6_channel[3] => src_payload.IN1 -sink6_channel[4] => src_payload.IN1 -sink6_channel[5] => src_payload.IN1 -sink6_channel[6] => src_payload.IN1 -sink6_channel[7] => src_payload.IN1 -sink6_channel[8] => src_payload.IN1 -sink6_channel[9] => src_payload.IN1 -sink6_channel[10] => src_payload.IN1 -sink6_channel[11] => src_payload.IN1 -sink6_channel[12] => src_payload.IN1 -sink6_channel[13] => src_payload.IN1 -sink6_channel[14] => src_payload.IN1 -sink6_channel[15] => src_payload.IN1 -sink6_channel[16] => src_payload.IN1 -sink6_channel[17] => src_payload.IN1 -sink6_startofpacket => src_payload.IN1 -sink6_endofpacket => src_payload.IN1 -sink6_ready <= sink6_ready.DB_MAX_OUTPUT_PORT_TYPE -sink7_valid => request[7].IN1 -sink7_data[0] => src_payload.IN1 -sink7_data[1] => src_payload.IN1 -sink7_data[2] => src_payload.IN1 -sink7_data[3] => src_payload.IN1 -sink7_data[4] => src_payload.IN1 -sink7_data[5] => src_payload.IN1 -sink7_data[6] => src_payload.IN1 -sink7_data[7] => src_payload.IN1 -sink7_data[8] => src_payload.IN1 -sink7_data[9] => src_payload.IN1 -sink7_data[10] => src_payload.IN1 -sink7_data[11] => src_payload.IN1 -sink7_data[12] => src_payload.IN1 -sink7_data[13] => src_payload.IN1 -sink7_data[14] => src_payload.IN1 -sink7_data[15] => src_payload.IN1 -sink7_data[16] => src_payload.IN1 -sink7_data[17] => src_payload.IN1 -sink7_data[18] => src_payload.IN1 -sink7_data[19] => src_payload.IN1 -sink7_data[20] => src_payload.IN1 -sink7_data[21] => src_payload.IN1 -sink7_data[22] => src_payload.IN1 -sink7_data[23] => src_payload.IN1 -sink7_data[24] => src_payload.IN1 -sink7_data[25] => src_payload.IN1 -sink7_data[26] => src_payload.IN1 -sink7_data[27] => src_payload.IN1 -sink7_data[28] => src_payload.IN1 -sink7_data[29] => src_payload.IN1 -sink7_data[30] => src_payload.IN1 -sink7_data[31] => src_payload.IN1 -sink7_data[32] => src_payload.IN1 -sink7_data[33] => src_payload.IN1 -sink7_data[34] => src_payload.IN1 -sink7_data[35] => src_payload.IN1 -sink7_data[36] => src_payload.IN1 -sink7_data[37] => src_payload.IN1 -sink7_data[38] => src_payload.IN1 -sink7_data[39] => src_payload.IN1 -sink7_data[40] => src_payload.IN1 -sink7_data[41] => src_payload.IN1 -sink7_data[42] => src_payload.IN1 -sink7_data[43] => src_payload.IN1 -sink7_data[44] => src_payload.IN1 -sink7_data[45] => src_payload.IN1 -sink7_data[46] => src_payload.IN1 -sink7_data[47] => src_payload.IN1 -sink7_data[48] => src_payload.IN1 -sink7_data[49] => src_payload.IN1 -sink7_data[50] => src_payload.IN1 -sink7_data[51] => src_payload.IN1 -sink7_data[52] => src_payload.IN1 -sink7_data[53] => src_payload.IN1 -sink7_data[54] => src_payload.IN1 -sink7_data[55] => src_payload.IN1 -sink7_data[56] => src_payload.IN1 -sink7_data[57] => src_payload.IN1 -sink7_data[58] => src_payload.IN1 -sink7_data[59] => src_payload.IN1 -sink7_data[59] => last_cycle.IN1 -sink7_data[60] => src_payload.IN1 -sink7_data[61] => src_payload.IN1 -sink7_data[62] => src_payload.IN1 -sink7_data[63] => src_payload.IN1 -sink7_data[64] => src_payload.IN1 -sink7_data[65] => src_payload.IN1 -sink7_data[66] => src_payload.IN1 -sink7_data[67] => src_payload.IN1 -sink7_data[68] => src_payload.IN1 -sink7_data[69] => src_payload.IN1 -sink7_data[70] => src_payload.IN1 -sink7_data[71] => src_payload.IN1 -sink7_data[72] => src_payload.IN1 -sink7_data[73] => src_payload.IN1 -sink7_data[74] => src_payload.IN1 -sink7_data[75] => src_payload.IN1 -sink7_data[76] => src_payload.IN1 -sink7_data[77] => src_payload.IN1 -sink7_data[78] => src_payload.IN1 -sink7_data[79] => src_payload.IN1 -sink7_data[80] => src_payload.IN1 -sink7_data[81] => src_payload.IN1 -sink7_data[82] => src_payload.IN1 -sink7_data[83] => src_payload.IN1 -sink7_data[84] => src_payload.IN1 -sink7_data[85] => src_payload.IN1 -sink7_data[86] => src_payload.IN1 -sink7_data[87] => src_payload.IN1 -sink7_data[88] => src_payload.IN1 -sink7_data[89] => src_payload.IN1 -sink7_data[90] => src_payload.IN1 -sink7_data[91] => src_payload.IN1 -sink7_data[92] => src_payload.IN1 -sink7_data[93] => src_payload.IN1 -sink7_data[94] => src_payload.IN1 -sink7_data[95] => src_payload.IN1 -sink7_channel[0] => src_payload.IN1 -sink7_channel[1] => src_payload.IN1 -sink7_channel[2] => src_payload.IN1 -sink7_channel[3] => src_payload.IN1 -sink7_channel[4] => src_payload.IN1 -sink7_channel[5] => src_payload.IN1 -sink7_channel[6] => src_payload.IN1 -sink7_channel[7] => src_payload.IN1 -sink7_channel[8] => src_payload.IN1 -sink7_channel[9] => src_payload.IN1 -sink7_channel[10] => src_payload.IN1 -sink7_channel[11] => src_payload.IN1 -sink7_channel[12] => src_payload.IN1 -sink7_channel[13] => src_payload.IN1 -sink7_channel[14] => src_payload.IN1 -sink7_channel[15] => src_payload.IN1 -sink7_channel[16] => src_payload.IN1 -sink7_channel[17] => src_payload.IN1 -sink7_startofpacket => src_payload.IN1 -sink7_endofpacket => src_payload.IN1 -sink7_ready <= sink7_ready.DB_MAX_OUTPUT_PORT_TYPE -sink8_valid => request[8].IN1 -sink8_data[0] => src_payload.IN1 -sink8_data[1] => src_payload.IN1 -sink8_data[2] => src_payload.IN1 -sink8_data[3] => src_payload.IN1 -sink8_data[4] => src_payload.IN1 -sink8_data[5] => src_payload.IN1 -sink8_data[6] => src_payload.IN1 -sink8_data[7] => src_payload.IN1 -sink8_data[8] => src_payload.IN1 -sink8_data[9] => src_payload.IN1 -sink8_data[10] => src_payload.IN1 -sink8_data[11] => src_payload.IN1 -sink8_data[12] => src_payload.IN1 -sink8_data[13] => src_payload.IN1 -sink8_data[14] => src_payload.IN1 -sink8_data[15] => src_payload.IN1 -sink8_data[16] => src_payload.IN1 -sink8_data[17] => src_payload.IN1 -sink8_data[18] => src_payload.IN1 -sink8_data[19] => src_payload.IN1 -sink8_data[20] => src_payload.IN1 -sink8_data[21] => src_payload.IN1 -sink8_data[22] => src_payload.IN1 -sink8_data[23] => src_payload.IN1 -sink8_data[24] => src_payload.IN1 -sink8_data[25] => src_payload.IN1 -sink8_data[26] => src_payload.IN1 -sink8_data[27] => src_payload.IN1 -sink8_data[28] => src_payload.IN1 -sink8_data[29] => src_payload.IN1 -sink8_data[30] => src_payload.IN1 -sink8_data[31] => src_payload.IN1 -sink8_data[32] => src_payload.IN1 -sink8_data[33] => src_payload.IN1 -sink8_data[34] => src_payload.IN1 -sink8_data[35] => src_payload.IN1 -sink8_data[36] => src_payload.IN1 -sink8_data[37] => src_payload.IN1 -sink8_data[38] => src_payload.IN1 -sink8_data[39] => src_payload.IN1 -sink8_data[40] => src_payload.IN1 -sink8_data[41] => src_payload.IN1 -sink8_data[42] => src_payload.IN1 -sink8_data[43] => src_payload.IN1 -sink8_data[44] => src_payload.IN1 -sink8_data[45] => src_payload.IN1 -sink8_data[46] => src_payload.IN1 -sink8_data[47] => src_payload.IN1 -sink8_data[48] => src_payload.IN1 -sink8_data[49] => src_payload.IN1 -sink8_data[50] => src_payload.IN1 -sink8_data[51] => src_payload.IN1 -sink8_data[52] => src_payload.IN1 -sink8_data[53] => src_payload.IN1 -sink8_data[54] => src_payload.IN1 -sink8_data[55] => src_payload.IN1 -sink8_data[56] => src_payload.IN1 -sink8_data[57] => src_payload.IN1 -sink8_data[58] => src_payload.IN1 -sink8_data[59] => src_payload.IN1 -sink8_data[59] => last_cycle.IN1 -sink8_data[60] => src_payload.IN1 -sink8_data[61] => src_payload.IN1 -sink8_data[62] => src_payload.IN1 -sink8_data[63] => src_payload.IN1 -sink8_data[64] => src_payload.IN1 -sink8_data[65] => src_payload.IN1 -sink8_data[66] => src_payload.IN1 -sink8_data[67] => src_payload.IN1 -sink8_data[68] => src_payload.IN1 -sink8_data[69] => src_payload.IN1 -sink8_data[70] => src_payload.IN1 -sink8_data[71] => src_payload.IN1 -sink8_data[72] => src_payload.IN1 -sink8_data[73] => src_payload.IN1 -sink8_data[74] => src_payload.IN1 -sink8_data[75] => src_payload.IN1 -sink8_data[76] => src_payload.IN1 -sink8_data[77] => src_payload.IN1 -sink8_data[78] => src_payload.IN1 -sink8_data[79] => src_payload.IN1 -sink8_data[80] => src_payload.IN1 -sink8_data[81] => src_payload.IN1 -sink8_data[82] => src_payload.IN1 -sink8_data[83] => src_payload.IN1 -sink8_data[84] => src_payload.IN1 -sink8_data[85] => src_payload.IN1 -sink8_data[86] => src_payload.IN1 -sink8_data[87] => src_payload.IN1 -sink8_data[88] => src_payload.IN1 -sink8_data[89] => src_payload.IN1 -sink8_data[90] => src_payload.IN1 -sink8_data[91] => src_payload.IN1 -sink8_data[92] => src_payload.IN1 -sink8_data[93] => src_payload.IN1 -sink8_data[94] => src_payload.IN1 -sink8_data[95] => src_payload.IN1 -sink8_channel[0] => src_payload.IN1 -sink8_channel[1] => src_payload.IN1 -sink8_channel[2] => src_payload.IN1 -sink8_channel[3] => src_payload.IN1 -sink8_channel[4] => src_payload.IN1 -sink8_channel[5] => src_payload.IN1 -sink8_channel[6] => src_payload.IN1 -sink8_channel[7] => src_payload.IN1 -sink8_channel[8] => src_payload.IN1 -sink8_channel[9] => src_payload.IN1 -sink8_channel[10] => src_payload.IN1 -sink8_channel[11] => src_payload.IN1 -sink8_channel[12] => src_payload.IN1 -sink8_channel[13] => src_payload.IN1 -sink8_channel[14] => src_payload.IN1 -sink8_channel[15] => src_payload.IN1 -sink8_channel[16] => src_payload.IN1 -sink8_channel[17] => src_payload.IN1 -sink8_startofpacket => src_payload.IN1 -sink8_endofpacket => src_payload.IN1 -sink8_ready <= sink8_ready.DB_MAX_OUTPUT_PORT_TYPE -sink9_valid => request[9].IN1 -sink9_data[0] => src_payload.IN1 -sink9_data[1] => src_payload.IN1 -sink9_data[2] => src_payload.IN1 -sink9_data[3] => src_payload.IN1 -sink9_data[4] => src_payload.IN1 -sink9_data[5] => src_payload.IN1 -sink9_data[6] => src_payload.IN1 -sink9_data[7] => src_payload.IN1 -sink9_data[8] => src_payload.IN1 -sink9_data[9] => src_payload.IN1 -sink9_data[10] => src_payload.IN1 -sink9_data[11] => src_payload.IN1 -sink9_data[12] => src_payload.IN1 -sink9_data[13] => src_payload.IN1 -sink9_data[14] => src_payload.IN1 -sink9_data[15] => src_payload.IN1 -sink9_data[16] => src_payload.IN1 -sink9_data[17] => src_payload.IN1 -sink9_data[18] => src_payload.IN1 -sink9_data[19] => src_payload.IN1 -sink9_data[20] => src_payload.IN1 -sink9_data[21] => src_payload.IN1 -sink9_data[22] => src_payload.IN1 -sink9_data[23] => src_payload.IN1 -sink9_data[24] => src_payload.IN1 -sink9_data[25] => src_payload.IN1 -sink9_data[26] => src_payload.IN1 -sink9_data[27] => src_payload.IN1 -sink9_data[28] => src_payload.IN1 -sink9_data[29] => src_payload.IN1 -sink9_data[30] => src_payload.IN1 -sink9_data[31] => src_payload.IN1 -sink9_data[32] => src_payload.IN1 -sink9_data[33] => src_payload.IN1 -sink9_data[34] => src_payload.IN1 -sink9_data[35] => src_payload.IN1 -sink9_data[36] => src_payload.IN1 -sink9_data[37] => src_payload.IN1 -sink9_data[38] => src_payload.IN1 -sink9_data[39] => src_payload.IN1 -sink9_data[40] => src_payload.IN1 -sink9_data[41] => src_payload.IN1 -sink9_data[42] => src_payload.IN1 -sink9_data[43] => src_payload.IN1 -sink9_data[44] => src_payload.IN1 -sink9_data[45] => src_payload.IN1 -sink9_data[46] => src_payload.IN1 -sink9_data[47] => src_payload.IN1 -sink9_data[48] => src_payload.IN1 -sink9_data[49] => src_payload.IN1 -sink9_data[50] => src_payload.IN1 -sink9_data[51] => src_payload.IN1 -sink9_data[52] => src_payload.IN1 -sink9_data[53] => src_payload.IN1 -sink9_data[54] => src_payload.IN1 -sink9_data[55] => src_payload.IN1 -sink9_data[56] => src_payload.IN1 -sink9_data[57] => src_payload.IN1 -sink9_data[58] => src_payload.IN1 -sink9_data[59] => src_payload.IN1 -sink9_data[59] => last_cycle.IN1 -sink9_data[60] => src_payload.IN1 -sink9_data[61] => src_payload.IN1 -sink9_data[62] => src_payload.IN1 -sink9_data[63] => src_payload.IN1 -sink9_data[64] => src_payload.IN1 -sink9_data[65] => src_payload.IN1 -sink9_data[66] => src_payload.IN1 -sink9_data[67] => src_payload.IN1 -sink9_data[68] => src_payload.IN1 -sink9_data[69] => src_payload.IN1 -sink9_data[70] => src_payload.IN1 -sink9_data[71] => src_payload.IN1 -sink9_data[72] => src_payload.IN1 -sink9_data[73] => src_payload.IN1 -sink9_data[74] => src_payload.IN1 -sink9_data[75] => src_payload.IN1 -sink9_data[76] => src_payload.IN1 -sink9_data[77] => src_payload.IN1 -sink9_data[78] => src_payload.IN1 -sink9_data[79] => src_payload.IN1 -sink9_data[80] => src_payload.IN1 -sink9_data[81] => src_payload.IN1 -sink9_data[82] => src_payload.IN1 -sink9_data[83] => src_payload.IN1 -sink9_data[84] => src_payload.IN1 -sink9_data[85] => src_payload.IN1 -sink9_data[86] => src_payload.IN1 -sink9_data[87] => src_payload.IN1 -sink9_data[88] => src_payload.IN1 -sink9_data[89] => src_payload.IN1 -sink9_data[90] => src_payload.IN1 -sink9_data[91] => src_payload.IN1 -sink9_data[92] => src_payload.IN1 -sink9_data[93] => src_payload.IN1 -sink9_data[94] => src_payload.IN1 -sink9_data[95] => src_payload.IN1 -sink9_channel[0] => src_payload.IN1 -sink9_channel[1] => src_payload.IN1 -sink9_channel[2] => src_payload.IN1 -sink9_channel[3] => src_payload.IN1 -sink9_channel[4] => src_payload.IN1 -sink9_channel[5] => src_payload.IN1 -sink9_channel[6] => src_payload.IN1 -sink9_channel[7] => src_payload.IN1 -sink9_channel[8] => src_payload.IN1 -sink9_channel[9] => src_payload.IN1 -sink9_channel[10] => src_payload.IN1 -sink9_channel[11] => src_payload.IN1 -sink9_channel[12] => src_payload.IN1 -sink9_channel[13] => src_payload.IN1 -sink9_channel[14] => src_payload.IN1 -sink9_channel[15] => src_payload.IN1 -sink9_channel[16] => src_payload.IN1 -sink9_channel[17] => src_payload.IN1 -sink9_startofpacket => src_payload.IN1 -sink9_endofpacket => src_payload.IN1 -sink9_ready <= sink9_ready.DB_MAX_OUTPUT_PORT_TYPE -sink10_valid => request[10].IN1 -sink10_data[0] => src_payload.IN1 -sink10_data[1] => src_payload.IN1 -sink10_data[2] => src_payload.IN1 -sink10_data[3] => src_payload.IN1 -sink10_data[4] => src_payload.IN1 -sink10_data[5] => src_payload.IN1 -sink10_data[6] => src_payload.IN1 -sink10_data[7] => src_payload.IN1 -sink10_data[8] => src_payload.IN1 -sink10_data[9] => src_payload.IN1 -sink10_data[10] => src_payload.IN1 -sink10_data[11] => src_payload.IN1 -sink10_data[12] => src_payload.IN1 -sink10_data[13] => src_payload.IN1 -sink10_data[14] => src_payload.IN1 -sink10_data[15] => src_payload.IN1 -sink10_data[16] => src_payload.IN1 -sink10_data[17] => src_payload.IN1 -sink10_data[18] => src_payload.IN1 -sink10_data[19] => src_payload.IN1 -sink10_data[20] => src_payload.IN1 -sink10_data[21] => src_payload.IN1 -sink10_data[22] => src_payload.IN1 -sink10_data[23] => src_payload.IN1 -sink10_data[24] => src_payload.IN1 -sink10_data[25] => src_payload.IN1 -sink10_data[26] => src_payload.IN1 -sink10_data[27] => src_payload.IN1 -sink10_data[28] => src_payload.IN1 -sink10_data[29] => src_payload.IN1 -sink10_data[30] => src_payload.IN1 -sink10_data[31] => src_payload.IN1 -sink10_data[32] => src_payload.IN1 -sink10_data[33] => src_payload.IN1 -sink10_data[34] => src_payload.IN1 -sink10_data[35] => src_payload.IN1 -sink10_data[36] => src_payload.IN1 -sink10_data[37] => src_payload.IN1 -sink10_data[38] => src_payload.IN1 -sink10_data[39] => src_payload.IN1 -sink10_data[40] => src_payload.IN1 -sink10_data[41] => src_payload.IN1 -sink10_data[42] => src_payload.IN1 -sink10_data[43] => src_payload.IN1 -sink10_data[44] => src_payload.IN1 -sink10_data[45] => src_payload.IN1 -sink10_data[46] => src_payload.IN1 -sink10_data[47] => src_payload.IN1 -sink10_data[48] => src_payload.IN1 -sink10_data[49] => src_payload.IN1 -sink10_data[50] => src_payload.IN1 -sink10_data[51] => src_payload.IN1 -sink10_data[52] => src_payload.IN1 -sink10_data[53] => src_payload.IN1 -sink10_data[54] => src_payload.IN1 -sink10_data[55] => src_payload.IN1 -sink10_data[56] => src_payload.IN1 -sink10_data[57] => src_payload.IN1 -sink10_data[58] => src_payload.IN1 -sink10_data[59] => src_payload.IN1 -sink10_data[59] => last_cycle.IN1 -sink10_data[60] => src_payload.IN1 -sink10_data[61] => src_payload.IN1 -sink10_data[62] => src_payload.IN1 -sink10_data[63] => src_payload.IN1 -sink10_data[64] => src_payload.IN1 -sink10_data[65] => src_payload.IN1 -sink10_data[66] => src_payload.IN1 -sink10_data[67] => src_payload.IN1 -sink10_data[68] => src_payload.IN1 -sink10_data[69] => src_payload.IN1 -sink10_data[70] => src_payload.IN1 -sink10_data[71] => src_payload.IN1 -sink10_data[72] => src_payload.IN1 -sink10_data[73] => src_payload.IN1 -sink10_data[74] => src_payload.IN1 -sink10_data[75] => src_payload.IN1 -sink10_data[76] => src_payload.IN1 -sink10_data[77] => src_payload.IN1 -sink10_data[78] => src_payload.IN1 -sink10_data[79] => src_payload.IN1 -sink10_data[80] => src_payload.IN1 -sink10_data[81] => src_payload.IN1 -sink10_data[82] => src_payload.IN1 -sink10_data[83] => src_payload.IN1 -sink10_data[84] => src_payload.IN1 -sink10_data[85] => src_payload.IN1 -sink10_data[86] => src_payload.IN1 -sink10_data[87] => src_payload.IN1 -sink10_data[88] => src_payload.IN1 -sink10_data[89] => src_payload.IN1 -sink10_data[90] => src_payload.IN1 -sink10_data[91] => src_payload.IN1 -sink10_data[92] => src_payload.IN1 -sink10_data[93] => src_payload.IN1 -sink10_data[94] => src_payload.IN1 -sink10_data[95] => src_payload.IN1 -sink10_channel[0] => src_payload.IN1 -sink10_channel[1] => src_payload.IN1 -sink10_channel[2] => src_payload.IN1 -sink10_channel[3] => src_payload.IN1 -sink10_channel[4] => src_payload.IN1 -sink10_channel[5] => src_payload.IN1 -sink10_channel[6] => src_payload.IN1 -sink10_channel[7] => src_payload.IN1 -sink10_channel[8] => src_payload.IN1 -sink10_channel[9] => src_payload.IN1 -sink10_channel[10] => src_payload.IN1 -sink10_channel[11] => src_payload.IN1 -sink10_channel[12] => src_payload.IN1 -sink10_channel[13] => src_payload.IN1 -sink10_channel[14] => src_payload.IN1 -sink10_channel[15] => src_payload.IN1 -sink10_channel[16] => src_payload.IN1 -sink10_channel[17] => src_payload.IN1 -sink10_startofpacket => src_payload.IN1 -sink10_endofpacket => src_payload.IN1 -sink10_ready <= sink10_ready.DB_MAX_OUTPUT_PORT_TYPE -sink11_valid => request[11].IN1 -sink11_data[0] => src_payload.IN1 -sink11_data[1] => src_payload.IN1 -sink11_data[2] => src_payload.IN1 -sink11_data[3] => src_payload.IN1 -sink11_data[4] => src_payload.IN1 -sink11_data[5] => src_payload.IN1 -sink11_data[6] => src_payload.IN1 -sink11_data[7] => src_payload.IN1 -sink11_data[8] => src_payload.IN1 -sink11_data[9] => src_payload.IN1 -sink11_data[10] => src_payload.IN1 -sink11_data[11] => src_payload.IN1 -sink11_data[12] => src_payload.IN1 -sink11_data[13] => src_payload.IN1 -sink11_data[14] => src_payload.IN1 -sink11_data[15] => src_payload.IN1 -sink11_data[16] => src_payload.IN1 -sink11_data[17] => src_payload.IN1 -sink11_data[18] => src_payload.IN1 -sink11_data[19] => src_payload.IN1 -sink11_data[20] => src_payload.IN1 -sink11_data[21] => src_payload.IN1 -sink11_data[22] => src_payload.IN1 -sink11_data[23] => src_payload.IN1 -sink11_data[24] => src_payload.IN1 -sink11_data[25] => src_payload.IN1 -sink11_data[26] => src_payload.IN1 -sink11_data[27] => src_payload.IN1 -sink11_data[28] => src_payload.IN1 -sink11_data[29] => src_payload.IN1 -sink11_data[30] => src_payload.IN1 -sink11_data[31] => src_payload.IN1 -sink11_data[32] => src_payload.IN1 -sink11_data[33] => src_payload.IN1 -sink11_data[34] => src_payload.IN1 -sink11_data[35] => src_payload.IN1 -sink11_data[36] => src_payload.IN1 -sink11_data[37] => src_payload.IN1 -sink11_data[38] => src_payload.IN1 -sink11_data[39] => src_payload.IN1 -sink11_data[40] => src_payload.IN1 -sink11_data[41] => src_payload.IN1 -sink11_data[42] => src_payload.IN1 -sink11_data[43] => src_payload.IN1 -sink11_data[44] => src_payload.IN1 -sink11_data[45] => src_payload.IN1 -sink11_data[46] => src_payload.IN1 -sink11_data[47] => src_payload.IN1 -sink11_data[48] => src_payload.IN1 -sink11_data[49] => src_payload.IN1 -sink11_data[50] => src_payload.IN1 -sink11_data[51] => src_payload.IN1 -sink11_data[52] => src_payload.IN1 -sink11_data[53] => src_payload.IN1 -sink11_data[54] => src_payload.IN1 -sink11_data[55] => src_payload.IN1 -sink11_data[56] => src_payload.IN1 -sink11_data[57] => src_payload.IN1 -sink11_data[58] => src_payload.IN1 -sink11_data[59] => src_payload.IN1 -sink11_data[59] => last_cycle.IN1 -sink11_data[60] => src_payload.IN1 -sink11_data[61] => src_payload.IN1 -sink11_data[62] => src_payload.IN1 -sink11_data[63] => src_payload.IN1 -sink11_data[64] => src_payload.IN1 -sink11_data[65] => src_payload.IN1 -sink11_data[66] => src_payload.IN1 -sink11_data[67] => src_payload.IN1 -sink11_data[68] => src_payload.IN1 -sink11_data[69] => src_payload.IN1 -sink11_data[70] => src_payload.IN1 -sink11_data[71] => src_payload.IN1 -sink11_data[72] => src_payload.IN1 -sink11_data[73] => src_payload.IN1 -sink11_data[74] => src_payload.IN1 -sink11_data[75] => src_payload.IN1 -sink11_data[76] => src_payload.IN1 -sink11_data[77] => src_payload.IN1 -sink11_data[78] => src_payload.IN1 -sink11_data[79] => src_payload.IN1 -sink11_data[80] => src_payload.IN1 -sink11_data[81] => src_payload.IN1 -sink11_data[82] => src_payload.IN1 -sink11_data[83] => src_payload.IN1 -sink11_data[84] => src_payload.IN1 -sink11_data[85] => src_payload.IN1 -sink11_data[86] => src_payload.IN1 -sink11_data[87] => src_payload.IN1 -sink11_data[88] => src_payload.IN1 -sink11_data[89] => src_payload.IN1 -sink11_data[90] => src_payload.IN1 -sink11_data[91] => src_payload.IN1 -sink11_data[92] => src_payload.IN1 -sink11_data[93] => src_payload.IN1 -sink11_data[94] => src_payload.IN1 -sink11_data[95] => src_payload.IN1 -sink11_channel[0] => src_payload.IN1 -sink11_channel[1] => src_payload.IN1 -sink11_channel[2] => src_payload.IN1 -sink11_channel[3] => src_payload.IN1 -sink11_channel[4] => src_payload.IN1 -sink11_channel[5] => src_payload.IN1 -sink11_channel[6] => src_payload.IN1 -sink11_channel[7] => src_payload.IN1 -sink11_channel[8] => src_payload.IN1 -sink11_channel[9] => src_payload.IN1 -sink11_channel[10] => src_payload.IN1 -sink11_channel[11] => src_payload.IN1 -sink11_channel[12] => src_payload.IN1 -sink11_channel[13] => src_payload.IN1 -sink11_channel[14] => src_payload.IN1 -sink11_channel[15] => src_payload.IN1 -sink11_channel[16] => src_payload.IN1 -sink11_channel[17] => src_payload.IN1 -sink11_startofpacket => src_payload.IN1 -sink11_endofpacket => src_payload.IN1 -sink11_ready <= sink11_ready.DB_MAX_OUTPUT_PORT_TYPE -sink12_valid => request[12].IN1 -sink12_data[0] => src_payload.IN1 -sink12_data[1] => src_payload.IN1 -sink12_data[2] => src_payload.IN1 -sink12_data[3] => src_payload.IN1 -sink12_data[4] => src_payload.IN1 -sink12_data[5] => src_payload.IN1 -sink12_data[6] => src_payload.IN1 -sink12_data[7] => src_payload.IN1 -sink12_data[8] => src_payload.IN1 -sink12_data[9] => src_payload.IN1 -sink12_data[10] => src_payload.IN1 -sink12_data[11] => src_payload.IN1 -sink12_data[12] => src_payload.IN1 -sink12_data[13] => src_payload.IN1 -sink12_data[14] => src_payload.IN1 -sink12_data[15] => src_payload.IN1 -sink12_data[16] => src_payload.IN1 -sink12_data[17] => src_payload.IN1 -sink12_data[18] => src_payload.IN1 -sink12_data[19] => src_payload.IN1 -sink12_data[20] => src_payload.IN1 -sink12_data[21] => src_payload.IN1 -sink12_data[22] => src_payload.IN1 -sink12_data[23] => src_payload.IN1 -sink12_data[24] => src_payload.IN1 -sink12_data[25] => src_payload.IN1 -sink12_data[26] => src_payload.IN1 -sink12_data[27] => src_payload.IN1 -sink12_data[28] => src_payload.IN1 -sink12_data[29] => src_payload.IN1 -sink12_data[30] => src_payload.IN1 -sink12_data[31] => src_payload.IN1 -sink12_data[32] => src_payload.IN1 -sink12_data[33] => src_payload.IN1 -sink12_data[34] => src_payload.IN1 -sink12_data[35] => src_payload.IN1 -sink12_data[36] => src_payload.IN1 -sink12_data[37] => src_payload.IN1 -sink12_data[38] => src_payload.IN1 -sink12_data[39] => src_payload.IN1 -sink12_data[40] => src_payload.IN1 -sink12_data[41] => src_payload.IN1 -sink12_data[42] => src_payload.IN1 -sink12_data[43] => src_payload.IN1 -sink12_data[44] => src_payload.IN1 -sink12_data[45] => src_payload.IN1 -sink12_data[46] => src_payload.IN1 -sink12_data[47] => src_payload.IN1 -sink12_data[48] => src_payload.IN1 -sink12_data[49] => src_payload.IN1 -sink12_data[50] => src_payload.IN1 -sink12_data[51] => src_payload.IN1 -sink12_data[52] => src_payload.IN1 -sink12_data[53] => src_payload.IN1 -sink12_data[54] => src_payload.IN1 -sink12_data[55] => src_payload.IN1 -sink12_data[56] => src_payload.IN1 -sink12_data[57] => src_payload.IN1 -sink12_data[58] => src_payload.IN1 -sink12_data[59] => src_payload.IN1 -sink12_data[59] => last_cycle.IN1 -sink12_data[60] => src_payload.IN1 -sink12_data[61] => src_payload.IN1 -sink12_data[62] => src_payload.IN1 -sink12_data[63] => src_payload.IN1 -sink12_data[64] => src_payload.IN1 -sink12_data[65] => src_payload.IN1 -sink12_data[66] => src_payload.IN1 -sink12_data[67] => src_payload.IN1 -sink12_data[68] => src_payload.IN1 -sink12_data[69] => src_payload.IN1 -sink12_data[70] => src_payload.IN1 -sink12_data[71] => src_payload.IN1 -sink12_data[72] => src_payload.IN1 -sink12_data[73] => src_payload.IN1 -sink12_data[74] => src_payload.IN1 -sink12_data[75] => src_payload.IN1 -sink12_data[76] => src_payload.IN1 -sink12_data[77] => src_payload.IN1 -sink12_data[78] => src_payload.IN1 -sink12_data[79] => src_payload.IN1 -sink12_data[80] => src_payload.IN1 -sink12_data[81] => src_payload.IN1 -sink12_data[82] => src_payload.IN1 -sink12_data[83] => src_payload.IN1 -sink12_data[84] => src_payload.IN1 -sink12_data[85] => src_payload.IN1 -sink12_data[86] => src_payload.IN1 -sink12_data[87] => src_payload.IN1 -sink12_data[88] => src_payload.IN1 -sink12_data[89] => src_payload.IN1 -sink12_data[90] => src_payload.IN1 -sink12_data[91] => src_payload.IN1 -sink12_data[92] => src_payload.IN1 -sink12_data[93] => src_payload.IN1 -sink12_data[94] => src_payload.IN1 -sink12_data[95] => src_payload.IN1 -sink12_channel[0] => src_payload.IN1 -sink12_channel[1] => src_payload.IN1 -sink12_channel[2] => src_payload.IN1 -sink12_channel[3] => src_payload.IN1 -sink12_channel[4] => src_payload.IN1 -sink12_channel[5] => src_payload.IN1 -sink12_channel[6] => src_payload.IN1 -sink12_channel[7] => src_payload.IN1 -sink12_channel[8] => src_payload.IN1 -sink12_channel[9] => src_payload.IN1 -sink12_channel[10] => src_payload.IN1 -sink12_channel[11] => src_payload.IN1 -sink12_channel[12] => src_payload.IN1 -sink12_channel[13] => src_payload.IN1 -sink12_channel[14] => src_payload.IN1 -sink12_channel[15] => src_payload.IN1 -sink12_channel[16] => src_payload.IN1 -sink12_channel[17] => src_payload.IN1 -sink12_startofpacket => src_payload.IN1 -sink12_endofpacket => src_payload.IN1 -sink12_ready <= sink12_ready.DB_MAX_OUTPUT_PORT_TYPE -sink13_valid => request[13].IN1 -sink13_data[0] => src_payload.IN1 -sink13_data[1] => src_payload.IN1 -sink13_data[2] => src_payload.IN1 -sink13_data[3] => src_payload.IN1 -sink13_data[4] => src_payload.IN1 -sink13_data[5] => src_payload.IN1 -sink13_data[6] => src_payload.IN1 -sink13_data[7] => src_payload.IN1 -sink13_data[8] => src_payload.IN1 -sink13_data[9] => src_payload.IN1 -sink13_data[10] => src_payload.IN1 -sink13_data[11] => src_payload.IN1 -sink13_data[12] => src_payload.IN1 -sink13_data[13] => src_payload.IN1 -sink13_data[14] => src_payload.IN1 -sink13_data[15] => src_payload.IN1 -sink13_data[16] => src_payload.IN1 -sink13_data[17] => src_payload.IN1 -sink13_data[18] => src_payload.IN1 -sink13_data[19] => src_payload.IN1 -sink13_data[20] => src_payload.IN1 -sink13_data[21] => src_payload.IN1 -sink13_data[22] => src_payload.IN1 -sink13_data[23] => src_payload.IN1 -sink13_data[24] => src_payload.IN1 -sink13_data[25] => src_payload.IN1 -sink13_data[26] => src_payload.IN1 -sink13_data[27] => src_payload.IN1 -sink13_data[28] => src_payload.IN1 -sink13_data[29] => src_payload.IN1 -sink13_data[30] => src_payload.IN1 -sink13_data[31] => src_payload.IN1 -sink13_data[32] => src_payload.IN1 -sink13_data[33] => src_payload.IN1 -sink13_data[34] => src_payload.IN1 -sink13_data[35] => src_payload.IN1 -sink13_data[36] => src_payload.IN1 -sink13_data[37] => src_payload.IN1 -sink13_data[38] => src_payload.IN1 -sink13_data[39] => src_payload.IN1 -sink13_data[40] => src_payload.IN1 -sink13_data[41] => src_payload.IN1 -sink13_data[42] => src_payload.IN1 -sink13_data[43] => src_payload.IN1 -sink13_data[44] => src_payload.IN1 -sink13_data[45] => src_payload.IN1 -sink13_data[46] => src_payload.IN1 -sink13_data[47] => src_payload.IN1 -sink13_data[48] => src_payload.IN1 -sink13_data[49] => src_payload.IN1 -sink13_data[50] => src_payload.IN1 -sink13_data[51] => src_payload.IN1 -sink13_data[52] => src_payload.IN1 -sink13_data[53] => src_payload.IN1 -sink13_data[54] => src_payload.IN1 -sink13_data[55] => src_payload.IN1 -sink13_data[56] => src_payload.IN1 -sink13_data[57] => src_payload.IN1 -sink13_data[58] => src_payload.IN1 -sink13_data[59] => src_payload.IN1 -sink13_data[59] => last_cycle.IN1 -sink13_data[60] => src_payload.IN1 -sink13_data[61] => src_payload.IN1 -sink13_data[62] => src_payload.IN1 -sink13_data[63] => src_payload.IN1 -sink13_data[64] => src_payload.IN1 -sink13_data[65] => src_payload.IN1 -sink13_data[66] => src_payload.IN1 -sink13_data[67] => src_payload.IN1 -sink13_data[68] => src_payload.IN1 -sink13_data[69] => src_payload.IN1 -sink13_data[70] => src_payload.IN1 -sink13_data[71] => src_payload.IN1 -sink13_data[72] => src_payload.IN1 -sink13_data[73] => src_payload.IN1 -sink13_data[74] => src_payload.IN1 -sink13_data[75] => src_payload.IN1 -sink13_data[76] => src_payload.IN1 -sink13_data[77] => src_payload.IN1 -sink13_data[78] => src_payload.IN1 -sink13_data[79] => src_payload.IN1 -sink13_data[80] => src_payload.IN1 -sink13_data[81] => src_payload.IN1 -sink13_data[82] => src_payload.IN1 -sink13_data[83] => src_payload.IN1 -sink13_data[84] => src_payload.IN1 -sink13_data[85] => src_payload.IN1 -sink13_data[86] => src_payload.IN1 -sink13_data[87] => src_payload.IN1 -sink13_data[88] => src_payload.IN1 -sink13_data[89] => src_payload.IN1 -sink13_data[90] => src_payload.IN1 -sink13_data[91] => src_payload.IN1 -sink13_data[92] => src_payload.IN1 -sink13_data[93] => src_payload.IN1 -sink13_data[94] => src_payload.IN1 -sink13_data[95] => src_payload.IN1 -sink13_channel[0] => src_payload.IN1 -sink13_channel[1] => src_payload.IN1 -sink13_channel[2] => src_payload.IN1 -sink13_channel[3] => src_payload.IN1 -sink13_channel[4] => src_payload.IN1 -sink13_channel[5] => src_payload.IN1 -sink13_channel[6] => src_payload.IN1 -sink13_channel[7] => src_payload.IN1 -sink13_channel[8] => src_payload.IN1 -sink13_channel[9] => src_payload.IN1 -sink13_channel[10] => src_payload.IN1 -sink13_channel[11] => src_payload.IN1 -sink13_channel[12] => src_payload.IN1 -sink13_channel[13] => src_payload.IN1 -sink13_channel[14] => src_payload.IN1 -sink13_channel[15] => src_payload.IN1 -sink13_channel[16] => src_payload.IN1 -sink13_channel[17] => src_payload.IN1 -sink13_startofpacket => src_payload.IN1 -sink13_endofpacket => src_payload.IN1 -sink13_ready <= sink13_ready.DB_MAX_OUTPUT_PORT_TYPE -sink14_valid => request[14].IN1 -sink14_data[0] => src_payload.IN1 -sink14_data[1] => src_payload.IN1 -sink14_data[2] => src_payload.IN1 -sink14_data[3] => src_payload.IN1 -sink14_data[4] => src_payload.IN1 -sink14_data[5] => src_payload.IN1 -sink14_data[6] => src_payload.IN1 -sink14_data[7] => src_payload.IN1 -sink14_data[8] => src_payload.IN1 -sink14_data[9] => src_payload.IN1 -sink14_data[10] => src_payload.IN1 -sink14_data[11] => src_payload.IN1 -sink14_data[12] => src_payload.IN1 -sink14_data[13] => src_payload.IN1 -sink14_data[14] => src_payload.IN1 -sink14_data[15] => src_payload.IN1 -sink14_data[16] => src_payload.IN1 -sink14_data[17] => src_payload.IN1 -sink14_data[18] => src_payload.IN1 -sink14_data[19] => src_payload.IN1 -sink14_data[20] => src_payload.IN1 -sink14_data[21] => src_payload.IN1 -sink14_data[22] => src_payload.IN1 -sink14_data[23] => src_payload.IN1 -sink14_data[24] => src_payload.IN1 -sink14_data[25] => src_payload.IN1 -sink14_data[26] => src_payload.IN1 -sink14_data[27] => src_payload.IN1 -sink14_data[28] => src_payload.IN1 -sink14_data[29] => src_payload.IN1 -sink14_data[30] => src_payload.IN1 -sink14_data[31] => src_payload.IN1 -sink14_data[32] => src_payload.IN1 -sink14_data[33] => src_payload.IN1 -sink14_data[34] => src_payload.IN1 -sink14_data[35] => src_payload.IN1 -sink14_data[36] => src_payload.IN1 -sink14_data[37] => src_payload.IN1 -sink14_data[38] => src_payload.IN1 -sink14_data[39] => src_payload.IN1 -sink14_data[40] => src_payload.IN1 -sink14_data[41] => src_payload.IN1 -sink14_data[42] => src_payload.IN1 -sink14_data[43] => src_payload.IN1 -sink14_data[44] => src_payload.IN1 -sink14_data[45] => src_payload.IN1 -sink14_data[46] => src_payload.IN1 -sink14_data[47] => src_payload.IN1 -sink14_data[48] => src_payload.IN1 -sink14_data[49] => src_payload.IN1 -sink14_data[50] => src_payload.IN1 -sink14_data[51] => src_payload.IN1 -sink14_data[52] => src_payload.IN1 -sink14_data[53] => src_payload.IN1 -sink14_data[54] => src_payload.IN1 -sink14_data[55] => src_payload.IN1 -sink14_data[56] => src_payload.IN1 -sink14_data[57] => src_payload.IN1 -sink14_data[58] => src_payload.IN1 -sink14_data[59] => src_payload.IN1 -sink14_data[59] => last_cycle.IN1 -sink14_data[60] => src_payload.IN1 -sink14_data[61] => src_payload.IN1 -sink14_data[62] => src_payload.IN1 -sink14_data[63] => src_payload.IN1 -sink14_data[64] => src_payload.IN1 -sink14_data[65] => src_payload.IN1 -sink14_data[66] => src_payload.IN1 -sink14_data[67] => src_payload.IN1 -sink14_data[68] => src_payload.IN1 -sink14_data[69] => src_payload.IN1 -sink14_data[70] => src_payload.IN1 -sink14_data[71] => src_payload.IN1 -sink14_data[72] => src_payload.IN1 -sink14_data[73] => src_payload.IN1 -sink14_data[74] => src_payload.IN1 -sink14_data[75] => src_payload.IN1 -sink14_data[76] => src_payload.IN1 -sink14_data[77] => src_payload.IN1 -sink14_data[78] => src_payload.IN1 -sink14_data[79] => src_payload.IN1 -sink14_data[80] => src_payload.IN1 -sink14_data[81] => src_payload.IN1 -sink14_data[82] => src_payload.IN1 -sink14_data[83] => src_payload.IN1 -sink14_data[84] => src_payload.IN1 -sink14_data[85] => src_payload.IN1 -sink14_data[86] => src_payload.IN1 -sink14_data[87] => src_payload.IN1 -sink14_data[88] => src_payload.IN1 -sink14_data[89] => src_payload.IN1 -sink14_data[90] => src_payload.IN1 -sink14_data[91] => src_payload.IN1 -sink14_data[92] => src_payload.IN1 -sink14_data[93] => src_payload.IN1 -sink14_data[94] => src_payload.IN1 -sink14_data[95] => src_payload.IN1 -sink14_channel[0] => src_payload.IN1 -sink14_channel[1] => src_payload.IN1 -sink14_channel[2] => src_payload.IN1 -sink14_channel[3] => src_payload.IN1 -sink14_channel[4] => src_payload.IN1 -sink14_channel[5] => src_payload.IN1 -sink14_channel[6] => src_payload.IN1 -sink14_channel[7] => src_payload.IN1 -sink14_channel[8] => src_payload.IN1 -sink14_channel[9] => src_payload.IN1 -sink14_channel[10] => src_payload.IN1 -sink14_channel[11] => src_payload.IN1 -sink14_channel[12] => src_payload.IN1 -sink14_channel[13] => src_payload.IN1 -sink14_channel[14] => src_payload.IN1 -sink14_channel[15] => src_payload.IN1 -sink14_channel[16] => src_payload.IN1 -sink14_channel[17] => src_payload.IN1 -sink14_startofpacket => src_payload.IN1 -sink14_endofpacket => src_payload.IN1 -sink14_ready <= sink14_ready.DB_MAX_OUTPUT_PORT_TYPE -sink15_valid => request[15].IN1 -sink15_data[0] => src_payload.IN1 -sink15_data[1] => src_payload.IN1 -sink15_data[2] => src_payload.IN1 -sink15_data[3] => src_payload.IN1 -sink15_data[4] => src_payload.IN1 -sink15_data[5] => src_payload.IN1 -sink15_data[6] => src_payload.IN1 -sink15_data[7] => src_payload.IN1 -sink15_data[8] => src_payload.IN1 -sink15_data[9] => src_payload.IN1 -sink15_data[10] => src_payload.IN1 -sink15_data[11] => src_payload.IN1 -sink15_data[12] => src_payload.IN1 -sink15_data[13] => src_payload.IN1 -sink15_data[14] => src_payload.IN1 -sink15_data[15] => src_payload.IN1 -sink15_data[16] => src_payload.IN1 -sink15_data[17] => src_payload.IN1 -sink15_data[18] => src_payload.IN1 -sink15_data[19] => src_payload.IN1 -sink15_data[20] => src_payload.IN1 -sink15_data[21] => src_payload.IN1 -sink15_data[22] => src_payload.IN1 -sink15_data[23] => src_payload.IN1 -sink15_data[24] => src_payload.IN1 -sink15_data[25] => src_payload.IN1 -sink15_data[26] => src_payload.IN1 -sink15_data[27] => src_payload.IN1 -sink15_data[28] => src_payload.IN1 -sink15_data[29] => src_payload.IN1 -sink15_data[30] => src_payload.IN1 -sink15_data[31] => src_payload.IN1 -sink15_data[32] => src_payload.IN1 -sink15_data[33] => src_payload.IN1 -sink15_data[34] => src_payload.IN1 -sink15_data[35] => src_payload.IN1 -sink15_data[36] => src_payload.IN1 -sink15_data[37] => src_payload.IN1 -sink15_data[38] => src_payload.IN1 -sink15_data[39] => src_payload.IN1 -sink15_data[40] => src_payload.IN1 -sink15_data[41] => src_payload.IN1 -sink15_data[42] => src_payload.IN1 -sink15_data[43] => src_payload.IN1 -sink15_data[44] => src_payload.IN1 -sink15_data[45] => src_payload.IN1 -sink15_data[46] => src_payload.IN1 -sink15_data[47] => src_payload.IN1 -sink15_data[48] => src_payload.IN1 -sink15_data[49] => src_payload.IN1 -sink15_data[50] => src_payload.IN1 -sink15_data[51] => src_payload.IN1 -sink15_data[52] => src_payload.IN1 -sink15_data[53] => src_payload.IN1 -sink15_data[54] => src_payload.IN1 -sink15_data[55] => src_payload.IN1 -sink15_data[56] => src_payload.IN1 -sink15_data[57] => src_payload.IN1 -sink15_data[58] => src_payload.IN1 -sink15_data[59] => src_payload.IN1 -sink15_data[59] => last_cycle.IN1 -sink15_data[60] => src_payload.IN1 -sink15_data[61] => src_payload.IN1 -sink15_data[62] => src_payload.IN1 -sink15_data[63] => src_payload.IN1 -sink15_data[64] => src_payload.IN1 -sink15_data[65] => src_payload.IN1 -sink15_data[66] => src_payload.IN1 -sink15_data[67] => src_payload.IN1 -sink15_data[68] => src_payload.IN1 -sink15_data[69] => src_payload.IN1 -sink15_data[70] => src_payload.IN1 -sink15_data[71] => src_payload.IN1 -sink15_data[72] => src_payload.IN1 -sink15_data[73] => src_payload.IN1 -sink15_data[74] => src_payload.IN1 -sink15_data[75] => src_payload.IN1 -sink15_data[76] => src_payload.IN1 -sink15_data[77] => src_payload.IN1 -sink15_data[78] => src_payload.IN1 -sink15_data[79] => src_payload.IN1 -sink15_data[80] => src_payload.IN1 -sink15_data[81] => src_payload.IN1 -sink15_data[82] => src_payload.IN1 -sink15_data[83] => src_payload.IN1 -sink15_data[84] => src_payload.IN1 -sink15_data[85] => src_payload.IN1 -sink15_data[86] => src_payload.IN1 -sink15_data[87] => src_payload.IN1 -sink15_data[88] => src_payload.IN1 -sink15_data[89] => src_payload.IN1 -sink15_data[90] => src_payload.IN1 -sink15_data[91] => src_payload.IN1 -sink15_data[92] => src_payload.IN1 -sink15_data[93] => src_payload.IN1 -sink15_data[94] => src_payload.IN1 -sink15_data[95] => src_payload.IN1 -sink15_channel[0] => src_payload.IN1 -sink15_channel[1] => src_payload.IN1 -sink15_channel[2] => src_payload.IN1 -sink15_channel[3] => src_payload.IN1 -sink15_channel[4] => src_payload.IN1 -sink15_channel[5] => src_payload.IN1 -sink15_channel[6] => src_payload.IN1 -sink15_channel[7] => src_payload.IN1 -sink15_channel[8] => src_payload.IN1 -sink15_channel[9] => src_payload.IN1 -sink15_channel[10] => src_payload.IN1 -sink15_channel[11] => src_payload.IN1 -sink15_channel[12] => src_payload.IN1 -sink15_channel[13] => src_payload.IN1 -sink15_channel[14] => src_payload.IN1 -sink15_channel[15] => src_payload.IN1 -sink15_channel[16] => src_payload.IN1 -sink15_channel[17] => src_payload.IN1 -sink15_startofpacket => src_payload.IN1 -sink15_endofpacket => src_payload.IN1 -sink15_ready <= sink15_ready.DB_MAX_OUTPUT_PORT_TYPE -sink16_valid => request[16].IN1 -sink16_data[0] => src_payload.IN1 -sink16_data[1] => src_payload.IN1 -sink16_data[2] => src_payload.IN1 -sink16_data[3] => src_payload.IN1 -sink16_data[4] => src_payload.IN1 -sink16_data[5] => src_payload.IN1 -sink16_data[6] => src_payload.IN1 -sink16_data[7] => src_payload.IN1 -sink16_data[8] => src_payload.IN1 -sink16_data[9] => src_payload.IN1 -sink16_data[10] => src_payload.IN1 -sink16_data[11] => src_payload.IN1 -sink16_data[12] => src_payload.IN1 -sink16_data[13] => src_payload.IN1 -sink16_data[14] => src_payload.IN1 -sink16_data[15] => src_payload.IN1 -sink16_data[16] => src_payload.IN1 -sink16_data[17] => src_payload.IN1 -sink16_data[18] => src_payload.IN1 -sink16_data[19] => src_payload.IN1 -sink16_data[20] => src_payload.IN1 -sink16_data[21] => src_payload.IN1 -sink16_data[22] => src_payload.IN1 -sink16_data[23] => src_payload.IN1 -sink16_data[24] => src_payload.IN1 -sink16_data[25] => src_payload.IN1 -sink16_data[26] => src_payload.IN1 -sink16_data[27] => src_payload.IN1 -sink16_data[28] => src_payload.IN1 -sink16_data[29] => src_payload.IN1 -sink16_data[30] => src_payload.IN1 -sink16_data[31] => src_payload.IN1 -sink16_data[32] => src_payload.IN1 -sink16_data[33] => src_payload.IN1 -sink16_data[34] => src_payload.IN1 -sink16_data[35] => src_payload.IN1 -sink16_data[36] => src_payload.IN1 -sink16_data[37] => src_payload.IN1 -sink16_data[38] => src_payload.IN1 -sink16_data[39] => src_payload.IN1 -sink16_data[40] => src_payload.IN1 -sink16_data[41] => src_payload.IN1 -sink16_data[42] => src_payload.IN1 -sink16_data[43] => src_payload.IN1 -sink16_data[44] => src_payload.IN1 -sink16_data[45] => src_payload.IN1 -sink16_data[46] => src_payload.IN1 -sink16_data[47] => src_payload.IN1 -sink16_data[48] => src_payload.IN1 -sink16_data[49] => src_payload.IN1 -sink16_data[50] => src_payload.IN1 -sink16_data[51] => src_payload.IN1 -sink16_data[52] => src_payload.IN1 -sink16_data[53] => src_payload.IN1 -sink16_data[54] => src_payload.IN1 -sink16_data[55] => src_payload.IN1 -sink16_data[56] => src_payload.IN1 -sink16_data[57] => src_payload.IN1 -sink16_data[58] => src_payload.IN1 -sink16_data[59] => src_payload.IN1 -sink16_data[59] => last_cycle.IN1 -sink16_data[60] => src_payload.IN1 -sink16_data[61] => src_payload.IN1 -sink16_data[62] => src_payload.IN1 -sink16_data[63] => src_payload.IN1 -sink16_data[64] => src_payload.IN1 -sink16_data[65] => src_payload.IN1 -sink16_data[66] => src_payload.IN1 -sink16_data[67] => src_payload.IN1 -sink16_data[68] => src_payload.IN1 -sink16_data[69] => src_payload.IN1 -sink16_data[70] => src_payload.IN1 -sink16_data[71] => src_payload.IN1 -sink16_data[72] => src_payload.IN1 -sink16_data[73] => src_payload.IN1 -sink16_data[74] => src_payload.IN1 -sink16_data[75] => src_payload.IN1 -sink16_data[76] => src_payload.IN1 -sink16_data[77] => src_payload.IN1 -sink16_data[78] => src_payload.IN1 -sink16_data[79] => src_payload.IN1 -sink16_data[80] => src_payload.IN1 -sink16_data[81] => src_payload.IN1 -sink16_data[82] => src_payload.IN1 -sink16_data[83] => src_payload.IN1 -sink16_data[84] => src_payload.IN1 -sink16_data[85] => src_payload.IN1 -sink16_data[86] => src_payload.IN1 -sink16_data[87] => src_payload.IN1 -sink16_data[88] => src_payload.IN1 -sink16_data[89] => src_payload.IN1 -sink16_data[90] => src_payload.IN1 -sink16_data[91] => src_payload.IN1 -sink16_data[92] => src_payload.IN1 -sink16_data[93] => src_payload.IN1 -sink16_data[94] => src_payload.IN1 -sink16_data[95] => src_payload.IN1 -sink16_channel[0] => src_payload.IN1 -sink16_channel[1] => src_payload.IN1 -sink16_channel[2] => src_payload.IN1 -sink16_channel[3] => src_payload.IN1 -sink16_channel[4] => src_payload.IN1 -sink16_channel[5] => src_payload.IN1 -sink16_channel[6] => src_payload.IN1 -sink16_channel[7] => src_payload.IN1 -sink16_channel[8] => src_payload.IN1 -sink16_channel[9] => src_payload.IN1 -sink16_channel[10] => src_payload.IN1 -sink16_channel[11] => src_payload.IN1 -sink16_channel[12] => src_payload.IN1 -sink16_channel[13] => src_payload.IN1 -sink16_channel[14] => src_payload.IN1 -sink16_channel[15] => src_payload.IN1 -sink16_channel[16] => src_payload.IN1 -sink16_channel[17] => src_payload.IN1 -sink16_startofpacket => src_payload.IN1 -sink16_endofpacket => src_payload.IN1 -sink16_ready <= sink16_ready.DB_MAX_OUTPUT_PORT_TYPE -sink17_valid => request[17].IN1 -sink17_data[0] => src_payload.IN1 -sink17_data[1] => src_payload.IN1 -sink17_data[2] => src_payload.IN1 -sink17_data[3] => src_payload.IN1 -sink17_data[4] => src_payload.IN1 -sink17_data[5] => src_payload.IN1 -sink17_data[6] => src_payload.IN1 -sink17_data[7] => src_payload.IN1 -sink17_data[8] => src_payload.IN1 -sink17_data[9] => src_payload.IN1 -sink17_data[10] => src_payload.IN1 -sink17_data[11] => src_payload.IN1 -sink17_data[12] => src_payload.IN1 -sink17_data[13] => src_payload.IN1 -sink17_data[14] => src_payload.IN1 -sink17_data[15] => src_payload.IN1 -sink17_data[16] => src_payload.IN1 -sink17_data[17] => src_payload.IN1 -sink17_data[18] => src_payload.IN1 -sink17_data[19] => src_payload.IN1 -sink17_data[20] => src_payload.IN1 -sink17_data[21] => src_payload.IN1 -sink17_data[22] => src_payload.IN1 -sink17_data[23] => src_payload.IN1 -sink17_data[24] => src_payload.IN1 -sink17_data[25] => src_payload.IN1 -sink17_data[26] => src_payload.IN1 -sink17_data[27] => src_payload.IN1 -sink17_data[28] => src_payload.IN1 -sink17_data[29] => src_payload.IN1 -sink17_data[30] => src_payload.IN1 -sink17_data[31] => src_payload.IN1 -sink17_data[32] => src_payload.IN1 -sink17_data[33] => src_payload.IN1 -sink17_data[34] => src_payload.IN1 -sink17_data[35] => src_payload.IN1 -sink17_data[36] => src_payload.IN1 -sink17_data[37] => src_payload.IN1 -sink17_data[38] => src_payload.IN1 -sink17_data[39] => src_payload.IN1 -sink17_data[40] => src_payload.IN1 -sink17_data[41] => src_payload.IN1 -sink17_data[42] => src_payload.IN1 -sink17_data[43] => src_payload.IN1 -sink17_data[44] => src_payload.IN1 -sink17_data[45] => src_payload.IN1 -sink17_data[46] => src_payload.IN1 -sink17_data[47] => src_payload.IN1 -sink17_data[48] => src_payload.IN1 -sink17_data[49] => src_payload.IN1 -sink17_data[50] => src_payload.IN1 -sink17_data[51] => src_payload.IN1 -sink17_data[52] => src_payload.IN1 -sink17_data[53] => src_payload.IN1 -sink17_data[54] => src_payload.IN1 -sink17_data[55] => src_payload.IN1 -sink17_data[56] => src_payload.IN1 -sink17_data[57] => src_payload.IN1 -sink17_data[58] => src_payload.IN1 -sink17_data[59] => src_payload.IN1 -sink17_data[59] => last_cycle.IN1 -sink17_data[60] => src_payload.IN1 -sink17_data[61] => src_payload.IN1 -sink17_data[62] => src_payload.IN1 -sink17_data[63] => src_payload.IN1 -sink17_data[64] => src_payload.IN1 -sink17_data[65] => src_payload.IN1 -sink17_data[66] => src_payload.IN1 -sink17_data[67] => src_payload.IN1 -sink17_data[68] => src_payload.IN1 -sink17_data[69] => src_payload.IN1 -sink17_data[70] => src_payload.IN1 -sink17_data[71] => src_payload.IN1 -sink17_data[72] => src_payload.IN1 -sink17_data[73] => src_payload.IN1 -sink17_data[74] => src_payload.IN1 -sink17_data[75] => src_payload.IN1 -sink17_data[76] => src_payload.IN1 -sink17_data[77] => src_payload.IN1 -sink17_data[78] => src_payload.IN1 -sink17_data[79] => src_payload.IN1 -sink17_data[80] => src_payload.IN1 -sink17_data[81] => src_payload.IN1 -sink17_data[82] => src_payload.IN1 -sink17_data[83] => src_payload.IN1 -sink17_data[84] => src_payload.IN1 -sink17_data[85] => src_payload.IN1 -sink17_data[86] => src_payload.IN1 -sink17_data[87] => src_payload.IN1 -sink17_data[88] => src_payload.IN1 -sink17_data[89] => src_payload.IN1 -sink17_data[90] => src_payload.IN1 -sink17_data[91] => src_payload.IN1 -sink17_data[92] => src_payload.IN1 -sink17_data[93] => src_payload.IN1 -sink17_data[94] => src_payload.IN1 -sink17_data[95] => src_payload.IN1 -sink17_channel[0] => src_payload.IN1 -sink17_channel[1] => src_payload.IN1 -sink17_channel[2] => src_payload.IN1 -sink17_channel[3] => src_payload.IN1 -sink17_channel[4] => src_payload.IN1 -sink17_channel[5] => src_payload.IN1 -sink17_channel[6] => src_payload.IN1 -sink17_channel[7] => src_payload.IN1 -sink17_channel[8] => src_payload.IN1 -sink17_channel[9] => src_payload.IN1 -sink17_channel[10] => src_payload.IN1 -sink17_channel[11] => src_payload.IN1 -sink17_channel[12] => src_payload.IN1 -sink17_channel[13] => src_payload.IN1 -sink17_channel[14] => src_payload.IN1 -sink17_channel[15] => src_payload.IN1 -sink17_channel[16] => src_payload.IN1 -sink17_channel[17] => src_payload.IN1 -sink17_startofpacket => src_payload.IN1 -sink17_endofpacket => src_payload.IN1 -sink17_ready <= sink17_ready.DB_MAX_OUTPUT_PORT_TYPE -src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE -src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE -src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE -src_ready => last_cycle.IN0 -src_ready => sink0_ready.IN1 -src_ready => sink1_ready.IN1 -src_ready => sink2_ready.IN1 -src_ready => sink3_ready.IN1 -src_ready => sink4_ready.IN1 -src_ready => sink5_ready.IN1 -src_ready => sink6_ready.IN1 -src_ready => sink7_ready.IN1 -src_ready => sink8_ready.IN1 -src_ready => sink9_ready.IN1 -src_ready => sink10_ready.IN1 -src_ready => sink11_ready.IN1 -src_ready => sink12_ready.IN1 -src_ready => sink13_ready.IN1 -src_ready => sink14_ready.IN1 -src_ready => sink15_ready.IN1 -src_ready => sink16_ready.IN1 -src_ready => sink17_ready.IN1 -clk => clk.IN1 -reset => reset.IN1 - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -request[0] => grant[0].DATAIN -request[0] => _.IN1 -request[0] => _.IN1 -request[1] => grant[1].DATAIN -request[1] => _.IN1 -request[1] => _.IN1 -request[2] => grant[2].DATAIN -request[2] => _.IN1 -request[2] => _.IN1 -request[3] => grant[3].DATAIN -request[3] => _.IN1 -request[3] => _.IN1 -request[4] => grant[4].DATAIN -request[4] => _.IN1 -request[4] => _.IN1 -request[5] => grant[5].DATAIN -request[5] => _.IN1 -request[5] => _.IN1 -request[6] => grant[6].DATAIN -request[6] => _.IN1 -request[6] => _.IN1 -request[7] => grant[7].DATAIN -request[7] => _.IN1 -request[7] => _.IN1 -request[8] => grant[8].DATAIN -request[8] => _.IN1 -request[8] => _.IN1 -request[9] => grant[9].DATAIN -request[9] => _.IN1 -request[9] => _.IN1 -request[10] => grant[10].DATAIN -request[10] => _.IN1 -request[10] => _.IN1 -request[11] => grant[11].DATAIN -request[11] => _.IN1 -request[11] => _.IN1 -request[12] => grant[12].DATAIN -request[12] => _.IN1 -request[12] => _.IN1 -request[13] => grant[13].DATAIN -request[13] => _.IN1 -request[13] => _.IN1 -request[14] => grant[14].DATAIN -request[14] => _.IN1 -request[14] => _.IN1 -request[15] => grant[15].DATAIN -request[15] => _.IN1 -request[15] => _.IN1 -request[16] => grant[16].DATAIN -request[16] => _.IN1 -request[16] => _.IN1 -request[17] => grant[17].DATAIN -request[17] => _.IN1 -request[17] => _.IN1 -grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE -grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE -grant[2] <= request[2].DB_MAX_OUTPUT_PORT_TYPE -grant[3] <= request[3].DB_MAX_OUTPUT_PORT_TYPE -grant[4] <= request[4].DB_MAX_OUTPUT_PORT_TYPE -grant[5] <= request[5].DB_MAX_OUTPUT_PORT_TYPE -grant[6] <= request[6].DB_MAX_OUTPUT_PORT_TYPE -grant[7] <= request[7].DB_MAX_OUTPUT_PORT_TYPE -grant[8] <= request[8].DB_MAX_OUTPUT_PORT_TYPE -grant[9] <= request[9].DB_MAX_OUTPUT_PORT_TYPE -grant[10] <= request[10].DB_MAX_OUTPUT_PORT_TYPE -grant[11] <= request[11].DB_MAX_OUTPUT_PORT_TYPE -grant[12] <= request[12].DB_MAX_OUTPUT_PORT_TYPE -grant[13] <= request[13].DB_MAX_OUTPUT_PORT_TYPE -grant[14] <= request[14].DB_MAX_OUTPUT_PORT_TYPE -grant[15] <= request[15].DB_MAX_OUTPUT_PORT_TYPE -grant[16] <= request[16].DB_MAX_OUTPUT_PORT_TYPE -grant[17] <= request[17].DB_MAX_OUTPUT_PORT_TYPE -increment_top_priority => ~NO_FANOUT~ -save_top_priority => ~NO_FANOUT~ - - -|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -a[0] => Add0.IN36 -a[1] => Add0.IN35 -a[2] => Add0.IN34 -a[3] => Add0.IN33 -a[4] => Add0.IN32 -a[5] => Add0.IN31 -a[6] => Add0.IN30 -a[7] => Add0.IN29 -a[8] => Add0.IN28 -a[9] => Add0.IN27 -a[10] => Add0.IN26 -a[11] => Add0.IN25 -a[12] => Add0.IN24 -a[13] => Add0.IN23 -a[14] => Add0.IN22 -a[15] => Add0.IN21 -a[16] => Add0.IN20 -a[17] => Add0.IN19 -a[18] => Add0.IN18 -a[19] => Add0.IN17 -a[20] => Add0.IN16 -a[21] => Add0.IN15 -a[22] => Add0.IN14 -a[23] => Add0.IN13 -a[24] => Add0.IN12 -a[25] => Add0.IN11 -a[26] => Add0.IN10 -a[27] => Add0.IN9 -a[28] => Add0.IN8 -a[29] => Add0.IN7 -a[30] => Add0.IN6 -a[31] => Add0.IN5 -a[32] => Add0.IN4 -a[33] => Add0.IN3 -a[34] => Add0.IN2 -a[35] => Add0.IN1 -b[0] => Add0.IN72 -b[1] => Add0.IN71 -b[2] => Add0.IN70 -b[3] => Add0.IN69 -b[4] => Add0.IN68 -b[5] => Add0.IN67 -b[6] => Add0.IN66 -b[7] => Add0.IN65 -b[8] => Add0.IN64 -b[9] => Add0.IN63 -b[10] => Add0.IN62 -b[11] => Add0.IN61 -b[12] => Add0.IN60 -b[13] => Add0.IN59 -b[14] => Add0.IN58 -b[15] => Add0.IN57 -b[16] => Add0.IN56 -b[17] => Add0.IN55 -b[18] => Add0.IN54 -b[19] => Add0.IN53 -b[20] => Add0.IN52 -b[21] => Add0.IN51 -b[22] => Add0.IN50 -b[23] => Add0.IN49 -b[24] => Add0.IN48 -b[25] => Add0.IN47 -b[26] => Add0.IN46 -b[27] => Add0.IN45 -b[28] => Add0.IN44 -b[29] => Add0.IN43 -b[30] => Add0.IN42 -b[31] => Add0.IN41 -b[32] => Add0.IN40 -b[33] => Add0.IN39 -b[34] => Add0.IN38 -b[35] => Add0.IN37 -sum[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[32] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[33] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[34] <= Add0.DB_MAX_OUTPUT_PORT_TYPE -sum[35] <= Add0.DB_MAX_OUTPUT_PORT_TYPE - - -|lights|nios_system:NiosII|nios_system_irq_mapper:irq_mapper -clk => ~NO_FANOUT~ -reset => ~NO_FANOUT~ -receiver0_irq => sender_irq[5].DATAIN -sender_irq[0] <= -sender_irq[1] <= -sender_irq[2] <= -sender_irq[3] <= -sender_irq[4] <= -sender_irq[5] <= receiver0_irq.DB_MAX_OUTPUT_PORT_TYPE -sender_irq[6] <= -sender_irq[7] <= -sender_irq[8] <= -sender_irq[9] <= -sender_irq[10] <= -sender_irq[11] <= -sender_irq[12] <= -sender_irq[13] <= -sender_irq[14] <= -sender_irq[15] <= -sender_irq[16] <= -sender_irq[17] <= -sender_irq[18] <= -sender_irq[19] <= -sender_irq[20] <= -sender_irq[21] <= -sender_irq[22] <= -sender_irq[23] <= -sender_irq[24] <= -sender_irq[25] <= -sender_irq[26] <= -sender_irq[27] <= -sender_irq[28] <= -sender_irq[29] <= -sender_irq[30] <= -sender_irq[31] <= - - +|lights +CLOCK_50 => nios_system:NiosII.clk_clk +KEY[0] => nios_system:NiosII.reset_reset_n +KEY[1] => nios_system:NiosII.push_switches_export[0] +KEY[2] => nios_system:NiosII.push_switches_export[1] +KEY[3] => nios_system:NiosII.push_switches_export[2] +SW[0] => nios_system:NiosII.switches_export[0] +SW[1] => nios_system:NiosII.switches_export[1] +SW[2] => nios_system:NiosII.switches_export[2] +SW[3] => nios_system:NiosII.switches_export[3] +SW[4] => nios_system:NiosII.switches_export[4] +SW[5] => nios_system:NiosII.switches_export[5] +SW[6] => nios_system:NiosII.switches_export[6] +SW[7] => nios_system:NiosII.switches_export[7] +SW[8] => nios_system:NiosII.switches_export[8] +SW[9] => nios_system:NiosII.switches_export[9] +SW[10] => nios_system:NiosII.switches_export[10] +SW[11] => nios_system:NiosII.switches_export[11] +SW[12] => nios_system:NiosII.switches_export[12] +SW[13] => nios_system:NiosII.switches_export[13] +SW[14] => nios_system:NiosII.switches_export[14] +SW[15] => nios_system:NiosII.switches_export[15] +SW[16] => nios_system:NiosII.switches_export[16] +SW[17] => nios_system:NiosII.switches_export[17] +LEDG[0] <= nios_system:NiosII.leds_export[0] +LEDG[1] <= nios_system:NiosII.leds_export[1] +LEDG[2] <= nios_system:NiosII.leds_export[2] +LEDG[3] <= nios_system:NiosII.leds_export[3] +LEDG[4] <= nios_system:NiosII.leds_export[4] +LEDG[5] <= nios_system:NiosII.leds_export[5] +LEDG[6] <= nios_system:NiosII.leds_export[6] +LEDG[7] <= nios_system:NiosII.leds_export[7] +LEDR[0] <= nios_system:NiosII.ledrs_export[0] +LEDR[1] <= nios_system:NiosII.ledrs_export[1] +LEDR[2] <= nios_system:NiosII.ledrs_export[2] +LEDR[3] <= nios_system:NiosII.ledrs_export[3] +LEDR[4] <= nios_system:NiosII.ledrs_export[4] +LEDR[5] <= nios_system:NiosII.ledrs_export[5] +LEDR[6] <= nios_system:NiosII.ledrs_export[6] +LEDR[7] <= nios_system:NiosII.ledrs_export[7] +LEDR[8] <= nios_system:NiosII.ledrs_export[8] +LEDR[9] <= nios_system:NiosII.ledrs_export[9] +LEDR[10] <= nios_system:NiosII.ledrs_export[10] +LEDR[11] <= nios_system:NiosII.ledrs_export[11] +LEDR[12] <= nios_system:NiosII.ledrs_export[12] +LEDR[13] <= nios_system:NiosII.ledrs_export[13] +LEDR[14] <= nios_system:NiosII.ledrs_export[14] +LEDR[15] <= nios_system:NiosII.ledrs_export[15] +LEDR[16] <= nios_system:NiosII.ledrs_export[16] +LEDR[17] <= nios_system:NiosII.ledrs_export[17] +HEX0[0] <= nios_system:NiosII.hex0_export[0] +HEX0[1] <= nios_system:NiosII.hex0_export[1] +HEX0[2] <= nios_system:NiosII.hex0_export[2] +HEX0[3] <= nios_system:NiosII.hex0_export[3] +HEX0[4] <= nios_system:NiosII.hex0_export[4] +HEX0[5] <= nios_system:NiosII.hex0_export[5] +HEX0[6] <= nios_system:NiosII.hex0_export[6] +HEX1[0] <= nios_system:NiosII.hex1_export[0] +HEX1[1] <= nios_system:NiosII.hex1_export[1] +HEX1[2] <= nios_system:NiosII.hex1_export[2] +HEX1[3] <= nios_system:NiosII.hex1_export[3] +HEX1[4] <= nios_system:NiosII.hex1_export[4] +HEX1[5] <= nios_system:NiosII.hex1_export[5] +HEX1[6] <= nios_system:NiosII.hex1_export[6] +HEX2[0] <= nios_system:NiosII.hex2_export[0] +HEX2[1] <= nios_system:NiosII.hex2_export[1] +HEX2[2] <= nios_system:NiosII.hex2_export[2] +HEX2[3] <= nios_system:NiosII.hex2_export[3] +HEX2[4] <= nios_system:NiosII.hex2_export[4] +HEX2[5] <= nios_system:NiosII.hex2_export[5] +HEX2[6] <= nios_system:NiosII.hex2_export[6] +HEX3[0] <= nios_system:NiosII.hex3_export[0] +HEX3[1] <= nios_system:NiosII.hex3_export[1] +HEX3[2] <= nios_system:NiosII.hex3_export[2] +HEX3[3] <= nios_system:NiosII.hex3_export[3] +HEX3[4] <= nios_system:NiosII.hex3_export[4] +HEX3[5] <= nios_system:NiosII.hex3_export[5] +HEX3[6] <= nios_system:NiosII.hex3_export[6] +HEX4[0] <= nios_system:NiosII.hex4_export[0] +HEX4[1] <= nios_system:NiosII.hex4_export[1] +HEX4[2] <= nios_system:NiosII.hex4_export[2] +HEX4[3] <= nios_system:NiosII.hex4_export[3] +HEX4[4] <= nios_system:NiosII.hex4_export[4] +HEX4[5] <= nios_system:NiosII.hex4_export[5] +HEX4[6] <= nios_system:NiosII.hex4_export[6] +HEX5[0] <= nios_system:NiosII.hex5_export[0] +HEX5[1] <= nios_system:NiosII.hex5_export[1] +HEX5[2] <= nios_system:NiosII.hex5_export[2] +HEX5[3] <= nios_system:NiosII.hex5_export[3] +HEX5[4] <= nios_system:NiosII.hex5_export[4] +HEX5[5] <= nios_system:NiosII.hex5_export[5] +HEX5[6] <= nios_system:NiosII.hex5_export[6] +HEX6[0] <= nios_system:NiosII.hex6_export[0] +HEX6[1] <= nios_system:NiosII.hex6_export[1] +HEX6[2] <= nios_system:NiosII.hex6_export[2] +HEX6[3] <= nios_system:NiosII.hex6_export[3] +HEX6[4] <= nios_system:NiosII.hex6_export[4] +HEX6[5] <= nios_system:NiosII.hex6_export[5] +HEX6[6] <= nios_system:NiosII.hex6_export[6] +HEX7[0] <= nios_system:NiosII.hex7_export[0] +HEX7[1] <= nios_system:NiosII.hex7_export[1] +HEX7[2] <= nios_system:NiosII.hex7_export[2] +HEX7[3] <= nios_system:NiosII.hex7_export[3] +HEX7[4] <= nios_system:NiosII.hex7_export[4] +HEX7[5] <= nios_system:NiosII.hex7_export[5] +HEX7[6] <= nios_system:NiosII.hex7_export[6] +LCD_RS <= nios_system:NiosII.lcd_16207_0_RS +LCD_RW <= nios_system:NiosII.lcd_16207_0_RW +LCD_data[0] <= nios_system:NiosII.lcd_16207_0_data[0] +LCD_data[1] <= nios_system:NiosII.lcd_16207_0_data[1] +LCD_data[2] <= nios_system:NiosII.lcd_16207_0_data[2] +LCD_data[3] <= nios_system:NiosII.lcd_16207_0_data[3] +LCD_data[4] <= nios_system:NiosII.lcd_16207_0_data[4] +LCD_data[5] <= nios_system:NiosII.lcd_16207_0_data[5] +LCD_data[6] <= nios_system:NiosII.lcd_16207_0_data[6] +LCD_data[7] <= nios_system:NiosII.lcd_16207_0_data[7] +LCD_EN <= nios_system:NiosII.lcd_16207_0_E +LCD_ON <= nios_system:NiosII.lcd_on_export +LCD_BLON <= nios_system:NiosII.lcd_blon_export + + +|lights|nios_system:NiosII +clk_clk => clk_clk.IN122 +leds_export[0] <= nios_system_LEDs:leds.out_port +leds_export[1] <= nios_system_LEDs:leds.out_port +leds_export[2] <= nios_system_LEDs:leds.out_port +leds_export[3] <= nios_system_LEDs:leds.out_port +leds_export[4] <= nios_system_LEDs:leds.out_port +leds_export[5] <= nios_system_LEDs:leds.out_port +leds_export[6] <= nios_system_LEDs:leds.out_port +leds_export[7] <= nios_system_LEDs:leds.out_port +reset_reset_n => _.IN1 +ledrs_export[0] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[1] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[2] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[3] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[4] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[5] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[6] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[7] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[8] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[9] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[10] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[11] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[12] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[13] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[14] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[15] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[16] <= nios_system_LEDRs:ledrs.out_port +ledrs_export[17] <= nios_system_LEDRs:ledrs.out_port +switches_export[0] => switches_export[0].IN1 +switches_export[1] => switches_export[1].IN1 +switches_export[2] => switches_export[2].IN1 +switches_export[3] => switches_export[3].IN1 +switches_export[4] => switches_export[4].IN1 +switches_export[5] => switches_export[5].IN1 +switches_export[6] => switches_export[6].IN1 +switches_export[7] => switches_export[7].IN1 +switches_export[8] => switches_export[8].IN1 +switches_export[9] => switches_export[9].IN1 +switches_export[10] => switches_export[10].IN1 +switches_export[11] => switches_export[11].IN1 +switches_export[12] => switches_export[12].IN1 +switches_export[13] => switches_export[13].IN1 +switches_export[14] => switches_export[14].IN1 +switches_export[15] => switches_export[15].IN1 +switches_export[16] => switches_export[16].IN1 +switches_export[17] => switches_export[17].IN1 +push_switches_export[0] => push_switches_export[0].IN1 +push_switches_export[1] => push_switches_export[1].IN1 +push_switches_export[2] => push_switches_export[2].IN1 +hex0_export[0] <= nios_system_hex0:hex0.out_port +hex0_export[1] <= nios_system_hex0:hex0.out_port +hex0_export[2] <= nios_system_hex0:hex0.out_port +hex0_export[3] <= nios_system_hex0:hex0.out_port +hex0_export[4] <= nios_system_hex0:hex0.out_port +hex0_export[5] <= nios_system_hex0:hex0.out_port +hex0_export[6] <= nios_system_hex0:hex0.out_port +hex1_export[0] <= nios_system_hex0:hex1.out_port +hex1_export[1] <= nios_system_hex0:hex1.out_port +hex1_export[2] <= nios_system_hex0:hex1.out_port +hex1_export[3] <= nios_system_hex0:hex1.out_port +hex1_export[4] <= nios_system_hex0:hex1.out_port +hex1_export[5] <= nios_system_hex0:hex1.out_port +hex1_export[6] <= nios_system_hex0:hex1.out_port +hex2_export[0] <= nios_system_hex0:hex2.out_port +hex2_export[1] <= nios_system_hex0:hex2.out_port +hex2_export[2] <= nios_system_hex0:hex2.out_port +hex2_export[3] <= nios_system_hex0:hex2.out_port +hex2_export[4] <= nios_system_hex0:hex2.out_port +hex2_export[5] <= nios_system_hex0:hex2.out_port +hex2_export[6] <= nios_system_hex0:hex2.out_port +hex3_export[0] <= nios_system_hex0:hex3.out_port +hex3_export[1] <= nios_system_hex0:hex3.out_port +hex3_export[2] <= nios_system_hex0:hex3.out_port +hex3_export[3] <= nios_system_hex0:hex3.out_port +hex3_export[4] <= nios_system_hex0:hex3.out_port +hex3_export[5] <= nios_system_hex0:hex3.out_port +hex3_export[6] <= nios_system_hex0:hex3.out_port +hex4_export[0] <= nios_system_hex0:hex4.out_port +hex4_export[1] <= nios_system_hex0:hex4.out_port +hex4_export[2] <= nios_system_hex0:hex4.out_port +hex4_export[3] <= nios_system_hex0:hex4.out_port +hex4_export[4] <= nios_system_hex0:hex4.out_port +hex4_export[5] <= nios_system_hex0:hex4.out_port +hex4_export[6] <= nios_system_hex0:hex4.out_port +hex5_export[0] <= nios_system_hex0:hex5.out_port +hex5_export[1] <= nios_system_hex0:hex5.out_port +hex5_export[2] <= nios_system_hex0:hex5.out_port +hex5_export[3] <= nios_system_hex0:hex5.out_port +hex5_export[4] <= nios_system_hex0:hex5.out_port +hex5_export[5] <= nios_system_hex0:hex5.out_port +hex5_export[6] <= nios_system_hex0:hex5.out_port +hex6_export[0] <= nios_system_hex0:hex6.out_port +hex6_export[1] <= nios_system_hex0:hex6.out_port +hex6_export[2] <= nios_system_hex0:hex6.out_port +hex6_export[3] <= nios_system_hex0:hex6.out_port +hex6_export[4] <= nios_system_hex0:hex6.out_port +hex6_export[5] <= nios_system_hex0:hex6.out_port +hex6_export[6] <= nios_system_hex0:hex6.out_port +hex7_export[0] <= nios_system_hex0:hex7.out_port +hex7_export[1] <= nios_system_hex0:hex7.out_port +hex7_export[2] <= nios_system_hex0:hex7.out_port +hex7_export[3] <= nios_system_hex0:hex7.out_port +hex7_export[4] <= nios_system_hex0:hex7.out_port +hex7_export[5] <= nios_system_hex0:hex7.out_port +hex7_export[6] <= nios_system_hex0:hex7.out_port +lcd_16207_0_RS <= nios_system_lcd_16207_0:lcd_16207_0.LCD_RS +lcd_16207_0_RW <= nios_system_lcd_16207_0:lcd_16207_0.LCD_RW +lcd_16207_0_data[0] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_data[1] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_data[2] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_data[3] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_data[4] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_data[5] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_data[6] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_data[7] <> nios_system_lcd_16207_0:lcd_16207_0.LCD_data +lcd_16207_0_E <= nios_system_lcd_16207_0:lcd_16207_0.LCD_E +lcd_on_export <= nios_system_lcd_on:lcd_on.out_port +lcd_blon_export <= nios_system_lcd_on:lcd_blon.out_port + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor +clk => clk.IN4 +d_irq[0] => ~NO_FANOUT~ +d_irq[1] => ~NO_FANOUT~ +d_irq[2] => ~NO_FANOUT~ +d_irq[3] => ~NO_FANOUT~ +d_irq[4] => ~NO_FANOUT~ +d_irq[5] => W_ipending_reg_nxt.IN1 +d_irq[6] => ~NO_FANOUT~ +d_irq[7] => ~NO_FANOUT~ +d_irq[8] => ~NO_FANOUT~ +d_irq[9] => ~NO_FANOUT~ +d_irq[10] => ~NO_FANOUT~ +d_irq[11] => ~NO_FANOUT~ +d_irq[12] => ~NO_FANOUT~ +d_irq[13] => ~NO_FANOUT~ +d_irq[14] => ~NO_FANOUT~ +d_irq[15] => ~NO_FANOUT~ +d_irq[16] => ~NO_FANOUT~ +d_irq[17] => ~NO_FANOUT~ +d_irq[18] => ~NO_FANOUT~ +d_irq[19] => ~NO_FANOUT~ +d_irq[20] => ~NO_FANOUT~ +d_irq[21] => ~NO_FANOUT~ +d_irq[22] => ~NO_FANOUT~ +d_irq[23] => ~NO_FANOUT~ +d_irq[24] => ~NO_FANOUT~ +d_irq[25] => ~NO_FANOUT~ +d_irq[26] => ~NO_FANOUT~ +d_irq[27] => ~NO_FANOUT~ +d_irq[28] => ~NO_FANOUT~ +d_irq[29] => ~NO_FANOUT~ +d_irq[30] => ~NO_FANOUT~ +d_irq[31] => ~NO_FANOUT~ +d_readdata[0] => av_ld_byte0_data_nxt.DATAA +d_readdata[1] => av_ld_byte0_data_nxt.DATAA +d_readdata[2] => av_ld_byte0_data_nxt.DATAA +d_readdata[3] => av_ld_byte0_data_nxt.DATAA +d_readdata[4] => av_ld_byte0_data_nxt.DATAA +d_readdata[5] => av_ld_byte0_data_nxt.DATAA +d_readdata[6] => av_ld_byte0_data_nxt.DATAA +d_readdata[7] => av_ld_byte0_data_nxt.DATAA +d_readdata[8] => av_ld_byte1_data_nxt.DATAA +d_readdata[9] => av_ld_byte1_data_nxt.DATAA +d_readdata[10] => av_ld_byte1_data_nxt.DATAA +d_readdata[11] => av_ld_byte1_data_nxt.DATAA +d_readdata[12] => av_ld_byte1_data_nxt.DATAA +d_readdata[13] => av_ld_byte1_data_nxt.DATAA +d_readdata[14] => av_ld_byte1_data_nxt.DATAA +d_readdata[15] => av_ld_byte1_data_nxt.DATAA +d_readdata[16] => av_ld_byte2_data_nxt.DATAA +d_readdata[17] => av_ld_byte2_data_nxt.DATAA +d_readdata[18] => av_ld_byte2_data_nxt.DATAA +d_readdata[19] => av_ld_byte2_data_nxt.DATAA +d_readdata[20] => av_ld_byte2_data_nxt.DATAA +d_readdata[21] => av_ld_byte2_data_nxt.DATAA +d_readdata[22] => av_ld_byte2_data_nxt.DATAA +d_readdata[23] => av_ld_byte2_data_nxt.DATAA +d_readdata[24] => av_ld_byte3_data_nxt.DATAA +d_readdata[25] => av_ld_byte3_data_nxt.DATAA +d_readdata[26] => av_ld_byte3_data_nxt.DATAA +d_readdata[27] => av_ld_byte3_data_nxt.DATAA +d_readdata[28] => av_ld_byte3_data_nxt.DATAA +d_readdata[29] => av_ld_byte3_data_nxt.DATAA +d_readdata[30] => av_ld_byte3_data_nxt.DATAA +d_readdata[31] => av_ld_byte3_data_nxt.DATAA +d_waitrequest => d_waitrequest.IN1 +i_readdata[0] => i_readdata[0].IN1 +i_readdata[1] => i_readdata[1].IN1 +i_readdata[2] => i_readdata[2].IN1 +i_readdata[3] => i_readdata[3].IN1 +i_readdata[4] => i_readdata[4].IN1 +i_readdata[5] => i_readdata[5].IN1 +i_readdata[6] => i_readdata[6].IN1 +i_readdata[7] => i_readdata[7].IN1 +i_readdata[8] => i_readdata[8].IN1 +i_readdata[9] => i_readdata[9].IN1 +i_readdata[10] => i_readdata[10].IN1 +i_readdata[11] => i_readdata[11].IN1 +i_readdata[12] => i_readdata[12].IN1 +i_readdata[13] => i_readdata[13].IN1 +i_readdata[14] => i_readdata[14].IN1 +i_readdata[15] => i_readdata[15].IN1 +i_readdata[16] => i_readdata[16].IN1 +i_readdata[17] => i_readdata[17].IN1 +i_readdata[18] => i_readdata[18].IN1 +i_readdata[19] => i_readdata[19].IN1 +i_readdata[20] => i_readdata[20].IN1 +i_readdata[21] => i_readdata[21].IN1 +i_readdata[22] => i_readdata[22].IN1 +i_readdata[23] => i_readdata[23].IN1 +i_readdata[24] => i_readdata[24].IN1 +i_readdata[25] => i_readdata[25].IN1 +i_readdata[26] => i_readdata[26].IN1 +i_readdata[27] => i_readdata[27].IN1 +i_readdata[28] => i_readdata[28].IN1 +i_readdata[29] => i_readdata[29].IN1 +i_readdata[30] => i_readdata[30].IN1 +i_readdata[31] => i_readdata[31].IN1 +i_waitrequest => i_waitrequest.IN1 +jtag_debug_module_address[0] => jtag_debug_module_address[0].IN1 +jtag_debug_module_address[1] => jtag_debug_module_address[1].IN1 +jtag_debug_module_address[2] => jtag_debug_module_address[2].IN1 +jtag_debug_module_address[3] => jtag_debug_module_address[3].IN1 +jtag_debug_module_address[4] => jtag_debug_module_address[4].IN1 +jtag_debug_module_address[5] => jtag_debug_module_address[5].IN1 +jtag_debug_module_address[6] => jtag_debug_module_address[6].IN1 +jtag_debug_module_address[7] => jtag_debug_module_address[7].IN1 +jtag_debug_module_address[8] => jtag_debug_module_address[8].IN1 +jtag_debug_module_byteenable[0] => jtag_debug_module_byteenable[0].IN1 +jtag_debug_module_byteenable[1] => jtag_debug_module_byteenable[1].IN1 +jtag_debug_module_byteenable[2] => jtag_debug_module_byteenable[2].IN1 +jtag_debug_module_byteenable[3] => jtag_debug_module_byteenable[3].IN1 +jtag_debug_module_debugaccess => jtag_debug_module_debugaccess.IN1 +jtag_debug_module_read => jtag_debug_module_read.IN1 +jtag_debug_module_write => jtag_debug_module_write.IN1 +jtag_debug_module_writedata[0] => jtag_debug_module_writedata[0].IN1 +jtag_debug_module_writedata[1] => jtag_debug_module_writedata[1].IN1 +jtag_debug_module_writedata[2] => jtag_debug_module_writedata[2].IN1 +jtag_debug_module_writedata[3] => jtag_debug_module_writedata[3].IN1 +jtag_debug_module_writedata[4] => jtag_debug_module_writedata[4].IN1 +jtag_debug_module_writedata[5] => jtag_debug_module_writedata[5].IN1 +jtag_debug_module_writedata[6] => jtag_debug_module_writedata[6].IN1 +jtag_debug_module_writedata[7] => jtag_debug_module_writedata[7].IN1 +jtag_debug_module_writedata[8] => jtag_debug_module_writedata[8].IN1 +jtag_debug_module_writedata[9] => jtag_debug_module_writedata[9].IN1 +jtag_debug_module_writedata[10] => jtag_debug_module_writedata[10].IN1 +jtag_debug_module_writedata[11] => jtag_debug_module_writedata[11].IN1 +jtag_debug_module_writedata[12] => jtag_debug_module_writedata[12].IN1 +jtag_debug_module_writedata[13] => jtag_debug_module_writedata[13].IN1 +jtag_debug_module_writedata[14] => jtag_debug_module_writedata[14].IN1 +jtag_debug_module_writedata[15] => jtag_debug_module_writedata[15].IN1 +jtag_debug_module_writedata[16] => jtag_debug_module_writedata[16].IN1 +jtag_debug_module_writedata[17] => jtag_debug_module_writedata[17].IN1 +jtag_debug_module_writedata[18] => jtag_debug_module_writedata[18].IN1 +jtag_debug_module_writedata[19] => jtag_debug_module_writedata[19].IN1 +jtag_debug_module_writedata[20] => jtag_debug_module_writedata[20].IN1 +jtag_debug_module_writedata[21] => jtag_debug_module_writedata[21].IN1 +jtag_debug_module_writedata[22] => jtag_debug_module_writedata[22].IN1 +jtag_debug_module_writedata[23] => jtag_debug_module_writedata[23].IN1 +jtag_debug_module_writedata[24] => jtag_debug_module_writedata[24].IN1 +jtag_debug_module_writedata[25] => jtag_debug_module_writedata[25].IN1 +jtag_debug_module_writedata[26] => jtag_debug_module_writedata[26].IN1 +jtag_debug_module_writedata[27] => jtag_debug_module_writedata[27].IN1 +jtag_debug_module_writedata[28] => jtag_debug_module_writedata[28].IN1 +jtag_debug_module_writedata[29] => jtag_debug_module_writedata[29].IN1 +jtag_debug_module_writedata[30] => jtag_debug_module_writedata[30].IN1 +jtag_debug_module_writedata[31] => jtag_debug_module_writedata[31].IN1 +reset_n => reset_n.IN2 +d_address[0] <= d_address[0].DB_MAX_OUTPUT_PORT_TYPE +d_address[1] <= d_address[1].DB_MAX_OUTPUT_PORT_TYPE +d_address[2] <= d_address[2].DB_MAX_OUTPUT_PORT_TYPE +d_address[3] <= d_address[3].DB_MAX_OUTPUT_PORT_TYPE +d_address[4] <= d_address[4].DB_MAX_OUTPUT_PORT_TYPE +d_address[5] <= d_address[5].DB_MAX_OUTPUT_PORT_TYPE +d_address[6] <= d_address[6].DB_MAX_OUTPUT_PORT_TYPE +d_address[7] <= d_address[7].DB_MAX_OUTPUT_PORT_TYPE +d_address[8] <= d_address[8].DB_MAX_OUTPUT_PORT_TYPE +d_address[9] <= d_address[9].DB_MAX_OUTPUT_PORT_TYPE +d_address[10] <= d_address[10].DB_MAX_OUTPUT_PORT_TYPE +d_address[11] <= d_address[11].DB_MAX_OUTPUT_PORT_TYPE +d_address[12] <= d_address[12].DB_MAX_OUTPUT_PORT_TYPE +d_address[13] <= d_address[13].DB_MAX_OUTPUT_PORT_TYPE +d_address[14] <= d_address[14].DB_MAX_OUTPUT_PORT_TYPE +d_address[15] <= d_address[15].DB_MAX_OUTPUT_PORT_TYPE +d_address[16] <= d_address[16].DB_MAX_OUTPUT_PORT_TYPE +d_address[17] <= d_address[17].DB_MAX_OUTPUT_PORT_TYPE +d_address[18] <= d_address[18].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[0] <= d_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[1] <= d_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[2] <= d_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[3] <= d_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +d_read <= d_read.DB_MAX_OUTPUT_PORT_TYPE +d_write <= d_write.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[0] <= d_writedata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[1] <= d_writedata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[2] <= d_writedata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[3] <= d_writedata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[4] <= d_writedata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[5] <= d_writedata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[6] <= d_writedata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[7] <= d_writedata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[8] <= d_writedata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[9] <= d_writedata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[10] <= d_writedata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[11] <= d_writedata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[12] <= d_writedata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[13] <= d_writedata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[14] <= d_writedata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[15] <= d_writedata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[16] <= d_writedata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[17] <= d_writedata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[18] <= d_writedata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[19] <= d_writedata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[20] <= d_writedata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[21] <= d_writedata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[22] <= d_writedata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[23] <= d_writedata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[24] <= d_writedata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[25] <= d_writedata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[26] <= d_writedata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[27] <= d_writedata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[28] <= d_writedata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[29] <= d_writedata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[30] <= d_writedata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[31] <= d_writedata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +i_address[0] <= i_address[0].DB_MAX_OUTPUT_PORT_TYPE +i_address[1] <= i_address[1].DB_MAX_OUTPUT_PORT_TYPE +i_address[2] <= i_address[2].DB_MAX_OUTPUT_PORT_TYPE +i_address[3] <= i_address[3].DB_MAX_OUTPUT_PORT_TYPE +i_address[4] <= i_address[4].DB_MAX_OUTPUT_PORT_TYPE +i_address[5] <= i_address[5].DB_MAX_OUTPUT_PORT_TYPE +i_address[6] <= i_address[6].DB_MAX_OUTPUT_PORT_TYPE +i_address[7] <= i_address[7].DB_MAX_OUTPUT_PORT_TYPE +i_address[8] <= i_address[8].DB_MAX_OUTPUT_PORT_TYPE +i_address[9] <= i_address[9].DB_MAX_OUTPUT_PORT_TYPE +i_address[10] <= i_address[10].DB_MAX_OUTPUT_PORT_TYPE +i_address[11] <= i_address[11].DB_MAX_OUTPUT_PORT_TYPE +i_address[12] <= i_address[12].DB_MAX_OUTPUT_PORT_TYPE +i_address[13] <= i_address[13].DB_MAX_OUTPUT_PORT_TYPE +i_address[14] <= i_address[14].DB_MAX_OUTPUT_PORT_TYPE +i_address[15] <= i_address[15].DB_MAX_OUTPUT_PORT_TYPE +i_address[16] <= i_address[16].DB_MAX_OUTPUT_PORT_TYPE +i_address[17] <= i_address[17].DB_MAX_OUTPUT_PORT_TYPE +i_address[18] <= i_address[18].DB_MAX_OUTPUT_PORT_TYPE +i_read <= i_read.DB_MAX_OUTPUT_PORT_TYPE +jtag_debug_module_debugaccess_to_roms <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.jtag_debug_module_debugaccess_to_roms +jtag_debug_module_readdata[0] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[1] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[2] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[3] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[4] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[5] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[6] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[7] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[8] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[9] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[10] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[11] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[12] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[13] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[14] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[15] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[16] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[17] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[18] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[19] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[20] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[21] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[22] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[23] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[24] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[25] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[26] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[27] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[28] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[29] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[30] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_readdata[31] <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.readdata +jtag_debug_module_resetrequest <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.resetrequest +jtag_debug_module_waitrequest <= nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci.waitrequest +no_ci_readra <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench +D_iw[0] => ~NO_FANOUT~ +D_iw[1] => ~NO_FANOUT~ +D_iw[2] => ~NO_FANOUT~ +D_iw[3] => ~NO_FANOUT~ +D_iw[4] => ~NO_FANOUT~ +D_iw[5] => ~NO_FANOUT~ +D_iw[6] => ~NO_FANOUT~ +D_iw[7] => ~NO_FANOUT~ +D_iw[8] => ~NO_FANOUT~ +D_iw[9] => ~NO_FANOUT~ +D_iw[10] => ~NO_FANOUT~ +D_iw[11] => ~NO_FANOUT~ +D_iw[12] => ~NO_FANOUT~ +D_iw[13] => ~NO_FANOUT~ +D_iw[14] => ~NO_FANOUT~ +D_iw[15] => ~NO_FANOUT~ +D_iw[16] => ~NO_FANOUT~ +D_iw[17] => ~NO_FANOUT~ +D_iw[18] => ~NO_FANOUT~ +D_iw[19] => ~NO_FANOUT~ +D_iw[20] => ~NO_FANOUT~ +D_iw[21] => ~NO_FANOUT~ +D_iw[22] => ~NO_FANOUT~ +D_iw[23] => ~NO_FANOUT~ +D_iw[24] => ~NO_FANOUT~ +D_iw[25] => ~NO_FANOUT~ +D_iw[26] => ~NO_FANOUT~ +D_iw[27] => ~NO_FANOUT~ +D_iw[28] => ~NO_FANOUT~ +D_iw[29] => ~NO_FANOUT~ +D_iw[30] => ~NO_FANOUT~ +D_iw[31] => ~NO_FANOUT~ +D_iw_op[0] => ~NO_FANOUT~ +D_iw_op[1] => ~NO_FANOUT~ +D_iw_op[2] => ~NO_FANOUT~ +D_iw_op[3] => ~NO_FANOUT~ +D_iw_op[4] => ~NO_FANOUT~ +D_iw_op[5] => ~NO_FANOUT~ +D_iw_opx[0] => ~NO_FANOUT~ +D_iw_opx[1] => ~NO_FANOUT~ +D_iw_opx[2] => ~NO_FANOUT~ +D_iw_opx[3] => ~NO_FANOUT~ +D_iw_opx[4] => ~NO_FANOUT~ +D_iw_opx[5] => ~NO_FANOUT~ +D_valid => ~NO_FANOUT~ +E_valid => ~NO_FANOUT~ +F_pcb[0] => ~NO_FANOUT~ +F_pcb[1] => ~NO_FANOUT~ +F_pcb[2] => ~NO_FANOUT~ +F_pcb[3] => ~NO_FANOUT~ +F_pcb[4] => ~NO_FANOUT~ +F_pcb[5] => ~NO_FANOUT~ +F_pcb[6] => ~NO_FANOUT~ +F_pcb[7] => ~NO_FANOUT~ +F_pcb[8] => ~NO_FANOUT~ +F_pcb[9] => ~NO_FANOUT~ +F_pcb[10] => ~NO_FANOUT~ +F_pcb[11] => ~NO_FANOUT~ +F_pcb[12] => ~NO_FANOUT~ +F_pcb[13] => ~NO_FANOUT~ +F_pcb[14] => ~NO_FANOUT~ +F_pcb[15] => ~NO_FANOUT~ +F_pcb[16] => ~NO_FANOUT~ +F_pcb[17] => ~NO_FANOUT~ +F_pcb[18] => ~NO_FANOUT~ +F_valid => ~NO_FANOUT~ +R_ctrl_ld => ~NO_FANOUT~ +R_ctrl_ld_non_io => ~NO_FANOUT~ +R_dst_regnum[0] => ~NO_FANOUT~ +R_dst_regnum[1] => ~NO_FANOUT~ +R_dst_regnum[2] => ~NO_FANOUT~ +R_dst_regnum[3] => ~NO_FANOUT~ +R_dst_regnum[4] => ~NO_FANOUT~ +R_wr_dst_reg => ~NO_FANOUT~ +W_valid => ~NO_FANOUT~ +W_vinst[0] => ~NO_FANOUT~ +W_vinst[1] => ~NO_FANOUT~ +W_vinst[2] => ~NO_FANOUT~ +W_vinst[3] => ~NO_FANOUT~ +W_vinst[4] => ~NO_FANOUT~ +W_vinst[5] => ~NO_FANOUT~ +W_vinst[6] => ~NO_FANOUT~ +W_vinst[7] => ~NO_FANOUT~ +W_vinst[8] => ~NO_FANOUT~ +W_vinst[9] => ~NO_FANOUT~ +W_vinst[10] => ~NO_FANOUT~ +W_vinst[11] => ~NO_FANOUT~ +W_vinst[12] => ~NO_FANOUT~ +W_vinst[13] => ~NO_FANOUT~ +W_vinst[14] => ~NO_FANOUT~ +W_vinst[15] => ~NO_FANOUT~ +W_vinst[16] => ~NO_FANOUT~ +W_vinst[17] => ~NO_FANOUT~ +W_vinst[18] => ~NO_FANOUT~ +W_vinst[19] => ~NO_FANOUT~ +W_vinst[20] => ~NO_FANOUT~ +W_vinst[21] => ~NO_FANOUT~ +W_vinst[22] => ~NO_FANOUT~ +W_vinst[23] => ~NO_FANOUT~ +W_vinst[24] => ~NO_FANOUT~ +W_vinst[25] => ~NO_FANOUT~ +W_vinst[26] => ~NO_FANOUT~ +W_vinst[27] => ~NO_FANOUT~ +W_vinst[28] => ~NO_FANOUT~ +W_vinst[29] => ~NO_FANOUT~ +W_vinst[30] => ~NO_FANOUT~ +W_vinst[31] => ~NO_FANOUT~ +W_vinst[32] => ~NO_FANOUT~ +W_vinst[33] => ~NO_FANOUT~ +W_vinst[34] => ~NO_FANOUT~ +W_vinst[35] => ~NO_FANOUT~ +W_vinst[36] => ~NO_FANOUT~ +W_vinst[37] => ~NO_FANOUT~ +W_vinst[38] => ~NO_FANOUT~ +W_vinst[39] => ~NO_FANOUT~ +W_vinst[40] => ~NO_FANOUT~ +W_vinst[41] => ~NO_FANOUT~ +W_vinst[42] => ~NO_FANOUT~ +W_vinst[43] => ~NO_FANOUT~ +W_vinst[44] => ~NO_FANOUT~ +W_vinst[45] => ~NO_FANOUT~ +W_vinst[46] => ~NO_FANOUT~ +W_vinst[47] => ~NO_FANOUT~ +W_vinst[48] => ~NO_FANOUT~ +W_vinst[49] => ~NO_FANOUT~ +W_vinst[50] => ~NO_FANOUT~ +W_vinst[51] => ~NO_FANOUT~ +W_vinst[52] => ~NO_FANOUT~ +W_vinst[53] => ~NO_FANOUT~ +W_vinst[54] => ~NO_FANOUT~ +W_vinst[55] => ~NO_FANOUT~ +W_wr_data[0] => ~NO_FANOUT~ +W_wr_data[1] => ~NO_FANOUT~ +W_wr_data[2] => ~NO_FANOUT~ +W_wr_data[3] => ~NO_FANOUT~ +W_wr_data[4] => ~NO_FANOUT~ +W_wr_data[5] => ~NO_FANOUT~ +W_wr_data[6] => ~NO_FANOUT~ +W_wr_data[7] => ~NO_FANOUT~ +W_wr_data[8] => ~NO_FANOUT~ +W_wr_data[9] => ~NO_FANOUT~ +W_wr_data[10] => ~NO_FANOUT~ +W_wr_data[11] => ~NO_FANOUT~ +W_wr_data[12] => ~NO_FANOUT~ +W_wr_data[13] => ~NO_FANOUT~ +W_wr_data[14] => ~NO_FANOUT~ +W_wr_data[15] => ~NO_FANOUT~ +W_wr_data[16] => ~NO_FANOUT~ +W_wr_data[17] => ~NO_FANOUT~ +W_wr_data[18] => ~NO_FANOUT~ +W_wr_data[19] => ~NO_FANOUT~ +W_wr_data[20] => ~NO_FANOUT~ +W_wr_data[21] => ~NO_FANOUT~ +W_wr_data[22] => ~NO_FANOUT~ +W_wr_data[23] => ~NO_FANOUT~ +W_wr_data[24] => ~NO_FANOUT~ +W_wr_data[25] => ~NO_FANOUT~ +W_wr_data[26] => ~NO_FANOUT~ +W_wr_data[27] => ~NO_FANOUT~ +W_wr_data[28] => ~NO_FANOUT~ +W_wr_data[29] => ~NO_FANOUT~ +W_wr_data[30] => ~NO_FANOUT~ +W_wr_data[31] => ~NO_FANOUT~ +av_ld_data_aligned_unfiltered[0] => av_ld_data_aligned_filtered[0].DATAIN +av_ld_data_aligned_unfiltered[1] => av_ld_data_aligned_filtered[1].DATAIN +av_ld_data_aligned_unfiltered[2] => av_ld_data_aligned_filtered[2].DATAIN +av_ld_data_aligned_unfiltered[3] => av_ld_data_aligned_filtered[3].DATAIN +av_ld_data_aligned_unfiltered[4] => av_ld_data_aligned_filtered[4].DATAIN +av_ld_data_aligned_unfiltered[5] => av_ld_data_aligned_filtered[5].DATAIN +av_ld_data_aligned_unfiltered[6] => av_ld_data_aligned_filtered[6].DATAIN +av_ld_data_aligned_unfiltered[7] => av_ld_data_aligned_filtered[7].DATAIN +av_ld_data_aligned_unfiltered[8] => av_ld_data_aligned_filtered[8].DATAIN +av_ld_data_aligned_unfiltered[9] => av_ld_data_aligned_filtered[9].DATAIN +av_ld_data_aligned_unfiltered[10] => av_ld_data_aligned_filtered[10].DATAIN +av_ld_data_aligned_unfiltered[11] => av_ld_data_aligned_filtered[11].DATAIN +av_ld_data_aligned_unfiltered[12] => av_ld_data_aligned_filtered[12].DATAIN +av_ld_data_aligned_unfiltered[13] => av_ld_data_aligned_filtered[13].DATAIN +av_ld_data_aligned_unfiltered[14] => av_ld_data_aligned_filtered[14].DATAIN +av_ld_data_aligned_unfiltered[15] => av_ld_data_aligned_filtered[15].DATAIN +av_ld_data_aligned_unfiltered[16] => av_ld_data_aligned_filtered[16].DATAIN +av_ld_data_aligned_unfiltered[17] => av_ld_data_aligned_filtered[17].DATAIN +av_ld_data_aligned_unfiltered[18] => av_ld_data_aligned_filtered[18].DATAIN +av_ld_data_aligned_unfiltered[19] => av_ld_data_aligned_filtered[19].DATAIN +av_ld_data_aligned_unfiltered[20] => av_ld_data_aligned_filtered[20].DATAIN +av_ld_data_aligned_unfiltered[21] => av_ld_data_aligned_filtered[21].DATAIN +av_ld_data_aligned_unfiltered[22] => av_ld_data_aligned_filtered[22].DATAIN +av_ld_data_aligned_unfiltered[23] => av_ld_data_aligned_filtered[23].DATAIN +av_ld_data_aligned_unfiltered[24] => av_ld_data_aligned_filtered[24].DATAIN +av_ld_data_aligned_unfiltered[25] => av_ld_data_aligned_filtered[25].DATAIN +av_ld_data_aligned_unfiltered[26] => av_ld_data_aligned_filtered[26].DATAIN +av_ld_data_aligned_unfiltered[27] => av_ld_data_aligned_filtered[27].DATAIN +av_ld_data_aligned_unfiltered[28] => av_ld_data_aligned_filtered[28].DATAIN +av_ld_data_aligned_unfiltered[29] => av_ld_data_aligned_filtered[29].DATAIN +av_ld_data_aligned_unfiltered[30] => av_ld_data_aligned_filtered[30].DATAIN +av_ld_data_aligned_unfiltered[31] => av_ld_data_aligned_filtered[31].DATAIN +clk => d_write~reg0.CLK +d_address[0] => ~NO_FANOUT~ +d_address[1] => ~NO_FANOUT~ +d_address[2] => ~NO_FANOUT~ +d_address[3] => ~NO_FANOUT~ +d_address[4] => ~NO_FANOUT~ +d_address[5] => ~NO_FANOUT~ +d_address[6] => ~NO_FANOUT~ +d_address[7] => ~NO_FANOUT~ +d_address[8] => ~NO_FANOUT~ +d_address[9] => ~NO_FANOUT~ +d_address[10] => ~NO_FANOUT~ +d_address[11] => ~NO_FANOUT~ +d_address[12] => ~NO_FANOUT~ +d_address[13] => ~NO_FANOUT~ +d_address[14] => ~NO_FANOUT~ +d_address[15] => ~NO_FANOUT~ +d_address[16] => ~NO_FANOUT~ +d_address[17] => ~NO_FANOUT~ +d_address[18] => ~NO_FANOUT~ +d_byteenable[0] => ~NO_FANOUT~ +d_byteenable[1] => ~NO_FANOUT~ +d_byteenable[2] => ~NO_FANOUT~ +d_byteenable[3] => ~NO_FANOUT~ +d_read => ~NO_FANOUT~ +d_write_nxt => d_write~reg0.DATAIN +i_address[0] => ~NO_FANOUT~ +i_address[1] => ~NO_FANOUT~ +i_address[2] => ~NO_FANOUT~ +i_address[3] => ~NO_FANOUT~ +i_address[4] => ~NO_FANOUT~ +i_address[5] => ~NO_FANOUT~ +i_address[6] => ~NO_FANOUT~ +i_address[7] => ~NO_FANOUT~ +i_address[8] => ~NO_FANOUT~ +i_address[9] => ~NO_FANOUT~ +i_address[10] => ~NO_FANOUT~ +i_address[11] => ~NO_FANOUT~ +i_address[12] => ~NO_FANOUT~ +i_address[13] => ~NO_FANOUT~ +i_address[14] => ~NO_FANOUT~ +i_address[15] => ~NO_FANOUT~ +i_address[16] => ~NO_FANOUT~ +i_address[17] => ~NO_FANOUT~ +i_address[18] => ~NO_FANOUT~ +i_read => ~NO_FANOUT~ +i_readdata[0] => ~NO_FANOUT~ +i_readdata[1] => ~NO_FANOUT~ +i_readdata[2] => ~NO_FANOUT~ +i_readdata[3] => ~NO_FANOUT~ +i_readdata[4] => ~NO_FANOUT~ +i_readdata[5] => ~NO_FANOUT~ +i_readdata[6] => ~NO_FANOUT~ +i_readdata[7] => ~NO_FANOUT~ +i_readdata[8] => ~NO_FANOUT~ +i_readdata[9] => ~NO_FANOUT~ +i_readdata[10] => ~NO_FANOUT~ +i_readdata[11] => ~NO_FANOUT~ +i_readdata[12] => ~NO_FANOUT~ +i_readdata[13] => ~NO_FANOUT~ +i_readdata[14] => ~NO_FANOUT~ +i_readdata[15] => ~NO_FANOUT~ +i_readdata[16] => ~NO_FANOUT~ +i_readdata[17] => ~NO_FANOUT~ +i_readdata[18] => ~NO_FANOUT~ +i_readdata[19] => ~NO_FANOUT~ +i_readdata[20] => ~NO_FANOUT~ +i_readdata[21] => ~NO_FANOUT~ +i_readdata[22] => ~NO_FANOUT~ +i_readdata[23] => ~NO_FANOUT~ +i_readdata[24] => ~NO_FANOUT~ +i_readdata[25] => ~NO_FANOUT~ +i_readdata[26] => ~NO_FANOUT~ +i_readdata[27] => ~NO_FANOUT~ +i_readdata[28] => ~NO_FANOUT~ +i_readdata[29] => ~NO_FANOUT~ +i_readdata[30] => ~NO_FANOUT~ +i_readdata[31] => ~NO_FANOUT~ +i_waitrequest => ~NO_FANOUT~ +reset_n => d_write~reg0.ACLR +av_ld_data_aligned_filtered[0] <= av_ld_data_aligned_unfiltered[0].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[1] <= av_ld_data_aligned_unfiltered[1].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[2] <= av_ld_data_aligned_unfiltered[2].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[3] <= av_ld_data_aligned_unfiltered[3].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[4] <= av_ld_data_aligned_unfiltered[4].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[5] <= av_ld_data_aligned_unfiltered[5].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[6] <= av_ld_data_aligned_unfiltered[6].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[7] <= av_ld_data_aligned_unfiltered[7].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[8] <= av_ld_data_aligned_unfiltered[8].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[9] <= av_ld_data_aligned_unfiltered[9].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[10] <= av_ld_data_aligned_unfiltered[10].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[11] <= av_ld_data_aligned_unfiltered[11].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[12] <= av_ld_data_aligned_unfiltered[12].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[13] <= av_ld_data_aligned_unfiltered[13].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[14] <= av_ld_data_aligned_unfiltered[14].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[15] <= av_ld_data_aligned_unfiltered[15].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[16] <= av_ld_data_aligned_unfiltered[16].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[17] <= av_ld_data_aligned_unfiltered[17].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[18] <= av_ld_data_aligned_unfiltered[18].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[19] <= av_ld_data_aligned_unfiltered[19].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[20] <= av_ld_data_aligned_unfiltered[20].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[21] <= av_ld_data_aligned_unfiltered[21].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[22] <= av_ld_data_aligned_unfiltered[22].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[23] <= av_ld_data_aligned_unfiltered[23].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[24] <= av_ld_data_aligned_unfiltered[24].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[25] <= av_ld_data_aligned_unfiltered[25].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[26] <= av_ld_data_aligned_unfiltered[26].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[27] <= av_ld_data_aligned_unfiltered[27].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[28] <= av_ld_data_aligned_unfiltered[28].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[29] <= av_ld_data_aligned_unfiltered[29].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[30] <= av_ld_data_aligned_unfiltered[30].DB_MAX_OUTPUT_PORT_TYPE +av_ld_data_aligned_filtered[31] <= av_ld_data_aligned_unfiltered[31].DB_MAX_OUTPUT_PORT_TYPE +d_write <= d_write~reg0.DB_MAX_OUTPUT_PORT_TYPE +test_has_ended <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b +q[21] <= altsyncram:the_altsyncram.q_b +q[22] <= altsyncram:the_altsyncram.q_b +q[23] <= altsyncram:the_altsyncram.q_b +q[24] <= altsyncram:the_altsyncram.q_b +q[25] <= altsyncram:the_altsyncram.q_b +q[26] <= altsyncram:the_altsyncram.q_b +q[27] <= altsyncram:the_altsyncram.q_b +q[28] <= altsyncram:the_altsyncram.q_b +q[29] <= altsyncram:the_altsyncram.q_b +q[30] <= altsyncram:the_altsyncram.q_b +q[31] <= altsyncram:the_altsyncram.q_b + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram +wren_a => altsyncram_0rh1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_0rh1:auto_generated.data_a[0] +data_a[1] => altsyncram_0rh1:auto_generated.data_a[1] +data_a[2] => altsyncram_0rh1:auto_generated.data_a[2] +data_a[3] => altsyncram_0rh1:auto_generated.data_a[3] +data_a[4] => altsyncram_0rh1:auto_generated.data_a[4] +data_a[5] => altsyncram_0rh1:auto_generated.data_a[5] +data_a[6] => altsyncram_0rh1:auto_generated.data_a[6] +data_a[7] => altsyncram_0rh1:auto_generated.data_a[7] +data_a[8] => altsyncram_0rh1:auto_generated.data_a[8] +data_a[9] => altsyncram_0rh1:auto_generated.data_a[9] +data_a[10] => altsyncram_0rh1:auto_generated.data_a[10] +data_a[11] => altsyncram_0rh1:auto_generated.data_a[11] +data_a[12] => altsyncram_0rh1:auto_generated.data_a[12] +data_a[13] => altsyncram_0rh1:auto_generated.data_a[13] +data_a[14] => altsyncram_0rh1:auto_generated.data_a[14] +data_a[15] => altsyncram_0rh1:auto_generated.data_a[15] +data_a[16] => altsyncram_0rh1:auto_generated.data_a[16] +data_a[17] => altsyncram_0rh1:auto_generated.data_a[17] +data_a[18] => altsyncram_0rh1:auto_generated.data_a[18] +data_a[19] => altsyncram_0rh1:auto_generated.data_a[19] +data_a[20] => altsyncram_0rh1:auto_generated.data_a[20] +data_a[21] => altsyncram_0rh1:auto_generated.data_a[21] +data_a[22] => altsyncram_0rh1:auto_generated.data_a[22] +data_a[23] => altsyncram_0rh1:auto_generated.data_a[23] +data_a[24] => altsyncram_0rh1:auto_generated.data_a[24] +data_a[25] => altsyncram_0rh1:auto_generated.data_a[25] +data_a[26] => altsyncram_0rh1:auto_generated.data_a[26] +data_a[27] => altsyncram_0rh1:auto_generated.data_a[27] +data_a[28] => altsyncram_0rh1:auto_generated.data_a[28] +data_a[29] => altsyncram_0rh1:auto_generated.data_a[29] +data_a[30] => altsyncram_0rh1:auto_generated.data_a[30] +data_a[31] => altsyncram_0rh1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +data_b[21] => ~NO_FANOUT~ +data_b[22] => ~NO_FANOUT~ +data_b[23] => ~NO_FANOUT~ +data_b[24] => ~NO_FANOUT~ +data_b[25] => ~NO_FANOUT~ +data_b[26] => ~NO_FANOUT~ +data_b[27] => ~NO_FANOUT~ +data_b[28] => ~NO_FANOUT~ +data_b[29] => ~NO_FANOUT~ +data_b[30] => ~NO_FANOUT~ +data_b[31] => ~NO_FANOUT~ +address_a[0] => altsyncram_0rh1:auto_generated.address_a[0] +address_a[1] => altsyncram_0rh1:auto_generated.address_a[1] +address_a[2] => altsyncram_0rh1:auto_generated.address_a[2] +address_a[3] => altsyncram_0rh1:auto_generated.address_a[3] +address_a[4] => altsyncram_0rh1:auto_generated.address_a[4] +address_b[0] => altsyncram_0rh1:auto_generated.address_b[0] +address_b[1] => altsyncram_0rh1:auto_generated.address_b[1] +address_b[2] => altsyncram_0rh1:auto_generated.address_b[2] +address_b[3] => altsyncram_0rh1:auto_generated.address_b[3] +address_b[4] => altsyncram_0rh1:auto_generated.address_b[4] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_0rh1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_a[21] <= +q_a[22] <= +q_a[23] <= +q_a[24] <= +q_a[25] <= +q_a[26] <= +q_a[27] <= +q_a[28] <= +q_a[29] <= +q_a[30] <= +q_a[31] <= +q_b[0] <= altsyncram_0rh1:auto_generated.q_b[0] +q_b[1] <= altsyncram_0rh1:auto_generated.q_b[1] +q_b[2] <= altsyncram_0rh1:auto_generated.q_b[2] +q_b[3] <= altsyncram_0rh1:auto_generated.q_b[3] +q_b[4] <= altsyncram_0rh1:auto_generated.q_b[4] +q_b[5] <= altsyncram_0rh1:auto_generated.q_b[5] +q_b[6] <= altsyncram_0rh1:auto_generated.q_b[6] +q_b[7] <= altsyncram_0rh1:auto_generated.q_b[7] +q_b[8] <= altsyncram_0rh1:auto_generated.q_b[8] +q_b[9] <= altsyncram_0rh1:auto_generated.q_b[9] +q_b[10] <= altsyncram_0rh1:auto_generated.q_b[10] +q_b[11] <= altsyncram_0rh1:auto_generated.q_b[11] +q_b[12] <= altsyncram_0rh1:auto_generated.q_b[12] +q_b[13] <= altsyncram_0rh1:auto_generated.q_b[13] +q_b[14] <= altsyncram_0rh1:auto_generated.q_b[14] +q_b[15] <= altsyncram_0rh1:auto_generated.q_b[15] +q_b[16] <= altsyncram_0rh1:auto_generated.q_b[16] +q_b[17] <= altsyncram_0rh1:auto_generated.q_b[17] +q_b[18] <= altsyncram_0rh1:auto_generated.q_b[18] +q_b[19] <= altsyncram_0rh1:auto_generated.q_b[19] +q_b[20] <= altsyncram_0rh1:auto_generated.q_b[20] +q_b[21] <= altsyncram_0rh1:auto_generated.q_b[21] +q_b[22] <= altsyncram_0rh1:auto_generated.q_b[22] +q_b[23] <= altsyncram_0rh1:auto_generated.q_b[23] +q_b[24] <= altsyncram_0rh1:auto_generated.q_b[24] +q_b[25] <= altsyncram_0rh1:auto_generated.q_b[25] +q_b[26] <= altsyncram_0rh1:auto_generated.q_b[26] +q_b[27] <= altsyncram_0rh1:auto_generated.q_b[27] +q_b[28] <= altsyncram_0rh1:auto_generated.q_b[28] +q_b[29] <= altsyncram_0rh1:auto_generated.q_b[29] +q_b[30] <= altsyncram_0rh1:auto_generated.q_b[30] +q_b[31] <= altsyncram_0rh1:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b +q[21] <= altsyncram:the_altsyncram.q_b +q[22] <= altsyncram:the_altsyncram.q_b +q[23] <= altsyncram:the_altsyncram.q_b +q[24] <= altsyncram:the_altsyncram.q_b +q[25] <= altsyncram:the_altsyncram.q_b +q[26] <= altsyncram:the_altsyncram.q_b +q[27] <= altsyncram:the_altsyncram.q_b +q[28] <= altsyncram:the_altsyncram.q_b +q[29] <= altsyncram:the_altsyncram.q_b +q[30] <= altsyncram:the_altsyncram.q_b +q[31] <= altsyncram:the_altsyncram.q_b + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram +wren_a => altsyncram_1rh1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_1rh1:auto_generated.data_a[0] +data_a[1] => altsyncram_1rh1:auto_generated.data_a[1] +data_a[2] => altsyncram_1rh1:auto_generated.data_a[2] +data_a[3] => altsyncram_1rh1:auto_generated.data_a[3] +data_a[4] => altsyncram_1rh1:auto_generated.data_a[4] +data_a[5] => altsyncram_1rh1:auto_generated.data_a[5] +data_a[6] => altsyncram_1rh1:auto_generated.data_a[6] +data_a[7] => altsyncram_1rh1:auto_generated.data_a[7] +data_a[8] => altsyncram_1rh1:auto_generated.data_a[8] +data_a[9] => altsyncram_1rh1:auto_generated.data_a[9] +data_a[10] => altsyncram_1rh1:auto_generated.data_a[10] +data_a[11] => altsyncram_1rh1:auto_generated.data_a[11] +data_a[12] => altsyncram_1rh1:auto_generated.data_a[12] +data_a[13] => altsyncram_1rh1:auto_generated.data_a[13] +data_a[14] => altsyncram_1rh1:auto_generated.data_a[14] +data_a[15] => altsyncram_1rh1:auto_generated.data_a[15] +data_a[16] => altsyncram_1rh1:auto_generated.data_a[16] +data_a[17] => altsyncram_1rh1:auto_generated.data_a[17] +data_a[18] => altsyncram_1rh1:auto_generated.data_a[18] +data_a[19] => altsyncram_1rh1:auto_generated.data_a[19] +data_a[20] => altsyncram_1rh1:auto_generated.data_a[20] +data_a[21] => altsyncram_1rh1:auto_generated.data_a[21] +data_a[22] => altsyncram_1rh1:auto_generated.data_a[22] +data_a[23] => altsyncram_1rh1:auto_generated.data_a[23] +data_a[24] => altsyncram_1rh1:auto_generated.data_a[24] +data_a[25] => altsyncram_1rh1:auto_generated.data_a[25] +data_a[26] => altsyncram_1rh1:auto_generated.data_a[26] +data_a[27] => altsyncram_1rh1:auto_generated.data_a[27] +data_a[28] => altsyncram_1rh1:auto_generated.data_a[28] +data_a[29] => altsyncram_1rh1:auto_generated.data_a[29] +data_a[30] => altsyncram_1rh1:auto_generated.data_a[30] +data_a[31] => altsyncram_1rh1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +data_b[21] => ~NO_FANOUT~ +data_b[22] => ~NO_FANOUT~ +data_b[23] => ~NO_FANOUT~ +data_b[24] => ~NO_FANOUT~ +data_b[25] => ~NO_FANOUT~ +data_b[26] => ~NO_FANOUT~ +data_b[27] => ~NO_FANOUT~ +data_b[28] => ~NO_FANOUT~ +data_b[29] => ~NO_FANOUT~ +data_b[30] => ~NO_FANOUT~ +data_b[31] => ~NO_FANOUT~ +address_a[0] => altsyncram_1rh1:auto_generated.address_a[0] +address_a[1] => altsyncram_1rh1:auto_generated.address_a[1] +address_a[2] => altsyncram_1rh1:auto_generated.address_a[2] +address_a[3] => altsyncram_1rh1:auto_generated.address_a[3] +address_a[4] => altsyncram_1rh1:auto_generated.address_a[4] +address_b[0] => altsyncram_1rh1:auto_generated.address_b[0] +address_b[1] => altsyncram_1rh1:auto_generated.address_b[1] +address_b[2] => altsyncram_1rh1:auto_generated.address_b[2] +address_b[3] => altsyncram_1rh1:auto_generated.address_b[3] +address_b[4] => altsyncram_1rh1:auto_generated.address_b[4] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_1rh1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_a[21] <= +q_a[22] <= +q_a[23] <= +q_a[24] <= +q_a[25] <= +q_a[26] <= +q_a[27] <= +q_a[28] <= +q_a[29] <= +q_a[30] <= +q_a[31] <= +q_b[0] <= altsyncram_1rh1:auto_generated.q_b[0] +q_b[1] <= altsyncram_1rh1:auto_generated.q_b[1] +q_b[2] <= altsyncram_1rh1:auto_generated.q_b[2] +q_b[3] <= altsyncram_1rh1:auto_generated.q_b[3] +q_b[4] <= altsyncram_1rh1:auto_generated.q_b[4] +q_b[5] <= altsyncram_1rh1:auto_generated.q_b[5] +q_b[6] <= altsyncram_1rh1:auto_generated.q_b[6] +q_b[7] <= altsyncram_1rh1:auto_generated.q_b[7] +q_b[8] <= altsyncram_1rh1:auto_generated.q_b[8] +q_b[9] <= altsyncram_1rh1:auto_generated.q_b[9] +q_b[10] <= altsyncram_1rh1:auto_generated.q_b[10] +q_b[11] <= altsyncram_1rh1:auto_generated.q_b[11] +q_b[12] <= altsyncram_1rh1:auto_generated.q_b[12] +q_b[13] <= altsyncram_1rh1:auto_generated.q_b[13] +q_b[14] <= altsyncram_1rh1:auto_generated.q_b[14] +q_b[15] <= altsyncram_1rh1:auto_generated.q_b[15] +q_b[16] <= altsyncram_1rh1:auto_generated.q_b[16] +q_b[17] <= altsyncram_1rh1:auto_generated.q_b[17] +q_b[18] <= altsyncram_1rh1:auto_generated.q_b[18] +q_b[19] <= altsyncram_1rh1:auto_generated.q_b[19] +q_b[20] <= altsyncram_1rh1:auto_generated.q_b[20] +q_b[21] <= altsyncram_1rh1:auto_generated.q_b[21] +q_b[22] <= altsyncram_1rh1:auto_generated.q_b[22] +q_b[23] <= altsyncram_1rh1:auto_generated.q_b[23] +q_b[24] <= altsyncram_1rh1:auto_generated.q_b[24] +q_b[25] <= altsyncram_1rh1:auto_generated.q_b[25] +q_b[26] <= altsyncram_1rh1:auto_generated.q_b[26] +q_b[27] <= altsyncram_1rh1:auto_generated.q_b[27] +q_b[28] <= altsyncram_1rh1:auto_generated.q_b[28] +q_b[29] <= altsyncram_1rh1:auto_generated.q_b[29] +q_b[30] <= altsyncram_1rh1:auto_generated.q_b[30] +q_b[31] <= altsyncram_1rh1:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci +D_valid => D_valid.IN1 +E_st_data[0] => E_st_data[0].IN1 +E_st_data[1] => E_st_data[1].IN1 +E_st_data[2] => E_st_data[2].IN1 +E_st_data[3] => E_st_data[3].IN1 +E_st_data[4] => E_st_data[4].IN1 +E_st_data[5] => E_st_data[5].IN1 +E_st_data[6] => E_st_data[6].IN1 +E_st_data[7] => E_st_data[7].IN1 +E_st_data[8] => E_st_data[8].IN1 +E_st_data[9] => E_st_data[9].IN1 +E_st_data[10] => E_st_data[10].IN1 +E_st_data[11] => E_st_data[11].IN1 +E_st_data[12] => E_st_data[12].IN1 +E_st_data[13] => E_st_data[13].IN1 +E_st_data[14] => E_st_data[14].IN1 +E_st_data[15] => E_st_data[15].IN1 +E_st_data[16] => E_st_data[16].IN1 +E_st_data[17] => E_st_data[17].IN1 +E_st_data[18] => E_st_data[18].IN1 +E_st_data[19] => E_st_data[19].IN1 +E_st_data[20] => E_st_data[20].IN1 +E_st_data[21] => E_st_data[21].IN1 +E_st_data[22] => E_st_data[22].IN1 +E_st_data[23] => E_st_data[23].IN1 +E_st_data[24] => E_st_data[24].IN1 +E_st_data[25] => E_st_data[25].IN1 +E_st_data[26] => E_st_data[26].IN1 +E_st_data[27] => E_st_data[27].IN1 +E_st_data[28] => E_st_data[28].IN1 +E_st_data[29] => E_st_data[29].IN1 +E_st_data[30] => E_st_data[30].IN1 +E_st_data[31] => E_st_data[31].IN1 +E_valid => E_valid.IN1 +F_pc[0] => F_pc[0].IN1 +F_pc[1] => F_pc[1].IN1 +F_pc[2] => F_pc[2].IN1 +F_pc[3] => F_pc[3].IN1 +F_pc[4] => F_pc[4].IN1 +F_pc[5] => F_pc[5].IN1 +F_pc[6] => F_pc[6].IN1 +F_pc[7] => F_pc[7].IN1 +F_pc[8] => F_pc[8].IN1 +F_pc[9] => F_pc[9].IN1 +F_pc[10] => F_pc[10].IN1 +F_pc[11] => F_pc[11].IN1 +F_pc[12] => F_pc[12].IN1 +F_pc[13] => F_pc[13].IN1 +F_pc[14] => F_pc[14].IN1 +F_pc[15] => F_pc[15].IN1 +F_pc[16] => F_pc[16].IN1 +address_nxt[0] => address[0].DATAIN +address_nxt[1] => address[1].DATAIN +address_nxt[2] => address[2].DATAIN +address_nxt[3] => address[3].DATAIN +address_nxt[4] => address[4].DATAIN +address_nxt[5] => address[5].DATAIN +address_nxt[6] => address[6].DATAIN +address_nxt[7] => address[7].DATAIN +address_nxt[8] => address[8].DATAIN +av_ld_data_aligned_filtered[0] => av_ld_data_aligned_filtered[0].IN1 +av_ld_data_aligned_filtered[1] => av_ld_data_aligned_filtered[1].IN1 +av_ld_data_aligned_filtered[2] => av_ld_data_aligned_filtered[2].IN1 +av_ld_data_aligned_filtered[3] => av_ld_data_aligned_filtered[3].IN1 +av_ld_data_aligned_filtered[4] => av_ld_data_aligned_filtered[4].IN1 +av_ld_data_aligned_filtered[5] => av_ld_data_aligned_filtered[5].IN1 +av_ld_data_aligned_filtered[6] => av_ld_data_aligned_filtered[6].IN1 +av_ld_data_aligned_filtered[7] => av_ld_data_aligned_filtered[7].IN1 +av_ld_data_aligned_filtered[8] => av_ld_data_aligned_filtered[8].IN1 +av_ld_data_aligned_filtered[9] => av_ld_data_aligned_filtered[9].IN1 +av_ld_data_aligned_filtered[10] => av_ld_data_aligned_filtered[10].IN1 +av_ld_data_aligned_filtered[11] => av_ld_data_aligned_filtered[11].IN1 +av_ld_data_aligned_filtered[12] => av_ld_data_aligned_filtered[12].IN1 +av_ld_data_aligned_filtered[13] => av_ld_data_aligned_filtered[13].IN1 +av_ld_data_aligned_filtered[14] => av_ld_data_aligned_filtered[14].IN1 +av_ld_data_aligned_filtered[15] => av_ld_data_aligned_filtered[15].IN1 +av_ld_data_aligned_filtered[16] => av_ld_data_aligned_filtered[16].IN1 +av_ld_data_aligned_filtered[17] => av_ld_data_aligned_filtered[17].IN1 +av_ld_data_aligned_filtered[18] => av_ld_data_aligned_filtered[18].IN1 +av_ld_data_aligned_filtered[19] => av_ld_data_aligned_filtered[19].IN1 +av_ld_data_aligned_filtered[20] => av_ld_data_aligned_filtered[20].IN1 +av_ld_data_aligned_filtered[21] => av_ld_data_aligned_filtered[21].IN1 +av_ld_data_aligned_filtered[22] => av_ld_data_aligned_filtered[22].IN1 +av_ld_data_aligned_filtered[23] => av_ld_data_aligned_filtered[23].IN1 +av_ld_data_aligned_filtered[24] => av_ld_data_aligned_filtered[24].IN1 +av_ld_data_aligned_filtered[25] => av_ld_data_aligned_filtered[25].IN1 +av_ld_data_aligned_filtered[26] => av_ld_data_aligned_filtered[26].IN1 +av_ld_data_aligned_filtered[27] => av_ld_data_aligned_filtered[27].IN1 +av_ld_data_aligned_filtered[28] => av_ld_data_aligned_filtered[28].IN1 +av_ld_data_aligned_filtered[29] => av_ld_data_aligned_filtered[29].IN1 +av_ld_data_aligned_filtered[30] => av_ld_data_aligned_filtered[30].IN1 +av_ld_data_aligned_filtered[31] => av_ld_data_aligned_filtered[31].IN1 +byteenable_nxt[0] => byteenable[0].DATAIN +byteenable_nxt[1] => byteenable[1].DATAIN +byteenable_nxt[2] => byteenable[2].DATAIN +byteenable_nxt[3] => byteenable[3].DATAIN +clk => clk.IN12 +d_address[0] => d_address[0].IN1 +d_address[1] => d_address[1].IN1 +d_address[2] => d_address[2].IN1 +d_address[3] => d_address[3].IN1 +d_address[4] => d_address[4].IN1 +d_address[5] => d_address[5].IN1 +d_address[6] => d_address[6].IN1 +d_address[7] => d_address[7].IN1 +d_address[8] => d_address[8].IN1 +d_address[9] => d_address[9].IN1 +d_address[10] => d_address[10].IN1 +d_address[11] => d_address[11].IN1 +d_address[12] => d_address[12].IN1 +d_address[13] => d_address[13].IN1 +d_address[14] => d_address[14].IN1 +d_address[15] => d_address[15].IN1 +d_address[16] => d_address[16].IN1 +d_address[17] => d_address[17].IN1 +d_address[18] => d_address[18].IN1 +d_read => d_read.IN1 +d_waitrequest => d_waitrequest.IN1 +d_write => d_write.IN1 +debugaccess_nxt => debugaccess.DATAIN +hbreak_enabled => hbreak_enabled.IN1 +read_nxt => read.DATAA +reset => reset.IN1 +reset_n => reset_n.IN7 +test_ending => test_ending.IN1 +test_has_ended => test_has_ended.IN1 +write_nxt => write.DATAA +writedata_nxt[0] => writedata[0].DATAIN +writedata_nxt[1] => writedata[1].DATAIN +writedata_nxt[2] => writedata[2].DATAIN +writedata_nxt[3] => writedata[3].DATAIN +writedata_nxt[4] => writedata[4].DATAIN +writedata_nxt[5] => writedata[5].DATAIN +writedata_nxt[6] => writedata[6].DATAIN +writedata_nxt[7] => writedata[7].DATAIN +writedata_nxt[8] => writedata[8].DATAIN +writedata_nxt[9] => writedata[9].DATAIN +writedata_nxt[10] => writedata[10].DATAIN +writedata_nxt[11] => writedata[11].DATAIN +writedata_nxt[12] => writedata[12].DATAIN +writedata_nxt[13] => writedata[13].DATAIN +writedata_nxt[14] => writedata[14].DATAIN +writedata_nxt[15] => writedata[15].DATAIN +writedata_nxt[16] => writedata[16].DATAIN +writedata_nxt[17] => writedata[17].DATAIN +writedata_nxt[18] => writedata[18].DATAIN +writedata_nxt[19] => writedata[19].DATAIN +writedata_nxt[20] => writedata[20].DATAIN +writedata_nxt[21] => writedata[21].DATAIN +writedata_nxt[22] => writedata[22].DATAIN +writedata_nxt[23] => writedata[23].DATAIN +writedata_nxt[24] => writedata[24].DATAIN +writedata_nxt[25] => writedata[25].DATAIN +writedata_nxt[26] => writedata[26].DATAIN +writedata_nxt[27] => writedata[27].DATAIN +writedata_nxt[28] => writedata[28].DATAIN +writedata_nxt[29] => writedata[29].DATAIN +writedata_nxt[30] => writedata[30].DATAIN +writedata_nxt[31] => writedata[31].DATAIN +jtag_debug_module_debugaccess_to_roms <= debugack.DB_MAX_OUTPUT_PORT_TYPE +oci_hbreak_req <= nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug.oci_hbreak_req +oci_ienable[0] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[1] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[2] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[3] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[4] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[5] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[6] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[7] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[8] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[9] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[10] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[11] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[12] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[13] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[14] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[15] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[16] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[17] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[18] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[19] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[20] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[21] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[22] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[23] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[24] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[25] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[26] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[27] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[28] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[29] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[30] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_ienable[31] <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_ienable +oci_single_step_mode <= nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg.oci_single_step_mode +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resetrequest <= nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug.resetrequest +waitrequest <= nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem.waitrequest + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug +clk => clk.IN1 +dbrk_break => oci_hbreak_req.IN1 +debugreq => always0.IN0 +debugreq => oci_hbreak_req.IN1 +hbreak_enabled => always0.IN1 +hbreak_enabled => debugack.DATAIN +jdo[0] => ~NO_FANOUT~ +jdo[1] => ~NO_FANOUT~ +jdo[2] => ~NO_FANOUT~ +jdo[3] => ~NO_FANOUT~ +jdo[4] => ~NO_FANOUT~ +jdo[5] => ~NO_FANOUT~ +jdo[6] => ~NO_FANOUT~ +jdo[7] => ~NO_FANOUT~ +jdo[8] => ~NO_FANOUT~ +jdo[9] => ~NO_FANOUT~ +jdo[10] => ~NO_FANOUT~ +jdo[11] => ~NO_FANOUT~ +jdo[12] => ~NO_FANOUT~ +jdo[13] => ~NO_FANOUT~ +jdo[14] => ~NO_FANOUT~ +jdo[15] => ~NO_FANOUT~ +jdo[16] => ~NO_FANOUT~ +jdo[17] => ~NO_FANOUT~ +jdo[18] => break_on_reset.OUTPUTSELECT +jdo[19] => break_on_reset.OUTPUTSELECT +jdo[20] => jtag_break.OUTPUTSELECT +jdo[21] => jtag_break.OUTPUTSELECT +jdo[22] => resetrequest~reg0.DATAIN +jdo[23] => always1.IN0 +jdo[24] => resetlatch.OUTPUTSELECT +jdo[25] => always1.IN0 +jdo[26] => ~NO_FANOUT~ +jdo[27] => ~NO_FANOUT~ +jdo[28] => ~NO_FANOUT~ +jdo[29] => ~NO_FANOUT~ +jdo[30] => ~NO_FANOUT~ +jdo[31] => ~NO_FANOUT~ +jdo[32] => ~NO_FANOUT~ +jdo[33] => ~NO_FANOUT~ +jdo[34] => ~NO_FANOUT~ +jdo[35] => ~NO_FANOUT~ +jdo[36] => ~NO_FANOUT~ +jdo[37] => ~NO_FANOUT~ +jrst_n => unxcomplemented_resetxx0.IN1 +ocireg_ers => always1.IN0 +ocireg_mrs => always1.IN0 +reset => reset.IN1 +st_ready_test_idle => monitor_go.OUTPUTSELECT +take_action_ocimem_a => jtag_break.OUTPUTSELECT +take_action_ocimem_a => resetlatch.OUTPUTSELECT +take_action_ocimem_a => always1.IN1 +take_action_ocimem_a => always1.IN1 +take_action_ocimem_a => break_on_reset.ENA +take_action_ocimem_a => resetrequest~reg0.ENA +take_action_ocireg => always1.IN1 +take_action_ocireg => always1.IN1 +xbrk_break => oci_hbreak_req.IN1 +debugack <= hbreak_enabled.DB_MAX_OUTPUT_PORT_TYPE +monitor_error <= monitor_error~reg0.DB_MAX_OUTPUT_PORT_TYPE +monitor_go <= monitor_go~reg0.DB_MAX_OUTPUT_PORT_TYPE +monitor_ready <= monitor_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_hbreak_req <= oci_hbreak_req.DB_MAX_OUTPUT_PORT_TYPE +resetlatch <= resetlatch~reg0.DB_MAX_OUTPUT_PORT_TYPE +resetrequest <= resetrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem +address[0] => ociram_addr.DATAA +address[1] => ociram_addr.DATAA +address[2] => ociram_addr.DATAA +address[3] => ociram_addr.DATAA +address[4] => ociram_addr.DATAA +address[5] => ociram_addr.DATAA +address[6] => ociram_addr.DATAA +address[7] => ociram_addr.DATAA +address[8] => waitrequest.IN1 +address[8] => avalon_ram_wr.IN0 +byteenable[0] => ociram_byteenable.DATAA +byteenable[1] => ociram_byteenable.DATAA +byteenable[2] => ociram_byteenable.DATAA +byteenable[3] => ociram_byteenable.DATAA +clk => clk.IN1 +debugaccess => avalon_ram_wr.IN1 +jdo[0] => ~NO_FANOUT~ +jdo[1] => ~NO_FANOUT~ +jdo[2] => ~NO_FANOUT~ +jdo[3] => MonDReg.DATAB +jdo[4] => MonDReg.DATAB +jdo[5] => MonDReg.DATAB +jdo[6] => MonDReg.DATAB +jdo[7] => MonDReg.DATAB +jdo[8] => MonDReg.DATAB +jdo[9] => MonDReg.DATAB +jdo[10] => MonDReg.DATAB +jdo[11] => MonDReg.DATAB +jdo[12] => MonDReg.DATAB +jdo[13] => MonDReg.DATAB +jdo[14] => MonDReg.DATAB +jdo[15] => MonDReg.DATAB +jdo[16] => MonDReg.DATAB +jdo[17] => MonDReg.DATAB +jdo[17] => MonAReg.DATAB +jdo[17] => jtag_ram_rd.DATAB +jdo[17] => jtag_ram_access.DATAB +jdo[18] => MonDReg.DATAB +jdo[19] => MonDReg.DATAB +jdo[20] => MonDReg.DATAB +jdo[21] => MonDReg.DATAB +jdo[22] => MonDReg.DATAB +jdo[23] => MonDReg.DATAB +jdo[24] => MonDReg.DATAB +jdo[25] => MonDReg.DATAB +jdo[26] => MonDReg.DATAB +jdo[26] => MonAReg.DATAB +jdo[27] => MonDReg.DATAB +jdo[27] => MonAReg.DATAB +jdo[28] => MonDReg.DATAB +jdo[28] => MonAReg.DATAB +jdo[29] => MonDReg.DATAB +jdo[29] => MonAReg.DATAB +jdo[30] => MonDReg.DATAB +jdo[30] => MonAReg.DATAB +jdo[31] => MonDReg.DATAB +jdo[31] => MonAReg.DATAB +jdo[32] => MonDReg.DATAB +jdo[32] => MonAReg.DATAB +jdo[33] => MonDReg.DATAB +jdo[33] => MonAReg.DATAB +jdo[34] => MonDReg.DATAB +jdo[35] => ~NO_FANOUT~ +jdo[36] => ~NO_FANOUT~ +jdo[37] => ~NO_FANOUT~ +jrst_n => avalon_ociram_readdata_ready.ACLR +jrst_n => waitrequest~reg0.PRESET +jrst_n => MonDReg[0]~reg0.ACLR +jrst_n => MonDReg[1]~reg0.ACLR +jrst_n => MonDReg[2]~reg0.ACLR +jrst_n => MonDReg[3]~reg0.ACLR +jrst_n => MonDReg[4]~reg0.ACLR +jrst_n => MonDReg[5]~reg0.ACLR +jrst_n => MonDReg[6]~reg0.ACLR +jrst_n => MonDReg[7]~reg0.ACLR +jrst_n => MonDReg[8]~reg0.ACLR +jrst_n => MonDReg[9]~reg0.ACLR +jrst_n => MonDReg[10]~reg0.ACLR +jrst_n => MonDReg[11]~reg0.ACLR +jrst_n => MonDReg[12]~reg0.ACLR +jrst_n => MonDReg[13]~reg0.ACLR +jrst_n => MonDReg[14]~reg0.ACLR +jrst_n => MonDReg[15]~reg0.ACLR +jrst_n => MonDReg[16]~reg0.ACLR +jrst_n => MonDReg[17]~reg0.ACLR +jrst_n => MonDReg[18]~reg0.ACLR +jrst_n => MonDReg[19]~reg0.ACLR +jrst_n => MonDReg[20]~reg0.ACLR +jrst_n => MonDReg[21]~reg0.ACLR +jrst_n => MonDReg[22]~reg0.ACLR +jrst_n => MonDReg[23]~reg0.ACLR +jrst_n => MonDReg[24]~reg0.ACLR +jrst_n => MonDReg[25]~reg0.ACLR +jrst_n => MonDReg[26]~reg0.ACLR +jrst_n => MonDReg[27]~reg0.ACLR +jrst_n => MonDReg[28]~reg0.ACLR +jrst_n => MonDReg[29]~reg0.ACLR +jrst_n => MonDReg[30]~reg0.ACLR +jrst_n => MonDReg[31]~reg0.ACLR +jrst_n => MonAReg[2].ACLR +jrst_n => MonAReg[3].ACLR +jrst_n => MonAReg[4].ACLR +jrst_n => MonAReg[5].ACLR +jrst_n => MonAReg[6].ACLR +jrst_n => MonAReg[7].ACLR +jrst_n => MonAReg[8].ACLR +jrst_n => MonAReg[9].ACLR +jrst_n => MonAReg[10].ACLR +jrst_n => jtag_ram_access.ACLR +jrst_n => jtag_ram_rd_d1.ACLR +jrst_n => jtag_ram_rd.ACLR +jrst_n => jtag_ram_wr.ACLR +jrst_n => jtag_rd_d1.ACLR +jrst_n => jtag_rd.ACLR +read => avalon_ociram_readdata_ready.OUTPUTSELECT +read => waitrequest.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => jtag_rd.OUTPUTSELECT +take_action_ocimem_a => jtag_ram_rd.OUTPUTSELECT +take_action_ocimem_a => jtag_ram_access.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => jtag_ram_wr.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => jtag_ram_wr.OUTPUTSELECT +take_action_ocimem_b => jtag_rd.OUTPUTSELECT +take_action_ocimem_b => jtag_ram_rd.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => jtag_rd.OUTPUTSELECT +take_no_action_ocimem_a => jtag_ram_rd.OUTPUTSELECT +take_no_action_ocimem_a => jtag_ram_access.OUTPUTSELECT +take_no_action_ocimem_a => jtag_ram_wr.ENA +take_no_action_ocimem_a => MonDReg[31]~reg0.ENA +take_no_action_ocimem_a => MonDReg[30]~reg0.ENA +take_no_action_ocimem_a => MonDReg[29]~reg0.ENA +take_no_action_ocimem_a => MonDReg[28]~reg0.ENA +take_no_action_ocimem_a => MonDReg[27]~reg0.ENA +take_no_action_ocimem_a => MonDReg[26]~reg0.ENA +take_no_action_ocimem_a => MonDReg[25]~reg0.ENA +take_no_action_ocimem_a => MonDReg[24]~reg0.ENA +take_no_action_ocimem_a => MonDReg[23]~reg0.ENA +take_no_action_ocimem_a => MonDReg[22]~reg0.ENA +take_no_action_ocimem_a => MonDReg[21]~reg0.ENA +take_no_action_ocimem_a => MonDReg[20]~reg0.ENA +take_no_action_ocimem_a => MonDReg[19]~reg0.ENA +take_no_action_ocimem_a => MonDReg[18]~reg0.ENA +take_no_action_ocimem_a => MonDReg[17]~reg0.ENA +take_no_action_ocimem_a => MonDReg[16]~reg0.ENA +take_no_action_ocimem_a => MonDReg[15]~reg0.ENA +take_no_action_ocimem_a => MonDReg[14]~reg0.ENA +take_no_action_ocimem_a => MonDReg[13]~reg0.ENA +take_no_action_ocimem_a => MonDReg[12]~reg0.ENA +take_no_action_ocimem_a => MonDReg[11]~reg0.ENA +take_no_action_ocimem_a => MonDReg[10]~reg0.ENA +take_no_action_ocimem_a => MonDReg[9]~reg0.ENA +take_no_action_ocimem_a => MonDReg[8]~reg0.ENA +take_no_action_ocimem_a => MonDReg[7]~reg0.ENA +take_no_action_ocimem_a => MonDReg[6]~reg0.ENA +take_no_action_ocimem_a => MonDReg[5]~reg0.ENA +take_no_action_ocimem_a => MonDReg[4]~reg0.ENA +take_no_action_ocimem_a => MonDReg[3]~reg0.ENA +take_no_action_ocimem_a => MonDReg[2]~reg0.ENA +take_no_action_ocimem_a => MonDReg[1]~reg0.ENA +take_no_action_ocimem_a => MonDReg[0]~reg0.ENA +write => waitrequest.OUTPUTSELECT +write => avalon_ociram_readdata_ready.OUTPUTSELECT +write => avalon_ram_wr.IN1 +writedata[0] => ociram_wr_data.DATAA +writedata[1] => ociram_wr_data.DATAA +writedata[2] => ociram_wr_data.DATAA +writedata[3] => ociram_wr_data.DATAA +writedata[4] => ociram_wr_data.DATAA +writedata[5] => ociram_wr_data.DATAA +writedata[6] => ociram_wr_data.DATAA +writedata[7] => ociram_wr_data.DATAA +writedata[8] => ociram_wr_data.DATAA +writedata[9] => ociram_wr_data.DATAA +writedata[10] => ociram_wr_data.DATAA +writedata[11] => ociram_wr_data.DATAA +writedata[12] => ociram_wr_data.DATAA +writedata[13] => ociram_wr_data.DATAA +writedata[14] => ociram_wr_data.DATAA +writedata[15] => ociram_wr_data.DATAA +writedata[16] => ociram_wr_data.DATAA +writedata[17] => ociram_wr_data.DATAA +writedata[18] => ociram_wr_data.DATAA +writedata[19] => ociram_wr_data.DATAA +writedata[20] => ociram_wr_data.DATAA +writedata[21] => ociram_wr_data.DATAA +writedata[22] => ociram_wr_data.DATAA +writedata[23] => ociram_wr_data.DATAA +writedata[24] => ociram_wr_data.DATAA +writedata[25] => ociram_wr_data.DATAA +writedata[26] => ociram_wr_data.DATAA +writedata[27] => ociram_wr_data.DATAA +writedata[28] => ociram_wr_data.DATAA +writedata[29] => ociram_wr_data.DATAA +writedata[30] => ociram_wr_data.DATAA +writedata[31] => ociram_wr_data.DATAA +MonDReg[0] <= MonDReg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[1] <= MonDReg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[2] <= MonDReg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[3] <= MonDReg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[4] <= MonDReg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[5] <= MonDReg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[6] <= MonDReg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[7] <= MonDReg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[8] <= MonDReg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[9] <= MonDReg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[10] <= MonDReg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[11] <= MonDReg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[12] <= MonDReg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[13] <= MonDReg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[14] <= MonDReg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[15] <= MonDReg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[16] <= MonDReg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[17] <= MonDReg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[18] <= MonDReg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[19] <= MonDReg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[20] <= MonDReg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[21] <= MonDReg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[22] <= MonDReg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[23] <= MonDReg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[24] <= MonDReg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[25] <= MonDReg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[26] <= MonDReg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[27] <= MonDReg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[28] <= MonDReg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[29] <= MonDReg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[30] <= MonDReg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +MonDReg[31] <= MonDReg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +ociram_readdata[0] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[1] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[2] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[3] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[4] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[5] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[6] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[7] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[8] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[9] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[10] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[11] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[12] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[13] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[14] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[15] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[16] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[17] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[18] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[19] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[20] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[21] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[22] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[23] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[24] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[25] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[26] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[27] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[28] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[29] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[30] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +ociram_readdata[31] <= nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram.q +waitrequest <= waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram +address[0] => address[0].IN1 +address[1] => address[1].IN1 +address[2] => address[2].IN1 +address[3] => address[3].IN1 +address[4] => address[4].IN1 +address[5] => address[5].IN1 +address[6] => address[6].IN1 +address[7] => address[7].IN1 +byteenable[0] => byteenable[0].IN1 +byteenable[1] => byteenable[1].IN1 +byteenable[2] => byteenable[2].IN1 +byteenable[3] => byteenable[3].IN1 +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_a +q[1] <= altsyncram:the_altsyncram.q_a +q[2] <= altsyncram:the_altsyncram.q_a +q[3] <= altsyncram:the_altsyncram.q_a +q[4] <= altsyncram:the_altsyncram.q_a +q[5] <= altsyncram:the_altsyncram.q_a +q[6] <= altsyncram:the_altsyncram.q_a +q[7] <= altsyncram:the_altsyncram.q_a +q[8] <= altsyncram:the_altsyncram.q_a +q[9] <= altsyncram:the_altsyncram.q_a +q[10] <= altsyncram:the_altsyncram.q_a +q[11] <= altsyncram:the_altsyncram.q_a +q[12] <= altsyncram:the_altsyncram.q_a +q[13] <= altsyncram:the_altsyncram.q_a +q[14] <= altsyncram:the_altsyncram.q_a +q[15] <= altsyncram:the_altsyncram.q_a +q[16] <= altsyncram:the_altsyncram.q_a +q[17] <= altsyncram:the_altsyncram.q_a +q[18] <= altsyncram:the_altsyncram.q_a +q[19] <= altsyncram:the_altsyncram.q_a +q[20] <= altsyncram:the_altsyncram.q_a +q[21] <= altsyncram:the_altsyncram.q_a +q[22] <= altsyncram:the_altsyncram.q_a +q[23] <= altsyncram:the_altsyncram.q_a +q[24] <= altsyncram:the_altsyncram.q_a +q[25] <= altsyncram:the_altsyncram.q_a +q[26] <= altsyncram:the_altsyncram.q_a +q[27] <= altsyncram:the_altsyncram.q_a +q[28] <= altsyncram:the_altsyncram.q_a +q[29] <= altsyncram:the_altsyncram.q_a +q[30] <= altsyncram:the_altsyncram.q_a +q[31] <= altsyncram:the_altsyncram.q_a + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram +wren_a => altsyncram_4891:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_4891:auto_generated.data_a[0] +data_a[1] => altsyncram_4891:auto_generated.data_a[1] +data_a[2] => altsyncram_4891:auto_generated.data_a[2] +data_a[3] => altsyncram_4891:auto_generated.data_a[3] +data_a[4] => altsyncram_4891:auto_generated.data_a[4] +data_a[5] => altsyncram_4891:auto_generated.data_a[5] +data_a[6] => altsyncram_4891:auto_generated.data_a[6] +data_a[7] => altsyncram_4891:auto_generated.data_a[7] +data_a[8] => altsyncram_4891:auto_generated.data_a[8] +data_a[9] => altsyncram_4891:auto_generated.data_a[9] +data_a[10] => altsyncram_4891:auto_generated.data_a[10] +data_a[11] => altsyncram_4891:auto_generated.data_a[11] +data_a[12] => altsyncram_4891:auto_generated.data_a[12] +data_a[13] => altsyncram_4891:auto_generated.data_a[13] +data_a[14] => altsyncram_4891:auto_generated.data_a[14] +data_a[15] => altsyncram_4891:auto_generated.data_a[15] +data_a[16] => altsyncram_4891:auto_generated.data_a[16] +data_a[17] => altsyncram_4891:auto_generated.data_a[17] +data_a[18] => altsyncram_4891:auto_generated.data_a[18] +data_a[19] => altsyncram_4891:auto_generated.data_a[19] +data_a[20] => altsyncram_4891:auto_generated.data_a[20] +data_a[21] => altsyncram_4891:auto_generated.data_a[21] +data_a[22] => altsyncram_4891:auto_generated.data_a[22] +data_a[23] => altsyncram_4891:auto_generated.data_a[23] +data_a[24] => altsyncram_4891:auto_generated.data_a[24] +data_a[25] => altsyncram_4891:auto_generated.data_a[25] +data_a[26] => altsyncram_4891:auto_generated.data_a[26] +data_a[27] => altsyncram_4891:auto_generated.data_a[27] +data_a[28] => altsyncram_4891:auto_generated.data_a[28] +data_a[29] => altsyncram_4891:auto_generated.data_a[29] +data_a[30] => altsyncram_4891:auto_generated.data_a[30] +data_a[31] => altsyncram_4891:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +address_a[0] => altsyncram_4891:auto_generated.address_a[0] +address_a[1] => altsyncram_4891:auto_generated.address_a[1] +address_a[2] => altsyncram_4891:auto_generated.address_a[2] +address_a[3] => altsyncram_4891:auto_generated.address_a[3] +address_a[4] => altsyncram_4891:auto_generated.address_a[4] +address_a[5] => altsyncram_4891:auto_generated.address_a[5] +address_a[6] => altsyncram_4891:auto_generated.address_a[6] +address_a[7] => altsyncram_4891:auto_generated.address_a[7] +address_b[0] => ~NO_FANOUT~ +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_4891:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => altsyncram_4891:auto_generated.byteena_a[0] +byteena_a[1] => altsyncram_4891:auto_generated.byteena_a[1] +byteena_a[2] => altsyncram_4891:auto_generated.byteena_a[2] +byteena_a[3] => altsyncram_4891:auto_generated.byteena_a[3] +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_4891:auto_generated.q_a[0] +q_a[1] <= altsyncram_4891:auto_generated.q_a[1] +q_a[2] <= altsyncram_4891:auto_generated.q_a[2] +q_a[3] <= altsyncram_4891:auto_generated.q_a[3] +q_a[4] <= altsyncram_4891:auto_generated.q_a[4] +q_a[5] <= altsyncram_4891:auto_generated.q_a[5] +q_a[6] <= altsyncram_4891:auto_generated.q_a[6] +q_a[7] <= altsyncram_4891:auto_generated.q_a[7] +q_a[8] <= altsyncram_4891:auto_generated.q_a[8] +q_a[9] <= altsyncram_4891:auto_generated.q_a[9] +q_a[10] <= altsyncram_4891:auto_generated.q_a[10] +q_a[11] <= altsyncram_4891:auto_generated.q_a[11] +q_a[12] <= altsyncram_4891:auto_generated.q_a[12] +q_a[13] <= altsyncram_4891:auto_generated.q_a[13] +q_a[14] <= altsyncram_4891:auto_generated.q_a[14] +q_a[15] <= altsyncram_4891:auto_generated.q_a[15] +q_a[16] <= altsyncram_4891:auto_generated.q_a[16] +q_a[17] <= altsyncram_4891:auto_generated.q_a[17] +q_a[18] <= altsyncram_4891:auto_generated.q_a[18] +q_a[19] <= altsyncram_4891:auto_generated.q_a[19] +q_a[20] <= altsyncram_4891:auto_generated.q_a[20] +q_a[21] <= altsyncram_4891:auto_generated.q_a[21] +q_a[22] <= altsyncram_4891:auto_generated.q_a[22] +q_a[23] <= altsyncram_4891:auto_generated.q_a[23] +q_a[24] <= altsyncram_4891:auto_generated.q_a[24] +q_a[25] <= altsyncram_4891:auto_generated.q_a[25] +q_a[26] <= altsyncram_4891:auto_generated.q_a[26] +q_a[27] <= altsyncram_4891:auto_generated.q_a[27] +q_a[28] <= altsyncram_4891:auto_generated.q_a[28] +q_a[29] <= altsyncram_4891:auto_generated.q_a[29] +q_a[30] <= altsyncram_4891:auto_generated.q_a[30] +q_a[31] <= altsyncram_4891:auto_generated.q_a[31] +q_b[0] <= +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[5] => ram_block1a21.PORTAADDR5 +address_a[5] => ram_block1a22.PORTAADDR5 +address_a[5] => ram_block1a23.PORTAADDR5 +address_a[5] => ram_block1a24.PORTAADDR5 +address_a[5] => ram_block1a25.PORTAADDR5 +address_a[5] => ram_block1a26.PORTAADDR5 +address_a[5] => ram_block1a27.PORTAADDR5 +address_a[5] => ram_block1a28.PORTAADDR5 +address_a[5] => ram_block1a29.PORTAADDR5 +address_a[5] => ram_block1a30.PORTAADDR5 +address_a[5] => ram_block1a31.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[6] => ram_block1a21.PORTAADDR6 +address_a[6] => ram_block1a22.PORTAADDR6 +address_a[6] => ram_block1a23.PORTAADDR6 +address_a[6] => ram_block1a24.PORTAADDR6 +address_a[6] => ram_block1a25.PORTAADDR6 +address_a[6] => ram_block1a26.PORTAADDR6 +address_a[6] => ram_block1a27.PORTAADDR6 +address_a[6] => ram_block1a28.PORTAADDR6 +address_a[6] => ram_block1a29.PORTAADDR6 +address_a[6] => ram_block1a30.PORTAADDR6 +address_a[6] => ram_block1a31.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[7] => ram_block1a16.PORTAADDR7 +address_a[7] => ram_block1a17.PORTAADDR7 +address_a[7] => ram_block1a18.PORTAADDR7 +address_a[7] => ram_block1a19.PORTAADDR7 +address_a[7] => ram_block1a20.PORTAADDR7 +address_a[7] => ram_block1a21.PORTAADDR7 +address_a[7] => ram_block1a22.PORTAADDR7 +address_a[7] => ram_block1a23.PORTAADDR7 +address_a[7] => ram_block1a24.PORTAADDR7 +address_a[7] => ram_block1a25.PORTAADDR7 +address_a[7] => ram_block1a26.PORTAADDR7 +address_a[7] => ram_block1a27.PORTAADDR7 +address_a[7] => ram_block1a28.PORTAADDR7 +address_a[7] => ram_block1a29.PORTAADDR7 +address_a[7] => ram_block1a30.PORTAADDR7 +address_a[7] => ram_block1a31.PORTAADDR7 +byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_a[0] <= ram_block1a0.PORTADATAOUT +q_a[1] <= ram_block1a1.PORTADATAOUT +q_a[2] <= ram_block1a2.PORTADATAOUT +q_a[3] <= ram_block1a3.PORTADATAOUT +q_a[4] <= ram_block1a4.PORTADATAOUT +q_a[5] <= ram_block1a5.PORTADATAOUT +q_a[6] <= ram_block1a6.PORTADATAOUT +q_a[7] <= ram_block1a7.PORTADATAOUT +q_a[8] <= ram_block1a8.PORTADATAOUT +q_a[9] <= ram_block1a9.PORTADATAOUT +q_a[10] <= ram_block1a10.PORTADATAOUT +q_a[11] <= ram_block1a11.PORTADATAOUT +q_a[12] <= ram_block1a12.PORTADATAOUT +q_a[13] <= ram_block1a13.PORTADATAOUT +q_a[14] <= ram_block1a14.PORTADATAOUT +q_a[15] <= ram_block1a15.PORTADATAOUT +q_a[16] <= ram_block1a16.PORTADATAOUT +q_a[17] <= ram_block1a17.PORTADATAOUT +q_a[18] <= ram_block1a18.PORTADATAOUT +q_a[19] <= ram_block1a19.PORTADATAOUT +q_a[20] <= ram_block1a20.PORTADATAOUT +q_a[21] <= ram_block1a21.PORTADATAOUT +q_a[22] <= ram_block1a22.PORTADATAOUT +q_a[23] <= ram_block1a23.PORTADATAOUT +q_a[24] <= ram_block1a24.PORTADATAOUT +q_a[25] <= ram_block1a25.PORTADATAOUT +q_a[26] <= ram_block1a26.PORTADATAOUT +q_a[27] <= ram_block1a27.PORTADATAOUT +q_a[28] <= ram_block1a28.PORTADATAOUT +q_a[29] <= ram_block1a29.PORTADATAOUT +q_a[30] <= ram_block1a30.PORTADATAOUT +q_a[31] <= ram_block1a31.PORTADATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg +address[0] => Equal0.IN8 +address[0] => Equal1.IN1 +address[1] => Equal0.IN7 +address[1] => Equal1.IN8 +address[2] => Equal0.IN6 +address[2] => Equal1.IN7 +address[3] => Equal0.IN5 +address[3] => Equal1.IN6 +address[4] => Equal0.IN4 +address[4] => Equal1.IN5 +address[5] => Equal0.IN3 +address[5] => Equal1.IN4 +address[6] => Equal0.IN2 +address[6] => Equal1.IN3 +address[7] => Equal0.IN1 +address[7] => Equal1.IN2 +address[8] => Equal0.IN0 +address[8] => Equal1.IN0 +clk => oci_ienable[0]~reg0.CLK +clk => oci_ienable[1]~reg0.CLK +clk => oci_ienable[2]~reg0.CLK +clk => oci_ienable[3]~reg0.CLK +clk => oci_ienable[4]~reg0.CLK +clk => oci_ienable[5]~reg0.CLK +clk => oci_ienable[6]~reg0.CLK +clk => oci_ienable[7]~reg0.CLK +clk => oci_ienable[8]~reg0.CLK +clk => oci_ienable[9]~reg0.CLK +clk => oci_ienable[10]~reg0.CLK +clk => oci_ienable[11]~reg0.CLK +clk => oci_ienable[12]~reg0.CLK +clk => oci_ienable[13]~reg0.CLK +clk => oci_ienable[14]~reg0.CLK +clk => oci_ienable[15]~reg0.CLK +clk => oci_ienable[16]~reg0.CLK +clk => oci_ienable[17]~reg0.CLK +clk => oci_ienable[18]~reg0.CLK +clk => oci_ienable[19]~reg0.CLK +clk => oci_ienable[20]~reg0.CLK +clk => oci_ienable[21]~reg0.CLK +clk => oci_ienable[22]~reg0.CLK +clk => oci_ienable[23]~reg0.CLK +clk => oci_ienable[24]~reg0.CLK +clk => oci_ienable[25]~reg0.CLK +clk => oci_ienable[26]~reg0.CLK +clk => oci_ienable[27]~reg0.CLK +clk => oci_ienable[28]~reg0.CLK +clk => oci_ienable[29]~reg0.CLK +clk => oci_ienable[30]~reg0.CLK +clk => oci_ienable[31]~reg0.CLK +clk => oci_single_step_mode~reg0.CLK +debugaccess => write_strobe.IN0 +monitor_error => oci_reg_readdata.DATAB +monitor_go => oci_reg_readdata.DATAB +monitor_ready => oci_reg_readdata.DATAB +reset_n => oci_ienable[0]~reg0.ACLR +reset_n => oci_ienable[1]~reg0.ACLR +reset_n => oci_ienable[2]~reg0.ACLR +reset_n => oci_ienable[3]~reg0.ACLR +reset_n => oci_ienable[4]~reg0.ACLR +reset_n => oci_ienable[5]~reg0.PRESET +reset_n => oci_ienable[6]~reg0.ACLR +reset_n => oci_ienable[7]~reg0.ACLR +reset_n => oci_ienable[8]~reg0.ACLR +reset_n => oci_ienable[9]~reg0.ACLR +reset_n => oci_ienable[10]~reg0.ACLR +reset_n => oci_ienable[11]~reg0.ACLR +reset_n => oci_ienable[12]~reg0.ACLR +reset_n => oci_ienable[13]~reg0.ACLR +reset_n => oci_ienable[14]~reg0.ACLR +reset_n => oci_ienable[15]~reg0.ACLR +reset_n => oci_ienable[16]~reg0.ACLR +reset_n => oci_ienable[17]~reg0.ACLR +reset_n => oci_ienable[18]~reg0.ACLR +reset_n => oci_ienable[19]~reg0.ACLR +reset_n => oci_ienable[20]~reg0.ACLR +reset_n => oci_ienable[21]~reg0.ACLR +reset_n => oci_ienable[22]~reg0.ACLR +reset_n => oci_ienable[23]~reg0.ACLR +reset_n => oci_ienable[24]~reg0.ACLR +reset_n => oci_ienable[25]~reg0.ACLR +reset_n => oci_ienable[26]~reg0.ACLR +reset_n => oci_ienable[27]~reg0.ACLR +reset_n => oci_ienable[28]~reg0.ACLR +reset_n => oci_ienable[29]~reg0.ACLR +reset_n => oci_ienable[30]~reg0.ACLR +reset_n => oci_ienable[31]~reg0.ACLR +reset_n => oci_single_step_mode~reg0.ACLR +write => write_strobe.IN1 +writedata[0] => ocireg_mrs.DATAIN +writedata[1] => ocireg_ers.DATAIN +writedata[2] => ~NO_FANOUT~ +writedata[3] => oci_single_step_mode~reg0.DATAIN +writedata[4] => ~NO_FANOUT~ +writedata[5] => oci_ienable[5]~reg0.DATAIN +writedata[6] => ~NO_FANOUT~ +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +oci_ienable[0] <= oci_ienable[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[1] <= oci_ienable[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[2] <= oci_ienable[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[3] <= oci_ienable[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[4] <= oci_ienable[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[5] <= oci_ienable[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[6] <= oci_ienable[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[7] <= oci_ienable[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[8] <= oci_ienable[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[9] <= oci_ienable[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[10] <= oci_ienable[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[11] <= oci_ienable[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[12] <= oci_ienable[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[13] <= oci_ienable[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[14] <= oci_ienable[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[15] <= oci_ienable[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[16] <= oci_ienable[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[17] <= oci_ienable[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[18] <= oci_ienable[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[19] <= oci_ienable[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[20] <= oci_ienable[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[21] <= oci_ienable[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[22] <= oci_ienable[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[23] <= oci_ienable[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[24] <= oci_ienable[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[25] <= oci_ienable[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[26] <= oci_ienable[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[27] <= oci_ienable[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[28] <= oci_ienable[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[29] <= oci_ienable[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[30] <= oci_ienable[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[31] <= oci_ienable[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[0] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[1] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[2] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[3] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[4] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[5] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[6] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[7] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[8] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[9] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[10] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[11] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[12] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[13] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[14] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[15] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[16] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[17] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[18] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[19] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[20] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[21] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[22] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[23] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[24] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[25] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[26] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[27] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[28] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[29] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[30] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[31] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_single_step_mode <= oci_single_step_mode~reg0.DB_MAX_OUTPUT_PORT_TYPE +ocireg_ers <= writedata[1].DB_MAX_OUTPUT_PORT_TYPE +ocireg_mrs <= writedata[0].DB_MAX_OUTPUT_PORT_TYPE +take_action_ocireg <= take_action_ocireg.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break +clk => trigger_state.CLK +clk => break_readreg[0]~reg0.CLK +clk => break_readreg[1]~reg0.CLK +clk => break_readreg[2]~reg0.CLK +clk => break_readreg[3]~reg0.CLK +clk => break_readreg[4]~reg0.CLK +clk => break_readreg[5]~reg0.CLK +clk => break_readreg[6]~reg0.CLK +clk => break_readreg[7]~reg0.CLK +clk => break_readreg[8]~reg0.CLK +clk => break_readreg[9]~reg0.CLK +clk => break_readreg[10]~reg0.CLK +clk => break_readreg[11]~reg0.CLK +clk => break_readreg[12]~reg0.CLK +clk => break_readreg[13]~reg0.CLK +clk => break_readreg[14]~reg0.CLK +clk => break_readreg[15]~reg0.CLK +clk => break_readreg[16]~reg0.CLK +clk => break_readreg[17]~reg0.CLK +clk => break_readreg[18]~reg0.CLK +clk => break_readreg[19]~reg0.CLK +clk => break_readreg[20]~reg0.CLK +clk => break_readreg[21]~reg0.CLK +clk => break_readreg[22]~reg0.CLK +clk => break_readreg[23]~reg0.CLK +clk => break_readreg[24]~reg0.CLK +clk => break_readreg[25]~reg0.CLK +clk => break_readreg[26]~reg0.CLK +clk => break_readreg[27]~reg0.CLK +clk => break_readreg[28]~reg0.CLK +clk => break_readreg[29]~reg0.CLK +clk => break_readreg[30]~reg0.CLK +clk => break_readreg[31]~reg0.CLK +clk => trigbrktype~reg0.CLK +dbrk_break => trigbrktype.OUTPUTSELECT +dbrk_goto0 => always2.IN0 +dbrk_goto1 => always2.IN0 +jdo[0] => break_readreg.DATAB +jdo[0] => break_readreg.DATAB +jdo[0] => break_readreg.DATAB +jdo[1] => break_readreg.DATAB +jdo[1] => break_readreg.DATAB +jdo[1] => break_readreg.DATAB +jdo[2] => break_readreg.DATAB +jdo[2] => break_readreg.DATAB +jdo[2] => break_readreg.DATAB +jdo[3] => break_readreg.DATAB +jdo[3] => break_readreg.DATAB +jdo[3] => break_readreg.DATAB +jdo[4] => break_readreg.DATAB +jdo[4] => break_readreg.DATAB +jdo[4] => break_readreg.DATAB +jdo[5] => break_readreg.DATAB +jdo[5] => break_readreg.DATAB +jdo[5] => break_readreg.DATAB +jdo[6] => break_readreg.DATAB +jdo[6] => break_readreg.DATAB +jdo[6] => break_readreg.DATAB +jdo[7] => break_readreg.DATAB +jdo[7] => break_readreg.DATAB +jdo[7] => break_readreg.DATAB +jdo[8] => break_readreg.DATAB +jdo[8] => break_readreg.DATAB +jdo[8] => break_readreg.DATAB +jdo[9] => break_readreg.DATAB +jdo[9] => break_readreg.DATAB +jdo[9] => break_readreg.DATAB +jdo[10] => break_readreg.DATAB +jdo[10] => break_readreg.DATAB +jdo[10] => break_readreg.DATAB +jdo[11] => break_readreg.DATAB +jdo[11] => break_readreg.DATAB +jdo[11] => break_readreg.DATAB +jdo[12] => break_readreg.DATAB +jdo[12] => break_readreg.DATAB +jdo[12] => break_readreg.DATAB +jdo[13] => break_readreg.DATAB +jdo[13] => break_readreg.DATAB +jdo[13] => break_readreg.DATAB +jdo[14] => break_readreg.DATAB +jdo[14] => break_readreg.DATAB +jdo[14] => break_readreg.DATAB +jdo[15] => break_readreg.DATAB +jdo[15] => break_readreg.DATAB +jdo[15] => break_readreg.DATAB +jdo[16] => break_readreg.DATAB +jdo[16] => break_readreg.DATAB +jdo[16] => break_readreg.DATAB +jdo[17] => break_readreg.DATAB +jdo[17] => break_readreg.DATAB +jdo[17] => break_readreg.DATAB +jdo[18] => break_readreg.DATAB +jdo[18] => break_readreg.DATAB +jdo[18] => break_readreg.DATAB +jdo[19] => break_readreg.DATAB +jdo[19] => break_readreg.DATAB +jdo[19] => break_readreg.DATAB +jdo[20] => break_readreg.DATAB +jdo[20] => break_readreg.DATAB +jdo[20] => break_readreg.DATAB +jdo[21] => break_readreg.DATAB +jdo[21] => break_readreg.DATAB +jdo[21] => break_readreg.DATAB +jdo[22] => break_readreg.DATAB +jdo[22] => break_readreg.DATAB +jdo[22] => break_readreg.DATAB +jdo[23] => break_readreg.DATAB +jdo[23] => break_readreg.DATAB +jdo[23] => break_readreg.DATAB +jdo[24] => break_readreg.DATAB +jdo[24] => break_readreg.DATAB +jdo[24] => break_readreg.DATAB +jdo[25] => break_readreg.DATAB +jdo[25] => break_readreg.DATAB +jdo[25] => break_readreg.DATAB +jdo[26] => break_readreg.DATAB +jdo[26] => break_readreg.DATAB +jdo[26] => break_readreg.DATAB +jdo[27] => break_readreg.DATAB +jdo[27] => break_readreg.DATAB +jdo[27] => break_readreg.DATAB +jdo[28] => break_readreg.DATAB +jdo[28] => break_readreg.DATAB +jdo[28] => break_readreg.DATAB +jdo[29] => break_readreg.DATAB +jdo[29] => break_readreg.DATAB +jdo[29] => break_readreg.DATAB +jdo[30] => break_readreg.DATAB +jdo[30] => break_readreg.DATAB +jdo[30] => break_readreg.DATAB +jdo[31] => break_readreg.DATAB +jdo[31] => break_readreg.DATAB +jdo[31] => break_readreg.DATAB +jdo[32] => ~NO_FANOUT~ +jdo[33] => ~NO_FANOUT~ +jdo[34] => ~NO_FANOUT~ +jdo[35] => ~NO_FANOUT~ +jdo[36] => ~NO_FANOUT~ +jdo[37] => ~NO_FANOUT~ +jrst_n => break_readreg[0]~reg0.ACLR +jrst_n => break_readreg[1]~reg0.ACLR +jrst_n => break_readreg[2]~reg0.ACLR +jrst_n => break_readreg[3]~reg0.ACLR +jrst_n => break_readreg[4]~reg0.ACLR +jrst_n => break_readreg[5]~reg0.ACLR +jrst_n => break_readreg[6]~reg0.ACLR +jrst_n => break_readreg[7]~reg0.ACLR +jrst_n => break_readreg[8]~reg0.ACLR +jrst_n => break_readreg[9]~reg0.ACLR +jrst_n => break_readreg[10]~reg0.ACLR +jrst_n => break_readreg[11]~reg0.ACLR +jrst_n => break_readreg[12]~reg0.ACLR +jrst_n => break_readreg[13]~reg0.ACLR +jrst_n => break_readreg[14]~reg0.ACLR +jrst_n => break_readreg[15]~reg0.ACLR +jrst_n => break_readreg[16]~reg0.ACLR +jrst_n => break_readreg[17]~reg0.ACLR +jrst_n => break_readreg[18]~reg0.ACLR +jrst_n => break_readreg[19]~reg0.ACLR +jrst_n => break_readreg[20]~reg0.ACLR +jrst_n => break_readreg[21]~reg0.ACLR +jrst_n => break_readreg[22]~reg0.ACLR +jrst_n => break_readreg[23]~reg0.ACLR +jrst_n => break_readreg[24]~reg0.ACLR +jrst_n => break_readreg[25]~reg0.ACLR +jrst_n => break_readreg[26]~reg0.ACLR +jrst_n => break_readreg[27]~reg0.ACLR +jrst_n => break_readreg[28]~reg0.ACLR +jrst_n => break_readreg[29]~reg0.ACLR +jrst_n => break_readreg[30]~reg0.ACLR +jrst_n => break_readreg[31]~reg0.ACLR +jrst_n => trigbrktype~reg0.ACLR +reset_n => trigger_state.ACLR +take_action_break_a => take_action_any_break.IN0 +take_action_break_b => take_action_any_break.IN1 +take_action_break_c => take_action_any_break.IN1 +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +xbrk_goto0 => always2.IN1 +xbrk_goto1 => always2.IN1 +break_readreg[0] <= break_readreg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[1] <= break_readreg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[2] <= break_readreg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[3] <= break_readreg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[4] <= break_readreg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[5] <= break_readreg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[6] <= break_readreg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[7] <= break_readreg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[8] <= break_readreg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[9] <= break_readreg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[10] <= break_readreg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[11] <= break_readreg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[12] <= break_readreg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[13] <= break_readreg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[14] <= break_readreg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[15] <= break_readreg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[16] <= break_readreg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[17] <= break_readreg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[18] <= break_readreg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[19] <= break_readreg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[20] <= break_readreg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[21] <= break_readreg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[22] <= break_readreg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[23] <= break_readreg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[24] <= break_readreg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[25] <= break_readreg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[26] <= break_readreg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[27] <= break_readreg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[28] <= break_readreg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[29] <= break_readreg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[30] <= break_readreg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[31] <= break_readreg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_hit0_latch <= +dbrk_hit1_latch <= +dbrk_hit2_latch <= +dbrk_hit3_latch <= +trigbrktype <= trigbrktype~reg0.DB_MAX_OUTPUT_PORT_TYPE +trigger_state_0 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE +trigger_state_1 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE +xbrk_ctrl0[0] <= +xbrk_ctrl0[1] <= +xbrk_ctrl0[2] <= +xbrk_ctrl0[3] <= +xbrk_ctrl0[4] <= +xbrk_ctrl0[5] <= +xbrk_ctrl0[6] <= +xbrk_ctrl0[7] <= +xbrk_ctrl1[0] <= +xbrk_ctrl1[1] <= +xbrk_ctrl1[2] <= +xbrk_ctrl1[3] <= +xbrk_ctrl1[4] <= +xbrk_ctrl1[5] <= +xbrk_ctrl1[6] <= +xbrk_ctrl1[7] <= +xbrk_ctrl2[0] <= +xbrk_ctrl2[1] <= +xbrk_ctrl2[2] <= +xbrk_ctrl2[3] <= +xbrk_ctrl2[4] <= +xbrk_ctrl2[5] <= +xbrk_ctrl2[6] <= +xbrk_ctrl2[7] <= +xbrk_ctrl3[0] <= +xbrk_ctrl3[1] <= +xbrk_ctrl3[2] <= +xbrk_ctrl3[3] <= +xbrk_ctrl3[4] <= +xbrk_ctrl3[5] <= +xbrk_ctrl3[6] <= +xbrk_ctrl3[7] <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk +D_valid => ~NO_FANOUT~ +E_valid => xbrk_break~reg0.ENA +F_pc[0] => ~NO_FANOUT~ +F_pc[1] => ~NO_FANOUT~ +F_pc[2] => ~NO_FANOUT~ +F_pc[3] => ~NO_FANOUT~ +F_pc[4] => ~NO_FANOUT~ +F_pc[5] => ~NO_FANOUT~ +F_pc[6] => ~NO_FANOUT~ +F_pc[7] => ~NO_FANOUT~ +F_pc[8] => ~NO_FANOUT~ +F_pc[9] => ~NO_FANOUT~ +F_pc[10] => ~NO_FANOUT~ +F_pc[11] => ~NO_FANOUT~ +F_pc[12] => ~NO_FANOUT~ +F_pc[13] => ~NO_FANOUT~ +F_pc[14] => ~NO_FANOUT~ +F_pc[15] => ~NO_FANOUT~ +F_pc[16] => ~NO_FANOUT~ +clk => xbrk_break~reg0.CLK +reset_n => xbrk_break~reg0.ACLR +trigger_state_0 => ~NO_FANOUT~ +trigger_state_1 => ~NO_FANOUT~ +xbrk_ctrl0[0] => ~NO_FANOUT~ +xbrk_ctrl0[1] => ~NO_FANOUT~ +xbrk_ctrl0[2] => ~NO_FANOUT~ +xbrk_ctrl0[3] => ~NO_FANOUT~ +xbrk_ctrl0[4] => ~NO_FANOUT~ +xbrk_ctrl0[5] => ~NO_FANOUT~ +xbrk_ctrl0[6] => ~NO_FANOUT~ +xbrk_ctrl0[7] => ~NO_FANOUT~ +xbrk_ctrl1[0] => ~NO_FANOUT~ +xbrk_ctrl1[1] => ~NO_FANOUT~ +xbrk_ctrl1[2] => ~NO_FANOUT~ +xbrk_ctrl1[3] => ~NO_FANOUT~ +xbrk_ctrl1[4] => ~NO_FANOUT~ +xbrk_ctrl1[5] => ~NO_FANOUT~ +xbrk_ctrl1[6] => ~NO_FANOUT~ +xbrk_ctrl1[7] => ~NO_FANOUT~ +xbrk_ctrl2[0] => ~NO_FANOUT~ +xbrk_ctrl2[1] => ~NO_FANOUT~ +xbrk_ctrl2[2] => ~NO_FANOUT~ +xbrk_ctrl2[3] => ~NO_FANOUT~ +xbrk_ctrl2[4] => ~NO_FANOUT~ +xbrk_ctrl2[5] => ~NO_FANOUT~ +xbrk_ctrl2[6] => ~NO_FANOUT~ +xbrk_ctrl2[7] => ~NO_FANOUT~ +xbrk_ctrl3[0] => ~NO_FANOUT~ +xbrk_ctrl3[1] => ~NO_FANOUT~ +xbrk_ctrl3[2] => ~NO_FANOUT~ +xbrk_ctrl3[3] => ~NO_FANOUT~ +xbrk_ctrl3[4] => ~NO_FANOUT~ +xbrk_ctrl3[5] => ~NO_FANOUT~ +xbrk_ctrl3[6] => ~NO_FANOUT~ +xbrk_ctrl3[7] => ~NO_FANOUT~ +xbrk_break <= xbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE +xbrk_goto0 <= +xbrk_goto1 <= +xbrk_traceoff <= +xbrk_traceon <= +xbrk_trigout <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk +E_st_data[0] => cpu_d_writedata[0].DATAIN +E_st_data[1] => cpu_d_writedata[1].DATAIN +E_st_data[2] => cpu_d_writedata[2].DATAIN +E_st_data[3] => cpu_d_writedata[3].DATAIN +E_st_data[4] => cpu_d_writedata[4].DATAIN +E_st_data[5] => cpu_d_writedata[5].DATAIN +E_st_data[6] => cpu_d_writedata[6].DATAIN +E_st_data[7] => cpu_d_writedata[7].DATAIN +E_st_data[8] => cpu_d_writedata[8].DATAIN +E_st_data[9] => cpu_d_writedata[9].DATAIN +E_st_data[10] => cpu_d_writedata[10].DATAIN +E_st_data[11] => cpu_d_writedata[11].DATAIN +E_st_data[12] => cpu_d_writedata[12].DATAIN +E_st_data[13] => cpu_d_writedata[13].DATAIN +E_st_data[14] => cpu_d_writedata[14].DATAIN +E_st_data[15] => cpu_d_writedata[15].DATAIN +E_st_data[16] => cpu_d_writedata[16].DATAIN +E_st_data[17] => cpu_d_writedata[17].DATAIN +E_st_data[18] => cpu_d_writedata[18].DATAIN +E_st_data[19] => cpu_d_writedata[19].DATAIN +E_st_data[20] => cpu_d_writedata[20].DATAIN +E_st_data[21] => cpu_d_writedata[21].DATAIN +E_st_data[22] => cpu_d_writedata[22].DATAIN +E_st_data[23] => cpu_d_writedata[23].DATAIN +E_st_data[24] => cpu_d_writedata[24].DATAIN +E_st_data[25] => cpu_d_writedata[25].DATAIN +E_st_data[26] => cpu_d_writedata[26].DATAIN +E_st_data[27] => cpu_d_writedata[27].DATAIN +E_st_data[28] => cpu_d_writedata[28].DATAIN +E_st_data[29] => cpu_d_writedata[29].DATAIN +E_st_data[30] => cpu_d_writedata[30].DATAIN +E_st_data[31] => cpu_d_writedata[31].DATAIN +av_ld_data_aligned_filtered[0] => cpu_d_readdata[0].DATAIN +av_ld_data_aligned_filtered[1] => cpu_d_readdata[1].DATAIN +av_ld_data_aligned_filtered[2] => cpu_d_readdata[2].DATAIN +av_ld_data_aligned_filtered[3] => cpu_d_readdata[3].DATAIN +av_ld_data_aligned_filtered[4] => cpu_d_readdata[4].DATAIN +av_ld_data_aligned_filtered[5] => cpu_d_readdata[5].DATAIN +av_ld_data_aligned_filtered[6] => cpu_d_readdata[6].DATAIN +av_ld_data_aligned_filtered[7] => cpu_d_readdata[7].DATAIN +av_ld_data_aligned_filtered[8] => cpu_d_readdata[8].DATAIN +av_ld_data_aligned_filtered[9] => cpu_d_readdata[9].DATAIN +av_ld_data_aligned_filtered[10] => cpu_d_readdata[10].DATAIN +av_ld_data_aligned_filtered[11] => cpu_d_readdata[11].DATAIN +av_ld_data_aligned_filtered[12] => cpu_d_readdata[12].DATAIN +av_ld_data_aligned_filtered[13] => cpu_d_readdata[13].DATAIN +av_ld_data_aligned_filtered[14] => cpu_d_readdata[14].DATAIN +av_ld_data_aligned_filtered[15] => cpu_d_readdata[15].DATAIN +av_ld_data_aligned_filtered[16] => cpu_d_readdata[16].DATAIN +av_ld_data_aligned_filtered[17] => cpu_d_readdata[17].DATAIN +av_ld_data_aligned_filtered[18] => cpu_d_readdata[18].DATAIN +av_ld_data_aligned_filtered[19] => cpu_d_readdata[19].DATAIN +av_ld_data_aligned_filtered[20] => cpu_d_readdata[20].DATAIN +av_ld_data_aligned_filtered[21] => cpu_d_readdata[21].DATAIN +av_ld_data_aligned_filtered[22] => cpu_d_readdata[22].DATAIN +av_ld_data_aligned_filtered[23] => cpu_d_readdata[23].DATAIN +av_ld_data_aligned_filtered[24] => cpu_d_readdata[24].DATAIN +av_ld_data_aligned_filtered[25] => cpu_d_readdata[25].DATAIN +av_ld_data_aligned_filtered[26] => cpu_d_readdata[26].DATAIN +av_ld_data_aligned_filtered[27] => cpu_d_readdata[27].DATAIN +av_ld_data_aligned_filtered[28] => cpu_d_readdata[28].DATAIN +av_ld_data_aligned_filtered[29] => cpu_d_readdata[29].DATAIN +av_ld_data_aligned_filtered[30] => cpu_d_readdata[30].DATAIN +av_ld_data_aligned_filtered[31] => cpu_d_readdata[31].DATAIN +clk => dbrk_goto1~reg0.CLK +clk => dbrk_goto0~reg0.CLK +clk => dbrk_traceme~reg0.CLK +clk => dbrk_traceon~reg0.CLK +clk => dbrk_traceoff~reg0.CLK +clk => dbrk_break_pulse.CLK +clk => dbrk_trigout~reg0.CLK +clk => dbrk_break~reg0.CLK +d_address[0] => cpu_d_address[0].DATAIN +d_address[1] => cpu_d_address[1].DATAIN +d_address[2] => cpu_d_address[2].DATAIN +d_address[3] => cpu_d_address[3].DATAIN +d_address[4] => cpu_d_address[4].DATAIN +d_address[5] => cpu_d_address[5].DATAIN +d_address[6] => cpu_d_address[6].DATAIN +d_address[7] => cpu_d_address[7].DATAIN +d_address[8] => cpu_d_address[8].DATAIN +d_address[9] => cpu_d_address[9].DATAIN +d_address[10] => cpu_d_address[10].DATAIN +d_address[11] => cpu_d_address[11].DATAIN +d_address[12] => cpu_d_address[12].DATAIN +d_address[13] => cpu_d_address[13].DATAIN +d_address[14] => cpu_d_address[14].DATAIN +d_address[15] => cpu_d_address[15].DATAIN +d_address[16] => cpu_d_address[16].DATAIN +d_address[17] => cpu_d_address[17].DATAIN +d_address[18] => cpu_d_address[18].DATAIN +d_read => cpu_d_read.DATAIN +d_waitrequest => cpu_d_wait.DATAIN +d_write => cpu_d_write.DATAIN +debugack => dbrk_break.DATAB +reset_n => dbrk_goto1~reg0.ACLR +reset_n => dbrk_goto0~reg0.ACLR +reset_n => dbrk_traceme~reg0.ACLR +reset_n => dbrk_traceon~reg0.ACLR +reset_n => dbrk_traceoff~reg0.ACLR +reset_n => dbrk_break_pulse.ACLR +reset_n => dbrk_trigout~reg0.ACLR +reset_n => dbrk_break~reg0.ACLR +cpu_d_address[0] <= d_address[0].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[1] <= d_address[1].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[2] <= d_address[2].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[3] <= d_address[3].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[4] <= d_address[4].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[5] <= d_address[5].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[6] <= d_address[6].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[7] <= d_address[7].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[8] <= d_address[8].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[9] <= d_address[9].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[10] <= d_address[10].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[11] <= d_address[11].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[12] <= d_address[12].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[13] <= d_address[13].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[14] <= d_address[14].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[15] <= d_address[15].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[16] <= d_address[16].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[17] <= d_address[17].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[18] <= d_address[18].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_read <= d_read.DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[0] <= av_ld_data_aligned_filtered[0].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[1] <= av_ld_data_aligned_filtered[1].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[2] <= av_ld_data_aligned_filtered[2].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[3] <= av_ld_data_aligned_filtered[3].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[4] <= av_ld_data_aligned_filtered[4].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[5] <= av_ld_data_aligned_filtered[5].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[6] <= av_ld_data_aligned_filtered[6].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[7] <= av_ld_data_aligned_filtered[7].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[8] <= av_ld_data_aligned_filtered[8].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[9] <= av_ld_data_aligned_filtered[9].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[10] <= av_ld_data_aligned_filtered[10].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[11] <= av_ld_data_aligned_filtered[11].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[12] <= av_ld_data_aligned_filtered[12].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[13] <= av_ld_data_aligned_filtered[13].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[14] <= av_ld_data_aligned_filtered[14].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[15] <= av_ld_data_aligned_filtered[15].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[16] <= av_ld_data_aligned_filtered[16].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[17] <= av_ld_data_aligned_filtered[17].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[18] <= av_ld_data_aligned_filtered[18].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[19] <= av_ld_data_aligned_filtered[19].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[20] <= av_ld_data_aligned_filtered[20].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[21] <= av_ld_data_aligned_filtered[21].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[22] <= av_ld_data_aligned_filtered[22].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[23] <= av_ld_data_aligned_filtered[23].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[24] <= av_ld_data_aligned_filtered[24].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[25] <= av_ld_data_aligned_filtered[25].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[26] <= av_ld_data_aligned_filtered[26].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[27] <= av_ld_data_aligned_filtered[27].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[28] <= av_ld_data_aligned_filtered[28].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[29] <= av_ld_data_aligned_filtered[29].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[30] <= av_ld_data_aligned_filtered[30].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[31] <= av_ld_data_aligned_filtered[31].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_wait <= d_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +cpu_d_write <= d_write.DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[0] <= E_st_data[0].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[1] <= E_st_data[1].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[2] <= E_st_data[2].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[3] <= E_st_data[3].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[4] <= E_st_data[4].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[5] <= E_st_data[5].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[6] <= E_st_data[6].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[7] <= E_st_data[7].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[8] <= E_st_data[8].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[9] <= E_st_data[9].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[10] <= E_st_data[10].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[11] <= E_st_data[11].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[12] <= E_st_data[12].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[13] <= E_st_data[13].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[14] <= E_st_data[14].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[15] <= E_st_data[15].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[16] <= E_st_data[16].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[17] <= E_st_data[17].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[18] <= E_st_data[18].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[19] <= E_st_data[19].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[20] <= E_st_data[20].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[21] <= E_st_data[21].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[22] <= E_st_data[22].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[23] <= E_st_data[23].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[24] <= E_st_data[24].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[25] <= E_st_data[25].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[26] <= E_st_data[26].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[27] <= E_st_data[27].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[28] <= E_st_data[28].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[29] <= E_st_data[29].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[30] <= E_st_data[30].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[31] <= E_st_data[31].DB_MAX_OUTPUT_PORT_TYPE +dbrk_break <= dbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_goto0 <= dbrk_goto0~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_goto1 <= dbrk_goto1~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_traceme <= dbrk_traceme~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_traceoff <= dbrk_traceoff~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_traceon <= dbrk_traceon~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_trigout <= dbrk_trigout~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace +clk => dct_count[0]~reg0.CLK +clk => dct_count[1]~reg0.CLK +clk => dct_count[2]~reg0.CLK +clk => dct_count[3]~reg0.CLK +clk => dct_buffer[0]~reg0.CLK +clk => dct_buffer[1]~reg0.CLK +clk => dct_buffer[2]~reg0.CLK +clk => dct_buffer[3]~reg0.CLK +clk => dct_buffer[4]~reg0.CLK +clk => dct_buffer[5]~reg0.CLK +clk => dct_buffer[6]~reg0.CLK +clk => dct_buffer[7]~reg0.CLK +clk => dct_buffer[8]~reg0.CLK +clk => dct_buffer[9]~reg0.CLK +clk => dct_buffer[10]~reg0.CLK +clk => dct_buffer[11]~reg0.CLK +clk => dct_buffer[12]~reg0.CLK +clk => dct_buffer[13]~reg0.CLK +clk => dct_buffer[14]~reg0.CLK +clk => dct_buffer[15]~reg0.CLK +clk => dct_buffer[16]~reg0.CLK +clk => dct_buffer[17]~reg0.CLK +clk => dct_buffer[18]~reg0.CLK +clk => dct_buffer[19]~reg0.CLK +clk => dct_buffer[20]~reg0.CLK +clk => dct_buffer[21]~reg0.CLK +clk => dct_buffer[22]~reg0.CLK +clk => dct_buffer[23]~reg0.CLK +clk => dct_buffer[24]~reg0.CLK +clk => dct_buffer[25]~reg0.CLK +clk => dct_buffer[26]~reg0.CLK +clk => dct_buffer[27]~reg0.CLK +clk => dct_buffer[28]~reg0.CLK +clk => dct_buffer[29]~reg0.CLK +clk => itm[0]~reg0.CLK +clk => itm[1]~reg0.CLK +clk => itm[2]~reg0.CLK +clk => itm[3]~reg0.CLK +clk => itm[4]~reg0.CLK +clk => itm[5]~reg0.CLK +clk => itm[6]~reg0.CLK +clk => itm[7]~reg0.CLK +clk => itm[8]~reg0.CLK +clk => itm[9]~reg0.CLK +clk => itm[10]~reg0.CLK +clk => itm[11]~reg0.CLK +clk => itm[12]~reg0.CLK +clk => itm[13]~reg0.CLK +clk => itm[14]~reg0.CLK +clk => itm[15]~reg0.CLK +clk => itm[16]~reg0.CLK +clk => itm[17]~reg0.CLK +clk => itm[18]~reg0.CLK +clk => itm[19]~reg0.CLK +clk => itm[20]~reg0.CLK +clk => itm[21]~reg0.CLK +clk => itm[22]~reg0.CLK +clk => itm[23]~reg0.CLK +clk => itm[24]~reg0.CLK +clk => itm[25]~reg0.CLK +clk => itm[26]~reg0.CLK +clk => itm[27]~reg0.CLK +clk => itm[28]~reg0.CLK +clk => itm[29]~reg0.CLK +clk => itm[30]~reg0.CLK +clk => itm[31]~reg0.CLK +clk => itm[32]~reg0.CLK +clk => itm[33]~reg0.CLK +clk => itm[34]~reg0.CLK +clk => itm[35]~reg0.CLK +dbrk_traceoff => ~NO_FANOUT~ +dbrk_traceon => ~NO_FANOUT~ +jdo[0] => ~NO_FANOUT~ +jdo[1] => ~NO_FANOUT~ +jdo[2] => ~NO_FANOUT~ +jdo[3] => ~NO_FANOUT~ +jdo[4] => ~NO_FANOUT~ +jdo[5] => ~NO_FANOUT~ +jdo[6] => ~NO_FANOUT~ +jdo[7] => ~NO_FANOUT~ +jdo[8] => ~NO_FANOUT~ +jdo[9] => ~NO_FANOUT~ +jdo[10] => ~NO_FANOUT~ +jdo[11] => ~NO_FANOUT~ +jdo[12] => ~NO_FANOUT~ +jdo[13] => ~NO_FANOUT~ +jdo[14] => ~NO_FANOUT~ +jdo[15] => ~NO_FANOUT~ +jrst_n => dct_count[0]~reg0.ACLR +jrst_n => dct_count[1]~reg0.ACLR +jrst_n => dct_count[2]~reg0.ACLR +jrst_n => dct_count[3]~reg0.ACLR +jrst_n => dct_buffer[0]~reg0.ACLR +jrst_n => dct_buffer[1]~reg0.ACLR +jrst_n => dct_buffer[2]~reg0.ACLR +jrst_n => dct_buffer[3]~reg0.ACLR +jrst_n => dct_buffer[4]~reg0.ACLR +jrst_n => dct_buffer[5]~reg0.ACLR +jrst_n => dct_buffer[6]~reg0.ACLR +jrst_n => dct_buffer[7]~reg0.ACLR +jrst_n => dct_buffer[8]~reg0.ACLR +jrst_n => dct_buffer[9]~reg0.ACLR +jrst_n => dct_buffer[10]~reg0.ACLR +jrst_n => dct_buffer[11]~reg0.ACLR +jrst_n => dct_buffer[12]~reg0.ACLR +jrst_n => dct_buffer[13]~reg0.ACLR +jrst_n => dct_buffer[14]~reg0.ACLR +jrst_n => dct_buffer[15]~reg0.ACLR +jrst_n => dct_buffer[16]~reg0.ACLR +jrst_n => dct_buffer[17]~reg0.ACLR +jrst_n => dct_buffer[18]~reg0.ACLR +jrst_n => dct_buffer[19]~reg0.ACLR +jrst_n => dct_buffer[20]~reg0.ACLR +jrst_n => dct_buffer[21]~reg0.ACLR +jrst_n => dct_buffer[22]~reg0.ACLR +jrst_n => dct_buffer[23]~reg0.ACLR +jrst_n => dct_buffer[24]~reg0.ACLR +jrst_n => dct_buffer[25]~reg0.ACLR +jrst_n => dct_buffer[26]~reg0.ACLR +jrst_n => dct_buffer[27]~reg0.ACLR +jrst_n => dct_buffer[28]~reg0.ACLR +jrst_n => dct_buffer[29]~reg0.ACLR +jrst_n => itm[0]~reg0.ACLR +jrst_n => itm[1]~reg0.ACLR +jrst_n => itm[2]~reg0.ACLR +jrst_n => itm[3]~reg0.ACLR +jrst_n => itm[4]~reg0.ACLR +jrst_n => itm[5]~reg0.ACLR +jrst_n => itm[6]~reg0.ACLR +jrst_n => itm[7]~reg0.ACLR +jrst_n => itm[8]~reg0.ACLR +jrst_n => itm[9]~reg0.ACLR +jrst_n => itm[10]~reg0.ACLR +jrst_n => itm[11]~reg0.ACLR +jrst_n => itm[12]~reg0.ACLR +jrst_n => itm[13]~reg0.ACLR +jrst_n => itm[14]~reg0.ACLR +jrst_n => itm[15]~reg0.ACLR +jrst_n => itm[16]~reg0.ACLR +jrst_n => itm[17]~reg0.ACLR +jrst_n => itm[18]~reg0.ACLR +jrst_n => itm[19]~reg0.ACLR +jrst_n => itm[20]~reg0.ACLR +jrst_n => itm[21]~reg0.ACLR +jrst_n => itm[22]~reg0.ACLR +jrst_n => itm[23]~reg0.ACLR +jrst_n => itm[24]~reg0.ACLR +jrst_n => itm[25]~reg0.ACLR +jrst_n => itm[26]~reg0.ACLR +jrst_n => itm[27]~reg0.ACLR +jrst_n => itm[28]~reg0.ACLR +jrst_n => itm[29]~reg0.ACLR +jrst_n => itm[30]~reg0.ACLR +jrst_n => itm[31]~reg0.ACLR +jrst_n => itm[32]~reg0.ACLR +jrst_n => itm[33]~reg0.ACLR +jrst_n => itm[34]~reg0.ACLR +jrst_n => itm[35]~reg0.ACLR +take_action_tracectrl => ~NO_FANOUT~ +trc_enb => ~NO_FANOUT~ +xbrk_traceoff => ~NO_FANOUT~ +xbrk_traceon => ~NO_FANOUT~ +xbrk_wrap_traceoff => ~NO_FANOUT~ +dct_buffer[0] <= dct_buffer[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[1] <= dct_buffer[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[2] <= dct_buffer[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[3] <= dct_buffer[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[4] <= dct_buffer[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[5] <= dct_buffer[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[6] <= dct_buffer[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[7] <= dct_buffer[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[8] <= dct_buffer[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[9] <= dct_buffer[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[10] <= dct_buffer[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[11] <= dct_buffer[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[12] <= dct_buffer[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[13] <= dct_buffer[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[14] <= dct_buffer[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[15] <= dct_buffer[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[16] <= dct_buffer[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[17] <= dct_buffer[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[18] <= dct_buffer[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[19] <= dct_buffer[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[20] <= dct_buffer[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[21] <= dct_buffer[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[22] <= dct_buffer[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[23] <= dct_buffer[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[24] <= dct_buffer[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[25] <= dct_buffer[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[26] <= dct_buffer[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[27] <= dct_buffer[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[28] <= dct_buffer[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[29] <= dct_buffer[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[0] <= dct_count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[1] <= dct_count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[2] <= dct_count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[3] <= dct_count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[0] <= itm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[1] <= itm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[2] <= itm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[3] <= itm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[4] <= itm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[5] <= itm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[6] <= itm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[7] <= itm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[8] <= itm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[9] <= itm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[10] <= itm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[11] <= itm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[12] <= itm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[13] <= itm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[14] <= itm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[15] <= itm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[16] <= itm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[17] <= itm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[18] <= itm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[19] <= itm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[20] <= itm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[21] <= itm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[22] <= itm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[23] <= itm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[24] <= itm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[25] <= itm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[26] <= itm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[27] <= itm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[28] <= itm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[29] <= itm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[30] <= itm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[31] <= itm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[32] <= itm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[33] <= itm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[34] <= itm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[35] <= itm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_ctrl[0] <= +trc_ctrl[1] <= +trc_ctrl[2] <= +trc_ctrl[3] <= +trc_ctrl[4] <= +trc_ctrl[5] <= +trc_ctrl[6] <= +trc_ctrl[7] <= +trc_ctrl[8] <= +trc_ctrl[9] <= +trc_ctrl[10] <= +trc_ctrl[11] <= +trc_ctrl[12] <= +trc_ctrl[13] <= +trc_ctrl[14] <= +trc_ctrl[15] <= +trc_on <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace +clk => dtm[0]~reg0.CLK +clk => dtm[1]~reg0.CLK +clk => dtm[2]~reg0.CLK +clk => dtm[3]~reg0.CLK +clk => dtm[4]~reg0.CLK +clk => dtm[5]~reg0.CLK +clk => dtm[6]~reg0.CLK +clk => dtm[7]~reg0.CLK +clk => dtm[8]~reg0.CLK +clk => dtm[9]~reg0.CLK +clk => dtm[10]~reg0.CLK +clk => dtm[11]~reg0.CLK +clk => dtm[12]~reg0.CLK +clk => dtm[13]~reg0.CLK +clk => dtm[14]~reg0.CLK +clk => dtm[15]~reg0.CLK +clk => dtm[16]~reg0.CLK +clk => dtm[17]~reg0.CLK +clk => dtm[18]~reg0.CLK +clk => dtm[19]~reg0.CLK +clk => dtm[20]~reg0.CLK +clk => dtm[21]~reg0.CLK +clk => dtm[22]~reg0.CLK +clk => dtm[23]~reg0.CLK +clk => dtm[24]~reg0.CLK +clk => dtm[25]~reg0.CLK +clk => dtm[26]~reg0.CLK +clk => dtm[27]~reg0.CLK +clk => dtm[28]~reg0.CLK +clk => dtm[29]~reg0.CLK +clk => dtm[30]~reg0.CLK +clk => dtm[31]~reg0.CLK +clk => dtm[32]~reg0.CLK +clk => dtm[33]~reg0.CLK +clk => dtm[34]~reg0.CLK +clk => dtm[35]~reg0.CLK +clk => atm[0]~reg0.CLK +clk => atm[1]~reg0.CLK +clk => atm[2]~reg0.CLK +clk => atm[3]~reg0.CLK +clk => atm[4]~reg0.CLK +clk => atm[5]~reg0.CLK +clk => atm[6]~reg0.CLK +clk => atm[7]~reg0.CLK +clk => atm[8]~reg0.CLK +clk => atm[9]~reg0.CLK +clk => atm[10]~reg0.CLK +clk => atm[11]~reg0.CLK +clk => atm[12]~reg0.CLK +clk => atm[13]~reg0.CLK +clk => atm[14]~reg0.CLK +clk => atm[15]~reg0.CLK +clk => atm[16]~reg0.CLK +clk => atm[17]~reg0.CLK +clk => atm[18]~reg0.CLK +clk => atm[19]~reg0.CLK +clk => atm[20]~reg0.CLK +clk => atm[21]~reg0.CLK +clk => atm[22]~reg0.CLK +clk => atm[23]~reg0.CLK +clk => atm[24]~reg0.CLK +clk => atm[25]~reg0.CLK +clk => atm[26]~reg0.CLK +clk => atm[27]~reg0.CLK +clk => atm[28]~reg0.CLK +clk => atm[29]~reg0.CLK +clk => atm[30]~reg0.CLK +clk => atm[31]~reg0.CLK +clk => atm[32]~reg0.CLK +clk => atm[33]~reg0.CLK +clk => atm[34]~reg0.CLK +clk => atm[35]~reg0.CLK +cpu_d_address[0] => ~NO_FANOUT~ +cpu_d_address[1] => ~NO_FANOUT~ +cpu_d_address[2] => ~NO_FANOUT~ +cpu_d_address[3] => ~NO_FANOUT~ +cpu_d_address[4] => ~NO_FANOUT~ +cpu_d_address[5] => ~NO_FANOUT~ +cpu_d_address[6] => ~NO_FANOUT~ +cpu_d_address[7] => ~NO_FANOUT~ +cpu_d_address[8] => ~NO_FANOUT~ +cpu_d_address[9] => ~NO_FANOUT~ +cpu_d_address[10] => ~NO_FANOUT~ +cpu_d_address[11] => ~NO_FANOUT~ +cpu_d_address[12] => ~NO_FANOUT~ +cpu_d_address[13] => ~NO_FANOUT~ +cpu_d_address[14] => ~NO_FANOUT~ +cpu_d_address[15] => ~NO_FANOUT~ +cpu_d_address[16] => ~NO_FANOUT~ +cpu_d_address[17] => ~NO_FANOUT~ +cpu_d_address[18] => ~NO_FANOUT~ +cpu_d_read => ~NO_FANOUT~ +cpu_d_readdata[0] => ~NO_FANOUT~ +cpu_d_readdata[1] => ~NO_FANOUT~ +cpu_d_readdata[2] => ~NO_FANOUT~ +cpu_d_readdata[3] => ~NO_FANOUT~ +cpu_d_readdata[4] => ~NO_FANOUT~ +cpu_d_readdata[5] => ~NO_FANOUT~ +cpu_d_readdata[6] => ~NO_FANOUT~ +cpu_d_readdata[7] => ~NO_FANOUT~ +cpu_d_readdata[8] => ~NO_FANOUT~ +cpu_d_readdata[9] => ~NO_FANOUT~ +cpu_d_readdata[10] => ~NO_FANOUT~ +cpu_d_readdata[11] => ~NO_FANOUT~ +cpu_d_readdata[12] => ~NO_FANOUT~ +cpu_d_readdata[13] => ~NO_FANOUT~ +cpu_d_readdata[14] => ~NO_FANOUT~ +cpu_d_readdata[15] => ~NO_FANOUT~ +cpu_d_readdata[16] => ~NO_FANOUT~ +cpu_d_readdata[17] => ~NO_FANOUT~ +cpu_d_readdata[18] => ~NO_FANOUT~ +cpu_d_readdata[19] => ~NO_FANOUT~ +cpu_d_readdata[20] => ~NO_FANOUT~ +cpu_d_readdata[21] => ~NO_FANOUT~ +cpu_d_readdata[22] => ~NO_FANOUT~ +cpu_d_readdata[23] => ~NO_FANOUT~ +cpu_d_readdata[24] => ~NO_FANOUT~ +cpu_d_readdata[25] => ~NO_FANOUT~ +cpu_d_readdata[26] => ~NO_FANOUT~ +cpu_d_readdata[27] => ~NO_FANOUT~ +cpu_d_readdata[28] => ~NO_FANOUT~ +cpu_d_readdata[29] => ~NO_FANOUT~ +cpu_d_readdata[30] => ~NO_FANOUT~ +cpu_d_readdata[31] => ~NO_FANOUT~ +cpu_d_wait => ~NO_FANOUT~ +cpu_d_write => ~NO_FANOUT~ +cpu_d_writedata[0] => ~NO_FANOUT~ +cpu_d_writedata[1] => ~NO_FANOUT~ +cpu_d_writedata[2] => ~NO_FANOUT~ +cpu_d_writedata[3] => ~NO_FANOUT~ +cpu_d_writedata[4] => ~NO_FANOUT~ +cpu_d_writedata[5] => ~NO_FANOUT~ +cpu_d_writedata[6] => ~NO_FANOUT~ +cpu_d_writedata[7] => ~NO_FANOUT~ +cpu_d_writedata[8] => ~NO_FANOUT~ +cpu_d_writedata[9] => ~NO_FANOUT~ +cpu_d_writedata[10] => ~NO_FANOUT~ +cpu_d_writedata[11] => ~NO_FANOUT~ +cpu_d_writedata[12] => ~NO_FANOUT~ +cpu_d_writedata[13] => ~NO_FANOUT~ +cpu_d_writedata[14] => ~NO_FANOUT~ +cpu_d_writedata[15] => ~NO_FANOUT~ +cpu_d_writedata[16] => ~NO_FANOUT~ +cpu_d_writedata[17] => ~NO_FANOUT~ +cpu_d_writedata[18] => ~NO_FANOUT~ +cpu_d_writedata[19] => ~NO_FANOUT~ +cpu_d_writedata[20] => ~NO_FANOUT~ +cpu_d_writedata[21] => ~NO_FANOUT~ +cpu_d_writedata[22] => ~NO_FANOUT~ +cpu_d_writedata[23] => ~NO_FANOUT~ +cpu_d_writedata[24] => ~NO_FANOUT~ +cpu_d_writedata[25] => ~NO_FANOUT~ +cpu_d_writedata[26] => ~NO_FANOUT~ +cpu_d_writedata[27] => ~NO_FANOUT~ +cpu_d_writedata[28] => ~NO_FANOUT~ +cpu_d_writedata[29] => ~NO_FANOUT~ +cpu_d_writedata[30] => ~NO_FANOUT~ +cpu_d_writedata[31] => ~NO_FANOUT~ +jrst_n => dtm[0]~reg0.ACLR +jrst_n => dtm[1]~reg0.ACLR +jrst_n => dtm[2]~reg0.ACLR +jrst_n => dtm[3]~reg0.ACLR +jrst_n => dtm[4]~reg0.ACLR +jrst_n => dtm[5]~reg0.ACLR +jrst_n => dtm[6]~reg0.ACLR +jrst_n => dtm[7]~reg0.ACLR +jrst_n => dtm[8]~reg0.ACLR +jrst_n => dtm[9]~reg0.ACLR +jrst_n => dtm[10]~reg0.ACLR +jrst_n => dtm[11]~reg0.ACLR +jrst_n => dtm[12]~reg0.ACLR +jrst_n => dtm[13]~reg0.ACLR +jrst_n => dtm[14]~reg0.ACLR +jrst_n => dtm[15]~reg0.ACLR +jrst_n => dtm[16]~reg0.ACLR +jrst_n => dtm[17]~reg0.ACLR +jrst_n => dtm[18]~reg0.ACLR +jrst_n => dtm[19]~reg0.ACLR +jrst_n => dtm[20]~reg0.ACLR +jrst_n => dtm[21]~reg0.ACLR +jrst_n => dtm[22]~reg0.ACLR +jrst_n => dtm[23]~reg0.ACLR +jrst_n => dtm[24]~reg0.ACLR +jrst_n => dtm[25]~reg0.ACLR +jrst_n => dtm[26]~reg0.ACLR +jrst_n => dtm[27]~reg0.ACLR +jrst_n => dtm[28]~reg0.ACLR +jrst_n => dtm[29]~reg0.ACLR +jrst_n => dtm[30]~reg0.ACLR +jrst_n => dtm[31]~reg0.ACLR +jrst_n => dtm[32]~reg0.ACLR +jrst_n => dtm[33]~reg0.ACLR +jrst_n => dtm[34]~reg0.ACLR +jrst_n => dtm[35]~reg0.ACLR +jrst_n => atm[0]~reg0.ACLR +jrst_n => atm[1]~reg0.ACLR +jrst_n => atm[2]~reg0.ACLR +jrst_n => atm[3]~reg0.ACLR +jrst_n => atm[4]~reg0.ACLR +jrst_n => atm[5]~reg0.ACLR +jrst_n => atm[6]~reg0.ACLR +jrst_n => atm[7]~reg0.ACLR +jrst_n => atm[8]~reg0.ACLR +jrst_n => atm[9]~reg0.ACLR +jrst_n => atm[10]~reg0.ACLR +jrst_n => atm[11]~reg0.ACLR +jrst_n => atm[12]~reg0.ACLR +jrst_n => atm[13]~reg0.ACLR +jrst_n => atm[14]~reg0.ACLR +jrst_n => atm[15]~reg0.ACLR +jrst_n => atm[16]~reg0.ACLR +jrst_n => atm[17]~reg0.ACLR +jrst_n => atm[18]~reg0.ACLR +jrst_n => atm[19]~reg0.ACLR +jrst_n => atm[20]~reg0.ACLR +jrst_n => atm[21]~reg0.ACLR +jrst_n => atm[22]~reg0.ACLR +jrst_n => atm[23]~reg0.ACLR +jrst_n => atm[24]~reg0.ACLR +jrst_n => atm[25]~reg0.ACLR +jrst_n => atm[26]~reg0.ACLR +jrst_n => atm[27]~reg0.ACLR +jrst_n => atm[28]~reg0.ACLR +jrst_n => atm[29]~reg0.ACLR +jrst_n => atm[30]~reg0.ACLR +jrst_n => atm[31]~reg0.ACLR +jrst_n => atm[32]~reg0.ACLR +jrst_n => atm[33]~reg0.ACLR +jrst_n => atm[34]~reg0.ACLR +jrst_n => atm[35]~reg0.ACLR +trc_ctrl[0] => trc_ctrl[0].IN1 +trc_ctrl[1] => trc_ctrl[1].IN1 +trc_ctrl[2] => trc_ctrl[2].IN1 +trc_ctrl[3] => trc_ctrl[3].IN1 +trc_ctrl[4] => trc_ctrl[4].IN1 +trc_ctrl[5] => trc_ctrl[5].IN1 +trc_ctrl[6] => trc_ctrl[6].IN1 +trc_ctrl[7] => trc_ctrl[7].IN1 +trc_ctrl[8] => trc_ctrl[8].IN1 +trc_ctrl[9] => ~NO_FANOUT~ +trc_ctrl[10] => ~NO_FANOUT~ +trc_ctrl[11] => ~NO_FANOUT~ +trc_ctrl[12] => ~NO_FANOUT~ +trc_ctrl[13] => ~NO_FANOUT~ +trc_ctrl[14] => ~NO_FANOUT~ +trc_ctrl[15] => ~NO_FANOUT~ +atm[0] <= atm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[1] <= atm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[2] <= atm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[3] <= atm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[4] <= atm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[5] <= atm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[6] <= atm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[7] <= atm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[8] <= atm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[9] <= atm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[10] <= atm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[11] <= atm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[12] <= atm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[13] <= atm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[14] <= atm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[15] <= atm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[16] <= atm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[17] <= atm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[18] <= atm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[19] <= atm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[20] <= atm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[21] <= atm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[22] <= atm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[23] <= atm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[24] <= atm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[25] <= atm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[26] <= atm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[27] <= atm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[28] <= atm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[29] <= atm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[30] <= atm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[31] <= atm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[32] <= atm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[33] <= atm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[34] <= atm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[35] <= atm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[0] <= dtm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[1] <= dtm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[2] <= dtm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[3] <= dtm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[4] <= dtm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[5] <= dtm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[6] <= dtm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[7] <= dtm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[8] <= dtm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[9] <= dtm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[10] <= dtm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[11] <= dtm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[12] <= dtm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[13] <= dtm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[14] <= dtm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[15] <= dtm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[16] <= dtm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[17] <= dtm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[18] <= dtm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[19] <= dtm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[20] <= dtm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[21] <= dtm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[22] <= dtm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[23] <= dtm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[24] <= dtm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[25] <= dtm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[26] <= dtm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[27] <= dtm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[28] <= dtm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[29] <= dtm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[30] <= dtm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[31] <= dtm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[32] <= dtm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[33] <= dtm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[34] <= dtm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[35] <= dtm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode +ctrl[0] => ~NO_FANOUT~ +ctrl[1] => ~NO_FANOUT~ +ctrl[2] => ~NO_FANOUT~ +ctrl[3] => ~NO_FANOUT~ +ctrl[4] => ~NO_FANOUT~ +ctrl[5] => Decoder0.IN2 +ctrl[5] => td_mode[3].DATAIN +ctrl[6] => Decoder0.IN1 +ctrl[6] => Decoder1.IN1 +ctrl[6] => td_mode[2].DATAIN +ctrl[7] => Decoder0.IN0 +ctrl[7] => Decoder1.IN0 +ctrl[8] => ~NO_FANOUT~ +td_mode[0] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE +td_mode[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +td_mode[2] <= ctrl[6].DB_MAX_OUTPUT_PORT_TYPE +td_mode[3] <= ctrl[5].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo +atm[0] => ~NO_FANOUT~ +atm[1] => ~NO_FANOUT~ +atm[2] => ~NO_FANOUT~ +atm[3] => ~NO_FANOUT~ +atm[4] => ~NO_FANOUT~ +atm[5] => ~NO_FANOUT~ +atm[6] => ~NO_FANOUT~ +atm[7] => ~NO_FANOUT~ +atm[8] => ~NO_FANOUT~ +atm[9] => ~NO_FANOUT~ +atm[10] => ~NO_FANOUT~ +atm[11] => ~NO_FANOUT~ +atm[12] => ~NO_FANOUT~ +atm[13] => ~NO_FANOUT~ +atm[14] => ~NO_FANOUT~ +atm[15] => ~NO_FANOUT~ +atm[16] => ~NO_FANOUT~ +atm[17] => ~NO_FANOUT~ +atm[18] => ~NO_FANOUT~ +atm[19] => ~NO_FANOUT~ +atm[20] => ~NO_FANOUT~ +atm[21] => ~NO_FANOUT~ +atm[22] => ~NO_FANOUT~ +atm[23] => ~NO_FANOUT~ +atm[24] => ~NO_FANOUT~ +atm[25] => ~NO_FANOUT~ +atm[26] => ~NO_FANOUT~ +atm[27] => ~NO_FANOUT~ +atm[28] => ~NO_FANOUT~ +atm[29] => ~NO_FANOUT~ +atm[30] => ~NO_FANOUT~ +atm[31] => ~NO_FANOUT~ +atm[32] => WideOr1.IN0 +atm[33] => WideOr1.IN1 +atm[34] => WideOr1.IN2 +atm[35] => WideOr1.IN3 +clk => fifocount[0].CLK +clk => fifocount[1].CLK +clk => fifocount[2].CLK +clk => fifocount[3].CLK +clk => fifocount[4].CLK +dbrk_traceme => trc_this.IN1 +dbrk_traceoff => trc_this.IN0 +dbrk_traceon => trc_this.IN1 +dct_buffer[0] => dct_buffer[0].IN1 +dct_buffer[1] => dct_buffer[1].IN1 +dct_buffer[2] => dct_buffer[2].IN1 +dct_buffer[3] => dct_buffer[3].IN1 +dct_buffer[4] => dct_buffer[4].IN1 +dct_buffer[5] => dct_buffer[5].IN1 +dct_buffer[6] => dct_buffer[6].IN1 +dct_buffer[7] => dct_buffer[7].IN1 +dct_buffer[8] => dct_buffer[8].IN1 +dct_buffer[9] => dct_buffer[9].IN1 +dct_buffer[10] => dct_buffer[10].IN1 +dct_buffer[11] => dct_buffer[11].IN1 +dct_buffer[12] => dct_buffer[12].IN1 +dct_buffer[13] => dct_buffer[13].IN1 +dct_buffer[14] => dct_buffer[14].IN1 +dct_buffer[15] => dct_buffer[15].IN1 +dct_buffer[16] => dct_buffer[16].IN1 +dct_buffer[17] => dct_buffer[17].IN1 +dct_buffer[18] => dct_buffer[18].IN1 +dct_buffer[19] => dct_buffer[19].IN1 +dct_buffer[20] => dct_buffer[20].IN1 +dct_buffer[21] => dct_buffer[21].IN1 +dct_buffer[22] => dct_buffer[22].IN1 +dct_buffer[23] => dct_buffer[23].IN1 +dct_buffer[24] => dct_buffer[24].IN1 +dct_buffer[25] => dct_buffer[25].IN1 +dct_buffer[26] => dct_buffer[26].IN1 +dct_buffer[27] => dct_buffer[27].IN1 +dct_buffer[28] => dct_buffer[28].IN1 +dct_buffer[29] => dct_buffer[29].IN1 +dct_count[0] => dct_count[0].IN1 +dct_count[1] => dct_count[1].IN1 +dct_count[2] => dct_count[2].IN1 +dct_count[3] => dct_count[3].IN1 +dtm[0] => ~NO_FANOUT~ +dtm[1] => ~NO_FANOUT~ +dtm[2] => ~NO_FANOUT~ +dtm[3] => ~NO_FANOUT~ +dtm[4] => ~NO_FANOUT~ +dtm[5] => ~NO_FANOUT~ +dtm[6] => ~NO_FANOUT~ +dtm[7] => ~NO_FANOUT~ +dtm[8] => ~NO_FANOUT~ +dtm[9] => ~NO_FANOUT~ +dtm[10] => ~NO_FANOUT~ +dtm[11] => ~NO_FANOUT~ +dtm[12] => ~NO_FANOUT~ +dtm[13] => ~NO_FANOUT~ +dtm[14] => ~NO_FANOUT~ +dtm[15] => ~NO_FANOUT~ +dtm[16] => ~NO_FANOUT~ +dtm[17] => ~NO_FANOUT~ +dtm[18] => ~NO_FANOUT~ +dtm[19] => ~NO_FANOUT~ +dtm[20] => ~NO_FANOUT~ +dtm[21] => ~NO_FANOUT~ +dtm[22] => ~NO_FANOUT~ +dtm[23] => ~NO_FANOUT~ +dtm[24] => ~NO_FANOUT~ +dtm[25] => ~NO_FANOUT~ +dtm[26] => ~NO_FANOUT~ +dtm[27] => ~NO_FANOUT~ +dtm[28] => ~NO_FANOUT~ +dtm[29] => ~NO_FANOUT~ +dtm[30] => ~NO_FANOUT~ +dtm[31] => ~NO_FANOUT~ +dtm[32] => WideOr2.IN0 +dtm[33] => WideOr2.IN1 +dtm[34] => WideOr2.IN2 +dtm[35] => WideOr2.IN3 +itm[0] => tw[0].DATAIN +itm[1] => tw[1].DATAIN +itm[2] => tw[2].DATAIN +itm[3] => tw[3].DATAIN +itm[4] => tw[4].DATAIN +itm[5] => tw[5].DATAIN +itm[6] => tw[6].DATAIN +itm[7] => tw[7].DATAIN +itm[8] => tw[8].DATAIN +itm[9] => tw[9].DATAIN +itm[10] => tw[10].DATAIN +itm[11] => tw[11].DATAIN +itm[12] => tw[12].DATAIN +itm[13] => tw[13].DATAIN +itm[14] => tw[14].DATAIN +itm[15] => tw[15].DATAIN +itm[16] => tw[16].DATAIN +itm[17] => tw[17].DATAIN +itm[18] => tw[18].DATAIN +itm[19] => tw[19].DATAIN +itm[20] => tw[20].DATAIN +itm[21] => tw[21].DATAIN +itm[22] => tw[22].DATAIN +itm[23] => tw[23].DATAIN +itm[24] => tw[24].DATAIN +itm[25] => tw[25].DATAIN +itm[26] => tw[26].DATAIN +itm[27] => tw[27].DATAIN +itm[28] => tw[28].DATAIN +itm[29] => tw[29].DATAIN +itm[30] => tw[30].DATAIN +itm[31] => tw[31].DATAIN +itm[32] => WideOr0.IN0 +itm[32] => tw[32].DATAIN +itm[33] => WideOr0.IN1 +itm[33] => tw[33].DATAIN +itm[34] => WideOr0.IN2 +itm[34] => tw[34].DATAIN +itm[35] => WideOr0.IN3 +itm[35] => tw[35].DATAIN +jrst_n => fifocount[0].ACLR +jrst_n => fifocount[1].ACLR +jrst_n => fifocount[2].ACLR +jrst_n => fifocount[3].ACLR +jrst_n => fifocount[4].ACLR +reset_n => ~NO_FANOUT~ +test_ending => test_ending.IN1 +test_has_ended => test_has_ended.IN1 +trc_on => trc_this.IN1 +tw[0] <= itm[0].DB_MAX_OUTPUT_PORT_TYPE +tw[1] <= itm[1].DB_MAX_OUTPUT_PORT_TYPE +tw[2] <= itm[2].DB_MAX_OUTPUT_PORT_TYPE +tw[3] <= itm[3].DB_MAX_OUTPUT_PORT_TYPE +tw[4] <= itm[4].DB_MAX_OUTPUT_PORT_TYPE +tw[5] <= itm[5].DB_MAX_OUTPUT_PORT_TYPE +tw[6] <= itm[6].DB_MAX_OUTPUT_PORT_TYPE +tw[7] <= itm[7].DB_MAX_OUTPUT_PORT_TYPE +tw[8] <= itm[8].DB_MAX_OUTPUT_PORT_TYPE +tw[9] <= itm[9].DB_MAX_OUTPUT_PORT_TYPE +tw[10] <= itm[10].DB_MAX_OUTPUT_PORT_TYPE +tw[11] <= itm[11].DB_MAX_OUTPUT_PORT_TYPE +tw[12] <= itm[12].DB_MAX_OUTPUT_PORT_TYPE +tw[13] <= itm[13].DB_MAX_OUTPUT_PORT_TYPE +tw[14] <= itm[14].DB_MAX_OUTPUT_PORT_TYPE +tw[15] <= itm[15].DB_MAX_OUTPUT_PORT_TYPE +tw[16] <= itm[16].DB_MAX_OUTPUT_PORT_TYPE +tw[17] <= itm[17].DB_MAX_OUTPUT_PORT_TYPE +tw[18] <= itm[18].DB_MAX_OUTPUT_PORT_TYPE +tw[19] <= itm[19].DB_MAX_OUTPUT_PORT_TYPE +tw[20] <= itm[20].DB_MAX_OUTPUT_PORT_TYPE +tw[21] <= itm[21].DB_MAX_OUTPUT_PORT_TYPE +tw[22] <= itm[22].DB_MAX_OUTPUT_PORT_TYPE +tw[23] <= itm[23].DB_MAX_OUTPUT_PORT_TYPE +tw[24] <= itm[24].DB_MAX_OUTPUT_PORT_TYPE +tw[25] <= itm[25].DB_MAX_OUTPUT_PORT_TYPE +tw[26] <= itm[26].DB_MAX_OUTPUT_PORT_TYPE +tw[27] <= itm[27].DB_MAX_OUTPUT_PORT_TYPE +tw[28] <= itm[28].DB_MAX_OUTPUT_PORT_TYPE +tw[29] <= itm[29].DB_MAX_OUTPUT_PORT_TYPE +tw[30] <= itm[30].DB_MAX_OUTPUT_PORT_TYPE +tw[31] <= itm[31].DB_MAX_OUTPUT_PORT_TYPE +tw[32] <= itm[32].DB_MAX_OUTPUT_PORT_TYPE +tw[33] <= itm[33].DB_MAX_OUTPUT_PORT_TYPE +tw[34] <= itm[34].DB_MAX_OUTPUT_PORT_TYPE +tw[35] <= itm[35].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count +atm_valid => Decoder0.IN1 +dtm_valid => Decoder0.IN2 +itm_valid => Decoder0.IN0 +compute_tm_count[0] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +compute_tm_count[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp +free2 => always0.IN1 +free3 => always0.IN1 +tm_count[0] => LessThan0.IN4 +tm_count[0] => LessThan1.IN4 +tm_count[0] => Equal0.IN1 +tm_count[1] => LessThan0.IN3 +tm_count[1] => LessThan1.IN3 +tm_count[1] => Equal0.IN0 +fifowp_inc[0] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE +fifowp_inc[1] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE +fifowp_inc[2] <= +fifowp_inc[3] <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +free2 => always0.IN1 +free3 => always0.IN1 +tm_count[0] => LessThan0.IN4 +tm_count[0] => LessThan1.IN4 +tm_count[0] => fifocount_inc.DATAB +tm_count[0] => Equal0.IN1 +tm_count[1] => LessThan0.IN3 +tm_count[1] => LessThan1.IN3 +tm_count[1] => fifocount_inc.DATAB +tm_count[1] => Equal0.IN0 +fifocount_inc[0] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[1] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[2] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[3] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[4] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench +dct_buffer[0] => ~NO_FANOUT~ +dct_buffer[1] => ~NO_FANOUT~ +dct_buffer[2] => ~NO_FANOUT~ +dct_buffer[3] => ~NO_FANOUT~ +dct_buffer[4] => ~NO_FANOUT~ +dct_buffer[5] => ~NO_FANOUT~ +dct_buffer[6] => ~NO_FANOUT~ +dct_buffer[7] => ~NO_FANOUT~ +dct_buffer[8] => ~NO_FANOUT~ +dct_buffer[9] => ~NO_FANOUT~ +dct_buffer[10] => ~NO_FANOUT~ +dct_buffer[11] => ~NO_FANOUT~ +dct_buffer[12] => ~NO_FANOUT~ +dct_buffer[13] => ~NO_FANOUT~ +dct_buffer[14] => ~NO_FANOUT~ +dct_buffer[15] => ~NO_FANOUT~ +dct_buffer[16] => ~NO_FANOUT~ +dct_buffer[17] => ~NO_FANOUT~ +dct_buffer[18] => ~NO_FANOUT~ +dct_buffer[19] => ~NO_FANOUT~ +dct_buffer[20] => ~NO_FANOUT~ +dct_buffer[21] => ~NO_FANOUT~ +dct_buffer[22] => ~NO_FANOUT~ +dct_buffer[23] => ~NO_FANOUT~ +dct_buffer[24] => ~NO_FANOUT~ +dct_buffer[25] => ~NO_FANOUT~ +dct_buffer[26] => ~NO_FANOUT~ +dct_buffer[27] => ~NO_FANOUT~ +dct_buffer[28] => ~NO_FANOUT~ +dct_buffer[29] => ~NO_FANOUT~ +dct_count[0] => ~NO_FANOUT~ +dct_count[1] => ~NO_FANOUT~ +dct_count[2] => ~NO_FANOUT~ +dct_count[3] => ~NO_FANOUT~ +test_ending => ~NO_FANOUT~ +test_has_ended => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib +clk => ~NO_FANOUT~ +clkx2 => ~NO_FANOUT~ +jrst_n => ~NO_FANOUT~ +tw[0] => ~NO_FANOUT~ +tw[1] => ~NO_FANOUT~ +tw[2] => ~NO_FANOUT~ +tw[3] => ~NO_FANOUT~ +tw[4] => ~NO_FANOUT~ +tw[5] => ~NO_FANOUT~ +tw[6] => ~NO_FANOUT~ +tw[7] => ~NO_FANOUT~ +tw[8] => ~NO_FANOUT~ +tw[9] => ~NO_FANOUT~ +tw[10] => ~NO_FANOUT~ +tw[11] => ~NO_FANOUT~ +tw[12] => ~NO_FANOUT~ +tw[13] => ~NO_FANOUT~ +tw[14] => ~NO_FANOUT~ +tw[15] => ~NO_FANOUT~ +tw[16] => ~NO_FANOUT~ +tw[17] => ~NO_FANOUT~ +tw[18] => ~NO_FANOUT~ +tw[19] => ~NO_FANOUT~ +tw[20] => ~NO_FANOUT~ +tw[21] => ~NO_FANOUT~ +tw[22] => ~NO_FANOUT~ +tw[23] => ~NO_FANOUT~ +tw[24] => ~NO_FANOUT~ +tw[25] => ~NO_FANOUT~ +tw[26] => ~NO_FANOUT~ +tw[27] => ~NO_FANOUT~ +tw[28] => ~NO_FANOUT~ +tw[29] => ~NO_FANOUT~ +tw[30] => ~NO_FANOUT~ +tw[31] => ~NO_FANOUT~ +tw[32] => ~NO_FANOUT~ +tw[33] => ~NO_FANOUT~ +tw[34] => ~NO_FANOUT~ +tw[35] => ~NO_FANOUT~ +tr_clk <= +tr_data[0] <= +tr_data[1] <= +tr_data[2] <= +tr_data[3] <= +tr_data[4] <= +tr_data[5] <= +tr_data[6] <= +tr_data[7] <= +tr_data[8] <= +tr_data[9] <= +tr_data[10] <= +tr_data[11] <= +tr_data[12] <= +tr_data[13] <= +tr_data[14] <= +tr_data[15] <= +tr_data[16] <= +tr_data[17] <= + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im +clk => trc_wrap~reg0.CLK +clk => trc_im_addr[0]~reg0.CLK +clk => trc_im_addr[1]~reg0.CLK +clk => trc_im_addr[2]~reg0.CLK +clk => trc_im_addr[3]~reg0.CLK +clk => trc_im_addr[4]~reg0.CLK +clk => trc_im_addr[5]~reg0.CLK +clk => trc_im_addr[6]~reg0.CLK +jdo[0] => ~NO_FANOUT~ +jdo[1] => ~NO_FANOUT~ +jdo[2] => ~NO_FANOUT~ +jdo[3] => ~NO_FANOUT~ +jdo[4] => ~NO_FANOUT~ +jdo[5] => ~NO_FANOUT~ +jdo[6] => ~NO_FANOUT~ +jdo[7] => ~NO_FANOUT~ +jdo[8] => ~NO_FANOUT~ +jdo[9] => ~NO_FANOUT~ +jdo[10] => ~NO_FANOUT~ +jdo[11] => ~NO_FANOUT~ +jdo[12] => ~NO_FANOUT~ +jdo[13] => ~NO_FANOUT~ +jdo[14] => ~NO_FANOUT~ +jdo[15] => ~NO_FANOUT~ +jdo[16] => ~NO_FANOUT~ +jdo[17] => ~NO_FANOUT~ +jdo[18] => ~NO_FANOUT~ +jdo[19] => ~NO_FANOUT~ +jdo[20] => ~NO_FANOUT~ +jdo[21] => ~NO_FANOUT~ +jdo[22] => ~NO_FANOUT~ +jdo[23] => ~NO_FANOUT~ +jdo[24] => ~NO_FANOUT~ +jdo[25] => ~NO_FANOUT~ +jdo[26] => ~NO_FANOUT~ +jdo[27] => ~NO_FANOUT~ +jdo[28] => ~NO_FANOUT~ +jdo[29] => ~NO_FANOUT~ +jdo[30] => ~NO_FANOUT~ +jdo[31] => ~NO_FANOUT~ +jdo[32] => ~NO_FANOUT~ +jdo[33] => ~NO_FANOUT~ +jdo[34] => ~NO_FANOUT~ +jdo[35] => ~NO_FANOUT~ +jdo[36] => ~NO_FANOUT~ +jdo[37] => ~NO_FANOUT~ +jrst_n => trc_wrap~reg0.ACLR +jrst_n => trc_im_addr[0]~reg0.ACLR +jrst_n => trc_im_addr[1]~reg0.ACLR +jrst_n => trc_im_addr[2]~reg0.ACLR +jrst_n => trc_im_addr[3]~reg0.ACLR +jrst_n => trc_im_addr[4]~reg0.ACLR +jrst_n => trc_im_addr[5]~reg0.ACLR +jrst_n => trc_im_addr[6]~reg0.ACLR +reset_n => ~NO_FANOUT~ +take_action_tracectrl => ~NO_FANOUT~ +take_action_tracemem_a => ~NO_FANOUT~ +take_action_tracemem_b => ~NO_FANOUT~ +take_no_action_tracemem_a => ~NO_FANOUT~ +trc_ctrl[0] => tracemem_on.DATAIN +trc_ctrl[0] => trc_enb.DATAIN +trc_ctrl[1] => ~NO_FANOUT~ +trc_ctrl[2] => ~NO_FANOUT~ +trc_ctrl[3] => ~NO_FANOUT~ +trc_ctrl[4] => ~NO_FANOUT~ +trc_ctrl[5] => ~NO_FANOUT~ +trc_ctrl[6] => ~NO_FANOUT~ +trc_ctrl[7] => ~NO_FANOUT~ +trc_ctrl[8] => ~NO_FANOUT~ +trc_ctrl[9] => ~NO_FANOUT~ +trc_ctrl[10] => xbrk_wrap_traceoff.IN1 +trc_ctrl[11] => ~NO_FANOUT~ +trc_ctrl[12] => ~NO_FANOUT~ +trc_ctrl[13] => ~NO_FANOUT~ +trc_ctrl[14] => ~NO_FANOUT~ +trc_ctrl[15] => ~NO_FANOUT~ +tw[0] => ~NO_FANOUT~ +tw[1] => ~NO_FANOUT~ +tw[2] => ~NO_FANOUT~ +tw[3] => ~NO_FANOUT~ +tw[4] => ~NO_FANOUT~ +tw[5] => ~NO_FANOUT~ +tw[6] => ~NO_FANOUT~ +tw[7] => ~NO_FANOUT~ +tw[8] => ~NO_FANOUT~ +tw[9] => ~NO_FANOUT~ +tw[10] => ~NO_FANOUT~ +tw[11] => ~NO_FANOUT~ +tw[12] => ~NO_FANOUT~ +tw[13] => ~NO_FANOUT~ +tw[14] => ~NO_FANOUT~ +tw[15] => ~NO_FANOUT~ +tw[16] => ~NO_FANOUT~ +tw[17] => ~NO_FANOUT~ +tw[18] => ~NO_FANOUT~ +tw[19] => ~NO_FANOUT~ +tw[20] => ~NO_FANOUT~ +tw[21] => ~NO_FANOUT~ +tw[22] => ~NO_FANOUT~ +tw[23] => ~NO_FANOUT~ +tw[24] => ~NO_FANOUT~ +tw[25] => ~NO_FANOUT~ +tw[26] => ~NO_FANOUT~ +tw[27] => ~NO_FANOUT~ +tw[28] => ~NO_FANOUT~ +tw[29] => ~NO_FANOUT~ +tw[30] => ~NO_FANOUT~ +tw[31] => ~NO_FANOUT~ +tw[32] => ~NO_FANOUT~ +tw[33] => ~NO_FANOUT~ +tw[34] => ~NO_FANOUT~ +tw[35] => ~NO_FANOUT~ +tracemem_on <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE +tracemem_trcdata[0] <= +tracemem_trcdata[1] <= +tracemem_trcdata[2] <= +tracemem_trcdata[3] <= +tracemem_trcdata[4] <= +tracemem_trcdata[5] <= +tracemem_trcdata[6] <= +tracemem_trcdata[7] <= +tracemem_trcdata[8] <= +tracemem_trcdata[9] <= +tracemem_trcdata[10] <= +tracemem_trcdata[11] <= +tracemem_trcdata[12] <= +tracemem_trcdata[13] <= +tracemem_trcdata[14] <= +tracemem_trcdata[15] <= +tracemem_trcdata[16] <= +tracemem_trcdata[17] <= +tracemem_trcdata[18] <= +tracemem_trcdata[19] <= +tracemem_trcdata[20] <= +tracemem_trcdata[21] <= +tracemem_trcdata[22] <= +tracemem_trcdata[23] <= +tracemem_trcdata[24] <= +tracemem_trcdata[25] <= +tracemem_trcdata[26] <= +tracemem_trcdata[27] <= +tracemem_trcdata[28] <= +tracemem_trcdata[29] <= +tracemem_trcdata[30] <= +tracemem_trcdata[31] <= +tracemem_trcdata[32] <= +tracemem_trcdata[33] <= +tracemem_trcdata[34] <= +tracemem_trcdata[35] <= +tracemem_tw <= tracemem_tw.DB_MAX_OUTPUT_PORT_TYPE +trc_enb <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[0] <= trc_im_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[1] <= trc_im_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[2] <= trc_im_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[3] <= trc_im_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[4] <= trc_im_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[5] <= trc_im_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[6] <= trc_im_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_wrap <= trc_wrap~reg0.DB_MAX_OUTPUT_PORT_TYPE +xbrk_wrap_traceoff <= xbrk_wrap_traceoff.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper +MonDReg[0] => MonDReg[0].IN1 +MonDReg[1] => MonDReg[1].IN1 +MonDReg[2] => MonDReg[2].IN1 +MonDReg[3] => MonDReg[3].IN1 +MonDReg[4] => MonDReg[4].IN1 +MonDReg[5] => MonDReg[5].IN1 +MonDReg[6] => MonDReg[6].IN1 +MonDReg[7] => MonDReg[7].IN1 +MonDReg[8] => MonDReg[8].IN1 +MonDReg[9] => MonDReg[9].IN1 +MonDReg[10] => MonDReg[10].IN1 +MonDReg[11] => MonDReg[11].IN1 +MonDReg[12] => MonDReg[12].IN1 +MonDReg[13] => MonDReg[13].IN1 +MonDReg[14] => MonDReg[14].IN1 +MonDReg[15] => MonDReg[15].IN1 +MonDReg[16] => MonDReg[16].IN1 +MonDReg[17] => MonDReg[17].IN1 +MonDReg[18] => MonDReg[18].IN1 +MonDReg[19] => MonDReg[19].IN1 +MonDReg[20] => MonDReg[20].IN1 +MonDReg[21] => MonDReg[21].IN1 +MonDReg[22] => MonDReg[22].IN1 +MonDReg[23] => MonDReg[23].IN1 +MonDReg[24] => MonDReg[24].IN1 +MonDReg[25] => MonDReg[25].IN1 +MonDReg[26] => MonDReg[26].IN1 +MonDReg[27] => MonDReg[27].IN1 +MonDReg[28] => MonDReg[28].IN1 +MonDReg[29] => MonDReg[29].IN1 +MonDReg[30] => MonDReg[30].IN1 +MonDReg[31] => MonDReg[31].IN1 +break_readreg[0] => break_readreg[0].IN1 +break_readreg[1] => break_readreg[1].IN1 +break_readreg[2] => break_readreg[2].IN1 +break_readreg[3] => break_readreg[3].IN1 +break_readreg[4] => break_readreg[4].IN1 +break_readreg[5] => break_readreg[5].IN1 +break_readreg[6] => break_readreg[6].IN1 +break_readreg[7] => break_readreg[7].IN1 +break_readreg[8] => break_readreg[8].IN1 +break_readreg[9] => break_readreg[9].IN1 +break_readreg[10] => break_readreg[10].IN1 +break_readreg[11] => break_readreg[11].IN1 +break_readreg[12] => break_readreg[12].IN1 +break_readreg[13] => break_readreg[13].IN1 +break_readreg[14] => break_readreg[14].IN1 +break_readreg[15] => break_readreg[15].IN1 +break_readreg[16] => break_readreg[16].IN1 +break_readreg[17] => break_readreg[17].IN1 +break_readreg[18] => break_readreg[18].IN1 +break_readreg[19] => break_readreg[19].IN1 +break_readreg[20] => break_readreg[20].IN1 +break_readreg[21] => break_readreg[21].IN1 +break_readreg[22] => break_readreg[22].IN1 +break_readreg[23] => break_readreg[23].IN1 +break_readreg[24] => break_readreg[24].IN1 +break_readreg[25] => break_readreg[25].IN1 +break_readreg[26] => break_readreg[26].IN1 +break_readreg[27] => break_readreg[27].IN1 +break_readreg[28] => break_readreg[28].IN1 +break_readreg[29] => break_readreg[29].IN1 +break_readreg[30] => break_readreg[30].IN1 +break_readreg[31] => break_readreg[31].IN1 +clk => clk.IN1 +dbrk_hit0_latch => dbrk_hit0_latch.IN1 +dbrk_hit1_latch => dbrk_hit1_latch.IN1 +dbrk_hit2_latch => dbrk_hit2_latch.IN1 +dbrk_hit3_latch => dbrk_hit3_latch.IN1 +debugack => debugack.IN1 +monitor_error => monitor_error.IN1 +monitor_ready => monitor_ready.IN1 +reset_n => reset_n.IN1 +resetlatch => resetlatch.IN1 +tracemem_on => tracemem_on.IN1 +tracemem_trcdata[0] => tracemem_trcdata[0].IN1 +tracemem_trcdata[1] => tracemem_trcdata[1].IN1 +tracemem_trcdata[2] => tracemem_trcdata[2].IN1 +tracemem_trcdata[3] => tracemem_trcdata[3].IN1 +tracemem_trcdata[4] => tracemem_trcdata[4].IN1 +tracemem_trcdata[5] => tracemem_trcdata[5].IN1 +tracemem_trcdata[6] => tracemem_trcdata[6].IN1 +tracemem_trcdata[7] => tracemem_trcdata[7].IN1 +tracemem_trcdata[8] => tracemem_trcdata[8].IN1 +tracemem_trcdata[9] => tracemem_trcdata[9].IN1 +tracemem_trcdata[10] => tracemem_trcdata[10].IN1 +tracemem_trcdata[11] => tracemem_trcdata[11].IN1 +tracemem_trcdata[12] => tracemem_trcdata[12].IN1 +tracemem_trcdata[13] => tracemem_trcdata[13].IN1 +tracemem_trcdata[14] => tracemem_trcdata[14].IN1 +tracemem_trcdata[15] => tracemem_trcdata[15].IN1 +tracemem_trcdata[16] => tracemem_trcdata[16].IN1 +tracemem_trcdata[17] => tracemem_trcdata[17].IN1 +tracemem_trcdata[18] => tracemem_trcdata[18].IN1 +tracemem_trcdata[19] => tracemem_trcdata[19].IN1 +tracemem_trcdata[20] => tracemem_trcdata[20].IN1 +tracemem_trcdata[21] => tracemem_trcdata[21].IN1 +tracemem_trcdata[22] => tracemem_trcdata[22].IN1 +tracemem_trcdata[23] => tracemem_trcdata[23].IN1 +tracemem_trcdata[24] => tracemem_trcdata[24].IN1 +tracemem_trcdata[25] => tracemem_trcdata[25].IN1 +tracemem_trcdata[26] => tracemem_trcdata[26].IN1 +tracemem_trcdata[27] => tracemem_trcdata[27].IN1 +tracemem_trcdata[28] => tracemem_trcdata[28].IN1 +tracemem_trcdata[29] => tracemem_trcdata[29].IN1 +tracemem_trcdata[30] => tracemem_trcdata[30].IN1 +tracemem_trcdata[31] => tracemem_trcdata[31].IN1 +tracemem_trcdata[32] => tracemem_trcdata[32].IN1 +tracemem_trcdata[33] => tracemem_trcdata[33].IN1 +tracemem_trcdata[34] => tracemem_trcdata[34].IN1 +tracemem_trcdata[35] => tracemem_trcdata[35].IN1 +tracemem_tw => tracemem_tw.IN1 +trc_im_addr[0] => trc_im_addr[0].IN1 +trc_im_addr[1] => trc_im_addr[1].IN1 +trc_im_addr[2] => trc_im_addr[2].IN1 +trc_im_addr[3] => trc_im_addr[3].IN1 +trc_im_addr[4] => trc_im_addr[4].IN1 +trc_im_addr[5] => trc_im_addr[5].IN1 +trc_im_addr[6] => trc_im_addr[6].IN1 +trc_on => trc_on.IN1 +trc_wrap => trc_wrap.IN1 +trigbrktype => trigbrktype.IN1 +trigger_state_1 => trigger_state_1.IN1 +jdo[0] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[1] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[2] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[3] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[4] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[5] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[6] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[7] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[8] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[9] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[10] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[11] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[12] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[13] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[14] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[15] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[16] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[17] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[18] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[19] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[20] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[21] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[22] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[23] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[24] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[25] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[26] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[27] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[28] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[29] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[30] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[31] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[32] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[33] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[34] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[35] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[36] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jdo[37] <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.jdo +jrst_n <= nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck.jrst_n +st_ready_test_idle <= nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck.st_ready_test_idle +take_action_break_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_a +take_action_break_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_b +take_action_break_c <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_break_c +take_action_ocimem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_ocimem_a +take_action_ocimem_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_ocimem_b +take_action_tracectrl <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracectrl +take_action_tracemem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracemem_a +take_action_tracemem_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_action_tracemem_b +take_no_action_break_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_a +take_no_action_break_b <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_b +take_no_action_break_c <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_break_c +take_no_action_ocimem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_ocimem_a +take_no_action_tracemem_a <= nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk.take_no_action_tracemem_a + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck +MonDReg[0] => Mux36.IN0 +MonDReg[1] => Mux35.IN0 +MonDReg[2] => Mux34.IN0 +MonDReg[3] => Mux33.IN0 +MonDReg[4] => Mux32.IN0 +MonDReg[5] => Mux31.IN0 +MonDReg[6] => Mux30.IN0 +MonDReg[7] => Mux29.IN0 +MonDReg[8] => Mux28.IN1 +MonDReg[9] => Mux27.IN1 +MonDReg[10] => Mux26.IN1 +MonDReg[11] => Mux25.IN1 +MonDReg[12] => Mux24.IN1 +MonDReg[13] => Mux23.IN1 +MonDReg[14] => Mux22.IN1 +MonDReg[15] => Mux21.IN1 +MonDReg[16] => Mux20.IN1 +MonDReg[17] => Mux19.IN1 +MonDReg[18] => Mux18.IN1 +MonDReg[19] => Mux17.IN1 +MonDReg[20] => Mux16.IN1 +MonDReg[21] => Mux15.IN1 +MonDReg[22] => Mux14.IN1 +MonDReg[23] => Mux13.IN1 +MonDReg[24] => Mux12.IN1 +MonDReg[25] => Mux11.IN1 +MonDReg[26] => Mux10.IN1 +MonDReg[27] => Mux9.IN1 +MonDReg[28] => Mux8.IN1 +MonDReg[29] => Mux7.IN1 +MonDReg[30] => Mux6.IN1 +MonDReg[31] => Mux5.IN1 +break_readreg[0] => Mux36.IN1 +break_readreg[1] => Mux35.IN1 +break_readreg[2] => Mux34.IN1 +break_readreg[3] => Mux33.IN1 +break_readreg[4] => Mux32.IN1 +break_readreg[5] => Mux31.IN1 +break_readreg[6] => Mux30.IN1 +break_readreg[7] => Mux29.IN1 +break_readreg[8] => Mux28.IN2 +break_readreg[9] => Mux27.IN2 +break_readreg[10] => Mux26.IN2 +break_readreg[11] => Mux25.IN2 +break_readreg[12] => Mux24.IN2 +break_readreg[13] => Mux23.IN2 +break_readreg[14] => Mux22.IN2 +break_readreg[15] => Mux21.IN2 +break_readreg[16] => Mux20.IN2 +break_readreg[17] => Mux19.IN2 +break_readreg[18] => Mux18.IN2 +break_readreg[19] => Mux17.IN2 +break_readreg[20] => Mux16.IN2 +break_readreg[21] => Mux15.IN2 +break_readreg[22] => Mux14.IN2 +break_readreg[23] => Mux13.IN2 +break_readreg[24] => Mux12.IN2 +break_readreg[25] => Mux11.IN2 +break_readreg[26] => Mux10.IN2 +break_readreg[27] => Mux9.IN2 +break_readreg[28] => Mux8.IN2 +break_readreg[29] => Mux7.IN2 +break_readreg[30] => Mux6.IN2 +break_readreg[31] => Mux5.IN2 +dbrk_hit0_latch => Mux4.IN1 +dbrk_hit1_latch => Mux3.IN1 +dbrk_hit2_latch => Mux2.IN1 +dbrk_hit3_latch => Mux1.IN2 +debugack => debugack.IN1 +ir_in[0] => Mux0.IN3 +ir_in[0] => Mux1.IN4 +ir_in[0] => Mux2.IN3 +ir_in[0] => Mux3.IN3 +ir_in[0] => Mux4.IN3 +ir_in[0] => Mux5.IN4 +ir_in[0] => Mux6.IN4 +ir_in[0] => Mux7.IN4 +ir_in[0] => Mux8.IN4 +ir_in[0] => Mux9.IN4 +ir_in[0] => Mux10.IN4 +ir_in[0] => Mux11.IN4 +ir_in[0] => Mux12.IN4 +ir_in[0] => Mux13.IN4 +ir_in[0] => Mux14.IN4 +ir_in[0] => Mux15.IN4 +ir_in[0] => Mux16.IN4 +ir_in[0] => Mux17.IN4 +ir_in[0] => Mux18.IN4 +ir_in[0] => Mux19.IN4 +ir_in[0] => Mux20.IN4 +ir_in[0] => Mux21.IN4 +ir_in[0] => Mux22.IN4 +ir_in[0] => Mux23.IN4 +ir_in[0] => Mux24.IN4 +ir_in[0] => Mux25.IN4 +ir_in[0] => Mux26.IN4 +ir_in[0] => Mux27.IN4 +ir_in[0] => Mux28.IN4 +ir_in[0] => Mux29.IN3 +ir_in[0] => Mux30.IN3 +ir_in[0] => Mux31.IN3 +ir_in[0] => Mux32.IN3 +ir_in[0] => Mux33.IN3 +ir_in[0] => Mux34.IN3 +ir_in[0] => Mux35.IN3 +ir_in[0] => Mux36.IN3 +ir_in[0] => Mux37.IN1 +ir_in[0] => Decoder0.IN1 +ir_in[1] => Mux0.IN2 +ir_in[1] => Mux1.IN3 +ir_in[1] => Mux2.IN2 +ir_in[1] => Mux3.IN2 +ir_in[1] => Mux4.IN2 +ir_in[1] => Mux5.IN3 +ir_in[1] => Mux6.IN3 +ir_in[1] => Mux7.IN3 +ir_in[1] => Mux8.IN3 +ir_in[1] => Mux9.IN3 +ir_in[1] => Mux10.IN3 +ir_in[1] => Mux11.IN3 +ir_in[1] => Mux12.IN3 +ir_in[1] => Mux13.IN3 +ir_in[1] => Mux14.IN3 +ir_in[1] => Mux15.IN3 +ir_in[1] => Mux16.IN3 +ir_in[1] => Mux17.IN3 +ir_in[1] => Mux18.IN3 +ir_in[1] => Mux19.IN3 +ir_in[1] => Mux20.IN3 +ir_in[1] => Mux21.IN3 +ir_in[1] => Mux22.IN3 +ir_in[1] => Mux23.IN3 +ir_in[1] => Mux24.IN3 +ir_in[1] => Mux25.IN3 +ir_in[1] => Mux26.IN3 +ir_in[1] => Mux27.IN3 +ir_in[1] => Mux28.IN3 +ir_in[1] => Mux29.IN2 +ir_in[1] => Mux30.IN2 +ir_in[1] => Mux31.IN2 +ir_in[1] => Mux32.IN2 +ir_in[1] => Mux33.IN2 +ir_in[1] => Mux34.IN2 +ir_in[1] => Mux35.IN2 +ir_in[1] => Mux36.IN2 +ir_in[1] => Mux37.IN0 +ir_in[1] => Decoder0.IN0 +jtag_state_rti => st_ready_test_idle.DATAIN +monitor_error => Mux3.IN4 +monitor_ready => monitor_ready.IN1 +reset_n => ~NO_FANOUT~ +resetlatch => Mux4.IN4 +tck => tck.IN2 +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tracemem_on => Mux1.IN5 +tracemem_trcdata[0] => Mux37.IN2 +tracemem_trcdata[1] => Mux36.IN4 +tracemem_trcdata[2] => Mux35.IN4 +tracemem_trcdata[3] => Mux34.IN4 +tracemem_trcdata[4] => Mux33.IN4 +tracemem_trcdata[5] => Mux32.IN4 +tracemem_trcdata[6] => Mux31.IN4 +tracemem_trcdata[7] => Mux30.IN4 +tracemem_trcdata[8] => Mux29.IN4 +tracemem_trcdata[9] => Mux28.IN5 +tracemem_trcdata[10] => Mux27.IN5 +tracemem_trcdata[11] => Mux26.IN5 +tracemem_trcdata[12] => Mux25.IN5 +tracemem_trcdata[13] => Mux24.IN5 +tracemem_trcdata[14] => Mux23.IN5 +tracemem_trcdata[15] => Mux22.IN5 +tracemem_trcdata[16] => Mux21.IN5 +tracemem_trcdata[17] => Mux20.IN5 +tracemem_trcdata[18] => Mux19.IN5 +tracemem_trcdata[19] => Mux18.IN5 +tracemem_trcdata[20] => Mux17.IN5 +tracemem_trcdata[21] => Mux16.IN5 +tracemem_trcdata[22] => Mux15.IN5 +tracemem_trcdata[23] => Mux14.IN5 +tracemem_trcdata[24] => Mux13.IN5 +tracemem_trcdata[25] => Mux12.IN5 +tracemem_trcdata[26] => Mux11.IN5 +tracemem_trcdata[27] => Mux10.IN5 +tracemem_trcdata[28] => Mux9.IN5 +tracemem_trcdata[29] => Mux8.IN5 +tracemem_trcdata[30] => Mux7.IN5 +tracemem_trcdata[31] => Mux6.IN5 +tracemem_trcdata[32] => Mux5.IN5 +tracemem_trcdata[33] => Mux4.IN5 +tracemem_trcdata[34] => Mux3.IN5 +tracemem_trcdata[35] => Mux2.IN4 +tracemem_tw => Mux0.IN4 +trc_im_addr[0] => Mux35.IN5 +trc_im_addr[1] => Mux34.IN5 +trc_im_addr[2] => Mux33.IN5 +trc_im_addr[3] => Mux32.IN5 +trc_im_addr[4] => Mux31.IN5 +trc_im_addr[5] => Mux30.IN5 +trc_im_addr[6] => Mux29.IN5 +trc_on => Mux37.IN3 +trc_wrap => Mux36.IN5 +trigbrktype => Mux37.IN4 +trigger_state_1 => Mux0.IN5 +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +ir_out[0] <= ir_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +ir_out[1] <= ir_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jrst_n <= unxcomplemented_resetxx2.DB_MAX_OUTPUT_PORT_TYPE +sr[0] <= sr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[1] <= sr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[2] <= sr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[3] <= sr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[4] <= sr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[5] <= sr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[6] <= sr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[7] <= sr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[8] <= sr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[9] <= sr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[10] <= sr[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[11] <= sr[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[12] <= sr[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[13] <= sr[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[14] <= sr[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[15] <= sr[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[16] <= sr[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[17] <= sr[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[18] <= sr[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[19] <= sr[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[20] <= sr[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[21] <= sr[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[22] <= sr[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[23] <= sr[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[24] <= sr[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[25] <= sr[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[26] <= sr[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[27] <= sr[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[28] <= sr[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[29] <= sr[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[30] <= sr[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[31] <= sr[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[32] <= sr[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[33] <= sr[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[34] <= sr[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[35] <= sr[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[36] <= sr[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[37] <= sr[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE +st_ready_test_idle <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE +tdo <= tdo.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk +clk => clk.IN2 +ir_in[0] => ir[0].DATAIN +ir_in[1] => ir[1].DATAIN +sr[0] => jdo[0]~reg0.DATAIN +sr[1] => jdo[1]~reg0.DATAIN +sr[2] => jdo[2]~reg0.DATAIN +sr[3] => jdo[3]~reg0.DATAIN +sr[4] => jdo[4]~reg0.DATAIN +sr[5] => jdo[5]~reg0.DATAIN +sr[6] => jdo[6]~reg0.DATAIN +sr[7] => jdo[7]~reg0.DATAIN +sr[8] => jdo[8]~reg0.DATAIN +sr[9] => jdo[9]~reg0.DATAIN +sr[10] => jdo[10]~reg0.DATAIN +sr[11] => jdo[11]~reg0.DATAIN +sr[12] => jdo[12]~reg0.DATAIN +sr[13] => jdo[13]~reg0.DATAIN +sr[14] => jdo[14]~reg0.DATAIN +sr[15] => jdo[15]~reg0.DATAIN +sr[16] => jdo[16]~reg0.DATAIN +sr[17] => jdo[17]~reg0.DATAIN +sr[18] => jdo[18]~reg0.DATAIN +sr[19] => jdo[19]~reg0.DATAIN +sr[20] => jdo[20]~reg0.DATAIN +sr[21] => jdo[21]~reg0.DATAIN +sr[22] => jdo[22]~reg0.DATAIN +sr[23] => jdo[23]~reg0.DATAIN +sr[24] => jdo[24]~reg0.DATAIN +sr[25] => jdo[25]~reg0.DATAIN +sr[26] => jdo[26]~reg0.DATAIN +sr[27] => jdo[27]~reg0.DATAIN +sr[28] => jdo[28]~reg0.DATAIN +sr[29] => jdo[29]~reg0.DATAIN +sr[30] => jdo[30]~reg0.DATAIN +sr[31] => jdo[31]~reg0.DATAIN +sr[32] => jdo[32]~reg0.DATAIN +sr[33] => jdo[33]~reg0.DATAIN +sr[34] => jdo[34]~reg0.DATAIN +sr[35] => jdo[35]~reg0.DATAIN +sr[36] => jdo[36]~reg0.DATAIN +sr[37] => jdo[37]~reg0.DATAIN +vs_udr => vs_udr.IN1 +vs_uir => vs_uir.IN1 +jdo[0] <= jdo[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[1] <= jdo[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[2] <= jdo[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[3] <= jdo[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[4] <= jdo[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[5] <= jdo[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[6] <= jdo[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[7] <= jdo[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[8] <= jdo[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[9] <= jdo[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[10] <= jdo[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[11] <= jdo[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[12] <= jdo[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[13] <= jdo[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[14] <= jdo[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[15] <= jdo[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[16] <= jdo[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[17] <= jdo[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[18] <= jdo[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[19] <= jdo[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[20] <= jdo[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[21] <= jdo[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[22] <= jdo[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[23] <= jdo[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[24] <= jdo[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[25] <= jdo[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[26] <= jdo[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[27] <= jdo[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[28] <= jdo[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[29] <= jdo[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[30] <= jdo[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[31] <= jdo[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[32] <= jdo[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[33] <= jdo[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[34] <= jdo[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[35] <= jdo[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[36] <= jdo[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[37] <= jdo[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE +take_action_break_a <= take_action_break_a.DB_MAX_OUTPUT_PORT_TYPE +take_action_break_b <= take_action_break_b.DB_MAX_OUTPUT_PORT_TYPE +take_action_break_c <= take_action_break_c.DB_MAX_OUTPUT_PORT_TYPE +take_action_ocimem_a <= take_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE +take_action_ocimem_b <= take_action_ocimem_b.DB_MAX_OUTPUT_PORT_TYPE +take_action_tracectrl <= take_action_tracectrl.DB_MAX_OUTPUT_PORT_TYPE +take_action_tracemem_a <= take_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE +take_action_tracemem_b <= take_action_tracemem_b.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_break_a <= take_no_action_break_a.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_break_b <= take_no_action_break_b.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_break_c <= take_no_action_break_c.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_ocimem_a <= take_no_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_tracemem_a <= take_no_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy +tck <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tck +tdi <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tdi +ir_in[0] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in +ir_in[1] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in +tdo => tdo.IN1 +ir_out[0] => ir_out[0].IN1 +ir_out[1] => ir_out[1].IN1 +virtual_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cdr +virtual_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_sdr +virtual_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e1dr +virtual_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_pdr +virtual_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e2dr +virtual_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_udr +virtual_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cir +virtual_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_uir +tms <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tms +jtag_state_tlr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_tlr +jtag_state_rti <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_rti +jtag_state_sdrs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdrs +jtag_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cdr +jtag_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdr +jtag_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1dr +jtag_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pdr +jtag_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2dr +jtag_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_udr +jtag_state_sirs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sirs +jtag_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cir +jtag_state_sir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sir +jtag_state_e1ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1ir +jtag_state_pir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pir +jtag_state_e2ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2ir +jtag_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_uir + + +|lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst +usr_tck <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE +usr_tdi <= tdi.DB_MAX_OUTPUT_PORT_TYPE +usr_ir_in[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE +usr_ir_in[1] <= ir_in[1].DB_MAX_OUTPUT_PORT_TYPE +usr_tdo => tdo.DATAIN +usr_ir_out[0] => ir_out[0].DATAIN +usr_ir_out[1] => ir_out[1].DATAIN +usr_virtual_state_cdr <= virtual_state_cdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_sdr <= virtual_state_sdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_e1dr <= virtual_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_pdr <= virtual_state_pdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_e2dr <= virtual_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_udr <= virtual_state_udr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_cir <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_uir <= virtual_state_uir.DB_MAX_OUTPUT_PORT_TYPE +usr_tms <= raw_tms.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_tlr <= jtag_state_tlr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_rti <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sdrs <= jtag_state_sdrs.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_cdr <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sdr <= jtag_state_sdr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e1dr <= jtag_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_pdr <= jtag_state_pdr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e2dr <= jtag_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_udr <= jtag_state_udr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sirs <= jtag_state_sirs.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_cir <= jtag_state_cir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sir <= jtag_state_sir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e1ir <= jtag_state_e1ir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_pir <= jtag_state_pir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e2ir <= jtag_state_e2ir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_uir <= jtag_state_uir.DB_MAX_OUTPUT_PORT_TYPE +raw_tck => usr_tck.DATAIN +raw_tms => usr_tms.DATAIN +tdi => usr_tdi.DATAIN +jtag_state_tlr => usr_jtag_state_tlr.DATAIN +jtag_state_rti => usr_jtag_state_rti.DATAIN +jtag_state_sdrs => usr_jtag_state_sdrs.DATAIN +jtag_state_cdr => virtual_state_cdr.IN1 +jtag_state_cdr => usr_virtual_state_cir.DATAIN +jtag_state_cdr => usr_jtag_state_cdr.DATAIN +jtag_state_sdr => virtual_state_sdr.IN1 +jtag_state_sdr => usr_jtag_state_sdr.DATAIN +jtag_state_e1dr => virtual_state_e1dr.IN1 +jtag_state_e1dr => usr_jtag_state_e1dr.DATAIN +jtag_state_pdr => virtual_state_pdr.IN1 +jtag_state_pdr => usr_jtag_state_pdr.DATAIN +jtag_state_e2dr => virtual_state_e2dr.IN1 +jtag_state_e2dr => usr_jtag_state_e2dr.DATAIN +jtag_state_udr => virtual_state_udr.IN1 +jtag_state_udr => virtual_state_uir.IN1 +jtag_state_udr => usr_jtag_state_udr.DATAIN +jtag_state_sirs => usr_jtag_state_sirs.DATAIN +jtag_state_cir => usr_jtag_state_cir.DATAIN +jtag_state_sir => usr_jtag_state_sir.DATAIN +jtag_state_e1ir => usr_jtag_state_e1ir.DATAIN +jtag_state_pir => usr_jtag_state_pir.DATAIN +jtag_state_e2ir => usr_jtag_state_e2ir.DATAIN +jtag_state_uir => usr_jtag_state_uir.DATAIN +usr1 => virtual_ir_scan.IN0 +usr1 => virtual_dr_scan.IN0 +clr => ~NO_FANOUT~ +ena => virtual_dr_scan.IN1 +ena => virtual_ir_scan.IN1 +ir_in[0] => usr_ir_in[0].DATAIN +ir_in[1] => usr_ir_in[1].DATAIN +tdo <= usr_tdo.DB_MAX_OUTPUT_PORT_TYPE +ir_out[0] <= usr_ir_out[0].DB_MAX_OUTPUT_PORT_TYPE +ir_out[1] <= usr_ir_out[1].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory +address[0] => address[0].IN1 +address[1] => address[1].IN1 +address[2] => address[2].IN1 +address[3] => address[3].IN1 +address[4] => address[4].IN1 +address[5] => address[5].IN1 +address[6] => address[6].IN1 +address[7] => address[7].IN1 +address[8] => address[8].IN1 +address[9] => address[9].IN1 +address[10] => address[10].IN1 +address[11] => address[11].IN1 +address[12] => address[12].IN1 +address[13] => address[13].IN1 +address[14] => address[14].IN1 +address[15] => address[15].IN1 +byteenable[0] => byteenable[0].IN1 +byteenable[1] => byteenable[1].IN1 +byteenable[2] => byteenable[2].IN1 +byteenable[3] => byteenable[3].IN1 +chipselect => wren.IN0 +clk => clk.IN1 +clken => clocken0.IN0 +reset => ~NO_FANOUT~ +reset_req => clocken0.IN1 +write => wren.IN1 +writedata[0] => writedata[0].IN1 +writedata[1] => writedata[1].IN1 +writedata[2] => writedata[2].IN1 +writedata[3] => writedata[3].IN1 +writedata[4] => writedata[4].IN1 +writedata[5] => writedata[5].IN1 +writedata[6] => writedata[6].IN1 +writedata[7] => writedata[7].IN1 +writedata[8] => writedata[8].IN1 +writedata[9] => writedata[9].IN1 +writedata[10] => writedata[10].IN1 +writedata[11] => writedata[11].IN1 +writedata[12] => writedata[12].IN1 +writedata[13] => writedata[13].IN1 +writedata[14] => writedata[14].IN1 +writedata[15] => writedata[15].IN1 +writedata[16] => writedata[16].IN1 +writedata[17] => writedata[17].IN1 +writedata[18] => writedata[18].IN1 +writedata[19] => writedata[19].IN1 +writedata[20] => writedata[20].IN1 +writedata[21] => writedata[21].IN1 +writedata[22] => writedata[22].IN1 +writedata[23] => writedata[23].IN1 +writedata[24] => writedata[24].IN1 +writedata[25] => writedata[25].IN1 +writedata[26] => writedata[26].IN1 +writedata[27] => writedata[27].IN1 +writedata[28] => writedata[28].IN1 +writedata[29] => writedata[29].IN1 +writedata[30] => writedata[30].IN1 +writedata[31] => writedata[31].IN1 +readdata[0] <= altsyncram:the_altsyncram.q_a +readdata[1] <= altsyncram:the_altsyncram.q_a +readdata[2] <= altsyncram:the_altsyncram.q_a +readdata[3] <= altsyncram:the_altsyncram.q_a +readdata[4] <= altsyncram:the_altsyncram.q_a +readdata[5] <= altsyncram:the_altsyncram.q_a +readdata[6] <= altsyncram:the_altsyncram.q_a +readdata[7] <= altsyncram:the_altsyncram.q_a +readdata[8] <= altsyncram:the_altsyncram.q_a +readdata[9] <= altsyncram:the_altsyncram.q_a +readdata[10] <= altsyncram:the_altsyncram.q_a +readdata[11] <= altsyncram:the_altsyncram.q_a +readdata[12] <= altsyncram:the_altsyncram.q_a +readdata[13] <= altsyncram:the_altsyncram.q_a +readdata[14] <= altsyncram:the_altsyncram.q_a +readdata[15] <= altsyncram:the_altsyncram.q_a +readdata[16] <= altsyncram:the_altsyncram.q_a +readdata[17] <= altsyncram:the_altsyncram.q_a +readdata[18] <= altsyncram:the_altsyncram.q_a +readdata[19] <= altsyncram:the_altsyncram.q_a +readdata[20] <= altsyncram:the_altsyncram.q_a +readdata[21] <= altsyncram:the_altsyncram.q_a +readdata[22] <= altsyncram:the_altsyncram.q_a +readdata[23] <= altsyncram:the_altsyncram.q_a +readdata[24] <= altsyncram:the_altsyncram.q_a +readdata[25] <= altsyncram:the_altsyncram.q_a +readdata[26] <= altsyncram:the_altsyncram.q_a +readdata[27] <= altsyncram:the_altsyncram.q_a +readdata[28] <= altsyncram:the_altsyncram.q_a +readdata[29] <= altsyncram:the_altsyncram.q_a +readdata[30] <= altsyncram:the_altsyncram.q_a +readdata[31] <= altsyncram:the_altsyncram.q_a + + +|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram +wren_a => altsyncram_4ed1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_4ed1:auto_generated.data_a[0] +data_a[1] => altsyncram_4ed1:auto_generated.data_a[1] +data_a[2] => altsyncram_4ed1:auto_generated.data_a[2] +data_a[3] => altsyncram_4ed1:auto_generated.data_a[3] +data_a[4] => altsyncram_4ed1:auto_generated.data_a[4] +data_a[5] => altsyncram_4ed1:auto_generated.data_a[5] +data_a[6] => altsyncram_4ed1:auto_generated.data_a[6] +data_a[7] => altsyncram_4ed1:auto_generated.data_a[7] +data_a[8] => altsyncram_4ed1:auto_generated.data_a[8] +data_a[9] => altsyncram_4ed1:auto_generated.data_a[9] +data_a[10] => altsyncram_4ed1:auto_generated.data_a[10] +data_a[11] => altsyncram_4ed1:auto_generated.data_a[11] +data_a[12] => altsyncram_4ed1:auto_generated.data_a[12] +data_a[13] => altsyncram_4ed1:auto_generated.data_a[13] +data_a[14] => altsyncram_4ed1:auto_generated.data_a[14] +data_a[15] => altsyncram_4ed1:auto_generated.data_a[15] +data_a[16] => altsyncram_4ed1:auto_generated.data_a[16] +data_a[17] => altsyncram_4ed1:auto_generated.data_a[17] +data_a[18] => altsyncram_4ed1:auto_generated.data_a[18] +data_a[19] => altsyncram_4ed1:auto_generated.data_a[19] +data_a[20] => altsyncram_4ed1:auto_generated.data_a[20] +data_a[21] => altsyncram_4ed1:auto_generated.data_a[21] +data_a[22] => altsyncram_4ed1:auto_generated.data_a[22] +data_a[23] => altsyncram_4ed1:auto_generated.data_a[23] +data_a[24] => altsyncram_4ed1:auto_generated.data_a[24] +data_a[25] => altsyncram_4ed1:auto_generated.data_a[25] +data_a[26] => altsyncram_4ed1:auto_generated.data_a[26] +data_a[27] => altsyncram_4ed1:auto_generated.data_a[27] +data_a[28] => altsyncram_4ed1:auto_generated.data_a[28] +data_a[29] => altsyncram_4ed1:auto_generated.data_a[29] +data_a[30] => altsyncram_4ed1:auto_generated.data_a[30] +data_a[31] => altsyncram_4ed1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +address_a[0] => altsyncram_4ed1:auto_generated.address_a[0] +address_a[1] => altsyncram_4ed1:auto_generated.address_a[1] +address_a[2] => altsyncram_4ed1:auto_generated.address_a[2] +address_a[3] => altsyncram_4ed1:auto_generated.address_a[3] +address_a[4] => altsyncram_4ed1:auto_generated.address_a[4] +address_a[5] => altsyncram_4ed1:auto_generated.address_a[5] +address_a[6] => altsyncram_4ed1:auto_generated.address_a[6] +address_a[7] => altsyncram_4ed1:auto_generated.address_a[7] +address_a[8] => altsyncram_4ed1:auto_generated.address_a[8] +address_a[9] => altsyncram_4ed1:auto_generated.address_a[9] +address_a[10] => altsyncram_4ed1:auto_generated.address_a[10] +address_a[11] => altsyncram_4ed1:auto_generated.address_a[11] +address_a[12] => altsyncram_4ed1:auto_generated.address_a[12] +address_a[13] => altsyncram_4ed1:auto_generated.address_a[13] +address_a[14] => altsyncram_4ed1:auto_generated.address_a[14] +address_a[15] => altsyncram_4ed1:auto_generated.address_a[15] +address_b[0] => ~NO_FANOUT~ +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_4ed1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => altsyncram_4ed1:auto_generated.clocken0 +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => altsyncram_4ed1:auto_generated.byteena_a[0] +byteena_a[1] => altsyncram_4ed1:auto_generated.byteena_a[1] +byteena_a[2] => altsyncram_4ed1:auto_generated.byteena_a[2] +byteena_a[3] => altsyncram_4ed1:auto_generated.byteena_a[3] +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_4ed1:auto_generated.q_a[0] +q_a[1] <= altsyncram_4ed1:auto_generated.q_a[1] +q_a[2] <= altsyncram_4ed1:auto_generated.q_a[2] +q_a[3] <= altsyncram_4ed1:auto_generated.q_a[3] +q_a[4] <= altsyncram_4ed1:auto_generated.q_a[4] +q_a[5] <= altsyncram_4ed1:auto_generated.q_a[5] +q_a[6] <= altsyncram_4ed1:auto_generated.q_a[6] +q_a[7] <= altsyncram_4ed1:auto_generated.q_a[7] +q_a[8] <= altsyncram_4ed1:auto_generated.q_a[8] +q_a[9] <= altsyncram_4ed1:auto_generated.q_a[9] +q_a[10] <= altsyncram_4ed1:auto_generated.q_a[10] +q_a[11] <= altsyncram_4ed1:auto_generated.q_a[11] +q_a[12] <= altsyncram_4ed1:auto_generated.q_a[12] +q_a[13] <= altsyncram_4ed1:auto_generated.q_a[13] +q_a[14] <= altsyncram_4ed1:auto_generated.q_a[14] +q_a[15] <= altsyncram_4ed1:auto_generated.q_a[15] +q_a[16] <= altsyncram_4ed1:auto_generated.q_a[16] +q_a[17] <= altsyncram_4ed1:auto_generated.q_a[17] +q_a[18] <= altsyncram_4ed1:auto_generated.q_a[18] +q_a[19] <= altsyncram_4ed1:auto_generated.q_a[19] +q_a[20] <= altsyncram_4ed1:auto_generated.q_a[20] +q_a[21] <= altsyncram_4ed1:auto_generated.q_a[21] +q_a[22] <= altsyncram_4ed1:auto_generated.q_a[22] +q_a[23] <= altsyncram_4ed1:auto_generated.q_a[23] +q_a[24] <= altsyncram_4ed1:auto_generated.q_a[24] +q_a[25] <= altsyncram_4ed1:auto_generated.q_a[25] +q_a[26] <= altsyncram_4ed1:auto_generated.q_a[26] +q_a[27] <= altsyncram_4ed1:auto_generated.q_a[27] +q_a[28] <= altsyncram_4ed1:auto_generated.q_a[28] +q_a[29] <= altsyncram_4ed1:auto_generated.q_a[29] +q_a[30] <= altsyncram_4ed1:auto_generated.q_a[30] +q_a[31] <= altsyncram_4ed1:auto_generated.q_a[31] +q_b[0] <= +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[0] => ram_block1a32.PORTAADDR +address_a[0] => ram_block1a33.PORTAADDR +address_a[0] => ram_block1a34.PORTAADDR +address_a[0] => ram_block1a35.PORTAADDR +address_a[0] => ram_block1a36.PORTAADDR +address_a[0] => ram_block1a37.PORTAADDR +address_a[0] => ram_block1a38.PORTAADDR +address_a[0] => ram_block1a39.PORTAADDR +address_a[0] => ram_block1a40.PORTAADDR +address_a[0] => ram_block1a41.PORTAADDR +address_a[0] => ram_block1a42.PORTAADDR +address_a[0] => ram_block1a43.PORTAADDR +address_a[0] => ram_block1a44.PORTAADDR +address_a[0] => ram_block1a45.PORTAADDR +address_a[0] => ram_block1a46.PORTAADDR +address_a[0] => ram_block1a47.PORTAADDR +address_a[0] => ram_block1a48.PORTAADDR +address_a[0] => ram_block1a49.PORTAADDR +address_a[0] => ram_block1a50.PORTAADDR +address_a[0] => ram_block1a51.PORTAADDR +address_a[0] => ram_block1a52.PORTAADDR +address_a[0] => ram_block1a53.PORTAADDR +address_a[0] => ram_block1a54.PORTAADDR +address_a[0] => ram_block1a55.PORTAADDR +address_a[0] => ram_block1a56.PORTAADDR +address_a[0] => ram_block1a57.PORTAADDR +address_a[0] => ram_block1a58.PORTAADDR +address_a[0] => ram_block1a59.PORTAADDR +address_a[0] => ram_block1a60.PORTAADDR +address_a[0] => ram_block1a61.PORTAADDR +address_a[0] => ram_block1a62.PORTAADDR +address_a[0] => ram_block1a63.PORTAADDR +address_a[0] => ram_block1a64.PORTAADDR +address_a[0] => ram_block1a65.PORTAADDR +address_a[0] => ram_block1a66.PORTAADDR +address_a[0] => ram_block1a67.PORTAADDR +address_a[0] => ram_block1a68.PORTAADDR +address_a[0] => ram_block1a69.PORTAADDR +address_a[0] => ram_block1a70.PORTAADDR +address_a[0] => ram_block1a71.PORTAADDR +address_a[0] => ram_block1a72.PORTAADDR +address_a[0] => ram_block1a73.PORTAADDR +address_a[0] => ram_block1a74.PORTAADDR +address_a[0] => ram_block1a75.PORTAADDR +address_a[0] => ram_block1a76.PORTAADDR +address_a[0] => ram_block1a77.PORTAADDR +address_a[0] => ram_block1a78.PORTAADDR +address_a[0] => ram_block1a79.PORTAADDR +address_a[0] => ram_block1a80.PORTAADDR +address_a[0] => ram_block1a81.PORTAADDR +address_a[0] => ram_block1a82.PORTAADDR +address_a[0] => ram_block1a83.PORTAADDR +address_a[0] => ram_block1a84.PORTAADDR +address_a[0] => ram_block1a85.PORTAADDR +address_a[0] => ram_block1a86.PORTAADDR +address_a[0] => ram_block1a87.PORTAADDR +address_a[0] => ram_block1a88.PORTAADDR +address_a[0] => ram_block1a89.PORTAADDR +address_a[0] => ram_block1a90.PORTAADDR +address_a[0] => ram_block1a91.PORTAADDR +address_a[0] => ram_block1a92.PORTAADDR +address_a[0] => ram_block1a93.PORTAADDR +address_a[0] => ram_block1a94.PORTAADDR +address_a[0] => ram_block1a95.PORTAADDR +address_a[0] => ram_block1a96.PORTAADDR +address_a[0] => ram_block1a97.PORTAADDR +address_a[0] => ram_block1a98.PORTAADDR +address_a[0] => ram_block1a99.PORTAADDR +address_a[0] => ram_block1a100.PORTAADDR +address_a[0] => ram_block1a101.PORTAADDR +address_a[0] => ram_block1a102.PORTAADDR +address_a[0] => ram_block1a103.PORTAADDR +address_a[0] => ram_block1a104.PORTAADDR +address_a[0] => ram_block1a105.PORTAADDR +address_a[0] => ram_block1a106.PORTAADDR +address_a[0] => ram_block1a107.PORTAADDR +address_a[0] => ram_block1a108.PORTAADDR +address_a[0] => ram_block1a109.PORTAADDR +address_a[0] => ram_block1a110.PORTAADDR +address_a[0] => ram_block1a111.PORTAADDR +address_a[0] => ram_block1a112.PORTAADDR +address_a[0] => ram_block1a113.PORTAADDR +address_a[0] => ram_block1a114.PORTAADDR +address_a[0] => ram_block1a115.PORTAADDR +address_a[0] => ram_block1a116.PORTAADDR +address_a[0] => ram_block1a117.PORTAADDR +address_a[0] => ram_block1a118.PORTAADDR +address_a[0] => ram_block1a119.PORTAADDR +address_a[0] => ram_block1a120.PORTAADDR +address_a[0] => ram_block1a121.PORTAADDR +address_a[0] => ram_block1a122.PORTAADDR +address_a[0] => ram_block1a123.PORTAADDR +address_a[0] => ram_block1a124.PORTAADDR +address_a[0] => ram_block1a125.PORTAADDR +address_a[0] => ram_block1a126.PORTAADDR +address_a[0] => ram_block1a127.PORTAADDR +address_a[0] => ram_block1a128.PORTAADDR +address_a[0] => ram_block1a129.PORTAADDR +address_a[0] => ram_block1a130.PORTAADDR +address_a[0] => ram_block1a131.PORTAADDR +address_a[0] => ram_block1a132.PORTAADDR +address_a[0] => ram_block1a133.PORTAADDR +address_a[0] => ram_block1a134.PORTAADDR +address_a[0] => ram_block1a135.PORTAADDR +address_a[0] => ram_block1a136.PORTAADDR +address_a[0] => ram_block1a137.PORTAADDR +address_a[0] => ram_block1a138.PORTAADDR +address_a[0] => ram_block1a139.PORTAADDR +address_a[0] => ram_block1a140.PORTAADDR +address_a[0] => ram_block1a141.PORTAADDR +address_a[0] => ram_block1a142.PORTAADDR +address_a[0] => ram_block1a143.PORTAADDR +address_a[0] => ram_block1a144.PORTAADDR +address_a[0] => ram_block1a145.PORTAADDR +address_a[0] => ram_block1a146.PORTAADDR +address_a[0] => ram_block1a147.PORTAADDR +address_a[0] => ram_block1a148.PORTAADDR +address_a[0] => ram_block1a149.PORTAADDR +address_a[0] => ram_block1a150.PORTAADDR +address_a[0] => ram_block1a151.PORTAADDR +address_a[0] => ram_block1a152.PORTAADDR +address_a[0] => ram_block1a153.PORTAADDR +address_a[0] => ram_block1a154.PORTAADDR +address_a[0] => ram_block1a155.PORTAADDR +address_a[0] => ram_block1a156.PORTAADDR +address_a[0] => ram_block1a157.PORTAADDR +address_a[0] => ram_block1a158.PORTAADDR +address_a[0] => ram_block1a159.PORTAADDR +address_a[0] => ram_block1a160.PORTAADDR +address_a[0] => ram_block1a161.PORTAADDR +address_a[0] => ram_block1a162.PORTAADDR +address_a[0] => ram_block1a163.PORTAADDR +address_a[0] => ram_block1a164.PORTAADDR +address_a[0] => ram_block1a165.PORTAADDR +address_a[0] => ram_block1a166.PORTAADDR +address_a[0] => ram_block1a167.PORTAADDR +address_a[0] => ram_block1a168.PORTAADDR +address_a[0] => ram_block1a169.PORTAADDR +address_a[0] => ram_block1a170.PORTAADDR +address_a[0] => ram_block1a171.PORTAADDR +address_a[0] => ram_block1a172.PORTAADDR +address_a[0] => ram_block1a173.PORTAADDR +address_a[0] => ram_block1a174.PORTAADDR +address_a[0] => ram_block1a175.PORTAADDR +address_a[0] => ram_block1a176.PORTAADDR +address_a[0] => ram_block1a177.PORTAADDR +address_a[0] => ram_block1a178.PORTAADDR +address_a[0] => ram_block1a179.PORTAADDR +address_a[0] => ram_block1a180.PORTAADDR +address_a[0] => ram_block1a181.PORTAADDR +address_a[0] => ram_block1a182.PORTAADDR +address_a[0] => ram_block1a183.PORTAADDR +address_a[0] => ram_block1a184.PORTAADDR +address_a[0] => ram_block1a185.PORTAADDR +address_a[0] => ram_block1a186.PORTAADDR +address_a[0] => ram_block1a187.PORTAADDR +address_a[0] => ram_block1a188.PORTAADDR +address_a[0] => ram_block1a189.PORTAADDR +address_a[0] => ram_block1a190.PORTAADDR +address_a[0] => ram_block1a191.PORTAADDR +address_a[0] => ram_block1a192.PORTAADDR +address_a[0] => ram_block1a193.PORTAADDR +address_a[0] => ram_block1a194.PORTAADDR +address_a[0] => ram_block1a195.PORTAADDR +address_a[0] => ram_block1a196.PORTAADDR +address_a[0] => ram_block1a197.PORTAADDR +address_a[0] => ram_block1a198.PORTAADDR +address_a[0] => ram_block1a199.PORTAADDR +address_a[0] => ram_block1a200.PORTAADDR +address_a[0] => ram_block1a201.PORTAADDR +address_a[0] => ram_block1a202.PORTAADDR +address_a[0] => ram_block1a203.PORTAADDR +address_a[0] => ram_block1a204.PORTAADDR +address_a[0] => ram_block1a205.PORTAADDR +address_a[0] => ram_block1a206.PORTAADDR +address_a[0] => ram_block1a207.PORTAADDR +address_a[0] => ram_block1a208.PORTAADDR +address_a[0] => ram_block1a209.PORTAADDR +address_a[0] => ram_block1a210.PORTAADDR +address_a[0] => ram_block1a211.PORTAADDR +address_a[0] => ram_block1a212.PORTAADDR +address_a[0] => ram_block1a213.PORTAADDR +address_a[0] => ram_block1a214.PORTAADDR +address_a[0] => ram_block1a215.PORTAADDR +address_a[0] => ram_block1a216.PORTAADDR +address_a[0] => ram_block1a217.PORTAADDR +address_a[0] => ram_block1a218.PORTAADDR +address_a[0] => ram_block1a219.PORTAADDR +address_a[0] => ram_block1a220.PORTAADDR +address_a[0] => ram_block1a221.PORTAADDR +address_a[0] => ram_block1a222.PORTAADDR +address_a[0] => ram_block1a223.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[1] => ram_block1a32.PORTAADDR1 +address_a[1] => ram_block1a33.PORTAADDR1 +address_a[1] => ram_block1a34.PORTAADDR1 +address_a[1] => ram_block1a35.PORTAADDR1 +address_a[1] => ram_block1a36.PORTAADDR1 +address_a[1] => ram_block1a37.PORTAADDR1 +address_a[1] => ram_block1a38.PORTAADDR1 +address_a[1] => ram_block1a39.PORTAADDR1 +address_a[1] => ram_block1a40.PORTAADDR1 +address_a[1] => ram_block1a41.PORTAADDR1 +address_a[1] => ram_block1a42.PORTAADDR1 +address_a[1] => ram_block1a43.PORTAADDR1 +address_a[1] => ram_block1a44.PORTAADDR1 +address_a[1] => ram_block1a45.PORTAADDR1 +address_a[1] => ram_block1a46.PORTAADDR1 +address_a[1] => ram_block1a47.PORTAADDR1 +address_a[1] => ram_block1a48.PORTAADDR1 +address_a[1] => ram_block1a49.PORTAADDR1 +address_a[1] => ram_block1a50.PORTAADDR1 +address_a[1] => ram_block1a51.PORTAADDR1 +address_a[1] => ram_block1a52.PORTAADDR1 +address_a[1] => ram_block1a53.PORTAADDR1 +address_a[1] => ram_block1a54.PORTAADDR1 +address_a[1] => ram_block1a55.PORTAADDR1 +address_a[1] => ram_block1a56.PORTAADDR1 +address_a[1] => ram_block1a57.PORTAADDR1 +address_a[1] => ram_block1a58.PORTAADDR1 +address_a[1] => ram_block1a59.PORTAADDR1 +address_a[1] => ram_block1a60.PORTAADDR1 +address_a[1] => ram_block1a61.PORTAADDR1 +address_a[1] => ram_block1a62.PORTAADDR1 +address_a[1] => ram_block1a63.PORTAADDR1 +address_a[1] => ram_block1a64.PORTAADDR1 +address_a[1] => ram_block1a65.PORTAADDR1 +address_a[1] => ram_block1a66.PORTAADDR1 +address_a[1] => ram_block1a67.PORTAADDR1 +address_a[1] => ram_block1a68.PORTAADDR1 +address_a[1] => ram_block1a69.PORTAADDR1 +address_a[1] => ram_block1a70.PORTAADDR1 +address_a[1] => ram_block1a71.PORTAADDR1 +address_a[1] => ram_block1a72.PORTAADDR1 +address_a[1] => ram_block1a73.PORTAADDR1 +address_a[1] => ram_block1a74.PORTAADDR1 +address_a[1] => ram_block1a75.PORTAADDR1 +address_a[1] => ram_block1a76.PORTAADDR1 +address_a[1] => ram_block1a77.PORTAADDR1 +address_a[1] => ram_block1a78.PORTAADDR1 +address_a[1] => ram_block1a79.PORTAADDR1 +address_a[1] => ram_block1a80.PORTAADDR1 +address_a[1] => ram_block1a81.PORTAADDR1 +address_a[1] => ram_block1a82.PORTAADDR1 +address_a[1] => ram_block1a83.PORTAADDR1 +address_a[1] => ram_block1a84.PORTAADDR1 +address_a[1] => ram_block1a85.PORTAADDR1 +address_a[1] => ram_block1a86.PORTAADDR1 +address_a[1] => ram_block1a87.PORTAADDR1 +address_a[1] => ram_block1a88.PORTAADDR1 +address_a[1] => ram_block1a89.PORTAADDR1 +address_a[1] => ram_block1a90.PORTAADDR1 +address_a[1] => ram_block1a91.PORTAADDR1 +address_a[1] => ram_block1a92.PORTAADDR1 +address_a[1] => ram_block1a93.PORTAADDR1 +address_a[1] => ram_block1a94.PORTAADDR1 +address_a[1] => ram_block1a95.PORTAADDR1 +address_a[1] => ram_block1a96.PORTAADDR1 +address_a[1] => ram_block1a97.PORTAADDR1 +address_a[1] => ram_block1a98.PORTAADDR1 +address_a[1] => ram_block1a99.PORTAADDR1 +address_a[1] => ram_block1a100.PORTAADDR1 +address_a[1] => ram_block1a101.PORTAADDR1 +address_a[1] => ram_block1a102.PORTAADDR1 +address_a[1] => ram_block1a103.PORTAADDR1 +address_a[1] => ram_block1a104.PORTAADDR1 +address_a[1] => ram_block1a105.PORTAADDR1 +address_a[1] => ram_block1a106.PORTAADDR1 +address_a[1] => ram_block1a107.PORTAADDR1 +address_a[1] => ram_block1a108.PORTAADDR1 +address_a[1] => ram_block1a109.PORTAADDR1 +address_a[1] => ram_block1a110.PORTAADDR1 +address_a[1] => ram_block1a111.PORTAADDR1 +address_a[1] => ram_block1a112.PORTAADDR1 +address_a[1] => ram_block1a113.PORTAADDR1 +address_a[1] => ram_block1a114.PORTAADDR1 +address_a[1] => ram_block1a115.PORTAADDR1 +address_a[1] => ram_block1a116.PORTAADDR1 +address_a[1] => ram_block1a117.PORTAADDR1 +address_a[1] => ram_block1a118.PORTAADDR1 +address_a[1] => ram_block1a119.PORTAADDR1 +address_a[1] => ram_block1a120.PORTAADDR1 +address_a[1] => ram_block1a121.PORTAADDR1 +address_a[1] => ram_block1a122.PORTAADDR1 +address_a[1] => ram_block1a123.PORTAADDR1 +address_a[1] => ram_block1a124.PORTAADDR1 +address_a[1] => ram_block1a125.PORTAADDR1 +address_a[1] => ram_block1a126.PORTAADDR1 +address_a[1] => ram_block1a127.PORTAADDR1 +address_a[1] => ram_block1a128.PORTAADDR1 +address_a[1] => ram_block1a129.PORTAADDR1 +address_a[1] => ram_block1a130.PORTAADDR1 +address_a[1] => ram_block1a131.PORTAADDR1 +address_a[1] => ram_block1a132.PORTAADDR1 +address_a[1] => ram_block1a133.PORTAADDR1 +address_a[1] => ram_block1a134.PORTAADDR1 +address_a[1] => ram_block1a135.PORTAADDR1 +address_a[1] => ram_block1a136.PORTAADDR1 +address_a[1] => ram_block1a137.PORTAADDR1 +address_a[1] => ram_block1a138.PORTAADDR1 +address_a[1] => ram_block1a139.PORTAADDR1 +address_a[1] => ram_block1a140.PORTAADDR1 +address_a[1] => ram_block1a141.PORTAADDR1 +address_a[1] => ram_block1a142.PORTAADDR1 +address_a[1] => ram_block1a143.PORTAADDR1 +address_a[1] => ram_block1a144.PORTAADDR1 +address_a[1] => ram_block1a145.PORTAADDR1 +address_a[1] => ram_block1a146.PORTAADDR1 +address_a[1] => ram_block1a147.PORTAADDR1 +address_a[1] => ram_block1a148.PORTAADDR1 +address_a[1] => ram_block1a149.PORTAADDR1 +address_a[1] => ram_block1a150.PORTAADDR1 +address_a[1] => ram_block1a151.PORTAADDR1 +address_a[1] => ram_block1a152.PORTAADDR1 +address_a[1] => ram_block1a153.PORTAADDR1 +address_a[1] => ram_block1a154.PORTAADDR1 +address_a[1] => ram_block1a155.PORTAADDR1 +address_a[1] => ram_block1a156.PORTAADDR1 +address_a[1] => ram_block1a157.PORTAADDR1 +address_a[1] => ram_block1a158.PORTAADDR1 +address_a[1] => ram_block1a159.PORTAADDR1 +address_a[1] => ram_block1a160.PORTAADDR1 +address_a[1] => ram_block1a161.PORTAADDR1 +address_a[1] => ram_block1a162.PORTAADDR1 +address_a[1] => ram_block1a163.PORTAADDR1 +address_a[1] => ram_block1a164.PORTAADDR1 +address_a[1] => ram_block1a165.PORTAADDR1 +address_a[1] => ram_block1a166.PORTAADDR1 +address_a[1] => ram_block1a167.PORTAADDR1 +address_a[1] => ram_block1a168.PORTAADDR1 +address_a[1] => ram_block1a169.PORTAADDR1 +address_a[1] => ram_block1a170.PORTAADDR1 +address_a[1] => ram_block1a171.PORTAADDR1 +address_a[1] => ram_block1a172.PORTAADDR1 +address_a[1] => ram_block1a173.PORTAADDR1 +address_a[1] => ram_block1a174.PORTAADDR1 +address_a[1] => ram_block1a175.PORTAADDR1 +address_a[1] => ram_block1a176.PORTAADDR1 +address_a[1] => ram_block1a177.PORTAADDR1 +address_a[1] => ram_block1a178.PORTAADDR1 +address_a[1] => ram_block1a179.PORTAADDR1 +address_a[1] => ram_block1a180.PORTAADDR1 +address_a[1] => ram_block1a181.PORTAADDR1 +address_a[1] => ram_block1a182.PORTAADDR1 +address_a[1] => ram_block1a183.PORTAADDR1 +address_a[1] => ram_block1a184.PORTAADDR1 +address_a[1] => ram_block1a185.PORTAADDR1 +address_a[1] => ram_block1a186.PORTAADDR1 +address_a[1] => ram_block1a187.PORTAADDR1 +address_a[1] => ram_block1a188.PORTAADDR1 +address_a[1] => ram_block1a189.PORTAADDR1 +address_a[1] => ram_block1a190.PORTAADDR1 +address_a[1] => ram_block1a191.PORTAADDR1 +address_a[1] => ram_block1a192.PORTAADDR1 +address_a[1] => ram_block1a193.PORTAADDR1 +address_a[1] => ram_block1a194.PORTAADDR1 +address_a[1] => ram_block1a195.PORTAADDR1 +address_a[1] => ram_block1a196.PORTAADDR1 +address_a[1] => ram_block1a197.PORTAADDR1 +address_a[1] => ram_block1a198.PORTAADDR1 +address_a[1] => ram_block1a199.PORTAADDR1 +address_a[1] => ram_block1a200.PORTAADDR1 +address_a[1] => ram_block1a201.PORTAADDR1 +address_a[1] => ram_block1a202.PORTAADDR1 +address_a[1] => ram_block1a203.PORTAADDR1 +address_a[1] => ram_block1a204.PORTAADDR1 +address_a[1] => ram_block1a205.PORTAADDR1 +address_a[1] => ram_block1a206.PORTAADDR1 +address_a[1] => ram_block1a207.PORTAADDR1 +address_a[1] => ram_block1a208.PORTAADDR1 +address_a[1] => ram_block1a209.PORTAADDR1 +address_a[1] => ram_block1a210.PORTAADDR1 +address_a[1] => ram_block1a211.PORTAADDR1 +address_a[1] => ram_block1a212.PORTAADDR1 +address_a[1] => ram_block1a213.PORTAADDR1 +address_a[1] => ram_block1a214.PORTAADDR1 +address_a[1] => ram_block1a215.PORTAADDR1 +address_a[1] => ram_block1a216.PORTAADDR1 +address_a[1] => ram_block1a217.PORTAADDR1 +address_a[1] => ram_block1a218.PORTAADDR1 +address_a[1] => ram_block1a219.PORTAADDR1 +address_a[1] => ram_block1a220.PORTAADDR1 +address_a[1] => ram_block1a221.PORTAADDR1 +address_a[1] => ram_block1a222.PORTAADDR1 +address_a[1] => ram_block1a223.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[2] => ram_block1a32.PORTAADDR2 +address_a[2] => ram_block1a33.PORTAADDR2 +address_a[2] => ram_block1a34.PORTAADDR2 +address_a[2] => ram_block1a35.PORTAADDR2 +address_a[2] => ram_block1a36.PORTAADDR2 +address_a[2] => ram_block1a37.PORTAADDR2 +address_a[2] => ram_block1a38.PORTAADDR2 +address_a[2] => ram_block1a39.PORTAADDR2 +address_a[2] => ram_block1a40.PORTAADDR2 +address_a[2] => ram_block1a41.PORTAADDR2 +address_a[2] => ram_block1a42.PORTAADDR2 +address_a[2] => ram_block1a43.PORTAADDR2 +address_a[2] => ram_block1a44.PORTAADDR2 +address_a[2] => ram_block1a45.PORTAADDR2 +address_a[2] => ram_block1a46.PORTAADDR2 +address_a[2] => ram_block1a47.PORTAADDR2 +address_a[2] => ram_block1a48.PORTAADDR2 +address_a[2] => ram_block1a49.PORTAADDR2 +address_a[2] => ram_block1a50.PORTAADDR2 +address_a[2] => ram_block1a51.PORTAADDR2 +address_a[2] => ram_block1a52.PORTAADDR2 +address_a[2] => ram_block1a53.PORTAADDR2 +address_a[2] => ram_block1a54.PORTAADDR2 +address_a[2] => ram_block1a55.PORTAADDR2 +address_a[2] => ram_block1a56.PORTAADDR2 +address_a[2] => ram_block1a57.PORTAADDR2 +address_a[2] => ram_block1a58.PORTAADDR2 +address_a[2] => ram_block1a59.PORTAADDR2 +address_a[2] => ram_block1a60.PORTAADDR2 +address_a[2] => ram_block1a61.PORTAADDR2 +address_a[2] => ram_block1a62.PORTAADDR2 +address_a[2] => ram_block1a63.PORTAADDR2 +address_a[2] => ram_block1a64.PORTAADDR2 +address_a[2] => ram_block1a65.PORTAADDR2 +address_a[2] => ram_block1a66.PORTAADDR2 +address_a[2] => ram_block1a67.PORTAADDR2 +address_a[2] => ram_block1a68.PORTAADDR2 +address_a[2] => ram_block1a69.PORTAADDR2 +address_a[2] => ram_block1a70.PORTAADDR2 +address_a[2] => ram_block1a71.PORTAADDR2 +address_a[2] => ram_block1a72.PORTAADDR2 +address_a[2] => ram_block1a73.PORTAADDR2 +address_a[2] => ram_block1a74.PORTAADDR2 +address_a[2] => ram_block1a75.PORTAADDR2 +address_a[2] => ram_block1a76.PORTAADDR2 +address_a[2] => ram_block1a77.PORTAADDR2 +address_a[2] => ram_block1a78.PORTAADDR2 +address_a[2] => ram_block1a79.PORTAADDR2 +address_a[2] => ram_block1a80.PORTAADDR2 +address_a[2] => ram_block1a81.PORTAADDR2 +address_a[2] => ram_block1a82.PORTAADDR2 +address_a[2] => ram_block1a83.PORTAADDR2 +address_a[2] => ram_block1a84.PORTAADDR2 +address_a[2] => ram_block1a85.PORTAADDR2 +address_a[2] => ram_block1a86.PORTAADDR2 +address_a[2] => ram_block1a87.PORTAADDR2 +address_a[2] => ram_block1a88.PORTAADDR2 +address_a[2] => ram_block1a89.PORTAADDR2 +address_a[2] => ram_block1a90.PORTAADDR2 +address_a[2] => ram_block1a91.PORTAADDR2 +address_a[2] => ram_block1a92.PORTAADDR2 +address_a[2] => ram_block1a93.PORTAADDR2 +address_a[2] => ram_block1a94.PORTAADDR2 +address_a[2] => ram_block1a95.PORTAADDR2 +address_a[2] => ram_block1a96.PORTAADDR2 +address_a[2] => ram_block1a97.PORTAADDR2 +address_a[2] => ram_block1a98.PORTAADDR2 +address_a[2] => ram_block1a99.PORTAADDR2 +address_a[2] => ram_block1a100.PORTAADDR2 +address_a[2] => ram_block1a101.PORTAADDR2 +address_a[2] => ram_block1a102.PORTAADDR2 +address_a[2] => ram_block1a103.PORTAADDR2 +address_a[2] => ram_block1a104.PORTAADDR2 +address_a[2] => ram_block1a105.PORTAADDR2 +address_a[2] => ram_block1a106.PORTAADDR2 +address_a[2] => ram_block1a107.PORTAADDR2 +address_a[2] => ram_block1a108.PORTAADDR2 +address_a[2] => ram_block1a109.PORTAADDR2 +address_a[2] => ram_block1a110.PORTAADDR2 +address_a[2] => ram_block1a111.PORTAADDR2 +address_a[2] => ram_block1a112.PORTAADDR2 +address_a[2] => ram_block1a113.PORTAADDR2 +address_a[2] => ram_block1a114.PORTAADDR2 +address_a[2] => ram_block1a115.PORTAADDR2 +address_a[2] => ram_block1a116.PORTAADDR2 +address_a[2] => ram_block1a117.PORTAADDR2 +address_a[2] => ram_block1a118.PORTAADDR2 +address_a[2] => ram_block1a119.PORTAADDR2 +address_a[2] => ram_block1a120.PORTAADDR2 +address_a[2] => ram_block1a121.PORTAADDR2 +address_a[2] => ram_block1a122.PORTAADDR2 +address_a[2] => ram_block1a123.PORTAADDR2 +address_a[2] => ram_block1a124.PORTAADDR2 +address_a[2] => ram_block1a125.PORTAADDR2 +address_a[2] => ram_block1a126.PORTAADDR2 +address_a[2] => ram_block1a127.PORTAADDR2 +address_a[2] => ram_block1a128.PORTAADDR2 +address_a[2] => ram_block1a129.PORTAADDR2 +address_a[2] => ram_block1a130.PORTAADDR2 +address_a[2] => ram_block1a131.PORTAADDR2 +address_a[2] => ram_block1a132.PORTAADDR2 +address_a[2] => ram_block1a133.PORTAADDR2 +address_a[2] => ram_block1a134.PORTAADDR2 +address_a[2] => ram_block1a135.PORTAADDR2 +address_a[2] => ram_block1a136.PORTAADDR2 +address_a[2] => ram_block1a137.PORTAADDR2 +address_a[2] => ram_block1a138.PORTAADDR2 +address_a[2] => ram_block1a139.PORTAADDR2 +address_a[2] => ram_block1a140.PORTAADDR2 +address_a[2] => ram_block1a141.PORTAADDR2 +address_a[2] => ram_block1a142.PORTAADDR2 +address_a[2] => ram_block1a143.PORTAADDR2 +address_a[2] => ram_block1a144.PORTAADDR2 +address_a[2] => ram_block1a145.PORTAADDR2 +address_a[2] => ram_block1a146.PORTAADDR2 +address_a[2] => ram_block1a147.PORTAADDR2 +address_a[2] => ram_block1a148.PORTAADDR2 +address_a[2] => ram_block1a149.PORTAADDR2 +address_a[2] => ram_block1a150.PORTAADDR2 +address_a[2] => ram_block1a151.PORTAADDR2 +address_a[2] => ram_block1a152.PORTAADDR2 +address_a[2] => ram_block1a153.PORTAADDR2 +address_a[2] => ram_block1a154.PORTAADDR2 +address_a[2] => ram_block1a155.PORTAADDR2 +address_a[2] => ram_block1a156.PORTAADDR2 +address_a[2] => ram_block1a157.PORTAADDR2 +address_a[2] => ram_block1a158.PORTAADDR2 +address_a[2] => ram_block1a159.PORTAADDR2 +address_a[2] => ram_block1a160.PORTAADDR2 +address_a[2] => ram_block1a161.PORTAADDR2 +address_a[2] => ram_block1a162.PORTAADDR2 +address_a[2] => ram_block1a163.PORTAADDR2 +address_a[2] => ram_block1a164.PORTAADDR2 +address_a[2] => ram_block1a165.PORTAADDR2 +address_a[2] => ram_block1a166.PORTAADDR2 +address_a[2] => ram_block1a167.PORTAADDR2 +address_a[2] => ram_block1a168.PORTAADDR2 +address_a[2] => ram_block1a169.PORTAADDR2 +address_a[2] => ram_block1a170.PORTAADDR2 +address_a[2] => ram_block1a171.PORTAADDR2 +address_a[2] => ram_block1a172.PORTAADDR2 +address_a[2] => ram_block1a173.PORTAADDR2 +address_a[2] => ram_block1a174.PORTAADDR2 +address_a[2] => ram_block1a175.PORTAADDR2 +address_a[2] => ram_block1a176.PORTAADDR2 +address_a[2] => ram_block1a177.PORTAADDR2 +address_a[2] => ram_block1a178.PORTAADDR2 +address_a[2] => ram_block1a179.PORTAADDR2 +address_a[2] => ram_block1a180.PORTAADDR2 +address_a[2] => ram_block1a181.PORTAADDR2 +address_a[2] => ram_block1a182.PORTAADDR2 +address_a[2] => ram_block1a183.PORTAADDR2 +address_a[2] => ram_block1a184.PORTAADDR2 +address_a[2] => ram_block1a185.PORTAADDR2 +address_a[2] => ram_block1a186.PORTAADDR2 +address_a[2] => ram_block1a187.PORTAADDR2 +address_a[2] => ram_block1a188.PORTAADDR2 +address_a[2] => ram_block1a189.PORTAADDR2 +address_a[2] => ram_block1a190.PORTAADDR2 +address_a[2] => ram_block1a191.PORTAADDR2 +address_a[2] => ram_block1a192.PORTAADDR2 +address_a[2] => ram_block1a193.PORTAADDR2 +address_a[2] => ram_block1a194.PORTAADDR2 +address_a[2] => ram_block1a195.PORTAADDR2 +address_a[2] => ram_block1a196.PORTAADDR2 +address_a[2] => ram_block1a197.PORTAADDR2 +address_a[2] => ram_block1a198.PORTAADDR2 +address_a[2] => ram_block1a199.PORTAADDR2 +address_a[2] => ram_block1a200.PORTAADDR2 +address_a[2] => ram_block1a201.PORTAADDR2 +address_a[2] => ram_block1a202.PORTAADDR2 +address_a[2] => ram_block1a203.PORTAADDR2 +address_a[2] => ram_block1a204.PORTAADDR2 +address_a[2] => ram_block1a205.PORTAADDR2 +address_a[2] => ram_block1a206.PORTAADDR2 +address_a[2] => ram_block1a207.PORTAADDR2 +address_a[2] => ram_block1a208.PORTAADDR2 +address_a[2] => ram_block1a209.PORTAADDR2 +address_a[2] => ram_block1a210.PORTAADDR2 +address_a[2] => ram_block1a211.PORTAADDR2 +address_a[2] => ram_block1a212.PORTAADDR2 +address_a[2] => ram_block1a213.PORTAADDR2 +address_a[2] => ram_block1a214.PORTAADDR2 +address_a[2] => ram_block1a215.PORTAADDR2 +address_a[2] => ram_block1a216.PORTAADDR2 +address_a[2] => ram_block1a217.PORTAADDR2 +address_a[2] => ram_block1a218.PORTAADDR2 +address_a[2] => ram_block1a219.PORTAADDR2 +address_a[2] => ram_block1a220.PORTAADDR2 +address_a[2] => ram_block1a221.PORTAADDR2 +address_a[2] => ram_block1a222.PORTAADDR2 +address_a[2] => ram_block1a223.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[3] => ram_block1a32.PORTAADDR3 +address_a[3] => ram_block1a33.PORTAADDR3 +address_a[3] => ram_block1a34.PORTAADDR3 +address_a[3] => ram_block1a35.PORTAADDR3 +address_a[3] => ram_block1a36.PORTAADDR3 +address_a[3] => ram_block1a37.PORTAADDR3 +address_a[3] => ram_block1a38.PORTAADDR3 +address_a[3] => ram_block1a39.PORTAADDR3 +address_a[3] => ram_block1a40.PORTAADDR3 +address_a[3] => ram_block1a41.PORTAADDR3 +address_a[3] => ram_block1a42.PORTAADDR3 +address_a[3] => ram_block1a43.PORTAADDR3 +address_a[3] => ram_block1a44.PORTAADDR3 +address_a[3] => ram_block1a45.PORTAADDR3 +address_a[3] => ram_block1a46.PORTAADDR3 +address_a[3] => ram_block1a47.PORTAADDR3 +address_a[3] => ram_block1a48.PORTAADDR3 +address_a[3] => ram_block1a49.PORTAADDR3 +address_a[3] => ram_block1a50.PORTAADDR3 +address_a[3] => ram_block1a51.PORTAADDR3 +address_a[3] => ram_block1a52.PORTAADDR3 +address_a[3] => ram_block1a53.PORTAADDR3 +address_a[3] => ram_block1a54.PORTAADDR3 +address_a[3] => ram_block1a55.PORTAADDR3 +address_a[3] => ram_block1a56.PORTAADDR3 +address_a[3] => ram_block1a57.PORTAADDR3 +address_a[3] => ram_block1a58.PORTAADDR3 +address_a[3] => ram_block1a59.PORTAADDR3 +address_a[3] => ram_block1a60.PORTAADDR3 +address_a[3] => ram_block1a61.PORTAADDR3 +address_a[3] => ram_block1a62.PORTAADDR3 +address_a[3] => ram_block1a63.PORTAADDR3 +address_a[3] => ram_block1a64.PORTAADDR3 +address_a[3] => ram_block1a65.PORTAADDR3 +address_a[3] => ram_block1a66.PORTAADDR3 +address_a[3] => ram_block1a67.PORTAADDR3 +address_a[3] => ram_block1a68.PORTAADDR3 +address_a[3] => ram_block1a69.PORTAADDR3 +address_a[3] => ram_block1a70.PORTAADDR3 +address_a[3] => ram_block1a71.PORTAADDR3 +address_a[3] => ram_block1a72.PORTAADDR3 +address_a[3] => ram_block1a73.PORTAADDR3 +address_a[3] => ram_block1a74.PORTAADDR3 +address_a[3] => ram_block1a75.PORTAADDR3 +address_a[3] => ram_block1a76.PORTAADDR3 +address_a[3] => ram_block1a77.PORTAADDR3 +address_a[3] => ram_block1a78.PORTAADDR3 +address_a[3] => ram_block1a79.PORTAADDR3 +address_a[3] => ram_block1a80.PORTAADDR3 +address_a[3] => ram_block1a81.PORTAADDR3 +address_a[3] => ram_block1a82.PORTAADDR3 +address_a[3] => ram_block1a83.PORTAADDR3 +address_a[3] => ram_block1a84.PORTAADDR3 +address_a[3] => ram_block1a85.PORTAADDR3 +address_a[3] => ram_block1a86.PORTAADDR3 +address_a[3] => ram_block1a87.PORTAADDR3 +address_a[3] => ram_block1a88.PORTAADDR3 +address_a[3] => ram_block1a89.PORTAADDR3 +address_a[3] => ram_block1a90.PORTAADDR3 +address_a[3] => ram_block1a91.PORTAADDR3 +address_a[3] => ram_block1a92.PORTAADDR3 +address_a[3] => ram_block1a93.PORTAADDR3 +address_a[3] => ram_block1a94.PORTAADDR3 +address_a[3] => ram_block1a95.PORTAADDR3 +address_a[3] => ram_block1a96.PORTAADDR3 +address_a[3] => ram_block1a97.PORTAADDR3 +address_a[3] => ram_block1a98.PORTAADDR3 +address_a[3] => ram_block1a99.PORTAADDR3 +address_a[3] => ram_block1a100.PORTAADDR3 +address_a[3] => ram_block1a101.PORTAADDR3 +address_a[3] => ram_block1a102.PORTAADDR3 +address_a[3] => ram_block1a103.PORTAADDR3 +address_a[3] => ram_block1a104.PORTAADDR3 +address_a[3] => ram_block1a105.PORTAADDR3 +address_a[3] => ram_block1a106.PORTAADDR3 +address_a[3] => ram_block1a107.PORTAADDR3 +address_a[3] => ram_block1a108.PORTAADDR3 +address_a[3] => ram_block1a109.PORTAADDR3 +address_a[3] => ram_block1a110.PORTAADDR3 +address_a[3] => ram_block1a111.PORTAADDR3 +address_a[3] => ram_block1a112.PORTAADDR3 +address_a[3] => ram_block1a113.PORTAADDR3 +address_a[3] => ram_block1a114.PORTAADDR3 +address_a[3] => ram_block1a115.PORTAADDR3 +address_a[3] => ram_block1a116.PORTAADDR3 +address_a[3] => ram_block1a117.PORTAADDR3 +address_a[3] => ram_block1a118.PORTAADDR3 +address_a[3] => ram_block1a119.PORTAADDR3 +address_a[3] => ram_block1a120.PORTAADDR3 +address_a[3] => ram_block1a121.PORTAADDR3 +address_a[3] => ram_block1a122.PORTAADDR3 +address_a[3] => ram_block1a123.PORTAADDR3 +address_a[3] => ram_block1a124.PORTAADDR3 +address_a[3] => ram_block1a125.PORTAADDR3 +address_a[3] => ram_block1a126.PORTAADDR3 +address_a[3] => ram_block1a127.PORTAADDR3 +address_a[3] => ram_block1a128.PORTAADDR3 +address_a[3] => ram_block1a129.PORTAADDR3 +address_a[3] => ram_block1a130.PORTAADDR3 +address_a[3] => ram_block1a131.PORTAADDR3 +address_a[3] => ram_block1a132.PORTAADDR3 +address_a[3] => ram_block1a133.PORTAADDR3 +address_a[3] => ram_block1a134.PORTAADDR3 +address_a[3] => ram_block1a135.PORTAADDR3 +address_a[3] => ram_block1a136.PORTAADDR3 +address_a[3] => ram_block1a137.PORTAADDR3 +address_a[3] => ram_block1a138.PORTAADDR3 +address_a[3] => ram_block1a139.PORTAADDR3 +address_a[3] => ram_block1a140.PORTAADDR3 +address_a[3] => ram_block1a141.PORTAADDR3 +address_a[3] => ram_block1a142.PORTAADDR3 +address_a[3] => ram_block1a143.PORTAADDR3 +address_a[3] => ram_block1a144.PORTAADDR3 +address_a[3] => ram_block1a145.PORTAADDR3 +address_a[3] => ram_block1a146.PORTAADDR3 +address_a[3] => ram_block1a147.PORTAADDR3 +address_a[3] => ram_block1a148.PORTAADDR3 +address_a[3] => ram_block1a149.PORTAADDR3 +address_a[3] => ram_block1a150.PORTAADDR3 +address_a[3] => ram_block1a151.PORTAADDR3 +address_a[3] => ram_block1a152.PORTAADDR3 +address_a[3] => ram_block1a153.PORTAADDR3 +address_a[3] => ram_block1a154.PORTAADDR3 +address_a[3] => ram_block1a155.PORTAADDR3 +address_a[3] => ram_block1a156.PORTAADDR3 +address_a[3] => ram_block1a157.PORTAADDR3 +address_a[3] => ram_block1a158.PORTAADDR3 +address_a[3] => ram_block1a159.PORTAADDR3 +address_a[3] => ram_block1a160.PORTAADDR3 +address_a[3] => ram_block1a161.PORTAADDR3 +address_a[3] => ram_block1a162.PORTAADDR3 +address_a[3] => ram_block1a163.PORTAADDR3 +address_a[3] => ram_block1a164.PORTAADDR3 +address_a[3] => ram_block1a165.PORTAADDR3 +address_a[3] => ram_block1a166.PORTAADDR3 +address_a[3] => ram_block1a167.PORTAADDR3 +address_a[3] => ram_block1a168.PORTAADDR3 +address_a[3] => ram_block1a169.PORTAADDR3 +address_a[3] => ram_block1a170.PORTAADDR3 +address_a[3] => ram_block1a171.PORTAADDR3 +address_a[3] => ram_block1a172.PORTAADDR3 +address_a[3] => ram_block1a173.PORTAADDR3 +address_a[3] => ram_block1a174.PORTAADDR3 +address_a[3] => ram_block1a175.PORTAADDR3 +address_a[3] => ram_block1a176.PORTAADDR3 +address_a[3] => ram_block1a177.PORTAADDR3 +address_a[3] => ram_block1a178.PORTAADDR3 +address_a[3] => ram_block1a179.PORTAADDR3 +address_a[3] => ram_block1a180.PORTAADDR3 +address_a[3] => ram_block1a181.PORTAADDR3 +address_a[3] => ram_block1a182.PORTAADDR3 +address_a[3] => ram_block1a183.PORTAADDR3 +address_a[3] => ram_block1a184.PORTAADDR3 +address_a[3] => ram_block1a185.PORTAADDR3 +address_a[3] => ram_block1a186.PORTAADDR3 +address_a[3] => ram_block1a187.PORTAADDR3 +address_a[3] => ram_block1a188.PORTAADDR3 +address_a[3] => ram_block1a189.PORTAADDR3 +address_a[3] => ram_block1a190.PORTAADDR3 +address_a[3] => ram_block1a191.PORTAADDR3 +address_a[3] => ram_block1a192.PORTAADDR3 +address_a[3] => ram_block1a193.PORTAADDR3 +address_a[3] => ram_block1a194.PORTAADDR3 +address_a[3] => ram_block1a195.PORTAADDR3 +address_a[3] => ram_block1a196.PORTAADDR3 +address_a[3] => ram_block1a197.PORTAADDR3 +address_a[3] => ram_block1a198.PORTAADDR3 +address_a[3] => ram_block1a199.PORTAADDR3 +address_a[3] => ram_block1a200.PORTAADDR3 +address_a[3] => ram_block1a201.PORTAADDR3 +address_a[3] => ram_block1a202.PORTAADDR3 +address_a[3] => ram_block1a203.PORTAADDR3 +address_a[3] => ram_block1a204.PORTAADDR3 +address_a[3] => ram_block1a205.PORTAADDR3 +address_a[3] => ram_block1a206.PORTAADDR3 +address_a[3] => ram_block1a207.PORTAADDR3 +address_a[3] => ram_block1a208.PORTAADDR3 +address_a[3] => ram_block1a209.PORTAADDR3 +address_a[3] => ram_block1a210.PORTAADDR3 +address_a[3] => ram_block1a211.PORTAADDR3 +address_a[3] => ram_block1a212.PORTAADDR3 +address_a[3] => ram_block1a213.PORTAADDR3 +address_a[3] => ram_block1a214.PORTAADDR3 +address_a[3] => ram_block1a215.PORTAADDR3 +address_a[3] => ram_block1a216.PORTAADDR3 +address_a[3] => ram_block1a217.PORTAADDR3 +address_a[3] => ram_block1a218.PORTAADDR3 +address_a[3] => ram_block1a219.PORTAADDR3 +address_a[3] => ram_block1a220.PORTAADDR3 +address_a[3] => ram_block1a221.PORTAADDR3 +address_a[3] => ram_block1a222.PORTAADDR3 +address_a[3] => ram_block1a223.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_a[4] => ram_block1a32.PORTAADDR4 +address_a[4] => ram_block1a33.PORTAADDR4 +address_a[4] => ram_block1a34.PORTAADDR4 +address_a[4] => ram_block1a35.PORTAADDR4 +address_a[4] => ram_block1a36.PORTAADDR4 +address_a[4] => ram_block1a37.PORTAADDR4 +address_a[4] => ram_block1a38.PORTAADDR4 +address_a[4] => ram_block1a39.PORTAADDR4 +address_a[4] => ram_block1a40.PORTAADDR4 +address_a[4] => ram_block1a41.PORTAADDR4 +address_a[4] => ram_block1a42.PORTAADDR4 +address_a[4] => ram_block1a43.PORTAADDR4 +address_a[4] => ram_block1a44.PORTAADDR4 +address_a[4] => ram_block1a45.PORTAADDR4 +address_a[4] => ram_block1a46.PORTAADDR4 +address_a[4] => ram_block1a47.PORTAADDR4 +address_a[4] => ram_block1a48.PORTAADDR4 +address_a[4] => ram_block1a49.PORTAADDR4 +address_a[4] => ram_block1a50.PORTAADDR4 +address_a[4] => ram_block1a51.PORTAADDR4 +address_a[4] => ram_block1a52.PORTAADDR4 +address_a[4] => ram_block1a53.PORTAADDR4 +address_a[4] => ram_block1a54.PORTAADDR4 +address_a[4] => ram_block1a55.PORTAADDR4 +address_a[4] => ram_block1a56.PORTAADDR4 +address_a[4] => ram_block1a57.PORTAADDR4 +address_a[4] => ram_block1a58.PORTAADDR4 +address_a[4] => ram_block1a59.PORTAADDR4 +address_a[4] => ram_block1a60.PORTAADDR4 +address_a[4] => ram_block1a61.PORTAADDR4 +address_a[4] => ram_block1a62.PORTAADDR4 +address_a[4] => ram_block1a63.PORTAADDR4 +address_a[4] => ram_block1a64.PORTAADDR4 +address_a[4] => ram_block1a65.PORTAADDR4 +address_a[4] => ram_block1a66.PORTAADDR4 +address_a[4] => ram_block1a67.PORTAADDR4 +address_a[4] => ram_block1a68.PORTAADDR4 +address_a[4] => ram_block1a69.PORTAADDR4 +address_a[4] => ram_block1a70.PORTAADDR4 +address_a[4] => ram_block1a71.PORTAADDR4 +address_a[4] => ram_block1a72.PORTAADDR4 +address_a[4] => ram_block1a73.PORTAADDR4 +address_a[4] => ram_block1a74.PORTAADDR4 +address_a[4] => ram_block1a75.PORTAADDR4 +address_a[4] => ram_block1a76.PORTAADDR4 +address_a[4] => ram_block1a77.PORTAADDR4 +address_a[4] => ram_block1a78.PORTAADDR4 +address_a[4] => ram_block1a79.PORTAADDR4 +address_a[4] => ram_block1a80.PORTAADDR4 +address_a[4] => ram_block1a81.PORTAADDR4 +address_a[4] => ram_block1a82.PORTAADDR4 +address_a[4] => ram_block1a83.PORTAADDR4 +address_a[4] => ram_block1a84.PORTAADDR4 +address_a[4] => ram_block1a85.PORTAADDR4 +address_a[4] => ram_block1a86.PORTAADDR4 +address_a[4] => ram_block1a87.PORTAADDR4 +address_a[4] => ram_block1a88.PORTAADDR4 +address_a[4] => ram_block1a89.PORTAADDR4 +address_a[4] => ram_block1a90.PORTAADDR4 +address_a[4] => ram_block1a91.PORTAADDR4 +address_a[4] => ram_block1a92.PORTAADDR4 +address_a[4] => ram_block1a93.PORTAADDR4 +address_a[4] => ram_block1a94.PORTAADDR4 +address_a[4] => ram_block1a95.PORTAADDR4 +address_a[4] => ram_block1a96.PORTAADDR4 +address_a[4] => ram_block1a97.PORTAADDR4 +address_a[4] => ram_block1a98.PORTAADDR4 +address_a[4] => ram_block1a99.PORTAADDR4 +address_a[4] => ram_block1a100.PORTAADDR4 +address_a[4] => ram_block1a101.PORTAADDR4 +address_a[4] => ram_block1a102.PORTAADDR4 +address_a[4] => ram_block1a103.PORTAADDR4 +address_a[4] => ram_block1a104.PORTAADDR4 +address_a[4] => ram_block1a105.PORTAADDR4 +address_a[4] => ram_block1a106.PORTAADDR4 +address_a[4] => ram_block1a107.PORTAADDR4 +address_a[4] => ram_block1a108.PORTAADDR4 +address_a[4] => ram_block1a109.PORTAADDR4 +address_a[4] => ram_block1a110.PORTAADDR4 +address_a[4] => ram_block1a111.PORTAADDR4 +address_a[4] => ram_block1a112.PORTAADDR4 +address_a[4] => ram_block1a113.PORTAADDR4 +address_a[4] => ram_block1a114.PORTAADDR4 +address_a[4] => ram_block1a115.PORTAADDR4 +address_a[4] => ram_block1a116.PORTAADDR4 +address_a[4] => ram_block1a117.PORTAADDR4 +address_a[4] => ram_block1a118.PORTAADDR4 +address_a[4] => ram_block1a119.PORTAADDR4 +address_a[4] => ram_block1a120.PORTAADDR4 +address_a[4] => ram_block1a121.PORTAADDR4 +address_a[4] => ram_block1a122.PORTAADDR4 +address_a[4] => ram_block1a123.PORTAADDR4 +address_a[4] => ram_block1a124.PORTAADDR4 +address_a[4] => ram_block1a125.PORTAADDR4 +address_a[4] => ram_block1a126.PORTAADDR4 +address_a[4] => ram_block1a127.PORTAADDR4 +address_a[4] => ram_block1a128.PORTAADDR4 +address_a[4] => ram_block1a129.PORTAADDR4 +address_a[4] => ram_block1a130.PORTAADDR4 +address_a[4] => ram_block1a131.PORTAADDR4 +address_a[4] => ram_block1a132.PORTAADDR4 +address_a[4] => ram_block1a133.PORTAADDR4 +address_a[4] => ram_block1a134.PORTAADDR4 +address_a[4] => ram_block1a135.PORTAADDR4 +address_a[4] => ram_block1a136.PORTAADDR4 +address_a[4] => ram_block1a137.PORTAADDR4 +address_a[4] => ram_block1a138.PORTAADDR4 +address_a[4] => ram_block1a139.PORTAADDR4 +address_a[4] => ram_block1a140.PORTAADDR4 +address_a[4] => ram_block1a141.PORTAADDR4 +address_a[4] => ram_block1a142.PORTAADDR4 +address_a[4] => ram_block1a143.PORTAADDR4 +address_a[4] => ram_block1a144.PORTAADDR4 +address_a[4] => ram_block1a145.PORTAADDR4 +address_a[4] => ram_block1a146.PORTAADDR4 +address_a[4] => ram_block1a147.PORTAADDR4 +address_a[4] => ram_block1a148.PORTAADDR4 +address_a[4] => ram_block1a149.PORTAADDR4 +address_a[4] => ram_block1a150.PORTAADDR4 +address_a[4] => ram_block1a151.PORTAADDR4 +address_a[4] => ram_block1a152.PORTAADDR4 +address_a[4] => ram_block1a153.PORTAADDR4 +address_a[4] => ram_block1a154.PORTAADDR4 +address_a[4] => ram_block1a155.PORTAADDR4 +address_a[4] => ram_block1a156.PORTAADDR4 +address_a[4] => ram_block1a157.PORTAADDR4 +address_a[4] => ram_block1a158.PORTAADDR4 +address_a[4] => ram_block1a159.PORTAADDR4 +address_a[4] => ram_block1a160.PORTAADDR4 +address_a[4] => ram_block1a161.PORTAADDR4 +address_a[4] => ram_block1a162.PORTAADDR4 +address_a[4] => ram_block1a163.PORTAADDR4 +address_a[4] => ram_block1a164.PORTAADDR4 +address_a[4] => ram_block1a165.PORTAADDR4 +address_a[4] => ram_block1a166.PORTAADDR4 +address_a[4] => ram_block1a167.PORTAADDR4 +address_a[4] => ram_block1a168.PORTAADDR4 +address_a[4] => ram_block1a169.PORTAADDR4 +address_a[4] => ram_block1a170.PORTAADDR4 +address_a[4] => ram_block1a171.PORTAADDR4 +address_a[4] => ram_block1a172.PORTAADDR4 +address_a[4] => ram_block1a173.PORTAADDR4 +address_a[4] => ram_block1a174.PORTAADDR4 +address_a[4] => ram_block1a175.PORTAADDR4 +address_a[4] => ram_block1a176.PORTAADDR4 +address_a[4] => ram_block1a177.PORTAADDR4 +address_a[4] => ram_block1a178.PORTAADDR4 +address_a[4] => ram_block1a179.PORTAADDR4 +address_a[4] => ram_block1a180.PORTAADDR4 +address_a[4] => ram_block1a181.PORTAADDR4 +address_a[4] => ram_block1a182.PORTAADDR4 +address_a[4] => ram_block1a183.PORTAADDR4 +address_a[4] => ram_block1a184.PORTAADDR4 +address_a[4] => ram_block1a185.PORTAADDR4 +address_a[4] => ram_block1a186.PORTAADDR4 +address_a[4] => ram_block1a187.PORTAADDR4 +address_a[4] => ram_block1a188.PORTAADDR4 +address_a[4] => ram_block1a189.PORTAADDR4 +address_a[4] => ram_block1a190.PORTAADDR4 +address_a[4] => ram_block1a191.PORTAADDR4 +address_a[4] => ram_block1a192.PORTAADDR4 +address_a[4] => ram_block1a193.PORTAADDR4 +address_a[4] => ram_block1a194.PORTAADDR4 +address_a[4] => ram_block1a195.PORTAADDR4 +address_a[4] => ram_block1a196.PORTAADDR4 +address_a[4] => ram_block1a197.PORTAADDR4 +address_a[4] => ram_block1a198.PORTAADDR4 +address_a[4] => ram_block1a199.PORTAADDR4 +address_a[4] => ram_block1a200.PORTAADDR4 +address_a[4] => ram_block1a201.PORTAADDR4 +address_a[4] => ram_block1a202.PORTAADDR4 +address_a[4] => ram_block1a203.PORTAADDR4 +address_a[4] => ram_block1a204.PORTAADDR4 +address_a[4] => ram_block1a205.PORTAADDR4 +address_a[4] => ram_block1a206.PORTAADDR4 +address_a[4] => ram_block1a207.PORTAADDR4 +address_a[4] => ram_block1a208.PORTAADDR4 +address_a[4] => ram_block1a209.PORTAADDR4 +address_a[4] => ram_block1a210.PORTAADDR4 +address_a[4] => ram_block1a211.PORTAADDR4 +address_a[4] => ram_block1a212.PORTAADDR4 +address_a[4] => ram_block1a213.PORTAADDR4 +address_a[4] => ram_block1a214.PORTAADDR4 +address_a[4] => ram_block1a215.PORTAADDR4 +address_a[4] => ram_block1a216.PORTAADDR4 +address_a[4] => ram_block1a217.PORTAADDR4 +address_a[4] => ram_block1a218.PORTAADDR4 +address_a[4] => ram_block1a219.PORTAADDR4 +address_a[4] => ram_block1a220.PORTAADDR4 +address_a[4] => ram_block1a221.PORTAADDR4 +address_a[4] => ram_block1a222.PORTAADDR4 +address_a[4] => ram_block1a223.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[5] => ram_block1a21.PORTAADDR5 +address_a[5] => ram_block1a22.PORTAADDR5 +address_a[5] => ram_block1a23.PORTAADDR5 +address_a[5] => ram_block1a24.PORTAADDR5 +address_a[5] => ram_block1a25.PORTAADDR5 +address_a[5] => ram_block1a26.PORTAADDR5 +address_a[5] => ram_block1a27.PORTAADDR5 +address_a[5] => ram_block1a28.PORTAADDR5 +address_a[5] => ram_block1a29.PORTAADDR5 +address_a[5] => ram_block1a30.PORTAADDR5 +address_a[5] => ram_block1a31.PORTAADDR5 +address_a[5] => ram_block1a32.PORTAADDR5 +address_a[5] => ram_block1a33.PORTAADDR5 +address_a[5] => ram_block1a34.PORTAADDR5 +address_a[5] => ram_block1a35.PORTAADDR5 +address_a[5] => ram_block1a36.PORTAADDR5 +address_a[5] => ram_block1a37.PORTAADDR5 +address_a[5] => ram_block1a38.PORTAADDR5 +address_a[5] => ram_block1a39.PORTAADDR5 +address_a[5] => ram_block1a40.PORTAADDR5 +address_a[5] => ram_block1a41.PORTAADDR5 +address_a[5] => ram_block1a42.PORTAADDR5 +address_a[5] => ram_block1a43.PORTAADDR5 +address_a[5] => ram_block1a44.PORTAADDR5 +address_a[5] => ram_block1a45.PORTAADDR5 +address_a[5] => ram_block1a46.PORTAADDR5 +address_a[5] => ram_block1a47.PORTAADDR5 +address_a[5] => ram_block1a48.PORTAADDR5 +address_a[5] => ram_block1a49.PORTAADDR5 +address_a[5] => ram_block1a50.PORTAADDR5 +address_a[5] => ram_block1a51.PORTAADDR5 +address_a[5] => ram_block1a52.PORTAADDR5 +address_a[5] => ram_block1a53.PORTAADDR5 +address_a[5] => ram_block1a54.PORTAADDR5 +address_a[5] => ram_block1a55.PORTAADDR5 +address_a[5] => ram_block1a56.PORTAADDR5 +address_a[5] => ram_block1a57.PORTAADDR5 +address_a[5] => ram_block1a58.PORTAADDR5 +address_a[5] => ram_block1a59.PORTAADDR5 +address_a[5] => ram_block1a60.PORTAADDR5 +address_a[5] => ram_block1a61.PORTAADDR5 +address_a[5] => ram_block1a62.PORTAADDR5 +address_a[5] => ram_block1a63.PORTAADDR5 +address_a[5] => ram_block1a64.PORTAADDR5 +address_a[5] => ram_block1a65.PORTAADDR5 +address_a[5] => ram_block1a66.PORTAADDR5 +address_a[5] => ram_block1a67.PORTAADDR5 +address_a[5] => ram_block1a68.PORTAADDR5 +address_a[5] => ram_block1a69.PORTAADDR5 +address_a[5] => ram_block1a70.PORTAADDR5 +address_a[5] => ram_block1a71.PORTAADDR5 +address_a[5] => ram_block1a72.PORTAADDR5 +address_a[5] => ram_block1a73.PORTAADDR5 +address_a[5] => ram_block1a74.PORTAADDR5 +address_a[5] => ram_block1a75.PORTAADDR5 +address_a[5] => ram_block1a76.PORTAADDR5 +address_a[5] => ram_block1a77.PORTAADDR5 +address_a[5] => ram_block1a78.PORTAADDR5 +address_a[5] => ram_block1a79.PORTAADDR5 +address_a[5] => ram_block1a80.PORTAADDR5 +address_a[5] => ram_block1a81.PORTAADDR5 +address_a[5] => ram_block1a82.PORTAADDR5 +address_a[5] => ram_block1a83.PORTAADDR5 +address_a[5] => ram_block1a84.PORTAADDR5 +address_a[5] => ram_block1a85.PORTAADDR5 +address_a[5] => ram_block1a86.PORTAADDR5 +address_a[5] => ram_block1a87.PORTAADDR5 +address_a[5] => ram_block1a88.PORTAADDR5 +address_a[5] => ram_block1a89.PORTAADDR5 +address_a[5] => ram_block1a90.PORTAADDR5 +address_a[5] => ram_block1a91.PORTAADDR5 +address_a[5] => ram_block1a92.PORTAADDR5 +address_a[5] => ram_block1a93.PORTAADDR5 +address_a[5] => ram_block1a94.PORTAADDR5 +address_a[5] => ram_block1a95.PORTAADDR5 +address_a[5] => ram_block1a96.PORTAADDR5 +address_a[5] => ram_block1a97.PORTAADDR5 +address_a[5] => ram_block1a98.PORTAADDR5 +address_a[5] => ram_block1a99.PORTAADDR5 +address_a[5] => ram_block1a100.PORTAADDR5 +address_a[5] => ram_block1a101.PORTAADDR5 +address_a[5] => ram_block1a102.PORTAADDR5 +address_a[5] => ram_block1a103.PORTAADDR5 +address_a[5] => ram_block1a104.PORTAADDR5 +address_a[5] => ram_block1a105.PORTAADDR5 +address_a[5] => ram_block1a106.PORTAADDR5 +address_a[5] => ram_block1a107.PORTAADDR5 +address_a[5] => ram_block1a108.PORTAADDR5 +address_a[5] => ram_block1a109.PORTAADDR5 +address_a[5] => ram_block1a110.PORTAADDR5 +address_a[5] => ram_block1a111.PORTAADDR5 +address_a[5] => ram_block1a112.PORTAADDR5 +address_a[5] => ram_block1a113.PORTAADDR5 +address_a[5] => ram_block1a114.PORTAADDR5 +address_a[5] => ram_block1a115.PORTAADDR5 +address_a[5] => ram_block1a116.PORTAADDR5 +address_a[5] => ram_block1a117.PORTAADDR5 +address_a[5] => ram_block1a118.PORTAADDR5 +address_a[5] => ram_block1a119.PORTAADDR5 +address_a[5] => ram_block1a120.PORTAADDR5 +address_a[5] => ram_block1a121.PORTAADDR5 +address_a[5] => ram_block1a122.PORTAADDR5 +address_a[5] => ram_block1a123.PORTAADDR5 +address_a[5] => ram_block1a124.PORTAADDR5 +address_a[5] => ram_block1a125.PORTAADDR5 +address_a[5] => ram_block1a126.PORTAADDR5 +address_a[5] => ram_block1a127.PORTAADDR5 +address_a[5] => ram_block1a128.PORTAADDR5 +address_a[5] => ram_block1a129.PORTAADDR5 +address_a[5] => ram_block1a130.PORTAADDR5 +address_a[5] => ram_block1a131.PORTAADDR5 +address_a[5] => ram_block1a132.PORTAADDR5 +address_a[5] => ram_block1a133.PORTAADDR5 +address_a[5] => ram_block1a134.PORTAADDR5 +address_a[5] => ram_block1a135.PORTAADDR5 +address_a[5] => ram_block1a136.PORTAADDR5 +address_a[5] => ram_block1a137.PORTAADDR5 +address_a[5] => ram_block1a138.PORTAADDR5 +address_a[5] => ram_block1a139.PORTAADDR5 +address_a[5] => ram_block1a140.PORTAADDR5 +address_a[5] => ram_block1a141.PORTAADDR5 +address_a[5] => ram_block1a142.PORTAADDR5 +address_a[5] => ram_block1a143.PORTAADDR5 +address_a[5] => ram_block1a144.PORTAADDR5 +address_a[5] => ram_block1a145.PORTAADDR5 +address_a[5] => ram_block1a146.PORTAADDR5 +address_a[5] => ram_block1a147.PORTAADDR5 +address_a[5] => ram_block1a148.PORTAADDR5 +address_a[5] => ram_block1a149.PORTAADDR5 +address_a[5] => ram_block1a150.PORTAADDR5 +address_a[5] => ram_block1a151.PORTAADDR5 +address_a[5] => ram_block1a152.PORTAADDR5 +address_a[5] => ram_block1a153.PORTAADDR5 +address_a[5] => ram_block1a154.PORTAADDR5 +address_a[5] => ram_block1a155.PORTAADDR5 +address_a[5] => ram_block1a156.PORTAADDR5 +address_a[5] => ram_block1a157.PORTAADDR5 +address_a[5] => ram_block1a158.PORTAADDR5 +address_a[5] => ram_block1a159.PORTAADDR5 +address_a[5] => ram_block1a160.PORTAADDR5 +address_a[5] => ram_block1a161.PORTAADDR5 +address_a[5] => ram_block1a162.PORTAADDR5 +address_a[5] => ram_block1a163.PORTAADDR5 +address_a[5] => ram_block1a164.PORTAADDR5 +address_a[5] => ram_block1a165.PORTAADDR5 +address_a[5] => ram_block1a166.PORTAADDR5 +address_a[5] => ram_block1a167.PORTAADDR5 +address_a[5] => ram_block1a168.PORTAADDR5 +address_a[5] => ram_block1a169.PORTAADDR5 +address_a[5] => ram_block1a170.PORTAADDR5 +address_a[5] => ram_block1a171.PORTAADDR5 +address_a[5] => ram_block1a172.PORTAADDR5 +address_a[5] => ram_block1a173.PORTAADDR5 +address_a[5] => ram_block1a174.PORTAADDR5 +address_a[5] => ram_block1a175.PORTAADDR5 +address_a[5] => ram_block1a176.PORTAADDR5 +address_a[5] => ram_block1a177.PORTAADDR5 +address_a[5] => ram_block1a178.PORTAADDR5 +address_a[5] => ram_block1a179.PORTAADDR5 +address_a[5] => ram_block1a180.PORTAADDR5 +address_a[5] => ram_block1a181.PORTAADDR5 +address_a[5] => ram_block1a182.PORTAADDR5 +address_a[5] => ram_block1a183.PORTAADDR5 +address_a[5] => ram_block1a184.PORTAADDR5 +address_a[5] => ram_block1a185.PORTAADDR5 +address_a[5] => ram_block1a186.PORTAADDR5 +address_a[5] => ram_block1a187.PORTAADDR5 +address_a[5] => ram_block1a188.PORTAADDR5 +address_a[5] => ram_block1a189.PORTAADDR5 +address_a[5] => ram_block1a190.PORTAADDR5 +address_a[5] => ram_block1a191.PORTAADDR5 +address_a[5] => ram_block1a192.PORTAADDR5 +address_a[5] => ram_block1a193.PORTAADDR5 +address_a[5] => ram_block1a194.PORTAADDR5 +address_a[5] => ram_block1a195.PORTAADDR5 +address_a[5] => ram_block1a196.PORTAADDR5 +address_a[5] => ram_block1a197.PORTAADDR5 +address_a[5] => ram_block1a198.PORTAADDR5 +address_a[5] => ram_block1a199.PORTAADDR5 +address_a[5] => ram_block1a200.PORTAADDR5 +address_a[5] => ram_block1a201.PORTAADDR5 +address_a[5] => ram_block1a202.PORTAADDR5 +address_a[5] => ram_block1a203.PORTAADDR5 +address_a[5] => ram_block1a204.PORTAADDR5 +address_a[5] => ram_block1a205.PORTAADDR5 +address_a[5] => ram_block1a206.PORTAADDR5 +address_a[5] => ram_block1a207.PORTAADDR5 +address_a[5] => ram_block1a208.PORTAADDR5 +address_a[5] => ram_block1a209.PORTAADDR5 +address_a[5] => ram_block1a210.PORTAADDR5 +address_a[5] => ram_block1a211.PORTAADDR5 +address_a[5] => ram_block1a212.PORTAADDR5 +address_a[5] => ram_block1a213.PORTAADDR5 +address_a[5] => ram_block1a214.PORTAADDR5 +address_a[5] => ram_block1a215.PORTAADDR5 +address_a[5] => ram_block1a216.PORTAADDR5 +address_a[5] => ram_block1a217.PORTAADDR5 +address_a[5] => ram_block1a218.PORTAADDR5 +address_a[5] => ram_block1a219.PORTAADDR5 +address_a[5] => ram_block1a220.PORTAADDR5 +address_a[5] => ram_block1a221.PORTAADDR5 +address_a[5] => ram_block1a222.PORTAADDR5 +address_a[5] => ram_block1a223.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[6] => ram_block1a21.PORTAADDR6 +address_a[6] => ram_block1a22.PORTAADDR6 +address_a[6] => ram_block1a23.PORTAADDR6 +address_a[6] => ram_block1a24.PORTAADDR6 +address_a[6] => ram_block1a25.PORTAADDR6 +address_a[6] => ram_block1a26.PORTAADDR6 +address_a[6] => ram_block1a27.PORTAADDR6 +address_a[6] => ram_block1a28.PORTAADDR6 +address_a[6] => ram_block1a29.PORTAADDR6 +address_a[6] => ram_block1a30.PORTAADDR6 +address_a[6] => ram_block1a31.PORTAADDR6 +address_a[6] => ram_block1a32.PORTAADDR6 +address_a[6] => ram_block1a33.PORTAADDR6 +address_a[6] => ram_block1a34.PORTAADDR6 +address_a[6] => ram_block1a35.PORTAADDR6 +address_a[6] => ram_block1a36.PORTAADDR6 +address_a[6] => ram_block1a37.PORTAADDR6 +address_a[6] => ram_block1a38.PORTAADDR6 +address_a[6] => ram_block1a39.PORTAADDR6 +address_a[6] => ram_block1a40.PORTAADDR6 +address_a[6] => ram_block1a41.PORTAADDR6 +address_a[6] => ram_block1a42.PORTAADDR6 +address_a[6] => ram_block1a43.PORTAADDR6 +address_a[6] => ram_block1a44.PORTAADDR6 +address_a[6] => ram_block1a45.PORTAADDR6 +address_a[6] => ram_block1a46.PORTAADDR6 +address_a[6] => ram_block1a47.PORTAADDR6 +address_a[6] => ram_block1a48.PORTAADDR6 +address_a[6] => ram_block1a49.PORTAADDR6 +address_a[6] => ram_block1a50.PORTAADDR6 +address_a[6] => ram_block1a51.PORTAADDR6 +address_a[6] => ram_block1a52.PORTAADDR6 +address_a[6] => ram_block1a53.PORTAADDR6 +address_a[6] => ram_block1a54.PORTAADDR6 +address_a[6] => ram_block1a55.PORTAADDR6 +address_a[6] => ram_block1a56.PORTAADDR6 +address_a[6] => ram_block1a57.PORTAADDR6 +address_a[6] => ram_block1a58.PORTAADDR6 +address_a[6] => ram_block1a59.PORTAADDR6 +address_a[6] => ram_block1a60.PORTAADDR6 +address_a[6] => ram_block1a61.PORTAADDR6 +address_a[6] => ram_block1a62.PORTAADDR6 +address_a[6] => ram_block1a63.PORTAADDR6 +address_a[6] => ram_block1a64.PORTAADDR6 +address_a[6] => ram_block1a65.PORTAADDR6 +address_a[6] => ram_block1a66.PORTAADDR6 +address_a[6] => ram_block1a67.PORTAADDR6 +address_a[6] => ram_block1a68.PORTAADDR6 +address_a[6] => ram_block1a69.PORTAADDR6 +address_a[6] => ram_block1a70.PORTAADDR6 +address_a[6] => ram_block1a71.PORTAADDR6 +address_a[6] => ram_block1a72.PORTAADDR6 +address_a[6] => ram_block1a73.PORTAADDR6 +address_a[6] => ram_block1a74.PORTAADDR6 +address_a[6] => ram_block1a75.PORTAADDR6 +address_a[6] => ram_block1a76.PORTAADDR6 +address_a[6] => ram_block1a77.PORTAADDR6 +address_a[6] => ram_block1a78.PORTAADDR6 +address_a[6] => ram_block1a79.PORTAADDR6 +address_a[6] => ram_block1a80.PORTAADDR6 +address_a[6] => ram_block1a81.PORTAADDR6 +address_a[6] => ram_block1a82.PORTAADDR6 +address_a[6] => ram_block1a83.PORTAADDR6 +address_a[6] => ram_block1a84.PORTAADDR6 +address_a[6] => ram_block1a85.PORTAADDR6 +address_a[6] => ram_block1a86.PORTAADDR6 +address_a[6] => ram_block1a87.PORTAADDR6 +address_a[6] => ram_block1a88.PORTAADDR6 +address_a[6] => ram_block1a89.PORTAADDR6 +address_a[6] => ram_block1a90.PORTAADDR6 +address_a[6] => ram_block1a91.PORTAADDR6 +address_a[6] => ram_block1a92.PORTAADDR6 +address_a[6] => ram_block1a93.PORTAADDR6 +address_a[6] => ram_block1a94.PORTAADDR6 +address_a[6] => ram_block1a95.PORTAADDR6 +address_a[6] => ram_block1a96.PORTAADDR6 +address_a[6] => ram_block1a97.PORTAADDR6 +address_a[6] => ram_block1a98.PORTAADDR6 +address_a[6] => ram_block1a99.PORTAADDR6 +address_a[6] => ram_block1a100.PORTAADDR6 +address_a[6] => ram_block1a101.PORTAADDR6 +address_a[6] => ram_block1a102.PORTAADDR6 +address_a[6] => ram_block1a103.PORTAADDR6 +address_a[6] => ram_block1a104.PORTAADDR6 +address_a[6] => ram_block1a105.PORTAADDR6 +address_a[6] => ram_block1a106.PORTAADDR6 +address_a[6] => ram_block1a107.PORTAADDR6 +address_a[6] => ram_block1a108.PORTAADDR6 +address_a[6] => ram_block1a109.PORTAADDR6 +address_a[6] => ram_block1a110.PORTAADDR6 +address_a[6] => ram_block1a111.PORTAADDR6 +address_a[6] => ram_block1a112.PORTAADDR6 +address_a[6] => ram_block1a113.PORTAADDR6 +address_a[6] => ram_block1a114.PORTAADDR6 +address_a[6] => ram_block1a115.PORTAADDR6 +address_a[6] => ram_block1a116.PORTAADDR6 +address_a[6] => ram_block1a117.PORTAADDR6 +address_a[6] => ram_block1a118.PORTAADDR6 +address_a[6] => ram_block1a119.PORTAADDR6 +address_a[6] => ram_block1a120.PORTAADDR6 +address_a[6] => ram_block1a121.PORTAADDR6 +address_a[6] => ram_block1a122.PORTAADDR6 +address_a[6] => ram_block1a123.PORTAADDR6 +address_a[6] => ram_block1a124.PORTAADDR6 +address_a[6] => ram_block1a125.PORTAADDR6 +address_a[6] => ram_block1a126.PORTAADDR6 +address_a[6] => ram_block1a127.PORTAADDR6 +address_a[6] => ram_block1a128.PORTAADDR6 +address_a[6] => ram_block1a129.PORTAADDR6 +address_a[6] => ram_block1a130.PORTAADDR6 +address_a[6] => ram_block1a131.PORTAADDR6 +address_a[6] => ram_block1a132.PORTAADDR6 +address_a[6] => ram_block1a133.PORTAADDR6 +address_a[6] => ram_block1a134.PORTAADDR6 +address_a[6] => ram_block1a135.PORTAADDR6 +address_a[6] => ram_block1a136.PORTAADDR6 +address_a[6] => ram_block1a137.PORTAADDR6 +address_a[6] => ram_block1a138.PORTAADDR6 +address_a[6] => ram_block1a139.PORTAADDR6 +address_a[6] => ram_block1a140.PORTAADDR6 +address_a[6] => ram_block1a141.PORTAADDR6 +address_a[6] => ram_block1a142.PORTAADDR6 +address_a[6] => ram_block1a143.PORTAADDR6 +address_a[6] => ram_block1a144.PORTAADDR6 +address_a[6] => ram_block1a145.PORTAADDR6 +address_a[6] => ram_block1a146.PORTAADDR6 +address_a[6] => ram_block1a147.PORTAADDR6 +address_a[6] => ram_block1a148.PORTAADDR6 +address_a[6] => ram_block1a149.PORTAADDR6 +address_a[6] => ram_block1a150.PORTAADDR6 +address_a[6] => ram_block1a151.PORTAADDR6 +address_a[6] => ram_block1a152.PORTAADDR6 +address_a[6] => ram_block1a153.PORTAADDR6 +address_a[6] => ram_block1a154.PORTAADDR6 +address_a[6] => ram_block1a155.PORTAADDR6 +address_a[6] => ram_block1a156.PORTAADDR6 +address_a[6] => ram_block1a157.PORTAADDR6 +address_a[6] => ram_block1a158.PORTAADDR6 +address_a[6] => ram_block1a159.PORTAADDR6 +address_a[6] => ram_block1a160.PORTAADDR6 +address_a[6] => ram_block1a161.PORTAADDR6 +address_a[6] => ram_block1a162.PORTAADDR6 +address_a[6] => ram_block1a163.PORTAADDR6 +address_a[6] => ram_block1a164.PORTAADDR6 +address_a[6] => ram_block1a165.PORTAADDR6 +address_a[6] => ram_block1a166.PORTAADDR6 +address_a[6] => ram_block1a167.PORTAADDR6 +address_a[6] => ram_block1a168.PORTAADDR6 +address_a[6] => ram_block1a169.PORTAADDR6 +address_a[6] => ram_block1a170.PORTAADDR6 +address_a[6] => ram_block1a171.PORTAADDR6 +address_a[6] => ram_block1a172.PORTAADDR6 +address_a[6] => ram_block1a173.PORTAADDR6 +address_a[6] => ram_block1a174.PORTAADDR6 +address_a[6] => ram_block1a175.PORTAADDR6 +address_a[6] => ram_block1a176.PORTAADDR6 +address_a[6] => ram_block1a177.PORTAADDR6 +address_a[6] => ram_block1a178.PORTAADDR6 +address_a[6] => ram_block1a179.PORTAADDR6 +address_a[6] => ram_block1a180.PORTAADDR6 +address_a[6] => ram_block1a181.PORTAADDR6 +address_a[6] => ram_block1a182.PORTAADDR6 +address_a[6] => ram_block1a183.PORTAADDR6 +address_a[6] => ram_block1a184.PORTAADDR6 +address_a[6] => ram_block1a185.PORTAADDR6 +address_a[6] => ram_block1a186.PORTAADDR6 +address_a[6] => ram_block1a187.PORTAADDR6 +address_a[6] => ram_block1a188.PORTAADDR6 +address_a[6] => ram_block1a189.PORTAADDR6 +address_a[6] => ram_block1a190.PORTAADDR6 +address_a[6] => ram_block1a191.PORTAADDR6 +address_a[6] => ram_block1a192.PORTAADDR6 +address_a[6] => ram_block1a193.PORTAADDR6 +address_a[6] => ram_block1a194.PORTAADDR6 +address_a[6] => ram_block1a195.PORTAADDR6 +address_a[6] => ram_block1a196.PORTAADDR6 +address_a[6] => ram_block1a197.PORTAADDR6 +address_a[6] => ram_block1a198.PORTAADDR6 +address_a[6] => ram_block1a199.PORTAADDR6 +address_a[6] => ram_block1a200.PORTAADDR6 +address_a[6] => ram_block1a201.PORTAADDR6 +address_a[6] => ram_block1a202.PORTAADDR6 +address_a[6] => ram_block1a203.PORTAADDR6 +address_a[6] => ram_block1a204.PORTAADDR6 +address_a[6] => ram_block1a205.PORTAADDR6 +address_a[6] => ram_block1a206.PORTAADDR6 +address_a[6] => ram_block1a207.PORTAADDR6 +address_a[6] => ram_block1a208.PORTAADDR6 +address_a[6] => ram_block1a209.PORTAADDR6 +address_a[6] => ram_block1a210.PORTAADDR6 +address_a[6] => ram_block1a211.PORTAADDR6 +address_a[6] => ram_block1a212.PORTAADDR6 +address_a[6] => ram_block1a213.PORTAADDR6 +address_a[6] => ram_block1a214.PORTAADDR6 +address_a[6] => ram_block1a215.PORTAADDR6 +address_a[6] => ram_block1a216.PORTAADDR6 +address_a[6] => ram_block1a217.PORTAADDR6 +address_a[6] => ram_block1a218.PORTAADDR6 +address_a[6] => ram_block1a219.PORTAADDR6 +address_a[6] => ram_block1a220.PORTAADDR6 +address_a[6] => ram_block1a221.PORTAADDR6 +address_a[6] => ram_block1a222.PORTAADDR6 +address_a[6] => ram_block1a223.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[7] => ram_block1a16.PORTAADDR7 +address_a[7] => ram_block1a17.PORTAADDR7 +address_a[7] => ram_block1a18.PORTAADDR7 +address_a[7] => ram_block1a19.PORTAADDR7 +address_a[7] => ram_block1a20.PORTAADDR7 +address_a[7] => ram_block1a21.PORTAADDR7 +address_a[7] => ram_block1a22.PORTAADDR7 +address_a[7] => ram_block1a23.PORTAADDR7 +address_a[7] => ram_block1a24.PORTAADDR7 +address_a[7] => ram_block1a25.PORTAADDR7 +address_a[7] => ram_block1a26.PORTAADDR7 +address_a[7] => ram_block1a27.PORTAADDR7 +address_a[7] => ram_block1a28.PORTAADDR7 +address_a[7] => ram_block1a29.PORTAADDR7 +address_a[7] => ram_block1a30.PORTAADDR7 +address_a[7] => ram_block1a31.PORTAADDR7 +address_a[7] => ram_block1a32.PORTAADDR7 +address_a[7] => ram_block1a33.PORTAADDR7 +address_a[7] => ram_block1a34.PORTAADDR7 +address_a[7] => ram_block1a35.PORTAADDR7 +address_a[7] => ram_block1a36.PORTAADDR7 +address_a[7] => ram_block1a37.PORTAADDR7 +address_a[7] => ram_block1a38.PORTAADDR7 +address_a[7] => ram_block1a39.PORTAADDR7 +address_a[7] => ram_block1a40.PORTAADDR7 +address_a[7] => ram_block1a41.PORTAADDR7 +address_a[7] => ram_block1a42.PORTAADDR7 +address_a[7] => ram_block1a43.PORTAADDR7 +address_a[7] => ram_block1a44.PORTAADDR7 +address_a[7] => ram_block1a45.PORTAADDR7 +address_a[7] => ram_block1a46.PORTAADDR7 +address_a[7] => ram_block1a47.PORTAADDR7 +address_a[7] => ram_block1a48.PORTAADDR7 +address_a[7] => ram_block1a49.PORTAADDR7 +address_a[7] => ram_block1a50.PORTAADDR7 +address_a[7] => ram_block1a51.PORTAADDR7 +address_a[7] => ram_block1a52.PORTAADDR7 +address_a[7] => ram_block1a53.PORTAADDR7 +address_a[7] => ram_block1a54.PORTAADDR7 +address_a[7] => ram_block1a55.PORTAADDR7 +address_a[7] => ram_block1a56.PORTAADDR7 +address_a[7] => ram_block1a57.PORTAADDR7 +address_a[7] => ram_block1a58.PORTAADDR7 +address_a[7] => ram_block1a59.PORTAADDR7 +address_a[7] => ram_block1a60.PORTAADDR7 +address_a[7] => ram_block1a61.PORTAADDR7 +address_a[7] => ram_block1a62.PORTAADDR7 +address_a[7] => ram_block1a63.PORTAADDR7 +address_a[7] => ram_block1a64.PORTAADDR7 +address_a[7] => ram_block1a65.PORTAADDR7 +address_a[7] => ram_block1a66.PORTAADDR7 +address_a[7] => ram_block1a67.PORTAADDR7 +address_a[7] => ram_block1a68.PORTAADDR7 +address_a[7] => ram_block1a69.PORTAADDR7 +address_a[7] => ram_block1a70.PORTAADDR7 +address_a[7] => ram_block1a71.PORTAADDR7 +address_a[7] => ram_block1a72.PORTAADDR7 +address_a[7] => ram_block1a73.PORTAADDR7 +address_a[7] => ram_block1a74.PORTAADDR7 +address_a[7] => ram_block1a75.PORTAADDR7 +address_a[7] => ram_block1a76.PORTAADDR7 +address_a[7] => ram_block1a77.PORTAADDR7 +address_a[7] => ram_block1a78.PORTAADDR7 +address_a[7] => ram_block1a79.PORTAADDR7 +address_a[7] => ram_block1a80.PORTAADDR7 +address_a[7] => ram_block1a81.PORTAADDR7 +address_a[7] => ram_block1a82.PORTAADDR7 +address_a[7] => ram_block1a83.PORTAADDR7 +address_a[7] => ram_block1a84.PORTAADDR7 +address_a[7] => ram_block1a85.PORTAADDR7 +address_a[7] => ram_block1a86.PORTAADDR7 +address_a[7] => ram_block1a87.PORTAADDR7 +address_a[7] => ram_block1a88.PORTAADDR7 +address_a[7] => ram_block1a89.PORTAADDR7 +address_a[7] => ram_block1a90.PORTAADDR7 +address_a[7] => ram_block1a91.PORTAADDR7 +address_a[7] => ram_block1a92.PORTAADDR7 +address_a[7] => ram_block1a93.PORTAADDR7 +address_a[7] => ram_block1a94.PORTAADDR7 +address_a[7] => ram_block1a95.PORTAADDR7 +address_a[7] => ram_block1a96.PORTAADDR7 +address_a[7] => ram_block1a97.PORTAADDR7 +address_a[7] => ram_block1a98.PORTAADDR7 +address_a[7] => ram_block1a99.PORTAADDR7 +address_a[7] => ram_block1a100.PORTAADDR7 +address_a[7] => ram_block1a101.PORTAADDR7 +address_a[7] => ram_block1a102.PORTAADDR7 +address_a[7] => ram_block1a103.PORTAADDR7 +address_a[7] => ram_block1a104.PORTAADDR7 +address_a[7] => ram_block1a105.PORTAADDR7 +address_a[7] => ram_block1a106.PORTAADDR7 +address_a[7] => ram_block1a107.PORTAADDR7 +address_a[7] => ram_block1a108.PORTAADDR7 +address_a[7] => ram_block1a109.PORTAADDR7 +address_a[7] => ram_block1a110.PORTAADDR7 +address_a[7] => ram_block1a111.PORTAADDR7 +address_a[7] => ram_block1a112.PORTAADDR7 +address_a[7] => ram_block1a113.PORTAADDR7 +address_a[7] => ram_block1a114.PORTAADDR7 +address_a[7] => ram_block1a115.PORTAADDR7 +address_a[7] => ram_block1a116.PORTAADDR7 +address_a[7] => ram_block1a117.PORTAADDR7 +address_a[7] => ram_block1a118.PORTAADDR7 +address_a[7] => ram_block1a119.PORTAADDR7 +address_a[7] => ram_block1a120.PORTAADDR7 +address_a[7] => ram_block1a121.PORTAADDR7 +address_a[7] => ram_block1a122.PORTAADDR7 +address_a[7] => ram_block1a123.PORTAADDR7 +address_a[7] => ram_block1a124.PORTAADDR7 +address_a[7] => ram_block1a125.PORTAADDR7 +address_a[7] => ram_block1a126.PORTAADDR7 +address_a[7] => ram_block1a127.PORTAADDR7 +address_a[7] => ram_block1a128.PORTAADDR7 +address_a[7] => ram_block1a129.PORTAADDR7 +address_a[7] => ram_block1a130.PORTAADDR7 +address_a[7] => ram_block1a131.PORTAADDR7 +address_a[7] => ram_block1a132.PORTAADDR7 +address_a[7] => ram_block1a133.PORTAADDR7 +address_a[7] => ram_block1a134.PORTAADDR7 +address_a[7] => ram_block1a135.PORTAADDR7 +address_a[7] => ram_block1a136.PORTAADDR7 +address_a[7] => ram_block1a137.PORTAADDR7 +address_a[7] => ram_block1a138.PORTAADDR7 +address_a[7] => ram_block1a139.PORTAADDR7 +address_a[7] => ram_block1a140.PORTAADDR7 +address_a[7] => ram_block1a141.PORTAADDR7 +address_a[7] => ram_block1a142.PORTAADDR7 +address_a[7] => ram_block1a143.PORTAADDR7 +address_a[7] => ram_block1a144.PORTAADDR7 +address_a[7] => ram_block1a145.PORTAADDR7 +address_a[7] => ram_block1a146.PORTAADDR7 +address_a[7] => ram_block1a147.PORTAADDR7 +address_a[7] => ram_block1a148.PORTAADDR7 +address_a[7] => ram_block1a149.PORTAADDR7 +address_a[7] => ram_block1a150.PORTAADDR7 +address_a[7] => ram_block1a151.PORTAADDR7 +address_a[7] => ram_block1a152.PORTAADDR7 +address_a[7] => ram_block1a153.PORTAADDR7 +address_a[7] => ram_block1a154.PORTAADDR7 +address_a[7] => ram_block1a155.PORTAADDR7 +address_a[7] => ram_block1a156.PORTAADDR7 +address_a[7] => ram_block1a157.PORTAADDR7 +address_a[7] => ram_block1a158.PORTAADDR7 +address_a[7] => ram_block1a159.PORTAADDR7 +address_a[7] => ram_block1a160.PORTAADDR7 +address_a[7] => ram_block1a161.PORTAADDR7 +address_a[7] => ram_block1a162.PORTAADDR7 +address_a[7] => ram_block1a163.PORTAADDR7 +address_a[7] => ram_block1a164.PORTAADDR7 +address_a[7] => ram_block1a165.PORTAADDR7 +address_a[7] => ram_block1a166.PORTAADDR7 +address_a[7] => ram_block1a167.PORTAADDR7 +address_a[7] => ram_block1a168.PORTAADDR7 +address_a[7] => ram_block1a169.PORTAADDR7 +address_a[7] => ram_block1a170.PORTAADDR7 +address_a[7] => ram_block1a171.PORTAADDR7 +address_a[7] => ram_block1a172.PORTAADDR7 +address_a[7] => ram_block1a173.PORTAADDR7 +address_a[7] => ram_block1a174.PORTAADDR7 +address_a[7] => ram_block1a175.PORTAADDR7 +address_a[7] => ram_block1a176.PORTAADDR7 +address_a[7] => ram_block1a177.PORTAADDR7 +address_a[7] => ram_block1a178.PORTAADDR7 +address_a[7] => ram_block1a179.PORTAADDR7 +address_a[7] => ram_block1a180.PORTAADDR7 +address_a[7] => ram_block1a181.PORTAADDR7 +address_a[7] => ram_block1a182.PORTAADDR7 +address_a[7] => ram_block1a183.PORTAADDR7 +address_a[7] => ram_block1a184.PORTAADDR7 +address_a[7] => ram_block1a185.PORTAADDR7 +address_a[7] => ram_block1a186.PORTAADDR7 +address_a[7] => ram_block1a187.PORTAADDR7 +address_a[7] => ram_block1a188.PORTAADDR7 +address_a[7] => ram_block1a189.PORTAADDR7 +address_a[7] => ram_block1a190.PORTAADDR7 +address_a[7] => ram_block1a191.PORTAADDR7 +address_a[7] => ram_block1a192.PORTAADDR7 +address_a[7] => ram_block1a193.PORTAADDR7 +address_a[7] => ram_block1a194.PORTAADDR7 +address_a[7] => ram_block1a195.PORTAADDR7 +address_a[7] => ram_block1a196.PORTAADDR7 +address_a[7] => ram_block1a197.PORTAADDR7 +address_a[7] => ram_block1a198.PORTAADDR7 +address_a[7] => ram_block1a199.PORTAADDR7 +address_a[7] => ram_block1a200.PORTAADDR7 +address_a[7] => ram_block1a201.PORTAADDR7 +address_a[7] => ram_block1a202.PORTAADDR7 +address_a[7] => ram_block1a203.PORTAADDR7 +address_a[7] => ram_block1a204.PORTAADDR7 +address_a[7] => ram_block1a205.PORTAADDR7 +address_a[7] => ram_block1a206.PORTAADDR7 +address_a[7] => ram_block1a207.PORTAADDR7 +address_a[7] => ram_block1a208.PORTAADDR7 +address_a[7] => ram_block1a209.PORTAADDR7 +address_a[7] => ram_block1a210.PORTAADDR7 +address_a[7] => ram_block1a211.PORTAADDR7 +address_a[7] => ram_block1a212.PORTAADDR7 +address_a[7] => ram_block1a213.PORTAADDR7 +address_a[7] => ram_block1a214.PORTAADDR7 +address_a[7] => ram_block1a215.PORTAADDR7 +address_a[7] => ram_block1a216.PORTAADDR7 +address_a[7] => ram_block1a217.PORTAADDR7 +address_a[7] => ram_block1a218.PORTAADDR7 +address_a[7] => ram_block1a219.PORTAADDR7 +address_a[7] => ram_block1a220.PORTAADDR7 +address_a[7] => ram_block1a221.PORTAADDR7 +address_a[7] => ram_block1a222.PORTAADDR7 +address_a[7] => ram_block1a223.PORTAADDR7 +address_a[8] => ram_block1a0.PORTAADDR8 +address_a[8] => ram_block1a1.PORTAADDR8 +address_a[8] => ram_block1a2.PORTAADDR8 +address_a[8] => ram_block1a3.PORTAADDR8 +address_a[8] => ram_block1a4.PORTAADDR8 +address_a[8] => ram_block1a5.PORTAADDR8 +address_a[8] => ram_block1a6.PORTAADDR8 +address_a[8] => ram_block1a7.PORTAADDR8 +address_a[8] => ram_block1a8.PORTAADDR8 +address_a[8] => ram_block1a9.PORTAADDR8 +address_a[8] => ram_block1a10.PORTAADDR8 +address_a[8] => ram_block1a11.PORTAADDR8 +address_a[8] => ram_block1a12.PORTAADDR8 +address_a[8] => ram_block1a13.PORTAADDR8 +address_a[8] => ram_block1a14.PORTAADDR8 +address_a[8] => ram_block1a15.PORTAADDR8 +address_a[8] => ram_block1a16.PORTAADDR8 +address_a[8] => ram_block1a17.PORTAADDR8 +address_a[8] => ram_block1a18.PORTAADDR8 +address_a[8] => ram_block1a19.PORTAADDR8 +address_a[8] => ram_block1a20.PORTAADDR8 +address_a[8] => ram_block1a21.PORTAADDR8 +address_a[8] => ram_block1a22.PORTAADDR8 +address_a[8] => ram_block1a23.PORTAADDR8 +address_a[8] => ram_block1a24.PORTAADDR8 +address_a[8] => ram_block1a25.PORTAADDR8 +address_a[8] => ram_block1a26.PORTAADDR8 +address_a[8] => ram_block1a27.PORTAADDR8 +address_a[8] => ram_block1a28.PORTAADDR8 +address_a[8] => ram_block1a29.PORTAADDR8 +address_a[8] => ram_block1a30.PORTAADDR8 +address_a[8] => ram_block1a31.PORTAADDR8 +address_a[8] => ram_block1a32.PORTAADDR8 +address_a[8] => ram_block1a33.PORTAADDR8 +address_a[8] => ram_block1a34.PORTAADDR8 +address_a[8] => ram_block1a35.PORTAADDR8 +address_a[8] => ram_block1a36.PORTAADDR8 +address_a[8] => ram_block1a37.PORTAADDR8 +address_a[8] => ram_block1a38.PORTAADDR8 +address_a[8] => ram_block1a39.PORTAADDR8 +address_a[8] => ram_block1a40.PORTAADDR8 +address_a[8] => ram_block1a41.PORTAADDR8 +address_a[8] => ram_block1a42.PORTAADDR8 +address_a[8] => ram_block1a43.PORTAADDR8 +address_a[8] => ram_block1a44.PORTAADDR8 +address_a[8] => ram_block1a45.PORTAADDR8 +address_a[8] => ram_block1a46.PORTAADDR8 +address_a[8] => ram_block1a47.PORTAADDR8 +address_a[8] => ram_block1a48.PORTAADDR8 +address_a[8] => ram_block1a49.PORTAADDR8 +address_a[8] => ram_block1a50.PORTAADDR8 +address_a[8] => ram_block1a51.PORTAADDR8 +address_a[8] => ram_block1a52.PORTAADDR8 +address_a[8] => ram_block1a53.PORTAADDR8 +address_a[8] => ram_block1a54.PORTAADDR8 +address_a[8] => ram_block1a55.PORTAADDR8 +address_a[8] => ram_block1a56.PORTAADDR8 +address_a[8] => ram_block1a57.PORTAADDR8 +address_a[8] => ram_block1a58.PORTAADDR8 +address_a[8] => ram_block1a59.PORTAADDR8 +address_a[8] => ram_block1a60.PORTAADDR8 +address_a[8] => ram_block1a61.PORTAADDR8 +address_a[8] => ram_block1a62.PORTAADDR8 +address_a[8] => ram_block1a63.PORTAADDR8 +address_a[8] => ram_block1a64.PORTAADDR8 +address_a[8] => ram_block1a65.PORTAADDR8 +address_a[8] => ram_block1a66.PORTAADDR8 +address_a[8] => ram_block1a67.PORTAADDR8 +address_a[8] => ram_block1a68.PORTAADDR8 +address_a[8] => ram_block1a69.PORTAADDR8 +address_a[8] => ram_block1a70.PORTAADDR8 +address_a[8] => ram_block1a71.PORTAADDR8 +address_a[8] => ram_block1a72.PORTAADDR8 +address_a[8] => ram_block1a73.PORTAADDR8 +address_a[8] => ram_block1a74.PORTAADDR8 +address_a[8] => ram_block1a75.PORTAADDR8 +address_a[8] => ram_block1a76.PORTAADDR8 +address_a[8] => ram_block1a77.PORTAADDR8 +address_a[8] => ram_block1a78.PORTAADDR8 +address_a[8] => ram_block1a79.PORTAADDR8 +address_a[8] => ram_block1a80.PORTAADDR8 +address_a[8] => ram_block1a81.PORTAADDR8 +address_a[8] => ram_block1a82.PORTAADDR8 +address_a[8] => ram_block1a83.PORTAADDR8 +address_a[8] => ram_block1a84.PORTAADDR8 +address_a[8] => ram_block1a85.PORTAADDR8 +address_a[8] => ram_block1a86.PORTAADDR8 +address_a[8] => ram_block1a87.PORTAADDR8 +address_a[8] => ram_block1a88.PORTAADDR8 +address_a[8] => ram_block1a89.PORTAADDR8 +address_a[8] => ram_block1a90.PORTAADDR8 +address_a[8] => ram_block1a91.PORTAADDR8 +address_a[8] => ram_block1a92.PORTAADDR8 +address_a[8] => ram_block1a93.PORTAADDR8 +address_a[8] => ram_block1a94.PORTAADDR8 +address_a[8] => ram_block1a95.PORTAADDR8 +address_a[8] => ram_block1a96.PORTAADDR8 +address_a[8] => ram_block1a97.PORTAADDR8 +address_a[8] => ram_block1a98.PORTAADDR8 +address_a[8] => ram_block1a99.PORTAADDR8 +address_a[8] => ram_block1a100.PORTAADDR8 +address_a[8] => ram_block1a101.PORTAADDR8 +address_a[8] => ram_block1a102.PORTAADDR8 +address_a[8] => ram_block1a103.PORTAADDR8 +address_a[8] => ram_block1a104.PORTAADDR8 +address_a[8] => ram_block1a105.PORTAADDR8 +address_a[8] => ram_block1a106.PORTAADDR8 +address_a[8] => ram_block1a107.PORTAADDR8 +address_a[8] => ram_block1a108.PORTAADDR8 +address_a[8] => ram_block1a109.PORTAADDR8 +address_a[8] => ram_block1a110.PORTAADDR8 +address_a[8] => ram_block1a111.PORTAADDR8 +address_a[8] => ram_block1a112.PORTAADDR8 +address_a[8] => ram_block1a113.PORTAADDR8 +address_a[8] => ram_block1a114.PORTAADDR8 +address_a[8] => ram_block1a115.PORTAADDR8 +address_a[8] => ram_block1a116.PORTAADDR8 +address_a[8] => ram_block1a117.PORTAADDR8 +address_a[8] => ram_block1a118.PORTAADDR8 +address_a[8] => ram_block1a119.PORTAADDR8 +address_a[8] => ram_block1a120.PORTAADDR8 +address_a[8] => ram_block1a121.PORTAADDR8 +address_a[8] => ram_block1a122.PORTAADDR8 +address_a[8] => ram_block1a123.PORTAADDR8 +address_a[8] => ram_block1a124.PORTAADDR8 +address_a[8] => ram_block1a125.PORTAADDR8 +address_a[8] => ram_block1a126.PORTAADDR8 +address_a[8] => ram_block1a127.PORTAADDR8 +address_a[8] => ram_block1a128.PORTAADDR8 +address_a[8] => ram_block1a129.PORTAADDR8 +address_a[8] => ram_block1a130.PORTAADDR8 +address_a[8] => ram_block1a131.PORTAADDR8 +address_a[8] => ram_block1a132.PORTAADDR8 +address_a[8] => ram_block1a133.PORTAADDR8 +address_a[8] => ram_block1a134.PORTAADDR8 +address_a[8] => ram_block1a135.PORTAADDR8 +address_a[8] => ram_block1a136.PORTAADDR8 +address_a[8] => ram_block1a137.PORTAADDR8 +address_a[8] => ram_block1a138.PORTAADDR8 +address_a[8] => ram_block1a139.PORTAADDR8 +address_a[8] => ram_block1a140.PORTAADDR8 +address_a[8] => ram_block1a141.PORTAADDR8 +address_a[8] => ram_block1a142.PORTAADDR8 +address_a[8] => ram_block1a143.PORTAADDR8 +address_a[8] => ram_block1a144.PORTAADDR8 +address_a[8] => ram_block1a145.PORTAADDR8 +address_a[8] => ram_block1a146.PORTAADDR8 +address_a[8] => ram_block1a147.PORTAADDR8 +address_a[8] => ram_block1a148.PORTAADDR8 +address_a[8] => ram_block1a149.PORTAADDR8 +address_a[8] => ram_block1a150.PORTAADDR8 +address_a[8] => ram_block1a151.PORTAADDR8 +address_a[8] => ram_block1a152.PORTAADDR8 +address_a[8] => ram_block1a153.PORTAADDR8 +address_a[8] => ram_block1a154.PORTAADDR8 +address_a[8] => ram_block1a155.PORTAADDR8 +address_a[8] => ram_block1a156.PORTAADDR8 +address_a[8] => ram_block1a157.PORTAADDR8 +address_a[8] => ram_block1a158.PORTAADDR8 +address_a[8] => ram_block1a159.PORTAADDR8 +address_a[8] => ram_block1a160.PORTAADDR8 +address_a[8] => ram_block1a161.PORTAADDR8 +address_a[8] => ram_block1a162.PORTAADDR8 +address_a[8] => ram_block1a163.PORTAADDR8 +address_a[8] => ram_block1a164.PORTAADDR8 +address_a[8] => ram_block1a165.PORTAADDR8 +address_a[8] => ram_block1a166.PORTAADDR8 +address_a[8] => ram_block1a167.PORTAADDR8 +address_a[8] => ram_block1a168.PORTAADDR8 +address_a[8] => ram_block1a169.PORTAADDR8 +address_a[8] => ram_block1a170.PORTAADDR8 +address_a[8] => ram_block1a171.PORTAADDR8 +address_a[8] => ram_block1a172.PORTAADDR8 +address_a[8] => ram_block1a173.PORTAADDR8 +address_a[8] => ram_block1a174.PORTAADDR8 +address_a[8] => ram_block1a175.PORTAADDR8 +address_a[8] => ram_block1a176.PORTAADDR8 +address_a[8] => ram_block1a177.PORTAADDR8 +address_a[8] => ram_block1a178.PORTAADDR8 +address_a[8] => ram_block1a179.PORTAADDR8 +address_a[8] => ram_block1a180.PORTAADDR8 +address_a[8] => ram_block1a181.PORTAADDR8 +address_a[8] => ram_block1a182.PORTAADDR8 +address_a[8] => ram_block1a183.PORTAADDR8 +address_a[8] => ram_block1a184.PORTAADDR8 +address_a[8] => ram_block1a185.PORTAADDR8 +address_a[8] => ram_block1a186.PORTAADDR8 +address_a[8] => ram_block1a187.PORTAADDR8 +address_a[8] => ram_block1a188.PORTAADDR8 +address_a[8] => ram_block1a189.PORTAADDR8 +address_a[8] => ram_block1a190.PORTAADDR8 +address_a[8] => ram_block1a191.PORTAADDR8 +address_a[8] => ram_block1a192.PORTAADDR8 +address_a[8] => ram_block1a193.PORTAADDR8 +address_a[8] => ram_block1a194.PORTAADDR8 +address_a[8] => ram_block1a195.PORTAADDR8 +address_a[8] => ram_block1a196.PORTAADDR8 +address_a[8] => ram_block1a197.PORTAADDR8 +address_a[8] => ram_block1a198.PORTAADDR8 +address_a[8] => ram_block1a199.PORTAADDR8 +address_a[8] => ram_block1a200.PORTAADDR8 +address_a[8] => ram_block1a201.PORTAADDR8 +address_a[8] => ram_block1a202.PORTAADDR8 +address_a[8] => ram_block1a203.PORTAADDR8 +address_a[8] => ram_block1a204.PORTAADDR8 +address_a[8] => ram_block1a205.PORTAADDR8 +address_a[8] => ram_block1a206.PORTAADDR8 +address_a[8] => ram_block1a207.PORTAADDR8 +address_a[8] => ram_block1a208.PORTAADDR8 +address_a[8] => ram_block1a209.PORTAADDR8 +address_a[8] => ram_block1a210.PORTAADDR8 +address_a[8] => ram_block1a211.PORTAADDR8 +address_a[8] => ram_block1a212.PORTAADDR8 +address_a[8] => ram_block1a213.PORTAADDR8 +address_a[8] => ram_block1a214.PORTAADDR8 +address_a[8] => ram_block1a215.PORTAADDR8 +address_a[8] => ram_block1a216.PORTAADDR8 +address_a[8] => ram_block1a217.PORTAADDR8 +address_a[8] => ram_block1a218.PORTAADDR8 +address_a[8] => ram_block1a219.PORTAADDR8 +address_a[8] => ram_block1a220.PORTAADDR8 +address_a[8] => ram_block1a221.PORTAADDR8 +address_a[8] => ram_block1a222.PORTAADDR8 +address_a[8] => ram_block1a223.PORTAADDR8 +address_a[9] => ram_block1a0.PORTAADDR9 +address_a[9] => ram_block1a1.PORTAADDR9 +address_a[9] => ram_block1a2.PORTAADDR9 +address_a[9] => ram_block1a3.PORTAADDR9 +address_a[9] => ram_block1a4.PORTAADDR9 +address_a[9] => ram_block1a5.PORTAADDR9 +address_a[9] => ram_block1a6.PORTAADDR9 +address_a[9] => ram_block1a7.PORTAADDR9 +address_a[9] => ram_block1a8.PORTAADDR9 +address_a[9] => ram_block1a9.PORTAADDR9 +address_a[9] => ram_block1a10.PORTAADDR9 +address_a[9] => ram_block1a11.PORTAADDR9 +address_a[9] => ram_block1a12.PORTAADDR9 +address_a[9] => ram_block1a13.PORTAADDR9 +address_a[9] => ram_block1a14.PORTAADDR9 +address_a[9] => ram_block1a15.PORTAADDR9 +address_a[9] => ram_block1a16.PORTAADDR9 +address_a[9] => ram_block1a17.PORTAADDR9 +address_a[9] => ram_block1a18.PORTAADDR9 +address_a[9] => ram_block1a19.PORTAADDR9 +address_a[9] => ram_block1a20.PORTAADDR9 +address_a[9] => ram_block1a21.PORTAADDR9 +address_a[9] => ram_block1a22.PORTAADDR9 +address_a[9] => ram_block1a23.PORTAADDR9 +address_a[9] => ram_block1a24.PORTAADDR9 +address_a[9] => ram_block1a25.PORTAADDR9 +address_a[9] => ram_block1a26.PORTAADDR9 +address_a[9] => ram_block1a27.PORTAADDR9 +address_a[9] => ram_block1a28.PORTAADDR9 +address_a[9] => ram_block1a29.PORTAADDR9 +address_a[9] => ram_block1a30.PORTAADDR9 +address_a[9] => ram_block1a31.PORTAADDR9 +address_a[9] => ram_block1a32.PORTAADDR9 +address_a[9] => ram_block1a33.PORTAADDR9 +address_a[9] => ram_block1a34.PORTAADDR9 +address_a[9] => ram_block1a35.PORTAADDR9 +address_a[9] => ram_block1a36.PORTAADDR9 +address_a[9] => ram_block1a37.PORTAADDR9 +address_a[9] => ram_block1a38.PORTAADDR9 +address_a[9] => ram_block1a39.PORTAADDR9 +address_a[9] => ram_block1a40.PORTAADDR9 +address_a[9] => ram_block1a41.PORTAADDR9 +address_a[9] => ram_block1a42.PORTAADDR9 +address_a[9] => ram_block1a43.PORTAADDR9 +address_a[9] => ram_block1a44.PORTAADDR9 +address_a[9] => ram_block1a45.PORTAADDR9 +address_a[9] => ram_block1a46.PORTAADDR9 +address_a[9] => ram_block1a47.PORTAADDR9 +address_a[9] => ram_block1a48.PORTAADDR9 +address_a[9] => ram_block1a49.PORTAADDR9 +address_a[9] => ram_block1a50.PORTAADDR9 +address_a[9] => ram_block1a51.PORTAADDR9 +address_a[9] => ram_block1a52.PORTAADDR9 +address_a[9] => ram_block1a53.PORTAADDR9 +address_a[9] => ram_block1a54.PORTAADDR9 +address_a[9] => ram_block1a55.PORTAADDR9 +address_a[9] => ram_block1a56.PORTAADDR9 +address_a[9] => ram_block1a57.PORTAADDR9 +address_a[9] => ram_block1a58.PORTAADDR9 +address_a[9] => ram_block1a59.PORTAADDR9 +address_a[9] => ram_block1a60.PORTAADDR9 +address_a[9] => ram_block1a61.PORTAADDR9 +address_a[9] => ram_block1a62.PORTAADDR9 +address_a[9] => ram_block1a63.PORTAADDR9 +address_a[9] => ram_block1a64.PORTAADDR9 +address_a[9] => ram_block1a65.PORTAADDR9 +address_a[9] => ram_block1a66.PORTAADDR9 +address_a[9] => ram_block1a67.PORTAADDR9 +address_a[9] => ram_block1a68.PORTAADDR9 +address_a[9] => ram_block1a69.PORTAADDR9 +address_a[9] => ram_block1a70.PORTAADDR9 +address_a[9] => ram_block1a71.PORTAADDR9 +address_a[9] => ram_block1a72.PORTAADDR9 +address_a[9] => ram_block1a73.PORTAADDR9 +address_a[9] => ram_block1a74.PORTAADDR9 +address_a[9] => ram_block1a75.PORTAADDR9 +address_a[9] => ram_block1a76.PORTAADDR9 +address_a[9] => ram_block1a77.PORTAADDR9 +address_a[9] => ram_block1a78.PORTAADDR9 +address_a[9] => ram_block1a79.PORTAADDR9 +address_a[9] => ram_block1a80.PORTAADDR9 +address_a[9] => ram_block1a81.PORTAADDR9 +address_a[9] => ram_block1a82.PORTAADDR9 +address_a[9] => ram_block1a83.PORTAADDR9 +address_a[9] => ram_block1a84.PORTAADDR9 +address_a[9] => ram_block1a85.PORTAADDR9 +address_a[9] => ram_block1a86.PORTAADDR9 +address_a[9] => ram_block1a87.PORTAADDR9 +address_a[9] => ram_block1a88.PORTAADDR9 +address_a[9] => ram_block1a89.PORTAADDR9 +address_a[9] => ram_block1a90.PORTAADDR9 +address_a[9] => ram_block1a91.PORTAADDR9 +address_a[9] => ram_block1a92.PORTAADDR9 +address_a[9] => ram_block1a93.PORTAADDR9 +address_a[9] => ram_block1a94.PORTAADDR9 +address_a[9] => ram_block1a95.PORTAADDR9 +address_a[9] => ram_block1a96.PORTAADDR9 +address_a[9] => ram_block1a97.PORTAADDR9 +address_a[9] => ram_block1a98.PORTAADDR9 +address_a[9] => ram_block1a99.PORTAADDR9 +address_a[9] => ram_block1a100.PORTAADDR9 +address_a[9] => ram_block1a101.PORTAADDR9 +address_a[9] => ram_block1a102.PORTAADDR9 +address_a[9] => ram_block1a103.PORTAADDR9 +address_a[9] => ram_block1a104.PORTAADDR9 +address_a[9] => ram_block1a105.PORTAADDR9 +address_a[9] => ram_block1a106.PORTAADDR9 +address_a[9] => ram_block1a107.PORTAADDR9 +address_a[9] => ram_block1a108.PORTAADDR9 +address_a[9] => ram_block1a109.PORTAADDR9 +address_a[9] => ram_block1a110.PORTAADDR9 +address_a[9] => ram_block1a111.PORTAADDR9 +address_a[9] => ram_block1a112.PORTAADDR9 +address_a[9] => ram_block1a113.PORTAADDR9 +address_a[9] => ram_block1a114.PORTAADDR9 +address_a[9] => ram_block1a115.PORTAADDR9 +address_a[9] => ram_block1a116.PORTAADDR9 +address_a[9] => ram_block1a117.PORTAADDR9 +address_a[9] => ram_block1a118.PORTAADDR9 +address_a[9] => ram_block1a119.PORTAADDR9 +address_a[9] => ram_block1a120.PORTAADDR9 +address_a[9] => ram_block1a121.PORTAADDR9 +address_a[9] => ram_block1a122.PORTAADDR9 +address_a[9] => ram_block1a123.PORTAADDR9 +address_a[9] => ram_block1a124.PORTAADDR9 +address_a[9] => ram_block1a125.PORTAADDR9 +address_a[9] => ram_block1a126.PORTAADDR9 +address_a[9] => ram_block1a127.PORTAADDR9 +address_a[9] => ram_block1a128.PORTAADDR9 +address_a[9] => ram_block1a129.PORTAADDR9 +address_a[9] => ram_block1a130.PORTAADDR9 +address_a[9] => ram_block1a131.PORTAADDR9 +address_a[9] => ram_block1a132.PORTAADDR9 +address_a[9] => ram_block1a133.PORTAADDR9 +address_a[9] => ram_block1a134.PORTAADDR9 +address_a[9] => ram_block1a135.PORTAADDR9 +address_a[9] => ram_block1a136.PORTAADDR9 +address_a[9] => ram_block1a137.PORTAADDR9 +address_a[9] => ram_block1a138.PORTAADDR9 +address_a[9] => ram_block1a139.PORTAADDR9 +address_a[9] => ram_block1a140.PORTAADDR9 +address_a[9] => ram_block1a141.PORTAADDR9 +address_a[9] => ram_block1a142.PORTAADDR9 +address_a[9] => ram_block1a143.PORTAADDR9 +address_a[9] => ram_block1a144.PORTAADDR9 +address_a[9] => ram_block1a145.PORTAADDR9 +address_a[9] => ram_block1a146.PORTAADDR9 +address_a[9] => ram_block1a147.PORTAADDR9 +address_a[9] => ram_block1a148.PORTAADDR9 +address_a[9] => ram_block1a149.PORTAADDR9 +address_a[9] => ram_block1a150.PORTAADDR9 +address_a[9] => ram_block1a151.PORTAADDR9 +address_a[9] => ram_block1a152.PORTAADDR9 +address_a[9] => ram_block1a153.PORTAADDR9 +address_a[9] => ram_block1a154.PORTAADDR9 +address_a[9] => ram_block1a155.PORTAADDR9 +address_a[9] => ram_block1a156.PORTAADDR9 +address_a[9] => ram_block1a157.PORTAADDR9 +address_a[9] => ram_block1a158.PORTAADDR9 +address_a[9] => ram_block1a159.PORTAADDR9 +address_a[9] => ram_block1a160.PORTAADDR9 +address_a[9] => ram_block1a161.PORTAADDR9 +address_a[9] => ram_block1a162.PORTAADDR9 +address_a[9] => ram_block1a163.PORTAADDR9 +address_a[9] => ram_block1a164.PORTAADDR9 +address_a[9] => ram_block1a165.PORTAADDR9 +address_a[9] => ram_block1a166.PORTAADDR9 +address_a[9] => ram_block1a167.PORTAADDR9 +address_a[9] => ram_block1a168.PORTAADDR9 +address_a[9] => ram_block1a169.PORTAADDR9 +address_a[9] => ram_block1a170.PORTAADDR9 +address_a[9] => ram_block1a171.PORTAADDR9 +address_a[9] => ram_block1a172.PORTAADDR9 +address_a[9] => ram_block1a173.PORTAADDR9 +address_a[9] => ram_block1a174.PORTAADDR9 +address_a[9] => ram_block1a175.PORTAADDR9 +address_a[9] => ram_block1a176.PORTAADDR9 +address_a[9] => ram_block1a177.PORTAADDR9 +address_a[9] => ram_block1a178.PORTAADDR9 +address_a[9] => ram_block1a179.PORTAADDR9 +address_a[9] => ram_block1a180.PORTAADDR9 +address_a[9] => ram_block1a181.PORTAADDR9 +address_a[9] => ram_block1a182.PORTAADDR9 +address_a[9] => ram_block1a183.PORTAADDR9 +address_a[9] => ram_block1a184.PORTAADDR9 +address_a[9] => ram_block1a185.PORTAADDR9 +address_a[9] => ram_block1a186.PORTAADDR9 +address_a[9] => ram_block1a187.PORTAADDR9 +address_a[9] => ram_block1a188.PORTAADDR9 +address_a[9] => ram_block1a189.PORTAADDR9 +address_a[9] => ram_block1a190.PORTAADDR9 +address_a[9] => ram_block1a191.PORTAADDR9 +address_a[9] => ram_block1a192.PORTAADDR9 +address_a[9] => ram_block1a193.PORTAADDR9 +address_a[9] => ram_block1a194.PORTAADDR9 +address_a[9] => ram_block1a195.PORTAADDR9 +address_a[9] => ram_block1a196.PORTAADDR9 +address_a[9] => ram_block1a197.PORTAADDR9 +address_a[9] => ram_block1a198.PORTAADDR9 +address_a[9] => ram_block1a199.PORTAADDR9 +address_a[9] => ram_block1a200.PORTAADDR9 +address_a[9] => ram_block1a201.PORTAADDR9 +address_a[9] => ram_block1a202.PORTAADDR9 +address_a[9] => ram_block1a203.PORTAADDR9 +address_a[9] => ram_block1a204.PORTAADDR9 +address_a[9] => ram_block1a205.PORTAADDR9 +address_a[9] => ram_block1a206.PORTAADDR9 +address_a[9] => ram_block1a207.PORTAADDR9 +address_a[9] => ram_block1a208.PORTAADDR9 +address_a[9] => ram_block1a209.PORTAADDR9 +address_a[9] => ram_block1a210.PORTAADDR9 +address_a[9] => ram_block1a211.PORTAADDR9 +address_a[9] => ram_block1a212.PORTAADDR9 +address_a[9] => ram_block1a213.PORTAADDR9 +address_a[9] => ram_block1a214.PORTAADDR9 +address_a[9] => ram_block1a215.PORTAADDR9 +address_a[9] => ram_block1a216.PORTAADDR9 +address_a[9] => ram_block1a217.PORTAADDR9 +address_a[9] => ram_block1a218.PORTAADDR9 +address_a[9] => ram_block1a219.PORTAADDR9 +address_a[9] => ram_block1a220.PORTAADDR9 +address_a[9] => ram_block1a221.PORTAADDR9 +address_a[9] => ram_block1a222.PORTAADDR9 +address_a[9] => ram_block1a223.PORTAADDR9 +address_a[10] => ram_block1a0.PORTAADDR10 +address_a[10] => ram_block1a1.PORTAADDR10 +address_a[10] => ram_block1a2.PORTAADDR10 +address_a[10] => ram_block1a3.PORTAADDR10 +address_a[10] => ram_block1a4.PORTAADDR10 +address_a[10] => ram_block1a5.PORTAADDR10 +address_a[10] => ram_block1a6.PORTAADDR10 +address_a[10] => ram_block1a7.PORTAADDR10 +address_a[10] => ram_block1a8.PORTAADDR10 +address_a[10] => ram_block1a9.PORTAADDR10 +address_a[10] => ram_block1a10.PORTAADDR10 +address_a[10] => ram_block1a11.PORTAADDR10 +address_a[10] => ram_block1a12.PORTAADDR10 +address_a[10] => ram_block1a13.PORTAADDR10 +address_a[10] => ram_block1a14.PORTAADDR10 +address_a[10] => ram_block1a15.PORTAADDR10 +address_a[10] => ram_block1a16.PORTAADDR10 +address_a[10] => ram_block1a17.PORTAADDR10 +address_a[10] => ram_block1a18.PORTAADDR10 +address_a[10] => ram_block1a19.PORTAADDR10 +address_a[10] => ram_block1a20.PORTAADDR10 +address_a[10] => ram_block1a21.PORTAADDR10 +address_a[10] => ram_block1a22.PORTAADDR10 +address_a[10] => ram_block1a23.PORTAADDR10 +address_a[10] => ram_block1a24.PORTAADDR10 +address_a[10] => ram_block1a25.PORTAADDR10 +address_a[10] => ram_block1a26.PORTAADDR10 +address_a[10] => ram_block1a27.PORTAADDR10 +address_a[10] => ram_block1a28.PORTAADDR10 +address_a[10] => ram_block1a29.PORTAADDR10 +address_a[10] => ram_block1a30.PORTAADDR10 +address_a[10] => ram_block1a31.PORTAADDR10 +address_a[10] => ram_block1a32.PORTAADDR10 +address_a[10] => ram_block1a33.PORTAADDR10 +address_a[10] => ram_block1a34.PORTAADDR10 +address_a[10] => ram_block1a35.PORTAADDR10 +address_a[10] => ram_block1a36.PORTAADDR10 +address_a[10] => ram_block1a37.PORTAADDR10 +address_a[10] => ram_block1a38.PORTAADDR10 +address_a[10] => ram_block1a39.PORTAADDR10 +address_a[10] => ram_block1a40.PORTAADDR10 +address_a[10] => ram_block1a41.PORTAADDR10 +address_a[10] => ram_block1a42.PORTAADDR10 +address_a[10] => ram_block1a43.PORTAADDR10 +address_a[10] => ram_block1a44.PORTAADDR10 +address_a[10] => ram_block1a45.PORTAADDR10 +address_a[10] => ram_block1a46.PORTAADDR10 +address_a[10] => ram_block1a47.PORTAADDR10 +address_a[10] => ram_block1a48.PORTAADDR10 +address_a[10] => ram_block1a49.PORTAADDR10 +address_a[10] => ram_block1a50.PORTAADDR10 +address_a[10] => ram_block1a51.PORTAADDR10 +address_a[10] => ram_block1a52.PORTAADDR10 +address_a[10] => ram_block1a53.PORTAADDR10 +address_a[10] => ram_block1a54.PORTAADDR10 +address_a[10] => ram_block1a55.PORTAADDR10 +address_a[10] => ram_block1a56.PORTAADDR10 +address_a[10] => ram_block1a57.PORTAADDR10 +address_a[10] => ram_block1a58.PORTAADDR10 +address_a[10] => ram_block1a59.PORTAADDR10 +address_a[10] => ram_block1a60.PORTAADDR10 +address_a[10] => ram_block1a61.PORTAADDR10 +address_a[10] => ram_block1a62.PORTAADDR10 +address_a[10] => ram_block1a63.PORTAADDR10 +address_a[10] => ram_block1a64.PORTAADDR10 +address_a[10] => ram_block1a65.PORTAADDR10 +address_a[10] => ram_block1a66.PORTAADDR10 +address_a[10] => ram_block1a67.PORTAADDR10 +address_a[10] => ram_block1a68.PORTAADDR10 +address_a[10] => ram_block1a69.PORTAADDR10 +address_a[10] => ram_block1a70.PORTAADDR10 +address_a[10] => ram_block1a71.PORTAADDR10 +address_a[10] => ram_block1a72.PORTAADDR10 +address_a[10] => ram_block1a73.PORTAADDR10 +address_a[10] => ram_block1a74.PORTAADDR10 +address_a[10] => ram_block1a75.PORTAADDR10 +address_a[10] => ram_block1a76.PORTAADDR10 +address_a[10] => ram_block1a77.PORTAADDR10 +address_a[10] => ram_block1a78.PORTAADDR10 +address_a[10] => ram_block1a79.PORTAADDR10 +address_a[10] => ram_block1a80.PORTAADDR10 +address_a[10] => ram_block1a81.PORTAADDR10 +address_a[10] => ram_block1a82.PORTAADDR10 +address_a[10] => ram_block1a83.PORTAADDR10 +address_a[10] => ram_block1a84.PORTAADDR10 +address_a[10] => ram_block1a85.PORTAADDR10 +address_a[10] => ram_block1a86.PORTAADDR10 +address_a[10] => ram_block1a87.PORTAADDR10 +address_a[10] => ram_block1a88.PORTAADDR10 +address_a[10] => ram_block1a89.PORTAADDR10 +address_a[10] => ram_block1a90.PORTAADDR10 +address_a[10] => ram_block1a91.PORTAADDR10 +address_a[10] => ram_block1a92.PORTAADDR10 +address_a[10] => ram_block1a93.PORTAADDR10 +address_a[10] => ram_block1a94.PORTAADDR10 +address_a[10] => ram_block1a95.PORTAADDR10 +address_a[10] => ram_block1a96.PORTAADDR10 +address_a[10] => ram_block1a97.PORTAADDR10 +address_a[10] => ram_block1a98.PORTAADDR10 +address_a[10] => ram_block1a99.PORTAADDR10 +address_a[10] => ram_block1a100.PORTAADDR10 +address_a[10] => ram_block1a101.PORTAADDR10 +address_a[10] => ram_block1a102.PORTAADDR10 +address_a[10] => ram_block1a103.PORTAADDR10 +address_a[10] => ram_block1a104.PORTAADDR10 +address_a[10] => ram_block1a105.PORTAADDR10 +address_a[10] => ram_block1a106.PORTAADDR10 +address_a[10] => ram_block1a107.PORTAADDR10 +address_a[10] => ram_block1a108.PORTAADDR10 +address_a[10] => ram_block1a109.PORTAADDR10 +address_a[10] => ram_block1a110.PORTAADDR10 +address_a[10] => ram_block1a111.PORTAADDR10 +address_a[10] => ram_block1a112.PORTAADDR10 +address_a[10] => ram_block1a113.PORTAADDR10 +address_a[10] => ram_block1a114.PORTAADDR10 +address_a[10] => ram_block1a115.PORTAADDR10 +address_a[10] => ram_block1a116.PORTAADDR10 +address_a[10] => ram_block1a117.PORTAADDR10 +address_a[10] => ram_block1a118.PORTAADDR10 +address_a[10] => ram_block1a119.PORTAADDR10 +address_a[10] => ram_block1a120.PORTAADDR10 +address_a[10] => ram_block1a121.PORTAADDR10 +address_a[10] => ram_block1a122.PORTAADDR10 +address_a[10] => ram_block1a123.PORTAADDR10 +address_a[10] => ram_block1a124.PORTAADDR10 +address_a[10] => ram_block1a125.PORTAADDR10 +address_a[10] => ram_block1a126.PORTAADDR10 +address_a[10] => ram_block1a127.PORTAADDR10 +address_a[10] => ram_block1a128.PORTAADDR10 +address_a[10] => ram_block1a129.PORTAADDR10 +address_a[10] => ram_block1a130.PORTAADDR10 +address_a[10] => ram_block1a131.PORTAADDR10 +address_a[10] => ram_block1a132.PORTAADDR10 +address_a[10] => ram_block1a133.PORTAADDR10 +address_a[10] => ram_block1a134.PORTAADDR10 +address_a[10] => ram_block1a135.PORTAADDR10 +address_a[10] => ram_block1a136.PORTAADDR10 +address_a[10] => ram_block1a137.PORTAADDR10 +address_a[10] => ram_block1a138.PORTAADDR10 +address_a[10] => ram_block1a139.PORTAADDR10 +address_a[10] => ram_block1a140.PORTAADDR10 +address_a[10] => ram_block1a141.PORTAADDR10 +address_a[10] => ram_block1a142.PORTAADDR10 +address_a[10] => ram_block1a143.PORTAADDR10 +address_a[10] => ram_block1a144.PORTAADDR10 +address_a[10] => ram_block1a145.PORTAADDR10 +address_a[10] => ram_block1a146.PORTAADDR10 +address_a[10] => ram_block1a147.PORTAADDR10 +address_a[10] => ram_block1a148.PORTAADDR10 +address_a[10] => ram_block1a149.PORTAADDR10 +address_a[10] => ram_block1a150.PORTAADDR10 +address_a[10] => ram_block1a151.PORTAADDR10 +address_a[10] => ram_block1a152.PORTAADDR10 +address_a[10] => ram_block1a153.PORTAADDR10 +address_a[10] => ram_block1a154.PORTAADDR10 +address_a[10] => ram_block1a155.PORTAADDR10 +address_a[10] => ram_block1a156.PORTAADDR10 +address_a[10] => ram_block1a157.PORTAADDR10 +address_a[10] => ram_block1a158.PORTAADDR10 +address_a[10] => ram_block1a159.PORTAADDR10 +address_a[10] => ram_block1a160.PORTAADDR10 +address_a[10] => ram_block1a161.PORTAADDR10 +address_a[10] => ram_block1a162.PORTAADDR10 +address_a[10] => ram_block1a163.PORTAADDR10 +address_a[10] => ram_block1a164.PORTAADDR10 +address_a[10] => ram_block1a165.PORTAADDR10 +address_a[10] => ram_block1a166.PORTAADDR10 +address_a[10] => ram_block1a167.PORTAADDR10 +address_a[10] => ram_block1a168.PORTAADDR10 +address_a[10] => ram_block1a169.PORTAADDR10 +address_a[10] => ram_block1a170.PORTAADDR10 +address_a[10] => ram_block1a171.PORTAADDR10 +address_a[10] => ram_block1a172.PORTAADDR10 +address_a[10] => ram_block1a173.PORTAADDR10 +address_a[10] => ram_block1a174.PORTAADDR10 +address_a[10] => ram_block1a175.PORTAADDR10 +address_a[10] => ram_block1a176.PORTAADDR10 +address_a[10] => ram_block1a177.PORTAADDR10 +address_a[10] => ram_block1a178.PORTAADDR10 +address_a[10] => ram_block1a179.PORTAADDR10 +address_a[10] => ram_block1a180.PORTAADDR10 +address_a[10] => ram_block1a181.PORTAADDR10 +address_a[10] => ram_block1a182.PORTAADDR10 +address_a[10] => ram_block1a183.PORTAADDR10 +address_a[10] => ram_block1a184.PORTAADDR10 +address_a[10] => ram_block1a185.PORTAADDR10 +address_a[10] => ram_block1a186.PORTAADDR10 +address_a[10] => ram_block1a187.PORTAADDR10 +address_a[10] => ram_block1a188.PORTAADDR10 +address_a[10] => ram_block1a189.PORTAADDR10 +address_a[10] => ram_block1a190.PORTAADDR10 +address_a[10] => ram_block1a191.PORTAADDR10 +address_a[10] => ram_block1a192.PORTAADDR10 +address_a[10] => ram_block1a193.PORTAADDR10 +address_a[10] => ram_block1a194.PORTAADDR10 +address_a[10] => ram_block1a195.PORTAADDR10 +address_a[10] => ram_block1a196.PORTAADDR10 +address_a[10] => ram_block1a197.PORTAADDR10 +address_a[10] => ram_block1a198.PORTAADDR10 +address_a[10] => ram_block1a199.PORTAADDR10 +address_a[10] => ram_block1a200.PORTAADDR10 +address_a[10] => ram_block1a201.PORTAADDR10 +address_a[10] => ram_block1a202.PORTAADDR10 +address_a[10] => ram_block1a203.PORTAADDR10 +address_a[10] => ram_block1a204.PORTAADDR10 +address_a[10] => ram_block1a205.PORTAADDR10 +address_a[10] => ram_block1a206.PORTAADDR10 +address_a[10] => ram_block1a207.PORTAADDR10 +address_a[10] => ram_block1a208.PORTAADDR10 +address_a[10] => ram_block1a209.PORTAADDR10 +address_a[10] => ram_block1a210.PORTAADDR10 +address_a[10] => ram_block1a211.PORTAADDR10 +address_a[10] => ram_block1a212.PORTAADDR10 +address_a[10] => ram_block1a213.PORTAADDR10 +address_a[10] => ram_block1a214.PORTAADDR10 +address_a[10] => ram_block1a215.PORTAADDR10 +address_a[10] => ram_block1a216.PORTAADDR10 +address_a[10] => ram_block1a217.PORTAADDR10 +address_a[10] => ram_block1a218.PORTAADDR10 +address_a[10] => ram_block1a219.PORTAADDR10 +address_a[10] => ram_block1a220.PORTAADDR10 +address_a[10] => ram_block1a221.PORTAADDR10 +address_a[10] => ram_block1a222.PORTAADDR10 +address_a[10] => ram_block1a223.PORTAADDR10 +address_a[11] => ram_block1a0.PORTAADDR11 +address_a[11] => ram_block1a1.PORTAADDR11 +address_a[11] => ram_block1a2.PORTAADDR11 +address_a[11] => ram_block1a3.PORTAADDR11 +address_a[11] => ram_block1a4.PORTAADDR11 +address_a[11] => ram_block1a5.PORTAADDR11 +address_a[11] => ram_block1a6.PORTAADDR11 +address_a[11] => ram_block1a7.PORTAADDR11 +address_a[11] => ram_block1a8.PORTAADDR11 +address_a[11] => ram_block1a9.PORTAADDR11 +address_a[11] => ram_block1a10.PORTAADDR11 +address_a[11] => ram_block1a11.PORTAADDR11 +address_a[11] => ram_block1a12.PORTAADDR11 +address_a[11] => ram_block1a13.PORTAADDR11 +address_a[11] => ram_block1a14.PORTAADDR11 +address_a[11] => ram_block1a15.PORTAADDR11 +address_a[11] => ram_block1a16.PORTAADDR11 +address_a[11] => ram_block1a17.PORTAADDR11 +address_a[11] => ram_block1a18.PORTAADDR11 +address_a[11] => ram_block1a19.PORTAADDR11 +address_a[11] => ram_block1a20.PORTAADDR11 +address_a[11] => ram_block1a21.PORTAADDR11 +address_a[11] => ram_block1a22.PORTAADDR11 +address_a[11] => ram_block1a23.PORTAADDR11 +address_a[11] => ram_block1a24.PORTAADDR11 +address_a[11] => ram_block1a25.PORTAADDR11 +address_a[11] => ram_block1a26.PORTAADDR11 +address_a[11] => ram_block1a27.PORTAADDR11 +address_a[11] => ram_block1a28.PORTAADDR11 +address_a[11] => ram_block1a29.PORTAADDR11 +address_a[11] => ram_block1a30.PORTAADDR11 +address_a[11] => ram_block1a31.PORTAADDR11 +address_a[11] => ram_block1a32.PORTAADDR11 +address_a[11] => ram_block1a33.PORTAADDR11 +address_a[11] => ram_block1a34.PORTAADDR11 +address_a[11] => ram_block1a35.PORTAADDR11 +address_a[11] => ram_block1a36.PORTAADDR11 +address_a[11] => ram_block1a37.PORTAADDR11 +address_a[11] => ram_block1a38.PORTAADDR11 +address_a[11] => ram_block1a39.PORTAADDR11 +address_a[11] => ram_block1a40.PORTAADDR11 +address_a[11] => ram_block1a41.PORTAADDR11 +address_a[11] => ram_block1a42.PORTAADDR11 +address_a[11] => ram_block1a43.PORTAADDR11 +address_a[11] => ram_block1a44.PORTAADDR11 +address_a[11] => ram_block1a45.PORTAADDR11 +address_a[11] => ram_block1a46.PORTAADDR11 +address_a[11] => ram_block1a47.PORTAADDR11 +address_a[11] => ram_block1a48.PORTAADDR11 +address_a[11] => ram_block1a49.PORTAADDR11 +address_a[11] => ram_block1a50.PORTAADDR11 +address_a[11] => ram_block1a51.PORTAADDR11 +address_a[11] => ram_block1a52.PORTAADDR11 +address_a[11] => ram_block1a53.PORTAADDR11 +address_a[11] => ram_block1a54.PORTAADDR11 +address_a[11] => ram_block1a55.PORTAADDR11 +address_a[11] => ram_block1a56.PORTAADDR11 +address_a[11] => ram_block1a57.PORTAADDR11 +address_a[11] => ram_block1a58.PORTAADDR11 +address_a[11] => ram_block1a59.PORTAADDR11 +address_a[11] => ram_block1a60.PORTAADDR11 +address_a[11] => ram_block1a61.PORTAADDR11 +address_a[11] => ram_block1a62.PORTAADDR11 +address_a[11] => ram_block1a63.PORTAADDR11 +address_a[11] => ram_block1a64.PORTAADDR11 +address_a[11] => ram_block1a65.PORTAADDR11 +address_a[11] => ram_block1a66.PORTAADDR11 +address_a[11] => ram_block1a67.PORTAADDR11 +address_a[11] => ram_block1a68.PORTAADDR11 +address_a[11] => ram_block1a69.PORTAADDR11 +address_a[11] => ram_block1a70.PORTAADDR11 +address_a[11] => ram_block1a71.PORTAADDR11 +address_a[11] => ram_block1a72.PORTAADDR11 +address_a[11] => ram_block1a73.PORTAADDR11 +address_a[11] => ram_block1a74.PORTAADDR11 +address_a[11] => ram_block1a75.PORTAADDR11 +address_a[11] => ram_block1a76.PORTAADDR11 +address_a[11] => ram_block1a77.PORTAADDR11 +address_a[11] => ram_block1a78.PORTAADDR11 +address_a[11] => ram_block1a79.PORTAADDR11 +address_a[11] => ram_block1a80.PORTAADDR11 +address_a[11] => ram_block1a81.PORTAADDR11 +address_a[11] => ram_block1a82.PORTAADDR11 +address_a[11] => ram_block1a83.PORTAADDR11 +address_a[11] => ram_block1a84.PORTAADDR11 +address_a[11] => ram_block1a85.PORTAADDR11 +address_a[11] => ram_block1a86.PORTAADDR11 +address_a[11] => ram_block1a87.PORTAADDR11 +address_a[11] => ram_block1a88.PORTAADDR11 +address_a[11] => ram_block1a89.PORTAADDR11 +address_a[11] => ram_block1a90.PORTAADDR11 +address_a[11] => ram_block1a91.PORTAADDR11 +address_a[11] => ram_block1a92.PORTAADDR11 +address_a[11] => ram_block1a93.PORTAADDR11 +address_a[11] => ram_block1a94.PORTAADDR11 +address_a[11] => ram_block1a95.PORTAADDR11 +address_a[11] => ram_block1a96.PORTAADDR11 +address_a[11] => ram_block1a97.PORTAADDR11 +address_a[11] => ram_block1a98.PORTAADDR11 +address_a[11] => ram_block1a99.PORTAADDR11 +address_a[11] => ram_block1a100.PORTAADDR11 +address_a[11] => ram_block1a101.PORTAADDR11 +address_a[11] => ram_block1a102.PORTAADDR11 +address_a[11] => ram_block1a103.PORTAADDR11 +address_a[11] => ram_block1a104.PORTAADDR11 +address_a[11] => ram_block1a105.PORTAADDR11 +address_a[11] => ram_block1a106.PORTAADDR11 +address_a[11] => ram_block1a107.PORTAADDR11 +address_a[11] => ram_block1a108.PORTAADDR11 +address_a[11] => ram_block1a109.PORTAADDR11 +address_a[11] => ram_block1a110.PORTAADDR11 +address_a[11] => ram_block1a111.PORTAADDR11 +address_a[11] => ram_block1a112.PORTAADDR11 +address_a[11] => ram_block1a113.PORTAADDR11 +address_a[11] => ram_block1a114.PORTAADDR11 +address_a[11] => ram_block1a115.PORTAADDR11 +address_a[11] => ram_block1a116.PORTAADDR11 +address_a[11] => ram_block1a117.PORTAADDR11 +address_a[11] => ram_block1a118.PORTAADDR11 +address_a[11] => ram_block1a119.PORTAADDR11 +address_a[11] => ram_block1a120.PORTAADDR11 +address_a[11] => ram_block1a121.PORTAADDR11 +address_a[11] => ram_block1a122.PORTAADDR11 +address_a[11] => ram_block1a123.PORTAADDR11 +address_a[11] => ram_block1a124.PORTAADDR11 +address_a[11] => ram_block1a125.PORTAADDR11 +address_a[11] => ram_block1a126.PORTAADDR11 +address_a[11] => ram_block1a127.PORTAADDR11 +address_a[11] => ram_block1a128.PORTAADDR11 +address_a[11] => ram_block1a129.PORTAADDR11 +address_a[11] => ram_block1a130.PORTAADDR11 +address_a[11] => ram_block1a131.PORTAADDR11 +address_a[11] => ram_block1a132.PORTAADDR11 +address_a[11] => ram_block1a133.PORTAADDR11 +address_a[11] => ram_block1a134.PORTAADDR11 +address_a[11] => ram_block1a135.PORTAADDR11 +address_a[11] => ram_block1a136.PORTAADDR11 +address_a[11] => ram_block1a137.PORTAADDR11 +address_a[11] => ram_block1a138.PORTAADDR11 +address_a[11] => ram_block1a139.PORTAADDR11 +address_a[11] => ram_block1a140.PORTAADDR11 +address_a[11] => ram_block1a141.PORTAADDR11 +address_a[11] => ram_block1a142.PORTAADDR11 +address_a[11] => ram_block1a143.PORTAADDR11 +address_a[11] => ram_block1a144.PORTAADDR11 +address_a[11] => ram_block1a145.PORTAADDR11 +address_a[11] => ram_block1a146.PORTAADDR11 +address_a[11] => ram_block1a147.PORTAADDR11 +address_a[11] => ram_block1a148.PORTAADDR11 +address_a[11] => ram_block1a149.PORTAADDR11 +address_a[11] => ram_block1a150.PORTAADDR11 +address_a[11] => ram_block1a151.PORTAADDR11 +address_a[11] => ram_block1a152.PORTAADDR11 +address_a[11] => ram_block1a153.PORTAADDR11 +address_a[11] => ram_block1a154.PORTAADDR11 +address_a[11] => ram_block1a155.PORTAADDR11 +address_a[11] => ram_block1a156.PORTAADDR11 +address_a[11] => ram_block1a157.PORTAADDR11 +address_a[11] => ram_block1a158.PORTAADDR11 +address_a[11] => ram_block1a159.PORTAADDR11 +address_a[11] => ram_block1a160.PORTAADDR11 +address_a[11] => ram_block1a161.PORTAADDR11 +address_a[11] => ram_block1a162.PORTAADDR11 +address_a[11] => ram_block1a163.PORTAADDR11 +address_a[11] => ram_block1a164.PORTAADDR11 +address_a[11] => ram_block1a165.PORTAADDR11 +address_a[11] => ram_block1a166.PORTAADDR11 +address_a[11] => ram_block1a167.PORTAADDR11 +address_a[11] => ram_block1a168.PORTAADDR11 +address_a[11] => ram_block1a169.PORTAADDR11 +address_a[11] => ram_block1a170.PORTAADDR11 +address_a[11] => ram_block1a171.PORTAADDR11 +address_a[11] => ram_block1a172.PORTAADDR11 +address_a[11] => ram_block1a173.PORTAADDR11 +address_a[11] => ram_block1a174.PORTAADDR11 +address_a[11] => ram_block1a175.PORTAADDR11 +address_a[11] => ram_block1a176.PORTAADDR11 +address_a[11] => ram_block1a177.PORTAADDR11 +address_a[11] => ram_block1a178.PORTAADDR11 +address_a[11] => ram_block1a179.PORTAADDR11 +address_a[11] => ram_block1a180.PORTAADDR11 +address_a[11] => ram_block1a181.PORTAADDR11 +address_a[11] => ram_block1a182.PORTAADDR11 +address_a[11] => ram_block1a183.PORTAADDR11 +address_a[11] => ram_block1a184.PORTAADDR11 +address_a[11] => ram_block1a185.PORTAADDR11 +address_a[11] => ram_block1a186.PORTAADDR11 +address_a[11] => ram_block1a187.PORTAADDR11 +address_a[11] => ram_block1a188.PORTAADDR11 +address_a[11] => ram_block1a189.PORTAADDR11 +address_a[11] => ram_block1a190.PORTAADDR11 +address_a[11] => ram_block1a191.PORTAADDR11 +address_a[12] => ram_block1a0.PORTAADDR12 +address_a[12] => ram_block1a1.PORTAADDR12 +address_a[12] => ram_block1a2.PORTAADDR12 +address_a[12] => ram_block1a3.PORTAADDR12 +address_a[12] => ram_block1a4.PORTAADDR12 +address_a[12] => ram_block1a5.PORTAADDR12 +address_a[12] => ram_block1a6.PORTAADDR12 +address_a[12] => ram_block1a7.PORTAADDR12 +address_a[12] => ram_block1a8.PORTAADDR12 +address_a[12] => ram_block1a9.PORTAADDR12 +address_a[12] => ram_block1a10.PORTAADDR12 +address_a[12] => ram_block1a11.PORTAADDR12 +address_a[12] => ram_block1a12.PORTAADDR12 +address_a[12] => ram_block1a13.PORTAADDR12 +address_a[12] => ram_block1a14.PORTAADDR12 +address_a[12] => ram_block1a15.PORTAADDR12 +address_a[12] => ram_block1a16.PORTAADDR12 +address_a[12] => ram_block1a17.PORTAADDR12 +address_a[12] => ram_block1a18.PORTAADDR12 +address_a[12] => ram_block1a19.PORTAADDR12 +address_a[12] => ram_block1a20.PORTAADDR12 +address_a[12] => ram_block1a21.PORTAADDR12 +address_a[12] => ram_block1a22.PORTAADDR12 +address_a[12] => ram_block1a23.PORTAADDR12 +address_a[12] => ram_block1a24.PORTAADDR12 +address_a[12] => ram_block1a25.PORTAADDR12 +address_a[12] => ram_block1a26.PORTAADDR12 +address_a[12] => ram_block1a27.PORTAADDR12 +address_a[12] => ram_block1a28.PORTAADDR12 +address_a[12] => ram_block1a29.PORTAADDR12 +address_a[12] => ram_block1a30.PORTAADDR12 +address_a[12] => ram_block1a31.PORTAADDR12 +address_a[12] => ram_block1a32.PORTAADDR12 +address_a[12] => ram_block1a33.PORTAADDR12 +address_a[12] => ram_block1a34.PORTAADDR12 +address_a[12] => ram_block1a35.PORTAADDR12 +address_a[12] => ram_block1a36.PORTAADDR12 +address_a[12] => ram_block1a37.PORTAADDR12 +address_a[12] => ram_block1a38.PORTAADDR12 +address_a[12] => ram_block1a39.PORTAADDR12 +address_a[12] => ram_block1a40.PORTAADDR12 +address_a[12] => ram_block1a41.PORTAADDR12 +address_a[12] => ram_block1a42.PORTAADDR12 +address_a[12] => ram_block1a43.PORTAADDR12 +address_a[12] => ram_block1a44.PORTAADDR12 +address_a[12] => ram_block1a45.PORTAADDR12 +address_a[12] => ram_block1a46.PORTAADDR12 +address_a[12] => ram_block1a47.PORTAADDR12 +address_a[12] => ram_block1a48.PORTAADDR12 +address_a[12] => ram_block1a49.PORTAADDR12 +address_a[12] => ram_block1a50.PORTAADDR12 +address_a[12] => ram_block1a51.PORTAADDR12 +address_a[12] => ram_block1a52.PORTAADDR12 +address_a[12] => ram_block1a53.PORTAADDR12 +address_a[12] => ram_block1a54.PORTAADDR12 +address_a[12] => ram_block1a55.PORTAADDR12 +address_a[12] => ram_block1a56.PORTAADDR12 +address_a[12] => ram_block1a57.PORTAADDR12 +address_a[12] => ram_block1a58.PORTAADDR12 +address_a[12] => ram_block1a59.PORTAADDR12 +address_a[12] => ram_block1a60.PORTAADDR12 +address_a[12] => ram_block1a61.PORTAADDR12 +address_a[12] => ram_block1a62.PORTAADDR12 +address_a[12] => ram_block1a63.PORTAADDR12 +address_a[12] => ram_block1a64.PORTAADDR12 +address_a[12] => ram_block1a65.PORTAADDR12 +address_a[12] => ram_block1a66.PORTAADDR12 +address_a[12] => ram_block1a67.PORTAADDR12 +address_a[12] => ram_block1a68.PORTAADDR12 +address_a[12] => ram_block1a69.PORTAADDR12 +address_a[12] => ram_block1a70.PORTAADDR12 +address_a[12] => ram_block1a71.PORTAADDR12 +address_a[12] => ram_block1a72.PORTAADDR12 +address_a[12] => ram_block1a73.PORTAADDR12 +address_a[12] => ram_block1a74.PORTAADDR12 +address_a[12] => ram_block1a75.PORTAADDR12 +address_a[12] => ram_block1a76.PORTAADDR12 +address_a[12] => ram_block1a77.PORTAADDR12 +address_a[12] => ram_block1a78.PORTAADDR12 +address_a[12] => ram_block1a79.PORTAADDR12 +address_a[12] => ram_block1a80.PORTAADDR12 +address_a[12] => ram_block1a81.PORTAADDR12 +address_a[12] => ram_block1a82.PORTAADDR12 +address_a[12] => ram_block1a83.PORTAADDR12 +address_a[12] => ram_block1a84.PORTAADDR12 +address_a[12] => ram_block1a85.PORTAADDR12 +address_a[12] => ram_block1a86.PORTAADDR12 +address_a[12] => ram_block1a87.PORTAADDR12 +address_a[12] => ram_block1a88.PORTAADDR12 +address_a[12] => ram_block1a89.PORTAADDR12 +address_a[12] => ram_block1a90.PORTAADDR12 +address_a[12] => ram_block1a91.PORTAADDR12 +address_a[12] => ram_block1a92.PORTAADDR12 +address_a[12] => ram_block1a93.PORTAADDR12 +address_a[12] => ram_block1a94.PORTAADDR12 +address_a[12] => ram_block1a95.PORTAADDR12 +address_a[12] => ram_block1a96.PORTAADDR12 +address_a[12] => ram_block1a97.PORTAADDR12 +address_a[12] => ram_block1a98.PORTAADDR12 +address_a[12] => ram_block1a99.PORTAADDR12 +address_a[12] => ram_block1a100.PORTAADDR12 +address_a[12] => ram_block1a101.PORTAADDR12 +address_a[12] => ram_block1a102.PORTAADDR12 +address_a[12] => ram_block1a103.PORTAADDR12 +address_a[12] => ram_block1a104.PORTAADDR12 +address_a[12] => ram_block1a105.PORTAADDR12 +address_a[12] => ram_block1a106.PORTAADDR12 +address_a[12] => ram_block1a107.PORTAADDR12 +address_a[12] => ram_block1a108.PORTAADDR12 +address_a[12] => ram_block1a109.PORTAADDR12 +address_a[12] => ram_block1a110.PORTAADDR12 +address_a[12] => ram_block1a111.PORTAADDR12 +address_a[12] => ram_block1a112.PORTAADDR12 +address_a[12] => ram_block1a113.PORTAADDR12 +address_a[12] => ram_block1a114.PORTAADDR12 +address_a[12] => ram_block1a115.PORTAADDR12 +address_a[12] => ram_block1a116.PORTAADDR12 +address_a[12] => ram_block1a117.PORTAADDR12 +address_a[12] => ram_block1a118.PORTAADDR12 +address_a[12] => ram_block1a119.PORTAADDR12 +address_a[12] => ram_block1a120.PORTAADDR12 +address_a[12] => ram_block1a121.PORTAADDR12 +address_a[12] => ram_block1a122.PORTAADDR12 +address_a[12] => ram_block1a123.PORTAADDR12 +address_a[12] => ram_block1a124.PORTAADDR12 +address_a[12] => ram_block1a125.PORTAADDR12 +address_a[12] => ram_block1a126.PORTAADDR12 +address_a[12] => ram_block1a127.PORTAADDR12 +address_a[12] => ram_block1a128.PORTAADDR12 +address_a[12] => ram_block1a129.PORTAADDR12 +address_a[12] => ram_block1a130.PORTAADDR12 +address_a[12] => ram_block1a131.PORTAADDR12 +address_a[12] => ram_block1a132.PORTAADDR12 +address_a[12] => ram_block1a133.PORTAADDR12 +address_a[12] => ram_block1a134.PORTAADDR12 +address_a[12] => ram_block1a135.PORTAADDR12 +address_a[12] => ram_block1a136.PORTAADDR12 +address_a[12] => ram_block1a137.PORTAADDR12 +address_a[12] => ram_block1a138.PORTAADDR12 +address_a[12] => ram_block1a139.PORTAADDR12 +address_a[12] => ram_block1a140.PORTAADDR12 +address_a[12] => ram_block1a141.PORTAADDR12 +address_a[12] => ram_block1a142.PORTAADDR12 +address_a[12] => ram_block1a143.PORTAADDR12 +address_a[12] => ram_block1a144.PORTAADDR12 +address_a[12] => ram_block1a145.PORTAADDR12 +address_a[12] => ram_block1a146.PORTAADDR12 +address_a[12] => ram_block1a147.PORTAADDR12 +address_a[12] => ram_block1a148.PORTAADDR12 +address_a[12] => ram_block1a149.PORTAADDR12 +address_a[12] => ram_block1a150.PORTAADDR12 +address_a[12] => ram_block1a151.PORTAADDR12 +address_a[12] => ram_block1a152.PORTAADDR12 +address_a[12] => ram_block1a153.PORTAADDR12 +address_a[12] => ram_block1a154.PORTAADDR12 +address_a[12] => ram_block1a155.PORTAADDR12 +address_a[12] => ram_block1a156.PORTAADDR12 +address_a[12] => ram_block1a157.PORTAADDR12 +address_a[12] => ram_block1a158.PORTAADDR12 +address_a[12] => ram_block1a159.PORTAADDR12 +address_a[12] => ram_block1a160.PORTAADDR12 +address_a[12] => ram_block1a161.PORTAADDR12 +address_a[12] => ram_block1a162.PORTAADDR12 +address_a[12] => ram_block1a163.PORTAADDR12 +address_a[12] => ram_block1a164.PORTAADDR12 +address_a[12] => ram_block1a165.PORTAADDR12 +address_a[12] => ram_block1a166.PORTAADDR12 +address_a[12] => ram_block1a167.PORTAADDR12 +address_a[12] => ram_block1a168.PORTAADDR12 +address_a[12] => ram_block1a169.PORTAADDR12 +address_a[12] => ram_block1a170.PORTAADDR12 +address_a[12] => ram_block1a171.PORTAADDR12 +address_a[12] => ram_block1a172.PORTAADDR12 +address_a[12] => ram_block1a173.PORTAADDR12 +address_a[12] => ram_block1a174.PORTAADDR12 +address_a[12] => ram_block1a175.PORTAADDR12 +address_a[12] => ram_block1a176.PORTAADDR12 +address_a[12] => ram_block1a177.PORTAADDR12 +address_a[12] => ram_block1a178.PORTAADDR12 +address_a[12] => ram_block1a179.PORTAADDR12 +address_a[12] => ram_block1a180.PORTAADDR12 +address_a[12] => ram_block1a181.PORTAADDR12 +address_a[12] => ram_block1a182.PORTAADDR12 +address_a[12] => ram_block1a183.PORTAADDR12 +address_a[12] => ram_block1a184.PORTAADDR12 +address_a[12] => ram_block1a185.PORTAADDR12 +address_a[12] => ram_block1a186.PORTAADDR12 +address_a[12] => ram_block1a187.PORTAADDR12 +address_a[12] => ram_block1a188.PORTAADDR12 +address_a[12] => ram_block1a189.PORTAADDR12 +address_a[12] => ram_block1a190.PORTAADDR12 +address_a[12] => ram_block1a191.PORTAADDR12 +address_a[13] => address_reg_a[0].DATAIN +address_a[13] => decode_qsa:decode3.data[0] +address_a[14] => address_reg_a[1].DATAIN +address_a[14] => decode_qsa:decode3.data[1] +address_a[15] => address_reg_a[2].DATAIN +address_a[15] => decode_qsa:decode3.data[2] +byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a32.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a33.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a34.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a35.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a36.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a37.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a38.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a39.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a64.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a65.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a66.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a67.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a68.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a69.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a70.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a71.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a96.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a97.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a98.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a99.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a100.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a101.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a102.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a103.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a128.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a129.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a130.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a131.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a132.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a133.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a134.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a135.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a160.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a161.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a162.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a163.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a164.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a165.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a166.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a167.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a192.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a193.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a194.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a195.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a196.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a197.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a198.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a199.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a40.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a41.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a42.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a43.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a44.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a45.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a46.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a47.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a72.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a73.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a74.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a75.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a76.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a77.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a78.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a79.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a104.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a105.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a106.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a107.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a108.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a109.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a110.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a111.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a136.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a137.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a138.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a139.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a140.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a141.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a142.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a143.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a168.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a169.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a170.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a171.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a172.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a173.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a174.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a175.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a200.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a201.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a202.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a203.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a204.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a205.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a206.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a207.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a48.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a49.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a50.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a51.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a52.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a53.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a54.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a55.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a80.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a81.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a82.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a83.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a84.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a85.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a86.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a87.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a112.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a113.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a114.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a115.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a116.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a117.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a118.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a119.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a144.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a145.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a146.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a147.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a148.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a149.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a150.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a151.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a176.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a177.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a178.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a179.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a180.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a181.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a182.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a183.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a208.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a209.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a210.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a211.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a212.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a213.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a214.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a215.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a56.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a57.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a58.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a59.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a60.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a61.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a62.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a63.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a88.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a89.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a90.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a91.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a92.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a93.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a94.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a95.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a120.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a121.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a122.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a123.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a124.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a125.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a126.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a127.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a152.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a153.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a154.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a155.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a156.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a157.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a158.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a159.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a184.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a185.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a186.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a187.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a188.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a189.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a190.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a191.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a216.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a217.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a218.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a219.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a220.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a221.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a222.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a223.PORTABYTEENAMASKS +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +clock0 => ram_block1a32.CLK0 +clock0 => ram_block1a33.CLK0 +clock0 => ram_block1a34.CLK0 +clock0 => ram_block1a35.CLK0 +clock0 => ram_block1a36.CLK0 +clock0 => ram_block1a37.CLK0 +clock0 => ram_block1a38.CLK0 +clock0 => ram_block1a39.CLK0 +clock0 => ram_block1a40.CLK0 +clock0 => ram_block1a41.CLK0 +clock0 => ram_block1a42.CLK0 +clock0 => ram_block1a43.CLK0 +clock0 => ram_block1a44.CLK0 +clock0 => ram_block1a45.CLK0 +clock0 => ram_block1a46.CLK0 +clock0 => ram_block1a47.CLK0 +clock0 => ram_block1a48.CLK0 +clock0 => ram_block1a49.CLK0 +clock0 => ram_block1a50.CLK0 +clock0 => ram_block1a51.CLK0 +clock0 => ram_block1a52.CLK0 +clock0 => ram_block1a53.CLK0 +clock0 => ram_block1a54.CLK0 +clock0 => ram_block1a55.CLK0 +clock0 => ram_block1a56.CLK0 +clock0 => ram_block1a57.CLK0 +clock0 => ram_block1a58.CLK0 +clock0 => ram_block1a59.CLK0 +clock0 => ram_block1a60.CLK0 +clock0 => ram_block1a61.CLK0 +clock0 => ram_block1a62.CLK0 +clock0 => ram_block1a63.CLK0 +clock0 => ram_block1a64.CLK0 +clock0 => ram_block1a65.CLK0 +clock0 => ram_block1a66.CLK0 +clock0 => ram_block1a67.CLK0 +clock0 => ram_block1a68.CLK0 +clock0 => ram_block1a69.CLK0 +clock0 => ram_block1a70.CLK0 +clock0 => ram_block1a71.CLK0 +clock0 => ram_block1a72.CLK0 +clock0 => ram_block1a73.CLK0 +clock0 => ram_block1a74.CLK0 +clock0 => ram_block1a75.CLK0 +clock0 => ram_block1a76.CLK0 +clock0 => ram_block1a77.CLK0 +clock0 => ram_block1a78.CLK0 +clock0 => ram_block1a79.CLK0 +clock0 => ram_block1a80.CLK0 +clock0 => ram_block1a81.CLK0 +clock0 => ram_block1a82.CLK0 +clock0 => ram_block1a83.CLK0 +clock0 => ram_block1a84.CLK0 +clock0 => ram_block1a85.CLK0 +clock0 => ram_block1a86.CLK0 +clock0 => ram_block1a87.CLK0 +clock0 => ram_block1a88.CLK0 +clock0 => ram_block1a89.CLK0 +clock0 => ram_block1a90.CLK0 +clock0 => ram_block1a91.CLK0 +clock0 => ram_block1a92.CLK0 +clock0 => ram_block1a93.CLK0 +clock0 => ram_block1a94.CLK0 +clock0 => ram_block1a95.CLK0 +clock0 => ram_block1a96.CLK0 +clock0 => ram_block1a97.CLK0 +clock0 => ram_block1a98.CLK0 +clock0 => ram_block1a99.CLK0 +clock0 => ram_block1a100.CLK0 +clock0 => ram_block1a101.CLK0 +clock0 => ram_block1a102.CLK0 +clock0 => ram_block1a103.CLK0 +clock0 => ram_block1a104.CLK0 +clock0 => ram_block1a105.CLK0 +clock0 => ram_block1a106.CLK0 +clock0 => ram_block1a107.CLK0 +clock0 => ram_block1a108.CLK0 +clock0 => ram_block1a109.CLK0 +clock0 => ram_block1a110.CLK0 +clock0 => ram_block1a111.CLK0 +clock0 => ram_block1a112.CLK0 +clock0 => ram_block1a113.CLK0 +clock0 => ram_block1a114.CLK0 +clock0 => ram_block1a115.CLK0 +clock0 => ram_block1a116.CLK0 +clock0 => ram_block1a117.CLK0 +clock0 => ram_block1a118.CLK0 +clock0 => ram_block1a119.CLK0 +clock0 => ram_block1a120.CLK0 +clock0 => ram_block1a121.CLK0 +clock0 => ram_block1a122.CLK0 +clock0 => ram_block1a123.CLK0 +clock0 => ram_block1a124.CLK0 +clock0 => ram_block1a125.CLK0 +clock0 => ram_block1a126.CLK0 +clock0 => ram_block1a127.CLK0 +clock0 => ram_block1a128.CLK0 +clock0 => ram_block1a129.CLK0 +clock0 => ram_block1a130.CLK0 +clock0 => ram_block1a131.CLK0 +clock0 => ram_block1a132.CLK0 +clock0 => ram_block1a133.CLK0 +clock0 => ram_block1a134.CLK0 +clock0 => ram_block1a135.CLK0 +clock0 => ram_block1a136.CLK0 +clock0 => ram_block1a137.CLK0 +clock0 => ram_block1a138.CLK0 +clock0 => ram_block1a139.CLK0 +clock0 => ram_block1a140.CLK0 +clock0 => ram_block1a141.CLK0 +clock0 => ram_block1a142.CLK0 +clock0 => ram_block1a143.CLK0 +clock0 => ram_block1a144.CLK0 +clock0 => ram_block1a145.CLK0 +clock0 => ram_block1a146.CLK0 +clock0 => ram_block1a147.CLK0 +clock0 => ram_block1a148.CLK0 +clock0 => ram_block1a149.CLK0 +clock0 => ram_block1a150.CLK0 +clock0 => ram_block1a151.CLK0 +clock0 => ram_block1a152.CLK0 +clock0 => ram_block1a153.CLK0 +clock0 => ram_block1a154.CLK0 +clock0 => ram_block1a155.CLK0 +clock0 => ram_block1a156.CLK0 +clock0 => ram_block1a157.CLK0 +clock0 => ram_block1a158.CLK0 +clock0 => ram_block1a159.CLK0 +clock0 => ram_block1a160.CLK0 +clock0 => ram_block1a161.CLK0 +clock0 => ram_block1a162.CLK0 +clock0 => ram_block1a163.CLK0 +clock0 => ram_block1a164.CLK0 +clock0 => ram_block1a165.CLK0 +clock0 => ram_block1a166.CLK0 +clock0 => ram_block1a167.CLK0 +clock0 => ram_block1a168.CLK0 +clock0 => ram_block1a169.CLK0 +clock0 => ram_block1a170.CLK0 +clock0 => ram_block1a171.CLK0 +clock0 => ram_block1a172.CLK0 +clock0 => ram_block1a173.CLK0 +clock0 => ram_block1a174.CLK0 +clock0 => ram_block1a175.CLK0 +clock0 => ram_block1a176.CLK0 +clock0 => ram_block1a177.CLK0 +clock0 => ram_block1a178.CLK0 +clock0 => ram_block1a179.CLK0 +clock0 => ram_block1a180.CLK0 +clock0 => ram_block1a181.CLK0 +clock0 => ram_block1a182.CLK0 +clock0 => ram_block1a183.CLK0 +clock0 => ram_block1a184.CLK0 +clock0 => ram_block1a185.CLK0 +clock0 => ram_block1a186.CLK0 +clock0 => ram_block1a187.CLK0 +clock0 => ram_block1a188.CLK0 +clock0 => ram_block1a189.CLK0 +clock0 => ram_block1a190.CLK0 +clock0 => ram_block1a191.CLK0 +clock0 => ram_block1a192.CLK0 +clock0 => ram_block1a193.CLK0 +clock0 => ram_block1a194.CLK0 +clock0 => ram_block1a195.CLK0 +clock0 => ram_block1a196.CLK0 +clock0 => ram_block1a197.CLK0 +clock0 => ram_block1a198.CLK0 +clock0 => ram_block1a199.CLK0 +clock0 => ram_block1a200.CLK0 +clock0 => ram_block1a201.CLK0 +clock0 => ram_block1a202.CLK0 +clock0 => ram_block1a203.CLK0 +clock0 => ram_block1a204.CLK0 +clock0 => ram_block1a205.CLK0 +clock0 => ram_block1a206.CLK0 +clock0 => ram_block1a207.CLK0 +clock0 => ram_block1a208.CLK0 +clock0 => ram_block1a209.CLK0 +clock0 => ram_block1a210.CLK0 +clock0 => ram_block1a211.CLK0 +clock0 => ram_block1a212.CLK0 +clock0 => ram_block1a213.CLK0 +clock0 => ram_block1a214.CLK0 +clock0 => ram_block1a215.CLK0 +clock0 => ram_block1a216.CLK0 +clock0 => ram_block1a217.CLK0 +clock0 => ram_block1a218.CLK0 +clock0 => ram_block1a219.CLK0 +clock0 => ram_block1a220.CLK0 +clock0 => ram_block1a221.CLK0 +clock0 => ram_block1a222.CLK0 +clock0 => ram_block1a223.CLK0 +clock0 => address_reg_a[2].CLK +clock0 => address_reg_a[1].CLK +clock0 => address_reg_a[0].CLK +clocken0 => ram_block1a0.ENA0 +clocken0 => ram_block1a1.ENA0 +clocken0 => ram_block1a2.ENA0 +clocken0 => ram_block1a3.ENA0 +clocken0 => ram_block1a4.ENA0 +clocken0 => ram_block1a5.ENA0 +clocken0 => ram_block1a6.ENA0 +clocken0 => ram_block1a7.ENA0 +clocken0 => ram_block1a8.ENA0 +clocken0 => ram_block1a9.ENA0 +clocken0 => ram_block1a10.ENA0 +clocken0 => ram_block1a11.ENA0 +clocken0 => ram_block1a12.ENA0 +clocken0 => ram_block1a13.ENA0 +clocken0 => ram_block1a14.ENA0 +clocken0 => ram_block1a15.ENA0 +clocken0 => ram_block1a16.ENA0 +clocken0 => ram_block1a17.ENA0 +clocken0 => ram_block1a18.ENA0 +clocken0 => ram_block1a19.ENA0 +clocken0 => ram_block1a20.ENA0 +clocken0 => ram_block1a21.ENA0 +clocken0 => ram_block1a22.ENA0 +clocken0 => ram_block1a23.ENA0 +clocken0 => ram_block1a24.ENA0 +clocken0 => ram_block1a25.ENA0 +clocken0 => ram_block1a26.ENA0 +clocken0 => ram_block1a27.ENA0 +clocken0 => ram_block1a28.ENA0 +clocken0 => ram_block1a29.ENA0 +clocken0 => ram_block1a30.ENA0 +clocken0 => ram_block1a31.ENA0 +clocken0 => ram_block1a32.ENA0 +clocken0 => ram_block1a33.ENA0 +clocken0 => ram_block1a34.ENA0 +clocken0 => ram_block1a35.ENA0 +clocken0 => ram_block1a36.ENA0 +clocken0 => ram_block1a37.ENA0 +clocken0 => ram_block1a38.ENA0 +clocken0 => ram_block1a39.ENA0 +clocken0 => ram_block1a40.ENA0 +clocken0 => ram_block1a41.ENA0 +clocken0 => ram_block1a42.ENA0 +clocken0 => ram_block1a43.ENA0 +clocken0 => ram_block1a44.ENA0 +clocken0 => ram_block1a45.ENA0 +clocken0 => ram_block1a46.ENA0 +clocken0 => ram_block1a47.ENA0 +clocken0 => ram_block1a48.ENA0 +clocken0 => ram_block1a49.ENA0 +clocken0 => ram_block1a50.ENA0 +clocken0 => ram_block1a51.ENA0 +clocken0 => ram_block1a52.ENA0 +clocken0 => ram_block1a53.ENA0 +clocken0 => ram_block1a54.ENA0 +clocken0 => ram_block1a55.ENA0 +clocken0 => ram_block1a56.ENA0 +clocken0 => ram_block1a57.ENA0 +clocken0 => ram_block1a58.ENA0 +clocken0 => ram_block1a59.ENA0 +clocken0 => ram_block1a60.ENA0 +clocken0 => ram_block1a61.ENA0 +clocken0 => ram_block1a62.ENA0 +clocken0 => ram_block1a63.ENA0 +clocken0 => ram_block1a64.ENA0 +clocken0 => ram_block1a65.ENA0 +clocken0 => ram_block1a66.ENA0 +clocken0 => ram_block1a67.ENA0 +clocken0 => ram_block1a68.ENA0 +clocken0 => ram_block1a69.ENA0 +clocken0 => ram_block1a70.ENA0 +clocken0 => ram_block1a71.ENA0 +clocken0 => ram_block1a72.ENA0 +clocken0 => ram_block1a73.ENA0 +clocken0 => ram_block1a74.ENA0 +clocken0 => ram_block1a75.ENA0 +clocken0 => ram_block1a76.ENA0 +clocken0 => ram_block1a77.ENA0 +clocken0 => ram_block1a78.ENA0 +clocken0 => ram_block1a79.ENA0 +clocken0 => ram_block1a80.ENA0 +clocken0 => ram_block1a81.ENA0 +clocken0 => ram_block1a82.ENA0 +clocken0 => ram_block1a83.ENA0 +clocken0 => ram_block1a84.ENA0 +clocken0 => ram_block1a85.ENA0 +clocken0 => ram_block1a86.ENA0 +clocken0 => ram_block1a87.ENA0 +clocken0 => ram_block1a88.ENA0 +clocken0 => ram_block1a89.ENA0 +clocken0 => ram_block1a90.ENA0 +clocken0 => ram_block1a91.ENA0 +clocken0 => ram_block1a92.ENA0 +clocken0 => ram_block1a93.ENA0 +clocken0 => ram_block1a94.ENA0 +clocken0 => ram_block1a95.ENA0 +clocken0 => ram_block1a96.ENA0 +clocken0 => ram_block1a97.ENA0 +clocken0 => ram_block1a98.ENA0 +clocken0 => ram_block1a99.ENA0 +clocken0 => ram_block1a100.ENA0 +clocken0 => ram_block1a101.ENA0 +clocken0 => ram_block1a102.ENA0 +clocken0 => ram_block1a103.ENA0 +clocken0 => ram_block1a104.ENA0 +clocken0 => ram_block1a105.ENA0 +clocken0 => ram_block1a106.ENA0 +clocken0 => ram_block1a107.ENA0 +clocken0 => ram_block1a108.ENA0 +clocken0 => ram_block1a109.ENA0 +clocken0 => ram_block1a110.ENA0 +clocken0 => ram_block1a111.ENA0 +clocken0 => ram_block1a112.ENA0 +clocken0 => ram_block1a113.ENA0 +clocken0 => ram_block1a114.ENA0 +clocken0 => ram_block1a115.ENA0 +clocken0 => ram_block1a116.ENA0 +clocken0 => ram_block1a117.ENA0 +clocken0 => ram_block1a118.ENA0 +clocken0 => ram_block1a119.ENA0 +clocken0 => ram_block1a120.ENA0 +clocken0 => ram_block1a121.ENA0 +clocken0 => ram_block1a122.ENA0 +clocken0 => ram_block1a123.ENA0 +clocken0 => ram_block1a124.ENA0 +clocken0 => ram_block1a125.ENA0 +clocken0 => ram_block1a126.ENA0 +clocken0 => ram_block1a127.ENA0 +clocken0 => ram_block1a128.ENA0 +clocken0 => ram_block1a129.ENA0 +clocken0 => ram_block1a130.ENA0 +clocken0 => ram_block1a131.ENA0 +clocken0 => ram_block1a132.ENA0 +clocken0 => ram_block1a133.ENA0 +clocken0 => ram_block1a134.ENA0 +clocken0 => ram_block1a135.ENA0 +clocken0 => ram_block1a136.ENA0 +clocken0 => ram_block1a137.ENA0 +clocken0 => ram_block1a138.ENA0 +clocken0 => ram_block1a139.ENA0 +clocken0 => ram_block1a140.ENA0 +clocken0 => ram_block1a141.ENA0 +clocken0 => ram_block1a142.ENA0 +clocken0 => ram_block1a143.ENA0 +clocken0 => ram_block1a144.ENA0 +clocken0 => ram_block1a145.ENA0 +clocken0 => ram_block1a146.ENA0 +clocken0 => ram_block1a147.ENA0 +clocken0 => ram_block1a148.ENA0 +clocken0 => ram_block1a149.ENA0 +clocken0 => ram_block1a150.ENA0 +clocken0 => ram_block1a151.ENA0 +clocken0 => ram_block1a152.ENA0 +clocken0 => ram_block1a153.ENA0 +clocken0 => ram_block1a154.ENA0 +clocken0 => ram_block1a155.ENA0 +clocken0 => ram_block1a156.ENA0 +clocken0 => ram_block1a157.ENA0 +clocken0 => ram_block1a158.ENA0 +clocken0 => ram_block1a159.ENA0 +clocken0 => ram_block1a160.ENA0 +clocken0 => ram_block1a161.ENA0 +clocken0 => ram_block1a162.ENA0 +clocken0 => ram_block1a163.ENA0 +clocken0 => ram_block1a164.ENA0 +clocken0 => ram_block1a165.ENA0 +clocken0 => ram_block1a166.ENA0 +clocken0 => ram_block1a167.ENA0 +clocken0 => ram_block1a168.ENA0 +clocken0 => ram_block1a169.ENA0 +clocken0 => ram_block1a170.ENA0 +clocken0 => ram_block1a171.ENA0 +clocken0 => ram_block1a172.ENA0 +clocken0 => ram_block1a173.ENA0 +clocken0 => ram_block1a174.ENA0 +clocken0 => ram_block1a175.ENA0 +clocken0 => ram_block1a176.ENA0 +clocken0 => ram_block1a177.ENA0 +clocken0 => ram_block1a178.ENA0 +clocken0 => ram_block1a179.ENA0 +clocken0 => ram_block1a180.ENA0 +clocken0 => ram_block1a181.ENA0 +clocken0 => ram_block1a182.ENA0 +clocken0 => ram_block1a183.ENA0 +clocken0 => ram_block1a184.ENA0 +clocken0 => ram_block1a185.ENA0 +clocken0 => ram_block1a186.ENA0 +clocken0 => ram_block1a187.ENA0 +clocken0 => ram_block1a188.ENA0 +clocken0 => ram_block1a189.ENA0 +clocken0 => ram_block1a190.ENA0 +clocken0 => ram_block1a191.ENA0 +clocken0 => ram_block1a192.ENA0 +clocken0 => ram_block1a193.ENA0 +clocken0 => ram_block1a194.ENA0 +clocken0 => ram_block1a195.ENA0 +clocken0 => ram_block1a196.ENA0 +clocken0 => ram_block1a197.ENA0 +clocken0 => ram_block1a198.ENA0 +clocken0 => ram_block1a199.ENA0 +clocken0 => ram_block1a200.ENA0 +clocken0 => ram_block1a201.ENA0 +clocken0 => ram_block1a202.ENA0 +clocken0 => ram_block1a203.ENA0 +clocken0 => ram_block1a204.ENA0 +clocken0 => ram_block1a205.ENA0 +clocken0 => ram_block1a206.ENA0 +clocken0 => ram_block1a207.ENA0 +clocken0 => ram_block1a208.ENA0 +clocken0 => ram_block1a209.ENA0 +clocken0 => ram_block1a210.ENA0 +clocken0 => ram_block1a211.ENA0 +clocken0 => ram_block1a212.ENA0 +clocken0 => ram_block1a213.ENA0 +clocken0 => ram_block1a214.ENA0 +clocken0 => ram_block1a215.ENA0 +clocken0 => ram_block1a216.ENA0 +clocken0 => ram_block1a217.ENA0 +clocken0 => ram_block1a218.ENA0 +clocken0 => ram_block1a219.ENA0 +clocken0 => ram_block1a220.ENA0 +clocken0 => ram_block1a221.ENA0 +clocken0 => ram_block1a222.ENA0 +clocken0 => ram_block1a223.ENA0 +clocken0 => address_reg_a[2].ENA +clocken0 => address_reg_a[1].ENA +clocken0 => address_reg_a[0].ENA +data_a[0] => ram_block1a0.PORTADATAIN +data_a[0] => ram_block1a32.PORTADATAIN +data_a[0] => ram_block1a64.PORTADATAIN +data_a[0] => ram_block1a96.PORTADATAIN +data_a[0] => ram_block1a128.PORTADATAIN +data_a[0] => ram_block1a160.PORTADATAIN +data_a[0] => ram_block1a192.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[1] => ram_block1a33.PORTADATAIN +data_a[1] => ram_block1a65.PORTADATAIN +data_a[1] => ram_block1a97.PORTADATAIN +data_a[1] => ram_block1a129.PORTADATAIN +data_a[1] => ram_block1a161.PORTADATAIN +data_a[1] => ram_block1a193.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[2] => ram_block1a34.PORTADATAIN +data_a[2] => ram_block1a66.PORTADATAIN +data_a[2] => ram_block1a98.PORTADATAIN +data_a[2] => ram_block1a130.PORTADATAIN +data_a[2] => ram_block1a162.PORTADATAIN +data_a[2] => ram_block1a194.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[3] => ram_block1a35.PORTADATAIN +data_a[3] => ram_block1a67.PORTADATAIN +data_a[3] => ram_block1a99.PORTADATAIN +data_a[3] => ram_block1a131.PORTADATAIN +data_a[3] => ram_block1a163.PORTADATAIN +data_a[3] => ram_block1a195.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[4] => ram_block1a36.PORTADATAIN +data_a[4] => ram_block1a68.PORTADATAIN +data_a[4] => ram_block1a100.PORTADATAIN +data_a[4] => ram_block1a132.PORTADATAIN +data_a[4] => ram_block1a164.PORTADATAIN +data_a[4] => ram_block1a196.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[5] => ram_block1a37.PORTADATAIN +data_a[5] => ram_block1a69.PORTADATAIN +data_a[5] => ram_block1a101.PORTADATAIN +data_a[5] => ram_block1a133.PORTADATAIN +data_a[5] => ram_block1a165.PORTADATAIN +data_a[5] => ram_block1a197.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[6] => ram_block1a38.PORTADATAIN +data_a[6] => ram_block1a70.PORTADATAIN +data_a[6] => ram_block1a102.PORTADATAIN +data_a[6] => ram_block1a134.PORTADATAIN +data_a[6] => ram_block1a166.PORTADATAIN +data_a[6] => ram_block1a198.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[7] => ram_block1a39.PORTADATAIN +data_a[7] => ram_block1a71.PORTADATAIN +data_a[7] => ram_block1a103.PORTADATAIN +data_a[7] => ram_block1a135.PORTADATAIN +data_a[7] => ram_block1a167.PORTADATAIN +data_a[7] => ram_block1a199.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[8] => ram_block1a40.PORTADATAIN +data_a[8] => ram_block1a72.PORTADATAIN +data_a[8] => ram_block1a104.PORTADATAIN +data_a[8] => ram_block1a136.PORTADATAIN +data_a[8] => ram_block1a168.PORTADATAIN +data_a[8] => ram_block1a200.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[9] => ram_block1a41.PORTADATAIN +data_a[9] => ram_block1a73.PORTADATAIN +data_a[9] => ram_block1a105.PORTADATAIN +data_a[9] => ram_block1a137.PORTADATAIN +data_a[9] => ram_block1a169.PORTADATAIN +data_a[9] => ram_block1a201.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[10] => ram_block1a42.PORTADATAIN +data_a[10] => ram_block1a74.PORTADATAIN +data_a[10] => ram_block1a106.PORTADATAIN +data_a[10] => ram_block1a138.PORTADATAIN +data_a[10] => ram_block1a170.PORTADATAIN +data_a[10] => ram_block1a202.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[11] => ram_block1a43.PORTADATAIN +data_a[11] => ram_block1a75.PORTADATAIN +data_a[11] => ram_block1a107.PORTADATAIN +data_a[11] => ram_block1a139.PORTADATAIN +data_a[11] => ram_block1a171.PORTADATAIN +data_a[11] => ram_block1a203.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[12] => ram_block1a44.PORTADATAIN +data_a[12] => ram_block1a76.PORTADATAIN +data_a[12] => ram_block1a108.PORTADATAIN +data_a[12] => ram_block1a140.PORTADATAIN +data_a[12] => ram_block1a172.PORTADATAIN +data_a[12] => ram_block1a204.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[13] => ram_block1a45.PORTADATAIN +data_a[13] => ram_block1a77.PORTADATAIN +data_a[13] => ram_block1a109.PORTADATAIN +data_a[13] => ram_block1a141.PORTADATAIN +data_a[13] => ram_block1a173.PORTADATAIN +data_a[13] => ram_block1a205.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[14] => ram_block1a46.PORTADATAIN +data_a[14] => ram_block1a78.PORTADATAIN +data_a[14] => ram_block1a110.PORTADATAIN +data_a[14] => ram_block1a142.PORTADATAIN +data_a[14] => ram_block1a174.PORTADATAIN +data_a[14] => ram_block1a206.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[15] => ram_block1a47.PORTADATAIN +data_a[15] => ram_block1a79.PORTADATAIN +data_a[15] => ram_block1a111.PORTADATAIN +data_a[15] => ram_block1a143.PORTADATAIN +data_a[15] => ram_block1a175.PORTADATAIN +data_a[15] => ram_block1a207.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[16] => ram_block1a48.PORTADATAIN +data_a[16] => ram_block1a80.PORTADATAIN +data_a[16] => ram_block1a112.PORTADATAIN +data_a[16] => ram_block1a144.PORTADATAIN +data_a[16] => ram_block1a176.PORTADATAIN +data_a[16] => ram_block1a208.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[17] => ram_block1a49.PORTADATAIN +data_a[17] => ram_block1a81.PORTADATAIN +data_a[17] => ram_block1a113.PORTADATAIN +data_a[17] => ram_block1a145.PORTADATAIN +data_a[17] => ram_block1a177.PORTADATAIN +data_a[17] => ram_block1a209.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[18] => ram_block1a50.PORTADATAIN +data_a[18] => ram_block1a82.PORTADATAIN +data_a[18] => ram_block1a114.PORTADATAIN +data_a[18] => ram_block1a146.PORTADATAIN +data_a[18] => ram_block1a178.PORTADATAIN +data_a[18] => ram_block1a210.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[19] => ram_block1a51.PORTADATAIN +data_a[19] => ram_block1a83.PORTADATAIN +data_a[19] => ram_block1a115.PORTADATAIN +data_a[19] => ram_block1a147.PORTADATAIN +data_a[19] => ram_block1a179.PORTADATAIN +data_a[19] => ram_block1a211.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[20] => ram_block1a52.PORTADATAIN +data_a[20] => ram_block1a84.PORTADATAIN +data_a[20] => ram_block1a116.PORTADATAIN +data_a[20] => ram_block1a148.PORTADATAIN +data_a[20] => ram_block1a180.PORTADATAIN +data_a[20] => ram_block1a212.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[21] => ram_block1a53.PORTADATAIN +data_a[21] => ram_block1a85.PORTADATAIN +data_a[21] => ram_block1a117.PORTADATAIN +data_a[21] => ram_block1a149.PORTADATAIN +data_a[21] => ram_block1a181.PORTADATAIN +data_a[21] => ram_block1a213.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[22] => ram_block1a54.PORTADATAIN +data_a[22] => ram_block1a86.PORTADATAIN +data_a[22] => ram_block1a118.PORTADATAIN +data_a[22] => ram_block1a150.PORTADATAIN +data_a[22] => ram_block1a182.PORTADATAIN +data_a[22] => ram_block1a214.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[23] => ram_block1a55.PORTADATAIN +data_a[23] => ram_block1a87.PORTADATAIN +data_a[23] => ram_block1a119.PORTADATAIN +data_a[23] => ram_block1a151.PORTADATAIN +data_a[23] => ram_block1a183.PORTADATAIN +data_a[23] => ram_block1a215.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[24] => ram_block1a56.PORTADATAIN +data_a[24] => ram_block1a88.PORTADATAIN +data_a[24] => ram_block1a120.PORTADATAIN +data_a[24] => ram_block1a152.PORTADATAIN +data_a[24] => ram_block1a184.PORTADATAIN +data_a[24] => ram_block1a216.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[25] => ram_block1a57.PORTADATAIN +data_a[25] => ram_block1a89.PORTADATAIN +data_a[25] => ram_block1a121.PORTADATAIN +data_a[25] => ram_block1a153.PORTADATAIN +data_a[25] => ram_block1a185.PORTADATAIN +data_a[25] => ram_block1a217.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[26] => ram_block1a58.PORTADATAIN +data_a[26] => ram_block1a90.PORTADATAIN +data_a[26] => ram_block1a122.PORTADATAIN +data_a[26] => ram_block1a154.PORTADATAIN +data_a[26] => ram_block1a186.PORTADATAIN +data_a[26] => ram_block1a218.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[27] => ram_block1a59.PORTADATAIN +data_a[27] => ram_block1a91.PORTADATAIN +data_a[27] => ram_block1a123.PORTADATAIN +data_a[27] => ram_block1a155.PORTADATAIN +data_a[27] => ram_block1a187.PORTADATAIN +data_a[27] => ram_block1a219.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[28] => ram_block1a60.PORTADATAIN +data_a[28] => ram_block1a92.PORTADATAIN +data_a[28] => ram_block1a124.PORTADATAIN +data_a[28] => ram_block1a156.PORTADATAIN +data_a[28] => ram_block1a188.PORTADATAIN +data_a[28] => ram_block1a220.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[29] => ram_block1a61.PORTADATAIN +data_a[29] => ram_block1a93.PORTADATAIN +data_a[29] => ram_block1a125.PORTADATAIN +data_a[29] => ram_block1a157.PORTADATAIN +data_a[29] => ram_block1a189.PORTADATAIN +data_a[29] => ram_block1a221.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[30] => ram_block1a62.PORTADATAIN +data_a[30] => ram_block1a94.PORTADATAIN +data_a[30] => ram_block1a126.PORTADATAIN +data_a[30] => ram_block1a158.PORTADATAIN +data_a[30] => ram_block1a190.PORTADATAIN +data_a[30] => ram_block1a222.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +data_a[31] => ram_block1a63.PORTADATAIN +data_a[31] => ram_block1a95.PORTADATAIN +data_a[31] => ram_block1a127.PORTADATAIN +data_a[31] => ram_block1a159.PORTADATAIN +data_a[31] => ram_block1a191.PORTADATAIN +data_a[31] => ram_block1a223.PORTADATAIN +q_a[0] <= mux_nob:mux2.result[0] +q_a[1] <= mux_nob:mux2.result[1] +q_a[2] <= mux_nob:mux2.result[2] +q_a[3] <= mux_nob:mux2.result[3] +q_a[4] <= mux_nob:mux2.result[4] +q_a[5] <= mux_nob:mux2.result[5] +q_a[6] <= mux_nob:mux2.result[6] +q_a[7] <= mux_nob:mux2.result[7] +q_a[8] <= mux_nob:mux2.result[8] +q_a[9] <= mux_nob:mux2.result[9] +q_a[10] <= mux_nob:mux2.result[10] +q_a[11] <= mux_nob:mux2.result[11] +q_a[12] <= mux_nob:mux2.result[12] +q_a[13] <= mux_nob:mux2.result[13] +q_a[14] <= mux_nob:mux2.result[14] +q_a[15] <= mux_nob:mux2.result[15] +q_a[16] <= mux_nob:mux2.result[16] +q_a[17] <= mux_nob:mux2.result[17] +q_a[18] <= mux_nob:mux2.result[18] +q_a[19] <= mux_nob:mux2.result[19] +q_a[20] <= mux_nob:mux2.result[20] +q_a[21] <= mux_nob:mux2.result[21] +q_a[22] <= mux_nob:mux2.result[22] +q_a[23] <= mux_nob:mux2.result[23] +q_a[24] <= mux_nob:mux2.result[24] +q_a[25] <= mux_nob:mux2.result[25] +q_a[26] <= mux_nob:mux2.result[26] +q_a[27] <= mux_nob:mux2.result[27] +q_a[28] <= mux_nob:mux2.result[28] +q_a[29] <= mux_nob:mux2.result[29] +q_a[30] <= mux_nob:mux2.result[30] +q_a[31] <= mux_nob:mux2.result[31] +wren_a => decode_qsa:decode3.enable + + +|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 +data[0] => w_anode1849w[1].IN0 +data[0] => w_anode1866w[1].IN1 +data[0] => w_anode1876w[1].IN0 +data[0] => w_anode1886w[1].IN1 +data[0] => w_anode1896w[1].IN0 +data[0] => w_anode1906w[1].IN1 +data[0] => w_anode1916w[1].IN0 +data[0] => w_anode1926w[1].IN1 +data[1] => w_anode1849w[2].IN0 +data[1] => w_anode1866w[2].IN0 +data[1] => w_anode1876w[2].IN1 +data[1] => w_anode1886w[2].IN1 +data[1] => w_anode1896w[2].IN0 +data[1] => w_anode1906w[2].IN0 +data[1] => w_anode1916w[2].IN1 +data[1] => w_anode1926w[2].IN1 +data[2] => w_anode1849w[3].IN0 +data[2] => w_anode1866w[3].IN0 +data[2] => w_anode1876w[3].IN0 +data[2] => w_anode1886w[3].IN0 +data[2] => w_anode1896w[3].IN1 +data[2] => w_anode1906w[3].IN1 +data[2] => w_anode1916w[3].IN1 +data[2] => w_anode1926w[3].IN1 +enable => w_anode1849w[1].IN0 +enable => w_anode1866w[1].IN0 +enable => w_anode1876w[1].IN0 +enable => w_anode1886w[1].IN0 +enable => w_anode1896w[1].IN0 +enable => w_anode1906w[1].IN0 +enable => w_anode1916w[1].IN0 +enable => w_anode1926w[1].IN0 +eq[0] <= w_anode1849w[3].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= w_anode1866w[3].DB_MAX_OUTPUT_PORT_TYPE +eq[2] <= w_anode1876w[3].DB_MAX_OUTPUT_PORT_TYPE +eq[3] <= w_anode1886w[3].DB_MAX_OUTPUT_PORT_TYPE +eq[4] <= w_anode1896w[3].DB_MAX_OUTPUT_PORT_TYPE +eq[5] <= w_anode1906w[3].DB_MAX_OUTPUT_PORT_TYPE +eq[6] <= w_anode1916w[3].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 +data[0] => _.IN0 +data[0] => _.IN0 +data[1] => _.IN0 +data[1] => _.IN0 +data[2] => _.IN0 +data[2] => _.IN0 +data[3] => _.IN0 +data[3] => _.IN0 +data[4] => _.IN0 +data[4] => _.IN0 +data[5] => _.IN0 +data[5] => _.IN0 +data[6] => _.IN0 +data[6] => _.IN0 +data[7] => _.IN0 +data[7] => _.IN0 +data[8] => _.IN0 +data[8] => _.IN0 +data[9] => _.IN0 +data[9] => _.IN0 +data[10] => _.IN0 +data[10] => _.IN0 +data[11] => _.IN0 +data[11] => _.IN0 +data[12] => _.IN0 +data[12] => _.IN0 +data[13] => _.IN0 +data[13] => _.IN0 +data[14] => _.IN0 +data[14] => _.IN0 +data[15] => _.IN0 +data[15] => _.IN0 +data[16] => _.IN0 +data[16] => _.IN0 +data[17] => _.IN0 +data[17] => _.IN0 +data[18] => _.IN0 +data[18] => _.IN0 +data[19] => _.IN0 +data[19] => _.IN0 +data[20] => _.IN0 +data[20] => _.IN0 +data[21] => _.IN0 +data[21] => _.IN0 +data[22] => _.IN0 +data[22] => _.IN0 +data[23] => _.IN0 +data[23] => _.IN0 +data[24] => _.IN0 +data[24] => _.IN0 +data[25] => _.IN0 +data[25] => _.IN0 +data[26] => _.IN0 +data[26] => _.IN0 +data[27] => _.IN0 +data[27] => _.IN0 +data[28] => _.IN0 +data[28] => _.IN0 +data[29] => _.IN0 +data[29] => _.IN0 +data[30] => _.IN0 +data[30] => _.IN0 +data[31] => _.IN0 +data[31] => _.IN0 +data[32] => _.IN0 +data[33] => _.IN0 +data[34] => _.IN0 +data[35] => _.IN0 +data[36] => _.IN0 +data[37] => _.IN0 +data[38] => _.IN0 +data[39] => _.IN0 +data[40] => _.IN0 +data[41] => _.IN0 +data[42] => _.IN0 +data[43] => _.IN0 +data[44] => _.IN0 +data[45] => _.IN0 +data[46] => _.IN0 +data[47] => _.IN0 +data[48] => _.IN0 +data[49] => _.IN0 +data[50] => _.IN0 +data[51] => _.IN0 +data[52] => _.IN0 +data[53] => _.IN0 +data[54] => _.IN0 +data[55] => _.IN0 +data[56] => _.IN0 +data[57] => _.IN0 +data[58] => _.IN0 +data[59] => _.IN0 +data[60] => _.IN0 +data[61] => _.IN0 +data[62] => _.IN0 +data[63] => _.IN0 +data[64] => _.IN1 +data[64] => _.IN1 +data[65] => _.IN1 +data[65] => _.IN1 +data[66] => _.IN1 +data[66] => _.IN1 +data[67] => _.IN1 +data[67] => _.IN1 +data[68] => _.IN1 +data[68] => _.IN1 +data[69] => _.IN1 +data[69] => _.IN1 +data[70] => _.IN1 +data[70] => _.IN1 +data[71] => _.IN1 +data[71] => _.IN1 +data[72] => _.IN1 +data[72] => _.IN1 +data[73] => _.IN1 +data[73] => _.IN1 +data[74] => _.IN1 +data[74] => _.IN1 +data[75] => _.IN1 +data[75] => _.IN1 +data[76] => _.IN1 +data[76] => _.IN1 +data[77] => _.IN1 +data[77] => _.IN1 +data[78] => _.IN1 +data[78] => _.IN1 +data[79] => _.IN1 +data[79] => _.IN1 +data[80] => _.IN1 +data[80] => _.IN1 +data[81] => _.IN1 +data[81] => _.IN1 +data[82] => _.IN1 +data[82] => _.IN1 +data[83] => _.IN1 +data[83] => _.IN1 +data[84] => _.IN1 +data[84] => _.IN1 +data[85] => _.IN1 +data[85] => _.IN1 +data[86] => _.IN1 +data[86] => _.IN1 +data[87] => _.IN1 +data[87] => _.IN1 +data[88] => _.IN1 +data[88] => _.IN1 +data[89] => _.IN1 +data[89] => _.IN1 +data[90] => _.IN1 +data[90] => _.IN1 +data[91] => _.IN1 +data[91] => _.IN1 +data[92] => _.IN1 +data[92] => _.IN1 +data[93] => _.IN1 +data[93] => _.IN1 +data[94] => _.IN1 +data[94] => _.IN1 +data[95] => _.IN1 +data[95] => _.IN1 +data[96] => _.IN0 +data[97] => _.IN0 +data[98] => _.IN0 +data[99] => _.IN0 +data[100] => _.IN0 +data[101] => _.IN0 +data[102] => _.IN0 +data[103] => _.IN0 +data[104] => _.IN0 +data[105] => _.IN0 +data[106] => _.IN0 +data[107] => _.IN0 +data[108] => _.IN0 +data[109] => _.IN0 +data[110] => _.IN0 +data[111] => _.IN0 +data[112] => _.IN0 +data[113] => _.IN0 +data[114] => _.IN0 +data[115] => _.IN0 +data[116] => _.IN0 +data[117] => _.IN0 +data[118] => _.IN0 +data[119] => _.IN0 +data[120] => _.IN0 +data[121] => _.IN0 +data[122] => _.IN0 +data[123] => _.IN0 +data[124] => _.IN0 +data[125] => _.IN0 +data[126] => _.IN0 +data[127] => _.IN0 +data[128] => _.IN0 +data[128] => _.IN0 +data[129] => _.IN0 +data[129] => _.IN0 +data[130] => _.IN0 +data[130] => _.IN0 +data[131] => _.IN0 +data[131] => _.IN0 +data[132] => _.IN0 +data[132] => _.IN0 +data[133] => _.IN0 +data[133] => _.IN0 +data[134] => _.IN0 +data[134] => _.IN0 +data[135] => _.IN0 +data[135] => _.IN0 +data[136] => _.IN0 +data[136] => _.IN0 +data[137] => _.IN0 +data[137] => _.IN0 +data[138] => _.IN0 +data[138] => _.IN0 +data[139] => _.IN0 +data[139] => _.IN0 +data[140] => _.IN0 +data[140] => _.IN0 +data[141] => _.IN0 +data[141] => _.IN0 +data[142] => _.IN0 +data[142] => _.IN0 +data[143] => _.IN0 +data[143] => _.IN0 +data[144] => _.IN0 +data[144] => _.IN0 +data[145] => _.IN0 +data[145] => _.IN0 +data[146] => _.IN0 +data[146] => _.IN0 +data[147] => _.IN0 +data[147] => _.IN0 +data[148] => _.IN0 +data[148] => _.IN0 +data[149] => _.IN0 +data[149] => _.IN0 +data[150] => _.IN0 +data[150] => _.IN0 +data[151] => _.IN0 +data[151] => _.IN0 +data[152] => _.IN0 +data[152] => _.IN0 +data[153] => _.IN0 +data[153] => _.IN0 +data[154] => _.IN0 +data[154] => _.IN0 +data[155] => _.IN0 +data[155] => _.IN0 +data[156] => _.IN0 +data[156] => _.IN0 +data[157] => _.IN0 +data[157] => _.IN0 +data[158] => _.IN0 +data[158] => _.IN0 +data[159] => _.IN0 +data[159] => _.IN0 +data[160] => _.IN0 +data[161] => _.IN0 +data[162] => _.IN0 +data[163] => _.IN0 +data[164] => _.IN0 +data[165] => _.IN0 +data[166] => _.IN0 +data[167] => _.IN0 +data[168] => _.IN0 +data[169] => _.IN0 +data[170] => _.IN0 +data[171] => _.IN0 +data[172] => _.IN0 +data[173] => _.IN0 +data[174] => _.IN0 +data[175] => _.IN0 +data[176] => _.IN0 +data[177] => _.IN0 +data[178] => _.IN0 +data[179] => _.IN0 +data[180] => _.IN0 +data[181] => _.IN0 +data[182] => _.IN0 +data[183] => _.IN0 +data[184] => _.IN0 +data[185] => _.IN0 +data[186] => _.IN0 +data[187] => _.IN0 +data[188] => _.IN0 +data[189] => _.IN0 +data[190] => _.IN0 +data[191] => _.IN0 +data[192] => _.IN1 +data[192] => _.IN1 +data[193] => _.IN1 +data[193] => _.IN1 +data[194] => _.IN1 +data[194] => _.IN1 +data[195] => _.IN1 +data[195] => _.IN1 +data[196] => _.IN1 +data[196] => _.IN1 +data[197] => _.IN1 +data[197] => _.IN1 +data[198] => _.IN1 +data[198] => _.IN1 +data[199] => _.IN1 +data[199] => _.IN1 +data[200] => _.IN1 +data[200] => _.IN1 +data[201] => _.IN1 +data[201] => _.IN1 +data[202] => _.IN1 +data[202] => _.IN1 +data[203] => _.IN1 +data[203] => _.IN1 +data[204] => _.IN1 +data[204] => _.IN1 +data[205] => _.IN1 +data[205] => _.IN1 +data[206] => _.IN1 +data[206] => _.IN1 +data[207] => _.IN1 +data[207] => _.IN1 +data[208] => _.IN1 +data[208] => _.IN1 +data[209] => _.IN1 +data[209] => _.IN1 +data[210] => _.IN1 +data[210] => _.IN1 +data[211] => _.IN1 +data[211] => _.IN1 +data[212] => _.IN1 +data[212] => _.IN1 +data[213] => _.IN1 +data[213] => _.IN1 +data[214] => _.IN1 +data[214] => _.IN1 +data[215] => _.IN1 +data[215] => _.IN1 +data[216] => _.IN1 +data[216] => _.IN1 +data[217] => _.IN1 +data[217] => _.IN1 +data[218] => _.IN1 +data[218] => _.IN1 +data[219] => _.IN1 +data[219] => _.IN1 +data[220] => _.IN1 +data[220] => _.IN1 +data[221] => _.IN1 +data[221] => _.IN1 +data[222] => _.IN1 +data[222] => _.IN1 +data[223] => _.IN1 +data[223] => _.IN1 +result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE +result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE +result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE +result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE +result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE +result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE +result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE +result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE +result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE +result[16] <= result_node[16].DB_MAX_OUTPUT_PORT_TYPE +result[17] <= result_node[17].DB_MAX_OUTPUT_PORT_TYPE +result[18] <= result_node[18].DB_MAX_OUTPUT_PORT_TYPE +result[19] <= result_node[19].DB_MAX_OUTPUT_PORT_TYPE +result[20] <= result_node[20].DB_MAX_OUTPUT_PORT_TYPE +result[21] <= result_node[21].DB_MAX_OUTPUT_PORT_TYPE +result[22] <= result_node[22].DB_MAX_OUTPUT_PORT_TYPE +result[23] <= result_node[23].DB_MAX_OUTPUT_PORT_TYPE +result[24] <= result_node[24].DB_MAX_OUTPUT_PORT_TYPE +result[25] <= result_node[25].DB_MAX_OUTPUT_PORT_TYPE +result[26] <= result_node[26].DB_MAX_OUTPUT_PORT_TYPE +result[27] <= result_node[27].DB_MAX_OUTPUT_PORT_TYPE +result[28] <= result_node[28].DB_MAX_OUTPUT_PORT_TYPE +result[29] <= result_node[29].DB_MAX_OUTPUT_PORT_TYPE +result[30] <= result_node[30].DB_MAX_OUTPUT_PORT_TYPE +result[31] <= result_node[31].DB_MAX_OUTPUT_PORT_TYPE +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN1 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[0] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[1] => _.IN0 +sel[2] => result_node[31].IN0 +sel[2] => _.IN0 +sel[2] => result_node[30].IN0 +sel[2] => _.IN0 +sel[2] => result_node[29].IN0 +sel[2] => _.IN0 +sel[2] => result_node[28].IN0 +sel[2] => _.IN0 +sel[2] => result_node[27].IN0 +sel[2] => _.IN0 +sel[2] => result_node[26].IN0 +sel[2] => _.IN0 +sel[2] => result_node[25].IN0 +sel[2] => _.IN0 +sel[2] => result_node[24].IN0 +sel[2] => _.IN0 +sel[2] => result_node[23].IN0 +sel[2] => _.IN0 +sel[2] => result_node[22].IN0 +sel[2] => _.IN0 +sel[2] => result_node[21].IN0 +sel[2] => _.IN0 +sel[2] => result_node[20].IN0 +sel[2] => _.IN0 +sel[2] => result_node[19].IN0 +sel[2] => _.IN0 +sel[2] => result_node[18].IN0 +sel[2] => _.IN0 +sel[2] => result_node[17].IN0 +sel[2] => _.IN0 +sel[2] => result_node[16].IN0 +sel[2] => _.IN0 +sel[2] => result_node[15].IN0 +sel[2] => _.IN0 +sel[2] => result_node[14].IN0 +sel[2] => _.IN0 +sel[2] => result_node[13].IN0 +sel[2] => _.IN0 +sel[2] => result_node[12].IN0 +sel[2] => _.IN0 +sel[2] => result_node[11].IN0 +sel[2] => _.IN0 +sel[2] => result_node[10].IN0 +sel[2] => _.IN0 +sel[2] => result_node[9].IN0 +sel[2] => _.IN0 +sel[2] => result_node[8].IN0 +sel[2] => _.IN0 +sel[2] => result_node[7].IN0 +sel[2] => _.IN0 +sel[2] => result_node[6].IN0 +sel[2] => _.IN0 +sel[2] => result_node[5].IN0 +sel[2] => _.IN0 +sel[2] => result_node[4].IN0 +sel[2] => _.IN0 +sel[2] => result_node[3].IN0 +sel[2] => _.IN0 +sel[2] => result_node[2].IN0 +sel[2] => _.IN0 +sel[2] => result_node[1].IN0 +sel[2] => _.IN0 +sel[2] => result_node[0].IN0 +sel[2] => _.IN0 + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart +av_address => ien_AF.OUTPUTSELECT +av_address => ien_AE.OUTPUTSELECT +av_address => ac.OUTPUTSELECT +av_address => fifo_wr.OUTPUTSELECT +av_address => woverflow.OUTPUTSELECT +av_address => rvalid.OUTPUTSELECT +av_address => read_0.DATAB +av_address => fifo_rd.IN1 +av_chipselect => av_waitrequest.IN1 +av_chipselect => always2.IN0 +av_chipselect => always2.IN0 +av_chipselect => fifo_rd.IN0 +av_read_n => always2.IN1 +av_read_n => av_waitrequest.IN0 +av_read_n => fifo_rd.IN1 +av_write_n => always2.IN1 +av_write_n => av_waitrequest.IN1 +av_writedata[0] => fifo_wdata[0].IN1 +av_writedata[1] => fifo_wdata[1].IN1 +av_writedata[2] => fifo_wdata[2].IN1 +av_writedata[3] => fifo_wdata[3].IN1 +av_writedata[4] => fifo_wdata[4].IN1 +av_writedata[5] => fifo_wdata[5].IN1 +av_writedata[6] => fifo_wdata[6].IN1 +av_writedata[7] => fifo_wdata[7].IN1 +av_writedata[8] => ~NO_FANOUT~ +av_writedata[9] => ~NO_FANOUT~ +av_writedata[10] => always2.IN1 +av_writedata[11] => ~NO_FANOUT~ +av_writedata[12] => ~NO_FANOUT~ +av_writedata[13] => ~NO_FANOUT~ +av_writedata[14] => ~NO_FANOUT~ +av_writedata[15] => ~NO_FANOUT~ +av_writedata[16] => ~NO_FANOUT~ +av_writedata[17] => ~NO_FANOUT~ +av_writedata[18] => ~NO_FANOUT~ +av_writedata[19] => ~NO_FANOUT~ +av_writedata[20] => ~NO_FANOUT~ +av_writedata[21] => ~NO_FANOUT~ +av_writedata[22] => ~NO_FANOUT~ +av_writedata[23] => ~NO_FANOUT~ +av_writedata[24] => ~NO_FANOUT~ +av_writedata[25] => ~NO_FANOUT~ +av_writedata[26] => ~NO_FANOUT~ +av_writedata[27] => ~NO_FANOUT~ +av_writedata[28] => ~NO_FANOUT~ +av_writedata[29] => ~NO_FANOUT~ +av_writedata[30] => ~NO_FANOUT~ +av_writedata[31] => ~NO_FANOUT~ +clk => clk.IN3 +rst_n => rst_n.IN2 +av_irq <= av_irq.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= ipen_AF.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= ipen_AE.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= ac.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= +av_readdata[12] <= nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r.fifo_EF +av_readdata[13] <= nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w.fifo_FF +av_readdata[14] <= woverflow.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= rvalid.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= +av_readdata[24] <= +av_readdata[25] <= +av_readdata[26] <= +av_readdata[27] <= +av_readdata[28] <= +av_readdata[29] <= +av_readdata[30] <= +av_readdata[31] <= +av_waitrequest <= av_waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE +dataavailable <= dataavailable~reg0.DB_MAX_OUTPUT_PORT_TYPE +readyfordata <= readyfordata~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w +clk => clk.IN1 +fifo_clear => fifo_clear.IN1 +fifo_wdata[0] => fifo_wdata[0].IN1 +fifo_wdata[1] => fifo_wdata[1].IN1 +fifo_wdata[2] => fifo_wdata[2].IN1 +fifo_wdata[3] => fifo_wdata[3].IN1 +fifo_wdata[4] => fifo_wdata[4].IN1 +fifo_wdata[5] => fifo_wdata[5].IN1 +fifo_wdata[6] => fifo_wdata[6].IN1 +fifo_wdata[7] => fifo_wdata[7].IN1 +fifo_wr => fifo_wr.IN1 +rd_wfifo => rd_wfifo.IN1 +fifo_FF <= scfifo:wfifo.full +r_dat[0] <= scfifo:wfifo.q +r_dat[1] <= scfifo:wfifo.q +r_dat[2] <= scfifo:wfifo.q +r_dat[3] <= scfifo:wfifo.q +r_dat[4] <= scfifo:wfifo.q +r_dat[5] <= scfifo:wfifo.q +r_dat[6] <= scfifo:wfifo.q +r_dat[7] <= scfifo:wfifo.q +wfifo_empty <= scfifo:wfifo.empty +wfifo_used[0] <= scfifo:wfifo.usedw +wfifo_used[1] <= scfifo:wfifo.usedw +wfifo_used[2] <= scfifo:wfifo.usedw +wfifo_used[3] <= scfifo:wfifo.usedw +wfifo_used[4] <= scfifo:wfifo.usedw +wfifo_used[5] <= scfifo:wfifo.usedw + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo +data[0] => scfifo_jr21:auto_generated.data[0] +data[1] => scfifo_jr21:auto_generated.data[1] +data[2] => scfifo_jr21:auto_generated.data[2] +data[3] => scfifo_jr21:auto_generated.data[3] +data[4] => scfifo_jr21:auto_generated.data[4] +data[5] => scfifo_jr21:auto_generated.data[5] +data[6] => scfifo_jr21:auto_generated.data[6] +data[7] => scfifo_jr21:auto_generated.data[7] +q[0] <= scfifo_jr21:auto_generated.q[0] +q[1] <= scfifo_jr21:auto_generated.q[1] +q[2] <= scfifo_jr21:auto_generated.q[2] +q[3] <= scfifo_jr21:auto_generated.q[3] +q[4] <= scfifo_jr21:auto_generated.q[4] +q[5] <= scfifo_jr21:auto_generated.q[5] +q[6] <= scfifo_jr21:auto_generated.q[6] +q[7] <= scfifo_jr21:auto_generated.q[7] +wrreq => scfifo_jr21:auto_generated.wrreq +rdreq => scfifo_jr21:auto_generated.rdreq +clock => scfifo_jr21:auto_generated.clock +aclr => scfifo_jr21:auto_generated.aclr +sclr => ~NO_FANOUT~ +empty <= scfifo_jr21:auto_generated.empty +full <= scfifo_jr21:auto_generated.full +almost_full <= +almost_empty <= +usedw[0] <= scfifo_jr21:auto_generated.usedw[0] +usedw[1] <= scfifo_jr21:auto_generated.usedw[1] +usedw[2] <= scfifo_jr21:auto_generated.usedw[2] +usedw[3] <= scfifo_jr21:auto_generated.usedw[3] +usedw[4] <= scfifo_jr21:auto_generated.usedw[4] +usedw[5] <= scfifo_jr21:auto_generated.usedw[5] + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated +aclr => a_dpfifo_q131:dpfifo.aclr +clock => a_dpfifo_q131:dpfifo.clock +data[0] => a_dpfifo_q131:dpfifo.data[0] +data[1] => a_dpfifo_q131:dpfifo.data[1] +data[2] => a_dpfifo_q131:dpfifo.data[2] +data[3] => a_dpfifo_q131:dpfifo.data[3] +data[4] => a_dpfifo_q131:dpfifo.data[4] +data[5] => a_dpfifo_q131:dpfifo.data[5] +data[6] => a_dpfifo_q131:dpfifo.data[6] +data[7] => a_dpfifo_q131:dpfifo.data[7] +empty <= a_dpfifo_q131:dpfifo.empty +full <= a_dpfifo_q131:dpfifo.full +q[0] <= a_dpfifo_q131:dpfifo.q[0] +q[1] <= a_dpfifo_q131:dpfifo.q[1] +q[2] <= a_dpfifo_q131:dpfifo.q[2] +q[3] <= a_dpfifo_q131:dpfifo.q[3] +q[4] <= a_dpfifo_q131:dpfifo.q[4] +q[5] <= a_dpfifo_q131:dpfifo.q[5] +q[6] <= a_dpfifo_q131:dpfifo.q[6] +q[7] <= a_dpfifo_q131:dpfifo.q[7] +rdreq => a_dpfifo_q131:dpfifo.rreq +usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] +usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] +usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] +usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] +usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] +usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] +wrreq => a_dpfifo_q131:dpfifo.wreq + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo +aclr => a_fefifo_7cf:fifo_state.aclr +aclr => cntr_1ob:rd_ptr_count.aclr +aclr => cntr_1ob:wr_ptr.aclr +clock => a_fefifo_7cf:fifo_state.clock +clock => dpram_nl21:FIFOram.inclock +clock => dpram_nl21:FIFOram.outclock +clock => cntr_1ob:rd_ptr_count.clock +clock => cntr_1ob:wr_ptr.clock +data[0] => dpram_nl21:FIFOram.data[0] +data[1] => dpram_nl21:FIFOram.data[1] +data[2] => dpram_nl21:FIFOram.data[2] +data[3] => dpram_nl21:FIFOram.data[3] +data[4] => dpram_nl21:FIFOram.data[4] +data[5] => dpram_nl21:FIFOram.data[5] +data[6] => dpram_nl21:FIFOram.data[6] +data[7] => dpram_nl21:FIFOram.data[7] +empty <= a_fefifo_7cf:fifo_state.empty +full <= a_fefifo_7cf:fifo_state.full +q[0] <= dpram_nl21:FIFOram.q[0] +q[1] <= dpram_nl21:FIFOram.q[1] +q[2] <= dpram_nl21:FIFOram.q[2] +q[3] <= dpram_nl21:FIFOram.q[3] +q[4] <= dpram_nl21:FIFOram.q[4] +q[5] <= dpram_nl21:FIFOram.q[5] +q[6] <= dpram_nl21:FIFOram.q[6] +q[7] <= dpram_nl21:FIFOram.q[7] +rreq => a_fefifo_7cf:fifo_state.rreq +rreq => _.IN0 +rreq => cntr_1ob:rd_ptr_count.cnt_en +sclr => a_fefifo_7cf:fifo_state.sclr +sclr => _.IN1 +sclr => _.IN0 +sclr => cntr_1ob:rd_ptr_count.sclr +sclr => cntr_1ob:wr_ptr.sclr +usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] +usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] +usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] +usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] +usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] +usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] +wreq => a_fefifo_7cf:fifo_state.wreq +wreq => dpram_nl21:FIFOram.wren +wreq => cntr_1ob:wr_ptr.cnt_en + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state +aclr => b_full.IN0 +aclr => b_non_empty.IN0 +aclr => cntr_do7:count_usedw.aclr +clock => cntr_do7:count_usedw.clock +clock => b_full.CLK +clock => b_non_empty.CLK +empty <= empty.DB_MAX_OUTPUT_PORT_TYPE +full <= b_full.DB_MAX_OUTPUT_PORT_TYPE +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => cntr_do7:count_usedw.sclr +usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE +wreq => _.IN1 +wreq => _.IN1 +wreq => _.IN0 +wreq => _.IN0 +wreq => cntr_do7:count_usedw.updown + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +updown => counter_comb_bita0.DATAB +updown => counter_comb_bita1.DATAB +updown => counter_comb_bita2.DATAB +updown => counter_comb_bita3.DATAB +updown => counter_comb_bita4.DATAB +updown => counter_comb_bita5.DATAB + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram +data[0] => altsyncram_r1m1:altsyncram1.data_a[0] +data[1] => altsyncram_r1m1:altsyncram1.data_a[1] +data[2] => altsyncram_r1m1:altsyncram1.data_a[2] +data[3] => altsyncram_r1m1:altsyncram1.data_a[3] +data[4] => altsyncram_r1m1:altsyncram1.data_a[4] +data[5] => altsyncram_r1m1:altsyncram1.data_a[5] +data[6] => altsyncram_r1m1:altsyncram1.data_a[6] +data[7] => altsyncram_r1m1:altsyncram1.data_a[7] +inclock => altsyncram_r1m1:altsyncram1.clock0 +outclock => altsyncram_r1m1:altsyncram1.clock1 +outclocken => altsyncram_r1m1:altsyncram1.clocken1 +q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] +q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] +q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] +q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] +q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] +q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] +q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] +q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] +rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] +rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] +rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] +rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] +rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] +rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] +wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] +wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] +wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] +wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] +wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] +wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] +wren => altsyncram_r1m1:altsyncram1.wren_a + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 +address_a[0] => ram_block2a0.PORTAADDR +address_a[0] => ram_block2a1.PORTAADDR +address_a[0] => ram_block2a2.PORTAADDR +address_a[0] => ram_block2a3.PORTAADDR +address_a[0] => ram_block2a4.PORTAADDR +address_a[0] => ram_block2a5.PORTAADDR +address_a[0] => ram_block2a6.PORTAADDR +address_a[0] => ram_block2a7.PORTAADDR +address_a[1] => ram_block2a0.PORTAADDR1 +address_a[1] => ram_block2a1.PORTAADDR1 +address_a[1] => ram_block2a2.PORTAADDR1 +address_a[1] => ram_block2a3.PORTAADDR1 +address_a[1] => ram_block2a4.PORTAADDR1 +address_a[1] => ram_block2a5.PORTAADDR1 +address_a[1] => ram_block2a6.PORTAADDR1 +address_a[1] => ram_block2a7.PORTAADDR1 +address_a[2] => ram_block2a0.PORTAADDR2 +address_a[2] => ram_block2a1.PORTAADDR2 +address_a[2] => ram_block2a2.PORTAADDR2 +address_a[2] => ram_block2a3.PORTAADDR2 +address_a[2] => ram_block2a4.PORTAADDR2 +address_a[2] => ram_block2a5.PORTAADDR2 +address_a[2] => ram_block2a6.PORTAADDR2 +address_a[2] => ram_block2a7.PORTAADDR2 +address_a[3] => ram_block2a0.PORTAADDR3 +address_a[3] => ram_block2a1.PORTAADDR3 +address_a[3] => ram_block2a2.PORTAADDR3 +address_a[3] => ram_block2a3.PORTAADDR3 +address_a[3] => ram_block2a4.PORTAADDR3 +address_a[3] => ram_block2a5.PORTAADDR3 +address_a[3] => ram_block2a6.PORTAADDR3 +address_a[3] => ram_block2a7.PORTAADDR3 +address_a[4] => ram_block2a0.PORTAADDR4 +address_a[4] => ram_block2a1.PORTAADDR4 +address_a[4] => ram_block2a2.PORTAADDR4 +address_a[4] => ram_block2a3.PORTAADDR4 +address_a[4] => ram_block2a4.PORTAADDR4 +address_a[4] => ram_block2a5.PORTAADDR4 +address_a[4] => ram_block2a6.PORTAADDR4 +address_a[4] => ram_block2a7.PORTAADDR4 +address_a[5] => ram_block2a0.PORTAADDR5 +address_a[5] => ram_block2a1.PORTAADDR5 +address_a[5] => ram_block2a2.PORTAADDR5 +address_a[5] => ram_block2a3.PORTAADDR5 +address_a[5] => ram_block2a4.PORTAADDR5 +address_a[5] => ram_block2a5.PORTAADDR5 +address_a[5] => ram_block2a6.PORTAADDR5 +address_a[5] => ram_block2a7.PORTAADDR5 +address_b[0] => ram_block2a0.PORTBADDR +address_b[0] => ram_block2a1.PORTBADDR +address_b[0] => ram_block2a2.PORTBADDR +address_b[0] => ram_block2a3.PORTBADDR +address_b[0] => ram_block2a4.PORTBADDR +address_b[0] => ram_block2a5.PORTBADDR +address_b[0] => ram_block2a6.PORTBADDR +address_b[0] => ram_block2a7.PORTBADDR +address_b[1] => ram_block2a0.PORTBADDR1 +address_b[1] => ram_block2a1.PORTBADDR1 +address_b[1] => ram_block2a2.PORTBADDR1 +address_b[1] => ram_block2a3.PORTBADDR1 +address_b[1] => ram_block2a4.PORTBADDR1 +address_b[1] => ram_block2a5.PORTBADDR1 +address_b[1] => ram_block2a6.PORTBADDR1 +address_b[1] => ram_block2a7.PORTBADDR1 +address_b[2] => ram_block2a0.PORTBADDR2 +address_b[2] => ram_block2a1.PORTBADDR2 +address_b[2] => ram_block2a2.PORTBADDR2 +address_b[2] => ram_block2a3.PORTBADDR2 +address_b[2] => ram_block2a4.PORTBADDR2 +address_b[2] => ram_block2a5.PORTBADDR2 +address_b[2] => ram_block2a6.PORTBADDR2 +address_b[2] => ram_block2a7.PORTBADDR2 +address_b[3] => ram_block2a0.PORTBADDR3 +address_b[3] => ram_block2a1.PORTBADDR3 +address_b[3] => ram_block2a2.PORTBADDR3 +address_b[3] => ram_block2a3.PORTBADDR3 +address_b[3] => ram_block2a4.PORTBADDR3 +address_b[3] => ram_block2a5.PORTBADDR3 +address_b[3] => ram_block2a6.PORTBADDR3 +address_b[3] => ram_block2a7.PORTBADDR3 +address_b[4] => ram_block2a0.PORTBADDR4 +address_b[4] => ram_block2a1.PORTBADDR4 +address_b[4] => ram_block2a2.PORTBADDR4 +address_b[4] => ram_block2a3.PORTBADDR4 +address_b[4] => ram_block2a4.PORTBADDR4 +address_b[4] => ram_block2a5.PORTBADDR4 +address_b[4] => ram_block2a6.PORTBADDR4 +address_b[4] => ram_block2a7.PORTBADDR4 +address_b[5] => ram_block2a0.PORTBADDR5 +address_b[5] => ram_block2a1.PORTBADDR5 +address_b[5] => ram_block2a2.PORTBADDR5 +address_b[5] => ram_block2a3.PORTBADDR5 +address_b[5] => ram_block2a4.PORTBADDR5 +address_b[5] => ram_block2a5.PORTBADDR5 +address_b[5] => ram_block2a6.PORTBADDR5 +address_b[5] => ram_block2a7.PORTBADDR5 +clock0 => ram_block2a0.CLK0 +clock0 => ram_block2a1.CLK0 +clock0 => ram_block2a2.CLK0 +clock0 => ram_block2a3.CLK0 +clock0 => ram_block2a4.CLK0 +clock0 => ram_block2a5.CLK0 +clock0 => ram_block2a6.CLK0 +clock0 => ram_block2a7.CLK0 +clock1 => ram_block2a0.CLK1 +clock1 => ram_block2a1.CLK1 +clock1 => ram_block2a2.CLK1 +clock1 => ram_block2a3.CLK1 +clock1 => ram_block2a4.CLK1 +clock1 => ram_block2a5.CLK1 +clock1 => ram_block2a6.CLK1 +clock1 => ram_block2a7.CLK1 +clocken1 => ram_block2a0.ENA1 +clocken1 => ram_block2a1.ENA1 +clocken1 => ram_block2a2.ENA1 +clocken1 => ram_block2a3.ENA1 +clocken1 => ram_block2a4.ENA1 +clocken1 => ram_block2a5.ENA1 +clocken1 => ram_block2a6.ENA1 +clocken1 => ram_block2a7.ENA1 +data_a[0] => ram_block2a0.PORTADATAIN +data_a[1] => ram_block2a1.PORTADATAIN +data_a[2] => ram_block2a2.PORTADATAIN +data_a[3] => ram_block2a3.PORTADATAIN +data_a[4] => ram_block2a4.PORTADATAIN +data_a[5] => ram_block2a5.PORTADATAIN +data_a[6] => ram_block2a6.PORTADATAIN +data_a[7] => ram_block2a7.PORTADATAIN +q_b[0] <= ram_block2a0.PORTBDATAOUT +q_b[1] <= ram_block2a1.PORTBDATAOUT +q_b[2] <= ram_block2a2.PORTBDATAOUT +q_b[3] <= ram_block2a3.PORTBDATAOUT +q_b[4] <= ram_block2a4.PORTBDATAOUT +q_b[5] <= ram_block2a5.PORTBDATAOUT +q_b[6] <= ram_block2a6.PORTBDATAOUT +q_b[7] <= ram_block2a7.PORTBDATAOUT +wren_a => ram_block2a0.PORTAWE +wren_a => ram_block2a0.ENA0 +wren_a => ram_block2a1.PORTAWE +wren_a => ram_block2a1.ENA0 +wren_a => ram_block2a2.PORTAWE +wren_a => ram_block2a2.ENA0 +wren_a => ram_block2a3.PORTAWE +wren_a => ram_block2a3.ENA0 +wren_a => ram_block2a4.PORTAWE +wren_a => ram_block2a4.ENA0 +wren_a => ram_block2a5.PORTAWE +wren_a => ram_block2a5.ENA0 +wren_a => ram_block2a6.PORTAWE +wren_a => ram_block2a6.ENA0 +wren_a => ram_block2a7.PORTAWE +wren_a => ram_block2a7.ENA0 + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r +clk => clk.IN1 +fifo_clear => fifo_clear.IN1 +fifo_rd => fifo_rd.IN1 +rst_n => ~NO_FANOUT~ +t_dat[0] => t_dat[0].IN1 +t_dat[1] => t_dat[1].IN1 +t_dat[2] => t_dat[2].IN1 +t_dat[3] => t_dat[3].IN1 +t_dat[4] => t_dat[4].IN1 +t_dat[5] => t_dat[5].IN1 +t_dat[6] => t_dat[6].IN1 +t_dat[7] => t_dat[7].IN1 +wr_rfifo => wr_rfifo.IN1 +fifo_EF <= scfifo:rfifo.empty +fifo_rdata[0] <= scfifo:rfifo.q +fifo_rdata[1] <= scfifo:rfifo.q +fifo_rdata[2] <= scfifo:rfifo.q +fifo_rdata[3] <= scfifo:rfifo.q +fifo_rdata[4] <= scfifo:rfifo.q +fifo_rdata[5] <= scfifo:rfifo.q +fifo_rdata[6] <= scfifo:rfifo.q +fifo_rdata[7] <= scfifo:rfifo.q +rfifo_full <= scfifo:rfifo.full +rfifo_used[0] <= scfifo:rfifo.usedw +rfifo_used[1] <= scfifo:rfifo.usedw +rfifo_used[2] <= scfifo:rfifo.usedw +rfifo_used[3] <= scfifo:rfifo.usedw +rfifo_used[4] <= scfifo:rfifo.usedw +rfifo_used[5] <= scfifo:rfifo.usedw + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo +data[0] => scfifo_jr21:auto_generated.data[0] +data[1] => scfifo_jr21:auto_generated.data[1] +data[2] => scfifo_jr21:auto_generated.data[2] +data[3] => scfifo_jr21:auto_generated.data[3] +data[4] => scfifo_jr21:auto_generated.data[4] +data[5] => scfifo_jr21:auto_generated.data[5] +data[6] => scfifo_jr21:auto_generated.data[6] +data[7] => scfifo_jr21:auto_generated.data[7] +q[0] <= scfifo_jr21:auto_generated.q[0] +q[1] <= scfifo_jr21:auto_generated.q[1] +q[2] <= scfifo_jr21:auto_generated.q[2] +q[3] <= scfifo_jr21:auto_generated.q[3] +q[4] <= scfifo_jr21:auto_generated.q[4] +q[5] <= scfifo_jr21:auto_generated.q[5] +q[6] <= scfifo_jr21:auto_generated.q[6] +q[7] <= scfifo_jr21:auto_generated.q[7] +wrreq => scfifo_jr21:auto_generated.wrreq +rdreq => scfifo_jr21:auto_generated.rdreq +clock => scfifo_jr21:auto_generated.clock +aclr => scfifo_jr21:auto_generated.aclr +sclr => ~NO_FANOUT~ +empty <= scfifo_jr21:auto_generated.empty +full <= scfifo_jr21:auto_generated.full +almost_full <= +almost_empty <= +usedw[0] <= scfifo_jr21:auto_generated.usedw[0] +usedw[1] <= scfifo_jr21:auto_generated.usedw[1] +usedw[2] <= scfifo_jr21:auto_generated.usedw[2] +usedw[3] <= scfifo_jr21:auto_generated.usedw[3] +usedw[4] <= scfifo_jr21:auto_generated.usedw[4] +usedw[5] <= scfifo_jr21:auto_generated.usedw[5] + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated +aclr => a_dpfifo_q131:dpfifo.aclr +clock => a_dpfifo_q131:dpfifo.clock +data[0] => a_dpfifo_q131:dpfifo.data[0] +data[1] => a_dpfifo_q131:dpfifo.data[1] +data[2] => a_dpfifo_q131:dpfifo.data[2] +data[3] => a_dpfifo_q131:dpfifo.data[3] +data[4] => a_dpfifo_q131:dpfifo.data[4] +data[5] => a_dpfifo_q131:dpfifo.data[5] +data[6] => a_dpfifo_q131:dpfifo.data[6] +data[7] => a_dpfifo_q131:dpfifo.data[7] +empty <= a_dpfifo_q131:dpfifo.empty +full <= a_dpfifo_q131:dpfifo.full +q[0] <= a_dpfifo_q131:dpfifo.q[0] +q[1] <= a_dpfifo_q131:dpfifo.q[1] +q[2] <= a_dpfifo_q131:dpfifo.q[2] +q[3] <= a_dpfifo_q131:dpfifo.q[3] +q[4] <= a_dpfifo_q131:dpfifo.q[4] +q[5] <= a_dpfifo_q131:dpfifo.q[5] +q[6] <= a_dpfifo_q131:dpfifo.q[6] +q[7] <= a_dpfifo_q131:dpfifo.q[7] +rdreq => a_dpfifo_q131:dpfifo.rreq +usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] +usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] +usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] +usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] +usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] +usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] +wrreq => a_dpfifo_q131:dpfifo.wreq + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo +aclr => a_fefifo_7cf:fifo_state.aclr +aclr => cntr_1ob:rd_ptr_count.aclr +aclr => cntr_1ob:wr_ptr.aclr +clock => a_fefifo_7cf:fifo_state.clock +clock => dpram_nl21:FIFOram.inclock +clock => dpram_nl21:FIFOram.outclock +clock => cntr_1ob:rd_ptr_count.clock +clock => cntr_1ob:wr_ptr.clock +data[0] => dpram_nl21:FIFOram.data[0] +data[1] => dpram_nl21:FIFOram.data[1] +data[2] => dpram_nl21:FIFOram.data[2] +data[3] => dpram_nl21:FIFOram.data[3] +data[4] => dpram_nl21:FIFOram.data[4] +data[5] => dpram_nl21:FIFOram.data[5] +data[6] => dpram_nl21:FIFOram.data[6] +data[7] => dpram_nl21:FIFOram.data[7] +empty <= a_fefifo_7cf:fifo_state.empty +full <= a_fefifo_7cf:fifo_state.full +q[0] <= dpram_nl21:FIFOram.q[0] +q[1] <= dpram_nl21:FIFOram.q[1] +q[2] <= dpram_nl21:FIFOram.q[2] +q[3] <= dpram_nl21:FIFOram.q[3] +q[4] <= dpram_nl21:FIFOram.q[4] +q[5] <= dpram_nl21:FIFOram.q[5] +q[6] <= dpram_nl21:FIFOram.q[6] +q[7] <= dpram_nl21:FIFOram.q[7] +rreq => a_fefifo_7cf:fifo_state.rreq +rreq => _.IN0 +rreq => cntr_1ob:rd_ptr_count.cnt_en +sclr => a_fefifo_7cf:fifo_state.sclr +sclr => _.IN1 +sclr => _.IN0 +sclr => cntr_1ob:rd_ptr_count.sclr +sclr => cntr_1ob:wr_ptr.sclr +usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] +usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] +usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] +usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] +usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] +usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] +wreq => a_fefifo_7cf:fifo_state.wreq +wreq => dpram_nl21:FIFOram.wren +wreq => cntr_1ob:wr_ptr.cnt_en + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state +aclr => b_full.IN0 +aclr => b_non_empty.IN0 +aclr => cntr_do7:count_usedw.aclr +clock => cntr_do7:count_usedw.clock +clock => b_full.CLK +clock => b_non_empty.CLK +empty <= empty.DB_MAX_OUTPUT_PORT_TYPE +full <= b_full.DB_MAX_OUTPUT_PORT_TYPE +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => cntr_do7:count_usedw.sclr +usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE +wreq => _.IN1 +wreq => _.IN1 +wreq => _.IN0 +wreq => _.IN0 +wreq => cntr_do7:count_usedw.updown + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +updown => counter_comb_bita0.DATAB +updown => counter_comb_bita1.DATAB +updown => counter_comb_bita2.DATAB +updown => counter_comb_bita3.DATAB +updown => counter_comb_bita4.DATAB +updown => counter_comb_bita5.DATAB + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram +data[0] => altsyncram_r1m1:altsyncram1.data_a[0] +data[1] => altsyncram_r1m1:altsyncram1.data_a[1] +data[2] => altsyncram_r1m1:altsyncram1.data_a[2] +data[3] => altsyncram_r1m1:altsyncram1.data_a[3] +data[4] => altsyncram_r1m1:altsyncram1.data_a[4] +data[5] => altsyncram_r1m1:altsyncram1.data_a[5] +data[6] => altsyncram_r1m1:altsyncram1.data_a[6] +data[7] => altsyncram_r1m1:altsyncram1.data_a[7] +inclock => altsyncram_r1m1:altsyncram1.clock0 +outclock => altsyncram_r1m1:altsyncram1.clock1 +outclocken => altsyncram_r1m1:altsyncram1.clocken1 +q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] +q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] +q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] +q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] +q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] +q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] +q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] +q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] +rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] +rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] +rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] +rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] +rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] +rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] +wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] +wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] +wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] +wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] +wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] +wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] +wren => altsyncram_r1m1:altsyncram1.wren_a + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 +address_a[0] => ram_block2a0.PORTAADDR +address_a[0] => ram_block2a1.PORTAADDR +address_a[0] => ram_block2a2.PORTAADDR +address_a[0] => ram_block2a3.PORTAADDR +address_a[0] => ram_block2a4.PORTAADDR +address_a[0] => ram_block2a5.PORTAADDR +address_a[0] => ram_block2a6.PORTAADDR +address_a[0] => ram_block2a7.PORTAADDR +address_a[1] => ram_block2a0.PORTAADDR1 +address_a[1] => ram_block2a1.PORTAADDR1 +address_a[1] => ram_block2a2.PORTAADDR1 +address_a[1] => ram_block2a3.PORTAADDR1 +address_a[1] => ram_block2a4.PORTAADDR1 +address_a[1] => ram_block2a5.PORTAADDR1 +address_a[1] => ram_block2a6.PORTAADDR1 +address_a[1] => ram_block2a7.PORTAADDR1 +address_a[2] => ram_block2a0.PORTAADDR2 +address_a[2] => ram_block2a1.PORTAADDR2 +address_a[2] => ram_block2a2.PORTAADDR2 +address_a[2] => ram_block2a3.PORTAADDR2 +address_a[2] => ram_block2a4.PORTAADDR2 +address_a[2] => ram_block2a5.PORTAADDR2 +address_a[2] => ram_block2a6.PORTAADDR2 +address_a[2] => ram_block2a7.PORTAADDR2 +address_a[3] => ram_block2a0.PORTAADDR3 +address_a[3] => ram_block2a1.PORTAADDR3 +address_a[3] => ram_block2a2.PORTAADDR3 +address_a[3] => ram_block2a3.PORTAADDR3 +address_a[3] => ram_block2a4.PORTAADDR3 +address_a[3] => ram_block2a5.PORTAADDR3 +address_a[3] => ram_block2a6.PORTAADDR3 +address_a[3] => ram_block2a7.PORTAADDR3 +address_a[4] => ram_block2a0.PORTAADDR4 +address_a[4] => ram_block2a1.PORTAADDR4 +address_a[4] => ram_block2a2.PORTAADDR4 +address_a[4] => ram_block2a3.PORTAADDR4 +address_a[4] => ram_block2a4.PORTAADDR4 +address_a[4] => ram_block2a5.PORTAADDR4 +address_a[4] => ram_block2a6.PORTAADDR4 +address_a[4] => ram_block2a7.PORTAADDR4 +address_a[5] => ram_block2a0.PORTAADDR5 +address_a[5] => ram_block2a1.PORTAADDR5 +address_a[5] => ram_block2a2.PORTAADDR5 +address_a[5] => ram_block2a3.PORTAADDR5 +address_a[5] => ram_block2a4.PORTAADDR5 +address_a[5] => ram_block2a5.PORTAADDR5 +address_a[5] => ram_block2a6.PORTAADDR5 +address_a[5] => ram_block2a7.PORTAADDR5 +address_b[0] => ram_block2a0.PORTBADDR +address_b[0] => ram_block2a1.PORTBADDR +address_b[0] => ram_block2a2.PORTBADDR +address_b[0] => ram_block2a3.PORTBADDR +address_b[0] => ram_block2a4.PORTBADDR +address_b[0] => ram_block2a5.PORTBADDR +address_b[0] => ram_block2a6.PORTBADDR +address_b[0] => ram_block2a7.PORTBADDR +address_b[1] => ram_block2a0.PORTBADDR1 +address_b[1] => ram_block2a1.PORTBADDR1 +address_b[1] => ram_block2a2.PORTBADDR1 +address_b[1] => ram_block2a3.PORTBADDR1 +address_b[1] => ram_block2a4.PORTBADDR1 +address_b[1] => ram_block2a5.PORTBADDR1 +address_b[1] => ram_block2a6.PORTBADDR1 +address_b[1] => ram_block2a7.PORTBADDR1 +address_b[2] => ram_block2a0.PORTBADDR2 +address_b[2] => ram_block2a1.PORTBADDR2 +address_b[2] => ram_block2a2.PORTBADDR2 +address_b[2] => ram_block2a3.PORTBADDR2 +address_b[2] => ram_block2a4.PORTBADDR2 +address_b[2] => ram_block2a5.PORTBADDR2 +address_b[2] => ram_block2a6.PORTBADDR2 +address_b[2] => ram_block2a7.PORTBADDR2 +address_b[3] => ram_block2a0.PORTBADDR3 +address_b[3] => ram_block2a1.PORTBADDR3 +address_b[3] => ram_block2a2.PORTBADDR3 +address_b[3] => ram_block2a3.PORTBADDR3 +address_b[3] => ram_block2a4.PORTBADDR3 +address_b[3] => ram_block2a5.PORTBADDR3 +address_b[3] => ram_block2a6.PORTBADDR3 +address_b[3] => ram_block2a7.PORTBADDR3 +address_b[4] => ram_block2a0.PORTBADDR4 +address_b[4] => ram_block2a1.PORTBADDR4 +address_b[4] => ram_block2a2.PORTBADDR4 +address_b[4] => ram_block2a3.PORTBADDR4 +address_b[4] => ram_block2a4.PORTBADDR4 +address_b[4] => ram_block2a5.PORTBADDR4 +address_b[4] => ram_block2a6.PORTBADDR4 +address_b[4] => ram_block2a7.PORTBADDR4 +address_b[5] => ram_block2a0.PORTBADDR5 +address_b[5] => ram_block2a1.PORTBADDR5 +address_b[5] => ram_block2a2.PORTBADDR5 +address_b[5] => ram_block2a3.PORTBADDR5 +address_b[5] => ram_block2a4.PORTBADDR5 +address_b[5] => ram_block2a5.PORTBADDR5 +address_b[5] => ram_block2a6.PORTBADDR5 +address_b[5] => ram_block2a7.PORTBADDR5 +clock0 => ram_block2a0.CLK0 +clock0 => ram_block2a1.CLK0 +clock0 => ram_block2a2.CLK0 +clock0 => ram_block2a3.CLK0 +clock0 => ram_block2a4.CLK0 +clock0 => ram_block2a5.CLK0 +clock0 => ram_block2a6.CLK0 +clock0 => ram_block2a7.CLK0 +clock1 => ram_block2a0.CLK1 +clock1 => ram_block2a1.CLK1 +clock1 => ram_block2a2.CLK1 +clock1 => ram_block2a3.CLK1 +clock1 => ram_block2a4.CLK1 +clock1 => ram_block2a5.CLK1 +clock1 => ram_block2a6.CLK1 +clock1 => ram_block2a7.CLK1 +clocken1 => ram_block2a0.ENA1 +clocken1 => ram_block2a1.ENA1 +clocken1 => ram_block2a2.ENA1 +clocken1 => ram_block2a3.ENA1 +clocken1 => ram_block2a4.ENA1 +clocken1 => ram_block2a5.ENA1 +clocken1 => ram_block2a6.ENA1 +clocken1 => ram_block2a7.ENA1 +data_a[0] => ram_block2a0.PORTADATAIN +data_a[1] => ram_block2a1.PORTADATAIN +data_a[2] => ram_block2a2.PORTADATAIN +data_a[3] => ram_block2a3.PORTADATAIN +data_a[4] => ram_block2a4.PORTADATAIN +data_a[5] => ram_block2a5.PORTADATAIN +data_a[6] => ram_block2a6.PORTADATAIN +data_a[7] => ram_block2a7.PORTADATAIN +q_b[0] <= ram_block2a0.PORTBDATAOUT +q_b[1] <= ram_block2a1.PORTBDATAOUT +q_b[2] <= ram_block2a2.PORTBDATAOUT +q_b[3] <= ram_block2a3.PORTBDATAOUT +q_b[4] <= ram_block2a4.PORTBDATAOUT +q_b[5] <= ram_block2a5.PORTBDATAOUT +q_b[6] <= ram_block2a6.PORTBDATAOUT +q_b[7] <= ram_block2a7.PORTBDATAOUT +wren_a => ram_block2a0.PORTAWE +wren_a => ram_block2a0.ENA0 +wren_a => ram_block2a1.PORTAWE +wren_a => ram_block2a1.ENA0 +wren_a => ram_block2a2.PORTAWE +wren_a => ram_block2a2.ENA0 +wren_a => ram_block2a3.PORTAWE +wren_a => ram_block2a3.ENA0 +wren_a => ram_block2a4.PORTAWE +wren_a => ram_block2a4.ENA0 +wren_a => ram_block2a5.PORTAWE +wren_a => ram_block2a5.ENA0 +wren_a => ram_block2a6.PORTAWE +wren_a => ram_block2a6.ENA0 +wren_a => ram_block2a7.PORTAWE +wren_a => ram_block2a7.ENA0 + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic +raw_tck => write_stalled.CLK +raw_tck => wdata[0].CLK +raw_tck => wdata[1].CLK +raw_tck => wdata[2].CLK +raw_tck => wdata[3].CLK +raw_tck => wdata[4].CLK +raw_tck => wdata[5].CLK +raw_tck => wdata[6].CLK +raw_tck => wdata[7].CLK +raw_tck => write.CLK +raw_tck => read.CLK +raw_tck => read_req.CLK +raw_tck => write_valid.CLK +raw_tck => count[0].CLK +raw_tck => count[1].CLK +raw_tck => count[2].CLK +raw_tck => count[3].CLK +raw_tck => count[4].CLK +raw_tck => count[5].CLK +raw_tck => count[6].CLK +raw_tck => count[7].CLK +raw_tck => count[8].CLK +raw_tck => count[9].CLK +raw_tck => state.CLK +raw_tck => user_saw_rvalid.CLK +raw_tck => td_shift[0].CLK +raw_tck => td_shift[1].CLK +raw_tck => td_shift[2].CLK +raw_tck => td_shift[3].CLK +raw_tck => td_shift[4].CLK +raw_tck => td_shift[5].CLK +raw_tck => td_shift[6].CLK +raw_tck => td_shift[7].CLK +raw_tck => td_shift[8].CLK +raw_tck => td_shift[9].CLK +raw_tck => td_shift[10].CLK +raw_tck => tck_t_dav.CLK +raw_tck => jupdate.CLK +raw_tck => tdo~reg0.CLK +tck => ~NO_FANOUT~ +tdi => td_shift.OUTPUTSELECT +tdi => count.OUTPUTSELECT +tdi => state.OUTPUTSELECT +tdi => wdata.DATAB +tdi => always0.IN1 +tdi => wdata.DATAB +tdi => td_shift.DATAB +rti => ~NO_FANOUT~ +shift => ~NO_FANOUT~ +update => ~NO_FANOUT~ +usr1 => always0.IN0 +clr => jupdate.ACLR +clr => tdo~reg0.ACLR +clr => write_stalled.ACLR +clr => wdata[0].ACLR +clr => wdata[1].ACLR +clr => wdata[2].ACLR +clr => wdata[3].ACLR +clr => wdata[4].ACLR +clr => wdata[5].ACLR +clr => wdata[6].ACLR +clr => wdata[7].ACLR +clr => write.ACLR +clr => read.ACLR +clr => read_req.ACLR +clr => write_valid.ACLR +clr => count[0].ACLR +clr => count[1].ACLR +clr => count[2].ACLR +clr => count[3].ACLR +clr => count[4].ACLR +clr => count[5].ACLR +clr => count[6].ACLR +clr => count[7].ACLR +clr => count[8].ACLR +clr => count[9].PRESET +clr => state.ACLR +clr => user_saw_rvalid.ACLR +clr => td_shift[0].ACLR +clr => td_shift[1].ACLR +clr => td_shift[2].ACLR +clr => td_shift[3].ACLR +clr => td_shift[4].ACLR +clr => td_shift[5].ACLR +clr => td_shift[6].ACLR +clr => td_shift[7].ACLR +clr => td_shift[8].ACLR +clr => td_shift[9].ACLR +clr => td_shift[10].ACLR +clr => tck_t_dav.ACLR +ena => always0.IN1 +ir_in[0] => Decoder1.IN0 +ir_in[0] => ir_out[0].DATAIN +tdo <= tdo~reg0.DB_MAX_OUTPUT_PORT_TYPE +irq <= +ir_out[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE +jtag_state_cdr => state.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => write.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => user_saw_rvalid.OUTPUTSELECT +jtag_state_sdr => read.OUTPUTSELECT +jtag_state_sdr => write_valid.OUTPUTSELECT +jtag_state_sdr => read_req.OUTPUTSELECT +jtag_state_sdr => write_stalled.OUTPUTSELECT +jtag_state_sdr => state.OUTPUTSELECT +jtag_state_udr => jupdate.OUTPUTSELECT +clk => t_pause~reg0.CLK +clk => t_ena~reg0.CLK +clk => rdata[0].CLK +clk => rdata[1].CLK +clk => rdata[2].CLK +clk => rdata[3].CLK +clk => rdata[4].CLK +clk => rdata[5].CLK +clk => rdata[6].CLK +clk => rdata[7].CLK +clk => rvalid.CLK +clk => rvalid0.CLK +clk => r_ena1.CLK +clk => jupdate2.CLK +clk => jupdate1.CLK +clk => write2.CLK +clk => write1.CLK +clk => read2.CLK +clk => read1.CLK +clk => rst2.CLK +clk => rst1.CLK +rst_n => t_pause~reg0.ACLR +rst_n => t_ena~reg0.ACLR +rst_n => rdata[0].ACLR +rst_n => rdata[1].ACLR +rst_n => rdata[2].ACLR +rst_n => rdata[3].ACLR +rst_n => rdata[4].ACLR +rst_n => rdata[5].ACLR +rst_n => rdata[6].ACLR +rst_n => rdata[7].ACLR +rst_n => rvalid.ACLR +rst_n => rvalid0.ACLR +rst_n => r_ena1.ACLR +rst_n => jupdate2.ACLR +rst_n => jupdate1.ACLR +rst_n => write2.ACLR +rst_n => write1.ACLR +rst_n => read2.ACLR +rst_n => read1.ACLR +rst_n => rst2.PRESET +rst_n => rst1.PRESET +r_ena <= r_ena.DB_MAX_OUTPUT_PORT_TYPE +r_val => r_ena.IN1 +r_dat[0] => rdata[0].DATAIN +r_dat[1] => rdata[1].DATAIN +r_dat[2] => rdata[2].DATAIN +r_dat[3] => rdata[3].DATAIN +r_dat[4] => rdata[4].DATAIN +r_dat[5] => rdata[5].DATAIN +r_dat[6] => rdata[6].DATAIN +r_dat[7] => rdata[7].DATAIN +t_dav => always2.IN1 +t_dav => tck_t_dav.DATAIN +t_ena <= t_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE +t_dat[0] <= t_dat[0].DB_MAX_OUTPUT_PORT_TYPE +t_dat[1] <= t_dat[1].DB_MAX_OUTPUT_PORT_TYPE +t_dat[2] <= t_dat[2].DB_MAX_OUTPUT_PORT_TYPE +t_dat[3] <= t_dat[3].DB_MAX_OUTPUT_PORT_TYPE +t_dat[4] <= t_dat[4].DB_MAX_OUTPUT_PORT_TYPE +t_dat[5] <= t_dat[5].DB_MAX_OUTPUT_PORT_TYPE +t_dat[6] <= t_dat[6].DB_MAX_OUTPUT_PORT_TYPE +t_dat[7] <= t_dat[7].DB_MAX_OUTPUT_PORT_TYPE +t_pause <= t_pause~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_LEDs:leds +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +clk => data_out[7].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +reset_n => data_out[7].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => data_out[7].DATAIN +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_LEDRs:ledrs +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +clk => data_out[7].CLK +clk => data_out[8].CLK +clk => data_out[9].CLK +clk => data_out[10].CLK +clk => data_out[11].CLK +clk => data_out[12].CLK +clk => data_out[13].CLK +clk => data_out[14].CLK +clk => data_out[15].CLK +clk => data_out[16].CLK +clk => data_out[17].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +reset_n => data_out[7].ACLR +reset_n => data_out[8].ACLR +reset_n => data_out[9].ACLR +reset_n => data_out[10].ACLR +reset_n => data_out[11].ACLR +reset_n => data_out[12].ACLR +reset_n => data_out[13].ACLR +reset_n => data_out[14].ACLR +reset_n => data_out[15].ACLR +reset_n => data_out[16].ACLR +reset_n => data_out[17].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => data_out[7].DATAIN +writedata[8] => data_out[8].DATAIN +writedata[9] => data_out[9].DATAIN +writedata[10] => data_out[10].DATAIN +writedata[11] => data_out[11].DATAIN +writedata[12] => data_out[12].DATAIN +writedata[13] => data_out[13].DATAIN +writedata[14] => data_out[14].DATAIN +writedata[15] => data_out[15].DATAIN +writedata[16] => data_out[16].DATAIN +writedata[17] => data_out[17].DATAIN +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +out_port[7] <= data_out[7].DB_MAX_OUTPUT_PORT_TYPE +out_port[8] <= data_out[8].DB_MAX_OUTPUT_PORT_TYPE +out_port[9] <= data_out[9].DB_MAX_OUTPUT_PORT_TYPE +out_port[10] <= data_out[10].DB_MAX_OUTPUT_PORT_TYPE +out_port[11] <= data_out[11].DB_MAX_OUTPUT_PORT_TYPE +out_port[12] <= data_out[12].DB_MAX_OUTPUT_PORT_TYPE +out_port[13] <= data_out[13].DB_MAX_OUTPUT_PORT_TYPE +out_port[14] <= data_out[14].DB_MAX_OUTPUT_PORT_TYPE +out_port[15] <= data_out[15].DB_MAX_OUTPUT_PORT_TYPE +out_port[16] <= data_out[16].DB_MAX_OUTPUT_PORT_TYPE +out_port[17] <= data_out[17].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_switches:switches +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +clk => readdata[0]~reg0.CLK +clk => readdata[1]~reg0.CLK +clk => readdata[2]~reg0.CLK +clk => readdata[3]~reg0.CLK +clk => readdata[4]~reg0.CLK +clk => readdata[5]~reg0.CLK +clk => readdata[6]~reg0.CLK +clk => readdata[7]~reg0.CLK +clk => readdata[8]~reg0.CLK +clk => readdata[9]~reg0.CLK +clk => readdata[10]~reg0.CLK +clk => readdata[11]~reg0.CLK +clk => readdata[12]~reg0.CLK +clk => readdata[13]~reg0.CLK +clk => readdata[14]~reg0.CLK +clk => readdata[15]~reg0.CLK +clk => readdata[16]~reg0.CLK +clk => readdata[17]~reg0.CLK +clk => readdata[18]~reg0.CLK +clk => readdata[19]~reg0.CLK +clk => readdata[20]~reg0.CLK +clk => readdata[21]~reg0.CLK +clk => readdata[22]~reg0.CLK +clk => readdata[23]~reg0.CLK +clk => readdata[24]~reg0.CLK +clk => readdata[25]~reg0.CLK +clk => readdata[26]~reg0.CLK +clk => readdata[27]~reg0.CLK +clk => readdata[28]~reg0.CLK +clk => readdata[29]~reg0.CLK +clk => readdata[30]~reg0.CLK +clk => readdata[31]~reg0.CLK +in_port[0] => read_mux_out[0].IN1 +in_port[1] => read_mux_out[1].IN1 +in_port[2] => read_mux_out[2].IN1 +in_port[3] => read_mux_out[3].IN1 +in_port[4] => read_mux_out[4].IN1 +in_port[5] => read_mux_out[5].IN1 +in_port[6] => read_mux_out[6].IN1 +in_port[7] => read_mux_out[7].IN1 +in_port[8] => read_mux_out[8].IN1 +in_port[9] => read_mux_out[9].IN1 +in_port[10] => read_mux_out[10].IN1 +in_port[11] => read_mux_out[11].IN1 +in_port[12] => read_mux_out[12].IN1 +in_port[13] => read_mux_out[13].IN1 +in_port[14] => read_mux_out[14].IN1 +in_port[15] => read_mux_out[15].IN1 +in_port[16] => read_mux_out[16].IN1 +in_port[17] => read_mux_out[17].IN1 +reset_n => readdata[0]~reg0.ACLR +reset_n => readdata[1]~reg0.ACLR +reset_n => readdata[2]~reg0.ACLR +reset_n => readdata[3]~reg0.ACLR +reset_n => readdata[4]~reg0.ACLR +reset_n => readdata[5]~reg0.ACLR +reset_n => readdata[6]~reg0.ACLR +reset_n => readdata[7]~reg0.ACLR +reset_n => readdata[8]~reg0.ACLR +reset_n => readdata[9]~reg0.ACLR +reset_n => readdata[10]~reg0.ACLR +reset_n => readdata[11]~reg0.ACLR +reset_n => readdata[12]~reg0.ACLR +reset_n => readdata[13]~reg0.ACLR +reset_n => readdata[14]~reg0.ACLR +reset_n => readdata[15]~reg0.ACLR +reset_n => readdata[16]~reg0.ACLR +reset_n => readdata[17]~reg0.ACLR +reset_n => readdata[18]~reg0.ACLR +reset_n => readdata[19]~reg0.ACLR +reset_n => readdata[20]~reg0.ACLR +reset_n => readdata[21]~reg0.ACLR +reset_n => readdata[22]~reg0.ACLR +reset_n => readdata[23]~reg0.ACLR +reset_n => readdata[24]~reg0.ACLR +reset_n => readdata[25]~reg0.ACLR +reset_n => readdata[26]~reg0.ACLR +reset_n => readdata[27]~reg0.ACLR +reset_n => readdata[28]~reg0.ACLR +reset_n => readdata[29]~reg0.ACLR +reset_n => readdata[30]~reg0.ACLR +reset_n => readdata[31]~reg0.ACLR +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_push_switches:push_switches +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +clk => readdata[0]~reg0.CLK +clk => readdata[1]~reg0.CLK +clk => readdata[2]~reg0.CLK +clk => readdata[3]~reg0.CLK +clk => readdata[4]~reg0.CLK +clk => readdata[5]~reg0.CLK +clk => readdata[6]~reg0.CLK +clk => readdata[7]~reg0.CLK +clk => readdata[8]~reg0.CLK +clk => readdata[9]~reg0.CLK +clk => readdata[10]~reg0.CLK +clk => readdata[11]~reg0.CLK +clk => readdata[12]~reg0.CLK +clk => readdata[13]~reg0.CLK +clk => readdata[14]~reg0.CLK +clk => readdata[15]~reg0.CLK +clk => readdata[16]~reg0.CLK +clk => readdata[17]~reg0.CLK +clk => readdata[18]~reg0.CLK +clk => readdata[19]~reg0.CLK +clk => readdata[20]~reg0.CLK +clk => readdata[21]~reg0.CLK +clk => readdata[22]~reg0.CLK +clk => readdata[23]~reg0.CLK +clk => readdata[24]~reg0.CLK +clk => readdata[25]~reg0.CLK +clk => readdata[26]~reg0.CLK +clk => readdata[27]~reg0.CLK +clk => readdata[28]~reg0.CLK +clk => readdata[29]~reg0.CLK +clk => readdata[30]~reg0.CLK +clk => readdata[31]~reg0.CLK +in_port[0] => read_mux_out[0].IN1 +in_port[1] => read_mux_out[1].IN1 +in_port[2] => read_mux_out[2].IN1 +reset_n => readdata[0]~reg0.ACLR +reset_n => readdata[1]~reg0.ACLR +reset_n => readdata[2]~reg0.ACLR +reset_n => readdata[3]~reg0.ACLR +reset_n => readdata[4]~reg0.ACLR +reset_n => readdata[5]~reg0.ACLR +reset_n => readdata[6]~reg0.ACLR +reset_n => readdata[7]~reg0.ACLR +reset_n => readdata[8]~reg0.ACLR +reset_n => readdata[9]~reg0.ACLR +reset_n => readdata[10]~reg0.ACLR +reset_n => readdata[11]~reg0.ACLR +reset_n => readdata[12]~reg0.ACLR +reset_n => readdata[13]~reg0.ACLR +reset_n => readdata[14]~reg0.ACLR +reset_n => readdata[15]~reg0.ACLR +reset_n => readdata[16]~reg0.ACLR +reset_n => readdata[17]~reg0.ACLR +reset_n => readdata[18]~reg0.ACLR +reset_n => readdata[19]~reg0.ACLR +reset_n => readdata[20]~reg0.ACLR +reset_n => readdata[21]~reg0.ACLR +reset_n => readdata[22]~reg0.ACLR +reset_n => readdata[23]~reg0.ACLR +reset_n => readdata[24]~reg0.ACLR +reset_n => readdata[25]~reg0.ACLR +reset_n => readdata[26]~reg0.ACLR +reset_n => readdata[27]~reg0.ACLR +reset_n => readdata[28]~reg0.ACLR +reset_n => readdata[29]~reg0.ACLR +reset_n => readdata[30]~reg0.ACLR +reset_n => readdata[31]~reg0.ACLR +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_hex0:hex0 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_hex0:hex1 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_hex0:hex2 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_hex0:hex3 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_hex0:hex4 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_hex0:hex5 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_hex0:hex6 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_hex0:hex7 +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => always0.IN1 +writedata[0] => data_out[0].DATAIN +writedata[1] => data_out[1].DATAIN +writedata[2] => data_out[2].DATAIN +writedata[3] => data_out[3].DATAIN +writedata[4] => data_out[4].DATAIN +writedata[5] => data_out[5].DATAIN +writedata[6] => data_out[6].DATAIN +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 +address[0] => LCD_RW.DATAIN +address[0] => LCD_data[7].OE +address[0] => LCD_data[6].OE +address[0] => LCD_data[5].OE +address[0] => LCD_data[4].OE +address[0] => LCD_data[3].OE +address[0] => LCD_data[2].OE +address[0] => LCD_data[1].OE +address[0] => LCD_data[0].OE +address[1] => LCD_RS.DATAIN +begintransfer => ~NO_FANOUT~ +clk => ~NO_FANOUT~ +read => LCD_E.IN0 +reset_n => ~NO_FANOUT~ +write => LCD_E.IN1 +writedata[0] => LCD_data[0].DATAIN +writedata[1] => LCD_data[1].DATAIN +writedata[2] => LCD_data[2].DATAIN +writedata[3] => LCD_data[3].DATAIN +writedata[4] => LCD_data[4].DATAIN +writedata[5] => LCD_data[5].DATAIN +writedata[6] => LCD_data[6].DATAIN +writedata[7] => LCD_data[7].DATAIN +LCD_E <= LCD_E.DB_MAX_OUTPUT_PORT_TYPE +LCD_RS <= address[1].DB_MAX_OUTPUT_PORT_TYPE +LCD_RW <= address[0].DB_MAX_OUTPUT_PORT_TYPE +LCD_data[0] <> LCD_data[0] +LCD_data[1] <> LCD_data[1] +LCD_data[2] <> LCD_data[2] +LCD_data[3] <> LCD_data[3] +LCD_data[4] <> LCD_data[4] +LCD_data[5] <> LCD_data[5] +LCD_data[6] <> LCD_data[6] +LCD_data[7] <> LCD_data[7] +readdata[0] <= readdata[0].DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1].DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2].DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3].DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4].DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5].DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_lcd_on:lcd_on +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out.CLK +reset_n => data_out.ACLR +write_n => always0.IN1 +writedata[0] => data_out.DATAIN +writedata[1] => ~NO_FANOUT~ +writedata[2] => ~NO_FANOUT~ +writedata[3] => ~NO_FANOUT~ +writedata[4] => ~NO_FANOUT~ +writedata[5] => ~NO_FANOUT~ +writedata[6] => ~NO_FANOUT~ +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= +readdata[2] <= +readdata[3] <= +readdata[4] <= +readdata[5] <= +readdata[6] <= +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out.CLK +reset_n => data_out.ACLR +write_n => always0.IN1 +writedata[0] => data_out.DATAIN +writedata[1] => ~NO_FANOUT~ +writedata[2] => ~NO_FANOUT~ +writedata[3] => ~NO_FANOUT~ +writedata[4] => ~NO_FANOUT~ +writedata[5] => ~NO_FANOUT~ +writedata[6] => ~NO_FANOUT~ +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= +readdata[2] <= +readdata[3] <= +readdata[4] <= +readdata[5] <= +readdata[6] <= +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator +clk => read_accepted.CLK +reset => read_accepted.ACLR +uav_write <= +uav_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE +uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE +uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +uav_burstcount[0] <= +uav_burstcount[1] <= +uav_burstcount[2] <= +uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] => av_readdata[0].DATAIN +uav_readdata[1] => av_readdata[1].DATAIN +uav_readdata[2] => av_readdata[2].DATAIN +uav_readdata[3] => av_readdata[3].DATAIN +uav_readdata[4] => av_readdata[4].DATAIN +uav_readdata[5] => av_readdata[5].DATAIN +uav_readdata[6] => av_readdata[6].DATAIN +uav_readdata[7] => av_readdata[7].DATAIN +uav_readdata[8] => av_readdata[8].DATAIN +uav_readdata[9] => av_readdata[9].DATAIN +uav_readdata[10] => av_readdata[10].DATAIN +uav_readdata[11] => av_readdata[11].DATAIN +uav_readdata[12] => av_readdata[12].DATAIN +uav_readdata[13] => av_readdata[13].DATAIN +uav_readdata[14] => av_readdata[14].DATAIN +uav_readdata[15] => av_readdata[15].DATAIN +uav_readdata[16] => av_readdata[16].DATAIN +uav_readdata[17] => av_readdata[17].DATAIN +uav_readdata[18] => av_readdata[18].DATAIN +uav_readdata[19] => av_readdata[19].DATAIN +uav_readdata[20] => av_readdata[20].DATAIN +uav_readdata[21] => av_readdata[21].DATAIN +uav_readdata[22] => av_readdata[22].DATAIN +uav_readdata[23] => av_readdata[23].DATAIN +uav_readdata[24] => av_readdata[24].DATAIN +uav_readdata[25] => av_readdata[25].DATAIN +uav_readdata[26] => av_readdata[26].DATAIN +uav_readdata[27] => av_readdata[27].DATAIN +uav_readdata[28] => av_readdata[28].DATAIN +uav_readdata[29] => av_readdata[29].DATAIN +uav_readdata[30] => av_readdata[30].DATAIN +uav_readdata[31] => av_readdata[31].DATAIN +uav_readdatavalid => always5.IN1 +uav_readdatavalid => av_readdatavalid.DATAIN +uav_readdatavalid => av_waitrequest.DATAB +uav_waitrequest => av_waitrequest.DATAA +uav_waitrequest => read_accepted.IN0 +uav_response[0] => ~NO_FANOUT~ +uav_response[1] => ~NO_FANOUT~ +uav_writeresponserequest <= +uav_writeresponsevalid => ~NO_FANOUT~ +av_write => ~NO_FANOUT~ +av_read => read_accepted.IN1 +av_read => av_waitrequest.OUTPUTSELECT +av_read => uav_read.IN1 +av_address[0] => uav_address[0].DATAIN +av_address[1] => uav_address[1].DATAIN +av_address[2] => uav_address[2].DATAIN +av_address[3] => uav_address[3].DATAIN +av_address[4] => uav_address[4].DATAIN +av_address[5] => uav_address[5].DATAIN +av_address[6] => uav_address[6].DATAIN +av_address[7] => uav_address[7].DATAIN +av_address[8] => uav_address[8].DATAIN +av_address[9] => uav_address[9].DATAIN +av_address[10] => uav_address[10].DATAIN +av_address[11] => uav_address[11].DATAIN +av_address[12] => uav_address[12].DATAIN +av_address[13] => uav_address[13].DATAIN +av_address[14] => uav_address[14].DATAIN +av_address[15] => uav_address[15].DATAIN +av_address[16] => uav_address[16].DATAIN +av_address[17] => uav_address[17].DATAIN +av_address[18] => uav_address[18].DATAIN +av_byteenable[0] => uav_byteenable[0].DATAIN +av_byteenable[1] => uav_byteenable[1].DATAIN +av_byteenable[2] => uav_byteenable[2].DATAIN +av_byteenable[3] => uav_byteenable[3].DATAIN +av_burstcount[0] => ~NO_FANOUT~ +av_writedata[0] => uav_writedata[0].DATAIN +av_writedata[1] => uav_writedata[1].DATAIN +av_writedata[2] => uav_writedata[2].DATAIN +av_writedata[3] => uav_writedata[3].DATAIN +av_writedata[4] => uav_writedata[4].DATAIN +av_writedata[5] => uav_writedata[5].DATAIN +av_writedata[6] => uav_writedata[6].DATAIN +av_writedata[7] => uav_writedata[7].DATAIN +av_writedata[8] => uav_writedata[8].DATAIN +av_writedata[9] => uav_writedata[9].DATAIN +av_writedata[10] => uav_writedata[10].DATAIN +av_writedata[11] => uav_writedata[11].DATAIN +av_writedata[12] => uav_writedata[12].DATAIN +av_writedata[13] => uav_writedata[13].DATAIN +av_writedata[14] => uav_writedata[14].DATAIN +av_writedata[15] => uav_writedata[15].DATAIN +av_writedata[16] => uav_writedata[16].DATAIN +av_writedata[17] => uav_writedata[17].DATAIN +av_writedata[18] => uav_writedata[18].DATAIN +av_writedata[19] => uav_writedata[19].DATAIN +av_writedata[20] => uav_writedata[20].DATAIN +av_writedata[21] => uav_writedata[21].DATAIN +av_writedata[22] => uav_writedata[22].DATAIN +av_writedata[23] => uav_writedata[23].DATAIN +av_writedata[24] => uav_writedata[24].DATAIN +av_writedata[25] => uav_writedata[25].DATAIN +av_writedata[26] => uav_writedata[26].DATAIN +av_writedata[27] => uav_writedata[27].DATAIN +av_writedata[28] => uav_writedata[28].DATAIN +av_writedata[29] => uav_writedata[29].DATAIN +av_writedata[30] => uav_writedata[30].DATAIN +av_writedata[31] => uav_writedata[31].DATAIN +av_begintransfer => ~NO_FANOUT~ +av_beginbursttransfer => ~NO_FANOUT~ +av_lock => uav_lock.DATAIN +av_chipselect => ~NO_FANOUT~ +av_debugaccess => uav_debugaccess.DATAIN +av_clken => uav_clken.DATAIN +av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +av_response[0] <= +av_response[1] <= +av_writeresponserequest => ~NO_FANOUT~ +av_writeresponsevalid <= + + +|lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator +clk => end_begintransfer.CLK +clk => write_accepted.CLK +clk => read_accepted.CLK +reset => end_begintransfer.ACLR +reset => write_accepted.ACLR +reset => read_accepted.ACLR +uav_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE +uav_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE +uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE +uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +uav_burstcount[0] <= +uav_burstcount[1] <= +uav_burstcount[2] <= +uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] => av_readdata[0].DATAIN +uav_readdata[1] => av_readdata[1].DATAIN +uav_readdata[2] => av_readdata[2].DATAIN +uav_readdata[3] => av_readdata[3].DATAIN +uav_readdata[4] => av_readdata[4].DATAIN +uav_readdata[5] => av_readdata[5].DATAIN +uav_readdata[6] => av_readdata[6].DATAIN +uav_readdata[7] => av_readdata[7].DATAIN +uav_readdata[8] => av_readdata[8].DATAIN +uav_readdata[9] => av_readdata[9].DATAIN +uav_readdata[10] => av_readdata[10].DATAIN +uav_readdata[11] => av_readdata[11].DATAIN +uav_readdata[12] => av_readdata[12].DATAIN +uav_readdata[13] => av_readdata[13].DATAIN +uav_readdata[14] => av_readdata[14].DATAIN +uav_readdata[15] => av_readdata[15].DATAIN +uav_readdata[16] => av_readdata[16].DATAIN +uav_readdata[17] => av_readdata[17].DATAIN +uav_readdata[18] => av_readdata[18].DATAIN +uav_readdata[19] => av_readdata[19].DATAIN +uav_readdata[20] => av_readdata[20].DATAIN +uav_readdata[21] => av_readdata[21].DATAIN +uav_readdata[22] => av_readdata[22].DATAIN +uav_readdata[23] => av_readdata[23].DATAIN +uav_readdata[24] => av_readdata[24].DATAIN +uav_readdata[25] => av_readdata[25].DATAIN +uav_readdata[26] => av_readdata[26].DATAIN +uav_readdata[27] => av_readdata[27].DATAIN +uav_readdata[28] => av_readdata[28].DATAIN +uav_readdata[29] => av_readdata[29].DATAIN +uav_readdata[30] => av_readdata[30].DATAIN +uav_readdata[31] => av_readdata[31].DATAIN +uav_readdatavalid => always5.IN1 +uav_readdatavalid => av_readdatavalid.DATAIN +uav_readdatavalid => av_waitrequest.DATAB +uav_waitrequest => av_waitrequest.IN1 +uav_waitrequest => always10.IN1 +uav_waitrequest => end_begintransfer.OUTPUTSELECT +uav_waitrequest => read_accepted.IN0 +uav_waitrequest => write_accepted.IN1 +uav_response[0] => ~NO_FANOUT~ +uav_response[1] => ~NO_FANOUT~ +uav_writeresponserequest <= +uav_writeresponsevalid => ~NO_FANOUT~ +av_write => av_waitrequest.OUTPUTSELECT +av_write => uav_write.IN1 +av_read => read_accepted.IN1 +av_read => av_waitrequest.OUTPUTSELECT +av_read => uav_read.IN1 +av_address[0] => uav_address[0].DATAIN +av_address[1] => uav_address[1].DATAIN +av_address[2] => uav_address[2].DATAIN +av_address[3] => uav_address[3].DATAIN +av_address[4] => uav_address[4].DATAIN +av_address[5] => uav_address[5].DATAIN +av_address[6] => uav_address[6].DATAIN +av_address[7] => uav_address[7].DATAIN +av_address[8] => uav_address[8].DATAIN +av_address[9] => uav_address[9].DATAIN +av_address[10] => uav_address[10].DATAIN +av_address[11] => uav_address[11].DATAIN +av_address[12] => uav_address[12].DATAIN +av_address[13] => uav_address[13].DATAIN +av_address[14] => uav_address[14].DATAIN +av_address[15] => uav_address[15].DATAIN +av_address[16] => uav_address[16].DATAIN +av_address[17] => uav_address[17].DATAIN +av_address[18] => uav_address[18].DATAIN +av_byteenable[0] => uav_byteenable[0].DATAIN +av_byteenable[1] => uav_byteenable[1].DATAIN +av_byteenable[2] => uav_byteenable[2].DATAIN +av_byteenable[3] => uav_byteenable[3].DATAIN +av_burstcount[0] => ~NO_FANOUT~ +av_writedata[0] => uav_writedata[0].DATAIN +av_writedata[1] => uav_writedata[1].DATAIN +av_writedata[2] => uav_writedata[2].DATAIN +av_writedata[3] => uav_writedata[3].DATAIN +av_writedata[4] => uav_writedata[4].DATAIN +av_writedata[5] => uav_writedata[5].DATAIN +av_writedata[6] => uav_writedata[6].DATAIN +av_writedata[7] => uav_writedata[7].DATAIN +av_writedata[8] => uav_writedata[8].DATAIN +av_writedata[9] => uav_writedata[9].DATAIN +av_writedata[10] => uav_writedata[10].DATAIN +av_writedata[11] => uav_writedata[11].DATAIN +av_writedata[12] => uav_writedata[12].DATAIN +av_writedata[13] => uav_writedata[13].DATAIN +av_writedata[14] => uav_writedata[14].DATAIN +av_writedata[15] => uav_writedata[15].DATAIN +av_writedata[16] => uav_writedata[16].DATAIN +av_writedata[17] => uav_writedata[17].DATAIN +av_writedata[18] => uav_writedata[18].DATAIN +av_writedata[19] => uav_writedata[19].DATAIN +av_writedata[20] => uav_writedata[20].DATAIN +av_writedata[21] => uav_writedata[21].DATAIN +av_writedata[22] => uav_writedata[22].DATAIN +av_writedata[23] => uav_writedata[23].DATAIN +av_writedata[24] => uav_writedata[24].DATAIN +av_writedata[25] => uav_writedata[25].DATAIN +av_writedata[26] => uav_writedata[26].DATAIN +av_writedata[27] => uav_writedata[27].DATAIN +av_writedata[28] => uav_writedata[28].DATAIN +av_writedata[29] => uav_writedata[29].DATAIN +av_writedata[30] => uav_writedata[30].DATAIN +av_writedata[31] => uav_writedata[31].DATAIN +av_begintransfer => ~NO_FANOUT~ +av_beginbursttransfer => ~NO_FANOUT~ +av_lock => uav_lock.DATAIN +av_chipselect => ~NO_FANOUT~ +av_debugaccess => uav_debugaccess.DATAIN +av_clken => uav_clken.DATAIN +av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +av_response[0] <= +av_response[1] <= +av_writeresponserequest => ~NO_FANOUT~ +av_writeresponsevalid <= + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => av_address[2].DATAIN +uav_address[5] => av_address[3].DATAIN +uav_address[6] => av_address[4].DATAIN +uav_address[7] => av_address[5].DATAIN +uav_address[8] => av_address[6].DATAIN +uav_address[9] => av_address[7].DATAIN +uav_address[10] => av_address[8].DATAIN +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_write => av_write.DATAIN +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_read => av_read.DATAIN +uav_burstcount[0] => Equal0.IN3 +uav_burstcount[1] => Equal0.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal0.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => av_writebyteenable.IN1 +uav_byteenable[1] => av_byteenable[1].DATAIN +uav_byteenable[2] => av_writebyteenable.IN1 +uav_byteenable[2] => av_byteenable[2].DATAIN +uav_byteenable[3] => av_writebyteenable.IN1 +uav_byteenable[3] => av_byteenable[3].DATAIN +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE +av_address[3] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE +av_address[4] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE +av_address[5] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE +av_address[6] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE +av_address[7] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE +av_address[8] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => always18.IN1 +av_waitrequest => end_begintransfer.OUTPUTSELECT +av_waitrequest => uav_waitrequest.DATAIN +av_waitrequest => read_latency_shift_reg.IN1 +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => waitrequest_reset_override.CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => waitrequest_reset_override.PRESET +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => av_address[2].DATAIN +uav_address[5] => av_address[3].DATAIN +uav_address[6] => av_address[4].DATAIN +uav_address[7] => av_address[5].DATAIN +uav_address[8] => av_address[6].DATAIN +uav_address[9] => av_address[7].DATAIN +uav_address[10] => av_address[8].DATAIN +uav_address[11] => av_address[9].DATAIN +uav_address[12] => av_address[10].DATAIN +uav_address[13] => av_address[11].DATAIN +uav_address[14] => av_address[12].DATAIN +uav_address[15] => av_address[13].DATAIN +uav_address[16] => av_address[14].DATAIN +uav_address[17] => av_address[15].DATAIN +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_write => av_write.DATAIN +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_read => av_read.DATAIN +uav_read => av_outputenable_pre.DATAIN +uav_burstcount[0] => Equal0.IN3 +uav_burstcount[1] => Equal0.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal0.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => av_writebyteenable.IN1 +uav_byteenable[1] => av_byteenable[1].DATAIN +uav_byteenable[2] => av_writebyteenable.IN1 +uav_byteenable[2] => av_byteenable[2].DATAIN +uav_byteenable[3] => av_writebyteenable.IN1 +uav_byteenable[3] => av_byteenable[3].DATAIN +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= waitrequest_reset_override.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE +av_address[3] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE +av_address[4] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE +av_address[5] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE +av_address[6] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE +av_address[7] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE +av_address[8] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE +av_address[9] <= uav_address[11].DB_MAX_OUTPUT_PORT_TYPE +av_address[10] <= uav_address[12].DB_MAX_OUTPUT_PORT_TYPE +av_address[11] <= uav_address[13].DB_MAX_OUTPUT_PORT_TYPE +av_address[12] <= uav_address[14].DB_MAX_OUTPUT_PORT_TYPE +av_address[13] <= uav_address[15].DB_MAX_OUTPUT_PORT_TYPE +av_address[14] <= uav_address[16].DB_MAX_OUTPUT_PORT_TYPE +av_address[15] <= uav_address[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => uav_readdata[0].DATAIN +av_readdata[1] => uav_readdata[1].DATAIN +av_readdata[2] => uav_readdata[2].DATAIN +av_readdata[3] => uav_readdata[3].DATAIN +av_readdata[4] => uav_readdata[4].DATAIN +av_readdata[5] => uav_readdata[5].DATAIN +av_readdata[6] => uav_readdata[6].DATAIN +av_readdata[7] => uav_readdata[7].DATAIN +av_readdata[8] => uav_readdata[8].DATAIN +av_readdata[9] => uav_readdata[9].DATAIN +av_readdata[10] => uav_readdata[10].DATAIN +av_readdata[11] => uav_readdata[11].DATAIN +av_readdata[12] => uav_readdata[12].DATAIN +av_readdata[13] => uav_readdata[13].DATAIN +av_readdata[14] => uav_readdata[14].DATAIN +av_readdata[15] => uav_readdata[15].DATAIN +av_readdata[16] => uav_readdata[16].DATAIN +av_readdata[17] => uav_readdata[17].DATAIN +av_readdata[18] => uav_readdata[18].DATAIN +av_readdata[19] => uav_readdata[19].DATAIN +av_readdata[20] => uav_readdata[20].DATAIN +av_readdata[21] => uav_readdata[21].DATAIN +av_readdata[22] => uav_readdata[22].DATAIN +av_readdata[23] => uav_readdata[23].DATAIN +av_readdata[24] => uav_readdata[24].DATAIN +av_readdata[25] => uav_readdata[25].DATAIN +av_readdata[26] => uav_readdata[26].DATAIN +av_readdata[27] => uav_readdata[27].DATAIN +av_readdata[28] => uav_readdata[28].DATAIN +av_readdata[29] => uav_readdata[29].DATAIN +av_readdata[30] => uav_readdata[30].DATAIN +av_readdata[31] => uav_readdata[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => ~NO_FANOUT~ +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_write => av_write.DATAIN +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_read => av_read.DATAIN +uav_burstcount[0] => Equal0.IN3 +uav_burstcount[1] => Equal0.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal0.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => always18.IN1 +av_waitrequest => end_begintransfer.OUTPUTSELECT +av_waitrequest => uav_waitrequest.DATAIN +av_waitrequest => read_latency_shift_reg.IN1 +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +clk => wait_latency_counter[2].CLK +clk => wait_latency_counter[3].CLK +clk => wait_latency_counter[4].CLK +clk => wait_latency_counter[5].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +reset => wait_latency_counter[2].ACLR +reset => wait_latency_counter[3].ACLR +reset => wait_latency_counter[4].ACLR +reset => wait_latency_counter[5].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => ~NO_FANOUT~ +uav_writedata[9] => ~NO_FANOUT~ +uav_writedata[10] => ~NO_FANOUT~ +uav_writedata[11] => ~NO_FANOUT~ +uav_writedata[12] => ~NO_FANOUT~ +uav_writedata[13] => ~NO_FANOUT~ +uav_writedata[14] => ~NO_FANOUT~ +uav_writedata[15] => ~NO_FANOUT~ +uav_writedata[16] => ~NO_FANOUT~ +uav_writedata[17] => ~NO_FANOUT~ +uav_writedata[18] => ~NO_FANOUT~ +uav_writedata[19] => ~NO_FANOUT~ +uav_writedata[20] => ~NO_FANOUT~ +uav_writedata[21] => ~NO_FANOUT~ +uav_writedata[22] => ~NO_FANOUT~ +uav_writedata[23] => ~NO_FANOUT~ +uav_writedata[24] => ~NO_FANOUT~ +uav_writedata[25] => ~NO_FANOUT~ +uav_writedata[26] => ~NO_FANOUT~ +uav_writedata[27] => ~NO_FANOUT~ +uav_writedata[28] => ~NO_FANOUT~ +uav_writedata[29] => ~NO_FANOUT~ +uav_writedata[30] => ~NO_FANOUT~ +uav_writedata[31] => ~NO_FANOUT~ +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= +uav_readdata[9] <= +uav_readdata[10] <= +uav_readdata[11] <= +uav_readdata[12] <= +uav_readdata[13] <= +uav_readdata[14] <= +uav_readdata[15] <= +uav_readdata[16] <= +uav_readdata[17] <= +uav_readdata[18] <= +uav_readdata[19] <= +uav_readdata[20] <= +uav_readdata[21] <= +uav_readdata[22] <= +uav_readdata[23] <= +uav_readdata[24] <= +uav_readdata[25] <= +uav_readdata[26] <= +uav_readdata[27] <= +uav_readdata[28] <= +uav_readdata[29] <= +uav_readdata[30] <= +uav_readdata[31] <= +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always20.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +uav_response[0] <= +uav_response[1] <= +uav_writeresponserequest => av_writeresponserequest.DATAIN +uav_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ +av_response[0] => ~NO_FANOUT~ +av_response[1] => ~NO_FANOUT~ +av_writeresponserequest <= uav_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +av_writeresponsevalid => uav_writeresponsevalid.DATAIN + + +|lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent +clk => hold_waitrequest.CLK +reset => hold_waitrequest.PRESET +av_address[0] => ~NO_FANOUT~ +av_address[1] => ~NO_FANOUT~ +av_address[2] => cp_data[38].DATAIN +av_address[3] => cp_data[39].DATAIN +av_address[4] => cp_data[40].DATAIN +av_address[5] => cp_data[41].DATAIN +av_address[6] => cp_data[42].DATAIN +av_address[7] => cp_data[43].DATAIN +av_address[8] => cp_data[44].DATAIN +av_address[9] => cp_data[45].DATAIN +av_address[10] => cp_data[46].DATAIN +av_address[11] => cp_data[47].DATAIN +av_address[12] => cp_data[48].DATAIN +av_address[13] => cp_data[49].DATAIN +av_address[14] => cp_data[50].DATAIN +av_address[15] => cp_data[51].DATAIN +av_address[16] => cp_data[52].DATAIN +av_address[17] => cp_data[53].DATAIN +av_address[18] => cp_data[54].DATAIN +av_write => cp_data.IN0 +av_write => always1.IN0 +av_write => cp_data[57].DATAIN +av_read => always1.IN1 +av_read => cp_data[58].DATAIN +av_writedata[0] => cp_data[0].DATAIN +av_writedata[1] => cp_data[1].DATAIN +av_writedata[2] => cp_data[2].DATAIN +av_writedata[3] => cp_data[3].DATAIN +av_writedata[4] => cp_data[4].DATAIN +av_writedata[5] => cp_data[5].DATAIN +av_writedata[6] => cp_data[6].DATAIN +av_writedata[7] => cp_data[7].DATAIN +av_writedata[8] => cp_data[8].DATAIN +av_writedata[9] => cp_data[9].DATAIN +av_writedata[10] => cp_data[10].DATAIN +av_writedata[11] => cp_data[11].DATAIN +av_writedata[12] => cp_data[12].DATAIN +av_writedata[13] => cp_data[13].DATAIN +av_writedata[14] => cp_data[14].DATAIN +av_writedata[15] => cp_data[15].DATAIN +av_writedata[16] => cp_data[16].DATAIN +av_writedata[17] => cp_data[17].DATAIN +av_writedata[18] => cp_data[18].DATAIN +av_writedata[19] => cp_data[19].DATAIN +av_writedata[20] => cp_data[20].DATAIN +av_writedata[21] => cp_data[21].DATAIN +av_writedata[22] => cp_data[22].DATAIN +av_writedata[23] => cp_data[23].DATAIN +av_writedata[24] => cp_data[24].DATAIN +av_writedata[25] => cp_data[25].DATAIN +av_writedata[26] => cp_data[26].DATAIN +av_writedata[27] => cp_data[27].DATAIN +av_writedata[28] => cp_data[28].DATAIN +av_writedata[29] => cp_data[29].DATAIN +av_writedata[30] => cp_data[30].DATAIN +av_writedata[31] => cp_data[31].DATAIN +av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= av_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] => cp_data[32].DATAIN +av_byteenable[1] => cp_data[33].DATAIN +av_byteenable[2] => cp_data[34].DATAIN +av_byteenable[3] => cp_data[35].DATAIN +av_burstcount[0] => cp_data[61].DATAIN +av_burstcount[1] => cp_data[62].DATAIN +av_burstcount[2] => cp_data[63].DATAIN +av_debugaccess => cp_data[87].DATAIN +av_lock => cp_data[59].DATAIN +av_response[0] <= +av_response[1] <= +av_writeresponserequest => cp_data.IN1 +av_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE +cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[36] <= +cp_data[37] <= +cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[55] <= +cp_data[56] <= cp_data.DB_MAX_OUTPUT_PORT_TYPE +cp_data[57] <= av_write.DB_MAX_OUTPUT_PORT_TYPE +cp_data[58] <= av_read.DB_MAX_OUTPUT_PORT_TYPE +cp_data[59] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +cp_data[60] <= +cp_data[61] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[62] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[63] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[64] <= +cp_data[65] <= +cp_data[66] <= +cp_data[67] <= +cp_data[68] <= +cp_data[69] <= +cp_data[70] <= +cp_data[71] <= +cp_data[72] <= +cp_data[73] <= +cp_data[74] <= +cp_data[75] <= +cp_data[76] <= +cp_data[77] <= +cp_data[78] <= +cp_data[79] <= +cp_data[80] <= +cp_data[81] <= +cp_data[82] <= +cp_data[83] <= +cp_data[84] <= +cp_data[85] <= +cp_data[86] <= +cp_data[87] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +cp_data[88] <= +cp_data[89] <= +cp_data[90] <= +cp_data[91] <= +cp_data[92] <= +cp_data[93] <= +cp_data[94] <= +cp_data[95] <= +cp_startofpacket <= +cp_endofpacket <= +cp_ready => av_waitrequest.IN1 +rp_valid => av_writeresponsevalid.DATAB +rp_valid => av_readdatavalid.DATAA +rp_data[0] => av_readdata[0].DATAIN +rp_data[1] => av_readdata[1].DATAIN +rp_data[2] => av_readdata[2].DATAIN +rp_data[3] => av_readdata[3].DATAIN +rp_data[4] => av_readdata[4].DATAIN +rp_data[5] => av_readdata[5].DATAIN +rp_data[6] => av_readdata[6].DATAIN +rp_data[7] => av_readdata[7].DATAIN +rp_data[8] => av_readdata[8].DATAIN +rp_data[9] => av_readdata[9].DATAIN +rp_data[10] => av_readdata[10].DATAIN +rp_data[11] => av_readdata[11].DATAIN +rp_data[12] => av_readdata[12].DATAIN +rp_data[13] => av_readdata[13].DATAIN +rp_data[14] => av_readdata[14].DATAIN +rp_data[15] => av_readdata[15].DATAIN +rp_data[16] => av_readdata[16].DATAIN +rp_data[17] => av_readdata[17].DATAIN +rp_data[18] => av_readdata[18].DATAIN +rp_data[19] => av_readdata[19].DATAIN +rp_data[20] => av_readdata[20].DATAIN +rp_data[21] => av_readdata[21].DATAIN +rp_data[22] => av_readdata[22].DATAIN +rp_data[23] => av_readdata[23].DATAIN +rp_data[24] => av_readdata[24].DATAIN +rp_data[25] => av_readdata[25].DATAIN +rp_data[26] => av_readdata[26].DATAIN +rp_data[27] => av_readdata[27].DATAIN +rp_data[28] => av_readdata[28].DATAIN +rp_data[29] => av_readdata[29].DATAIN +rp_data[30] => av_readdata[30].DATAIN +rp_data[31] => av_readdata[31].DATAIN +rp_data[32] => ~NO_FANOUT~ +rp_data[33] => ~NO_FANOUT~ +rp_data[34] => ~NO_FANOUT~ +rp_data[35] => ~NO_FANOUT~ +rp_data[36] => ~NO_FANOUT~ +rp_data[37] => ~NO_FANOUT~ +rp_data[38] => ~NO_FANOUT~ +rp_data[39] => ~NO_FANOUT~ +rp_data[40] => ~NO_FANOUT~ +rp_data[41] => ~NO_FANOUT~ +rp_data[42] => ~NO_FANOUT~ +rp_data[43] => ~NO_FANOUT~ +rp_data[44] => ~NO_FANOUT~ +rp_data[45] => ~NO_FANOUT~ +rp_data[46] => ~NO_FANOUT~ +rp_data[47] => ~NO_FANOUT~ +rp_data[48] => ~NO_FANOUT~ +rp_data[49] => ~NO_FANOUT~ +rp_data[50] => ~NO_FANOUT~ +rp_data[51] => ~NO_FANOUT~ +rp_data[52] => ~NO_FANOUT~ +rp_data[53] => ~NO_FANOUT~ +rp_data[54] => ~NO_FANOUT~ +rp_data[55] => ~NO_FANOUT~ +rp_data[56] => ~NO_FANOUT~ +rp_data[57] => av_writeresponsevalid.OUTPUTSELECT +rp_data[57] => av_readdatavalid.OUTPUTSELECT +rp_data[58] => ~NO_FANOUT~ +rp_data[59] => ~NO_FANOUT~ +rp_data[60] => ~NO_FANOUT~ +rp_data[61] => ~NO_FANOUT~ +rp_data[62] => ~NO_FANOUT~ +rp_data[63] => ~NO_FANOUT~ +rp_data[64] => ~NO_FANOUT~ +rp_data[65] => ~NO_FANOUT~ +rp_data[66] => ~NO_FANOUT~ +rp_data[67] => ~NO_FANOUT~ +rp_data[68] => ~NO_FANOUT~ +rp_data[69] => ~NO_FANOUT~ +rp_data[70] => ~NO_FANOUT~ +rp_data[71] => ~NO_FANOUT~ +rp_data[72] => ~NO_FANOUT~ +rp_data[73] => ~NO_FANOUT~ +rp_data[74] => ~NO_FANOUT~ +rp_data[75] => ~NO_FANOUT~ +rp_data[76] => ~NO_FANOUT~ +rp_data[77] => ~NO_FANOUT~ +rp_data[78] => ~NO_FANOUT~ +rp_data[79] => ~NO_FANOUT~ +rp_data[80] => ~NO_FANOUT~ +rp_data[81] => ~NO_FANOUT~ +rp_data[82] => ~NO_FANOUT~ +rp_data[83] => ~NO_FANOUT~ +rp_data[84] => ~NO_FANOUT~ +rp_data[85] => ~NO_FANOUT~ +rp_data[86] => ~NO_FANOUT~ +rp_data[87] => ~NO_FANOUT~ +rp_data[88] => ~NO_FANOUT~ +rp_data[89] => ~NO_FANOUT~ +rp_data[90] => ~NO_FANOUT~ +rp_data[91] => ~NO_FANOUT~ +rp_data[92] => ~NO_FANOUT~ +rp_data[93] => ~NO_FANOUT~ +rp_data[94] => ~NO_FANOUT~ +rp_data[95] => ~NO_FANOUT~ +rp_channel[0] => ~NO_FANOUT~ +rp_channel[1] => ~NO_FANOUT~ +rp_channel[2] => ~NO_FANOUT~ +rp_channel[3] => ~NO_FANOUT~ +rp_channel[4] => ~NO_FANOUT~ +rp_channel[5] => ~NO_FANOUT~ +rp_channel[6] => ~NO_FANOUT~ +rp_channel[7] => ~NO_FANOUT~ +rp_channel[8] => ~NO_FANOUT~ +rp_channel[9] => ~NO_FANOUT~ +rp_channel[10] => ~NO_FANOUT~ +rp_channel[11] => ~NO_FANOUT~ +rp_channel[12] => ~NO_FANOUT~ +rp_channel[13] => ~NO_FANOUT~ +rp_channel[14] => ~NO_FANOUT~ +rp_channel[15] => ~NO_FANOUT~ +rp_channel[16] => ~NO_FANOUT~ +rp_channel[17] => ~NO_FANOUT~ +rp_startofpacket => ~NO_FANOUT~ +rp_endofpacket => ~NO_FANOUT~ +rp_ready <= + + +|lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent +clk => hold_waitrequest.CLK +reset => hold_waitrequest.PRESET +av_address[0] => ~NO_FANOUT~ +av_address[1] => ~NO_FANOUT~ +av_address[2] => cp_data[38].DATAIN +av_address[3] => cp_data[39].DATAIN +av_address[4] => cp_data[40].DATAIN +av_address[5] => cp_data[41].DATAIN +av_address[6] => cp_data[42].DATAIN +av_address[7] => cp_data[43].DATAIN +av_address[8] => cp_data[44].DATAIN +av_address[9] => cp_data[45].DATAIN +av_address[10] => cp_data[46].DATAIN +av_address[11] => cp_data[47].DATAIN +av_address[12] => cp_data[48].DATAIN +av_address[13] => cp_data[49].DATAIN +av_address[14] => cp_data[50].DATAIN +av_address[15] => cp_data[51].DATAIN +av_address[16] => cp_data[52].DATAIN +av_address[17] => cp_data[53].DATAIN +av_address[18] => cp_data[54].DATAIN +av_write => cp_data.IN0 +av_write => always1.IN0 +av_write => cp_data[57].DATAIN +av_read => always1.IN1 +av_read => cp_data[58].DATAIN +av_writedata[0] => cp_data[0].DATAIN +av_writedata[1] => cp_data[1].DATAIN +av_writedata[2] => cp_data[2].DATAIN +av_writedata[3] => cp_data[3].DATAIN +av_writedata[4] => cp_data[4].DATAIN +av_writedata[5] => cp_data[5].DATAIN +av_writedata[6] => cp_data[6].DATAIN +av_writedata[7] => cp_data[7].DATAIN +av_writedata[8] => cp_data[8].DATAIN +av_writedata[9] => cp_data[9].DATAIN +av_writedata[10] => cp_data[10].DATAIN +av_writedata[11] => cp_data[11].DATAIN +av_writedata[12] => cp_data[12].DATAIN +av_writedata[13] => cp_data[13].DATAIN +av_writedata[14] => cp_data[14].DATAIN +av_writedata[15] => cp_data[15].DATAIN +av_writedata[16] => cp_data[16].DATAIN +av_writedata[17] => cp_data[17].DATAIN +av_writedata[18] => cp_data[18].DATAIN +av_writedata[19] => cp_data[19].DATAIN +av_writedata[20] => cp_data[20].DATAIN +av_writedata[21] => cp_data[21].DATAIN +av_writedata[22] => cp_data[22].DATAIN +av_writedata[23] => cp_data[23].DATAIN +av_writedata[24] => cp_data[24].DATAIN +av_writedata[25] => cp_data[25].DATAIN +av_writedata[26] => cp_data[26].DATAIN +av_writedata[27] => cp_data[27].DATAIN +av_writedata[28] => cp_data[28].DATAIN +av_writedata[29] => cp_data[29].DATAIN +av_writedata[30] => cp_data[30].DATAIN +av_writedata[31] => cp_data[31].DATAIN +av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= av_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] => cp_data[32].DATAIN +av_byteenable[1] => cp_data[33].DATAIN +av_byteenable[2] => cp_data[34].DATAIN +av_byteenable[3] => cp_data[35].DATAIN +av_burstcount[0] => cp_data[61].DATAIN +av_burstcount[1] => cp_data[62].DATAIN +av_burstcount[2] => cp_data[63].DATAIN +av_debugaccess => cp_data[87].DATAIN +av_lock => cp_data[59].DATAIN +av_response[0] <= +av_response[1] <= +av_writeresponserequest => cp_data.IN1 +av_writeresponsevalid <= av_writeresponsevalid.DB_MAX_OUTPUT_PORT_TYPE +cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE +cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[36] <= +cp_data[37] <= +cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[55] <= +cp_data[56] <= cp_data.DB_MAX_OUTPUT_PORT_TYPE +cp_data[57] <= av_write.DB_MAX_OUTPUT_PORT_TYPE +cp_data[58] <= av_read.DB_MAX_OUTPUT_PORT_TYPE +cp_data[59] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +cp_data[60] <= +cp_data[61] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[62] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[63] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[64] <= +cp_data[65] <= +cp_data[66] <= +cp_data[67] <= +cp_data[68] <= +cp_data[69] <= +cp_data[70] <= +cp_data[71] <= +cp_data[72] <= +cp_data[73] <= +cp_data[74] <= +cp_data[75] <= +cp_data[76] <= +cp_data[77] <= +cp_data[78] <= +cp_data[79] <= +cp_data[80] <= +cp_data[81] <= +cp_data[82] <= +cp_data[83] <= +cp_data[84] <= +cp_data[85] <= +cp_data[86] <= +cp_data[87] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +cp_data[88] <= +cp_data[89] <= +cp_data[90] <= +cp_data[91] <= +cp_data[92] <= +cp_data[93] <= +cp_data[94] <= +cp_data[95] <= +cp_startofpacket <= +cp_endofpacket <= +cp_ready => av_waitrequest.IN1 +rp_valid => av_writeresponsevalid.DATAB +rp_valid => av_readdatavalid.DATAA +rp_data[0] => av_readdata[0].DATAIN +rp_data[1] => av_readdata[1].DATAIN +rp_data[2] => av_readdata[2].DATAIN +rp_data[3] => av_readdata[3].DATAIN +rp_data[4] => av_readdata[4].DATAIN +rp_data[5] => av_readdata[5].DATAIN +rp_data[6] => av_readdata[6].DATAIN +rp_data[7] => av_readdata[7].DATAIN +rp_data[8] => av_readdata[8].DATAIN +rp_data[9] => av_readdata[9].DATAIN +rp_data[10] => av_readdata[10].DATAIN +rp_data[11] => av_readdata[11].DATAIN +rp_data[12] => av_readdata[12].DATAIN +rp_data[13] => av_readdata[13].DATAIN +rp_data[14] => av_readdata[14].DATAIN +rp_data[15] => av_readdata[15].DATAIN +rp_data[16] => av_readdata[16].DATAIN +rp_data[17] => av_readdata[17].DATAIN +rp_data[18] => av_readdata[18].DATAIN +rp_data[19] => av_readdata[19].DATAIN +rp_data[20] => av_readdata[20].DATAIN +rp_data[21] => av_readdata[21].DATAIN +rp_data[22] => av_readdata[22].DATAIN +rp_data[23] => av_readdata[23].DATAIN +rp_data[24] => av_readdata[24].DATAIN +rp_data[25] => av_readdata[25].DATAIN +rp_data[26] => av_readdata[26].DATAIN +rp_data[27] => av_readdata[27].DATAIN +rp_data[28] => av_readdata[28].DATAIN +rp_data[29] => av_readdata[29].DATAIN +rp_data[30] => av_readdata[30].DATAIN +rp_data[31] => av_readdata[31].DATAIN +rp_data[32] => ~NO_FANOUT~ +rp_data[33] => ~NO_FANOUT~ +rp_data[34] => ~NO_FANOUT~ +rp_data[35] => ~NO_FANOUT~ +rp_data[36] => ~NO_FANOUT~ +rp_data[37] => ~NO_FANOUT~ +rp_data[38] => ~NO_FANOUT~ +rp_data[39] => ~NO_FANOUT~ +rp_data[40] => ~NO_FANOUT~ +rp_data[41] => ~NO_FANOUT~ +rp_data[42] => ~NO_FANOUT~ +rp_data[43] => ~NO_FANOUT~ +rp_data[44] => ~NO_FANOUT~ +rp_data[45] => ~NO_FANOUT~ +rp_data[46] => ~NO_FANOUT~ +rp_data[47] => ~NO_FANOUT~ +rp_data[48] => ~NO_FANOUT~ +rp_data[49] => ~NO_FANOUT~ +rp_data[50] => ~NO_FANOUT~ +rp_data[51] => ~NO_FANOUT~ +rp_data[52] => ~NO_FANOUT~ +rp_data[53] => ~NO_FANOUT~ +rp_data[54] => ~NO_FANOUT~ +rp_data[55] => ~NO_FANOUT~ +rp_data[56] => ~NO_FANOUT~ +rp_data[57] => av_writeresponsevalid.OUTPUTSELECT +rp_data[57] => av_readdatavalid.OUTPUTSELECT +rp_data[58] => ~NO_FANOUT~ +rp_data[59] => ~NO_FANOUT~ +rp_data[60] => ~NO_FANOUT~ +rp_data[61] => ~NO_FANOUT~ +rp_data[62] => ~NO_FANOUT~ +rp_data[63] => ~NO_FANOUT~ +rp_data[64] => ~NO_FANOUT~ +rp_data[65] => ~NO_FANOUT~ +rp_data[66] => ~NO_FANOUT~ +rp_data[67] => ~NO_FANOUT~ +rp_data[68] => ~NO_FANOUT~ +rp_data[69] => ~NO_FANOUT~ +rp_data[70] => ~NO_FANOUT~ +rp_data[71] => ~NO_FANOUT~ +rp_data[72] => ~NO_FANOUT~ +rp_data[73] => ~NO_FANOUT~ +rp_data[74] => ~NO_FANOUT~ +rp_data[75] => ~NO_FANOUT~ +rp_data[76] => ~NO_FANOUT~ +rp_data[77] => ~NO_FANOUT~ +rp_data[78] => ~NO_FANOUT~ +rp_data[79] => ~NO_FANOUT~ +rp_data[80] => ~NO_FANOUT~ +rp_data[81] => ~NO_FANOUT~ +rp_data[82] => ~NO_FANOUT~ +rp_data[83] => ~NO_FANOUT~ +rp_data[84] => ~NO_FANOUT~ +rp_data[85] => ~NO_FANOUT~ +rp_data[86] => ~NO_FANOUT~ +rp_data[87] => ~NO_FANOUT~ +rp_data[88] => ~NO_FANOUT~ +rp_data[89] => ~NO_FANOUT~ +rp_data[90] => ~NO_FANOUT~ +rp_data[91] => ~NO_FANOUT~ +rp_data[92] => ~NO_FANOUT~ +rp_data[93] => ~NO_FANOUT~ +rp_data[94] => ~NO_FANOUT~ +rp_data[95] => ~NO_FANOUT~ +rp_channel[0] => ~NO_FANOUT~ +rp_channel[1] => ~NO_FANOUT~ +rp_channel[2] => ~NO_FANOUT~ +rp_channel[3] => ~NO_FANOUT~ +rp_channel[4] => ~NO_FANOUT~ +rp_channel[5] => ~NO_FANOUT~ +rp_channel[6] => ~NO_FANOUT~ +rp_channel[7] => ~NO_FANOUT~ +rp_channel[8] => ~NO_FANOUT~ +rp_channel[9] => ~NO_FANOUT~ +rp_channel[10] => ~NO_FANOUT~ +rp_channel[11] => ~NO_FANOUT~ +rp_channel[12] => ~NO_FANOUT~ +rp_channel[13] => ~NO_FANOUT~ +rp_channel[14] => ~NO_FANOUT~ +rp_channel[15] => ~NO_FANOUT~ +rp_channel[16] => ~NO_FANOUT~ +rp_channel[17] => ~NO_FANOUT~ +rp_startofpacket => ~NO_FANOUT~ +rp_endofpacket => ~NO_FANOUT~ +rp_ready <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.IN0 +m0_debugaccess <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +m0_response[0] => rdata_fifo_src_data[32].DATAIN +m0_response[1] => rdata_fifo_src_data[33].DATAIN +m0_writeresponserequest <= m0_writeresponserequest.DB_MAX_OUTPUT_PORT_TYPE +m0_writeresponsevalid => rdata_fifo_src_valid.IN1 +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= +rf_source_data[89] <= +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= cp_data[93].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[94] <= cp_data[94].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_compressed.IN1 +rf_sink_data[56] => rp_data[56].DATAIN +rf_sink_data[57] => comb.OUTPUTSELECT +rf_sink_data[57] => rp_data[57].DATAIN +rf_sink_data[58] => rp_data.IN0 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[62] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[63] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[64] => rf_sink_burstwrap[0].IN1 +rf_sink_data[65] => rf_sink_burstwrap[1].IN1 +rf_sink_data[66] => rf_sink_burstwrap[2].IN1 +rf_sink_data[67] => rf_sink_burstsize[0].IN1 +rf_sink_data[68] => rf_sink_burstsize[1].IN1 +rf_sink_data[69] => rf_sink_burstsize[2].IN1 +rf_sink_data[70] => rp_data[70].DATAIN +rf_sink_data[71] => rp_data[71].DATAIN +rf_sink_data[72] => rp_data[72].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[81].DATAIN +rf_sink_data[77] => rp_data[82].DATAIN +rf_sink_data[78] => rp_data[83].DATAIN +rf_sink_data[79] => rp_data[84].DATAIN +rf_sink_data[80] => rp_data[85].DATAIN +rf_sink_data[81] => rp_data[76].DATAIN +rf_sink_data[82] => rp_data[77].DATAIN +rf_sink_data[83] => rp_data[78].DATAIN +rf_sink_data[84] => rp_data[79].DATAIN +rf_sink_data[85] => rp_data[80].DATAIN +rf_sink_data[86] => rp_data[86].DATAIN +rf_sink_data[87] => rp_data[87].DATAIN +rf_sink_data[88] => rp_data[88].DATAIN +rf_sink_data[89] => rp_data[89].DATAIN +rf_sink_data[90] => rp_data[90].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => ~NO_FANOUT~ +rf_sink_data[95] => ~NO_FANOUT~ +rf_sink_data[96] => rdata_fifo_sink_ready.IN0 +rf_sink_data[96] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[32] <= m0_response[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[33] <= m0_response[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= rdata_fifo_src_valid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_data[32] => rp_data[94].DATAIN +rdata_fifo_sink_data[33] => rp_data[95].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => local_compressed_read.IN1 +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_writeresponserequest.IN1 +cp_data[56] => comb.IN1 +cp_data[57] => local_write.IN1 +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => local_read.IN1 +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => local_lock.IN1 +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => m0_burstcount.DATAA +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => m0_burstcount.DATAA +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => m0_burstcount.DATAA +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[87] => m0_debugaccess.DATAIN +cp_data[88] => ~NO_FANOUT~ +cp_data[89] => ~NO_FANOUT~ +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[93] => rf_source_data[93].DATAIN +cp_data[94] => rf_source_data[94].DATAIN +cp_data[95] => rf_source_data[95].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_channel[11] => ~NO_FANOUT~ +cp_channel[12] => ~NO_FANOUT~ +cp_channel[13] => ~NO_FANOUT~ +cp_channel[14] => ~NO_FANOUT~ +cp_channel[15] => ~NO_FANOUT~ +cp_channel[16] => ~NO_FANOUT~ +cp_channel[17] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[56] <= rf_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rp_data[57] <= rf_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rp_data[58] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[63] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[64] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[65] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[66] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[67] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[70] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rdata_fifo_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rdata_fifo_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_read => csr_readdata[0]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|lights|nios_system:NiosII|nios_system_addr_router:addr_router +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[47] => Equal0.IN1 +sink_data[48] => src_data[48].DATAIN +sink_data[48] => Equal0.IN7 +sink_data[49] => src_data[49].DATAIN +sink_data[49] => Equal0.IN6 +sink_data[50] => src_data[50].DATAIN +sink_data[50] => Equal0.IN5 +sink_data[51] => src_data[51].DATAIN +sink_data[51] => Equal0.IN4 +sink_data[52] => src_data[52].DATAIN +sink_data[52] => Equal0.IN3 +sink_data[53] => src_data[53].DATAIN +sink_data[53] => Equal0.IN2 +sink_data[54] => src_data[54].DATAIN +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => Equal0.IN0 +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => ~NO_FANOUT~ +sink_data[82] => ~NO_FANOUT~ +sink_data[83] => ~NO_FANOUT~ +sink_data[84] => ~NO_FANOUT~ +sink_data[85] => ~NO_FANOUT~ +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[39] => Equal16.IN15 +sink_data[40] => src_data[40].DATAIN +sink_data[40] => Equal1.IN2 +sink_data[40] => Equal2.IN14 +sink_data[40] => Equal3.IN3 +sink_data[40] => Equal4.IN14 +sink_data[40] => Equal5.IN3 +sink_data[40] => Equal6.IN14 +sink_data[40] => Equal7.IN4 +sink_data[40] => Equal8.IN14 +sink_data[40] => Equal9.IN3 +sink_data[40] => Equal10.IN14 +sink_data[40] => Equal11.IN4 +sink_data[40] => Equal12.IN14 +sink_data[40] => Equal13.IN4 +sink_data[40] => Equal14.IN14 +sink_data[40] => Equal15.IN5 +sink_data[40] => Equal16.IN14 +sink_data[41] => src_data[41].DATAIN +sink_data[41] => Equal1.IN14 +sink_data[41] => Equal2.IN2 +sink_data[41] => Equal3.IN2 +sink_data[41] => Equal4.IN13 +sink_data[41] => Equal5.IN14 +sink_data[41] => Equal6.IN3 +sink_data[41] => Equal7.IN3 +sink_data[41] => Equal8.IN13 +sink_data[41] => Equal9.IN14 +sink_data[41] => Equal10.IN3 +sink_data[41] => Equal11.IN3 +sink_data[41] => Equal12.IN13 +sink_data[41] => Equal13.IN14 +sink_data[41] => Equal14.IN4 +sink_data[41] => Equal15.IN4 +sink_data[41] => Equal16.IN13 +sink_data[42] => src_data[42].DATAIN +sink_data[42] => Equal1.IN13 +sink_data[42] => Equal2.IN13 +sink_data[42] => Equal3.IN14 +sink_data[42] => Equal4.IN2 +sink_data[42] => Equal5.IN2 +sink_data[42] => Equal6.IN2 +sink_data[42] => Equal7.IN2 +sink_data[42] => Equal8.IN12 +sink_data[42] => Equal9.IN13 +sink_data[42] => Equal10.IN13 +sink_data[42] => Equal11.IN14 +sink_data[42] => Equal12.IN3 +sink_data[42] => Equal13.IN3 +sink_data[42] => Equal14.IN3 +sink_data[42] => Equal15.IN3 +sink_data[42] => Equal16.IN12 +sink_data[43] => src_data[43].DATAIN +sink_data[43] => Equal1.IN12 +sink_data[43] => Equal2.IN12 +sink_data[43] => Equal3.IN13 +sink_data[43] => Equal4.IN12 +sink_data[43] => Equal5.IN13 +sink_data[43] => Equal6.IN13 +sink_data[43] => Equal7.IN14 +sink_data[43] => Equal8.IN2 +sink_data[43] => Equal9.IN2 +sink_data[43] => Equal10.IN2 +sink_data[43] => Equal11.IN2 +sink_data[43] => Equal12.IN2 +sink_data[43] => Equal13.IN2 +sink_data[43] => Equal14.IN2 +sink_data[43] => Equal15.IN2 +sink_data[43] => Equal16.IN11 +sink_data[44] => src_data[44].DATAIN +sink_data[44] => Equal1.IN11 +sink_data[44] => Equal2.IN11 +sink_data[44] => Equal3.IN12 +sink_data[44] => Equal4.IN11 +sink_data[44] => Equal5.IN12 +sink_data[44] => Equal6.IN12 +sink_data[44] => Equal7.IN13 +sink_data[44] => Equal8.IN11 +sink_data[44] => Equal9.IN12 +sink_data[44] => Equal10.IN12 +sink_data[44] => Equal11.IN13 +sink_data[44] => Equal12.IN12 +sink_data[44] => Equal13.IN13 +sink_data[44] => Equal14.IN13 +sink_data[44] => Equal15.IN14 +sink_data[44] => Equal16.IN2 +sink_data[45] => src_data[45].DATAIN +sink_data[45] => Equal1.IN10 +sink_data[45] => Equal2.IN10 +sink_data[45] => Equal3.IN11 +sink_data[45] => Equal4.IN10 +sink_data[45] => Equal5.IN11 +sink_data[45] => Equal6.IN11 +sink_data[45] => Equal7.IN12 +sink_data[45] => Equal8.IN10 +sink_data[45] => Equal9.IN11 +sink_data[45] => Equal10.IN11 +sink_data[45] => Equal11.IN12 +sink_data[45] => Equal12.IN11 +sink_data[45] => Equal13.IN12 +sink_data[45] => Equal14.IN12 +sink_data[45] => Equal15.IN13 +sink_data[45] => Equal16.IN10 +sink_data[46] => src_data[46].DATAIN +sink_data[46] => Equal1.IN9 +sink_data[46] => Equal2.IN9 +sink_data[46] => Equal3.IN10 +sink_data[46] => Equal4.IN9 +sink_data[46] => Equal5.IN10 +sink_data[46] => Equal6.IN10 +sink_data[46] => Equal7.IN11 +sink_data[46] => Equal8.IN9 +sink_data[46] => Equal9.IN10 +sink_data[46] => Equal10.IN10 +sink_data[46] => Equal11.IN11 +sink_data[46] => Equal12.IN10 +sink_data[46] => Equal13.IN11 +sink_data[46] => Equal14.IN11 +sink_data[46] => Equal15.IN12 +sink_data[46] => Equal16.IN9 +sink_data[47] => src_data[47].DATAIN +sink_data[47] => Equal0.IN1 +sink_data[47] => Equal1.IN8 +sink_data[47] => Equal2.IN8 +sink_data[47] => Equal3.IN9 +sink_data[47] => Equal4.IN8 +sink_data[47] => Equal5.IN9 +sink_data[47] => Equal6.IN9 +sink_data[47] => Equal7.IN10 +sink_data[47] => Equal8.IN8 +sink_data[47] => Equal9.IN9 +sink_data[47] => Equal10.IN9 +sink_data[47] => Equal11.IN10 +sink_data[47] => Equal12.IN9 +sink_data[47] => Equal13.IN10 +sink_data[47] => Equal14.IN10 +sink_data[47] => Equal15.IN11 +sink_data[47] => Equal16.IN8 +sink_data[48] => src_data[48].DATAIN +sink_data[48] => Equal0.IN7 +sink_data[48] => Equal1.IN1 +sink_data[48] => Equal2.IN1 +sink_data[48] => Equal3.IN1 +sink_data[48] => Equal4.IN1 +sink_data[48] => Equal5.IN1 +sink_data[48] => Equal6.IN1 +sink_data[48] => Equal7.IN1 +sink_data[48] => Equal8.IN1 +sink_data[48] => Equal9.IN1 +sink_data[48] => Equal10.IN1 +sink_data[48] => Equal11.IN1 +sink_data[48] => Equal12.IN1 +sink_data[48] => Equal13.IN1 +sink_data[48] => Equal14.IN1 +sink_data[48] => Equal15.IN1 +sink_data[48] => Equal16.IN1 +sink_data[49] => src_data[49].DATAIN +sink_data[49] => Equal0.IN6 +sink_data[49] => Equal1.IN7 +sink_data[49] => Equal2.IN7 +sink_data[49] => Equal3.IN8 +sink_data[49] => Equal4.IN7 +sink_data[49] => Equal5.IN8 +sink_data[49] => Equal6.IN8 +sink_data[49] => Equal7.IN9 +sink_data[49] => Equal8.IN7 +sink_data[49] => Equal9.IN8 +sink_data[49] => Equal10.IN8 +sink_data[49] => Equal11.IN9 +sink_data[49] => Equal12.IN8 +sink_data[49] => Equal13.IN9 +sink_data[49] => Equal14.IN9 +sink_data[49] => Equal15.IN10 +sink_data[49] => Equal16.IN7 +sink_data[50] => src_data[50].DATAIN +sink_data[50] => Equal0.IN5 +sink_data[50] => Equal1.IN6 +sink_data[50] => Equal2.IN6 +sink_data[50] => Equal3.IN7 +sink_data[50] => Equal4.IN6 +sink_data[50] => Equal5.IN7 +sink_data[50] => Equal6.IN7 +sink_data[50] => Equal7.IN8 +sink_data[50] => Equal8.IN6 +sink_data[50] => Equal9.IN7 +sink_data[50] => Equal10.IN7 +sink_data[50] => Equal11.IN8 +sink_data[50] => Equal12.IN7 +sink_data[50] => Equal13.IN8 +sink_data[50] => Equal14.IN8 +sink_data[50] => Equal15.IN9 +sink_data[50] => Equal16.IN6 +sink_data[51] => src_data[51].DATAIN +sink_data[51] => Equal0.IN4 +sink_data[51] => Equal1.IN5 +sink_data[51] => Equal2.IN5 +sink_data[51] => Equal3.IN6 +sink_data[51] => Equal4.IN5 +sink_data[51] => Equal5.IN6 +sink_data[51] => Equal6.IN6 +sink_data[51] => Equal7.IN7 +sink_data[51] => Equal8.IN5 +sink_data[51] => Equal9.IN6 +sink_data[51] => Equal10.IN6 +sink_data[51] => Equal11.IN7 +sink_data[51] => Equal12.IN6 +sink_data[51] => Equal13.IN7 +sink_data[51] => Equal14.IN7 +sink_data[51] => Equal15.IN8 +sink_data[51] => Equal16.IN5 +sink_data[52] => src_data[52].DATAIN +sink_data[52] => Equal0.IN3 +sink_data[52] => Equal1.IN4 +sink_data[52] => Equal2.IN4 +sink_data[52] => Equal3.IN5 +sink_data[52] => Equal4.IN4 +sink_data[52] => Equal5.IN5 +sink_data[52] => Equal6.IN5 +sink_data[52] => Equal7.IN6 +sink_data[52] => Equal8.IN4 +sink_data[52] => Equal9.IN5 +sink_data[52] => Equal10.IN5 +sink_data[52] => Equal11.IN6 +sink_data[52] => Equal12.IN5 +sink_data[52] => Equal13.IN6 +sink_data[52] => Equal14.IN6 +sink_data[52] => Equal15.IN7 +sink_data[52] => Equal16.IN4 +sink_data[53] => src_data[53].DATAIN +sink_data[53] => Equal0.IN2 +sink_data[53] => Equal1.IN3 +sink_data[53] => Equal2.IN3 +sink_data[53] => Equal3.IN4 +sink_data[53] => Equal4.IN3 +sink_data[53] => Equal5.IN4 +sink_data[53] => Equal6.IN4 +sink_data[53] => Equal7.IN5 +sink_data[53] => Equal8.IN3 +sink_data[53] => Equal9.IN4 +sink_data[53] => Equal10.IN4 +sink_data[53] => Equal11.IN5 +sink_data[53] => Equal12.IN4 +sink_data[53] => Equal13.IN5 +sink_data[53] => Equal14.IN5 +sink_data[53] => Equal15.IN6 +sink_data[53] => Equal16.IN3 +sink_data[54] => src_data[54].DATAIN +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_channel.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => src_data.OUTPUTSELECT +sink_data[54] => Equal0.IN0 +sink_data[54] => Equal1.IN0 +sink_data[54] => Equal2.IN0 +sink_data[54] => Equal3.IN0 +sink_data[54] => Equal4.IN0 +sink_data[54] => Equal5.IN0 +sink_data[54] => Equal6.IN0 +sink_data[54] => Equal7.IN0 +sink_data[54] => Equal8.IN0 +sink_data[54] => Equal9.IN0 +sink_data[54] => Equal10.IN0 +sink_data[54] => Equal11.IN0 +sink_data[54] => Equal12.IN0 +sink_data[54] => Equal13.IN0 +sink_data[54] => Equal14.IN0 +sink_data[54] => Equal15.IN0 +sink_data[54] => Equal16.IN0 +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => ~NO_FANOUT~ +sink_data[82] => ~NO_FANOUT~ +sink_data[83] => ~NO_FANOUT~ +sink_data[84] => ~NO_FANOUT~ +sink_data[85] => ~NO_FANOUT~ +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router:id_router +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN0 +sink_data[81] => Equal1.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN31 +sink_data[82] => Equal1.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN30 +sink_data[83] => Equal1.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN29 +sink_data[84] => Equal1.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN28 +sink_data[85] => Equal1.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router:id_router_001 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN0 +sink_data[81] => Equal1.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN31 +sink_data[82] => Equal1.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN30 +sink_data[83] => Equal1.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN29 +sink_data[84] => Equal1.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN28 +sink_data[85] => Equal1.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_002 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_003 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_004 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_005 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_006 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_007 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_008 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_009 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_010 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_011 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_012 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_013 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_014 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_015 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_016 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_017 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[81] => Equal0.IN31 +sink_data[82] => src_data[82].DATAIN +sink_data[82] => Equal0.IN30 +sink_data[83] => src_data[83].DATAIN +sink_data[83] => Equal0.IN29 +sink_data[84] => src_data[84].DATAIN +sink_data[84] => Equal0.IN28 +sink_data[85] => src_data[85].DATAIN +sink_data[85] => Equal0.IN27 +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[88] => src_data[88].DATAIN +sink_data[89] => src_data[89].DATAIN +sink_data[90] => src_data[90].DATAIN +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|lights|nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_destination_id[4] <= +default_wr_channel[0] <= +default_wr_channel[1] <= +default_wr_channel[2] <= +default_wr_channel[3] <= +default_wr_channel[4] <= +default_wr_channel[5] <= +default_wr_channel[6] <= +default_wr_channel[7] <= +default_wr_channel[8] <= +default_wr_channel[9] <= +default_wr_channel[10] <= +default_wr_channel[11] <= +default_wr_channel[12] <= +default_wr_channel[13] <= +default_wr_channel[14] <= +default_wr_channel[15] <= +default_wr_channel[16] <= +default_wr_channel[17] <= +default_rd_channel[0] <= +default_rd_channel[1] <= +default_rd_channel[2] <= +default_rd_channel[3] <= +default_rd_channel[4] <= +default_rd_channel[5] <= +default_rd_channel[6] <= +default_rd_channel[7] <= +default_rd_channel[8] <= +default_rd_channel[9] <= +default_rd_channel[10] <= +default_rd_channel[11] <= +default_rd_channel[12] <= +default_rd_channel[13] <= +default_rd_channel[14] <= +default_rd_channel[15] <= +default_rd_channel[16] <= +default_rd_channel[17] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= +default_src_channel[11] <= +default_src_channel[12] <= +default_src_channel[13] <= +default_src_channel[14] <= +default_src_channel[15] <= +default_src_channel[16] <= +default_src_channel[17] <= + + +|lights|nios_system:NiosII|altera_reset_controller:rst_controller +reset_in0 => merged_reset.IN0 +reset_in1 => merged_reset.IN1 +reset_in2 => merged_reset.IN1 +reset_in3 => merged_reset.IN1 +reset_in4 => merged_reset.IN1 +reset_in5 => merged_reset.IN1 +reset_in6 => merged_reset.IN1 +reset_in7 => merged_reset.IN1 +reset_in8 => merged_reset.IN1 +reset_in9 => merged_reset.IN1 +reset_in10 => merged_reset.IN1 +reset_in11 => merged_reset.IN1 +reset_in12 => merged_reset.IN1 +reset_in13 => merged_reset.IN1 +reset_in14 => merged_reset.IN1 +reset_in15 => merged_reset.IN1 +clk => clk.IN1 +reset_out <= r_sync_rst.DB_MAX_OUTPUT_PORT_TYPE +reset_req <= r_early_rst.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 +reset_in => altera_reset_synchronizer_int_chain_out.PRESET +reset_in => altera_reset_synchronizer_int_chain[0].PRESET +reset_in => altera_reset_synchronizer_int_chain[1].PRESET +clk => altera_reset_synchronizer_int_chain_out.CLK +clk => altera_reset_synchronizer_int_chain[0].CLK +clk => altera_reset_synchronizer_int_chain[1].CLK +reset_out <= altera_reset_synchronizer_int_chain_out.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux +sink_valid[0] => src0_valid.IN0 +sink_valid[0] => src1_valid.IN0 +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src1_channel[0].DATAIN +sink_channel[2] => src0_channel[0].DATAIN +sink_channel[3] => src1_channel[1].DATAIN +sink_channel[3] => src0_channel[1].DATAIN +sink_channel[4] => src1_channel[2].DATAIN +sink_channel[4] => src0_channel[2].DATAIN +sink_channel[5] => src1_channel[3].DATAIN +sink_channel[5] => src0_channel[3].DATAIN +sink_channel[6] => src1_channel[4].DATAIN +sink_channel[6] => src0_channel[4].DATAIN +sink_channel[7] => src1_channel[5].DATAIN +sink_channel[7] => src0_channel[5].DATAIN +sink_channel[8] => src1_channel[6].DATAIN +sink_channel[8] => src0_channel[6].DATAIN +sink_channel[9] => src1_channel[7].DATAIN +sink_channel[9] => src0_channel[7].DATAIN +sink_channel[10] => src1_channel[8].DATAIN +sink_channel[10] => src0_channel[8].DATAIN +sink_channel[11] => src1_channel[9].DATAIN +sink_channel[11] => src0_channel[9].DATAIN +sink_channel[12] => src1_channel[10].DATAIN +sink_channel[12] => src0_channel[10].DATAIN +sink_channel[13] => src1_channel[11].DATAIN +sink_channel[13] => src0_channel[11].DATAIN +sink_channel[14] => src1_channel[12].DATAIN +sink_channel[14] => src0_channel[12].DATAIN +sink_channel[15] => src1_channel[13].DATAIN +sink_channel[15] => src0_channel[13].DATAIN +sink_channel[16] => src1_channel[14].DATAIN +sink_channel[16] => src0_channel[14].DATAIN +sink_channel[17] => src1_channel[15].DATAIN +sink_channel[17] => src0_channel[15].DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[16] <= +src1_channel[17] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 +sink_valid[0] => src0_valid.IN0 +sink_valid[0] => src1_valid.IN0 +sink_valid[0] => src2_valid.IN0 +sink_valid[0] => src3_valid.IN0 +sink_valid[0] => src4_valid.IN0 +sink_valid[0] => src5_valid.IN0 +sink_valid[0] => src6_valid.IN0 +sink_valid[0] => src7_valid.IN0 +sink_valid[0] => src8_valid.IN0 +sink_valid[0] => src9_valid.IN0 +sink_valid[0] => src10_valid.IN0 +sink_valid[0] => src11_valid.IN0 +sink_valid[0] => src12_valid.IN0 +sink_valid[0] => src13_valid.IN0 +sink_valid[0] => src14_valid.IN0 +sink_valid[0] => src15_valid.IN0 +sink_valid[0] => src16_valid.IN0 +sink_valid[0] => src17_valid.IN0 +sink_data[0] => src17_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src2_data[0].DATAIN +sink_data[0] => src3_data[0].DATAIN +sink_data[0] => src4_data[0].DATAIN +sink_data[0] => src5_data[0].DATAIN +sink_data[0] => src6_data[0].DATAIN +sink_data[0] => src7_data[0].DATAIN +sink_data[0] => src8_data[0].DATAIN +sink_data[0] => src9_data[0].DATAIN +sink_data[0] => src10_data[0].DATAIN +sink_data[0] => src11_data[0].DATAIN +sink_data[0] => src12_data[0].DATAIN +sink_data[0] => src13_data[0].DATAIN +sink_data[0] => src14_data[0].DATAIN +sink_data[0] => src15_data[0].DATAIN +sink_data[0] => src16_data[0].DATAIN +sink_data[1] => src17_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src2_data[1].DATAIN +sink_data[1] => src3_data[1].DATAIN +sink_data[1] => src4_data[1].DATAIN +sink_data[1] => src5_data[1].DATAIN +sink_data[1] => src6_data[1].DATAIN +sink_data[1] => src7_data[1].DATAIN +sink_data[1] => src8_data[1].DATAIN +sink_data[1] => src9_data[1].DATAIN +sink_data[1] => src10_data[1].DATAIN +sink_data[1] => src11_data[1].DATAIN +sink_data[1] => src12_data[1].DATAIN +sink_data[1] => src13_data[1].DATAIN +sink_data[1] => src14_data[1].DATAIN +sink_data[1] => src15_data[1].DATAIN +sink_data[1] => src16_data[1].DATAIN +sink_data[2] => src17_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src2_data[2].DATAIN +sink_data[2] => src3_data[2].DATAIN +sink_data[2] => src4_data[2].DATAIN +sink_data[2] => src5_data[2].DATAIN +sink_data[2] => src6_data[2].DATAIN +sink_data[2] => src7_data[2].DATAIN +sink_data[2] => src8_data[2].DATAIN +sink_data[2] => src9_data[2].DATAIN +sink_data[2] => src10_data[2].DATAIN +sink_data[2] => src11_data[2].DATAIN +sink_data[2] => src12_data[2].DATAIN +sink_data[2] => src13_data[2].DATAIN +sink_data[2] => src14_data[2].DATAIN +sink_data[2] => src15_data[2].DATAIN +sink_data[2] => src16_data[2].DATAIN +sink_data[3] => src17_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src2_data[3].DATAIN +sink_data[3] => src3_data[3].DATAIN +sink_data[3] => src4_data[3].DATAIN +sink_data[3] => src5_data[3].DATAIN +sink_data[3] => src6_data[3].DATAIN +sink_data[3] => src7_data[3].DATAIN +sink_data[3] => src8_data[3].DATAIN +sink_data[3] => src9_data[3].DATAIN +sink_data[3] => src10_data[3].DATAIN +sink_data[3] => src11_data[3].DATAIN +sink_data[3] => src12_data[3].DATAIN +sink_data[3] => src13_data[3].DATAIN +sink_data[3] => src14_data[3].DATAIN +sink_data[3] => src15_data[3].DATAIN +sink_data[3] => src16_data[3].DATAIN +sink_data[4] => src17_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src2_data[4].DATAIN +sink_data[4] => src3_data[4].DATAIN +sink_data[4] => src4_data[4].DATAIN +sink_data[4] => src5_data[4].DATAIN +sink_data[4] => src6_data[4].DATAIN +sink_data[4] => src7_data[4].DATAIN +sink_data[4] => src8_data[4].DATAIN +sink_data[4] => src9_data[4].DATAIN +sink_data[4] => src10_data[4].DATAIN +sink_data[4] => src11_data[4].DATAIN +sink_data[4] => src12_data[4].DATAIN +sink_data[4] => src13_data[4].DATAIN +sink_data[4] => src14_data[4].DATAIN +sink_data[4] => src15_data[4].DATAIN +sink_data[4] => src16_data[4].DATAIN +sink_data[5] => src17_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src2_data[5].DATAIN +sink_data[5] => src3_data[5].DATAIN +sink_data[5] => src4_data[5].DATAIN +sink_data[5] => src5_data[5].DATAIN +sink_data[5] => src6_data[5].DATAIN +sink_data[5] => src7_data[5].DATAIN +sink_data[5] => src8_data[5].DATAIN +sink_data[5] => src9_data[5].DATAIN +sink_data[5] => src10_data[5].DATAIN +sink_data[5] => src11_data[5].DATAIN +sink_data[5] => src12_data[5].DATAIN +sink_data[5] => src13_data[5].DATAIN +sink_data[5] => src14_data[5].DATAIN +sink_data[5] => src15_data[5].DATAIN +sink_data[5] => src16_data[5].DATAIN +sink_data[6] => src17_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src2_data[6].DATAIN +sink_data[6] => src3_data[6].DATAIN +sink_data[6] => src4_data[6].DATAIN +sink_data[6] => src5_data[6].DATAIN +sink_data[6] => src6_data[6].DATAIN +sink_data[6] => src7_data[6].DATAIN +sink_data[6] => src8_data[6].DATAIN +sink_data[6] => src9_data[6].DATAIN +sink_data[6] => src10_data[6].DATAIN +sink_data[6] => src11_data[6].DATAIN +sink_data[6] => src12_data[6].DATAIN +sink_data[6] => src13_data[6].DATAIN +sink_data[6] => src14_data[6].DATAIN +sink_data[6] => src15_data[6].DATAIN +sink_data[6] => src16_data[6].DATAIN +sink_data[7] => src17_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src2_data[7].DATAIN +sink_data[7] => src3_data[7].DATAIN +sink_data[7] => src4_data[7].DATAIN +sink_data[7] => src5_data[7].DATAIN +sink_data[7] => src6_data[7].DATAIN +sink_data[7] => src7_data[7].DATAIN +sink_data[7] => src8_data[7].DATAIN +sink_data[7] => src9_data[7].DATAIN +sink_data[7] => src10_data[7].DATAIN +sink_data[7] => src11_data[7].DATAIN +sink_data[7] => src12_data[7].DATAIN +sink_data[7] => src13_data[7].DATAIN +sink_data[7] => src14_data[7].DATAIN +sink_data[7] => src15_data[7].DATAIN +sink_data[7] => src16_data[7].DATAIN +sink_data[8] => src17_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src2_data[8].DATAIN +sink_data[8] => src3_data[8].DATAIN +sink_data[8] => src4_data[8].DATAIN +sink_data[8] => src5_data[8].DATAIN +sink_data[8] => src6_data[8].DATAIN +sink_data[8] => src7_data[8].DATAIN +sink_data[8] => src8_data[8].DATAIN +sink_data[8] => src9_data[8].DATAIN +sink_data[8] => src10_data[8].DATAIN +sink_data[8] => src11_data[8].DATAIN +sink_data[8] => src12_data[8].DATAIN +sink_data[8] => src13_data[8].DATAIN +sink_data[8] => src14_data[8].DATAIN +sink_data[8] => src15_data[8].DATAIN +sink_data[8] => src16_data[8].DATAIN +sink_data[9] => src17_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src2_data[9].DATAIN +sink_data[9] => src3_data[9].DATAIN +sink_data[9] => src4_data[9].DATAIN +sink_data[9] => src5_data[9].DATAIN +sink_data[9] => src6_data[9].DATAIN +sink_data[9] => src7_data[9].DATAIN +sink_data[9] => src8_data[9].DATAIN +sink_data[9] => src9_data[9].DATAIN +sink_data[9] => src10_data[9].DATAIN +sink_data[9] => src11_data[9].DATAIN +sink_data[9] => src12_data[9].DATAIN +sink_data[9] => src13_data[9].DATAIN +sink_data[9] => src14_data[9].DATAIN +sink_data[9] => src15_data[9].DATAIN +sink_data[9] => src16_data[9].DATAIN +sink_data[10] => src17_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src2_data[10].DATAIN +sink_data[10] => src3_data[10].DATAIN +sink_data[10] => src4_data[10].DATAIN +sink_data[10] => src5_data[10].DATAIN +sink_data[10] => src6_data[10].DATAIN +sink_data[10] => src7_data[10].DATAIN +sink_data[10] => src8_data[10].DATAIN +sink_data[10] => src9_data[10].DATAIN +sink_data[10] => src10_data[10].DATAIN +sink_data[10] => src11_data[10].DATAIN +sink_data[10] => src12_data[10].DATAIN +sink_data[10] => src13_data[10].DATAIN +sink_data[10] => src14_data[10].DATAIN +sink_data[10] => src15_data[10].DATAIN +sink_data[10] => src16_data[10].DATAIN +sink_data[11] => src17_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src2_data[11].DATAIN +sink_data[11] => src3_data[11].DATAIN +sink_data[11] => src4_data[11].DATAIN +sink_data[11] => src5_data[11].DATAIN +sink_data[11] => src6_data[11].DATAIN +sink_data[11] => src7_data[11].DATAIN +sink_data[11] => src8_data[11].DATAIN +sink_data[11] => src9_data[11].DATAIN +sink_data[11] => src10_data[11].DATAIN +sink_data[11] => src11_data[11].DATAIN +sink_data[11] => src12_data[11].DATAIN +sink_data[11] => src13_data[11].DATAIN +sink_data[11] => src14_data[11].DATAIN +sink_data[11] => src15_data[11].DATAIN +sink_data[11] => src16_data[11].DATAIN +sink_data[12] => src17_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src2_data[12].DATAIN +sink_data[12] => src3_data[12].DATAIN +sink_data[12] => src4_data[12].DATAIN +sink_data[12] => src5_data[12].DATAIN +sink_data[12] => src6_data[12].DATAIN +sink_data[12] => src7_data[12].DATAIN +sink_data[12] => src8_data[12].DATAIN +sink_data[12] => src9_data[12].DATAIN +sink_data[12] => src10_data[12].DATAIN +sink_data[12] => src11_data[12].DATAIN +sink_data[12] => src12_data[12].DATAIN +sink_data[12] => src13_data[12].DATAIN +sink_data[12] => src14_data[12].DATAIN +sink_data[12] => src15_data[12].DATAIN +sink_data[12] => src16_data[12].DATAIN +sink_data[13] => src17_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src2_data[13].DATAIN +sink_data[13] => src3_data[13].DATAIN +sink_data[13] => src4_data[13].DATAIN +sink_data[13] => src5_data[13].DATAIN +sink_data[13] => src6_data[13].DATAIN +sink_data[13] => src7_data[13].DATAIN +sink_data[13] => src8_data[13].DATAIN +sink_data[13] => src9_data[13].DATAIN +sink_data[13] => src10_data[13].DATAIN +sink_data[13] => src11_data[13].DATAIN +sink_data[13] => src12_data[13].DATAIN +sink_data[13] => src13_data[13].DATAIN +sink_data[13] => src14_data[13].DATAIN +sink_data[13] => src15_data[13].DATAIN +sink_data[13] => src16_data[13].DATAIN +sink_data[14] => src17_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src2_data[14].DATAIN +sink_data[14] => src3_data[14].DATAIN +sink_data[14] => src4_data[14].DATAIN +sink_data[14] => src5_data[14].DATAIN +sink_data[14] => src6_data[14].DATAIN +sink_data[14] => src7_data[14].DATAIN +sink_data[14] => src8_data[14].DATAIN +sink_data[14] => src9_data[14].DATAIN +sink_data[14] => src10_data[14].DATAIN +sink_data[14] => src11_data[14].DATAIN +sink_data[14] => src12_data[14].DATAIN +sink_data[14] => src13_data[14].DATAIN +sink_data[14] => src14_data[14].DATAIN +sink_data[14] => src15_data[14].DATAIN +sink_data[14] => src16_data[14].DATAIN +sink_data[15] => src17_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src2_data[15].DATAIN +sink_data[15] => src3_data[15].DATAIN +sink_data[15] => src4_data[15].DATAIN +sink_data[15] => src5_data[15].DATAIN +sink_data[15] => src6_data[15].DATAIN +sink_data[15] => src7_data[15].DATAIN +sink_data[15] => src8_data[15].DATAIN +sink_data[15] => src9_data[15].DATAIN +sink_data[15] => src10_data[15].DATAIN +sink_data[15] => src11_data[15].DATAIN +sink_data[15] => src12_data[15].DATAIN +sink_data[15] => src13_data[15].DATAIN +sink_data[15] => src14_data[15].DATAIN +sink_data[15] => src15_data[15].DATAIN +sink_data[15] => src16_data[15].DATAIN +sink_data[16] => src17_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src2_data[16].DATAIN +sink_data[16] => src3_data[16].DATAIN +sink_data[16] => src4_data[16].DATAIN +sink_data[16] => src5_data[16].DATAIN +sink_data[16] => src6_data[16].DATAIN +sink_data[16] => src7_data[16].DATAIN +sink_data[16] => src8_data[16].DATAIN +sink_data[16] => src9_data[16].DATAIN +sink_data[16] => src10_data[16].DATAIN +sink_data[16] => src11_data[16].DATAIN +sink_data[16] => src12_data[16].DATAIN +sink_data[16] => src13_data[16].DATAIN +sink_data[16] => src14_data[16].DATAIN +sink_data[16] => src15_data[16].DATAIN +sink_data[16] => src16_data[16].DATAIN +sink_data[17] => src17_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src2_data[17].DATAIN +sink_data[17] => src3_data[17].DATAIN +sink_data[17] => src4_data[17].DATAIN +sink_data[17] => src5_data[17].DATAIN +sink_data[17] => src6_data[17].DATAIN +sink_data[17] => src7_data[17].DATAIN +sink_data[17] => src8_data[17].DATAIN +sink_data[17] => src9_data[17].DATAIN +sink_data[17] => src10_data[17].DATAIN +sink_data[17] => src11_data[17].DATAIN +sink_data[17] => src12_data[17].DATAIN +sink_data[17] => src13_data[17].DATAIN +sink_data[17] => src14_data[17].DATAIN +sink_data[17] => src15_data[17].DATAIN +sink_data[17] => src16_data[17].DATAIN +sink_data[18] => src17_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src2_data[18].DATAIN +sink_data[18] => src3_data[18].DATAIN +sink_data[18] => src4_data[18].DATAIN +sink_data[18] => src5_data[18].DATAIN +sink_data[18] => src6_data[18].DATAIN +sink_data[18] => src7_data[18].DATAIN +sink_data[18] => src8_data[18].DATAIN +sink_data[18] => src9_data[18].DATAIN +sink_data[18] => src10_data[18].DATAIN +sink_data[18] => src11_data[18].DATAIN +sink_data[18] => src12_data[18].DATAIN +sink_data[18] => src13_data[18].DATAIN +sink_data[18] => src14_data[18].DATAIN +sink_data[18] => src15_data[18].DATAIN +sink_data[18] => src16_data[18].DATAIN +sink_data[19] => src17_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src2_data[19].DATAIN +sink_data[19] => src3_data[19].DATAIN +sink_data[19] => src4_data[19].DATAIN +sink_data[19] => src5_data[19].DATAIN +sink_data[19] => src6_data[19].DATAIN +sink_data[19] => src7_data[19].DATAIN +sink_data[19] => src8_data[19].DATAIN +sink_data[19] => src9_data[19].DATAIN +sink_data[19] => src10_data[19].DATAIN +sink_data[19] => src11_data[19].DATAIN +sink_data[19] => src12_data[19].DATAIN +sink_data[19] => src13_data[19].DATAIN +sink_data[19] => src14_data[19].DATAIN +sink_data[19] => src15_data[19].DATAIN +sink_data[19] => src16_data[19].DATAIN +sink_data[20] => src17_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src2_data[20].DATAIN +sink_data[20] => src3_data[20].DATAIN +sink_data[20] => src4_data[20].DATAIN +sink_data[20] => src5_data[20].DATAIN +sink_data[20] => src6_data[20].DATAIN +sink_data[20] => src7_data[20].DATAIN +sink_data[20] => src8_data[20].DATAIN +sink_data[20] => src9_data[20].DATAIN +sink_data[20] => src10_data[20].DATAIN +sink_data[20] => src11_data[20].DATAIN +sink_data[20] => src12_data[20].DATAIN +sink_data[20] => src13_data[20].DATAIN +sink_data[20] => src14_data[20].DATAIN +sink_data[20] => src15_data[20].DATAIN +sink_data[20] => src16_data[20].DATAIN +sink_data[21] => src17_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src2_data[21].DATAIN +sink_data[21] => src3_data[21].DATAIN +sink_data[21] => src4_data[21].DATAIN +sink_data[21] => src5_data[21].DATAIN +sink_data[21] => src6_data[21].DATAIN +sink_data[21] => src7_data[21].DATAIN +sink_data[21] => src8_data[21].DATAIN +sink_data[21] => src9_data[21].DATAIN +sink_data[21] => src10_data[21].DATAIN +sink_data[21] => src11_data[21].DATAIN +sink_data[21] => src12_data[21].DATAIN +sink_data[21] => src13_data[21].DATAIN +sink_data[21] => src14_data[21].DATAIN +sink_data[21] => src15_data[21].DATAIN +sink_data[21] => src16_data[21].DATAIN +sink_data[22] => src17_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src2_data[22].DATAIN +sink_data[22] => src3_data[22].DATAIN +sink_data[22] => src4_data[22].DATAIN +sink_data[22] => src5_data[22].DATAIN +sink_data[22] => src6_data[22].DATAIN +sink_data[22] => src7_data[22].DATAIN +sink_data[22] => src8_data[22].DATAIN +sink_data[22] => src9_data[22].DATAIN +sink_data[22] => src10_data[22].DATAIN +sink_data[22] => src11_data[22].DATAIN +sink_data[22] => src12_data[22].DATAIN +sink_data[22] => src13_data[22].DATAIN +sink_data[22] => src14_data[22].DATAIN +sink_data[22] => src15_data[22].DATAIN +sink_data[22] => src16_data[22].DATAIN +sink_data[23] => src17_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src2_data[23].DATAIN +sink_data[23] => src3_data[23].DATAIN +sink_data[23] => src4_data[23].DATAIN +sink_data[23] => src5_data[23].DATAIN +sink_data[23] => src6_data[23].DATAIN +sink_data[23] => src7_data[23].DATAIN +sink_data[23] => src8_data[23].DATAIN +sink_data[23] => src9_data[23].DATAIN +sink_data[23] => src10_data[23].DATAIN +sink_data[23] => src11_data[23].DATAIN +sink_data[23] => src12_data[23].DATAIN +sink_data[23] => src13_data[23].DATAIN +sink_data[23] => src14_data[23].DATAIN +sink_data[23] => src15_data[23].DATAIN +sink_data[23] => src16_data[23].DATAIN +sink_data[24] => src17_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src2_data[24].DATAIN +sink_data[24] => src3_data[24].DATAIN +sink_data[24] => src4_data[24].DATAIN +sink_data[24] => src5_data[24].DATAIN +sink_data[24] => src6_data[24].DATAIN +sink_data[24] => src7_data[24].DATAIN +sink_data[24] => src8_data[24].DATAIN +sink_data[24] => src9_data[24].DATAIN +sink_data[24] => src10_data[24].DATAIN +sink_data[24] => src11_data[24].DATAIN +sink_data[24] => src12_data[24].DATAIN +sink_data[24] => src13_data[24].DATAIN +sink_data[24] => src14_data[24].DATAIN +sink_data[24] => src15_data[24].DATAIN +sink_data[24] => src16_data[24].DATAIN +sink_data[25] => src17_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src2_data[25].DATAIN +sink_data[25] => src3_data[25].DATAIN +sink_data[25] => src4_data[25].DATAIN +sink_data[25] => src5_data[25].DATAIN +sink_data[25] => src6_data[25].DATAIN +sink_data[25] => src7_data[25].DATAIN +sink_data[25] => src8_data[25].DATAIN +sink_data[25] => src9_data[25].DATAIN +sink_data[25] => src10_data[25].DATAIN +sink_data[25] => src11_data[25].DATAIN +sink_data[25] => src12_data[25].DATAIN +sink_data[25] => src13_data[25].DATAIN +sink_data[25] => src14_data[25].DATAIN +sink_data[25] => src15_data[25].DATAIN +sink_data[25] => src16_data[25].DATAIN +sink_data[26] => src17_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src2_data[26].DATAIN +sink_data[26] => src3_data[26].DATAIN +sink_data[26] => src4_data[26].DATAIN +sink_data[26] => src5_data[26].DATAIN +sink_data[26] => src6_data[26].DATAIN +sink_data[26] => src7_data[26].DATAIN +sink_data[26] => src8_data[26].DATAIN +sink_data[26] => src9_data[26].DATAIN +sink_data[26] => src10_data[26].DATAIN +sink_data[26] => src11_data[26].DATAIN +sink_data[26] => src12_data[26].DATAIN +sink_data[26] => src13_data[26].DATAIN +sink_data[26] => src14_data[26].DATAIN +sink_data[26] => src15_data[26].DATAIN +sink_data[26] => src16_data[26].DATAIN +sink_data[27] => src17_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src2_data[27].DATAIN +sink_data[27] => src3_data[27].DATAIN +sink_data[27] => src4_data[27].DATAIN +sink_data[27] => src5_data[27].DATAIN +sink_data[27] => src6_data[27].DATAIN +sink_data[27] => src7_data[27].DATAIN +sink_data[27] => src8_data[27].DATAIN +sink_data[27] => src9_data[27].DATAIN +sink_data[27] => src10_data[27].DATAIN +sink_data[27] => src11_data[27].DATAIN +sink_data[27] => src12_data[27].DATAIN +sink_data[27] => src13_data[27].DATAIN +sink_data[27] => src14_data[27].DATAIN +sink_data[27] => src15_data[27].DATAIN +sink_data[27] => src16_data[27].DATAIN +sink_data[28] => src17_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src2_data[28].DATAIN +sink_data[28] => src3_data[28].DATAIN +sink_data[28] => src4_data[28].DATAIN +sink_data[28] => src5_data[28].DATAIN +sink_data[28] => src6_data[28].DATAIN +sink_data[28] => src7_data[28].DATAIN +sink_data[28] => src8_data[28].DATAIN +sink_data[28] => src9_data[28].DATAIN +sink_data[28] => src10_data[28].DATAIN +sink_data[28] => src11_data[28].DATAIN +sink_data[28] => src12_data[28].DATAIN +sink_data[28] => src13_data[28].DATAIN +sink_data[28] => src14_data[28].DATAIN +sink_data[28] => src15_data[28].DATAIN +sink_data[28] => src16_data[28].DATAIN +sink_data[29] => src17_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src2_data[29].DATAIN +sink_data[29] => src3_data[29].DATAIN +sink_data[29] => src4_data[29].DATAIN +sink_data[29] => src5_data[29].DATAIN +sink_data[29] => src6_data[29].DATAIN +sink_data[29] => src7_data[29].DATAIN +sink_data[29] => src8_data[29].DATAIN +sink_data[29] => src9_data[29].DATAIN +sink_data[29] => src10_data[29].DATAIN +sink_data[29] => src11_data[29].DATAIN +sink_data[29] => src12_data[29].DATAIN +sink_data[29] => src13_data[29].DATAIN +sink_data[29] => src14_data[29].DATAIN +sink_data[29] => src15_data[29].DATAIN +sink_data[29] => src16_data[29].DATAIN +sink_data[30] => src17_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src2_data[30].DATAIN +sink_data[30] => src3_data[30].DATAIN +sink_data[30] => src4_data[30].DATAIN +sink_data[30] => src5_data[30].DATAIN +sink_data[30] => src6_data[30].DATAIN +sink_data[30] => src7_data[30].DATAIN +sink_data[30] => src8_data[30].DATAIN +sink_data[30] => src9_data[30].DATAIN +sink_data[30] => src10_data[30].DATAIN +sink_data[30] => src11_data[30].DATAIN +sink_data[30] => src12_data[30].DATAIN +sink_data[30] => src13_data[30].DATAIN +sink_data[30] => src14_data[30].DATAIN +sink_data[30] => src15_data[30].DATAIN +sink_data[30] => src16_data[30].DATAIN +sink_data[31] => src17_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src2_data[31].DATAIN +sink_data[31] => src3_data[31].DATAIN +sink_data[31] => src4_data[31].DATAIN +sink_data[31] => src5_data[31].DATAIN +sink_data[31] => src6_data[31].DATAIN +sink_data[31] => src7_data[31].DATAIN +sink_data[31] => src8_data[31].DATAIN +sink_data[31] => src9_data[31].DATAIN +sink_data[31] => src10_data[31].DATAIN +sink_data[31] => src11_data[31].DATAIN +sink_data[31] => src12_data[31].DATAIN +sink_data[31] => src13_data[31].DATAIN +sink_data[31] => src14_data[31].DATAIN +sink_data[31] => src15_data[31].DATAIN +sink_data[31] => src16_data[31].DATAIN +sink_data[32] => src17_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src2_data[32].DATAIN +sink_data[32] => src3_data[32].DATAIN +sink_data[32] => src4_data[32].DATAIN +sink_data[32] => src5_data[32].DATAIN +sink_data[32] => src6_data[32].DATAIN +sink_data[32] => src7_data[32].DATAIN +sink_data[32] => src8_data[32].DATAIN +sink_data[32] => src9_data[32].DATAIN +sink_data[32] => src10_data[32].DATAIN +sink_data[32] => src11_data[32].DATAIN +sink_data[32] => src12_data[32].DATAIN +sink_data[32] => src13_data[32].DATAIN +sink_data[32] => src14_data[32].DATAIN +sink_data[32] => src15_data[32].DATAIN +sink_data[32] => src16_data[32].DATAIN +sink_data[33] => src17_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src2_data[33].DATAIN +sink_data[33] => src3_data[33].DATAIN +sink_data[33] => src4_data[33].DATAIN +sink_data[33] => src5_data[33].DATAIN +sink_data[33] => src6_data[33].DATAIN +sink_data[33] => src7_data[33].DATAIN +sink_data[33] => src8_data[33].DATAIN +sink_data[33] => src9_data[33].DATAIN +sink_data[33] => src10_data[33].DATAIN +sink_data[33] => src11_data[33].DATAIN +sink_data[33] => src12_data[33].DATAIN +sink_data[33] => src13_data[33].DATAIN +sink_data[33] => src14_data[33].DATAIN +sink_data[33] => src15_data[33].DATAIN +sink_data[33] => src16_data[33].DATAIN +sink_data[34] => src17_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src2_data[34].DATAIN +sink_data[34] => src3_data[34].DATAIN +sink_data[34] => src4_data[34].DATAIN +sink_data[34] => src5_data[34].DATAIN +sink_data[34] => src6_data[34].DATAIN +sink_data[34] => src7_data[34].DATAIN +sink_data[34] => src8_data[34].DATAIN +sink_data[34] => src9_data[34].DATAIN +sink_data[34] => src10_data[34].DATAIN +sink_data[34] => src11_data[34].DATAIN +sink_data[34] => src12_data[34].DATAIN +sink_data[34] => src13_data[34].DATAIN +sink_data[34] => src14_data[34].DATAIN +sink_data[34] => src15_data[34].DATAIN +sink_data[34] => src16_data[34].DATAIN +sink_data[35] => src17_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src2_data[35].DATAIN +sink_data[35] => src3_data[35].DATAIN +sink_data[35] => src4_data[35].DATAIN +sink_data[35] => src5_data[35].DATAIN +sink_data[35] => src6_data[35].DATAIN +sink_data[35] => src7_data[35].DATAIN +sink_data[35] => src8_data[35].DATAIN +sink_data[35] => src9_data[35].DATAIN +sink_data[35] => src10_data[35].DATAIN +sink_data[35] => src11_data[35].DATAIN +sink_data[35] => src12_data[35].DATAIN +sink_data[35] => src13_data[35].DATAIN +sink_data[35] => src14_data[35].DATAIN +sink_data[35] => src15_data[35].DATAIN +sink_data[35] => src16_data[35].DATAIN +sink_data[36] => src17_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src2_data[36].DATAIN +sink_data[36] => src3_data[36].DATAIN +sink_data[36] => src4_data[36].DATAIN +sink_data[36] => src5_data[36].DATAIN +sink_data[36] => src6_data[36].DATAIN +sink_data[36] => src7_data[36].DATAIN +sink_data[36] => src8_data[36].DATAIN +sink_data[36] => src9_data[36].DATAIN +sink_data[36] => src10_data[36].DATAIN +sink_data[36] => src11_data[36].DATAIN +sink_data[36] => src12_data[36].DATAIN +sink_data[36] => src13_data[36].DATAIN +sink_data[36] => src14_data[36].DATAIN +sink_data[36] => src15_data[36].DATAIN +sink_data[36] => src16_data[36].DATAIN +sink_data[37] => src17_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src2_data[37].DATAIN +sink_data[37] => src3_data[37].DATAIN +sink_data[37] => src4_data[37].DATAIN +sink_data[37] => src5_data[37].DATAIN +sink_data[37] => src6_data[37].DATAIN +sink_data[37] => src7_data[37].DATAIN +sink_data[37] => src8_data[37].DATAIN +sink_data[37] => src9_data[37].DATAIN +sink_data[37] => src10_data[37].DATAIN +sink_data[37] => src11_data[37].DATAIN +sink_data[37] => src12_data[37].DATAIN +sink_data[37] => src13_data[37].DATAIN +sink_data[37] => src14_data[37].DATAIN +sink_data[37] => src15_data[37].DATAIN +sink_data[37] => src16_data[37].DATAIN +sink_data[38] => src17_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src2_data[38].DATAIN +sink_data[38] => src3_data[38].DATAIN +sink_data[38] => src4_data[38].DATAIN +sink_data[38] => src5_data[38].DATAIN +sink_data[38] => src6_data[38].DATAIN +sink_data[38] => src7_data[38].DATAIN +sink_data[38] => src8_data[38].DATAIN +sink_data[38] => src9_data[38].DATAIN +sink_data[38] => src10_data[38].DATAIN +sink_data[38] => src11_data[38].DATAIN +sink_data[38] => src12_data[38].DATAIN +sink_data[38] => src13_data[38].DATAIN +sink_data[38] => src14_data[38].DATAIN +sink_data[38] => src15_data[38].DATAIN +sink_data[38] => src16_data[38].DATAIN +sink_data[39] => src17_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src2_data[39].DATAIN +sink_data[39] => src3_data[39].DATAIN +sink_data[39] => src4_data[39].DATAIN +sink_data[39] => src5_data[39].DATAIN +sink_data[39] => src6_data[39].DATAIN +sink_data[39] => src7_data[39].DATAIN +sink_data[39] => src8_data[39].DATAIN +sink_data[39] => src9_data[39].DATAIN +sink_data[39] => src10_data[39].DATAIN +sink_data[39] => src11_data[39].DATAIN +sink_data[39] => src12_data[39].DATAIN +sink_data[39] => src13_data[39].DATAIN +sink_data[39] => src14_data[39].DATAIN +sink_data[39] => src15_data[39].DATAIN +sink_data[39] => src16_data[39].DATAIN +sink_data[40] => src17_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src2_data[40].DATAIN +sink_data[40] => src3_data[40].DATAIN +sink_data[40] => src4_data[40].DATAIN +sink_data[40] => src5_data[40].DATAIN +sink_data[40] => src6_data[40].DATAIN +sink_data[40] => src7_data[40].DATAIN +sink_data[40] => src8_data[40].DATAIN +sink_data[40] => src9_data[40].DATAIN +sink_data[40] => src10_data[40].DATAIN +sink_data[40] => src11_data[40].DATAIN +sink_data[40] => src12_data[40].DATAIN +sink_data[40] => src13_data[40].DATAIN +sink_data[40] => src14_data[40].DATAIN +sink_data[40] => src15_data[40].DATAIN +sink_data[40] => src16_data[40].DATAIN +sink_data[41] => src17_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src2_data[41].DATAIN +sink_data[41] => src3_data[41].DATAIN +sink_data[41] => src4_data[41].DATAIN +sink_data[41] => src5_data[41].DATAIN +sink_data[41] => src6_data[41].DATAIN +sink_data[41] => src7_data[41].DATAIN +sink_data[41] => src8_data[41].DATAIN +sink_data[41] => src9_data[41].DATAIN +sink_data[41] => src10_data[41].DATAIN +sink_data[41] => src11_data[41].DATAIN +sink_data[41] => src12_data[41].DATAIN +sink_data[41] => src13_data[41].DATAIN +sink_data[41] => src14_data[41].DATAIN +sink_data[41] => src15_data[41].DATAIN +sink_data[41] => src16_data[41].DATAIN +sink_data[42] => src17_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src2_data[42].DATAIN +sink_data[42] => src3_data[42].DATAIN +sink_data[42] => src4_data[42].DATAIN +sink_data[42] => src5_data[42].DATAIN +sink_data[42] => src6_data[42].DATAIN +sink_data[42] => src7_data[42].DATAIN +sink_data[42] => src8_data[42].DATAIN +sink_data[42] => src9_data[42].DATAIN +sink_data[42] => src10_data[42].DATAIN +sink_data[42] => src11_data[42].DATAIN +sink_data[42] => src12_data[42].DATAIN +sink_data[42] => src13_data[42].DATAIN +sink_data[42] => src14_data[42].DATAIN +sink_data[42] => src15_data[42].DATAIN +sink_data[42] => src16_data[42].DATAIN +sink_data[43] => src17_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src2_data[43].DATAIN +sink_data[43] => src3_data[43].DATAIN +sink_data[43] => src4_data[43].DATAIN +sink_data[43] => src5_data[43].DATAIN +sink_data[43] => src6_data[43].DATAIN +sink_data[43] => src7_data[43].DATAIN +sink_data[43] => src8_data[43].DATAIN +sink_data[43] => src9_data[43].DATAIN +sink_data[43] => src10_data[43].DATAIN +sink_data[43] => src11_data[43].DATAIN +sink_data[43] => src12_data[43].DATAIN +sink_data[43] => src13_data[43].DATAIN +sink_data[43] => src14_data[43].DATAIN +sink_data[43] => src15_data[43].DATAIN +sink_data[43] => src16_data[43].DATAIN +sink_data[44] => src17_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src2_data[44].DATAIN +sink_data[44] => src3_data[44].DATAIN +sink_data[44] => src4_data[44].DATAIN +sink_data[44] => src5_data[44].DATAIN +sink_data[44] => src6_data[44].DATAIN +sink_data[44] => src7_data[44].DATAIN +sink_data[44] => src8_data[44].DATAIN +sink_data[44] => src9_data[44].DATAIN +sink_data[44] => src10_data[44].DATAIN +sink_data[44] => src11_data[44].DATAIN +sink_data[44] => src12_data[44].DATAIN +sink_data[44] => src13_data[44].DATAIN +sink_data[44] => src14_data[44].DATAIN +sink_data[44] => src15_data[44].DATAIN +sink_data[44] => src16_data[44].DATAIN +sink_data[45] => src17_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src2_data[45].DATAIN +sink_data[45] => src3_data[45].DATAIN +sink_data[45] => src4_data[45].DATAIN +sink_data[45] => src5_data[45].DATAIN +sink_data[45] => src6_data[45].DATAIN +sink_data[45] => src7_data[45].DATAIN +sink_data[45] => src8_data[45].DATAIN +sink_data[45] => src9_data[45].DATAIN +sink_data[45] => src10_data[45].DATAIN +sink_data[45] => src11_data[45].DATAIN +sink_data[45] => src12_data[45].DATAIN +sink_data[45] => src13_data[45].DATAIN +sink_data[45] => src14_data[45].DATAIN +sink_data[45] => src15_data[45].DATAIN +sink_data[45] => src16_data[45].DATAIN +sink_data[46] => src17_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src2_data[46].DATAIN +sink_data[46] => src3_data[46].DATAIN +sink_data[46] => src4_data[46].DATAIN +sink_data[46] => src5_data[46].DATAIN +sink_data[46] => src6_data[46].DATAIN +sink_data[46] => src7_data[46].DATAIN +sink_data[46] => src8_data[46].DATAIN +sink_data[46] => src9_data[46].DATAIN +sink_data[46] => src10_data[46].DATAIN +sink_data[46] => src11_data[46].DATAIN +sink_data[46] => src12_data[46].DATAIN +sink_data[46] => src13_data[46].DATAIN +sink_data[46] => src14_data[46].DATAIN +sink_data[46] => src15_data[46].DATAIN +sink_data[46] => src16_data[46].DATAIN +sink_data[47] => src17_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src2_data[47].DATAIN +sink_data[47] => src3_data[47].DATAIN +sink_data[47] => src4_data[47].DATAIN +sink_data[47] => src5_data[47].DATAIN +sink_data[47] => src6_data[47].DATAIN +sink_data[47] => src7_data[47].DATAIN +sink_data[47] => src8_data[47].DATAIN +sink_data[47] => src9_data[47].DATAIN +sink_data[47] => src10_data[47].DATAIN +sink_data[47] => src11_data[47].DATAIN +sink_data[47] => src12_data[47].DATAIN +sink_data[47] => src13_data[47].DATAIN +sink_data[47] => src14_data[47].DATAIN +sink_data[47] => src15_data[47].DATAIN +sink_data[47] => src16_data[47].DATAIN +sink_data[48] => src17_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src2_data[48].DATAIN +sink_data[48] => src3_data[48].DATAIN +sink_data[48] => src4_data[48].DATAIN +sink_data[48] => src5_data[48].DATAIN +sink_data[48] => src6_data[48].DATAIN +sink_data[48] => src7_data[48].DATAIN +sink_data[48] => src8_data[48].DATAIN +sink_data[48] => src9_data[48].DATAIN +sink_data[48] => src10_data[48].DATAIN +sink_data[48] => src11_data[48].DATAIN +sink_data[48] => src12_data[48].DATAIN +sink_data[48] => src13_data[48].DATAIN +sink_data[48] => src14_data[48].DATAIN +sink_data[48] => src15_data[48].DATAIN +sink_data[48] => src16_data[48].DATAIN +sink_data[49] => src17_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src2_data[49].DATAIN +sink_data[49] => src3_data[49].DATAIN +sink_data[49] => src4_data[49].DATAIN +sink_data[49] => src5_data[49].DATAIN +sink_data[49] => src6_data[49].DATAIN +sink_data[49] => src7_data[49].DATAIN +sink_data[49] => src8_data[49].DATAIN +sink_data[49] => src9_data[49].DATAIN +sink_data[49] => src10_data[49].DATAIN +sink_data[49] => src11_data[49].DATAIN +sink_data[49] => src12_data[49].DATAIN +sink_data[49] => src13_data[49].DATAIN +sink_data[49] => src14_data[49].DATAIN +sink_data[49] => src15_data[49].DATAIN +sink_data[49] => src16_data[49].DATAIN +sink_data[50] => src17_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src2_data[50].DATAIN +sink_data[50] => src3_data[50].DATAIN +sink_data[50] => src4_data[50].DATAIN +sink_data[50] => src5_data[50].DATAIN +sink_data[50] => src6_data[50].DATAIN +sink_data[50] => src7_data[50].DATAIN +sink_data[50] => src8_data[50].DATAIN +sink_data[50] => src9_data[50].DATAIN +sink_data[50] => src10_data[50].DATAIN +sink_data[50] => src11_data[50].DATAIN +sink_data[50] => src12_data[50].DATAIN +sink_data[50] => src13_data[50].DATAIN +sink_data[50] => src14_data[50].DATAIN +sink_data[50] => src15_data[50].DATAIN +sink_data[50] => src16_data[50].DATAIN +sink_data[51] => src17_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src2_data[51].DATAIN +sink_data[51] => src3_data[51].DATAIN +sink_data[51] => src4_data[51].DATAIN +sink_data[51] => src5_data[51].DATAIN +sink_data[51] => src6_data[51].DATAIN +sink_data[51] => src7_data[51].DATAIN +sink_data[51] => src8_data[51].DATAIN +sink_data[51] => src9_data[51].DATAIN +sink_data[51] => src10_data[51].DATAIN +sink_data[51] => src11_data[51].DATAIN +sink_data[51] => src12_data[51].DATAIN +sink_data[51] => src13_data[51].DATAIN +sink_data[51] => src14_data[51].DATAIN +sink_data[51] => src15_data[51].DATAIN +sink_data[51] => src16_data[51].DATAIN +sink_data[52] => src17_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src2_data[52].DATAIN +sink_data[52] => src3_data[52].DATAIN +sink_data[52] => src4_data[52].DATAIN +sink_data[52] => src5_data[52].DATAIN +sink_data[52] => src6_data[52].DATAIN +sink_data[52] => src7_data[52].DATAIN +sink_data[52] => src8_data[52].DATAIN +sink_data[52] => src9_data[52].DATAIN +sink_data[52] => src10_data[52].DATAIN +sink_data[52] => src11_data[52].DATAIN +sink_data[52] => src12_data[52].DATAIN +sink_data[52] => src13_data[52].DATAIN +sink_data[52] => src14_data[52].DATAIN +sink_data[52] => src15_data[52].DATAIN +sink_data[52] => src16_data[52].DATAIN +sink_data[53] => src17_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src2_data[53].DATAIN +sink_data[53] => src3_data[53].DATAIN +sink_data[53] => src4_data[53].DATAIN +sink_data[53] => src5_data[53].DATAIN +sink_data[53] => src6_data[53].DATAIN +sink_data[53] => src7_data[53].DATAIN +sink_data[53] => src8_data[53].DATAIN +sink_data[53] => src9_data[53].DATAIN +sink_data[53] => src10_data[53].DATAIN +sink_data[53] => src11_data[53].DATAIN +sink_data[53] => src12_data[53].DATAIN +sink_data[53] => src13_data[53].DATAIN +sink_data[53] => src14_data[53].DATAIN +sink_data[53] => src15_data[53].DATAIN +sink_data[53] => src16_data[53].DATAIN +sink_data[54] => src17_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src2_data[54].DATAIN +sink_data[54] => src3_data[54].DATAIN +sink_data[54] => src4_data[54].DATAIN +sink_data[54] => src5_data[54].DATAIN +sink_data[54] => src6_data[54].DATAIN +sink_data[54] => src7_data[54].DATAIN +sink_data[54] => src8_data[54].DATAIN +sink_data[54] => src9_data[54].DATAIN +sink_data[54] => src10_data[54].DATAIN +sink_data[54] => src11_data[54].DATAIN +sink_data[54] => src12_data[54].DATAIN +sink_data[54] => src13_data[54].DATAIN +sink_data[54] => src14_data[54].DATAIN +sink_data[54] => src15_data[54].DATAIN +sink_data[54] => src16_data[54].DATAIN +sink_data[55] => src17_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src2_data[55].DATAIN +sink_data[55] => src3_data[55].DATAIN +sink_data[55] => src4_data[55].DATAIN +sink_data[55] => src5_data[55].DATAIN +sink_data[55] => src6_data[55].DATAIN +sink_data[55] => src7_data[55].DATAIN +sink_data[55] => src8_data[55].DATAIN +sink_data[55] => src9_data[55].DATAIN +sink_data[55] => src10_data[55].DATAIN +sink_data[55] => src11_data[55].DATAIN +sink_data[55] => src12_data[55].DATAIN +sink_data[55] => src13_data[55].DATAIN +sink_data[55] => src14_data[55].DATAIN +sink_data[55] => src15_data[55].DATAIN +sink_data[55] => src16_data[55].DATAIN +sink_data[56] => src17_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src2_data[56].DATAIN +sink_data[56] => src3_data[56].DATAIN +sink_data[56] => src4_data[56].DATAIN +sink_data[56] => src5_data[56].DATAIN +sink_data[56] => src6_data[56].DATAIN +sink_data[56] => src7_data[56].DATAIN +sink_data[56] => src8_data[56].DATAIN +sink_data[56] => src9_data[56].DATAIN +sink_data[56] => src10_data[56].DATAIN +sink_data[56] => src11_data[56].DATAIN +sink_data[56] => src12_data[56].DATAIN +sink_data[56] => src13_data[56].DATAIN +sink_data[56] => src14_data[56].DATAIN +sink_data[56] => src15_data[56].DATAIN +sink_data[56] => src16_data[56].DATAIN +sink_data[57] => src17_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src2_data[57].DATAIN +sink_data[57] => src3_data[57].DATAIN +sink_data[57] => src4_data[57].DATAIN +sink_data[57] => src5_data[57].DATAIN +sink_data[57] => src6_data[57].DATAIN +sink_data[57] => src7_data[57].DATAIN +sink_data[57] => src8_data[57].DATAIN +sink_data[57] => src9_data[57].DATAIN +sink_data[57] => src10_data[57].DATAIN +sink_data[57] => src11_data[57].DATAIN +sink_data[57] => src12_data[57].DATAIN +sink_data[57] => src13_data[57].DATAIN +sink_data[57] => src14_data[57].DATAIN +sink_data[57] => src15_data[57].DATAIN +sink_data[57] => src16_data[57].DATAIN +sink_data[58] => src17_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src2_data[58].DATAIN +sink_data[58] => src3_data[58].DATAIN +sink_data[58] => src4_data[58].DATAIN +sink_data[58] => src5_data[58].DATAIN +sink_data[58] => src6_data[58].DATAIN +sink_data[58] => src7_data[58].DATAIN +sink_data[58] => src8_data[58].DATAIN +sink_data[58] => src9_data[58].DATAIN +sink_data[58] => src10_data[58].DATAIN +sink_data[58] => src11_data[58].DATAIN +sink_data[58] => src12_data[58].DATAIN +sink_data[58] => src13_data[58].DATAIN +sink_data[58] => src14_data[58].DATAIN +sink_data[58] => src15_data[58].DATAIN +sink_data[58] => src16_data[58].DATAIN +sink_data[59] => src17_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src2_data[59].DATAIN +sink_data[59] => src3_data[59].DATAIN +sink_data[59] => src4_data[59].DATAIN +sink_data[59] => src5_data[59].DATAIN +sink_data[59] => src6_data[59].DATAIN +sink_data[59] => src7_data[59].DATAIN +sink_data[59] => src8_data[59].DATAIN +sink_data[59] => src9_data[59].DATAIN +sink_data[59] => src10_data[59].DATAIN +sink_data[59] => src11_data[59].DATAIN +sink_data[59] => src12_data[59].DATAIN +sink_data[59] => src13_data[59].DATAIN +sink_data[59] => src14_data[59].DATAIN +sink_data[59] => src15_data[59].DATAIN +sink_data[59] => src16_data[59].DATAIN +sink_data[60] => src17_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src2_data[60].DATAIN +sink_data[60] => src3_data[60].DATAIN +sink_data[60] => src4_data[60].DATAIN +sink_data[60] => src5_data[60].DATAIN +sink_data[60] => src6_data[60].DATAIN +sink_data[60] => src7_data[60].DATAIN +sink_data[60] => src8_data[60].DATAIN +sink_data[60] => src9_data[60].DATAIN +sink_data[60] => src10_data[60].DATAIN +sink_data[60] => src11_data[60].DATAIN +sink_data[60] => src12_data[60].DATAIN +sink_data[60] => src13_data[60].DATAIN +sink_data[60] => src14_data[60].DATAIN +sink_data[60] => src15_data[60].DATAIN +sink_data[60] => src16_data[60].DATAIN +sink_data[61] => src17_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src2_data[61].DATAIN +sink_data[61] => src3_data[61].DATAIN +sink_data[61] => src4_data[61].DATAIN +sink_data[61] => src5_data[61].DATAIN +sink_data[61] => src6_data[61].DATAIN +sink_data[61] => src7_data[61].DATAIN +sink_data[61] => src8_data[61].DATAIN +sink_data[61] => src9_data[61].DATAIN +sink_data[61] => src10_data[61].DATAIN +sink_data[61] => src11_data[61].DATAIN +sink_data[61] => src12_data[61].DATAIN +sink_data[61] => src13_data[61].DATAIN +sink_data[61] => src14_data[61].DATAIN +sink_data[61] => src15_data[61].DATAIN +sink_data[61] => src16_data[61].DATAIN +sink_data[62] => src17_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src2_data[62].DATAIN +sink_data[62] => src3_data[62].DATAIN +sink_data[62] => src4_data[62].DATAIN +sink_data[62] => src5_data[62].DATAIN +sink_data[62] => src6_data[62].DATAIN +sink_data[62] => src7_data[62].DATAIN +sink_data[62] => src8_data[62].DATAIN +sink_data[62] => src9_data[62].DATAIN +sink_data[62] => src10_data[62].DATAIN +sink_data[62] => src11_data[62].DATAIN +sink_data[62] => src12_data[62].DATAIN +sink_data[62] => src13_data[62].DATAIN +sink_data[62] => src14_data[62].DATAIN +sink_data[62] => src15_data[62].DATAIN +sink_data[62] => src16_data[62].DATAIN +sink_data[63] => src17_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src2_data[63].DATAIN +sink_data[63] => src3_data[63].DATAIN +sink_data[63] => src4_data[63].DATAIN +sink_data[63] => src5_data[63].DATAIN +sink_data[63] => src6_data[63].DATAIN +sink_data[63] => src7_data[63].DATAIN +sink_data[63] => src8_data[63].DATAIN +sink_data[63] => src9_data[63].DATAIN +sink_data[63] => src10_data[63].DATAIN +sink_data[63] => src11_data[63].DATAIN +sink_data[63] => src12_data[63].DATAIN +sink_data[63] => src13_data[63].DATAIN +sink_data[63] => src14_data[63].DATAIN +sink_data[63] => src15_data[63].DATAIN +sink_data[63] => src16_data[63].DATAIN +sink_data[64] => src17_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src2_data[64].DATAIN +sink_data[64] => src3_data[64].DATAIN +sink_data[64] => src4_data[64].DATAIN +sink_data[64] => src5_data[64].DATAIN +sink_data[64] => src6_data[64].DATAIN +sink_data[64] => src7_data[64].DATAIN +sink_data[64] => src8_data[64].DATAIN +sink_data[64] => src9_data[64].DATAIN +sink_data[64] => src10_data[64].DATAIN +sink_data[64] => src11_data[64].DATAIN +sink_data[64] => src12_data[64].DATAIN +sink_data[64] => src13_data[64].DATAIN +sink_data[64] => src14_data[64].DATAIN +sink_data[64] => src15_data[64].DATAIN +sink_data[64] => src16_data[64].DATAIN +sink_data[65] => src17_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src2_data[65].DATAIN +sink_data[65] => src3_data[65].DATAIN +sink_data[65] => src4_data[65].DATAIN +sink_data[65] => src5_data[65].DATAIN +sink_data[65] => src6_data[65].DATAIN +sink_data[65] => src7_data[65].DATAIN +sink_data[65] => src8_data[65].DATAIN +sink_data[65] => src9_data[65].DATAIN +sink_data[65] => src10_data[65].DATAIN +sink_data[65] => src11_data[65].DATAIN +sink_data[65] => src12_data[65].DATAIN +sink_data[65] => src13_data[65].DATAIN +sink_data[65] => src14_data[65].DATAIN +sink_data[65] => src15_data[65].DATAIN +sink_data[65] => src16_data[65].DATAIN +sink_data[66] => src17_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src2_data[66].DATAIN +sink_data[66] => src3_data[66].DATAIN +sink_data[66] => src4_data[66].DATAIN +sink_data[66] => src5_data[66].DATAIN +sink_data[66] => src6_data[66].DATAIN +sink_data[66] => src7_data[66].DATAIN +sink_data[66] => src8_data[66].DATAIN +sink_data[66] => src9_data[66].DATAIN +sink_data[66] => src10_data[66].DATAIN +sink_data[66] => src11_data[66].DATAIN +sink_data[66] => src12_data[66].DATAIN +sink_data[66] => src13_data[66].DATAIN +sink_data[66] => src14_data[66].DATAIN +sink_data[66] => src15_data[66].DATAIN +sink_data[66] => src16_data[66].DATAIN +sink_data[67] => src17_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src2_data[67].DATAIN +sink_data[67] => src3_data[67].DATAIN +sink_data[67] => src4_data[67].DATAIN +sink_data[67] => src5_data[67].DATAIN +sink_data[67] => src6_data[67].DATAIN +sink_data[67] => src7_data[67].DATAIN +sink_data[67] => src8_data[67].DATAIN +sink_data[67] => src9_data[67].DATAIN +sink_data[67] => src10_data[67].DATAIN +sink_data[67] => src11_data[67].DATAIN +sink_data[67] => src12_data[67].DATAIN +sink_data[67] => src13_data[67].DATAIN +sink_data[67] => src14_data[67].DATAIN +sink_data[67] => src15_data[67].DATAIN +sink_data[67] => src16_data[67].DATAIN +sink_data[68] => src17_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src2_data[68].DATAIN +sink_data[68] => src3_data[68].DATAIN +sink_data[68] => src4_data[68].DATAIN +sink_data[68] => src5_data[68].DATAIN +sink_data[68] => src6_data[68].DATAIN +sink_data[68] => src7_data[68].DATAIN +sink_data[68] => src8_data[68].DATAIN +sink_data[68] => src9_data[68].DATAIN +sink_data[68] => src10_data[68].DATAIN +sink_data[68] => src11_data[68].DATAIN +sink_data[68] => src12_data[68].DATAIN +sink_data[68] => src13_data[68].DATAIN +sink_data[68] => src14_data[68].DATAIN +sink_data[68] => src15_data[68].DATAIN +sink_data[68] => src16_data[68].DATAIN +sink_data[69] => src17_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src2_data[69].DATAIN +sink_data[69] => src3_data[69].DATAIN +sink_data[69] => src4_data[69].DATAIN +sink_data[69] => src5_data[69].DATAIN +sink_data[69] => src6_data[69].DATAIN +sink_data[69] => src7_data[69].DATAIN +sink_data[69] => src8_data[69].DATAIN +sink_data[69] => src9_data[69].DATAIN +sink_data[69] => src10_data[69].DATAIN +sink_data[69] => src11_data[69].DATAIN +sink_data[69] => src12_data[69].DATAIN +sink_data[69] => src13_data[69].DATAIN +sink_data[69] => src14_data[69].DATAIN +sink_data[69] => src15_data[69].DATAIN +sink_data[69] => src16_data[69].DATAIN +sink_data[70] => src17_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src2_data[70].DATAIN +sink_data[70] => src3_data[70].DATAIN +sink_data[70] => src4_data[70].DATAIN +sink_data[70] => src5_data[70].DATAIN +sink_data[70] => src6_data[70].DATAIN +sink_data[70] => src7_data[70].DATAIN +sink_data[70] => src8_data[70].DATAIN +sink_data[70] => src9_data[70].DATAIN +sink_data[70] => src10_data[70].DATAIN +sink_data[70] => src11_data[70].DATAIN +sink_data[70] => src12_data[70].DATAIN +sink_data[70] => src13_data[70].DATAIN +sink_data[70] => src14_data[70].DATAIN +sink_data[70] => src15_data[70].DATAIN +sink_data[70] => src16_data[70].DATAIN +sink_data[71] => src17_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src2_data[71].DATAIN +sink_data[71] => src3_data[71].DATAIN +sink_data[71] => src4_data[71].DATAIN +sink_data[71] => src5_data[71].DATAIN +sink_data[71] => src6_data[71].DATAIN +sink_data[71] => src7_data[71].DATAIN +sink_data[71] => src8_data[71].DATAIN +sink_data[71] => src9_data[71].DATAIN +sink_data[71] => src10_data[71].DATAIN +sink_data[71] => src11_data[71].DATAIN +sink_data[71] => src12_data[71].DATAIN +sink_data[71] => src13_data[71].DATAIN +sink_data[71] => src14_data[71].DATAIN +sink_data[71] => src15_data[71].DATAIN +sink_data[71] => src16_data[71].DATAIN +sink_data[72] => src17_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src2_data[72].DATAIN +sink_data[72] => src3_data[72].DATAIN +sink_data[72] => src4_data[72].DATAIN +sink_data[72] => src5_data[72].DATAIN +sink_data[72] => src6_data[72].DATAIN +sink_data[72] => src7_data[72].DATAIN +sink_data[72] => src8_data[72].DATAIN +sink_data[72] => src9_data[72].DATAIN +sink_data[72] => src10_data[72].DATAIN +sink_data[72] => src11_data[72].DATAIN +sink_data[72] => src12_data[72].DATAIN +sink_data[72] => src13_data[72].DATAIN +sink_data[72] => src14_data[72].DATAIN +sink_data[72] => src15_data[72].DATAIN +sink_data[72] => src16_data[72].DATAIN +sink_data[73] => src17_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src2_data[73].DATAIN +sink_data[73] => src3_data[73].DATAIN +sink_data[73] => src4_data[73].DATAIN +sink_data[73] => src5_data[73].DATAIN +sink_data[73] => src6_data[73].DATAIN +sink_data[73] => src7_data[73].DATAIN +sink_data[73] => src8_data[73].DATAIN +sink_data[73] => src9_data[73].DATAIN +sink_data[73] => src10_data[73].DATAIN +sink_data[73] => src11_data[73].DATAIN +sink_data[73] => src12_data[73].DATAIN +sink_data[73] => src13_data[73].DATAIN +sink_data[73] => src14_data[73].DATAIN +sink_data[73] => src15_data[73].DATAIN +sink_data[73] => src16_data[73].DATAIN +sink_data[74] => src17_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src2_data[74].DATAIN +sink_data[74] => src3_data[74].DATAIN +sink_data[74] => src4_data[74].DATAIN +sink_data[74] => src5_data[74].DATAIN +sink_data[74] => src6_data[74].DATAIN +sink_data[74] => src7_data[74].DATAIN +sink_data[74] => src8_data[74].DATAIN +sink_data[74] => src9_data[74].DATAIN +sink_data[74] => src10_data[74].DATAIN +sink_data[74] => src11_data[74].DATAIN +sink_data[74] => src12_data[74].DATAIN +sink_data[74] => src13_data[74].DATAIN +sink_data[74] => src14_data[74].DATAIN +sink_data[74] => src15_data[74].DATAIN +sink_data[74] => src16_data[74].DATAIN +sink_data[75] => src17_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src2_data[75].DATAIN +sink_data[75] => src3_data[75].DATAIN +sink_data[75] => src4_data[75].DATAIN +sink_data[75] => src5_data[75].DATAIN +sink_data[75] => src6_data[75].DATAIN +sink_data[75] => src7_data[75].DATAIN +sink_data[75] => src8_data[75].DATAIN +sink_data[75] => src9_data[75].DATAIN +sink_data[75] => src10_data[75].DATAIN +sink_data[75] => src11_data[75].DATAIN +sink_data[75] => src12_data[75].DATAIN +sink_data[75] => src13_data[75].DATAIN +sink_data[75] => src14_data[75].DATAIN +sink_data[75] => src15_data[75].DATAIN +sink_data[75] => src16_data[75].DATAIN +sink_data[76] => src17_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src2_data[76].DATAIN +sink_data[76] => src3_data[76].DATAIN +sink_data[76] => src4_data[76].DATAIN +sink_data[76] => src5_data[76].DATAIN +sink_data[76] => src6_data[76].DATAIN +sink_data[76] => src7_data[76].DATAIN +sink_data[76] => src8_data[76].DATAIN +sink_data[76] => src9_data[76].DATAIN +sink_data[76] => src10_data[76].DATAIN +sink_data[76] => src11_data[76].DATAIN +sink_data[76] => src12_data[76].DATAIN +sink_data[76] => src13_data[76].DATAIN +sink_data[76] => src14_data[76].DATAIN +sink_data[76] => src15_data[76].DATAIN +sink_data[76] => src16_data[76].DATAIN +sink_data[77] => src17_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src2_data[77].DATAIN +sink_data[77] => src3_data[77].DATAIN +sink_data[77] => src4_data[77].DATAIN +sink_data[77] => src5_data[77].DATAIN +sink_data[77] => src6_data[77].DATAIN +sink_data[77] => src7_data[77].DATAIN +sink_data[77] => src8_data[77].DATAIN +sink_data[77] => src9_data[77].DATAIN +sink_data[77] => src10_data[77].DATAIN +sink_data[77] => src11_data[77].DATAIN +sink_data[77] => src12_data[77].DATAIN +sink_data[77] => src13_data[77].DATAIN +sink_data[77] => src14_data[77].DATAIN +sink_data[77] => src15_data[77].DATAIN +sink_data[77] => src16_data[77].DATAIN +sink_data[78] => src17_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src2_data[78].DATAIN +sink_data[78] => src3_data[78].DATAIN +sink_data[78] => src4_data[78].DATAIN +sink_data[78] => src5_data[78].DATAIN +sink_data[78] => src6_data[78].DATAIN +sink_data[78] => src7_data[78].DATAIN +sink_data[78] => src8_data[78].DATAIN +sink_data[78] => src9_data[78].DATAIN +sink_data[78] => src10_data[78].DATAIN +sink_data[78] => src11_data[78].DATAIN +sink_data[78] => src12_data[78].DATAIN +sink_data[78] => src13_data[78].DATAIN +sink_data[78] => src14_data[78].DATAIN +sink_data[78] => src15_data[78].DATAIN +sink_data[78] => src16_data[78].DATAIN +sink_data[79] => src17_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src2_data[79].DATAIN +sink_data[79] => src3_data[79].DATAIN +sink_data[79] => src4_data[79].DATAIN +sink_data[79] => src5_data[79].DATAIN +sink_data[79] => src6_data[79].DATAIN +sink_data[79] => src7_data[79].DATAIN +sink_data[79] => src8_data[79].DATAIN +sink_data[79] => src9_data[79].DATAIN +sink_data[79] => src10_data[79].DATAIN +sink_data[79] => src11_data[79].DATAIN +sink_data[79] => src12_data[79].DATAIN +sink_data[79] => src13_data[79].DATAIN +sink_data[79] => src14_data[79].DATAIN +sink_data[79] => src15_data[79].DATAIN +sink_data[79] => src16_data[79].DATAIN +sink_data[80] => src17_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src2_data[80].DATAIN +sink_data[80] => src3_data[80].DATAIN +sink_data[80] => src4_data[80].DATAIN +sink_data[80] => src5_data[80].DATAIN +sink_data[80] => src6_data[80].DATAIN +sink_data[80] => src7_data[80].DATAIN +sink_data[80] => src8_data[80].DATAIN +sink_data[80] => src9_data[80].DATAIN +sink_data[80] => src10_data[80].DATAIN +sink_data[80] => src11_data[80].DATAIN +sink_data[80] => src12_data[80].DATAIN +sink_data[80] => src13_data[80].DATAIN +sink_data[80] => src14_data[80].DATAIN +sink_data[80] => src15_data[80].DATAIN +sink_data[80] => src16_data[80].DATAIN +sink_data[81] => src17_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src2_data[81].DATAIN +sink_data[81] => src3_data[81].DATAIN +sink_data[81] => src4_data[81].DATAIN +sink_data[81] => src5_data[81].DATAIN +sink_data[81] => src6_data[81].DATAIN +sink_data[81] => src7_data[81].DATAIN +sink_data[81] => src8_data[81].DATAIN +sink_data[81] => src9_data[81].DATAIN +sink_data[81] => src10_data[81].DATAIN +sink_data[81] => src11_data[81].DATAIN +sink_data[81] => src12_data[81].DATAIN +sink_data[81] => src13_data[81].DATAIN +sink_data[81] => src14_data[81].DATAIN +sink_data[81] => src15_data[81].DATAIN +sink_data[81] => src16_data[81].DATAIN +sink_data[82] => src17_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src2_data[82].DATAIN +sink_data[82] => src3_data[82].DATAIN +sink_data[82] => src4_data[82].DATAIN +sink_data[82] => src5_data[82].DATAIN +sink_data[82] => src6_data[82].DATAIN +sink_data[82] => src7_data[82].DATAIN +sink_data[82] => src8_data[82].DATAIN +sink_data[82] => src9_data[82].DATAIN +sink_data[82] => src10_data[82].DATAIN +sink_data[82] => src11_data[82].DATAIN +sink_data[82] => src12_data[82].DATAIN +sink_data[82] => src13_data[82].DATAIN +sink_data[82] => src14_data[82].DATAIN +sink_data[82] => src15_data[82].DATAIN +sink_data[82] => src16_data[82].DATAIN +sink_data[83] => src17_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src2_data[83].DATAIN +sink_data[83] => src3_data[83].DATAIN +sink_data[83] => src4_data[83].DATAIN +sink_data[83] => src5_data[83].DATAIN +sink_data[83] => src6_data[83].DATAIN +sink_data[83] => src7_data[83].DATAIN +sink_data[83] => src8_data[83].DATAIN +sink_data[83] => src9_data[83].DATAIN +sink_data[83] => src10_data[83].DATAIN +sink_data[83] => src11_data[83].DATAIN +sink_data[83] => src12_data[83].DATAIN +sink_data[83] => src13_data[83].DATAIN +sink_data[83] => src14_data[83].DATAIN +sink_data[83] => src15_data[83].DATAIN +sink_data[83] => src16_data[83].DATAIN +sink_data[84] => src17_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src2_data[84].DATAIN +sink_data[84] => src3_data[84].DATAIN +sink_data[84] => src4_data[84].DATAIN +sink_data[84] => src5_data[84].DATAIN +sink_data[84] => src6_data[84].DATAIN +sink_data[84] => src7_data[84].DATAIN +sink_data[84] => src8_data[84].DATAIN +sink_data[84] => src9_data[84].DATAIN +sink_data[84] => src10_data[84].DATAIN +sink_data[84] => src11_data[84].DATAIN +sink_data[84] => src12_data[84].DATAIN +sink_data[84] => src13_data[84].DATAIN +sink_data[84] => src14_data[84].DATAIN +sink_data[84] => src15_data[84].DATAIN +sink_data[84] => src16_data[84].DATAIN +sink_data[85] => src17_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src2_data[85].DATAIN +sink_data[85] => src3_data[85].DATAIN +sink_data[85] => src4_data[85].DATAIN +sink_data[85] => src5_data[85].DATAIN +sink_data[85] => src6_data[85].DATAIN +sink_data[85] => src7_data[85].DATAIN +sink_data[85] => src8_data[85].DATAIN +sink_data[85] => src9_data[85].DATAIN +sink_data[85] => src10_data[85].DATAIN +sink_data[85] => src11_data[85].DATAIN +sink_data[85] => src12_data[85].DATAIN +sink_data[85] => src13_data[85].DATAIN +sink_data[85] => src14_data[85].DATAIN +sink_data[85] => src15_data[85].DATAIN +sink_data[85] => src16_data[85].DATAIN +sink_data[86] => src17_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src2_data[86].DATAIN +sink_data[86] => src3_data[86].DATAIN +sink_data[86] => src4_data[86].DATAIN +sink_data[86] => src5_data[86].DATAIN +sink_data[86] => src6_data[86].DATAIN +sink_data[86] => src7_data[86].DATAIN +sink_data[86] => src8_data[86].DATAIN +sink_data[86] => src9_data[86].DATAIN +sink_data[86] => src10_data[86].DATAIN +sink_data[86] => src11_data[86].DATAIN +sink_data[86] => src12_data[86].DATAIN +sink_data[86] => src13_data[86].DATAIN +sink_data[86] => src14_data[86].DATAIN +sink_data[86] => src15_data[86].DATAIN +sink_data[86] => src16_data[86].DATAIN +sink_data[87] => src17_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src2_data[87].DATAIN +sink_data[87] => src3_data[87].DATAIN +sink_data[87] => src4_data[87].DATAIN +sink_data[87] => src5_data[87].DATAIN +sink_data[87] => src6_data[87].DATAIN +sink_data[87] => src7_data[87].DATAIN +sink_data[87] => src8_data[87].DATAIN +sink_data[87] => src9_data[87].DATAIN +sink_data[87] => src10_data[87].DATAIN +sink_data[87] => src11_data[87].DATAIN +sink_data[87] => src12_data[87].DATAIN +sink_data[87] => src13_data[87].DATAIN +sink_data[87] => src14_data[87].DATAIN +sink_data[87] => src15_data[87].DATAIN +sink_data[87] => src16_data[87].DATAIN +sink_data[88] => src17_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src2_data[88].DATAIN +sink_data[88] => src3_data[88].DATAIN +sink_data[88] => src4_data[88].DATAIN +sink_data[88] => src5_data[88].DATAIN +sink_data[88] => src6_data[88].DATAIN +sink_data[88] => src7_data[88].DATAIN +sink_data[88] => src8_data[88].DATAIN +sink_data[88] => src9_data[88].DATAIN +sink_data[88] => src10_data[88].DATAIN +sink_data[88] => src11_data[88].DATAIN +sink_data[88] => src12_data[88].DATAIN +sink_data[88] => src13_data[88].DATAIN +sink_data[88] => src14_data[88].DATAIN +sink_data[88] => src15_data[88].DATAIN +sink_data[88] => src16_data[88].DATAIN +sink_data[89] => src17_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src2_data[89].DATAIN +sink_data[89] => src3_data[89].DATAIN +sink_data[89] => src4_data[89].DATAIN +sink_data[89] => src5_data[89].DATAIN +sink_data[89] => src6_data[89].DATAIN +sink_data[89] => src7_data[89].DATAIN +sink_data[89] => src8_data[89].DATAIN +sink_data[89] => src9_data[89].DATAIN +sink_data[89] => src10_data[89].DATAIN +sink_data[89] => src11_data[89].DATAIN +sink_data[89] => src12_data[89].DATAIN +sink_data[89] => src13_data[89].DATAIN +sink_data[89] => src14_data[89].DATAIN +sink_data[89] => src15_data[89].DATAIN +sink_data[89] => src16_data[89].DATAIN +sink_data[90] => src17_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src2_data[90].DATAIN +sink_data[90] => src3_data[90].DATAIN +sink_data[90] => src4_data[90].DATAIN +sink_data[90] => src5_data[90].DATAIN +sink_data[90] => src6_data[90].DATAIN +sink_data[90] => src7_data[90].DATAIN +sink_data[90] => src8_data[90].DATAIN +sink_data[90] => src9_data[90].DATAIN +sink_data[90] => src10_data[90].DATAIN +sink_data[90] => src11_data[90].DATAIN +sink_data[90] => src12_data[90].DATAIN +sink_data[90] => src13_data[90].DATAIN +sink_data[90] => src14_data[90].DATAIN +sink_data[90] => src15_data[90].DATAIN +sink_data[90] => src16_data[90].DATAIN +sink_data[91] => src17_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src2_data[91].DATAIN +sink_data[91] => src3_data[91].DATAIN +sink_data[91] => src4_data[91].DATAIN +sink_data[91] => src5_data[91].DATAIN +sink_data[91] => src6_data[91].DATAIN +sink_data[91] => src7_data[91].DATAIN +sink_data[91] => src8_data[91].DATAIN +sink_data[91] => src9_data[91].DATAIN +sink_data[91] => src10_data[91].DATAIN +sink_data[91] => src11_data[91].DATAIN +sink_data[91] => src12_data[91].DATAIN +sink_data[91] => src13_data[91].DATAIN +sink_data[91] => src14_data[91].DATAIN +sink_data[91] => src15_data[91].DATAIN +sink_data[91] => src16_data[91].DATAIN +sink_data[92] => src17_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src2_data[92].DATAIN +sink_data[92] => src3_data[92].DATAIN +sink_data[92] => src4_data[92].DATAIN +sink_data[92] => src5_data[92].DATAIN +sink_data[92] => src6_data[92].DATAIN +sink_data[92] => src7_data[92].DATAIN +sink_data[92] => src8_data[92].DATAIN +sink_data[92] => src9_data[92].DATAIN +sink_data[92] => src10_data[92].DATAIN +sink_data[92] => src11_data[92].DATAIN +sink_data[92] => src12_data[92].DATAIN +sink_data[92] => src13_data[92].DATAIN +sink_data[92] => src14_data[92].DATAIN +sink_data[92] => src15_data[92].DATAIN +sink_data[92] => src16_data[92].DATAIN +sink_data[93] => src17_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src2_data[93].DATAIN +sink_data[93] => src3_data[93].DATAIN +sink_data[93] => src4_data[93].DATAIN +sink_data[93] => src5_data[93].DATAIN +sink_data[93] => src6_data[93].DATAIN +sink_data[93] => src7_data[93].DATAIN +sink_data[93] => src8_data[93].DATAIN +sink_data[93] => src9_data[93].DATAIN +sink_data[93] => src10_data[93].DATAIN +sink_data[93] => src11_data[93].DATAIN +sink_data[93] => src12_data[93].DATAIN +sink_data[93] => src13_data[93].DATAIN +sink_data[93] => src14_data[93].DATAIN +sink_data[93] => src15_data[93].DATAIN +sink_data[93] => src16_data[93].DATAIN +sink_data[94] => src17_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src2_data[94].DATAIN +sink_data[94] => src3_data[94].DATAIN +sink_data[94] => src4_data[94].DATAIN +sink_data[94] => src5_data[94].DATAIN +sink_data[94] => src6_data[94].DATAIN +sink_data[94] => src7_data[94].DATAIN +sink_data[94] => src8_data[94].DATAIN +sink_data[94] => src9_data[94].DATAIN +sink_data[94] => src10_data[94].DATAIN +sink_data[94] => src11_data[94].DATAIN +sink_data[94] => src12_data[94].DATAIN +sink_data[94] => src13_data[94].DATAIN +sink_data[94] => src14_data[94].DATAIN +sink_data[94] => src15_data[94].DATAIN +sink_data[94] => src16_data[94].DATAIN +sink_data[95] => src17_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src2_data[95].DATAIN +sink_data[95] => src3_data[95].DATAIN +sink_data[95] => src4_data[95].DATAIN +sink_data[95] => src5_data[95].DATAIN +sink_data[95] => src6_data[95].DATAIN +sink_data[95] => src7_data[95].DATAIN +sink_data[95] => src8_data[95].DATAIN +sink_data[95] => src9_data[95].DATAIN +sink_data[95] => src10_data[95].DATAIN +sink_data[95] => src11_data[95].DATAIN +sink_data[95] => src12_data[95].DATAIN +sink_data[95] => src13_data[95].DATAIN +sink_data[95] => src14_data[95].DATAIN +sink_data[95] => src15_data[95].DATAIN +sink_data[95] => src16_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src2_valid.IN1 +sink_channel[2] => sink_ready.IN0 +sink_channel[3] => src3_valid.IN1 +sink_channel[3] => sink_ready.IN0 +sink_channel[4] => src4_valid.IN1 +sink_channel[4] => sink_ready.IN0 +sink_channel[5] => src5_valid.IN1 +sink_channel[5] => sink_ready.IN0 +sink_channel[6] => src6_valid.IN1 +sink_channel[6] => sink_ready.IN0 +sink_channel[7] => src7_valid.IN1 +sink_channel[7] => sink_ready.IN0 +sink_channel[8] => src8_valid.IN1 +sink_channel[8] => sink_ready.IN0 +sink_channel[9] => src9_valid.IN1 +sink_channel[9] => sink_ready.IN0 +sink_channel[10] => src10_valid.IN1 +sink_channel[10] => sink_ready.IN0 +sink_channel[11] => src11_valid.IN1 +sink_channel[11] => sink_ready.IN0 +sink_channel[12] => src12_valid.IN1 +sink_channel[12] => sink_ready.IN0 +sink_channel[13] => src13_valid.IN1 +sink_channel[13] => sink_ready.IN0 +sink_channel[14] => src14_valid.IN1 +sink_channel[14] => sink_ready.IN0 +sink_channel[15] => src15_valid.IN1 +sink_channel[15] => sink_ready.IN0 +sink_channel[16] => src16_valid.IN1 +sink_channel[16] => sink_ready.IN0 +sink_channel[17] => src17_valid.IN1 +sink_channel[17] => sink_ready.IN0 +sink_startofpacket => src17_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src2_startofpacket.DATAIN +sink_startofpacket => src3_startofpacket.DATAIN +sink_startofpacket => src4_startofpacket.DATAIN +sink_startofpacket => src5_startofpacket.DATAIN +sink_startofpacket => src6_startofpacket.DATAIN +sink_startofpacket => src7_startofpacket.DATAIN +sink_startofpacket => src8_startofpacket.DATAIN +sink_startofpacket => src9_startofpacket.DATAIN +sink_startofpacket => src10_startofpacket.DATAIN +sink_startofpacket => src11_startofpacket.DATAIN +sink_startofpacket => src12_startofpacket.DATAIN +sink_startofpacket => src13_startofpacket.DATAIN +sink_startofpacket => src14_startofpacket.DATAIN +sink_startofpacket => src15_startofpacket.DATAIN +sink_startofpacket => src16_startofpacket.DATAIN +sink_endofpacket => src17_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src2_endofpacket.DATAIN +sink_endofpacket => src3_endofpacket.DATAIN +sink_endofpacket => src4_endofpacket.DATAIN +sink_endofpacket => src5_endofpacket.DATAIN +sink_endofpacket => src6_endofpacket.DATAIN +sink_endofpacket => src7_endofpacket.DATAIN +sink_endofpacket => src8_endofpacket.DATAIN +sink_endofpacket => src9_endofpacket.DATAIN +sink_endofpacket => src10_endofpacket.DATAIN +sink_endofpacket => src11_endofpacket.DATAIN +sink_endofpacket => src12_endofpacket.DATAIN +sink_endofpacket => src13_endofpacket.DATAIN +sink_endofpacket => src14_endofpacket.DATAIN +sink_endofpacket => src15_endofpacket.DATAIN +sink_endofpacket => src16_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= +src0_channel[1] <= +src0_channel[2] <= +src0_channel[3] <= +src0_channel[4] <= +src0_channel[5] <= +src0_channel[6] <= +src0_channel[7] <= +src0_channel[8] <= +src0_channel[9] <= +src0_channel[10] <= +src0_channel[11] <= +src0_channel[12] <= +src0_channel[13] <= +src0_channel[14] <= +src0_channel[15] <= +src0_channel[16] <= +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= +src1_channel[1] <= +src1_channel[2] <= +src1_channel[3] <= +src1_channel[4] <= +src1_channel[5] <= +src1_channel[6] <= +src1_channel[7] <= +src1_channel[8] <= +src1_channel[9] <= +src1_channel[10] <= +src1_channel[11] <= +src1_channel[12] <= +src1_channel[13] <= +src1_channel[14] <= +src1_channel[15] <= +src1_channel[16] <= +src1_channel[17] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +src2_valid <= src2_valid.DB_MAX_OUTPUT_PORT_TYPE +src2_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src2_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src2_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src2_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src2_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src2_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src2_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src2_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src2_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src2_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src2_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src2_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src2_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src2_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src2_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src2_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src2_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src2_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src2_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src2_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src2_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src2_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src2_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src2_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src2_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src2_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src2_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src2_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src2_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src2_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src2_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src2_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src2_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src2_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src2_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src2_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src2_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src2_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src2_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src2_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src2_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src2_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src2_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src2_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src2_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src2_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src2_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src2_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src2_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src2_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src2_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src2_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src2_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src2_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src2_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src2_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src2_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src2_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src2_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src2_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src2_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src2_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src2_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src2_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src2_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src2_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src2_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src2_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src2_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src2_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src2_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src2_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src2_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src2_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src2_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src2_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src2_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src2_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src2_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src2_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src2_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src2_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src2_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src2_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src2_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src2_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src2_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src2_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src2_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src2_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src2_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src2_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src2_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src2_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src2_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src2_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src2_channel[0] <= +src2_channel[1] <= +src2_channel[2] <= +src2_channel[3] <= +src2_channel[4] <= +src2_channel[5] <= +src2_channel[6] <= +src2_channel[7] <= +src2_channel[8] <= +src2_channel[9] <= +src2_channel[10] <= +src2_channel[11] <= +src2_channel[12] <= +src2_channel[13] <= +src2_channel[14] <= +src2_channel[15] <= +src2_channel[16] <= +src2_channel[17] <= +src2_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src2_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src2_ready => sink_ready.IN1 +src3_valid <= src3_valid.DB_MAX_OUTPUT_PORT_TYPE +src3_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src3_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src3_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src3_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src3_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src3_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src3_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src3_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src3_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src3_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src3_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src3_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src3_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src3_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src3_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src3_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src3_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src3_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src3_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src3_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src3_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src3_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src3_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src3_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src3_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src3_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src3_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src3_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src3_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src3_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src3_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src3_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src3_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src3_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src3_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src3_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src3_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src3_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src3_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src3_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src3_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src3_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src3_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src3_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src3_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src3_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src3_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src3_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src3_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src3_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src3_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src3_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src3_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src3_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src3_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src3_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src3_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src3_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src3_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src3_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src3_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src3_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src3_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src3_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src3_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src3_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src3_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src3_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src3_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src3_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src3_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src3_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src3_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src3_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src3_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src3_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src3_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src3_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src3_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src3_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src3_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src3_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src3_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src3_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src3_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src3_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src3_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src3_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src3_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src3_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src3_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src3_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src3_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src3_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src3_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src3_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src3_channel[0] <= +src3_channel[1] <= +src3_channel[2] <= +src3_channel[3] <= +src3_channel[4] <= +src3_channel[5] <= +src3_channel[6] <= +src3_channel[7] <= +src3_channel[8] <= +src3_channel[9] <= +src3_channel[10] <= +src3_channel[11] <= +src3_channel[12] <= +src3_channel[13] <= +src3_channel[14] <= +src3_channel[15] <= +src3_channel[16] <= +src3_channel[17] <= +src3_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src3_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src3_ready => sink_ready.IN1 +src4_valid <= src4_valid.DB_MAX_OUTPUT_PORT_TYPE +src4_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src4_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src4_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src4_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src4_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src4_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src4_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src4_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src4_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src4_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src4_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src4_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src4_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src4_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src4_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src4_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src4_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src4_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src4_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src4_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src4_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src4_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src4_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src4_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src4_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src4_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src4_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src4_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src4_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src4_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src4_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src4_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src4_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src4_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src4_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src4_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src4_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src4_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src4_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src4_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src4_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src4_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src4_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src4_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src4_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src4_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src4_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src4_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src4_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src4_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src4_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src4_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src4_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src4_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src4_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src4_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src4_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src4_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src4_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src4_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src4_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src4_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src4_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src4_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src4_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src4_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src4_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src4_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src4_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src4_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src4_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src4_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src4_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src4_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src4_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src4_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src4_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src4_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src4_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src4_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src4_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src4_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src4_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src4_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src4_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src4_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src4_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src4_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src4_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src4_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src4_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src4_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src4_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src4_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src4_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src4_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src4_channel[0] <= +src4_channel[1] <= +src4_channel[2] <= +src4_channel[3] <= +src4_channel[4] <= +src4_channel[5] <= +src4_channel[6] <= +src4_channel[7] <= +src4_channel[8] <= +src4_channel[9] <= +src4_channel[10] <= +src4_channel[11] <= +src4_channel[12] <= +src4_channel[13] <= +src4_channel[14] <= +src4_channel[15] <= +src4_channel[16] <= +src4_channel[17] <= +src4_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src4_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src4_ready => sink_ready.IN1 +src5_valid <= src5_valid.DB_MAX_OUTPUT_PORT_TYPE +src5_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src5_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src5_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src5_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src5_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src5_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src5_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src5_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src5_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src5_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src5_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src5_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src5_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src5_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src5_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src5_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src5_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src5_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src5_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src5_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src5_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src5_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src5_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src5_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src5_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src5_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src5_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src5_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src5_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src5_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src5_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src5_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src5_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src5_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src5_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src5_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src5_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src5_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src5_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src5_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src5_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src5_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src5_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src5_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src5_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src5_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src5_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src5_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src5_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src5_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src5_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src5_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src5_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src5_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src5_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src5_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src5_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src5_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src5_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src5_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src5_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src5_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src5_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src5_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src5_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src5_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src5_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src5_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src5_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src5_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src5_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src5_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src5_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src5_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src5_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src5_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src5_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src5_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src5_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src5_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src5_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src5_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src5_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src5_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src5_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src5_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src5_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src5_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src5_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src5_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src5_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src5_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src5_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src5_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src5_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src5_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src5_channel[0] <= +src5_channel[1] <= +src5_channel[2] <= +src5_channel[3] <= +src5_channel[4] <= +src5_channel[5] <= +src5_channel[6] <= +src5_channel[7] <= +src5_channel[8] <= +src5_channel[9] <= +src5_channel[10] <= +src5_channel[11] <= +src5_channel[12] <= +src5_channel[13] <= +src5_channel[14] <= +src5_channel[15] <= +src5_channel[16] <= +src5_channel[17] <= +src5_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src5_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src5_ready => sink_ready.IN1 +src6_valid <= src6_valid.DB_MAX_OUTPUT_PORT_TYPE +src6_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src6_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src6_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src6_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src6_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src6_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src6_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src6_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src6_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src6_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src6_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src6_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src6_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src6_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src6_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src6_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src6_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src6_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src6_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src6_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src6_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src6_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src6_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src6_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src6_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src6_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src6_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src6_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src6_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src6_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src6_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src6_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src6_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src6_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src6_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src6_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src6_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src6_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src6_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src6_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src6_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src6_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src6_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src6_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src6_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src6_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src6_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src6_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src6_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src6_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src6_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src6_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src6_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src6_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src6_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src6_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src6_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src6_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src6_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src6_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src6_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src6_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src6_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src6_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src6_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src6_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src6_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src6_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src6_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src6_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src6_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src6_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src6_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src6_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src6_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src6_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src6_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src6_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src6_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src6_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src6_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src6_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src6_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src6_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src6_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src6_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src6_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src6_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src6_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src6_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src6_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src6_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src6_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src6_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src6_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src6_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src6_channel[0] <= +src6_channel[1] <= +src6_channel[2] <= +src6_channel[3] <= +src6_channel[4] <= +src6_channel[5] <= +src6_channel[6] <= +src6_channel[7] <= +src6_channel[8] <= +src6_channel[9] <= +src6_channel[10] <= +src6_channel[11] <= +src6_channel[12] <= +src6_channel[13] <= +src6_channel[14] <= +src6_channel[15] <= +src6_channel[16] <= +src6_channel[17] <= +src6_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src6_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src6_ready => sink_ready.IN1 +src7_valid <= src7_valid.DB_MAX_OUTPUT_PORT_TYPE +src7_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src7_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src7_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src7_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src7_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src7_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src7_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src7_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src7_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src7_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src7_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src7_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src7_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src7_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src7_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src7_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src7_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src7_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src7_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src7_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src7_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src7_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src7_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src7_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src7_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src7_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src7_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src7_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src7_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src7_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src7_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src7_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src7_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src7_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src7_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src7_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src7_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src7_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src7_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src7_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src7_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src7_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src7_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src7_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src7_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src7_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src7_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src7_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src7_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src7_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src7_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src7_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src7_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src7_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src7_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src7_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src7_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src7_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src7_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src7_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src7_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src7_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src7_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src7_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src7_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src7_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src7_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src7_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src7_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src7_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src7_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src7_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src7_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src7_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src7_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src7_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src7_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src7_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src7_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src7_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src7_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src7_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src7_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src7_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src7_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src7_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src7_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src7_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src7_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src7_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src7_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src7_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src7_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src7_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src7_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src7_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src7_channel[0] <= +src7_channel[1] <= +src7_channel[2] <= +src7_channel[3] <= +src7_channel[4] <= +src7_channel[5] <= +src7_channel[6] <= +src7_channel[7] <= +src7_channel[8] <= +src7_channel[9] <= +src7_channel[10] <= +src7_channel[11] <= +src7_channel[12] <= +src7_channel[13] <= +src7_channel[14] <= +src7_channel[15] <= +src7_channel[16] <= +src7_channel[17] <= +src7_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src7_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src7_ready => sink_ready.IN1 +src8_valid <= src8_valid.DB_MAX_OUTPUT_PORT_TYPE +src8_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src8_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src8_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src8_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src8_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src8_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src8_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src8_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src8_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src8_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src8_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src8_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src8_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src8_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src8_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src8_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src8_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src8_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src8_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src8_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src8_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src8_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src8_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src8_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src8_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src8_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src8_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src8_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src8_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src8_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src8_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src8_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src8_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src8_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src8_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src8_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src8_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src8_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src8_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src8_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src8_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src8_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src8_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src8_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src8_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src8_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src8_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src8_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src8_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src8_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src8_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src8_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src8_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src8_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src8_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src8_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src8_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src8_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src8_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src8_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src8_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src8_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src8_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src8_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src8_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src8_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src8_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src8_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src8_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src8_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src8_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src8_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src8_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src8_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src8_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src8_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src8_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src8_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src8_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src8_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src8_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src8_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src8_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src8_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src8_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src8_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src8_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src8_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src8_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src8_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src8_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src8_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src8_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src8_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src8_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src8_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src8_channel[0] <= +src8_channel[1] <= +src8_channel[2] <= +src8_channel[3] <= +src8_channel[4] <= +src8_channel[5] <= +src8_channel[6] <= +src8_channel[7] <= +src8_channel[8] <= +src8_channel[9] <= +src8_channel[10] <= +src8_channel[11] <= +src8_channel[12] <= +src8_channel[13] <= +src8_channel[14] <= +src8_channel[15] <= +src8_channel[16] <= +src8_channel[17] <= +src8_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src8_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src8_ready => sink_ready.IN1 +src9_valid <= src9_valid.DB_MAX_OUTPUT_PORT_TYPE +src9_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src9_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src9_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src9_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src9_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src9_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src9_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src9_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src9_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src9_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src9_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src9_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src9_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src9_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src9_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src9_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src9_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src9_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src9_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src9_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src9_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src9_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src9_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src9_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src9_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src9_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src9_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src9_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src9_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src9_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src9_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src9_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src9_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src9_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src9_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src9_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src9_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src9_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src9_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src9_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src9_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src9_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src9_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src9_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src9_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src9_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src9_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src9_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src9_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src9_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src9_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src9_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src9_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src9_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src9_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src9_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src9_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src9_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src9_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src9_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src9_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src9_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src9_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src9_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src9_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src9_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src9_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src9_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src9_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src9_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src9_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src9_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src9_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src9_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src9_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src9_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src9_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src9_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src9_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src9_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src9_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src9_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src9_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src9_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src9_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src9_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src9_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src9_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src9_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src9_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src9_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src9_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src9_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src9_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src9_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src9_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src9_channel[0] <= +src9_channel[1] <= +src9_channel[2] <= +src9_channel[3] <= +src9_channel[4] <= +src9_channel[5] <= +src9_channel[6] <= +src9_channel[7] <= +src9_channel[8] <= +src9_channel[9] <= +src9_channel[10] <= +src9_channel[11] <= +src9_channel[12] <= +src9_channel[13] <= +src9_channel[14] <= +src9_channel[15] <= +src9_channel[16] <= +src9_channel[17] <= +src9_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src9_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src9_ready => sink_ready.IN1 +src10_valid <= src10_valid.DB_MAX_OUTPUT_PORT_TYPE +src10_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src10_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src10_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src10_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src10_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src10_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src10_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src10_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src10_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src10_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src10_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src10_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src10_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src10_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src10_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src10_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src10_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src10_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src10_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src10_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src10_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src10_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src10_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src10_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src10_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src10_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src10_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src10_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src10_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src10_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src10_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src10_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src10_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src10_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src10_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src10_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src10_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src10_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src10_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src10_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src10_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src10_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src10_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src10_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src10_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src10_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src10_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src10_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src10_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src10_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src10_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src10_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src10_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src10_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src10_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src10_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src10_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src10_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src10_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src10_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src10_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src10_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src10_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src10_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src10_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src10_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src10_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src10_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src10_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src10_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src10_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src10_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src10_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src10_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src10_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src10_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src10_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src10_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src10_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src10_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src10_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src10_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src10_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src10_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src10_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src10_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src10_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src10_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src10_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src10_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src10_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src10_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src10_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src10_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src10_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src10_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src10_channel[0] <= +src10_channel[1] <= +src10_channel[2] <= +src10_channel[3] <= +src10_channel[4] <= +src10_channel[5] <= +src10_channel[6] <= +src10_channel[7] <= +src10_channel[8] <= +src10_channel[9] <= +src10_channel[10] <= +src10_channel[11] <= +src10_channel[12] <= +src10_channel[13] <= +src10_channel[14] <= +src10_channel[15] <= +src10_channel[16] <= +src10_channel[17] <= +src10_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src10_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src10_ready => sink_ready.IN1 +src11_valid <= src11_valid.DB_MAX_OUTPUT_PORT_TYPE +src11_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src11_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src11_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src11_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src11_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src11_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src11_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src11_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src11_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src11_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src11_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src11_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src11_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src11_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src11_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src11_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src11_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src11_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src11_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src11_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src11_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src11_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src11_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src11_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src11_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src11_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src11_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src11_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src11_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src11_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src11_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src11_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src11_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src11_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src11_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src11_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src11_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src11_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src11_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src11_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src11_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src11_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src11_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src11_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src11_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src11_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src11_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src11_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src11_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src11_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src11_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src11_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src11_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src11_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src11_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src11_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src11_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src11_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src11_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src11_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src11_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src11_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src11_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src11_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src11_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src11_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src11_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src11_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src11_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src11_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src11_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src11_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src11_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src11_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src11_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src11_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src11_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src11_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src11_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src11_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src11_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src11_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src11_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src11_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src11_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src11_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src11_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src11_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src11_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src11_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src11_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src11_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src11_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src11_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src11_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src11_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src11_channel[0] <= +src11_channel[1] <= +src11_channel[2] <= +src11_channel[3] <= +src11_channel[4] <= +src11_channel[5] <= +src11_channel[6] <= +src11_channel[7] <= +src11_channel[8] <= +src11_channel[9] <= +src11_channel[10] <= +src11_channel[11] <= +src11_channel[12] <= +src11_channel[13] <= +src11_channel[14] <= +src11_channel[15] <= +src11_channel[16] <= +src11_channel[17] <= +src11_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src11_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src11_ready => sink_ready.IN1 +src12_valid <= src12_valid.DB_MAX_OUTPUT_PORT_TYPE +src12_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src12_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src12_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src12_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src12_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src12_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src12_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src12_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src12_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src12_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src12_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src12_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src12_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src12_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src12_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src12_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src12_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src12_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src12_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src12_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src12_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src12_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src12_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src12_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src12_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src12_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src12_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src12_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src12_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src12_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src12_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src12_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src12_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src12_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src12_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src12_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src12_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src12_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src12_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src12_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src12_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src12_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src12_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src12_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src12_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src12_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src12_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src12_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src12_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src12_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src12_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src12_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src12_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src12_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src12_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src12_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src12_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src12_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src12_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src12_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src12_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src12_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src12_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src12_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src12_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src12_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src12_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src12_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src12_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src12_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src12_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src12_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src12_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src12_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src12_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src12_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src12_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src12_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src12_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src12_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src12_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src12_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src12_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src12_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src12_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src12_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src12_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src12_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src12_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src12_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src12_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src12_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src12_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src12_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src12_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src12_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src12_channel[0] <= +src12_channel[1] <= +src12_channel[2] <= +src12_channel[3] <= +src12_channel[4] <= +src12_channel[5] <= +src12_channel[6] <= +src12_channel[7] <= +src12_channel[8] <= +src12_channel[9] <= +src12_channel[10] <= +src12_channel[11] <= +src12_channel[12] <= +src12_channel[13] <= +src12_channel[14] <= +src12_channel[15] <= +src12_channel[16] <= +src12_channel[17] <= +src12_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src12_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src12_ready => sink_ready.IN1 +src13_valid <= src13_valid.DB_MAX_OUTPUT_PORT_TYPE +src13_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src13_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src13_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src13_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src13_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src13_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src13_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src13_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src13_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src13_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src13_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src13_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src13_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src13_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src13_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src13_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src13_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src13_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src13_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src13_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src13_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src13_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src13_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src13_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src13_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src13_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src13_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src13_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src13_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src13_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src13_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src13_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src13_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src13_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src13_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src13_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src13_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src13_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src13_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src13_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src13_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src13_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src13_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src13_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src13_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src13_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src13_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src13_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src13_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src13_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src13_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src13_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src13_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src13_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src13_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src13_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src13_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src13_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src13_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src13_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src13_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src13_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src13_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src13_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src13_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src13_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src13_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src13_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src13_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src13_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src13_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src13_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src13_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src13_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src13_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src13_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src13_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src13_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src13_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src13_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src13_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src13_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src13_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src13_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src13_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src13_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src13_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src13_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src13_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src13_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src13_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src13_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src13_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src13_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src13_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src13_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src13_channel[0] <= +src13_channel[1] <= +src13_channel[2] <= +src13_channel[3] <= +src13_channel[4] <= +src13_channel[5] <= +src13_channel[6] <= +src13_channel[7] <= +src13_channel[8] <= +src13_channel[9] <= +src13_channel[10] <= +src13_channel[11] <= +src13_channel[12] <= +src13_channel[13] <= +src13_channel[14] <= +src13_channel[15] <= +src13_channel[16] <= +src13_channel[17] <= +src13_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src13_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src13_ready => sink_ready.IN1 +src14_valid <= src14_valid.DB_MAX_OUTPUT_PORT_TYPE +src14_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src14_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src14_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src14_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src14_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src14_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src14_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src14_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src14_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src14_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src14_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src14_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src14_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src14_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src14_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src14_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src14_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src14_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src14_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src14_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src14_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src14_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src14_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src14_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src14_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src14_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src14_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src14_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src14_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src14_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src14_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src14_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src14_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src14_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src14_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src14_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src14_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src14_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src14_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src14_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src14_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src14_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src14_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src14_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src14_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src14_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src14_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src14_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src14_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src14_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src14_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src14_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src14_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src14_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src14_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src14_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src14_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src14_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src14_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src14_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src14_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src14_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src14_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src14_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src14_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src14_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src14_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src14_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src14_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src14_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src14_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src14_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src14_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src14_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src14_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src14_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src14_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src14_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src14_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src14_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src14_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src14_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src14_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src14_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src14_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src14_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src14_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src14_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src14_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src14_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src14_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src14_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src14_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src14_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src14_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src14_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src14_channel[0] <= +src14_channel[1] <= +src14_channel[2] <= +src14_channel[3] <= +src14_channel[4] <= +src14_channel[5] <= +src14_channel[6] <= +src14_channel[7] <= +src14_channel[8] <= +src14_channel[9] <= +src14_channel[10] <= +src14_channel[11] <= +src14_channel[12] <= +src14_channel[13] <= +src14_channel[14] <= +src14_channel[15] <= +src14_channel[16] <= +src14_channel[17] <= +src14_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src14_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src14_ready => sink_ready.IN1 +src15_valid <= src15_valid.DB_MAX_OUTPUT_PORT_TYPE +src15_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src15_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src15_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src15_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src15_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src15_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src15_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src15_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src15_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src15_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src15_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src15_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src15_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src15_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src15_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src15_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src15_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src15_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src15_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src15_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src15_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src15_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src15_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src15_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src15_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src15_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src15_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src15_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src15_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src15_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src15_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src15_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src15_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src15_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src15_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src15_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src15_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src15_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src15_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src15_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src15_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src15_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src15_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src15_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src15_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src15_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src15_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src15_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src15_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src15_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src15_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src15_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src15_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src15_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src15_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src15_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src15_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src15_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src15_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src15_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src15_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src15_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src15_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src15_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src15_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src15_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src15_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src15_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src15_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src15_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src15_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src15_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src15_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src15_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src15_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src15_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src15_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src15_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src15_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src15_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src15_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src15_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src15_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src15_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src15_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src15_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src15_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src15_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src15_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src15_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src15_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src15_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src15_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src15_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src15_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src15_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src15_channel[0] <= +src15_channel[1] <= +src15_channel[2] <= +src15_channel[3] <= +src15_channel[4] <= +src15_channel[5] <= +src15_channel[6] <= +src15_channel[7] <= +src15_channel[8] <= +src15_channel[9] <= +src15_channel[10] <= +src15_channel[11] <= +src15_channel[12] <= +src15_channel[13] <= +src15_channel[14] <= +src15_channel[15] <= +src15_channel[16] <= +src15_channel[17] <= +src15_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src15_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src15_ready => sink_ready.IN1 +src16_valid <= src16_valid.DB_MAX_OUTPUT_PORT_TYPE +src16_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src16_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src16_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src16_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src16_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src16_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src16_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src16_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src16_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src16_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src16_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src16_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src16_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src16_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src16_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src16_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src16_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src16_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src16_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src16_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src16_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src16_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src16_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src16_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src16_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src16_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src16_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src16_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src16_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src16_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src16_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src16_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src16_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src16_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src16_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src16_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src16_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src16_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src16_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src16_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src16_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src16_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src16_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src16_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src16_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src16_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src16_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src16_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src16_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src16_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src16_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src16_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src16_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src16_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src16_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src16_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src16_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src16_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src16_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src16_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src16_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src16_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src16_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src16_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src16_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src16_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src16_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src16_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src16_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src16_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src16_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src16_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src16_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src16_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src16_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src16_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src16_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src16_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src16_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src16_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src16_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src16_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src16_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src16_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src16_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src16_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src16_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src16_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src16_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src16_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src16_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src16_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src16_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src16_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src16_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src16_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src16_channel[0] <= +src16_channel[1] <= +src16_channel[2] <= +src16_channel[3] <= +src16_channel[4] <= +src16_channel[5] <= +src16_channel[6] <= +src16_channel[7] <= +src16_channel[8] <= +src16_channel[9] <= +src16_channel[10] <= +src16_channel[11] <= +src16_channel[12] <= +src16_channel[13] <= +src16_channel[14] <= +src16_channel[15] <= +src16_channel[16] <= +src16_channel[17] <= +src16_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src16_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src16_ready => sink_ready.IN1 +src17_valid <= src17_valid.DB_MAX_OUTPUT_PORT_TYPE +src17_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src17_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src17_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src17_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src17_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src17_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src17_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src17_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src17_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src17_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src17_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src17_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src17_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src17_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src17_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src17_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src17_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src17_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src17_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src17_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src17_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src17_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src17_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src17_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src17_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src17_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src17_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src17_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src17_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src17_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src17_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src17_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src17_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src17_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src17_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src17_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src17_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src17_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src17_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src17_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src17_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src17_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src17_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src17_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src17_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src17_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src17_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src17_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src17_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src17_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src17_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src17_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src17_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src17_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src17_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src17_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src17_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src17_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src17_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src17_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src17_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src17_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src17_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src17_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src17_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src17_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src17_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src17_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src17_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src17_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src17_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src17_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src17_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src17_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src17_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src17_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src17_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src17_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src17_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src17_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src17_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src17_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src17_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src17_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src17_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src17_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src17_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src17_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src17_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src17_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src17_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src17_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src17_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src17_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src17_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src17_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src17_channel[0] <= +src17_channel[1] <= +src17_channel[2] <= +src17_channel[3] <= +src17_channel[4] <= +src17_channel[5] <= +src17_channel[6] <= +src17_channel[7] <= +src17_channel[8] <= +src17_channel[9] <= +src17_channel[10] <= +src17_channel[11] <= +src17_channel[12] <= +src17_channel[13] <= +src17_channel[14] <= +src17_channel[15] <= +src17_channel[16] <= +src17_channel[17] <= +src17_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src17_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src17_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux +sink0_valid => request.IN1 +sink0_valid => src_valid.IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => locked.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_channel[11] => src_payload.IN1 +sink0_channel[12] => src_payload.IN1 +sink0_channel[13] => src_payload.IN1 +sink0_channel[14] => src_payload.IN1 +sink0_channel[15] => src_payload.IN1 +sink0_channel[16] => src_payload.IN1 +sink0_channel[17] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request.IN1 +sink1_valid => src_valid.IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => locked.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_channel[11] => src_payload.IN1 +sink1_channel[12] => src_payload.IN1 +sink1_channel[13] => src_payload.IN1 +sink1_channel[14] => src_payload.IN1 +sink1_channel[15] => src_payload.IN1 +sink1_channel[16] => src_payload.IN1 +sink1_channel[17] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb +clk => top_priority_reg[0].CLK +clk => top_priority_reg[1].CLK +reset => top_priority_reg[0].PRESET +reset => top_priority_reg[1].ACLR +request[0] => grant_double_vector[0].IN1 +request[0] => grant_double_vector[2].IN1 +request[0] => WideOr0.IN0 +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant_double_vector[1].IN1 +request[1] => grant_double_vector[3].IN1 +request[1] => WideOr0.IN1 +request[1] => _.IN1 +request[1] => _.IN1 +grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => top_priority_reg.OUTPUTSELECT +increment_top_priority => top_priority_reg.OUTPUTSELECT +save_top_priority => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => sum.IN0 +a[0] => full_adder.cout[0].IN0 +a[1] => cout.IN0 +a[1] => cout.IN0 +a[2] => cout.IN0 +a[2] => cout.IN0 +a[3] => sum.IN0 +b[0] => sum.IN1 +b[0] => full_adder.cout[0].IN1 +b[1] => cout.IN1 +b[1] => cout.IN1 +b[2] => cout.IN1 +b[2] => cout.IN1 +b[3] => sum.IN1 +sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 +sink0_valid => request.IN1 +sink0_valid => src_valid.IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => locked.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_channel[11] => src_payload.IN1 +sink0_channel[12] => src_payload.IN1 +sink0_channel[13] => src_payload.IN1 +sink0_channel[14] => src_payload.IN1 +sink0_channel[15] => src_payload.IN1 +sink0_channel[16] => src_payload.IN1 +sink0_channel[17] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request.IN1 +sink1_valid => src_valid.IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => locked.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_channel[11] => src_payload.IN1 +sink1_channel[12] => src_payload.IN1 +sink1_channel[13] => src_payload.IN1 +sink1_channel[14] => src_payload.IN1 +sink1_channel[15] => src_payload.IN1 +sink1_channel[16] => src_payload.IN1 +sink1_channel[17] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb +clk => top_priority_reg[0].CLK +clk => top_priority_reg[1].CLK +reset => top_priority_reg[0].PRESET +reset => top_priority_reg[1].ACLR +request[0] => grant_double_vector[0].IN1 +request[0] => grant_double_vector[2].IN1 +request[0] => WideOr0.IN0 +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant_double_vector[1].IN1 +request[1] => grant_double_vector[3].IN1 +request[1] => WideOr0.IN1 +request[1] => _.IN1 +request[1] => _.IN1 +grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => top_priority_reg.OUTPUTSELECT +increment_top_priority => top_priority_reg.OUTPUTSELECT +save_top_priority => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => sum.IN0 +a[0] => full_adder.cout[0].IN0 +a[1] => cout.IN0 +a[1] => cout.IN0 +a[2] => cout.IN0 +a[2] => cout.IN0 +a[3] => sum.IN0 +b[0] => sum.IN1 +b[0] => full_adder.cout[0].IN1 +b[1] => cout.IN1 +b[1] => cout.IN1 +b[2] => cout.IN1 +b[2] => cout.IN1 +b[3] => sum.IN1 +sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux +sink_valid[0] => src0_valid.IN0 +sink_valid[0] => src1_valid.IN0 +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src1_channel[0].DATAIN +sink_channel[2] => src0_channel[0].DATAIN +sink_channel[3] => src1_channel[1].DATAIN +sink_channel[3] => src0_channel[1].DATAIN +sink_channel[4] => src1_channel[2].DATAIN +sink_channel[4] => src0_channel[2].DATAIN +sink_channel[5] => src1_channel[3].DATAIN +sink_channel[5] => src0_channel[3].DATAIN +sink_channel[6] => src1_channel[4].DATAIN +sink_channel[6] => src0_channel[4].DATAIN +sink_channel[7] => src1_channel[5].DATAIN +sink_channel[7] => src0_channel[5].DATAIN +sink_channel[8] => src1_channel[6].DATAIN +sink_channel[8] => src0_channel[6].DATAIN +sink_channel[9] => src1_channel[7].DATAIN +sink_channel[9] => src0_channel[7].DATAIN +sink_channel[10] => src1_channel[8].DATAIN +sink_channel[10] => src0_channel[8].DATAIN +sink_channel[11] => src1_channel[9].DATAIN +sink_channel[11] => src0_channel[9].DATAIN +sink_channel[12] => src1_channel[10].DATAIN +sink_channel[12] => src0_channel[10].DATAIN +sink_channel[13] => src1_channel[11].DATAIN +sink_channel[13] => src0_channel[11].DATAIN +sink_channel[14] => src1_channel[12].DATAIN +sink_channel[14] => src0_channel[12].DATAIN +sink_channel[15] => src1_channel[13].DATAIN +sink_channel[15] => src0_channel[13].DATAIN +sink_channel[16] => src1_channel[14].DATAIN +sink_channel[16] => src0_channel[14].DATAIN +sink_channel[17] => src1_channel[15].DATAIN +sink_channel[17] => src0_channel[15].DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[16] <= +src1_channel[17] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 +sink_valid[0] => src0_valid.IN0 +sink_valid[0] => src1_valid.IN0 +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src1_channel[0].DATAIN +sink_channel[2] => src0_channel[0].DATAIN +sink_channel[3] => src1_channel[1].DATAIN +sink_channel[3] => src0_channel[1].DATAIN +sink_channel[4] => src1_channel[2].DATAIN +sink_channel[4] => src0_channel[2].DATAIN +sink_channel[5] => src1_channel[3].DATAIN +sink_channel[5] => src0_channel[3].DATAIN +sink_channel[6] => src1_channel[4].DATAIN +sink_channel[6] => src0_channel[4].DATAIN +sink_channel[7] => src1_channel[5].DATAIN +sink_channel[7] => src0_channel[5].DATAIN +sink_channel[8] => src1_channel[6].DATAIN +sink_channel[8] => src0_channel[6].DATAIN +sink_channel[9] => src1_channel[7].DATAIN +sink_channel[9] => src0_channel[7].DATAIN +sink_channel[10] => src1_channel[8].DATAIN +sink_channel[10] => src0_channel[8].DATAIN +sink_channel[11] => src1_channel[9].DATAIN +sink_channel[11] => src0_channel[9].DATAIN +sink_channel[12] => src1_channel[10].DATAIN +sink_channel[12] => src0_channel[10].DATAIN +sink_channel[13] => src1_channel[11].DATAIN +sink_channel[13] => src0_channel[11].DATAIN +sink_channel[14] => src1_channel[12].DATAIN +sink_channel[14] => src0_channel[12].DATAIN +sink_channel[15] => src1_channel[13].DATAIN +sink_channel[15] => src0_channel[13].DATAIN +sink_channel[16] => src1_channel[14].DATAIN +sink_channel[16] => src0_channel[14].DATAIN +sink_channel[17] => src1_channel[15].DATAIN +sink_channel[17] => src0_channel[15].DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[9] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[10] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[11] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[12] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[13] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[14] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[15] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[16] <= +src1_channel[17] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_channel[11] => src0_channel[10].DATAIN +sink_channel[12] => src0_channel[11].DATAIN +sink_channel[13] => src0_channel[12].DATAIN +sink_channel[14] => src0_channel[13].DATAIN +sink_channel[15] => src0_channel[14].DATAIN +sink_channel[16] => src0_channel[15].DATAIN +sink_channel[17] => src0_channel[16].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= sink_channel[11].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[11] <= sink_channel[12].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[12] <= sink_channel[13].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[13] <= sink_channel[14].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[14] <= sink_channel[15].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[15] <= sink_channel[16].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[16] <= sink_channel[17].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[17] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux +sink0_valid => request[0].IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[59] => last_cycle.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_channel[11] => src_payload.IN1 +sink0_channel[12] => src_payload.IN1 +sink0_channel[13] => src_payload.IN1 +sink0_channel[14] => src_payload.IN1 +sink0_channel[15] => src_payload.IN1 +sink0_channel[16] => src_payload.IN1 +sink0_channel[17] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request[1].IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[59] => last_cycle.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_channel[11] => src_payload.IN1 +sink1_channel[12] => src_payload.IN1 +sink1_channel[13] => src_payload.IN1 +sink1_channel[14] => src_payload.IN1 +sink1_channel[15] => src_payload.IN1 +sink1_channel[16] => src_payload.IN1 +sink1_channel[17] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +request[0] => grant[0].DATAIN +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant[1].DATAIN +request[1] => _.IN1 +request[1] => _.IN1 +grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => ~NO_FANOUT~ +save_top_priority => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => sum.IN0 +a[0] => full_adder.cout[0].IN0 +a[1] => cout.IN0 +a[1] => cout.IN0 +a[2] => cout.IN0 +a[2] => cout.IN0 +a[3] => sum.IN0 +b[0] => sum.IN1 +b[0] => full_adder.cout[0].IN1 +b[1] => cout.IN1 +b[1] => cout.IN1 +b[2] => cout.IN1 +b[2] => cout.IN1 +b[3] => sum.IN1 +sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 +sink0_valid => request[0].IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[59] => last_cycle.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_channel[11] => src_payload.IN1 +sink0_channel[12] => src_payload.IN1 +sink0_channel[13] => src_payload.IN1 +sink0_channel[14] => src_payload.IN1 +sink0_channel[15] => src_payload.IN1 +sink0_channel[16] => src_payload.IN1 +sink0_channel[17] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request[1].IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[59] => last_cycle.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_channel[11] => src_payload.IN1 +sink1_channel[12] => src_payload.IN1 +sink1_channel[13] => src_payload.IN1 +sink1_channel[14] => src_payload.IN1 +sink1_channel[15] => src_payload.IN1 +sink1_channel[16] => src_payload.IN1 +sink1_channel[17] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +sink2_valid => request[2].IN1 +sink2_data[0] => src_payload.IN1 +sink2_data[1] => src_payload.IN1 +sink2_data[2] => src_payload.IN1 +sink2_data[3] => src_payload.IN1 +sink2_data[4] => src_payload.IN1 +sink2_data[5] => src_payload.IN1 +sink2_data[6] => src_payload.IN1 +sink2_data[7] => src_payload.IN1 +sink2_data[8] => src_payload.IN1 +sink2_data[9] => src_payload.IN1 +sink2_data[10] => src_payload.IN1 +sink2_data[11] => src_payload.IN1 +sink2_data[12] => src_payload.IN1 +sink2_data[13] => src_payload.IN1 +sink2_data[14] => src_payload.IN1 +sink2_data[15] => src_payload.IN1 +sink2_data[16] => src_payload.IN1 +sink2_data[17] => src_payload.IN1 +sink2_data[18] => src_payload.IN1 +sink2_data[19] => src_payload.IN1 +sink2_data[20] => src_payload.IN1 +sink2_data[21] => src_payload.IN1 +sink2_data[22] => src_payload.IN1 +sink2_data[23] => src_payload.IN1 +sink2_data[24] => src_payload.IN1 +sink2_data[25] => src_payload.IN1 +sink2_data[26] => src_payload.IN1 +sink2_data[27] => src_payload.IN1 +sink2_data[28] => src_payload.IN1 +sink2_data[29] => src_payload.IN1 +sink2_data[30] => src_payload.IN1 +sink2_data[31] => src_payload.IN1 +sink2_data[32] => src_payload.IN1 +sink2_data[33] => src_payload.IN1 +sink2_data[34] => src_payload.IN1 +sink2_data[35] => src_payload.IN1 +sink2_data[36] => src_payload.IN1 +sink2_data[37] => src_payload.IN1 +sink2_data[38] => src_payload.IN1 +sink2_data[39] => src_payload.IN1 +sink2_data[40] => src_payload.IN1 +sink2_data[41] => src_payload.IN1 +sink2_data[42] => src_payload.IN1 +sink2_data[43] => src_payload.IN1 +sink2_data[44] => src_payload.IN1 +sink2_data[45] => src_payload.IN1 +sink2_data[46] => src_payload.IN1 +sink2_data[47] => src_payload.IN1 +sink2_data[48] => src_payload.IN1 +sink2_data[49] => src_payload.IN1 +sink2_data[50] => src_payload.IN1 +sink2_data[51] => src_payload.IN1 +sink2_data[52] => src_payload.IN1 +sink2_data[53] => src_payload.IN1 +sink2_data[54] => src_payload.IN1 +sink2_data[55] => src_payload.IN1 +sink2_data[56] => src_payload.IN1 +sink2_data[57] => src_payload.IN1 +sink2_data[58] => src_payload.IN1 +sink2_data[59] => src_payload.IN1 +sink2_data[59] => last_cycle.IN1 +sink2_data[60] => src_payload.IN1 +sink2_data[61] => src_payload.IN1 +sink2_data[62] => src_payload.IN1 +sink2_data[63] => src_payload.IN1 +sink2_data[64] => src_payload.IN1 +sink2_data[65] => src_payload.IN1 +sink2_data[66] => src_payload.IN1 +sink2_data[67] => src_payload.IN1 +sink2_data[68] => src_payload.IN1 +sink2_data[69] => src_payload.IN1 +sink2_data[70] => src_payload.IN1 +sink2_data[71] => src_payload.IN1 +sink2_data[72] => src_payload.IN1 +sink2_data[73] => src_payload.IN1 +sink2_data[74] => src_payload.IN1 +sink2_data[75] => src_payload.IN1 +sink2_data[76] => src_payload.IN1 +sink2_data[77] => src_payload.IN1 +sink2_data[78] => src_payload.IN1 +sink2_data[79] => src_payload.IN1 +sink2_data[80] => src_payload.IN1 +sink2_data[81] => src_payload.IN1 +sink2_data[82] => src_payload.IN1 +sink2_data[83] => src_payload.IN1 +sink2_data[84] => src_payload.IN1 +sink2_data[85] => src_payload.IN1 +sink2_data[86] => src_payload.IN1 +sink2_data[87] => src_payload.IN1 +sink2_data[88] => src_payload.IN1 +sink2_data[89] => src_payload.IN1 +sink2_data[90] => src_payload.IN1 +sink2_data[91] => src_payload.IN1 +sink2_data[92] => src_payload.IN1 +sink2_data[93] => src_payload.IN1 +sink2_data[94] => src_payload.IN1 +sink2_data[95] => src_payload.IN1 +sink2_channel[0] => src_payload.IN1 +sink2_channel[1] => src_payload.IN1 +sink2_channel[2] => src_payload.IN1 +sink2_channel[3] => src_payload.IN1 +sink2_channel[4] => src_payload.IN1 +sink2_channel[5] => src_payload.IN1 +sink2_channel[6] => src_payload.IN1 +sink2_channel[7] => src_payload.IN1 +sink2_channel[8] => src_payload.IN1 +sink2_channel[9] => src_payload.IN1 +sink2_channel[10] => src_payload.IN1 +sink2_channel[11] => src_payload.IN1 +sink2_channel[12] => src_payload.IN1 +sink2_channel[13] => src_payload.IN1 +sink2_channel[14] => src_payload.IN1 +sink2_channel[15] => src_payload.IN1 +sink2_channel[16] => src_payload.IN1 +sink2_channel[17] => src_payload.IN1 +sink2_startofpacket => src_payload.IN1 +sink2_endofpacket => src_payload.IN1 +sink2_ready <= sink2_ready.DB_MAX_OUTPUT_PORT_TYPE +sink3_valid => request[3].IN1 +sink3_data[0] => src_payload.IN1 +sink3_data[1] => src_payload.IN1 +sink3_data[2] => src_payload.IN1 +sink3_data[3] => src_payload.IN1 +sink3_data[4] => src_payload.IN1 +sink3_data[5] => src_payload.IN1 +sink3_data[6] => src_payload.IN1 +sink3_data[7] => src_payload.IN1 +sink3_data[8] => src_payload.IN1 +sink3_data[9] => src_payload.IN1 +sink3_data[10] => src_payload.IN1 +sink3_data[11] => src_payload.IN1 +sink3_data[12] => src_payload.IN1 +sink3_data[13] => src_payload.IN1 +sink3_data[14] => src_payload.IN1 +sink3_data[15] => src_payload.IN1 +sink3_data[16] => src_payload.IN1 +sink3_data[17] => src_payload.IN1 +sink3_data[18] => src_payload.IN1 +sink3_data[19] => src_payload.IN1 +sink3_data[20] => src_payload.IN1 +sink3_data[21] => src_payload.IN1 +sink3_data[22] => src_payload.IN1 +sink3_data[23] => src_payload.IN1 +sink3_data[24] => src_payload.IN1 +sink3_data[25] => src_payload.IN1 +sink3_data[26] => src_payload.IN1 +sink3_data[27] => src_payload.IN1 +sink3_data[28] => src_payload.IN1 +sink3_data[29] => src_payload.IN1 +sink3_data[30] => src_payload.IN1 +sink3_data[31] => src_payload.IN1 +sink3_data[32] => src_payload.IN1 +sink3_data[33] => src_payload.IN1 +sink3_data[34] => src_payload.IN1 +sink3_data[35] => src_payload.IN1 +sink3_data[36] => src_payload.IN1 +sink3_data[37] => src_payload.IN1 +sink3_data[38] => src_payload.IN1 +sink3_data[39] => src_payload.IN1 +sink3_data[40] => src_payload.IN1 +sink3_data[41] => src_payload.IN1 +sink3_data[42] => src_payload.IN1 +sink3_data[43] => src_payload.IN1 +sink3_data[44] => src_payload.IN1 +sink3_data[45] => src_payload.IN1 +sink3_data[46] => src_payload.IN1 +sink3_data[47] => src_payload.IN1 +sink3_data[48] => src_payload.IN1 +sink3_data[49] => src_payload.IN1 +sink3_data[50] => src_payload.IN1 +sink3_data[51] => src_payload.IN1 +sink3_data[52] => src_payload.IN1 +sink3_data[53] => src_payload.IN1 +sink3_data[54] => src_payload.IN1 +sink3_data[55] => src_payload.IN1 +sink3_data[56] => src_payload.IN1 +sink3_data[57] => src_payload.IN1 +sink3_data[58] => src_payload.IN1 +sink3_data[59] => src_payload.IN1 +sink3_data[59] => last_cycle.IN1 +sink3_data[60] => src_payload.IN1 +sink3_data[61] => src_payload.IN1 +sink3_data[62] => src_payload.IN1 +sink3_data[63] => src_payload.IN1 +sink3_data[64] => src_payload.IN1 +sink3_data[65] => src_payload.IN1 +sink3_data[66] => src_payload.IN1 +sink3_data[67] => src_payload.IN1 +sink3_data[68] => src_payload.IN1 +sink3_data[69] => src_payload.IN1 +sink3_data[70] => src_payload.IN1 +sink3_data[71] => src_payload.IN1 +sink3_data[72] => src_payload.IN1 +sink3_data[73] => src_payload.IN1 +sink3_data[74] => src_payload.IN1 +sink3_data[75] => src_payload.IN1 +sink3_data[76] => src_payload.IN1 +sink3_data[77] => src_payload.IN1 +sink3_data[78] => src_payload.IN1 +sink3_data[79] => src_payload.IN1 +sink3_data[80] => src_payload.IN1 +sink3_data[81] => src_payload.IN1 +sink3_data[82] => src_payload.IN1 +sink3_data[83] => src_payload.IN1 +sink3_data[84] => src_payload.IN1 +sink3_data[85] => src_payload.IN1 +sink3_data[86] => src_payload.IN1 +sink3_data[87] => src_payload.IN1 +sink3_data[88] => src_payload.IN1 +sink3_data[89] => src_payload.IN1 +sink3_data[90] => src_payload.IN1 +sink3_data[91] => src_payload.IN1 +sink3_data[92] => src_payload.IN1 +sink3_data[93] => src_payload.IN1 +sink3_data[94] => src_payload.IN1 +sink3_data[95] => src_payload.IN1 +sink3_channel[0] => src_payload.IN1 +sink3_channel[1] => src_payload.IN1 +sink3_channel[2] => src_payload.IN1 +sink3_channel[3] => src_payload.IN1 +sink3_channel[4] => src_payload.IN1 +sink3_channel[5] => src_payload.IN1 +sink3_channel[6] => src_payload.IN1 +sink3_channel[7] => src_payload.IN1 +sink3_channel[8] => src_payload.IN1 +sink3_channel[9] => src_payload.IN1 +sink3_channel[10] => src_payload.IN1 +sink3_channel[11] => src_payload.IN1 +sink3_channel[12] => src_payload.IN1 +sink3_channel[13] => src_payload.IN1 +sink3_channel[14] => src_payload.IN1 +sink3_channel[15] => src_payload.IN1 +sink3_channel[16] => src_payload.IN1 +sink3_channel[17] => src_payload.IN1 +sink3_startofpacket => src_payload.IN1 +sink3_endofpacket => src_payload.IN1 +sink3_ready <= sink3_ready.DB_MAX_OUTPUT_PORT_TYPE +sink4_valid => request[4].IN1 +sink4_data[0] => src_payload.IN1 +sink4_data[1] => src_payload.IN1 +sink4_data[2] => src_payload.IN1 +sink4_data[3] => src_payload.IN1 +sink4_data[4] => src_payload.IN1 +sink4_data[5] => src_payload.IN1 +sink4_data[6] => src_payload.IN1 +sink4_data[7] => src_payload.IN1 +sink4_data[8] => src_payload.IN1 +sink4_data[9] => src_payload.IN1 +sink4_data[10] => src_payload.IN1 +sink4_data[11] => src_payload.IN1 +sink4_data[12] => src_payload.IN1 +sink4_data[13] => src_payload.IN1 +sink4_data[14] => src_payload.IN1 +sink4_data[15] => src_payload.IN1 +sink4_data[16] => src_payload.IN1 +sink4_data[17] => src_payload.IN1 +sink4_data[18] => src_payload.IN1 +sink4_data[19] => src_payload.IN1 +sink4_data[20] => src_payload.IN1 +sink4_data[21] => src_payload.IN1 +sink4_data[22] => src_payload.IN1 +sink4_data[23] => src_payload.IN1 +sink4_data[24] => src_payload.IN1 +sink4_data[25] => src_payload.IN1 +sink4_data[26] => src_payload.IN1 +sink4_data[27] => src_payload.IN1 +sink4_data[28] => src_payload.IN1 +sink4_data[29] => src_payload.IN1 +sink4_data[30] => src_payload.IN1 +sink4_data[31] => src_payload.IN1 +sink4_data[32] => src_payload.IN1 +sink4_data[33] => src_payload.IN1 +sink4_data[34] => src_payload.IN1 +sink4_data[35] => src_payload.IN1 +sink4_data[36] => src_payload.IN1 +sink4_data[37] => src_payload.IN1 +sink4_data[38] => src_payload.IN1 +sink4_data[39] => src_payload.IN1 +sink4_data[40] => src_payload.IN1 +sink4_data[41] => src_payload.IN1 +sink4_data[42] => src_payload.IN1 +sink4_data[43] => src_payload.IN1 +sink4_data[44] => src_payload.IN1 +sink4_data[45] => src_payload.IN1 +sink4_data[46] => src_payload.IN1 +sink4_data[47] => src_payload.IN1 +sink4_data[48] => src_payload.IN1 +sink4_data[49] => src_payload.IN1 +sink4_data[50] => src_payload.IN1 +sink4_data[51] => src_payload.IN1 +sink4_data[52] => src_payload.IN1 +sink4_data[53] => src_payload.IN1 +sink4_data[54] => src_payload.IN1 +sink4_data[55] => src_payload.IN1 +sink4_data[56] => src_payload.IN1 +sink4_data[57] => src_payload.IN1 +sink4_data[58] => src_payload.IN1 +sink4_data[59] => src_payload.IN1 +sink4_data[59] => last_cycle.IN1 +sink4_data[60] => src_payload.IN1 +sink4_data[61] => src_payload.IN1 +sink4_data[62] => src_payload.IN1 +sink4_data[63] => src_payload.IN1 +sink4_data[64] => src_payload.IN1 +sink4_data[65] => src_payload.IN1 +sink4_data[66] => src_payload.IN1 +sink4_data[67] => src_payload.IN1 +sink4_data[68] => src_payload.IN1 +sink4_data[69] => src_payload.IN1 +sink4_data[70] => src_payload.IN1 +sink4_data[71] => src_payload.IN1 +sink4_data[72] => src_payload.IN1 +sink4_data[73] => src_payload.IN1 +sink4_data[74] => src_payload.IN1 +sink4_data[75] => src_payload.IN1 +sink4_data[76] => src_payload.IN1 +sink4_data[77] => src_payload.IN1 +sink4_data[78] => src_payload.IN1 +sink4_data[79] => src_payload.IN1 +sink4_data[80] => src_payload.IN1 +sink4_data[81] => src_payload.IN1 +sink4_data[82] => src_payload.IN1 +sink4_data[83] => src_payload.IN1 +sink4_data[84] => src_payload.IN1 +sink4_data[85] => src_payload.IN1 +sink4_data[86] => src_payload.IN1 +sink4_data[87] => src_payload.IN1 +sink4_data[88] => src_payload.IN1 +sink4_data[89] => src_payload.IN1 +sink4_data[90] => src_payload.IN1 +sink4_data[91] => src_payload.IN1 +sink4_data[92] => src_payload.IN1 +sink4_data[93] => src_payload.IN1 +sink4_data[94] => src_payload.IN1 +sink4_data[95] => src_payload.IN1 +sink4_channel[0] => src_payload.IN1 +sink4_channel[1] => src_payload.IN1 +sink4_channel[2] => src_payload.IN1 +sink4_channel[3] => src_payload.IN1 +sink4_channel[4] => src_payload.IN1 +sink4_channel[5] => src_payload.IN1 +sink4_channel[6] => src_payload.IN1 +sink4_channel[7] => src_payload.IN1 +sink4_channel[8] => src_payload.IN1 +sink4_channel[9] => src_payload.IN1 +sink4_channel[10] => src_payload.IN1 +sink4_channel[11] => src_payload.IN1 +sink4_channel[12] => src_payload.IN1 +sink4_channel[13] => src_payload.IN1 +sink4_channel[14] => src_payload.IN1 +sink4_channel[15] => src_payload.IN1 +sink4_channel[16] => src_payload.IN1 +sink4_channel[17] => src_payload.IN1 +sink4_startofpacket => src_payload.IN1 +sink4_endofpacket => src_payload.IN1 +sink4_ready <= sink4_ready.DB_MAX_OUTPUT_PORT_TYPE +sink5_valid => request[5].IN1 +sink5_data[0] => src_payload.IN1 +sink5_data[1] => src_payload.IN1 +sink5_data[2] => src_payload.IN1 +sink5_data[3] => src_payload.IN1 +sink5_data[4] => src_payload.IN1 +sink5_data[5] => src_payload.IN1 +sink5_data[6] => src_payload.IN1 +sink5_data[7] => src_payload.IN1 +sink5_data[8] => src_payload.IN1 +sink5_data[9] => src_payload.IN1 +sink5_data[10] => src_payload.IN1 +sink5_data[11] => src_payload.IN1 +sink5_data[12] => src_payload.IN1 +sink5_data[13] => src_payload.IN1 +sink5_data[14] => src_payload.IN1 +sink5_data[15] => src_payload.IN1 +sink5_data[16] => src_payload.IN1 +sink5_data[17] => src_payload.IN1 +sink5_data[18] => src_payload.IN1 +sink5_data[19] => src_payload.IN1 +sink5_data[20] => src_payload.IN1 +sink5_data[21] => src_payload.IN1 +sink5_data[22] => src_payload.IN1 +sink5_data[23] => src_payload.IN1 +sink5_data[24] => src_payload.IN1 +sink5_data[25] => src_payload.IN1 +sink5_data[26] => src_payload.IN1 +sink5_data[27] => src_payload.IN1 +sink5_data[28] => src_payload.IN1 +sink5_data[29] => src_payload.IN1 +sink5_data[30] => src_payload.IN1 +sink5_data[31] => src_payload.IN1 +sink5_data[32] => src_payload.IN1 +sink5_data[33] => src_payload.IN1 +sink5_data[34] => src_payload.IN1 +sink5_data[35] => src_payload.IN1 +sink5_data[36] => src_payload.IN1 +sink5_data[37] => src_payload.IN1 +sink5_data[38] => src_payload.IN1 +sink5_data[39] => src_payload.IN1 +sink5_data[40] => src_payload.IN1 +sink5_data[41] => src_payload.IN1 +sink5_data[42] => src_payload.IN1 +sink5_data[43] => src_payload.IN1 +sink5_data[44] => src_payload.IN1 +sink5_data[45] => src_payload.IN1 +sink5_data[46] => src_payload.IN1 +sink5_data[47] => src_payload.IN1 +sink5_data[48] => src_payload.IN1 +sink5_data[49] => src_payload.IN1 +sink5_data[50] => src_payload.IN1 +sink5_data[51] => src_payload.IN1 +sink5_data[52] => src_payload.IN1 +sink5_data[53] => src_payload.IN1 +sink5_data[54] => src_payload.IN1 +sink5_data[55] => src_payload.IN1 +sink5_data[56] => src_payload.IN1 +sink5_data[57] => src_payload.IN1 +sink5_data[58] => src_payload.IN1 +sink5_data[59] => src_payload.IN1 +sink5_data[59] => last_cycle.IN1 +sink5_data[60] => src_payload.IN1 +sink5_data[61] => src_payload.IN1 +sink5_data[62] => src_payload.IN1 +sink5_data[63] => src_payload.IN1 +sink5_data[64] => src_payload.IN1 +sink5_data[65] => src_payload.IN1 +sink5_data[66] => src_payload.IN1 +sink5_data[67] => src_payload.IN1 +sink5_data[68] => src_payload.IN1 +sink5_data[69] => src_payload.IN1 +sink5_data[70] => src_payload.IN1 +sink5_data[71] => src_payload.IN1 +sink5_data[72] => src_payload.IN1 +sink5_data[73] => src_payload.IN1 +sink5_data[74] => src_payload.IN1 +sink5_data[75] => src_payload.IN1 +sink5_data[76] => src_payload.IN1 +sink5_data[77] => src_payload.IN1 +sink5_data[78] => src_payload.IN1 +sink5_data[79] => src_payload.IN1 +sink5_data[80] => src_payload.IN1 +sink5_data[81] => src_payload.IN1 +sink5_data[82] => src_payload.IN1 +sink5_data[83] => src_payload.IN1 +sink5_data[84] => src_payload.IN1 +sink5_data[85] => src_payload.IN1 +sink5_data[86] => src_payload.IN1 +sink5_data[87] => src_payload.IN1 +sink5_data[88] => src_payload.IN1 +sink5_data[89] => src_payload.IN1 +sink5_data[90] => src_payload.IN1 +sink5_data[91] => src_payload.IN1 +sink5_data[92] => src_payload.IN1 +sink5_data[93] => src_payload.IN1 +sink5_data[94] => src_payload.IN1 +sink5_data[95] => src_payload.IN1 +sink5_channel[0] => src_payload.IN1 +sink5_channel[1] => src_payload.IN1 +sink5_channel[2] => src_payload.IN1 +sink5_channel[3] => src_payload.IN1 +sink5_channel[4] => src_payload.IN1 +sink5_channel[5] => src_payload.IN1 +sink5_channel[6] => src_payload.IN1 +sink5_channel[7] => src_payload.IN1 +sink5_channel[8] => src_payload.IN1 +sink5_channel[9] => src_payload.IN1 +sink5_channel[10] => src_payload.IN1 +sink5_channel[11] => src_payload.IN1 +sink5_channel[12] => src_payload.IN1 +sink5_channel[13] => src_payload.IN1 +sink5_channel[14] => src_payload.IN1 +sink5_channel[15] => src_payload.IN1 +sink5_channel[16] => src_payload.IN1 +sink5_channel[17] => src_payload.IN1 +sink5_startofpacket => src_payload.IN1 +sink5_endofpacket => src_payload.IN1 +sink5_ready <= sink5_ready.DB_MAX_OUTPUT_PORT_TYPE +sink6_valid => request[6].IN1 +sink6_data[0] => src_payload.IN1 +sink6_data[1] => src_payload.IN1 +sink6_data[2] => src_payload.IN1 +sink6_data[3] => src_payload.IN1 +sink6_data[4] => src_payload.IN1 +sink6_data[5] => src_payload.IN1 +sink6_data[6] => src_payload.IN1 +sink6_data[7] => src_payload.IN1 +sink6_data[8] => src_payload.IN1 +sink6_data[9] => src_payload.IN1 +sink6_data[10] => src_payload.IN1 +sink6_data[11] => src_payload.IN1 +sink6_data[12] => src_payload.IN1 +sink6_data[13] => src_payload.IN1 +sink6_data[14] => src_payload.IN1 +sink6_data[15] => src_payload.IN1 +sink6_data[16] => src_payload.IN1 +sink6_data[17] => src_payload.IN1 +sink6_data[18] => src_payload.IN1 +sink6_data[19] => src_payload.IN1 +sink6_data[20] => src_payload.IN1 +sink6_data[21] => src_payload.IN1 +sink6_data[22] => src_payload.IN1 +sink6_data[23] => src_payload.IN1 +sink6_data[24] => src_payload.IN1 +sink6_data[25] => src_payload.IN1 +sink6_data[26] => src_payload.IN1 +sink6_data[27] => src_payload.IN1 +sink6_data[28] => src_payload.IN1 +sink6_data[29] => src_payload.IN1 +sink6_data[30] => src_payload.IN1 +sink6_data[31] => src_payload.IN1 +sink6_data[32] => src_payload.IN1 +sink6_data[33] => src_payload.IN1 +sink6_data[34] => src_payload.IN1 +sink6_data[35] => src_payload.IN1 +sink6_data[36] => src_payload.IN1 +sink6_data[37] => src_payload.IN1 +sink6_data[38] => src_payload.IN1 +sink6_data[39] => src_payload.IN1 +sink6_data[40] => src_payload.IN1 +sink6_data[41] => src_payload.IN1 +sink6_data[42] => src_payload.IN1 +sink6_data[43] => src_payload.IN1 +sink6_data[44] => src_payload.IN1 +sink6_data[45] => src_payload.IN1 +sink6_data[46] => src_payload.IN1 +sink6_data[47] => src_payload.IN1 +sink6_data[48] => src_payload.IN1 +sink6_data[49] => src_payload.IN1 +sink6_data[50] => src_payload.IN1 +sink6_data[51] => src_payload.IN1 +sink6_data[52] => src_payload.IN1 +sink6_data[53] => src_payload.IN1 +sink6_data[54] => src_payload.IN1 +sink6_data[55] => src_payload.IN1 +sink6_data[56] => src_payload.IN1 +sink6_data[57] => src_payload.IN1 +sink6_data[58] => src_payload.IN1 +sink6_data[59] => src_payload.IN1 +sink6_data[59] => last_cycle.IN1 +sink6_data[60] => src_payload.IN1 +sink6_data[61] => src_payload.IN1 +sink6_data[62] => src_payload.IN1 +sink6_data[63] => src_payload.IN1 +sink6_data[64] => src_payload.IN1 +sink6_data[65] => src_payload.IN1 +sink6_data[66] => src_payload.IN1 +sink6_data[67] => src_payload.IN1 +sink6_data[68] => src_payload.IN1 +sink6_data[69] => src_payload.IN1 +sink6_data[70] => src_payload.IN1 +sink6_data[71] => src_payload.IN1 +sink6_data[72] => src_payload.IN1 +sink6_data[73] => src_payload.IN1 +sink6_data[74] => src_payload.IN1 +sink6_data[75] => src_payload.IN1 +sink6_data[76] => src_payload.IN1 +sink6_data[77] => src_payload.IN1 +sink6_data[78] => src_payload.IN1 +sink6_data[79] => src_payload.IN1 +sink6_data[80] => src_payload.IN1 +sink6_data[81] => src_payload.IN1 +sink6_data[82] => src_payload.IN1 +sink6_data[83] => src_payload.IN1 +sink6_data[84] => src_payload.IN1 +sink6_data[85] => src_payload.IN1 +sink6_data[86] => src_payload.IN1 +sink6_data[87] => src_payload.IN1 +sink6_data[88] => src_payload.IN1 +sink6_data[89] => src_payload.IN1 +sink6_data[90] => src_payload.IN1 +sink6_data[91] => src_payload.IN1 +sink6_data[92] => src_payload.IN1 +sink6_data[93] => src_payload.IN1 +sink6_data[94] => src_payload.IN1 +sink6_data[95] => src_payload.IN1 +sink6_channel[0] => src_payload.IN1 +sink6_channel[1] => src_payload.IN1 +sink6_channel[2] => src_payload.IN1 +sink6_channel[3] => src_payload.IN1 +sink6_channel[4] => src_payload.IN1 +sink6_channel[5] => src_payload.IN1 +sink6_channel[6] => src_payload.IN1 +sink6_channel[7] => src_payload.IN1 +sink6_channel[8] => src_payload.IN1 +sink6_channel[9] => src_payload.IN1 +sink6_channel[10] => src_payload.IN1 +sink6_channel[11] => src_payload.IN1 +sink6_channel[12] => src_payload.IN1 +sink6_channel[13] => src_payload.IN1 +sink6_channel[14] => src_payload.IN1 +sink6_channel[15] => src_payload.IN1 +sink6_channel[16] => src_payload.IN1 +sink6_channel[17] => src_payload.IN1 +sink6_startofpacket => src_payload.IN1 +sink6_endofpacket => src_payload.IN1 +sink6_ready <= sink6_ready.DB_MAX_OUTPUT_PORT_TYPE +sink7_valid => request[7].IN1 +sink7_data[0] => src_payload.IN1 +sink7_data[1] => src_payload.IN1 +sink7_data[2] => src_payload.IN1 +sink7_data[3] => src_payload.IN1 +sink7_data[4] => src_payload.IN1 +sink7_data[5] => src_payload.IN1 +sink7_data[6] => src_payload.IN1 +sink7_data[7] => src_payload.IN1 +sink7_data[8] => src_payload.IN1 +sink7_data[9] => src_payload.IN1 +sink7_data[10] => src_payload.IN1 +sink7_data[11] => src_payload.IN1 +sink7_data[12] => src_payload.IN1 +sink7_data[13] => src_payload.IN1 +sink7_data[14] => src_payload.IN1 +sink7_data[15] => src_payload.IN1 +sink7_data[16] => src_payload.IN1 +sink7_data[17] => src_payload.IN1 +sink7_data[18] => src_payload.IN1 +sink7_data[19] => src_payload.IN1 +sink7_data[20] => src_payload.IN1 +sink7_data[21] => src_payload.IN1 +sink7_data[22] => src_payload.IN1 +sink7_data[23] => src_payload.IN1 +sink7_data[24] => src_payload.IN1 +sink7_data[25] => src_payload.IN1 +sink7_data[26] => src_payload.IN1 +sink7_data[27] => src_payload.IN1 +sink7_data[28] => src_payload.IN1 +sink7_data[29] => src_payload.IN1 +sink7_data[30] => src_payload.IN1 +sink7_data[31] => src_payload.IN1 +sink7_data[32] => src_payload.IN1 +sink7_data[33] => src_payload.IN1 +sink7_data[34] => src_payload.IN1 +sink7_data[35] => src_payload.IN1 +sink7_data[36] => src_payload.IN1 +sink7_data[37] => src_payload.IN1 +sink7_data[38] => src_payload.IN1 +sink7_data[39] => src_payload.IN1 +sink7_data[40] => src_payload.IN1 +sink7_data[41] => src_payload.IN1 +sink7_data[42] => src_payload.IN1 +sink7_data[43] => src_payload.IN1 +sink7_data[44] => src_payload.IN1 +sink7_data[45] => src_payload.IN1 +sink7_data[46] => src_payload.IN1 +sink7_data[47] => src_payload.IN1 +sink7_data[48] => src_payload.IN1 +sink7_data[49] => src_payload.IN1 +sink7_data[50] => src_payload.IN1 +sink7_data[51] => src_payload.IN1 +sink7_data[52] => src_payload.IN1 +sink7_data[53] => src_payload.IN1 +sink7_data[54] => src_payload.IN1 +sink7_data[55] => src_payload.IN1 +sink7_data[56] => src_payload.IN1 +sink7_data[57] => src_payload.IN1 +sink7_data[58] => src_payload.IN1 +sink7_data[59] => src_payload.IN1 +sink7_data[59] => last_cycle.IN1 +sink7_data[60] => src_payload.IN1 +sink7_data[61] => src_payload.IN1 +sink7_data[62] => src_payload.IN1 +sink7_data[63] => src_payload.IN1 +sink7_data[64] => src_payload.IN1 +sink7_data[65] => src_payload.IN1 +sink7_data[66] => src_payload.IN1 +sink7_data[67] => src_payload.IN1 +sink7_data[68] => src_payload.IN1 +sink7_data[69] => src_payload.IN1 +sink7_data[70] => src_payload.IN1 +sink7_data[71] => src_payload.IN1 +sink7_data[72] => src_payload.IN1 +sink7_data[73] => src_payload.IN1 +sink7_data[74] => src_payload.IN1 +sink7_data[75] => src_payload.IN1 +sink7_data[76] => src_payload.IN1 +sink7_data[77] => src_payload.IN1 +sink7_data[78] => src_payload.IN1 +sink7_data[79] => src_payload.IN1 +sink7_data[80] => src_payload.IN1 +sink7_data[81] => src_payload.IN1 +sink7_data[82] => src_payload.IN1 +sink7_data[83] => src_payload.IN1 +sink7_data[84] => src_payload.IN1 +sink7_data[85] => src_payload.IN1 +sink7_data[86] => src_payload.IN1 +sink7_data[87] => src_payload.IN1 +sink7_data[88] => src_payload.IN1 +sink7_data[89] => src_payload.IN1 +sink7_data[90] => src_payload.IN1 +sink7_data[91] => src_payload.IN1 +sink7_data[92] => src_payload.IN1 +sink7_data[93] => src_payload.IN1 +sink7_data[94] => src_payload.IN1 +sink7_data[95] => src_payload.IN1 +sink7_channel[0] => src_payload.IN1 +sink7_channel[1] => src_payload.IN1 +sink7_channel[2] => src_payload.IN1 +sink7_channel[3] => src_payload.IN1 +sink7_channel[4] => src_payload.IN1 +sink7_channel[5] => src_payload.IN1 +sink7_channel[6] => src_payload.IN1 +sink7_channel[7] => src_payload.IN1 +sink7_channel[8] => src_payload.IN1 +sink7_channel[9] => src_payload.IN1 +sink7_channel[10] => src_payload.IN1 +sink7_channel[11] => src_payload.IN1 +sink7_channel[12] => src_payload.IN1 +sink7_channel[13] => src_payload.IN1 +sink7_channel[14] => src_payload.IN1 +sink7_channel[15] => src_payload.IN1 +sink7_channel[16] => src_payload.IN1 +sink7_channel[17] => src_payload.IN1 +sink7_startofpacket => src_payload.IN1 +sink7_endofpacket => src_payload.IN1 +sink7_ready <= sink7_ready.DB_MAX_OUTPUT_PORT_TYPE +sink8_valid => request[8].IN1 +sink8_data[0] => src_payload.IN1 +sink8_data[1] => src_payload.IN1 +sink8_data[2] => src_payload.IN1 +sink8_data[3] => src_payload.IN1 +sink8_data[4] => src_payload.IN1 +sink8_data[5] => src_payload.IN1 +sink8_data[6] => src_payload.IN1 +sink8_data[7] => src_payload.IN1 +sink8_data[8] => src_payload.IN1 +sink8_data[9] => src_payload.IN1 +sink8_data[10] => src_payload.IN1 +sink8_data[11] => src_payload.IN1 +sink8_data[12] => src_payload.IN1 +sink8_data[13] => src_payload.IN1 +sink8_data[14] => src_payload.IN1 +sink8_data[15] => src_payload.IN1 +sink8_data[16] => src_payload.IN1 +sink8_data[17] => src_payload.IN1 +sink8_data[18] => src_payload.IN1 +sink8_data[19] => src_payload.IN1 +sink8_data[20] => src_payload.IN1 +sink8_data[21] => src_payload.IN1 +sink8_data[22] => src_payload.IN1 +sink8_data[23] => src_payload.IN1 +sink8_data[24] => src_payload.IN1 +sink8_data[25] => src_payload.IN1 +sink8_data[26] => src_payload.IN1 +sink8_data[27] => src_payload.IN1 +sink8_data[28] => src_payload.IN1 +sink8_data[29] => src_payload.IN1 +sink8_data[30] => src_payload.IN1 +sink8_data[31] => src_payload.IN1 +sink8_data[32] => src_payload.IN1 +sink8_data[33] => src_payload.IN1 +sink8_data[34] => src_payload.IN1 +sink8_data[35] => src_payload.IN1 +sink8_data[36] => src_payload.IN1 +sink8_data[37] => src_payload.IN1 +sink8_data[38] => src_payload.IN1 +sink8_data[39] => src_payload.IN1 +sink8_data[40] => src_payload.IN1 +sink8_data[41] => src_payload.IN1 +sink8_data[42] => src_payload.IN1 +sink8_data[43] => src_payload.IN1 +sink8_data[44] => src_payload.IN1 +sink8_data[45] => src_payload.IN1 +sink8_data[46] => src_payload.IN1 +sink8_data[47] => src_payload.IN1 +sink8_data[48] => src_payload.IN1 +sink8_data[49] => src_payload.IN1 +sink8_data[50] => src_payload.IN1 +sink8_data[51] => src_payload.IN1 +sink8_data[52] => src_payload.IN1 +sink8_data[53] => src_payload.IN1 +sink8_data[54] => src_payload.IN1 +sink8_data[55] => src_payload.IN1 +sink8_data[56] => src_payload.IN1 +sink8_data[57] => src_payload.IN1 +sink8_data[58] => src_payload.IN1 +sink8_data[59] => src_payload.IN1 +sink8_data[59] => last_cycle.IN1 +sink8_data[60] => src_payload.IN1 +sink8_data[61] => src_payload.IN1 +sink8_data[62] => src_payload.IN1 +sink8_data[63] => src_payload.IN1 +sink8_data[64] => src_payload.IN1 +sink8_data[65] => src_payload.IN1 +sink8_data[66] => src_payload.IN1 +sink8_data[67] => src_payload.IN1 +sink8_data[68] => src_payload.IN1 +sink8_data[69] => src_payload.IN1 +sink8_data[70] => src_payload.IN1 +sink8_data[71] => src_payload.IN1 +sink8_data[72] => src_payload.IN1 +sink8_data[73] => src_payload.IN1 +sink8_data[74] => src_payload.IN1 +sink8_data[75] => src_payload.IN1 +sink8_data[76] => src_payload.IN1 +sink8_data[77] => src_payload.IN1 +sink8_data[78] => src_payload.IN1 +sink8_data[79] => src_payload.IN1 +sink8_data[80] => src_payload.IN1 +sink8_data[81] => src_payload.IN1 +sink8_data[82] => src_payload.IN1 +sink8_data[83] => src_payload.IN1 +sink8_data[84] => src_payload.IN1 +sink8_data[85] => src_payload.IN1 +sink8_data[86] => src_payload.IN1 +sink8_data[87] => src_payload.IN1 +sink8_data[88] => src_payload.IN1 +sink8_data[89] => src_payload.IN1 +sink8_data[90] => src_payload.IN1 +sink8_data[91] => src_payload.IN1 +sink8_data[92] => src_payload.IN1 +sink8_data[93] => src_payload.IN1 +sink8_data[94] => src_payload.IN1 +sink8_data[95] => src_payload.IN1 +sink8_channel[0] => src_payload.IN1 +sink8_channel[1] => src_payload.IN1 +sink8_channel[2] => src_payload.IN1 +sink8_channel[3] => src_payload.IN1 +sink8_channel[4] => src_payload.IN1 +sink8_channel[5] => src_payload.IN1 +sink8_channel[6] => src_payload.IN1 +sink8_channel[7] => src_payload.IN1 +sink8_channel[8] => src_payload.IN1 +sink8_channel[9] => src_payload.IN1 +sink8_channel[10] => src_payload.IN1 +sink8_channel[11] => src_payload.IN1 +sink8_channel[12] => src_payload.IN1 +sink8_channel[13] => src_payload.IN1 +sink8_channel[14] => src_payload.IN1 +sink8_channel[15] => src_payload.IN1 +sink8_channel[16] => src_payload.IN1 +sink8_channel[17] => src_payload.IN1 +sink8_startofpacket => src_payload.IN1 +sink8_endofpacket => src_payload.IN1 +sink8_ready <= sink8_ready.DB_MAX_OUTPUT_PORT_TYPE +sink9_valid => request[9].IN1 +sink9_data[0] => src_payload.IN1 +sink9_data[1] => src_payload.IN1 +sink9_data[2] => src_payload.IN1 +sink9_data[3] => src_payload.IN1 +sink9_data[4] => src_payload.IN1 +sink9_data[5] => src_payload.IN1 +sink9_data[6] => src_payload.IN1 +sink9_data[7] => src_payload.IN1 +sink9_data[8] => src_payload.IN1 +sink9_data[9] => src_payload.IN1 +sink9_data[10] => src_payload.IN1 +sink9_data[11] => src_payload.IN1 +sink9_data[12] => src_payload.IN1 +sink9_data[13] => src_payload.IN1 +sink9_data[14] => src_payload.IN1 +sink9_data[15] => src_payload.IN1 +sink9_data[16] => src_payload.IN1 +sink9_data[17] => src_payload.IN1 +sink9_data[18] => src_payload.IN1 +sink9_data[19] => src_payload.IN1 +sink9_data[20] => src_payload.IN1 +sink9_data[21] => src_payload.IN1 +sink9_data[22] => src_payload.IN1 +sink9_data[23] => src_payload.IN1 +sink9_data[24] => src_payload.IN1 +sink9_data[25] => src_payload.IN1 +sink9_data[26] => src_payload.IN1 +sink9_data[27] => src_payload.IN1 +sink9_data[28] => src_payload.IN1 +sink9_data[29] => src_payload.IN1 +sink9_data[30] => src_payload.IN1 +sink9_data[31] => src_payload.IN1 +sink9_data[32] => src_payload.IN1 +sink9_data[33] => src_payload.IN1 +sink9_data[34] => src_payload.IN1 +sink9_data[35] => src_payload.IN1 +sink9_data[36] => src_payload.IN1 +sink9_data[37] => src_payload.IN1 +sink9_data[38] => src_payload.IN1 +sink9_data[39] => src_payload.IN1 +sink9_data[40] => src_payload.IN1 +sink9_data[41] => src_payload.IN1 +sink9_data[42] => src_payload.IN1 +sink9_data[43] => src_payload.IN1 +sink9_data[44] => src_payload.IN1 +sink9_data[45] => src_payload.IN1 +sink9_data[46] => src_payload.IN1 +sink9_data[47] => src_payload.IN1 +sink9_data[48] => src_payload.IN1 +sink9_data[49] => src_payload.IN1 +sink9_data[50] => src_payload.IN1 +sink9_data[51] => src_payload.IN1 +sink9_data[52] => src_payload.IN1 +sink9_data[53] => src_payload.IN1 +sink9_data[54] => src_payload.IN1 +sink9_data[55] => src_payload.IN1 +sink9_data[56] => src_payload.IN1 +sink9_data[57] => src_payload.IN1 +sink9_data[58] => src_payload.IN1 +sink9_data[59] => src_payload.IN1 +sink9_data[59] => last_cycle.IN1 +sink9_data[60] => src_payload.IN1 +sink9_data[61] => src_payload.IN1 +sink9_data[62] => src_payload.IN1 +sink9_data[63] => src_payload.IN1 +sink9_data[64] => src_payload.IN1 +sink9_data[65] => src_payload.IN1 +sink9_data[66] => src_payload.IN1 +sink9_data[67] => src_payload.IN1 +sink9_data[68] => src_payload.IN1 +sink9_data[69] => src_payload.IN1 +sink9_data[70] => src_payload.IN1 +sink9_data[71] => src_payload.IN1 +sink9_data[72] => src_payload.IN1 +sink9_data[73] => src_payload.IN1 +sink9_data[74] => src_payload.IN1 +sink9_data[75] => src_payload.IN1 +sink9_data[76] => src_payload.IN1 +sink9_data[77] => src_payload.IN1 +sink9_data[78] => src_payload.IN1 +sink9_data[79] => src_payload.IN1 +sink9_data[80] => src_payload.IN1 +sink9_data[81] => src_payload.IN1 +sink9_data[82] => src_payload.IN1 +sink9_data[83] => src_payload.IN1 +sink9_data[84] => src_payload.IN1 +sink9_data[85] => src_payload.IN1 +sink9_data[86] => src_payload.IN1 +sink9_data[87] => src_payload.IN1 +sink9_data[88] => src_payload.IN1 +sink9_data[89] => src_payload.IN1 +sink9_data[90] => src_payload.IN1 +sink9_data[91] => src_payload.IN1 +sink9_data[92] => src_payload.IN1 +sink9_data[93] => src_payload.IN1 +sink9_data[94] => src_payload.IN1 +sink9_data[95] => src_payload.IN1 +sink9_channel[0] => src_payload.IN1 +sink9_channel[1] => src_payload.IN1 +sink9_channel[2] => src_payload.IN1 +sink9_channel[3] => src_payload.IN1 +sink9_channel[4] => src_payload.IN1 +sink9_channel[5] => src_payload.IN1 +sink9_channel[6] => src_payload.IN1 +sink9_channel[7] => src_payload.IN1 +sink9_channel[8] => src_payload.IN1 +sink9_channel[9] => src_payload.IN1 +sink9_channel[10] => src_payload.IN1 +sink9_channel[11] => src_payload.IN1 +sink9_channel[12] => src_payload.IN1 +sink9_channel[13] => src_payload.IN1 +sink9_channel[14] => src_payload.IN1 +sink9_channel[15] => src_payload.IN1 +sink9_channel[16] => src_payload.IN1 +sink9_channel[17] => src_payload.IN1 +sink9_startofpacket => src_payload.IN1 +sink9_endofpacket => src_payload.IN1 +sink9_ready <= sink9_ready.DB_MAX_OUTPUT_PORT_TYPE +sink10_valid => request[10].IN1 +sink10_data[0] => src_payload.IN1 +sink10_data[1] => src_payload.IN1 +sink10_data[2] => src_payload.IN1 +sink10_data[3] => src_payload.IN1 +sink10_data[4] => src_payload.IN1 +sink10_data[5] => src_payload.IN1 +sink10_data[6] => src_payload.IN1 +sink10_data[7] => src_payload.IN1 +sink10_data[8] => src_payload.IN1 +sink10_data[9] => src_payload.IN1 +sink10_data[10] => src_payload.IN1 +sink10_data[11] => src_payload.IN1 +sink10_data[12] => src_payload.IN1 +sink10_data[13] => src_payload.IN1 +sink10_data[14] => src_payload.IN1 +sink10_data[15] => src_payload.IN1 +sink10_data[16] => src_payload.IN1 +sink10_data[17] => src_payload.IN1 +sink10_data[18] => src_payload.IN1 +sink10_data[19] => src_payload.IN1 +sink10_data[20] => src_payload.IN1 +sink10_data[21] => src_payload.IN1 +sink10_data[22] => src_payload.IN1 +sink10_data[23] => src_payload.IN1 +sink10_data[24] => src_payload.IN1 +sink10_data[25] => src_payload.IN1 +sink10_data[26] => src_payload.IN1 +sink10_data[27] => src_payload.IN1 +sink10_data[28] => src_payload.IN1 +sink10_data[29] => src_payload.IN1 +sink10_data[30] => src_payload.IN1 +sink10_data[31] => src_payload.IN1 +sink10_data[32] => src_payload.IN1 +sink10_data[33] => src_payload.IN1 +sink10_data[34] => src_payload.IN1 +sink10_data[35] => src_payload.IN1 +sink10_data[36] => src_payload.IN1 +sink10_data[37] => src_payload.IN1 +sink10_data[38] => src_payload.IN1 +sink10_data[39] => src_payload.IN1 +sink10_data[40] => src_payload.IN1 +sink10_data[41] => src_payload.IN1 +sink10_data[42] => src_payload.IN1 +sink10_data[43] => src_payload.IN1 +sink10_data[44] => src_payload.IN1 +sink10_data[45] => src_payload.IN1 +sink10_data[46] => src_payload.IN1 +sink10_data[47] => src_payload.IN1 +sink10_data[48] => src_payload.IN1 +sink10_data[49] => src_payload.IN1 +sink10_data[50] => src_payload.IN1 +sink10_data[51] => src_payload.IN1 +sink10_data[52] => src_payload.IN1 +sink10_data[53] => src_payload.IN1 +sink10_data[54] => src_payload.IN1 +sink10_data[55] => src_payload.IN1 +sink10_data[56] => src_payload.IN1 +sink10_data[57] => src_payload.IN1 +sink10_data[58] => src_payload.IN1 +sink10_data[59] => src_payload.IN1 +sink10_data[59] => last_cycle.IN1 +sink10_data[60] => src_payload.IN1 +sink10_data[61] => src_payload.IN1 +sink10_data[62] => src_payload.IN1 +sink10_data[63] => src_payload.IN1 +sink10_data[64] => src_payload.IN1 +sink10_data[65] => src_payload.IN1 +sink10_data[66] => src_payload.IN1 +sink10_data[67] => src_payload.IN1 +sink10_data[68] => src_payload.IN1 +sink10_data[69] => src_payload.IN1 +sink10_data[70] => src_payload.IN1 +sink10_data[71] => src_payload.IN1 +sink10_data[72] => src_payload.IN1 +sink10_data[73] => src_payload.IN1 +sink10_data[74] => src_payload.IN1 +sink10_data[75] => src_payload.IN1 +sink10_data[76] => src_payload.IN1 +sink10_data[77] => src_payload.IN1 +sink10_data[78] => src_payload.IN1 +sink10_data[79] => src_payload.IN1 +sink10_data[80] => src_payload.IN1 +sink10_data[81] => src_payload.IN1 +sink10_data[82] => src_payload.IN1 +sink10_data[83] => src_payload.IN1 +sink10_data[84] => src_payload.IN1 +sink10_data[85] => src_payload.IN1 +sink10_data[86] => src_payload.IN1 +sink10_data[87] => src_payload.IN1 +sink10_data[88] => src_payload.IN1 +sink10_data[89] => src_payload.IN1 +sink10_data[90] => src_payload.IN1 +sink10_data[91] => src_payload.IN1 +sink10_data[92] => src_payload.IN1 +sink10_data[93] => src_payload.IN1 +sink10_data[94] => src_payload.IN1 +sink10_data[95] => src_payload.IN1 +sink10_channel[0] => src_payload.IN1 +sink10_channel[1] => src_payload.IN1 +sink10_channel[2] => src_payload.IN1 +sink10_channel[3] => src_payload.IN1 +sink10_channel[4] => src_payload.IN1 +sink10_channel[5] => src_payload.IN1 +sink10_channel[6] => src_payload.IN1 +sink10_channel[7] => src_payload.IN1 +sink10_channel[8] => src_payload.IN1 +sink10_channel[9] => src_payload.IN1 +sink10_channel[10] => src_payload.IN1 +sink10_channel[11] => src_payload.IN1 +sink10_channel[12] => src_payload.IN1 +sink10_channel[13] => src_payload.IN1 +sink10_channel[14] => src_payload.IN1 +sink10_channel[15] => src_payload.IN1 +sink10_channel[16] => src_payload.IN1 +sink10_channel[17] => src_payload.IN1 +sink10_startofpacket => src_payload.IN1 +sink10_endofpacket => src_payload.IN1 +sink10_ready <= sink10_ready.DB_MAX_OUTPUT_PORT_TYPE +sink11_valid => request[11].IN1 +sink11_data[0] => src_payload.IN1 +sink11_data[1] => src_payload.IN1 +sink11_data[2] => src_payload.IN1 +sink11_data[3] => src_payload.IN1 +sink11_data[4] => src_payload.IN1 +sink11_data[5] => src_payload.IN1 +sink11_data[6] => src_payload.IN1 +sink11_data[7] => src_payload.IN1 +sink11_data[8] => src_payload.IN1 +sink11_data[9] => src_payload.IN1 +sink11_data[10] => src_payload.IN1 +sink11_data[11] => src_payload.IN1 +sink11_data[12] => src_payload.IN1 +sink11_data[13] => src_payload.IN1 +sink11_data[14] => src_payload.IN1 +sink11_data[15] => src_payload.IN1 +sink11_data[16] => src_payload.IN1 +sink11_data[17] => src_payload.IN1 +sink11_data[18] => src_payload.IN1 +sink11_data[19] => src_payload.IN1 +sink11_data[20] => src_payload.IN1 +sink11_data[21] => src_payload.IN1 +sink11_data[22] => src_payload.IN1 +sink11_data[23] => src_payload.IN1 +sink11_data[24] => src_payload.IN1 +sink11_data[25] => src_payload.IN1 +sink11_data[26] => src_payload.IN1 +sink11_data[27] => src_payload.IN1 +sink11_data[28] => src_payload.IN1 +sink11_data[29] => src_payload.IN1 +sink11_data[30] => src_payload.IN1 +sink11_data[31] => src_payload.IN1 +sink11_data[32] => src_payload.IN1 +sink11_data[33] => src_payload.IN1 +sink11_data[34] => src_payload.IN1 +sink11_data[35] => src_payload.IN1 +sink11_data[36] => src_payload.IN1 +sink11_data[37] => src_payload.IN1 +sink11_data[38] => src_payload.IN1 +sink11_data[39] => src_payload.IN1 +sink11_data[40] => src_payload.IN1 +sink11_data[41] => src_payload.IN1 +sink11_data[42] => src_payload.IN1 +sink11_data[43] => src_payload.IN1 +sink11_data[44] => src_payload.IN1 +sink11_data[45] => src_payload.IN1 +sink11_data[46] => src_payload.IN1 +sink11_data[47] => src_payload.IN1 +sink11_data[48] => src_payload.IN1 +sink11_data[49] => src_payload.IN1 +sink11_data[50] => src_payload.IN1 +sink11_data[51] => src_payload.IN1 +sink11_data[52] => src_payload.IN1 +sink11_data[53] => src_payload.IN1 +sink11_data[54] => src_payload.IN1 +sink11_data[55] => src_payload.IN1 +sink11_data[56] => src_payload.IN1 +sink11_data[57] => src_payload.IN1 +sink11_data[58] => src_payload.IN1 +sink11_data[59] => src_payload.IN1 +sink11_data[59] => last_cycle.IN1 +sink11_data[60] => src_payload.IN1 +sink11_data[61] => src_payload.IN1 +sink11_data[62] => src_payload.IN1 +sink11_data[63] => src_payload.IN1 +sink11_data[64] => src_payload.IN1 +sink11_data[65] => src_payload.IN1 +sink11_data[66] => src_payload.IN1 +sink11_data[67] => src_payload.IN1 +sink11_data[68] => src_payload.IN1 +sink11_data[69] => src_payload.IN1 +sink11_data[70] => src_payload.IN1 +sink11_data[71] => src_payload.IN1 +sink11_data[72] => src_payload.IN1 +sink11_data[73] => src_payload.IN1 +sink11_data[74] => src_payload.IN1 +sink11_data[75] => src_payload.IN1 +sink11_data[76] => src_payload.IN1 +sink11_data[77] => src_payload.IN1 +sink11_data[78] => src_payload.IN1 +sink11_data[79] => src_payload.IN1 +sink11_data[80] => src_payload.IN1 +sink11_data[81] => src_payload.IN1 +sink11_data[82] => src_payload.IN1 +sink11_data[83] => src_payload.IN1 +sink11_data[84] => src_payload.IN1 +sink11_data[85] => src_payload.IN1 +sink11_data[86] => src_payload.IN1 +sink11_data[87] => src_payload.IN1 +sink11_data[88] => src_payload.IN1 +sink11_data[89] => src_payload.IN1 +sink11_data[90] => src_payload.IN1 +sink11_data[91] => src_payload.IN1 +sink11_data[92] => src_payload.IN1 +sink11_data[93] => src_payload.IN1 +sink11_data[94] => src_payload.IN1 +sink11_data[95] => src_payload.IN1 +sink11_channel[0] => src_payload.IN1 +sink11_channel[1] => src_payload.IN1 +sink11_channel[2] => src_payload.IN1 +sink11_channel[3] => src_payload.IN1 +sink11_channel[4] => src_payload.IN1 +sink11_channel[5] => src_payload.IN1 +sink11_channel[6] => src_payload.IN1 +sink11_channel[7] => src_payload.IN1 +sink11_channel[8] => src_payload.IN1 +sink11_channel[9] => src_payload.IN1 +sink11_channel[10] => src_payload.IN1 +sink11_channel[11] => src_payload.IN1 +sink11_channel[12] => src_payload.IN1 +sink11_channel[13] => src_payload.IN1 +sink11_channel[14] => src_payload.IN1 +sink11_channel[15] => src_payload.IN1 +sink11_channel[16] => src_payload.IN1 +sink11_channel[17] => src_payload.IN1 +sink11_startofpacket => src_payload.IN1 +sink11_endofpacket => src_payload.IN1 +sink11_ready <= sink11_ready.DB_MAX_OUTPUT_PORT_TYPE +sink12_valid => request[12].IN1 +sink12_data[0] => src_payload.IN1 +sink12_data[1] => src_payload.IN1 +sink12_data[2] => src_payload.IN1 +sink12_data[3] => src_payload.IN1 +sink12_data[4] => src_payload.IN1 +sink12_data[5] => src_payload.IN1 +sink12_data[6] => src_payload.IN1 +sink12_data[7] => src_payload.IN1 +sink12_data[8] => src_payload.IN1 +sink12_data[9] => src_payload.IN1 +sink12_data[10] => src_payload.IN1 +sink12_data[11] => src_payload.IN1 +sink12_data[12] => src_payload.IN1 +sink12_data[13] => src_payload.IN1 +sink12_data[14] => src_payload.IN1 +sink12_data[15] => src_payload.IN1 +sink12_data[16] => src_payload.IN1 +sink12_data[17] => src_payload.IN1 +sink12_data[18] => src_payload.IN1 +sink12_data[19] => src_payload.IN1 +sink12_data[20] => src_payload.IN1 +sink12_data[21] => src_payload.IN1 +sink12_data[22] => src_payload.IN1 +sink12_data[23] => src_payload.IN1 +sink12_data[24] => src_payload.IN1 +sink12_data[25] => src_payload.IN1 +sink12_data[26] => src_payload.IN1 +sink12_data[27] => src_payload.IN1 +sink12_data[28] => src_payload.IN1 +sink12_data[29] => src_payload.IN1 +sink12_data[30] => src_payload.IN1 +sink12_data[31] => src_payload.IN1 +sink12_data[32] => src_payload.IN1 +sink12_data[33] => src_payload.IN1 +sink12_data[34] => src_payload.IN1 +sink12_data[35] => src_payload.IN1 +sink12_data[36] => src_payload.IN1 +sink12_data[37] => src_payload.IN1 +sink12_data[38] => src_payload.IN1 +sink12_data[39] => src_payload.IN1 +sink12_data[40] => src_payload.IN1 +sink12_data[41] => src_payload.IN1 +sink12_data[42] => src_payload.IN1 +sink12_data[43] => src_payload.IN1 +sink12_data[44] => src_payload.IN1 +sink12_data[45] => src_payload.IN1 +sink12_data[46] => src_payload.IN1 +sink12_data[47] => src_payload.IN1 +sink12_data[48] => src_payload.IN1 +sink12_data[49] => src_payload.IN1 +sink12_data[50] => src_payload.IN1 +sink12_data[51] => src_payload.IN1 +sink12_data[52] => src_payload.IN1 +sink12_data[53] => src_payload.IN1 +sink12_data[54] => src_payload.IN1 +sink12_data[55] => src_payload.IN1 +sink12_data[56] => src_payload.IN1 +sink12_data[57] => src_payload.IN1 +sink12_data[58] => src_payload.IN1 +sink12_data[59] => src_payload.IN1 +sink12_data[59] => last_cycle.IN1 +sink12_data[60] => src_payload.IN1 +sink12_data[61] => src_payload.IN1 +sink12_data[62] => src_payload.IN1 +sink12_data[63] => src_payload.IN1 +sink12_data[64] => src_payload.IN1 +sink12_data[65] => src_payload.IN1 +sink12_data[66] => src_payload.IN1 +sink12_data[67] => src_payload.IN1 +sink12_data[68] => src_payload.IN1 +sink12_data[69] => src_payload.IN1 +sink12_data[70] => src_payload.IN1 +sink12_data[71] => src_payload.IN1 +sink12_data[72] => src_payload.IN1 +sink12_data[73] => src_payload.IN1 +sink12_data[74] => src_payload.IN1 +sink12_data[75] => src_payload.IN1 +sink12_data[76] => src_payload.IN1 +sink12_data[77] => src_payload.IN1 +sink12_data[78] => src_payload.IN1 +sink12_data[79] => src_payload.IN1 +sink12_data[80] => src_payload.IN1 +sink12_data[81] => src_payload.IN1 +sink12_data[82] => src_payload.IN1 +sink12_data[83] => src_payload.IN1 +sink12_data[84] => src_payload.IN1 +sink12_data[85] => src_payload.IN1 +sink12_data[86] => src_payload.IN1 +sink12_data[87] => src_payload.IN1 +sink12_data[88] => src_payload.IN1 +sink12_data[89] => src_payload.IN1 +sink12_data[90] => src_payload.IN1 +sink12_data[91] => src_payload.IN1 +sink12_data[92] => src_payload.IN1 +sink12_data[93] => src_payload.IN1 +sink12_data[94] => src_payload.IN1 +sink12_data[95] => src_payload.IN1 +sink12_channel[0] => src_payload.IN1 +sink12_channel[1] => src_payload.IN1 +sink12_channel[2] => src_payload.IN1 +sink12_channel[3] => src_payload.IN1 +sink12_channel[4] => src_payload.IN1 +sink12_channel[5] => src_payload.IN1 +sink12_channel[6] => src_payload.IN1 +sink12_channel[7] => src_payload.IN1 +sink12_channel[8] => src_payload.IN1 +sink12_channel[9] => src_payload.IN1 +sink12_channel[10] => src_payload.IN1 +sink12_channel[11] => src_payload.IN1 +sink12_channel[12] => src_payload.IN1 +sink12_channel[13] => src_payload.IN1 +sink12_channel[14] => src_payload.IN1 +sink12_channel[15] => src_payload.IN1 +sink12_channel[16] => src_payload.IN1 +sink12_channel[17] => src_payload.IN1 +sink12_startofpacket => src_payload.IN1 +sink12_endofpacket => src_payload.IN1 +sink12_ready <= sink12_ready.DB_MAX_OUTPUT_PORT_TYPE +sink13_valid => request[13].IN1 +sink13_data[0] => src_payload.IN1 +sink13_data[1] => src_payload.IN1 +sink13_data[2] => src_payload.IN1 +sink13_data[3] => src_payload.IN1 +sink13_data[4] => src_payload.IN1 +sink13_data[5] => src_payload.IN1 +sink13_data[6] => src_payload.IN1 +sink13_data[7] => src_payload.IN1 +sink13_data[8] => src_payload.IN1 +sink13_data[9] => src_payload.IN1 +sink13_data[10] => src_payload.IN1 +sink13_data[11] => src_payload.IN1 +sink13_data[12] => src_payload.IN1 +sink13_data[13] => src_payload.IN1 +sink13_data[14] => src_payload.IN1 +sink13_data[15] => src_payload.IN1 +sink13_data[16] => src_payload.IN1 +sink13_data[17] => src_payload.IN1 +sink13_data[18] => src_payload.IN1 +sink13_data[19] => src_payload.IN1 +sink13_data[20] => src_payload.IN1 +sink13_data[21] => src_payload.IN1 +sink13_data[22] => src_payload.IN1 +sink13_data[23] => src_payload.IN1 +sink13_data[24] => src_payload.IN1 +sink13_data[25] => src_payload.IN1 +sink13_data[26] => src_payload.IN1 +sink13_data[27] => src_payload.IN1 +sink13_data[28] => src_payload.IN1 +sink13_data[29] => src_payload.IN1 +sink13_data[30] => src_payload.IN1 +sink13_data[31] => src_payload.IN1 +sink13_data[32] => src_payload.IN1 +sink13_data[33] => src_payload.IN1 +sink13_data[34] => src_payload.IN1 +sink13_data[35] => src_payload.IN1 +sink13_data[36] => src_payload.IN1 +sink13_data[37] => src_payload.IN1 +sink13_data[38] => src_payload.IN1 +sink13_data[39] => src_payload.IN1 +sink13_data[40] => src_payload.IN1 +sink13_data[41] => src_payload.IN1 +sink13_data[42] => src_payload.IN1 +sink13_data[43] => src_payload.IN1 +sink13_data[44] => src_payload.IN1 +sink13_data[45] => src_payload.IN1 +sink13_data[46] => src_payload.IN1 +sink13_data[47] => src_payload.IN1 +sink13_data[48] => src_payload.IN1 +sink13_data[49] => src_payload.IN1 +sink13_data[50] => src_payload.IN1 +sink13_data[51] => src_payload.IN1 +sink13_data[52] => src_payload.IN1 +sink13_data[53] => src_payload.IN1 +sink13_data[54] => src_payload.IN1 +sink13_data[55] => src_payload.IN1 +sink13_data[56] => src_payload.IN1 +sink13_data[57] => src_payload.IN1 +sink13_data[58] => src_payload.IN1 +sink13_data[59] => src_payload.IN1 +sink13_data[59] => last_cycle.IN1 +sink13_data[60] => src_payload.IN1 +sink13_data[61] => src_payload.IN1 +sink13_data[62] => src_payload.IN1 +sink13_data[63] => src_payload.IN1 +sink13_data[64] => src_payload.IN1 +sink13_data[65] => src_payload.IN1 +sink13_data[66] => src_payload.IN1 +sink13_data[67] => src_payload.IN1 +sink13_data[68] => src_payload.IN1 +sink13_data[69] => src_payload.IN1 +sink13_data[70] => src_payload.IN1 +sink13_data[71] => src_payload.IN1 +sink13_data[72] => src_payload.IN1 +sink13_data[73] => src_payload.IN1 +sink13_data[74] => src_payload.IN1 +sink13_data[75] => src_payload.IN1 +sink13_data[76] => src_payload.IN1 +sink13_data[77] => src_payload.IN1 +sink13_data[78] => src_payload.IN1 +sink13_data[79] => src_payload.IN1 +sink13_data[80] => src_payload.IN1 +sink13_data[81] => src_payload.IN1 +sink13_data[82] => src_payload.IN1 +sink13_data[83] => src_payload.IN1 +sink13_data[84] => src_payload.IN1 +sink13_data[85] => src_payload.IN1 +sink13_data[86] => src_payload.IN1 +sink13_data[87] => src_payload.IN1 +sink13_data[88] => src_payload.IN1 +sink13_data[89] => src_payload.IN1 +sink13_data[90] => src_payload.IN1 +sink13_data[91] => src_payload.IN1 +sink13_data[92] => src_payload.IN1 +sink13_data[93] => src_payload.IN1 +sink13_data[94] => src_payload.IN1 +sink13_data[95] => src_payload.IN1 +sink13_channel[0] => src_payload.IN1 +sink13_channel[1] => src_payload.IN1 +sink13_channel[2] => src_payload.IN1 +sink13_channel[3] => src_payload.IN1 +sink13_channel[4] => src_payload.IN1 +sink13_channel[5] => src_payload.IN1 +sink13_channel[6] => src_payload.IN1 +sink13_channel[7] => src_payload.IN1 +sink13_channel[8] => src_payload.IN1 +sink13_channel[9] => src_payload.IN1 +sink13_channel[10] => src_payload.IN1 +sink13_channel[11] => src_payload.IN1 +sink13_channel[12] => src_payload.IN1 +sink13_channel[13] => src_payload.IN1 +sink13_channel[14] => src_payload.IN1 +sink13_channel[15] => src_payload.IN1 +sink13_channel[16] => src_payload.IN1 +sink13_channel[17] => src_payload.IN1 +sink13_startofpacket => src_payload.IN1 +sink13_endofpacket => src_payload.IN1 +sink13_ready <= sink13_ready.DB_MAX_OUTPUT_PORT_TYPE +sink14_valid => request[14].IN1 +sink14_data[0] => src_payload.IN1 +sink14_data[1] => src_payload.IN1 +sink14_data[2] => src_payload.IN1 +sink14_data[3] => src_payload.IN1 +sink14_data[4] => src_payload.IN1 +sink14_data[5] => src_payload.IN1 +sink14_data[6] => src_payload.IN1 +sink14_data[7] => src_payload.IN1 +sink14_data[8] => src_payload.IN1 +sink14_data[9] => src_payload.IN1 +sink14_data[10] => src_payload.IN1 +sink14_data[11] => src_payload.IN1 +sink14_data[12] => src_payload.IN1 +sink14_data[13] => src_payload.IN1 +sink14_data[14] => src_payload.IN1 +sink14_data[15] => src_payload.IN1 +sink14_data[16] => src_payload.IN1 +sink14_data[17] => src_payload.IN1 +sink14_data[18] => src_payload.IN1 +sink14_data[19] => src_payload.IN1 +sink14_data[20] => src_payload.IN1 +sink14_data[21] => src_payload.IN1 +sink14_data[22] => src_payload.IN1 +sink14_data[23] => src_payload.IN1 +sink14_data[24] => src_payload.IN1 +sink14_data[25] => src_payload.IN1 +sink14_data[26] => src_payload.IN1 +sink14_data[27] => src_payload.IN1 +sink14_data[28] => src_payload.IN1 +sink14_data[29] => src_payload.IN1 +sink14_data[30] => src_payload.IN1 +sink14_data[31] => src_payload.IN1 +sink14_data[32] => src_payload.IN1 +sink14_data[33] => src_payload.IN1 +sink14_data[34] => src_payload.IN1 +sink14_data[35] => src_payload.IN1 +sink14_data[36] => src_payload.IN1 +sink14_data[37] => src_payload.IN1 +sink14_data[38] => src_payload.IN1 +sink14_data[39] => src_payload.IN1 +sink14_data[40] => src_payload.IN1 +sink14_data[41] => src_payload.IN1 +sink14_data[42] => src_payload.IN1 +sink14_data[43] => src_payload.IN1 +sink14_data[44] => src_payload.IN1 +sink14_data[45] => src_payload.IN1 +sink14_data[46] => src_payload.IN1 +sink14_data[47] => src_payload.IN1 +sink14_data[48] => src_payload.IN1 +sink14_data[49] => src_payload.IN1 +sink14_data[50] => src_payload.IN1 +sink14_data[51] => src_payload.IN1 +sink14_data[52] => src_payload.IN1 +sink14_data[53] => src_payload.IN1 +sink14_data[54] => src_payload.IN1 +sink14_data[55] => src_payload.IN1 +sink14_data[56] => src_payload.IN1 +sink14_data[57] => src_payload.IN1 +sink14_data[58] => src_payload.IN1 +sink14_data[59] => src_payload.IN1 +sink14_data[59] => last_cycle.IN1 +sink14_data[60] => src_payload.IN1 +sink14_data[61] => src_payload.IN1 +sink14_data[62] => src_payload.IN1 +sink14_data[63] => src_payload.IN1 +sink14_data[64] => src_payload.IN1 +sink14_data[65] => src_payload.IN1 +sink14_data[66] => src_payload.IN1 +sink14_data[67] => src_payload.IN1 +sink14_data[68] => src_payload.IN1 +sink14_data[69] => src_payload.IN1 +sink14_data[70] => src_payload.IN1 +sink14_data[71] => src_payload.IN1 +sink14_data[72] => src_payload.IN1 +sink14_data[73] => src_payload.IN1 +sink14_data[74] => src_payload.IN1 +sink14_data[75] => src_payload.IN1 +sink14_data[76] => src_payload.IN1 +sink14_data[77] => src_payload.IN1 +sink14_data[78] => src_payload.IN1 +sink14_data[79] => src_payload.IN1 +sink14_data[80] => src_payload.IN1 +sink14_data[81] => src_payload.IN1 +sink14_data[82] => src_payload.IN1 +sink14_data[83] => src_payload.IN1 +sink14_data[84] => src_payload.IN1 +sink14_data[85] => src_payload.IN1 +sink14_data[86] => src_payload.IN1 +sink14_data[87] => src_payload.IN1 +sink14_data[88] => src_payload.IN1 +sink14_data[89] => src_payload.IN1 +sink14_data[90] => src_payload.IN1 +sink14_data[91] => src_payload.IN1 +sink14_data[92] => src_payload.IN1 +sink14_data[93] => src_payload.IN1 +sink14_data[94] => src_payload.IN1 +sink14_data[95] => src_payload.IN1 +sink14_channel[0] => src_payload.IN1 +sink14_channel[1] => src_payload.IN1 +sink14_channel[2] => src_payload.IN1 +sink14_channel[3] => src_payload.IN1 +sink14_channel[4] => src_payload.IN1 +sink14_channel[5] => src_payload.IN1 +sink14_channel[6] => src_payload.IN1 +sink14_channel[7] => src_payload.IN1 +sink14_channel[8] => src_payload.IN1 +sink14_channel[9] => src_payload.IN1 +sink14_channel[10] => src_payload.IN1 +sink14_channel[11] => src_payload.IN1 +sink14_channel[12] => src_payload.IN1 +sink14_channel[13] => src_payload.IN1 +sink14_channel[14] => src_payload.IN1 +sink14_channel[15] => src_payload.IN1 +sink14_channel[16] => src_payload.IN1 +sink14_channel[17] => src_payload.IN1 +sink14_startofpacket => src_payload.IN1 +sink14_endofpacket => src_payload.IN1 +sink14_ready <= sink14_ready.DB_MAX_OUTPUT_PORT_TYPE +sink15_valid => request[15].IN1 +sink15_data[0] => src_payload.IN1 +sink15_data[1] => src_payload.IN1 +sink15_data[2] => src_payload.IN1 +sink15_data[3] => src_payload.IN1 +sink15_data[4] => src_payload.IN1 +sink15_data[5] => src_payload.IN1 +sink15_data[6] => src_payload.IN1 +sink15_data[7] => src_payload.IN1 +sink15_data[8] => src_payload.IN1 +sink15_data[9] => src_payload.IN1 +sink15_data[10] => src_payload.IN1 +sink15_data[11] => src_payload.IN1 +sink15_data[12] => src_payload.IN1 +sink15_data[13] => src_payload.IN1 +sink15_data[14] => src_payload.IN1 +sink15_data[15] => src_payload.IN1 +sink15_data[16] => src_payload.IN1 +sink15_data[17] => src_payload.IN1 +sink15_data[18] => src_payload.IN1 +sink15_data[19] => src_payload.IN1 +sink15_data[20] => src_payload.IN1 +sink15_data[21] => src_payload.IN1 +sink15_data[22] => src_payload.IN1 +sink15_data[23] => src_payload.IN1 +sink15_data[24] => src_payload.IN1 +sink15_data[25] => src_payload.IN1 +sink15_data[26] => src_payload.IN1 +sink15_data[27] => src_payload.IN1 +sink15_data[28] => src_payload.IN1 +sink15_data[29] => src_payload.IN1 +sink15_data[30] => src_payload.IN1 +sink15_data[31] => src_payload.IN1 +sink15_data[32] => src_payload.IN1 +sink15_data[33] => src_payload.IN1 +sink15_data[34] => src_payload.IN1 +sink15_data[35] => src_payload.IN1 +sink15_data[36] => src_payload.IN1 +sink15_data[37] => src_payload.IN1 +sink15_data[38] => src_payload.IN1 +sink15_data[39] => src_payload.IN1 +sink15_data[40] => src_payload.IN1 +sink15_data[41] => src_payload.IN1 +sink15_data[42] => src_payload.IN1 +sink15_data[43] => src_payload.IN1 +sink15_data[44] => src_payload.IN1 +sink15_data[45] => src_payload.IN1 +sink15_data[46] => src_payload.IN1 +sink15_data[47] => src_payload.IN1 +sink15_data[48] => src_payload.IN1 +sink15_data[49] => src_payload.IN1 +sink15_data[50] => src_payload.IN1 +sink15_data[51] => src_payload.IN1 +sink15_data[52] => src_payload.IN1 +sink15_data[53] => src_payload.IN1 +sink15_data[54] => src_payload.IN1 +sink15_data[55] => src_payload.IN1 +sink15_data[56] => src_payload.IN1 +sink15_data[57] => src_payload.IN1 +sink15_data[58] => src_payload.IN1 +sink15_data[59] => src_payload.IN1 +sink15_data[59] => last_cycle.IN1 +sink15_data[60] => src_payload.IN1 +sink15_data[61] => src_payload.IN1 +sink15_data[62] => src_payload.IN1 +sink15_data[63] => src_payload.IN1 +sink15_data[64] => src_payload.IN1 +sink15_data[65] => src_payload.IN1 +sink15_data[66] => src_payload.IN1 +sink15_data[67] => src_payload.IN1 +sink15_data[68] => src_payload.IN1 +sink15_data[69] => src_payload.IN1 +sink15_data[70] => src_payload.IN1 +sink15_data[71] => src_payload.IN1 +sink15_data[72] => src_payload.IN1 +sink15_data[73] => src_payload.IN1 +sink15_data[74] => src_payload.IN1 +sink15_data[75] => src_payload.IN1 +sink15_data[76] => src_payload.IN1 +sink15_data[77] => src_payload.IN1 +sink15_data[78] => src_payload.IN1 +sink15_data[79] => src_payload.IN1 +sink15_data[80] => src_payload.IN1 +sink15_data[81] => src_payload.IN1 +sink15_data[82] => src_payload.IN1 +sink15_data[83] => src_payload.IN1 +sink15_data[84] => src_payload.IN1 +sink15_data[85] => src_payload.IN1 +sink15_data[86] => src_payload.IN1 +sink15_data[87] => src_payload.IN1 +sink15_data[88] => src_payload.IN1 +sink15_data[89] => src_payload.IN1 +sink15_data[90] => src_payload.IN1 +sink15_data[91] => src_payload.IN1 +sink15_data[92] => src_payload.IN1 +sink15_data[93] => src_payload.IN1 +sink15_data[94] => src_payload.IN1 +sink15_data[95] => src_payload.IN1 +sink15_channel[0] => src_payload.IN1 +sink15_channel[1] => src_payload.IN1 +sink15_channel[2] => src_payload.IN1 +sink15_channel[3] => src_payload.IN1 +sink15_channel[4] => src_payload.IN1 +sink15_channel[5] => src_payload.IN1 +sink15_channel[6] => src_payload.IN1 +sink15_channel[7] => src_payload.IN1 +sink15_channel[8] => src_payload.IN1 +sink15_channel[9] => src_payload.IN1 +sink15_channel[10] => src_payload.IN1 +sink15_channel[11] => src_payload.IN1 +sink15_channel[12] => src_payload.IN1 +sink15_channel[13] => src_payload.IN1 +sink15_channel[14] => src_payload.IN1 +sink15_channel[15] => src_payload.IN1 +sink15_channel[16] => src_payload.IN1 +sink15_channel[17] => src_payload.IN1 +sink15_startofpacket => src_payload.IN1 +sink15_endofpacket => src_payload.IN1 +sink15_ready <= sink15_ready.DB_MAX_OUTPUT_PORT_TYPE +sink16_valid => request[16].IN1 +sink16_data[0] => src_payload.IN1 +sink16_data[1] => src_payload.IN1 +sink16_data[2] => src_payload.IN1 +sink16_data[3] => src_payload.IN1 +sink16_data[4] => src_payload.IN1 +sink16_data[5] => src_payload.IN1 +sink16_data[6] => src_payload.IN1 +sink16_data[7] => src_payload.IN1 +sink16_data[8] => src_payload.IN1 +sink16_data[9] => src_payload.IN1 +sink16_data[10] => src_payload.IN1 +sink16_data[11] => src_payload.IN1 +sink16_data[12] => src_payload.IN1 +sink16_data[13] => src_payload.IN1 +sink16_data[14] => src_payload.IN1 +sink16_data[15] => src_payload.IN1 +sink16_data[16] => src_payload.IN1 +sink16_data[17] => src_payload.IN1 +sink16_data[18] => src_payload.IN1 +sink16_data[19] => src_payload.IN1 +sink16_data[20] => src_payload.IN1 +sink16_data[21] => src_payload.IN1 +sink16_data[22] => src_payload.IN1 +sink16_data[23] => src_payload.IN1 +sink16_data[24] => src_payload.IN1 +sink16_data[25] => src_payload.IN1 +sink16_data[26] => src_payload.IN1 +sink16_data[27] => src_payload.IN1 +sink16_data[28] => src_payload.IN1 +sink16_data[29] => src_payload.IN1 +sink16_data[30] => src_payload.IN1 +sink16_data[31] => src_payload.IN1 +sink16_data[32] => src_payload.IN1 +sink16_data[33] => src_payload.IN1 +sink16_data[34] => src_payload.IN1 +sink16_data[35] => src_payload.IN1 +sink16_data[36] => src_payload.IN1 +sink16_data[37] => src_payload.IN1 +sink16_data[38] => src_payload.IN1 +sink16_data[39] => src_payload.IN1 +sink16_data[40] => src_payload.IN1 +sink16_data[41] => src_payload.IN1 +sink16_data[42] => src_payload.IN1 +sink16_data[43] => src_payload.IN1 +sink16_data[44] => src_payload.IN1 +sink16_data[45] => src_payload.IN1 +sink16_data[46] => src_payload.IN1 +sink16_data[47] => src_payload.IN1 +sink16_data[48] => src_payload.IN1 +sink16_data[49] => src_payload.IN1 +sink16_data[50] => src_payload.IN1 +sink16_data[51] => src_payload.IN1 +sink16_data[52] => src_payload.IN1 +sink16_data[53] => src_payload.IN1 +sink16_data[54] => src_payload.IN1 +sink16_data[55] => src_payload.IN1 +sink16_data[56] => src_payload.IN1 +sink16_data[57] => src_payload.IN1 +sink16_data[58] => src_payload.IN1 +sink16_data[59] => src_payload.IN1 +sink16_data[59] => last_cycle.IN1 +sink16_data[60] => src_payload.IN1 +sink16_data[61] => src_payload.IN1 +sink16_data[62] => src_payload.IN1 +sink16_data[63] => src_payload.IN1 +sink16_data[64] => src_payload.IN1 +sink16_data[65] => src_payload.IN1 +sink16_data[66] => src_payload.IN1 +sink16_data[67] => src_payload.IN1 +sink16_data[68] => src_payload.IN1 +sink16_data[69] => src_payload.IN1 +sink16_data[70] => src_payload.IN1 +sink16_data[71] => src_payload.IN1 +sink16_data[72] => src_payload.IN1 +sink16_data[73] => src_payload.IN1 +sink16_data[74] => src_payload.IN1 +sink16_data[75] => src_payload.IN1 +sink16_data[76] => src_payload.IN1 +sink16_data[77] => src_payload.IN1 +sink16_data[78] => src_payload.IN1 +sink16_data[79] => src_payload.IN1 +sink16_data[80] => src_payload.IN1 +sink16_data[81] => src_payload.IN1 +sink16_data[82] => src_payload.IN1 +sink16_data[83] => src_payload.IN1 +sink16_data[84] => src_payload.IN1 +sink16_data[85] => src_payload.IN1 +sink16_data[86] => src_payload.IN1 +sink16_data[87] => src_payload.IN1 +sink16_data[88] => src_payload.IN1 +sink16_data[89] => src_payload.IN1 +sink16_data[90] => src_payload.IN1 +sink16_data[91] => src_payload.IN1 +sink16_data[92] => src_payload.IN1 +sink16_data[93] => src_payload.IN1 +sink16_data[94] => src_payload.IN1 +sink16_data[95] => src_payload.IN1 +sink16_channel[0] => src_payload.IN1 +sink16_channel[1] => src_payload.IN1 +sink16_channel[2] => src_payload.IN1 +sink16_channel[3] => src_payload.IN1 +sink16_channel[4] => src_payload.IN1 +sink16_channel[5] => src_payload.IN1 +sink16_channel[6] => src_payload.IN1 +sink16_channel[7] => src_payload.IN1 +sink16_channel[8] => src_payload.IN1 +sink16_channel[9] => src_payload.IN1 +sink16_channel[10] => src_payload.IN1 +sink16_channel[11] => src_payload.IN1 +sink16_channel[12] => src_payload.IN1 +sink16_channel[13] => src_payload.IN1 +sink16_channel[14] => src_payload.IN1 +sink16_channel[15] => src_payload.IN1 +sink16_channel[16] => src_payload.IN1 +sink16_channel[17] => src_payload.IN1 +sink16_startofpacket => src_payload.IN1 +sink16_endofpacket => src_payload.IN1 +sink16_ready <= sink16_ready.DB_MAX_OUTPUT_PORT_TYPE +sink17_valid => request[17].IN1 +sink17_data[0] => src_payload.IN1 +sink17_data[1] => src_payload.IN1 +sink17_data[2] => src_payload.IN1 +sink17_data[3] => src_payload.IN1 +sink17_data[4] => src_payload.IN1 +sink17_data[5] => src_payload.IN1 +sink17_data[6] => src_payload.IN1 +sink17_data[7] => src_payload.IN1 +sink17_data[8] => src_payload.IN1 +sink17_data[9] => src_payload.IN1 +sink17_data[10] => src_payload.IN1 +sink17_data[11] => src_payload.IN1 +sink17_data[12] => src_payload.IN1 +sink17_data[13] => src_payload.IN1 +sink17_data[14] => src_payload.IN1 +sink17_data[15] => src_payload.IN1 +sink17_data[16] => src_payload.IN1 +sink17_data[17] => src_payload.IN1 +sink17_data[18] => src_payload.IN1 +sink17_data[19] => src_payload.IN1 +sink17_data[20] => src_payload.IN1 +sink17_data[21] => src_payload.IN1 +sink17_data[22] => src_payload.IN1 +sink17_data[23] => src_payload.IN1 +sink17_data[24] => src_payload.IN1 +sink17_data[25] => src_payload.IN1 +sink17_data[26] => src_payload.IN1 +sink17_data[27] => src_payload.IN1 +sink17_data[28] => src_payload.IN1 +sink17_data[29] => src_payload.IN1 +sink17_data[30] => src_payload.IN1 +sink17_data[31] => src_payload.IN1 +sink17_data[32] => src_payload.IN1 +sink17_data[33] => src_payload.IN1 +sink17_data[34] => src_payload.IN1 +sink17_data[35] => src_payload.IN1 +sink17_data[36] => src_payload.IN1 +sink17_data[37] => src_payload.IN1 +sink17_data[38] => src_payload.IN1 +sink17_data[39] => src_payload.IN1 +sink17_data[40] => src_payload.IN1 +sink17_data[41] => src_payload.IN1 +sink17_data[42] => src_payload.IN1 +sink17_data[43] => src_payload.IN1 +sink17_data[44] => src_payload.IN1 +sink17_data[45] => src_payload.IN1 +sink17_data[46] => src_payload.IN1 +sink17_data[47] => src_payload.IN1 +sink17_data[48] => src_payload.IN1 +sink17_data[49] => src_payload.IN1 +sink17_data[50] => src_payload.IN1 +sink17_data[51] => src_payload.IN1 +sink17_data[52] => src_payload.IN1 +sink17_data[53] => src_payload.IN1 +sink17_data[54] => src_payload.IN1 +sink17_data[55] => src_payload.IN1 +sink17_data[56] => src_payload.IN1 +sink17_data[57] => src_payload.IN1 +sink17_data[58] => src_payload.IN1 +sink17_data[59] => src_payload.IN1 +sink17_data[59] => last_cycle.IN1 +sink17_data[60] => src_payload.IN1 +sink17_data[61] => src_payload.IN1 +sink17_data[62] => src_payload.IN1 +sink17_data[63] => src_payload.IN1 +sink17_data[64] => src_payload.IN1 +sink17_data[65] => src_payload.IN1 +sink17_data[66] => src_payload.IN1 +sink17_data[67] => src_payload.IN1 +sink17_data[68] => src_payload.IN1 +sink17_data[69] => src_payload.IN1 +sink17_data[70] => src_payload.IN1 +sink17_data[71] => src_payload.IN1 +sink17_data[72] => src_payload.IN1 +sink17_data[73] => src_payload.IN1 +sink17_data[74] => src_payload.IN1 +sink17_data[75] => src_payload.IN1 +sink17_data[76] => src_payload.IN1 +sink17_data[77] => src_payload.IN1 +sink17_data[78] => src_payload.IN1 +sink17_data[79] => src_payload.IN1 +sink17_data[80] => src_payload.IN1 +sink17_data[81] => src_payload.IN1 +sink17_data[82] => src_payload.IN1 +sink17_data[83] => src_payload.IN1 +sink17_data[84] => src_payload.IN1 +sink17_data[85] => src_payload.IN1 +sink17_data[86] => src_payload.IN1 +sink17_data[87] => src_payload.IN1 +sink17_data[88] => src_payload.IN1 +sink17_data[89] => src_payload.IN1 +sink17_data[90] => src_payload.IN1 +sink17_data[91] => src_payload.IN1 +sink17_data[92] => src_payload.IN1 +sink17_data[93] => src_payload.IN1 +sink17_data[94] => src_payload.IN1 +sink17_data[95] => src_payload.IN1 +sink17_channel[0] => src_payload.IN1 +sink17_channel[1] => src_payload.IN1 +sink17_channel[2] => src_payload.IN1 +sink17_channel[3] => src_payload.IN1 +sink17_channel[4] => src_payload.IN1 +sink17_channel[5] => src_payload.IN1 +sink17_channel[6] => src_payload.IN1 +sink17_channel[7] => src_payload.IN1 +sink17_channel[8] => src_payload.IN1 +sink17_channel[9] => src_payload.IN1 +sink17_channel[10] => src_payload.IN1 +sink17_channel[11] => src_payload.IN1 +sink17_channel[12] => src_payload.IN1 +sink17_channel[13] => src_payload.IN1 +sink17_channel[14] => src_payload.IN1 +sink17_channel[15] => src_payload.IN1 +sink17_channel[16] => src_payload.IN1 +sink17_channel[17] => src_payload.IN1 +sink17_startofpacket => src_payload.IN1 +sink17_endofpacket => src_payload.IN1 +sink17_ready <= sink17_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +src_ready => sink2_ready.IN1 +src_ready => sink3_ready.IN1 +src_ready => sink4_ready.IN1 +src_ready => sink5_ready.IN1 +src_ready => sink6_ready.IN1 +src_ready => sink7_ready.IN1 +src_ready => sink8_ready.IN1 +src_ready => sink9_ready.IN1 +src_ready => sink10_ready.IN1 +src_ready => sink11_ready.IN1 +src_ready => sink12_ready.IN1 +src_ready => sink13_ready.IN1 +src_ready => sink14_ready.IN1 +src_ready => sink15_ready.IN1 +src_ready => sink16_ready.IN1 +src_ready => sink17_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +request[0] => grant[0].DATAIN +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant[1].DATAIN +request[1] => _.IN1 +request[1] => _.IN1 +request[2] => grant[2].DATAIN +request[2] => _.IN1 +request[2] => _.IN1 +request[3] => grant[3].DATAIN +request[3] => _.IN1 +request[3] => _.IN1 +request[4] => grant[4].DATAIN +request[4] => _.IN1 +request[4] => _.IN1 +request[5] => grant[5].DATAIN +request[5] => _.IN1 +request[5] => _.IN1 +request[6] => grant[6].DATAIN +request[6] => _.IN1 +request[6] => _.IN1 +request[7] => grant[7].DATAIN +request[7] => _.IN1 +request[7] => _.IN1 +request[8] => grant[8].DATAIN +request[8] => _.IN1 +request[8] => _.IN1 +request[9] => grant[9].DATAIN +request[9] => _.IN1 +request[9] => _.IN1 +request[10] => grant[10].DATAIN +request[10] => _.IN1 +request[10] => _.IN1 +request[11] => grant[11].DATAIN +request[11] => _.IN1 +request[11] => _.IN1 +request[12] => grant[12].DATAIN +request[12] => _.IN1 +request[12] => _.IN1 +request[13] => grant[13].DATAIN +request[13] => _.IN1 +request[13] => _.IN1 +request[14] => grant[14].DATAIN +request[14] => _.IN1 +request[14] => _.IN1 +request[15] => grant[15].DATAIN +request[15] => _.IN1 +request[15] => _.IN1 +request[16] => grant[16].DATAIN +request[16] => _.IN1 +request[16] => _.IN1 +request[17] => grant[17].DATAIN +request[17] => _.IN1 +request[17] => _.IN1 +grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE +grant[2] <= request[2].DB_MAX_OUTPUT_PORT_TYPE +grant[3] <= request[3].DB_MAX_OUTPUT_PORT_TYPE +grant[4] <= request[4].DB_MAX_OUTPUT_PORT_TYPE +grant[5] <= request[5].DB_MAX_OUTPUT_PORT_TYPE +grant[6] <= request[6].DB_MAX_OUTPUT_PORT_TYPE +grant[7] <= request[7].DB_MAX_OUTPUT_PORT_TYPE +grant[8] <= request[8].DB_MAX_OUTPUT_PORT_TYPE +grant[9] <= request[9].DB_MAX_OUTPUT_PORT_TYPE +grant[10] <= request[10].DB_MAX_OUTPUT_PORT_TYPE +grant[11] <= request[11].DB_MAX_OUTPUT_PORT_TYPE +grant[12] <= request[12].DB_MAX_OUTPUT_PORT_TYPE +grant[13] <= request[13].DB_MAX_OUTPUT_PORT_TYPE +grant[14] <= request[14].DB_MAX_OUTPUT_PORT_TYPE +grant[15] <= request[15].DB_MAX_OUTPUT_PORT_TYPE +grant[16] <= request[16].DB_MAX_OUTPUT_PORT_TYPE +grant[17] <= request[17].DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => ~NO_FANOUT~ +save_top_priority => ~NO_FANOUT~ + + +|lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => Add0.IN36 +a[1] => Add0.IN35 +a[2] => Add0.IN34 +a[3] => Add0.IN33 +a[4] => Add0.IN32 +a[5] => Add0.IN31 +a[6] => Add0.IN30 +a[7] => Add0.IN29 +a[8] => Add0.IN28 +a[9] => Add0.IN27 +a[10] => Add0.IN26 +a[11] => Add0.IN25 +a[12] => Add0.IN24 +a[13] => Add0.IN23 +a[14] => Add0.IN22 +a[15] => Add0.IN21 +a[16] => Add0.IN20 +a[17] => Add0.IN19 +a[18] => Add0.IN18 +a[19] => Add0.IN17 +a[20] => Add0.IN16 +a[21] => Add0.IN15 +a[22] => Add0.IN14 +a[23] => Add0.IN13 +a[24] => Add0.IN12 +a[25] => Add0.IN11 +a[26] => Add0.IN10 +a[27] => Add0.IN9 +a[28] => Add0.IN8 +a[29] => Add0.IN7 +a[30] => Add0.IN6 +a[31] => Add0.IN5 +a[32] => Add0.IN4 +a[33] => Add0.IN3 +a[34] => Add0.IN2 +a[35] => Add0.IN1 +b[0] => Add0.IN72 +b[1] => Add0.IN71 +b[2] => Add0.IN70 +b[3] => Add0.IN69 +b[4] => Add0.IN68 +b[5] => Add0.IN67 +b[6] => Add0.IN66 +b[7] => Add0.IN65 +b[8] => Add0.IN64 +b[9] => Add0.IN63 +b[10] => Add0.IN62 +b[11] => Add0.IN61 +b[12] => Add0.IN60 +b[13] => Add0.IN59 +b[14] => Add0.IN58 +b[15] => Add0.IN57 +b[16] => Add0.IN56 +b[17] => Add0.IN55 +b[18] => Add0.IN54 +b[19] => Add0.IN53 +b[20] => Add0.IN52 +b[21] => Add0.IN51 +b[22] => Add0.IN50 +b[23] => Add0.IN49 +b[24] => Add0.IN48 +b[25] => Add0.IN47 +b[26] => Add0.IN46 +b[27] => Add0.IN45 +b[28] => Add0.IN44 +b[29] => Add0.IN43 +b[30] => Add0.IN42 +b[31] => Add0.IN41 +b[32] => Add0.IN40 +b[33] => Add0.IN39 +b[34] => Add0.IN38 +b[35] => Add0.IN37 +sum[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[32] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[33] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[34] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[35] <= Add0.DB_MAX_OUTPUT_PORT_TYPE + + +|lights|nios_system:NiosII|nios_system_irq_mapper:irq_mapper +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +receiver0_irq => sender_irq[5].DATAIN +sender_irq[0] <= +sender_irq[1] <= +sender_irq[2] <= +sender_irq[3] <= +sender_irq[4] <= +sender_irq[5] <= receiver0_irq.DB_MAX_OUTPUT_PORT_TYPE +sender_irq[6] <= +sender_irq[7] <= +sender_irq[8] <= +sender_irq[9] <= +sender_irq[10] <= +sender_irq[11] <= +sender_irq[12] <= +sender_irq[13] <= +sender_irq[14] <= +sender_irq[15] <= +sender_irq[16] <= +sender_irq[17] <= +sender_irq[18] <= +sender_irq[19] <= +sender_irq[20] <= +sender_irq[21] <= +sender_irq[22] <= +sender_irq[23] <= +sender_irq[24] <= +sender_irq[25] <= +sender_irq[26] <= +sender_irq[27] <= +sender_irq[28] <= +sender_irq[29] <= +sender_irq[30] <= +sender_irq[31] <= + + diff --git a/db/lights.hif b/db/lights.hif index 93920d6..15bfca1 100644 --- a/db/lights.hif +++ b/db/lights.hif Binary files differ diff --git a/db/lights.lpc.html b/db/lights.lpc.html index ddac326..2d33dba 100644 --- a/db/lights.lpc.html +++ b/db/lights.lpc.html @@ -1,3506 +1,3506 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
NiosII|irq_mapper3312313231313100000
NiosII|rsp_xbar_mux_001|arb|adder72360363636363600000
NiosII|rsp_xbar_mux_001|arb220401800000000
NiosII|rsp_xbar_mux_001210900013500000000
NiosII|rsp_xbar_mux|arb|adder8404444400000
NiosII|rsp_xbar_mux|arb6040200000000
NiosII|rsp_xbar_mux23700011900000000
NiosII|rsp_xbar_demux_01712012111811100000
NiosII|rsp_xbar_demux_01612012111811100000
NiosII|rsp_xbar_demux_01512012111811100000
NiosII|rsp_xbar_demux_01412012111811100000
NiosII|rsp_xbar_demux_01312012111811100000
NiosII|rsp_xbar_demux_01212012111811100000
NiosII|rsp_xbar_demux_01112012111811100000
NiosII|rsp_xbar_demux_01012012111811100000
NiosII|rsp_xbar_demux_00912012111811100000
NiosII|rsp_xbar_demux_00812012111811100000
NiosII|rsp_xbar_demux_00712012111811100000
NiosII|rsp_xbar_demux_00612012111811100000
NiosII|rsp_xbar_demux_00512012111811100000
NiosII|rsp_xbar_demux_00412012111811100000
NiosII|rsp_xbar_demux_00312012111811100000
NiosII|rsp_xbar_demux_00212012111811100000
NiosII|rsp_xbar_demux_00112142423544400000
NiosII|rsp_xbar_demux12142423544400000
NiosII|cmd_xbar_mux_001|arb|adder8202422200000
NiosII|cmd_xbar_mux_001|arb6010200000000
NiosII|cmd_xbar_mux_00123700011900000000
NiosII|cmd_xbar_mux|arb|adder8202422200000
NiosII|cmd_xbar_mux|arb6010200000000
NiosII|cmd_xbar_mux23700011900000000
NiosII|cmd_xbar_demux_0011373242324210732432432400000
NiosII|cmd_xbar_demux12142423544400000
NiosII|rst_controller|alt_rst_sync_uq12000100000000
NiosII|rst_controller1714014214141400000
NiosII|id_router_017|the_default_decode0230232323232300000
NiosII|id_router_01710202011800000000
NiosII|id_router_016|the_default_decode0230232323232300000
NiosII|id_router_01610202011800000000
NiosII|id_router_015|the_default_decode0230232323232300000
NiosII|id_router_01510202011800000000
NiosII|id_router_014|the_default_decode0230232323232300000
NiosII|id_router_01410202011800000000
NiosII|id_router_013|the_default_decode0230232323232300000
NiosII|id_router_01310202011800000000
NiosII|id_router_012|the_default_decode0230232323232300000
NiosII|id_router_01210202011800000000
NiosII|id_router_011|the_default_decode0230232323232300000
NiosII|id_router_01110202011800000000
NiosII|id_router_010|the_default_decode0230232323232300000
NiosII|id_router_01010202011800000000
NiosII|id_router_009|the_default_decode0230232323232300000
NiosII|id_router_00910202011800000000
NiosII|id_router_008|the_default_decode0230232323232300000
NiosII|id_router_00810202011800000000
NiosII|id_router_007|the_default_decode0230232323232300000
NiosII|id_router_00710202011800000000
NiosII|id_router_006|the_default_decode0230232323232300000
NiosII|id_router_00610202011800000000
NiosII|id_router_005|the_default_decode0230232323232300000
NiosII|id_router_00510202011800000000
NiosII|id_router_004|the_default_decode0230232323232300000
NiosII|id_router_00410202011800000000
NiosII|id_router_003|the_default_decode0230232323232300000
NiosII|id_router_00310202011800000000
NiosII|id_router_002|the_default_decode0230232323232300000
NiosII|id_router_00210202011800000000
NiosII|id_router_001|the_default_decode0230232323232300000
NiosII|id_router_00110202011800000000
NiosII|id_router|the_default_decode0230232323232300000
NiosII|id_router10202011800000000
NiosII|addr_router_001|the_default_decode0230232323232300000
NiosII|addr_router_00110207011800000000
NiosII|addr_router|the_default_decode0230232323232300000
NiosII|addr_router10207011800000000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|nios2_processor_data_master_translator_avalon_universal_master_0_agent18339853913439393900000
NiosII|nios2_processor_instruction_master_translator_avalon_universal_master_0_agent18339853913439393900000
NiosII|lcd_blon_s1_translator10372077077700000
NiosII|lcd_on_s1_translator10372077077700000
NiosII|lcd_16207_0_control_slave_translator793144314731313100000
NiosII|hex7_s1_translator10372077077700000
NiosII|hex6_s1_translator10372077077700000
NiosII|hex5_s1_translator10372077077700000
NiosII|hex4_s1_translator10372077077700000
NiosII|hex3_s1_translator10372077077700000
NiosII|hex2_s1_translator10372077077700000
NiosII|hex1_s1_translator10372077077700000
NiosII|hex0_s1_translator10372077077700000
NiosII|push_switches_s1_translator10372073677700000
NiosII|switches_s1_translator10372073677700000
NiosII|ledrs_s1_translator10372077077700000
NiosII|jtag_uart_avalon_jtag_slave_translator10362167066600000
NiosII|leds_s1_translator10372077077700000
NiosII|onchip_memory_s1_translator1038388988800000
NiosII|nios2_processor_jtag_debug_module_translator10361068266600000
NiosII|nios2_processor_data_master_translator104130139513131300000
NiosII|nios2_processor_instruction_master_translator104520529552525200000
NiosII|lcd_blon383131313331313100000
NiosII|lcd_on383131313331313100000
NiosII|lcd_16207_0150301100080000
NiosII|hex7382525253925252500000
NiosII|hex6382525253925252500000
NiosII|hex5382525253925252500000
NiosII|hex4382525253925252500000
NiosII|hex3382525253925252500000
NiosII|hex2382525253925252500000
NiosII|hex1382525253925252500000
NiosII|hex0382525253925252500000
NiosII|push_switches70003200000000
NiosII|switches220003200000000
NiosII|ledrs381414145014141400000
NiosII|leds382424244024242400000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram24000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state5000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo130001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated120001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r130101600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram24000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state5000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo130001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated120001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w120001600000000
NiosII|jtag_uart381023103410101000000
NiosII|onchip_memory|the_altsyncram|auto_generated|mux22270003200000000
NiosII|onchip_memory|the_altsyncram|auto_generated|decode34000700000000
NiosII|onchip_memory|the_altsyncram|auto_generated550003200000000
NiosII|onchip_memory580103200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_sysclk430005100000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_tck1300104300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper1230005300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_im973693364836363600000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_pib392038201920202000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|the_nios_system_nios2_processor_oci_test_bench360360000000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount5000500000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp4202422200000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count3000200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo15106503600000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode9060400000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace10409307200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_itrace251723178717171700000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dbrk890009300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_xbrk555525655500000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_break52366367136363600000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_avalon_reg4802806800000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram|the_altsyncram|auto_generated460003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram460003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem910606500000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_debug501301711100000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci1590006900000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b|the_altsyncram|auto_generated440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a|the_altsyncram|auto_generated440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a440003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_test_bench275323833433300000
NiosII|nios2_processor148031011200000000
NiosII230008700080008
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
NiosII|irq_mapper3312313231313100000
NiosII|rsp_xbar_mux_001|arb|adder72360363636363600000
NiosII|rsp_xbar_mux_001|arb220401800000000
NiosII|rsp_xbar_mux_001210900013500000000
NiosII|rsp_xbar_mux|arb|adder8404444400000
NiosII|rsp_xbar_mux|arb6040200000000
NiosII|rsp_xbar_mux23700011900000000
NiosII|rsp_xbar_demux_01712012111811100000
NiosII|rsp_xbar_demux_01612012111811100000
NiosII|rsp_xbar_demux_01512012111811100000
NiosII|rsp_xbar_demux_01412012111811100000
NiosII|rsp_xbar_demux_01312012111811100000
NiosII|rsp_xbar_demux_01212012111811100000
NiosII|rsp_xbar_demux_01112012111811100000
NiosII|rsp_xbar_demux_01012012111811100000
NiosII|rsp_xbar_demux_00912012111811100000
NiosII|rsp_xbar_demux_00812012111811100000
NiosII|rsp_xbar_demux_00712012111811100000
NiosII|rsp_xbar_demux_00612012111811100000
NiosII|rsp_xbar_demux_00512012111811100000
NiosII|rsp_xbar_demux_00412012111811100000
NiosII|rsp_xbar_demux_00312012111811100000
NiosII|rsp_xbar_demux_00212012111811100000
NiosII|rsp_xbar_demux_00112142423544400000
NiosII|rsp_xbar_demux12142423544400000
NiosII|cmd_xbar_mux_001|arb|adder8202422200000
NiosII|cmd_xbar_mux_001|arb6010200000000
NiosII|cmd_xbar_mux_00123700011900000000
NiosII|cmd_xbar_mux|arb|adder8202422200000
NiosII|cmd_xbar_mux|arb6010200000000
NiosII|cmd_xbar_mux23700011900000000
NiosII|cmd_xbar_demux_0011373242324210732432432400000
NiosII|cmd_xbar_demux12142423544400000
NiosII|rst_controller|alt_rst_sync_uq12000100000000
NiosII|rst_controller1714014214141400000
NiosII|id_router_017|the_default_decode0230232323232300000
NiosII|id_router_01710202011800000000
NiosII|id_router_016|the_default_decode0230232323232300000
NiosII|id_router_01610202011800000000
NiosII|id_router_015|the_default_decode0230232323232300000
NiosII|id_router_01510202011800000000
NiosII|id_router_014|the_default_decode0230232323232300000
NiosII|id_router_01410202011800000000
NiosII|id_router_013|the_default_decode0230232323232300000
NiosII|id_router_01310202011800000000
NiosII|id_router_012|the_default_decode0230232323232300000
NiosII|id_router_01210202011800000000
NiosII|id_router_011|the_default_decode0230232323232300000
NiosII|id_router_01110202011800000000
NiosII|id_router_010|the_default_decode0230232323232300000
NiosII|id_router_01010202011800000000
NiosII|id_router_009|the_default_decode0230232323232300000
NiosII|id_router_00910202011800000000
NiosII|id_router_008|the_default_decode0230232323232300000
NiosII|id_router_00810202011800000000
NiosII|id_router_007|the_default_decode0230232323232300000
NiosII|id_router_00710202011800000000
NiosII|id_router_006|the_default_decode0230232323232300000
NiosII|id_router_00610202011800000000
NiosII|id_router_005|the_default_decode0230232323232300000
NiosII|id_router_00510202011800000000
NiosII|id_router_004|the_default_decode0230232323232300000
NiosII|id_router_00410202011800000000
NiosII|id_router_003|the_default_decode0230232323232300000
NiosII|id_router_00310202011800000000
NiosII|id_router_002|the_default_decode0230232323232300000
NiosII|id_router_00210202011800000000
NiosII|id_router_001|the_default_decode0230232323232300000
NiosII|id_router_00110202011800000000
NiosII|id_router|the_default_decode0230232323232300000
NiosII|id_router10202011800000000
NiosII|addr_router_001|the_default_decode0230232323232300000
NiosII|addr_router_00110207011800000000
NiosII|addr_router|the_default_decode0230232323232300000
NiosII|addr_router10207011800000000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex7_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex6_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex5_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex4_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex3_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex2_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex1_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|hex0_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|switches_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|leds_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo1423903910139393900000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor351013311100000
NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent29439553929939393900000
NiosII|nios2_processor_data_master_translator_avalon_universal_master_0_agent18339853913439393900000
NiosII|nios2_processor_instruction_master_translator_avalon_universal_master_0_agent18339853913439393900000
NiosII|lcd_blon_s1_translator10372077077700000
NiosII|lcd_on_s1_translator10372077077700000
NiosII|lcd_16207_0_control_slave_translator793144314731313100000
NiosII|hex7_s1_translator10372077077700000
NiosII|hex6_s1_translator10372077077700000
NiosII|hex5_s1_translator10372077077700000
NiosII|hex4_s1_translator10372077077700000
NiosII|hex3_s1_translator10372077077700000
NiosII|hex2_s1_translator10372077077700000
NiosII|hex1_s1_translator10372077077700000
NiosII|hex0_s1_translator10372077077700000
NiosII|push_switches_s1_translator10372073677700000
NiosII|switches_s1_translator10372073677700000
NiosII|ledrs_s1_translator10372077077700000
NiosII|jtag_uart_avalon_jtag_slave_translator10362167066600000
NiosII|leds_s1_translator10372077077700000
NiosII|onchip_memory_s1_translator1038388988800000
NiosII|nios2_processor_jtag_debug_module_translator10361068266600000
NiosII|nios2_processor_data_master_translator104130139513131300000
NiosII|nios2_processor_instruction_master_translator104520529552525200000
NiosII|lcd_blon383131313331313100000
NiosII|lcd_on383131313331313100000
NiosII|lcd_16207_0150301100080000
NiosII|hex7382525253925252500000
NiosII|hex6382525253925252500000
NiosII|hex5382525253925252500000
NiosII|hex4382525253925252500000
NiosII|hex3382525253925252500000
NiosII|hex2382525253925252500000
NiosII|hex1382525253925252500000
NiosII|hex0382525253925252500000
NiosII|push_switches70003200000000
NiosII|switches220003200000000
NiosII|ledrs381414145014141400000
NiosII|leds382424244024242400000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram24000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state5000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo130001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated120001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r130101600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram24000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state5000800000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo130001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated120001600000000
NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w120001600000000
NiosII|jtag_uart381023103410101000000
NiosII|onchip_memory|the_altsyncram|auto_generated|mux22270003200000000
NiosII|onchip_memory|the_altsyncram|auto_generated|decode34000700000000
NiosII|onchip_memory|the_altsyncram|auto_generated550003200000000
NiosII|onchip_memory580103200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_sysclk430005100000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_tck1300104300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper1230005300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_im973693364836363600000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_pib392038201920202000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|the_nios_system_nios2_processor_oci_test_bench360360000000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount5000500000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp4202422200000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count3000200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo15106503600000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode9060400000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace10409307200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_itrace251723178717171700000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dbrk890009300000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_xbrk555525655500000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_break52366367136363600000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_avalon_reg4802806800000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram|the_altsyncram|auto_generated460003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram460003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem910606500000000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_debug501301711100000
NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci1590006900000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b|the_altsyncram|auto_generated440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a|the_altsyncram|auto_generated440003200000000
NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a440003200000000
NiosII|nios2_processor|the_nios_system_nios2_processor_test_bench275323833433300000
NiosII|nios2_processor148031011200000000
NiosII230008700080008
diff --git a/db/lights.lpc.txt b/db/lights.lpc.txt index 1be8c1f..751930a 100644 --- a/db/lights.lpc.txt +++ b/db/lights.lpc.txt @@ -1,224 +1,224 @@ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Legal Partition Candidates ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; NiosII|irq_mapper ; 3 ; 31 ; 2 ; 31 ; 32 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux_001|arb|adder ; 72 ; 36 ; 0 ; 36 ; 36 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux_001|arb ; 22 ; 0 ; 4 ; 0 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux_001 ; 2109 ; 0 ; 0 ; 0 ; 135 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux|arb|adder ; 8 ; 4 ; 0 ; 4 ; 4 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux|arb ; 6 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_mux ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_017 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_016 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_015 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_014 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_013 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_012 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_011 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_010 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_009 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_008 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_007 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_006 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_005 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_004 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_003 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_002 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux_001 ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rsp_xbar_demux ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux_001|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux_001|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux_001 ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_mux ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_demux_001 ; 137 ; 324 ; 2 ; 324 ; 2107 ; 324 ; 324 ; 324 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|cmd_xbar_demux ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rst_controller|alt_rst_sync_uq1 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|rst_controller ; 17 ; 14 ; 0 ; 14 ; 2 ; 14 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_017|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_017 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_016|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_016 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_015|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_015 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_014|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_014 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_013|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_013 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_012|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_012 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_011|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_011 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_010|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_010 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_009|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_009 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_008|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_008 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_007|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_007 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_006|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_006 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_005|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_005 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_004|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_004 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_003|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_003 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_002|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_002 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_001|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router_001 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|id_router ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router_001|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router_001 ; 102 ; 0 ; 7 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|addr_router ; 102 ; 0 ; 7 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_data_master_translator_avalon_universal_master_0_agent ; 183 ; 39 ; 85 ; 39 ; 134 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; 183 ; 39 ; 85 ; 39 ; 134 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0_control_slave_translator ; 79 ; 31 ; 44 ; 31 ; 47 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches_s1_translator ; 103 ; 7 ; 20 ; 7 ; 36 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches_s1_translator ; 103 ; 7 ; 20 ; 7 ; 36 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart_avalon_jtag_slave_translator ; 103 ; 6 ; 21 ; 6 ; 70 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory_s1_translator ; 103 ; 8 ; 3 ; 8 ; 89 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_jtag_debug_module_translator ; 103 ; 6 ; 10 ; 6 ; 82 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_data_master_translator ; 104 ; 13 ; 0 ; 13 ; 95 ; 13 ; 13 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor_instruction_master_translator ; 104 ; 52 ; 0 ; 52 ; 95 ; 52 ; 52 ; 52 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_blon ; 38 ; 31 ; 31 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_on ; 38 ; 31 ; 31 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|lcd_16207_0 ; 15 ; 0 ; 3 ; 0 ; 11 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex7 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex6 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex5 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex4 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex3 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex2 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex1 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|hex0 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|push_switches ; 7 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|switches ; 22 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|ledrs ; 38 ; 14 ; 14 ; 14 ; 50 ; 14 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|leds ; 38 ; 24 ; 24 ; 24 ; 40 ; 24 ; 24 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r ; 13 ; 0 ; 1 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|jtag_uart ; 38 ; 10 ; 23 ; 10 ; 34 ; 10 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory|the_altsyncram|auto_generated|mux2 ; 227 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory|the_altsyncram|auto_generated|decode3 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory|the_altsyncram|auto_generated ; 55 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|onchip_memory ; 58 ; 0 ; 1 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_sysclk ; 43 ; 0 ; 0 ; 0 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_tck ; 130 ; 0 ; 1 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper ; 123 ; 0 ; 0 ; 0 ; 53 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_im ; 97 ; 36 ; 93 ; 36 ; 48 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_pib ; 39 ; 20 ; 38 ; 20 ; 19 ; 20 ; 20 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|the_nios_system_nios2_processor_oci_test_bench ; 36 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount ; 5 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp ; 4 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo ; 151 ; 0 ; 65 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode ; 9 ; 0 ; 6 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace ; 104 ; 0 ; 93 ; 0 ; 72 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_itrace ; 25 ; 17 ; 23 ; 17 ; 87 ; 17 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dbrk ; 89 ; 0 ; 0 ; 0 ; 93 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_xbrk ; 55 ; 5 ; 52 ; 5 ; 6 ; 5 ; 5 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_break ; 52 ; 36 ; 6 ; 36 ; 71 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_avalon_reg ; 48 ; 0 ; 28 ; 0 ; 68 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram|the_altsyncram|auto_generated ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem ; 91 ; 0 ; 6 ; 0 ; 65 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_debug ; 50 ; 1 ; 30 ; 1 ; 7 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci ; 159 ; 0 ; 0 ; 0 ; 69 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b|the_altsyncram|auto_generated ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a|the_altsyncram|auto_generated ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor|the_nios_system_nios2_processor_test_bench ; 275 ; 3 ; 238 ; 3 ; 34 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII|nios2_processor ; 148 ; 0 ; 31 ; 0 ; 112 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; NiosII ; 23 ; 0 ; 0 ; 0 ; 87 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 8 ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; NiosII|irq_mapper ; 3 ; 31 ; 2 ; 31 ; 32 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_mux_001|arb|adder ; 72 ; 36 ; 0 ; 36 ; 36 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_mux_001|arb ; 22 ; 0 ; 4 ; 0 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_mux_001 ; 2109 ; 0 ; 0 ; 0 ; 135 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_mux|arb|adder ; 8 ; 4 ; 0 ; 4 ; 4 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_mux|arb ; 6 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_mux ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_017 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_016 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_015 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_014 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_013 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_012 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_011 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_010 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_009 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_008 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_007 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_006 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_005 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_004 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_003 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_002 ; 120 ; 1 ; 2 ; 1 ; 118 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux_001 ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rsp_xbar_demux ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_mux_001|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_mux_001|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_mux_001 ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_mux|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_mux|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_mux ; 237 ; 0 ; 0 ; 0 ; 119 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_demux_001 ; 137 ; 324 ; 2 ; 324 ; 2107 ; 324 ; 324 ; 324 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|cmd_xbar_demux ; 121 ; 4 ; 2 ; 4 ; 235 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rst_controller|alt_rst_sync_uq1 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|rst_controller ; 17 ; 14 ; 0 ; 14 ; 2 ; 14 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_017|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_017 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_016|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_016 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_015|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_015 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_014|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_014 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_013|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_013 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_012|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_012 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_011|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_011 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_010|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_010 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_009|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_009 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_008|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_008 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_007|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_007 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_006|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_006 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_005|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_005 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_004|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_004 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_003|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_003 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_002|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_002 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_001|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router_001 ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|id_router ; 102 ; 0 ; 2 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|addr_router_001|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|addr_router_001 ; 102 ; 0 ; 7 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|addr_router|the_default_decode ; 0 ; 23 ; 0 ; 23 ; 23 ; 23 ; 23 ; 23 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|addr_router ; 102 ; 0 ; 7 ; 0 ; 118 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_blon_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_on_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex7_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex6_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex5_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex4_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex3_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex2_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex1_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex0_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|push_switches_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|switches_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|switches_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|ledrs_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|leds_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|leds_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory_s1_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; 142 ; 39 ; 0 ; 39 ; 101 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor ; 35 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; 294 ; 39 ; 55 ; 39 ; 299 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_data_master_translator_avalon_universal_master_0_agent ; 183 ; 39 ; 85 ; 39 ; 134 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; 183 ; 39 ; 85 ; 39 ; 134 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_blon_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_on_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_16207_0_control_slave_translator ; 79 ; 31 ; 44 ; 31 ; 47 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex7_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex6_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex5_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex4_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex3_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex2_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex1_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex0_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|push_switches_s1_translator ; 103 ; 7 ; 20 ; 7 ; 36 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|switches_s1_translator ; 103 ; 7 ; 20 ; 7 ; 36 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|ledrs_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart_avalon_jtag_slave_translator ; 103 ; 6 ; 21 ; 6 ; 70 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|leds_s1_translator ; 103 ; 7 ; 20 ; 7 ; 70 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory_s1_translator ; 103 ; 8 ; 3 ; 8 ; 89 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_jtag_debug_module_translator ; 103 ; 6 ; 10 ; 6 ; 82 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_data_master_translator ; 104 ; 13 ; 0 ; 13 ; 95 ; 13 ; 13 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor_instruction_master_translator ; 104 ; 52 ; 0 ; 52 ; 95 ; 52 ; 52 ; 52 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_blon ; 38 ; 31 ; 31 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_on ; 38 ; 31 ; 31 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|lcd_16207_0 ; 15 ; 0 ; 3 ; 0 ; 11 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex7 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex6 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex5 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex4 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex3 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex2 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex1 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|hex0 ; 38 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|push_switches ; 7 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|switches ; 22 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|ledrs ; 38 ; 14 ; 14 ; 14 ; 50 ; 14 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|leds ; 38 ; 24 ; 24 ; 24 ; 40 ; 24 ; 24 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r|rfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_r ; 13 ; 0 ; 1 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w|wfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart|the_nios_system_jtag_uart_scfifo_w ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|jtag_uart ; 38 ; 10 ; 23 ; 10 ; 34 ; 10 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory|the_altsyncram|auto_generated|mux2 ; 227 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory|the_altsyncram|auto_generated|decode3 ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory|the_altsyncram|auto_generated ; 55 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|onchip_memory ; 58 ; 0 ; 1 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_sysclk ; 43 ; 0 ; 0 ; 0 ; 51 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper|the_nios_system_nios2_processor_jtag_debug_module_tck ; 130 ; 0 ; 1 ; 0 ; 43 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_jtag_debug_module_wrapper ; 123 ; 0 ; 0 ; 0 ; 53 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_im ; 97 ; 36 ; 93 ; 36 ; 48 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_pib ; 39 ; 20 ; 38 ; 20 ; 19 ; 20 ; 20 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|the_nios_system_nios2_processor_oci_test_bench ; 36 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount ; 5 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp ; 4 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_fifo ; 151 ; 0 ; 65 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode ; 9 ; 0 ; 6 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dtrace ; 104 ; 0 ; 93 ; 0 ; 72 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_itrace ; 25 ; 17 ; 23 ; 17 ; 87 ; 17 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_dbrk ; 89 ; 0 ; 0 ; 0 ; 93 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_xbrk ; 55 ; 5 ; 52 ; 5 ; 6 ; 5 ; 5 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_break ; 52 ; 36 ; 6 ; 36 ; 71 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_avalon_reg ; 48 ; 0 ; 28 ; 0 ; 68 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram|the_altsyncram|auto_generated ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram ; 46 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_ocimem ; 91 ; 0 ; 6 ; 0 ; 65 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci|the_nios_system_nios2_processor_nios2_oci_debug ; 50 ; 1 ; 30 ; 1 ; 7 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_nios2_oci ; 159 ; 0 ; 0 ; 0 ; 69 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b|the_altsyncram|auto_generated ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_b ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a|the_altsyncram|auto_generated ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|nios_system_nios2_processor_register_bank_a ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor|the_nios_system_nios2_processor_test_bench ; 275 ; 3 ; 238 ; 3 ; 34 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII|nios2_processor ; 148 ; 0 ; 31 ; 0 ; 112 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; NiosII ; 23 ; 0 ; 0 ; 0 ; 87 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 8 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/db/lights.map.bpm b/db/lights.map.bpm index 4e5519a..47b5b67 100644 --- a/db/lights.map.bpm +++ b/db/lights.map.bpm Binary files differ diff --git a/db/lights.map.cdb b/db/lights.map.cdb index 03469df..7a6133a 100644 --- a/db/lights.map.cdb +++ b/db/lights.map.cdb Binary files differ diff --git a/db/lights.map.hdb b/db/lights.map.hdb index 1aa3208..5e9211f 100644 --- a/db/lights.map.hdb +++ b/db/lights.map.hdb Binary files differ diff --git a/db/lights.map.kpt b/db/lights.map.kpt index 0feb822..141e6b7 100644 --- a/db/lights.map.kpt +++ b/db/lights.map.kpt Binary files differ diff --git a/db/lights.map.logdb b/db/lights.map.logdb index 626799f..d45424f 100644 --- a/db/lights.map.logdb +++ b/db/lights.map.logdb @@ -1 +1 @@ -v1 +v1 diff --git a/db/lights.map.qmsg b/db/lights.map.qmsg index 95267eb..48de8e6 100644 --- a/db/lights.map.qmsg +++ b/db/lights.map.qmsg @@ -1,458 +1,459 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480609927965 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480609927965 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:32:07 2016 " "Processing started: Fri Dec 02 01:32:07 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480609927965 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480609927965 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lights -c lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480609927965 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480609928324 ""} -{ "Info" "ISGN_START_ELABORATION_QSYS" "nios_system.qsys " "Elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12248 "Elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609928362 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:09 Progress: Loading qsys_tutorial/nios_system.qsys " "2016.12.02.01:32:09 Progress: Loading qsys_tutorial/nios_system.qsys" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609929058 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:09 Progress: Reading input file " "2016.12.02.01:32:09 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609929246 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:09 Progress: Adding clk_0 \[clock_source 13.0\] " "2016.12.02.01:32:09 Progress: Adding clk_0 \[clock_source 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609929286 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:09 Progress: Parameterizing module clk_0 " "2016.12.02.01:32:09 Progress: Parameterizing module clk_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609929448 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:09 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\] " "2016.12.02.01:32:09 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609929451 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module nios2_processor " "2016.12.02.01:32:10 Progress: Parameterizing module nios2_processor" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930144 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930147 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module onchip_memory " "2016.12.02.01:32:10 Progress: Parameterizing module onchip_memory" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930213 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930214 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module jtag_uart " "2016.12.02.01:32:10 Progress: Parameterizing module jtag_uart" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930251 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930252 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module LEDs " "2016.12.02.01:32:10 Progress: Parameterizing module LEDs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930296 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930296 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module LEDRs " "2016.12.02.01:32:10 Progress: Parameterizing module LEDRs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930300 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930301 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module switches " "2016.12.02.01:32:10 Progress: Parameterizing module switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930302 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930303 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module push_switches " "2016.12.02.01:32:10 Progress: Parameterizing module push_switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930304 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930304 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex0 " "2016.12.02.01:32:10 Progress: Parameterizing module hex0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930307 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930307 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex1 " "2016.12.02.01:32:10 Progress: Parameterizing module hex1" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930309 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930309 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex2 " "2016.12.02.01:32:10 Progress: Parameterizing module hex2" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930310 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930311 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex3 " "2016.12.02.01:32:10 Progress: Parameterizing module hex3" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930313 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930313 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex4 " "2016.12.02.01:32:10 Progress: Parameterizing module hex4" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930314 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930315 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex5 " "2016.12.02.01:32:10 Progress: Parameterizing module hex5" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930317 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930318 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex6 " "2016.12.02.01:32:10 Progress: Parameterizing module hex6" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930319 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930320 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module hex7 " "2016.12.02.01:32:10 Progress: Parameterizing module hex7" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930321 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930321 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module lcd_16207_0 " "2016.12.02.01:32:10 Progress: Parameterizing module lcd_16207_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930341 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930341 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module lcd_on " "2016.12.02.01:32:10 Progress: Parameterizing module lcd_on" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930344 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.02.01:32:10 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930344 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing module lcd_blon " "2016.12.02.01:32:10 Progress: Parameterizing module lcd_blon" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930345 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Building connections " "2016.12.02.01:32:10 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930346 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Parameterizing connections " "2016.12.02.01:32:10 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930655 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:10 Progress: Validating " "2016.12.02.01:32:10 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609930658 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.02.01:32:11 Progress: Done reading input file " "2016.12.02.01:32:11 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609931326 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609931681 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609931681 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH " "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609932637 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections " "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609932866 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "No custom instruction connections, skipping transform " "No custom instruction connections, skipping transform " { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609932873 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_translator_transform: After transform: 39 modules, 155 connections " "Merlin_translator_transform: After transform: 39 modules, 155 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609933446 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_domain_transform: After transform: 78 modules, 423 connections " "Merlin_domain_transform: After transform: 78 modules, 423 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609934450 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_router_transform: After transform: 98 modules, 503 connections " "Merlin_router_transform: After transform: 98 modules, 503 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609934786 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reset_adaptation_transform: After transform: 99 modules, 390 connections " "Reset_adaptation_transform: After transform: 99 modules, 390 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609934856 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections " "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609935100 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_mm_transform: After transform: 138 modules, 470 connections " "Merlin_mm_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609935188 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections " "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609935222 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936159 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936160 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936160 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936160 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936160 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936160 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936161 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936161 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936161 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936161 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936161 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936162 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936162 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936162 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 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rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936173 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936173 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936173 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936173 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936174 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936174 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936174 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936174 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936174 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936174 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936174 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936175 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936175 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936175 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936175 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936175 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936175 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936176 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936176 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936176 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936176 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936176 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936176 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936185 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936185 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936185 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936185 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936186 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936186 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936186 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936186 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936186 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936187 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936187 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936187 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936187 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936187 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936188 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936188 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936188 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936188 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936188 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936188 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936189 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936189 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936189 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936189 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936190 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936190 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936190 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936191 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936191 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936191 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936191 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936192 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936193 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936193 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936193 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936193 ""} -{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936194 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936632 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \] " "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609936634 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) Starting Nios II generation " "Nios2_processor: # 2016.12.02 01:32:17 (*) Starting Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940786 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) Checking for plaintext license. " "Nios2_processor: # 2016.12.02 01:32:17 (*) Checking for plaintext license." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940786 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus " "Nios2_processor: # 2016.12.02 01:32:17 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940786 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) Defaulting to contents of LM_LICENSE_FILE environment variable " "Nios2_processor: # 2016.12.02 01:32:17 (*) Defaulting to contents of LM_LICENSE_FILE environment variable" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940786 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) LM_LICENSE_FILE environment variable is empty " "Nios2_processor: # 2016.12.02 01:32:17 (*) LM_LICENSE_FILE environment variable is empty" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940786 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) Plaintext license not found. " "Nios2_processor: # 2016.12.02 01:32:17 (*) Plaintext license not found." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940786 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) No license required to generate encrypted Nios II/e. " "Nios2_processor: # 2016.12.02 01:32:17 (*) No license required to generate encrypted Nios II/e." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) Elaborating CPU configuration settings " "Nios2_processor: # 2016.12.02 01:32:17 (*) Elaborating CPU configuration settings" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:17 (*) Creating all objects for CPU " "Nios2_processor: # 2016.12.02 01:32:17 (*) Creating all objects for CPU" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:18 (*) Generating RTL from CPU objects " "Nios2_processor: # 2016.12.02 01:32:18 (*) Generating RTL from CPU objects" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:18 (*) Creating plain-text RTL " "Nios2_processor: # 2016.12.02 01:32:18 (*) Creating plain-text RTL" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.02 01:32:20 (*) Done Nios II generation " "Nios2_processor: # 2016.12.02 01:32:20 (*) Done Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940787 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940788 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\" " "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940800 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940841 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \] " "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609940841 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609941877 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\" " "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609941888 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609941907 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \] " "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609941908 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942211 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\" " "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942216 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Starting RTL generation for module 'nios_system_LEDs' " "LEDs: Starting RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942236 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \] " "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942237 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Done RTL generation for module 'nios_system_LEDs' " "LEDs: Done RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942422 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\" " "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942425 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Starting RTL generation for module 'nios_system_LEDRs' " "LEDRs: Starting RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942440 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \] " "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942440 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Done RTL generation for module 'nios_system_LEDRs' " "LEDRs: Done RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942632 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\" " "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942634 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Starting RTL generation for module 'nios_system_switches' " "Switches: Starting RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942646 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \] " "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942647 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Done RTL generation for module 'nios_system_switches' " "Switches: Done RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942825 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\" " "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942827 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Starting RTL generation for module 'nios_system_push_switches' " "Push_switches: Starting RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942840 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \] " "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609942841 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Done RTL generation for module 'nios_system_push_switches' " "Push_switches: Done RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943020 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\" " "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943022 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Starting RTL generation for module 'nios_system_hex0' " "Hex0: Starting RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943038 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \] " "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943038 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Done RTL generation for module 'nios_system_hex0' " "Hex0: Done RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943218 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\" " "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943221 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943233 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \] " "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943233 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943412 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\" " "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943415 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943432 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \] " "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943433 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Done RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Done RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943619 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\" " "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943622 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\" " "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943624 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\" " "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943632 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\" " "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943640 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943648 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943662 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\" " "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943685 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\" " "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943703 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\" " "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943724 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\" " "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943733 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\" " "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943736 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\" " "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943768 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\" " "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943800 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\" " "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943837 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\" " "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943861 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\" " "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943895 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943896 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\" " "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943950 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943951 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\" " "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943973 ""} -{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes " "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1480609943975 ""} -{ "Info" "ISGN_END_ELABORATION_QSYS" "nios_system.qsys " "Finished elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12249 "Finished elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609944821 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lights.vhd 2 1 " "Found 2 design units, including 1 entities, in source file lights.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lights-lights_rtl " "Found design unit 1: lights-lights_rtl" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 27 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945240 ""} { "Info" "ISGN_ENTITY_NAME" "1 lights " "Found entity 1: lights" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945240 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945240 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_system/synthesis/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "nios_system/synthesis/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945261 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945261 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "db/ip/nios_system/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945281 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945286 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945290 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945290 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945294 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945298 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945298 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945302 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945306 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945310 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945310 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945314 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945314 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945317 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945317 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_ledrs.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDRs " "Found entity 1: nios_system_LEDRs" { } { { "db/ip/nios_system/submodules/nios_system_LEDRs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945320 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945320 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDs " "Found entity 1: nios_system_LEDs" { } { { "db/ip/nios_system/submodules/nios_system_LEDs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945323 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945323 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945325 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945326 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_default_decode " "Found entity 1: nios_system_addr_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945326 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router " "Found entity 2: nios_system_addr_router" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945326 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router_001.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945329 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router_001.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945329 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_001_default_decode " "Found entity 1: nios_system_addr_router_001_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945330 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router_001 " "Found entity 2: nios_system_addr_router_001" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945330 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945330 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux " "Found entity 1: nios_system_cmd_xbar_demux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945334 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945334 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux_001 " "Found entity 1: nios_system_cmd_xbar_demux_001" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945337 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945337 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_mux " "Found entity 1: nios_system_cmd_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945340 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945340 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_hex0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_hex0 " "Found entity 1: nios_system_hex0" { } { { "db/ip/nios_system/submodules/nios_system_hex0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945344 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945344 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router.sv(48) " "Verilog HDL Declaration information at nios_system_id_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945346 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router.sv(49) " "Verilog HDL Declaration information at nios_system_id_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945346 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_default_decode " "Found entity 1: nios_system_id_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945347 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router " "Found entity 2: nios_system_id_router" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945347 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945347 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router_002.sv(48) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945350 ""} -{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router_002.sv(49) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1480609945350 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_002_default_decode " "Found entity 1: nios_system_id_router_002_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945351 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router_002 " "Found entity 2: nios_system_id_router_002" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945351 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945351 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_irq_mapper " "Found entity 1: nios_system_irq_mapper" { } { { "db/ip/nios_system/submodules/nios_system_irq_mapper.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945354 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945354 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_jtag_uart.v 5 5 " "Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_jtag_uart_sim_scfifo_w " "Found entity 1: nios_system_jtag_uart_sim_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945358 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_jtag_uart_scfifo_w " "Found entity 2: nios_system_jtag_uart_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945358 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_jtag_uart_sim_scfifo_r " "Found entity 3: nios_system_jtag_uart_sim_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 162 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945358 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_jtag_uart_scfifo_r " "Found entity 4: nios_system_jtag_uart_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 240 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945358 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_jtag_uart " "Found entity 5: nios_system_jtag_uart" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 327 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945358 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_16207_0 " "Found entity 1: nios_system_lcd_16207_0" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945361 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945361 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_on.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_on " "Found entity 1: nios_system_lcd_on" { } { { "db/ip/nios_system/submodules/nios_system_lcd_on.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945364 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor.v 21 21 " "Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_register_bank_a_module " "Found entity 1: nios_system_nios2_processor_register_bank_a_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_nios2_processor_register_bank_b_module " "Found entity 2: nios_system_nios2_processor_register_bank_b_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_nios2_processor_nios2_oci_debug " "Found entity 3: nios_system_nios2_processor_nios2_oci_debug" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_nios2_processor_ociram_sp_ram_module " "Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 288 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_nios2_processor_nios2_ocimem " "Found entity 5: nios_system_nios2_processor_nios2_ocimem" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 346 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "6 nios_system_nios2_processor_nios2_avalon_reg " "Found entity 6: nios_system_nios2_processor_nios2_avalon_reg" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 524 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "7 nios_system_nios2_processor_nios2_oci_break " "Found entity 7: nios_system_nios2_processor_nios2_oci_break" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 616 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "8 nios_system_nios2_processor_nios2_oci_xbrk " "Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 910 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "9 nios_system_nios2_processor_nios2_oci_dbrk " "Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1116 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "10 nios_system_nios2_processor_nios2_oci_itrace " "Found entity 10: nios_system_nios2_processor_nios2_oci_itrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1302 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "11 nios_system_nios2_processor_nios2_oci_td_mode " "Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1599 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "12 nios_system_nios2_processor_nios2_oci_dtrace " "Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "13 nios_system_nios2_processor_nios2_oci_compute_tm_count " "Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1760 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "14 nios_system_nios2_processor_nios2_oci_fifowp_inc " "Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1831 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "15 nios_system_nios2_processor_nios2_oci_fifocount_inc " "Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1873 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "16 nios_system_nios2_processor_nios2_oci_fifo " "Found entity 16: nios_system_nios2_processor_nios2_oci_fifo" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1919 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "17 nios_system_nios2_processor_nios2_oci_pib " "Found entity 17: nios_system_nios2_processor_nios2_oci_pib" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2424 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "18 nios_system_nios2_processor_nios2_oci_im " "Found entity 18: nios_system_nios2_processor_nios2_oci_im" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "19 nios_system_nios2_processor_nios2_performance_monitors " "Found entity 19: nios_system_nios2_processor_nios2_performance_monitors" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2608 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "20 nios_system_nios2_processor_nios2_oci " "Found entity 20: nios_system_nios2_processor_nios2_oci" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2624 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} { "Info" "ISGN_ENTITY_NAME" "21 nios_system_nios2_processor " "Found entity 21: nios_system_nios2_processor" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3129 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945382 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_sysclk " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945387 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945387 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_tck " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945390 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945390 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_wrapper " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945394 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945394 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_oci_test_bench " "Found entity 1: nios_system_nios2_processor_oci_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945397 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945397 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_test_bench " "Found entity 1: nios_system_nios2_processor_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945401 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945401 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_onchip_memory.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_onchip_memory " "Found entity 1: nios_system_onchip_memory" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945404 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_push_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_push_switches " "Found entity 1: nios_system_push_switches" { } { { "db/ip/nios_system/submodules/nios_system_push_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945408 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945408 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_demux_002 " "Found entity 1: nios_system_rsp_xbar_demux_002" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945411 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945411 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux " "Found entity 1: nios_system_rsp_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945414 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux_001 " "Found entity 1: nios_system_rsp_xbar_mux_001" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945418 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945418 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_switches " "Found entity 1: nios_system_switches" { } { { "db/ip/nios_system/submodules/nios_system_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945421 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945421 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1567) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1567 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609945438 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1569) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1569 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609945438 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1725) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1725 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609945439 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(2553) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2553 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1480609945442 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "lights " "Elaborating entity \"lights\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1480609945570 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system nios_system:NiosII " "Elaborating entity \"nios_system\" for hierarchy \"nios_system:NiosII\"" { } { { "lights.vhd" "NiosII" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945593 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor nios_system:NiosII\|nios_system_nios2_processor:nios2_processor " "Elaborating entity \"nios_system_nios2_processor\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945652 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench " "Elaborating entity \"nios_system_nios2_processor_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945664 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_a_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a " "Elaborating entity \"nios_system_nios2_processor_register_bank_a_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_a" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945668 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945706 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_a.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945708 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609945708 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0rh1 " "Found entity 1: altsyncram_0rh1" { } { { "db/altsyncram_0rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945778 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945778 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated " "Elaborating entity \"altsyncram_0rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945780 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_b_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b " "Elaborating entity \"nios_system_nios2_processor_register_bank_b_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_b" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4300 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945814 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945823 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_b.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945825 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609945825 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1rh1 " "Found entity 1: altsyncram_1rh1" { } { { "db/altsyncram_1rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609945894 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609945894 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated " "Elaborating entity \"altsyncram_1rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945896 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci " "Elaborating entity \"nios_system_nios2_processor_nios2_oci\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4758 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945929 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_debug nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_debug\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_debug" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945936 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altera_std_synchronizer" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945949 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609945950 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945950 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609945950 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_ocimem nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem " "Elaborating entity \"nios_system_nios2_processor_nios2_ocimem\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_ocimem" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2821 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945953 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_ociram_sp_ram_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram " "Elaborating entity \"nios_system_nios2_processor_ociram_sp_ram_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_ociram_sp_ram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 491 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945958 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945966 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_ociram_default_contents.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609945968 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609945968 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4891.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4891 " "Found entity 1: altsyncram_4891" { } { { "db/altsyncram_4891.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946033 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946033 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4891 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated " "Elaborating entity \"altsyncram_4891\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946035 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_avalon_reg nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg " "Elaborating entity \"nios_system_nios2_processor_nios2_avalon_reg\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_avalon_reg" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2840 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946070 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_break nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_break\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_break" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2871 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946074 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_xbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_xbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_xbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2892 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946078 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946082 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_itrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_itrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_itrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2937 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946085 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dtrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dtrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dtrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2952 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946089 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_td_mode nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_td_mode\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946094 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifo nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifo\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946097 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_compute_tm_count\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2046 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946101 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifowp_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2056 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946105 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifocount_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2066 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946109 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_oci_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench " "Elaborating entity \"nios_system_nios2_processor_oci_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946113 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_pib nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_pib\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_pib" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2981 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946116 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_im nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_im\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_im" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3002 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946120 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_wrapper nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_wrapper\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_jtag_debug_module_wrapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3107 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946123 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_tck nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_tck\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_tck" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946127 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_sysclk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_sysclk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_sysclk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946135 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "nios_system_nios2_processor_jtag_debug_module_phy" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946155 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946156 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609946156 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946158 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946159 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_onchip_memory nios_system:NiosII\|nios_system_onchip_memory:onchip_memory " "Elaborating entity \"nios_system_onchip_memory\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946164 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946171 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_onchip_memory.hex " "Parameter \"init_file\" = \"nios_system_onchip_memory.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 51200 " "Parameter \"maximum_depth\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 51200 " "Parameter \"numwords_a\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 16 " "Parameter \"widthad_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946172 ""} } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609946172 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4ed1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4ed1 " "Found entity 1: altsyncram_4ed1" { } { { "db/altsyncram_4ed1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946282 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4ed1 nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated " "Elaborating entity \"altsyncram_4ed1\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946284 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_qsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_qsa " "Found entity 1: decode_qsa" { } { { "db/decode_qsa.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946347 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946347 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_qsa nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3 " "Elaborating entity \"decode_qsa\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3\"" { } { { "db/altsyncram_4ed1.tdf" "decode3" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946349 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_nob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_nob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_nob " "Found entity 1: mux_nob" { } { { "db/mux_nob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946414 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_nob nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2 " "Elaborating entity \"mux_nob\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2\"" { } { { "db/altsyncram_4ed1.tdf" "mux2" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946416 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart nios_system:NiosII\|nios_system_jtag_uart:jtag_uart " "Elaborating entity \"nios_system_jtag_uart\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1129 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946605 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_w nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w " "Elaborating entity \"nios_system_jtag_uart_scfifo_w\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_w" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946609 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "wfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946658 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609946659 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946660 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609946660 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946722 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946722 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946724 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946734 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946734 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946736 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946746 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946746 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946748 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946807 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946807 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946810 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946871 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946871 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946873 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609946935 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609946935 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609946937 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1480609947004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1480609947004 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947006 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_r nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r " "Elaborating entity \"nios_system_jtag_uart_scfifo_r\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_r" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 429 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947018 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "nios_system_jtag_uart_alt_jtag_atlantic" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947137 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609947139 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947139 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947139 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1480609947139 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDs nios_system:NiosII\|nios_system_LEDs:leds " "Elaborating entity \"nios_system_LEDs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDs:leds\"" { } { { "nios_system/synthesis/nios_system.v" "leds" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947146 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDRs nios_system:NiosII\|nios_system_LEDRs:ledrs " "Elaborating entity \"nios_system_LEDRs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDRs:ledrs\"" { } { { "nios_system/synthesis/nios_system.v" "ledrs" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947148 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_switches nios_system:NiosII\|nios_system_switches:switches " "Elaborating entity \"nios_system_switches\" for hierarchy \"nios_system:NiosII\|nios_system_switches:switches\"" { } { { "nios_system/synthesis/nios_system.v" "switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1159 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947151 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_push_switches nios_system:NiosII\|nios_system_push_switches:push_switches " "Elaborating entity \"nios_system_push_switches\" for hierarchy \"nios_system:NiosII\|nios_system_push_switches:push_switches\"" { } { { "nios_system/synthesis/nios_system.v" "push_switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947154 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_hex0 nios_system:NiosII\|nios_system_hex0:hex0 " "Elaborating entity \"nios_system_hex0\" for hierarchy \"nios_system:NiosII\|nios_system_hex0:hex0\"" { } { { "nios_system/synthesis/nios_system.v" "hex0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947157 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_16207_0 nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0 " "Elaborating entity \"nios_system_lcd_16207_0\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947171 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_on nios_system:NiosII\|nios_system_lcd_on:lcd_on " "Elaborating entity \"nios_system_lcd_on\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_on:lcd_on\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_on" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1281 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947173 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947178 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1416 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947182 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1482 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947186 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1548 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947190 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "leds_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1614 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947194 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart_avalon_jtag_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1680 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947198 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0_control_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947225 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2684 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947235 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2764 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947240 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2845 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947244 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947249 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947253 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router nios_system:NiosII\|nios_system_addr_router:addr_router " "Elaborating entity \"nios_system_addr_router\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4976 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947374 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_default_decode nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 177 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947378 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001 nios_system:NiosII\|nios_system_addr_router_001:addr_router_001 " "Elaborating entity \"nios_system_addr_router_001\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4992 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947381 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001_default_decode nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_001_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947385 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router nios_system:NiosII\|nios_system_id_router:id_router " "Elaborating entity \"nios_system_id_router\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\"" { } { { "nios_system/synthesis/nios_system.v" "id_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_default_decode nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947391 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002 nios_system:NiosII\|nios_system_id_router_002:id_router_002 " "Elaborating entity \"nios_system_id_router_002\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\"" { } { { "nios_system/synthesis/nios_system.v" "id_router_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5040 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947397 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002_default_decode nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_002_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947400 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller nios_system:NiosII\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\"" { } { { "nios_system/synthesis/nios_system.v" "rst_controller" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5307 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947449 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 120 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947451 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"nios_system_cmd_xbar_demux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947454 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux_001 nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"nios_system_cmd_xbar_demux_001\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5449 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947458 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_mux nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"nios_system_cmd_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947465 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947469 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947472 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_demux_002 nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"nios_system_rsp_xbar_demux_002\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_demux_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5558 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947483 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"nios_system_rsp_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5836 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947510 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947514 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux_001 nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"nios_system_rsp_xbar_mux_001\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5955 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947518 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 552 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947530 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947533 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_irq_mapper nios_system:NiosII\|nios_system_irq_mapper:irq_mapper " "Elaborating entity \"nios_system_irq_mapper\" for hierarchy \"nios_system:NiosII\|nios_system_irq_mapper:irq_mapper\"" { } { { "nios_system/synthesis/nios_system.v" "irq_mapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1480609947537 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "5 " "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1480609954485 ""} -{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1480609954635 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1480609954635 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 276 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 348 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3167 -1 0 } } { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3740 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 393 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 599 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 62 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609954692 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609954693 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609956253 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "166 " "166 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1480609958838 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1480609958984 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1480609958984 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" { } { { "sld_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1480609959077 "|lights|sld_hub:auto_hub|receive[0][0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1480609959077 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609959224 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1480609959839 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1480609960862 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1480609960862 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "2881 " "Implemented 2881 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1480609961572 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1480609961572 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2422 " "Implemented 2422 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1480609961572 ""} { "Info" "ICUT_CUT_TM_RAMS" "336 " "Implemented 336 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1480609961572 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1480609961572 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 149 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 149 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "654 " "Peak virtual memory: 654 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480609961680 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:32:41 2016 " "Processing ended: Fri Dec 02 01:32:41 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480609961680 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480609961680 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480609961680 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480609961680 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1482368833579 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 22 10:07:13 2016 " "Processing started: Thu Dec 22 10:07:13 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lights -c lights " "Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1482368833579 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1482368833940 ""} +{ "Info" "ISGN_START_ELABORATION_QSYS" "nios_system.qsys " "Elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12248 "Elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368833977 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:14 Progress: Loading qsys_tutorial/nios_system.qsys " "2016.12.22.10:07:14 Progress: Loading qsys_tutorial/nios_system.qsys" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368834703 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:14 Progress: Reading input file " "2016.12.22.10:07:14 Progress: Reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368834888 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:14 Progress: Adding clk_0 \[clock_source 13.0\] " "2016.12.22.10:07:14 Progress: Adding clk_0 \[clock_source 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368834935 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module clk_0 " "2016.12.22.10:07:15 Progress: Parameterizing module clk_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835119 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\] " "2016.12.22.10:07:15 Progress: Adding nios2_processor \[altera_nios2_qsys 13.0\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835119 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module nios2_processor " "2016.12.22.10:07:15 Progress: Parameterizing module nios2_processor" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835819 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding onchip_memory \[altera_avalon_onchip_memory2 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835819 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module onchip_memory " "2016.12.22.10:07:15 Progress: Parameterizing module onchip_memory" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835888 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding jtag_uart \[altera_avalon_jtag_uart 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835888 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module jtag_uart " "2016.12.22.10:07:15 Progress: Parameterizing module jtag_uart" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835935 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding LEDs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835935 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module LEDs " "2016.12.22.10:07:15 Progress: Parameterizing module LEDs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding LEDRs \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module LEDRs " "2016.12.22.10:07:15 Progress: Parameterizing module LEDRs" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835972 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module switches " "2016.12.22.10:07:15 Progress: Parameterizing module switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding push_switches \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module push_switches " "2016.12.22.10:07:15 Progress: Parameterizing module push_switches" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex0 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex0 " "2016.12.22.10:07:15 Progress: Parameterizing module hex0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex1 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex1 " "2016.12.22.10:07:15 Progress: Parameterizing module hex1" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex2 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex2 " "2016.12.22.10:07:15 Progress: Parameterizing module hex2" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex3 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex3 " "2016.12.22.10:07:15 Progress: Parameterizing module hex3" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex4 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex4 " "2016.12.22.10:07:15 Progress: Parameterizing module hex4" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex5 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Parameterizing module hex5 " "2016.12.22.10:07:15 Progress: Parameterizing module hex5" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:15 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:15 Progress: Adding hex6 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368835988 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module hex6 " "2016.12.22.10:07:16 Progress: Parameterizing module hex6" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding hex7 \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module hex7 " "2016.12.22.10:07:16 Progress: Parameterizing module hex7" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding lcd_16207_0 \[altera_avalon_lcd_16207 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836003 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module lcd_16207_0 " "2016.12.22.10:07:16 Progress: Parameterizing module lcd_16207_0" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding lcd_on \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module lcd_on " "2016.12.22.10:07:16 Progress: Parameterizing module lcd_on" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\] " "2016.12.22.10:07:16 Progress: Adding lcd_blon \[altera_avalon_pio 13.0.1.99.2\]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing module lcd_blon " "2016.12.22.10:07:16 Progress: Parameterizing module lcd_blon" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Building connections " "2016.12.22.10:07:16 Progress: Building connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836019 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Parameterizing connections " "2016.12.22.10:07:16 Progress: Parameterizing connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836335 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Validating " "2016.12.22.10:07:16 Progress: Validating" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836335 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "2016.12.22.10:07:16 Progress: Done reading input file " "2016.12.22.10:07:16 Progress: Done reading input file" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368836974 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368837290 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. " "Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368837290 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH " "Nios_system: Generating nios_system \"nios_system\" for QUARTUS_SYNTH" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368838207 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections " "Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368838438 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "No custom instruction connections, skipping transform " "No custom instruction connections, skipping transform " { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368838446 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_translator_transform: After transform: 39 modules, 155 connections " "Merlin_translator_transform: After transform: 39 modules, 155 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368839130 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_domain_transform: After transform: 78 modules, 423 connections " "Merlin_domain_transform: After transform: 78 modules, 423 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840233 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_router_transform: After transform: 98 modules, 503 connections " "Merlin_router_transform: After transform: 98 modules, 503 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840668 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reset_adaptation_transform: After transform: 99 modules, 390 connections " "Reset_adaptation_transform: After transform: 99 modules, 390 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840752 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections " "Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368840984 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_mm_transform: After transform: 138 modules, 470 connections " "Merlin_mm_transform: After transform: 138 modules, 470 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368841081 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections " "Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368841112 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842192 ""} +{ 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found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role 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(reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842207 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for 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"Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req 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"%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842223 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Warning" "WSGN_EXT_PROC_WARNING_MSG" "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\" " "Nios_system: \"No matching role found for rst_controller:reset_out:reset_req (reset_req)\"" { } { } 0 12251 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842239 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842677 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \] " "Nios2_processor: Generation command is \[exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368842677 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Starting Nios II generation " "Nios2_processor: # 2016.12.22 10:07:23 (*) Starting Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Checking for plaintext license. " "Nios2_processor: # 2016.12.22 10:07:23 (*) Checking for plaintext license." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus " "Nios2_processor: # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable " "Nios2_processor: # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty " "Nios2_processor: # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Plaintext license not found. " "Nios2_processor: # 2016.12.22 10:07:23 (*) Plaintext license not found." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. " "Nios2_processor: # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e." { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings " "Nios2_processor: # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:23 (*) Creating all objects for CPU " "Nios2_processor: # 2016.12.22 10:07:23 (*) Creating all objects for CPU" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects " "Nios2_processor: # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:24 (*) Creating plain-text RTL " "Nios2_processor: # 2016.12.22 10:07:24 (*) Creating plain-text RTL" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: # 2016.12.22 10:07:26 (*) Done Nios II generation " "Nios2_processor: # 2016.12.22 10:07:26 (*) Done Nios II generation" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' " "Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846824 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\" " "Nios2_processor: \"nios_system\" instantiated altera_nios2_qsys \"nios2_processor\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846840 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846877 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \] " "Onchip_memory: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368846877 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' " "Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847896 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\" " "Onchip_memory: \"nios_system\" instantiated altera_avalon_onchip_memory2 \"onchip_memory\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847911 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847927 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \] " "Jtag_uart: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368847927 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' " "Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848212 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\" " "Jtag_uart: \"nios_system\" instantiated altera_avalon_jtag_uart \"jtag_uart\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848212 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Starting RTL generation for module 'nios_system_LEDs' " "LEDs: Starting RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848227 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \] " "LEDs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848243 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: Done RTL generation for module 'nios_system_LEDs' " "LEDs: Done RTL generation for module 'nios_system_LEDs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848412 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\" " "LEDs: \"nios_system\" instantiated altera_avalon_pio \"LEDs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848412 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Starting RTL generation for module 'nios_system_LEDRs' " "LEDRs: Starting RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848428 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \] " "LEDRs: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848428 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: Done RTL generation for module 'nios_system_LEDRs' " "LEDRs: Done RTL generation for module 'nios_system_LEDRs'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848612 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\" " "LEDRs: \"nios_system\" instantiated altera_avalon_pio \"LEDRs\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848612 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Starting RTL generation for module 'nios_system_switches' " "Switches: Starting RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848643 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \] " "Switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848643 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: Done RTL generation for module 'nios_system_switches' " "Switches: Done RTL generation for module 'nios_system_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848812 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\" " "Switches: \"nios_system\" instantiated altera_avalon_pio \"switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848812 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Starting RTL generation for module 'nios_system_push_switches' " "Push_switches: Starting RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848828 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \] " "Push_switches: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848828 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: Done RTL generation for module 'nios_system_push_switches' " "Push_switches: Done RTL generation for module 'nios_system_push_switches'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848997 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\" " "Push_switches: \"nios_system\" instantiated altera_avalon_pio \"push_switches\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368848997 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Starting RTL generation for module 'nios_system_hex0' " "Hex0: Starting RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849013 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \] " "Hex0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849013 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: Done RTL generation for module 'nios_system_hex0' " "Hex0: Done RTL generation for module 'nios_system_hex0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849198 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\" " "Hex0: \"nios_system\" instantiated altera_avalon_pio \"hex0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849198 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849214 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \] " "Lcd_16207_0: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849214 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' " "Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849382 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\" " "Lcd_16207_0: \"nios_system\" instantiated altera_avalon_lcd_16207 \"lcd_16207_0\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849382 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Starting RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849398 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \] " "Lcd_on: Generation command is \[exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 \]" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849398 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: Done RTL generation for module 'nios_system_lcd_on' " "Lcd_on: Done RTL generation for module 'nios_system_lcd_on'" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849582 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\" " "Lcd_on: \"nios_system\" instantiated altera_avalon_pio \"lcd_on\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849582 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\" " "Nios2_processor_instruction_master_translator: \"nios_system\" instantiated altera_merlin_master_translator \"nios2_processor_instruction_master_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849582 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\" " "Nios2_processor_jtag_debug_module_translator: \"nios_system\" instantiated altera_merlin_slave_translator \"nios2_processor_jtag_debug_module_translator\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849598 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\" " "Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: \"nios_system\" instantiated altera_merlin_master_agent \"nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849614 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: \"nios_system\" instantiated altera_merlin_slave_agent \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849614 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\" " "Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: \"nios_system\" instantiated altera_avalon_sc_fifo \"nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849629 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\" " "Addr_router: \"nios_system\" instantiated altera_merlin_router \"addr_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849645 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\" " "Addr_router_001: \"nios_system\" instantiated altera_merlin_router \"addr_router_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849676 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\" " "Id_router: \"nios_system\" instantiated altera_merlin_router \"id_router\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849683 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\" " "Id_router_002: \"nios_system\" instantiated altera_merlin_router \"id_router_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849698 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\" " "Rst_controller: \"nios_system\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849698 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\" " "Cmd_xbar_demux: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849714 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\" " "Cmd_xbar_demux_001: \"nios_system\" instantiated altera_merlin_demultiplexer \"cmd_xbar_demux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849761 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\" " "Cmd_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"cmd_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849798 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\" " "Rsp_xbar_demux_002: \"nios_system\" instantiated altera_merlin_demultiplexer \"rsp_xbar_demux_002\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849829 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\" " "Rsp_xbar_mux: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849861 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849861 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\" " "Rsp_xbar_mux_001: \"nios_system\" instantiated altera_merlin_multiplexer \"rsp_xbar_mux_001\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849929 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv " "Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849929 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\" " "Irq_mapper: \"nios_system\" instantiated altera_irq_mapper \"irq_mapper\"" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849945 ""} +{ "Info" "ISGN_EXT_PROC_INFO_MSG" "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes " "Nios_system: Done nios_system\" with 28 modules, 155 files, 4086283 bytes" { } { } 0 12250 "%1!s!" 0 0 "Quartus II" 0 -1 1482368849945 ""} +{ "Info" "ISGN_END_ELABORATION_QSYS" "nios_system.qsys " "Finished elaborating Qsys system entity \"nios_system.qsys\"" { } { } 0 12249 "Finished elaborating Qsys system entity \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368850903 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lights.vhd 2 1 " "Found 2 design units, including 1 entities, in source file lights.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lights-lights_rtl " "Found design unit 1: lights-lights_rtl" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 27 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851319 ""} { "Info" "ISGN_ENTITY_NAME" "1 lights " "Found entity 1: lights" { } { { "lights.vhd" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851319 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851319 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_system/synthesis/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "nios_system/synthesis/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851335 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851335 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/nios_system.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system " "Found entity 1: nios_system" { } { { "db/ip/nios_system/nios_system.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/nios_system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851366 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851384 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851384 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_ledrs.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDRs " "Found entity 1: nios_system_LEDRs" { } { { "db/ip/nios_system/submodules/nios_system_LEDRs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_leds.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_LEDs " "Found entity 1: nios_system_LEDs" { } { { "db/ip/nios_system/submodules/nios_system_LEDs.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851388 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_default_decode " "Found entity 1: nios_system_addr_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router " "Found entity 2: nios_system_addr_router" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_addr_router_001.sv(48) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_addr_router_001.sv(49) " "Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851404 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_addr_router_001_default_decode " "Found entity 1: nios_system_addr_router_001_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_addr_router_001 " "Found entity 2: nios_system_addr_router_001" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux " "Found entity 1: nios_system_cmd_xbar_demux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851404 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_demux_001 " "Found entity 1: nios_system_cmd_xbar_demux_001" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_cmd_xbar_mux " "Found entity 1: nios_system_cmd_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_hex0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_hex0 " "Found entity 1: nios_system_hex0" { } { { "db/ip/nios_system/submodules/nios_system_hex0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router.sv(48) " "Verilog HDL Declaration information at nios_system_id_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router.sv(49) " "Verilog HDL Declaration information at nios_system_id_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_default_decode " "Found entity 1: nios_system_id_router_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router " "Found entity 2: nios_system_id_router" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel nios_system_id_router_002.sv(48) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel nios_system_id_router_002.sv(49) " "Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_id_router_002_default_decode " "Found entity 1: nios_system_id_router_002_default_decode" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_id_router_002 " "Found entity 2: nios_system_id_router_002" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851420 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_irq_mapper " "Found entity 1: nios_system_irq_mapper" { } { { "db/ip/nios_system/submodules/nios_system_irq_mapper.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_jtag_uart.v 5 5 " "Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_jtag_uart_sim_scfifo_w " "Found entity 1: nios_system_jtag_uart_sim_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_jtag_uart_scfifo_w " "Found entity 2: nios_system_jtag_uart_scfifo_w" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_jtag_uart_sim_scfifo_r " "Found entity 3: nios_system_jtag_uart_sim_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 162 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_jtag_uart_scfifo_r " "Found entity 4: nios_system_jtag_uart_scfifo_r" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 240 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_jtag_uart " "Found entity 5: nios_system_jtag_uart" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 327 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_16207_0 " "Found entity 1: nios_system_lcd_16207_0" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_lcd_on.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_lcd_on " "Found entity 1: nios_system_lcd_on" { } { { "db/ip/nios_system/submodules/nios_system_lcd_on.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851435 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor.v 21 21 " "Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_register_bank_a_module " "Found entity 1: nios_system_nios2_processor_register_bank_a_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "2 nios_system_nios2_processor_register_bank_b_module " "Found entity 2: nios_system_nios2_processor_register_bank_b_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "3 nios_system_nios2_processor_nios2_oci_debug " "Found entity 3: nios_system_nios2_processor_nios2_oci_debug" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 147 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "4 nios_system_nios2_processor_ociram_sp_ram_module " "Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 288 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "5 nios_system_nios2_processor_nios2_ocimem " "Found entity 5: nios_system_nios2_processor_nios2_ocimem" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 346 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "6 nios_system_nios2_processor_nios2_avalon_reg " "Found entity 6: nios_system_nios2_processor_nios2_avalon_reg" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 524 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "7 nios_system_nios2_processor_nios2_oci_break " "Found entity 7: nios_system_nios2_processor_nios2_oci_break" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 616 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "8 nios_system_nios2_processor_nios2_oci_xbrk " "Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 910 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "9 nios_system_nios2_processor_nios2_oci_dbrk " "Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1116 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "10 nios_system_nios2_processor_nios2_oci_itrace " "Found entity 10: nios_system_nios2_processor_nios2_oci_itrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1302 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "11 nios_system_nios2_processor_nios2_oci_td_mode " "Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1599 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "12 nios_system_nios2_processor_nios2_oci_dtrace " "Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "13 nios_system_nios2_processor_nios2_oci_compute_tm_count " "Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1760 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "14 nios_system_nios2_processor_nios2_oci_fifowp_inc " "Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1831 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "15 nios_system_nios2_processor_nios2_oci_fifocount_inc " "Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1873 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "16 nios_system_nios2_processor_nios2_oci_fifo " "Found entity 16: nios_system_nios2_processor_nios2_oci_fifo" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1919 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "17 nios_system_nios2_processor_nios2_oci_pib " "Found entity 17: nios_system_nios2_processor_nios2_oci_pib" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2424 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "18 nios_system_nios2_processor_nios2_oci_im " "Found entity 18: nios_system_nios2_processor_nios2_oci_im" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "19 nios_system_nios2_processor_nios2_performance_monitors " "Found entity 19: nios_system_nios2_processor_nios2_performance_monitors" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2608 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "20 nios_system_nios2_processor_nios2_oci " "Found entity 20: nios_system_nios2_processor_nios2_oci" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2624 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} { "Info" "ISGN_ENTITY_NAME" "21 nios_system_nios2_processor " "Found entity 21: nios_system_nios2_processor" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3129 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_sysclk " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_tck " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_jtag_debug_module_wrapper " "Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851467 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_oci_test_bench " "Found entity 1: nios_system_nios2_processor_oci_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851483 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851483 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_nios2_processor_test_bench " "Found entity 1: nios_system_nios2_processor_test_bench" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851487 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_onchip_memory.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_onchip_memory " "Found entity 1: nios_system_onchip_memory" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_push_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_push_switches " "Found entity 1: nios_system_push_switches" { } { { "db/ip/nios_system/submodules/nios_system_push_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_demux_002 " "Found entity 1: nios_system_rsp_xbar_demux_002" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux " "Found entity 1: nios_system_rsp_xbar_mux" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_rsp_xbar_mux_001 " "Found entity 1: nios_system_rsp_xbar_mux_001" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851488 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/nios_system/submodules/nios_system_switches.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v" { { "Info" "ISGN_ENTITY_NAME" "1 nios_system_switches " "Found entity 1: nios_system_switches" { } { { "db/ip/nios_system/submodules/nios_system_switches.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368851504 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368851504 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1567) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1567 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1569) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1569 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(1725) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1725 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "nios_system_nios2_processor.v(2553) " "Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2553 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 1 0 "Quartus II" 0 -1 1482368851520 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "lights " "Elaborating entity \"lights\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1482368851689 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system nios_system:NiosII " "Elaborating entity \"nios_system\" for hierarchy \"nios_system:NiosII\"" { } { { "lights.vhd" "NiosII" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd" 53 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368851689 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor nios_system:NiosII\|nios_system_nios2_processor:nios2_processor " "Elaborating entity \"nios_system_nios2_processor\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852468 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench " "Elaborating entity \"nios_system_nios2_processor_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852638 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_a_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a " "Elaborating entity \"nios_system_nios2_processor_register_bank_a_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_a" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4279 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852691 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852785 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368852787 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_a.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852788 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 55 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368852788 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0rh1 " "Found entity 1: altsyncram_0rh1" { } { { "db/altsyncram_0rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368852854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368852854 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated " "Elaborating entity \"altsyncram_0rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_0rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852854 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_register_bank_b_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b " "Elaborating entity \"nios_system_nios2_processor_register_bank_b_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_register_bank_b" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4300 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852891 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_rf_ram_b.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852923 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 118 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368852923 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1rh1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1rh1 " "Found entity 1: altsyncram_1rh1" { } { { "db/altsyncram_1rh1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368852992 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368852992 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1rh1 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated " "Elaborating entity \"altsyncram_1rh1\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_1rh1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368852992 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci " "Elaborating entity \"nios_system_nios2_processor_nios2_oci\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 4758 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853023 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_debug nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_debug\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_debug" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853070 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altera_std_synchronizer" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853092 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853092 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853092 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 213 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853092 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_ocimem nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem " "Elaborating entity \"nios_system_nios2_processor_nios2_ocimem\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_ocimem" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2821 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853107 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_ociram_sp_ram_module nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram " "Elaborating entity \"nios_system_nios2_processor_ociram_sp_ram_module\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_ociram_sp_ram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 491 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853170 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_nios2_processor_ociram_default_contents.mif " "Parameter \"init_file\" = \"nios_system_nios2_processor_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853192 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 322 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853192 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4891.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4891 " "Found entity 1: altsyncram_4891" { } { { "db/altsyncram_4891.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853255 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853255 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4891 nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated " "Elaborating entity \"altsyncram_4891\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem\|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_4891:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853255 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_avalon_reg nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg " "Elaborating entity \"nios_system_nios2_processor_nios2_avalon_reg\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_avalon_reg" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2840 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853292 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_break nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_break\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_break" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2871 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853308 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_xbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_xbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_xbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2892 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853339 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dbrk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dbrk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dbrk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853355 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_itrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_itrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_itrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2937 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853370 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_dtrace nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_dtrace\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_dtrace" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2952 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853393 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_td_mode nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_td_mode\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace\|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 1714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853424 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifo nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifo\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853439 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_compute_tm_count\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2046 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853488 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifowp_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2056 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853493 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_fifocount_inc\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2066 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853540 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_oci_test_bench nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench " "Elaborating entity \"nios_system_nios2_processor_oci_test_bench\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo\|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853571 ""} +{ "Warning" "WSGN_EMPTY_SHELL" "nios_system_nios2_processor_oci_test_bench " "Entity \"nios_system_nios2_processor_oci_test_bench\" contains only dangling pins" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_oci_test_bench" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2075 0 0 } } } 0 12158 "Entity \"%1!s!\" contains only dangling pins" 0 0 "Quartus II" 0 -1 1482368853571 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_pib nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_pib\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_pib" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 2981 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853588 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_nios2_oci_im nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im " "Elaborating entity \"nios_system_nios2_processor_nios2_oci_im\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_nios2_oci_im" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3002 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853593 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_wrapper nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_wrapper\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "the_nios_system_nios2_processor_jtag_debug_module_wrapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3107 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853609 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_tck nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_tck\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_tck" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853640 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_nios2_processor_jtag_debug_module_sysclk nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk " "Elaborating entity \"nios_system_nios2_processor_jtag_debug_module_sysclk\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "the_nios_system_nios2_processor_jtag_debug_module_sysclk" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853671 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "nios_system_nios2_processor_jtag_debug_module_phy" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Instantiated megafunction \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} } { { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853709 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"nios_system:NiosII\|nios_system_nios2_processor:nios2_processor\|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci\|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_onchip_memory nios_system:NiosII\|nios_system_onchip_memory:onchip_memory " "Elaborating entity \"nios_system_onchip_memory\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853709 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "the_altsyncram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853724 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\"" { } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram " "Instantiated megafunction \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file nios_system_onchip_memory.hex " "Parameter \"init_file\" = \"nios_system_onchip_memory.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 51200 " "Parameter \"maximum_depth\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 51200 " "Parameter \"numwords_a\" = \"51200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 16 " "Parameter \"widthad_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853740 ""} } { { "db/ip/nios_system/submodules/nios_system_onchip_memory.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v" 66 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368853740 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4ed1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4ed1 " "Found entity 1: altsyncram_4ed1" { } { { "db/altsyncram_4ed1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853824 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853824 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4ed1 nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated " "Elaborating entity \"altsyncram_4ed1\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853840 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_qsa.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_qsa " "Found entity 1: decode_qsa" { } { { "db/decode_qsa.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853893 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853893 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_qsa nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3 " "Elaborating entity \"decode_qsa\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|decode_qsa:decode3\"" { } { { "db/altsyncram_4ed1.tdf" "decode3" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853893 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_nob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_nob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_nob " "Found entity 1: mux_nob" { } { { "db/mux_nob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368853971 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368853971 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_nob nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2 " "Elaborating entity \"mux_nob\" for hierarchy \"nios_system:NiosII\|nios_system_onchip_memory:onchip_memory\|altsyncram:the_altsyncram\|altsyncram_4ed1:auto_generated\|mux_nob:mux2\"" { } { { "db/altsyncram_4ed1.tdf" "mux2" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368853971 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart nios_system:NiosII\|nios_system_jtag_uart:jtag_uart " "Elaborating entity \"nios_system_jtag_uart\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1129 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854272 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_w nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w " "Elaborating entity \"nios_system_jtag_uart_scfifo_w\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_w" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854294 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "wfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854372 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 137 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368854372 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854441 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854441 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854441 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854457 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854457 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854473 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854473 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854489 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854573 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854573 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854673 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854673 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854673 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854825 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854825 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854826 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1482368854889 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1482368854889 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854889 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_jtag_uart_scfifo_r nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r " "Elaborating entity \"nios_system_jtag_uart_scfifo_r\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "the_nios_system_jtag_uart_scfifo_r" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 429 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368854904 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "nios_system_jtag_uart_alt_jtag_atlantic" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855073 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Elaborated megafunction instantiation \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\"" { } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic " "Instantiated megafunction \"nios_system:NiosII\|nios_system_jtag_uart:jtag_uart\|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} } { { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 564 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1482368855089 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDs nios_system:NiosII\|nios_system_LEDs:leds " "Elaborating entity \"nios_system_LEDs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDs:leds\"" { } { { "nios_system/synthesis/nios_system.v" "leds" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855089 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_LEDRs nios_system:NiosII\|nios_system_LEDRs:ledrs " "Elaborating entity \"nios_system_LEDRs\" for hierarchy \"nios_system:NiosII\|nios_system_LEDRs:ledrs\"" { } { { "nios_system/synthesis/nios_system.v" "ledrs" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855104 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_switches nios_system:NiosII\|nios_system_switches:switches " "Elaborating entity \"nios_system_switches\" for hierarchy \"nios_system:NiosII\|nios_system_switches:switches\"" { } { { "nios_system/synthesis/nios_system.v" "switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1159 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855126 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_push_switches nios_system:NiosII\|nios_system_push_switches:push_switches " "Elaborating entity \"nios_system_push_switches\" for hierarchy \"nios_system:NiosII\|nios_system_push_switches:push_switches\"" { } { { "nios_system/synthesis/nios_system.v" "push_switches" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855142 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_hex0 nios_system:NiosII\|nios_system_hex0:hex0 " "Elaborating entity \"nios_system_hex0\" for hierarchy \"nios_system:NiosII\|nios_system_hex0:hex0\"" { } { { "nios_system/synthesis/nios_system.v" "hex0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1178 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855158 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_16207_0 nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0 " "Elaborating entity \"nios_system_lcd_16207_0\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855189 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_lcd_on nios_system:NiosII\|nios_system_lcd_on:lcd_on " "Elaborating entity \"nios_system_lcd_on\" for hierarchy \"nios_system:NiosII\|nios_system_lcd_on:lcd_on\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_on" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1281 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855204 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_instruction_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855227 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_translator:nios2_processor_data_master_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1416 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855324 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1482 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855342 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:onchip_memory_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "onchip_memory_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1548 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855374 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:leds_s1_translator\"" { } { { "nios_system/synthesis/nios_system.v" "leds_s1_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1614 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855405 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "jtag_uart_avalon_jtag_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 1680 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855443 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\"" { } { { "nios_system/synthesis/nios_system.v" "lcd_16207_0_control_slave_translator" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855505 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2684 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855559 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2764 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855590 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2845 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855627 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"nios_system:NiosII\|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv" 574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855659 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"nios_system:NiosII\|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "nios_system/synthesis/nios_system.v" "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 2886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855690 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router nios_system:NiosII\|nios_system_addr_router:addr_router " "Elaborating entity \"nios_system_addr_router\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4976 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855928 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_default_decode nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router:addr_router\|nios_system_addr_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv" 177 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855960 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001 nios_system:NiosII\|nios_system_addr_router_001:addr_router_001 " "Elaborating entity \"nios_system_addr_router_001\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\"" { } { { "nios_system/synthesis/nios_system.v" "addr_router_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 4992 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368855975 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_addr_router_001_default_decode nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"nios_system_addr_router_001_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_addr_router_001:addr_router_001\|nios_system_addr_router_001_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856029 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router nios_system:NiosII\|nios_system_id_router:id_router " "Elaborating entity \"nios_system_id_router\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\"" { } { { "nios_system/synthesis/nios_system.v" "id_router" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856044 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_default_decode nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router:id_router\|nios_system_id_router_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856076 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002 nios_system:NiosII\|nios_system_id_router_002:id_router_002 " "Elaborating entity \"nios_system_id_router_002\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\"" { } { { "nios_system/synthesis/nios_system.v" "id_router_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5040 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856091 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_id_router_002_default_decode nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"nios_system_id_router_002_default_decode\" for hierarchy \"nios_system:NiosII\|nios_system_id_router_002:id_router_002\|nios_system_id_router_002_default_decode:the_default_decode\"" { } { { "db/ip/nios_system/submodules/nios_system_id_router_002.sv" "the_default_decode" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv" 175 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856107 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller nios_system:NiosII\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\"" { } { { "nios_system/synthesis/nios_system.v" "rst_controller" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5307 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856608 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"nios_system:NiosII\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "db/ip/nios_system/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v" 120 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856629 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"nios_system_cmd_xbar_demux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5330 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856630 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_demux_001 nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"nios_system_cmd_xbar_demux_001\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_demux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5449 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856661 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_cmd_xbar_mux nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"nios_system_cmd_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "cmd_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5472 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856730 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856777 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856793 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_demux_002 nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"nios_system_rsp_xbar_demux_002\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_demux_002" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5558 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856830 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"nios_system_rsp_xbar_mux\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5836 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856893 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856930 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_rsp_xbar_mux_001 nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"nios_system_rsp_xbar_mux_001\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "nios_system/synthesis/nios_system.v" "rsp_xbar_mux_001" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5955 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368856962 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv" 552 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368857128 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"nios_system:NiosII\|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368857147 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_system_irq_mapper nios_system:NiosII\|nios_system_irq_mapper:irq_mapper " "Elaborating entity \"nios_system_irq_mapper\" for hierarchy \"nios_system:NiosII\|nios_system_irq_mapper:irq_mapper\"" { } { { "nios_system/synthesis/nios_system.v" "irq_mapper" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v" 5962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1482368857162 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "5 " "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1482368866226 ""} +{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[0\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[0\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[1\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[1\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[2\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[2\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[3\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[3\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[4\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[4\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[5\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[5\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[6\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[6\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\] nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\] " "Converted the fan-out from the tri-state buffer \"nios_system:NiosII\|nios_system_lcd_16207_0:lcd_16207_0\|LCD_data\[7\]\" to the node \"nios_system:NiosII\|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator\|av_readdata_pre\[7\]\" into an OR gate" { } { { "db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v" 43 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1482368866410 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1482368866410 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "db/ip/nios_system/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv" 276 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 348 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3167 -1 0 } } { "db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 3740 -1 0 } } { "db/ip/nios_system/submodules/nios_system_jtag_uart.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v" 393 -1 0 } } { "db/ip/nios_system/submodules/nios_system_nios2_processor.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v" 599 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "db/ip/nios_system/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v" 62 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1482368866448 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1482368866448 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368868229 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "166 " "166 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1482368870827 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 384 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 521 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1482368870965 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1482368870965 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" { } { { "sld_hub.vhd" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd" 181 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1482368871065 "|lights|sld_hub:auto_hub|receive[0][0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1482368871065 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368871212 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg " "Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1482368871813 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1482368872784 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1482368872784 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "2878 " "Implemented 2878 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Implemented 26 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1482368873216 ""} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Implemented 96 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1482368873216 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2419 " "Implemented 2419 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1482368873216 ""} { "Info" "ICUT_CUT_TM_RAMS" "336 " "Implemented 336 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1482368873216 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1482368873216 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 150 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 150 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "657 " "Peak virtual memory: 657 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368873385 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:07:53 2016 " "Processing ended: Thu Dec 22 10:07:53 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:36 " "Total CPU time (on all processors): 00:00:36" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1482368873385 ""} diff --git a/db/lights.map.rdb b/db/lights.map.rdb index 7ece1a4..f9de163 100644 --- a/db/lights.map.rdb +++ b/db/lights.map.rdb Binary files differ diff --git a/db/lights.map_bb.cdb b/db/lights.map_bb.cdb index 855b759..1e47766 100644 --- a/db/lights.map_bb.cdb +++ b/db/lights.map_bb.cdb Binary files differ diff --git a/db/lights.map_bb.hdb b/db/lights.map_bb.hdb index 17327b9..f876e14 100644 --- a/db/lights.map_bb.hdb +++ b/db/lights.map_bb.hdb Binary files differ diff --git a/db/lights.map_bb.logdb b/db/lights.map_bb.logdb index 626799f..d45424f 100644 --- a/db/lights.map_bb.logdb +++ b/db/lights.map_bb.logdb @@ -1 +1 @@ -v1 +v1 diff --git a/db/lights.pre_map.hdb b/db/lights.pre_map.hdb index d4a06ad..d1c0f30 100644 --- a/db/lights.pre_map.hdb +++ b/db/lights.pre_map.hdb Binary files differ diff --git a/db/lights.root_partition.map.reg_db.cdb b/db/lights.root_partition.map.reg_db.cdb index 273c591..6482524 100644 --- a/db/lights.root_partition.map.reg_db.cdb +++ b/db/lights.root_partition.map.reg_db.cdb Binary files differ diff --git a/db/lights.routing.rdb b/db/lights.routing.rdb index 18abead..de01a9e 100644 --- a/db/lights.routing.rdb +++ b/db/lights.routing.rdb Binary files differ diff --git a/db/lights.rtlv.hdb b/db/lights.rtlv.hdb index 52d09b3..e72b35f 100644 --- a/db/lights.rtlv.hdb +++ b/db/lights.rtlv.hdb Binary files differ diff --git a/db/lights.rtlv_sg.cdb b/db/lights.rtlv_sg.cdb index b4cfdd8..dd838f2 100644 --- a/db/lights.rtlv_sg.cdb +++ b/db/lights.rtlv_sg.cdb Binary files differ diff --git a/db/lights.rtlv_sg_swap.cdb b/db/lights.rtlv_sg_swap.cdb index b0df21c..203d12c 100644 --- a/db/lights.rtlv_sg_swap.cdb +++ b/db/lights.rtlv_sg_swap.cdb Binary files differ diff --git a/db/lights.sgdiff.cdb b/db/lights.sgdiff.cdb index d2fe7ab..3e4e6ed 100644 --- a/db/lights.sgdiff.cdb +++ b/db/lights.sgdiff.cdb Binary files differ diff --git a/db/lights.sgdiff.hdb b/db/lights.sgdiff.hdb index f15c16f..9620e6c 100644 --- a/db/lights.sgdiff.hdb +++ b/db/lights.sgdiff.hdb Binary files differ diff --git a/db/lights.sld_design_entry_dsc.sci b/db/lights.sld_design_entry_dsc.sci index 828738f..74164de 100644 --- a/db/lights.sld_design_entry_dsc.sci +++ b/db/lights.sld_design_entry_dsc.sci Binary files differ diff --git a/db/lights.smart_action.txt b/db/lights.smart_action.txt index c8e8a13..437a63e 100644 --- a/db/lights.smart_action.txt +++ b/db/lights.smart_action.txt @@ -1 +1 @@ -DONE +DONE diff --git a/db/lights.smp_dump.txt b/db/lights.smp_dump.txt index ac16d24..bed5286 100644 --- a/db/lights.smp_dump.txt +++ b/db/lights.smp_dump.txt @@ -1,9 +1,9 @@ - -State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize -Name DRsize.101 DRsize.100 DRsize.011 DRsize.010 DRsize.001 DRsize.000 -DRsize.000 0 0 0 0 0 0 -DRsize.001 0 0 0 0 1 1 -DRsize.010 0 0 0 1 0 1 -DRsize.011 0 0 1 0 0 1 -DRsize.100 0 1 0 0 0 1 -DRsize.101 1 0 0 0 0 1 + +State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize +Name DRsize.101 DRsize.100 DRsize.011 DRsize.010 DRsize.001 DRsize.000 +DRsize.000 0 0 0 0 0 0 +DRsize.001 0 0 0 0 1 1 +DRsize.010 0 0 0 1 0 1 +DRsize.011 0 0 1 0 0 1 +DRsize.100 0 1 0 0 0 1 +DRsize.101 1 0 0 0 0 1 diff --git a/db/lights.sta.qmsg b/db/lights.sta.qmsg index 5c9f85f..a097636 100644 --- a/db/lights.sta.qmsg +++ b/db/lights.sta.qmsg @@ -1,43 +1,43 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1480610002504 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1480610002505 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 01:33:22 2016 " "Processing started: Fri Dec 02 01:33:22 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1480610002505 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1480610002505 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lights -c lights " "Command: quartus_sta lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1480610002505 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1480610002592 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1480610003035 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480610003035 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480610003113 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1480610003113 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1480610003901 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1480610003901 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1480610003940 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480610003950 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610004496 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610004496 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610004496 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480610004496 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1480610004497 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1480610004562 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 45.777 " "Worst-case setup slack is 45.777" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004591 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004591 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 45.777 0.000 altera_reserved_tck " " 45.777 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004591 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610004591 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.403 " "Worst-case hold slack is 0.403" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004600 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.403 0.000 altera_reserved_tck " " 0.403 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004600 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610004600 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.734 " "Worst-case recovery slack is 47.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004607 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004607 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.734 0.000 altera_reserved_tck " " 47.734 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004607 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610004607 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.385 " "Worst-case removal slack is 1.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004615 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004615 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 altera_reserved_tck " " 1.385 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004615 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610004615 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.549 " "Worst-case minimum pulse width slack is 49.549" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004622 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.549 0.000 altera_reserved_tck " " 49.549 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004622 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610004622 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.101 ns " "Worst Case Available Settling Time: 197.101 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610004754 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480610004766 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1480610004807 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1480610006044 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480610006357 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610006367 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610006367 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610006367 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480610006367 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.283 " "Worst-case setup slack is 46.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.283 0.000 altera_reserved_tck " " 46.283 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006392 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610006392 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.353 " "Worst-case hold slack is 0.353" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.353 0.000 altera_reserved_tck " " 0.353 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006403 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610006403 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 48.047 " "Worst-case recovery slack is 48.047" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.047 0.000 altera_reserved_tck " " 48.047 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006413 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610006413 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.278 " "Worst-case removal slack is 1.278" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.278 0.000 altera_reserved_tck " " 1.278 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006423 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610006423 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.476 " "Worst-case minimum pulse width slack is 49.476" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.476 0.000 altera_reserved_tck " " 49.476 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006434 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610006434 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.386 ns " "Worst Case Available Settling Time: 197.386 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610006573 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1480610006590 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1480610007036 "|lights|CLOCK_50"} -{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610007046 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610007046 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1480610007046 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1480610007046 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.270 " "Worst-case setup slack is 48.270" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.270 0.000 altera_reserved_tck " " 48.270 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007611 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610007611 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.180 " "Worst-case hold slack is 0.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007623 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.180 0.000 altera_reserved_tck " " 0.180 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007623 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610007623 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.194 " "Worst-case recovery slack is 49.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007635 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.194 0.000 altera_reserved_tck " " 49.194 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007635 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610007635 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.657 " "Worst-case removal slack is 0.657" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007646 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007646 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.657 0.000 altera_reserved_tck " " 0.657 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007646 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610007646 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.301 " "Worst-case minimum pulse width slack is 49.301" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.301 0.000 altera_reserved_tck " " 49.301 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007657 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1480610007657 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.621 ns " "Worst Case Available Settling Time: 198.621 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1480610007778 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480610008406 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1480610008406 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "606 " "Peak virtual memory: 606 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1480610008671 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 01:33:28 2016 " "Processing ended: Fri Dec 02 01:33:28 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1480610008671 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1480610008671 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1480610008671 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1480610008671 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1482368922934 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 22 10:08:42 2016 " "Processing started: Thu Dec 22 10:08:42 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lights -c lights " "Command: quartus_sta lights -c lights" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1482368922934 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1482368923013 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1482368923350 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1482368923350 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1482368923435 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1482368923435 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1482368924166 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1482368924166 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "lights.sdc " "Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1482368924198 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1482368924213 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368924736 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368924736 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368924736 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1482368924736 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1482368924736 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1482368924783 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.656 " "Worst-case setup slack is 46.656" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.656 0.000 altera_reserved_tck " " 46.656 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924814 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 altera_reserved_tck " " 0.401 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924834 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.591 " "Worst-case recovery slack is 47.591" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.591 0.000 altera_reserved_tck " " 47.591 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.180 " "Worst-case removal slack is 1.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.180 0.000 altera_reserved_tck " " 1.180 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924836 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.555 " "Worst-case minimum pulse width slack is 49.555" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.555 0.000 altera_reserved_tck " " 49.555 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368924852 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.069 ns " "Worst Case Available Settling Time: 197.069 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368924967 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1482368924983 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1482368925014 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1482368926251 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1482368926652 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368926667 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368926667 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368926667 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1482368926667 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.042 " "Worst-case setup slack is 47.042" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.042 0.000 altera_reserved_tck " " 47.042 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926699 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.353 " "Worst-case hold slack is 0.353" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.353 0.000 altera_reserved_tck " " 0.353 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926714 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.930 " "Worst-case recovery slack is 47.930" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.930 0.000 altera_reserved_tck " " 47.930 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926730 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.082 " "Worst-case removal slack is 1.082" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.082 0.000 altera_reserved_tck " " 1.082 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.489 " "Worst-case minimum pulse width slack is 49.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.489 0.000 altera_reserved_tck " " 49.489 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368926736 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.362 ns " "Worst Case Available Settling Time: 197.362 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368926952 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1482368926967 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "CLOCK_50 " "Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1482368927452 "|lights|CLOCK_50"} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368927467 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368927467 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Fall) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1482368927467 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1482368927467 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.710 " "Worst-case setup slack is 48.710" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.710 0.000 altera_reserved_tck " " 48.710 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 altera_reserved_tck " " 0.178 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927483 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.091 " "Worst-case recovery slack is 49.091" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.091 0.000 altera_reserved_tck " " 49.091 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927499 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.560 " "Worst-case removal slack is 0.560" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.560 0.000 altera_reserved_tck " " 0.560 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927514 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.301 " "Worst-case minimum pulse width slack is 49.301" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.301 0.000 altera_reserved_tck " " 49.301 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1482368927531 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.608 ns " "Worst Case Available Settling Time: 198.608 ns" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} } { } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1482368927668 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1482368928485 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1482368928485 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "605 " "Peak virtual memory: 605 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1482368928785 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 22 10:08:48 2016 " "Processing ended: Thu Dec 22 10:08:48 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1482368928785 ""} diff --git a/db/lights.sta.rdb b/db/lights.sta.rdb index 0f9eebd..465b5e9 100644 --- a/db/lights.sta.rdb +++ b/db/lights.sta.rdb Binary files differ diff --git a/db/lights.sta_cmp.7_slow_1200mv_85c.tdb b/db/lights.sta_cmp.7_slow_1200mv_85c.tdb index 0e1bbb7..b34b9e3 100644 --- a/db/lights.sta_cmp.7_slow_1200mv_85c.tdb +++ b/db/lights.sta_cmp.7_slow_1200mv_85c.tdb Binary files differ diff --git a/db/lights.tiscmp.fast_1200mv_0c.ddb b/db/lights.tiscmp.fast_1200mv_0c.ddb index b1bd393..c611c18 100644 --- a/db/lights.tiscmp.fast_1200mv_0c.ddb +++ b/db/lights.tiscmp.fast_1200mv_0c.ddb Binary files differ diff --git a/db/lights.tiscmp.slow_1200mv_0c.ddb b/db/lights.tiscmp.slow_1200mv_0c.ddb index cab0102..985b273 100644 --- a/db/lights.tiscmp.slow_1200mv_0c.ddb +++ b/db/lights.tiscmp.slow_1200mv_0c.ddb Binary files differ diff --git a/db/lights.tiscmp.slow_1200mv_85c.ddb b/db/lights.tiscmp.slow_1200mv_85c.ddb index 0bb79a8..091992f 100644 --- a/db/lights.tiscmp.slow_1200mv_85c.ddb +++ b/db/lights.tiscmp.slow_1200mv_85c.ddb Binary files differ diff --git a/db/lights.tmw_info b/db/lights.tmw_info index 16f5f5b..e8b5b31 100644 --- a/db/lights.tmw_info +++ b/db/lights.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s -start_analysis_synthesis:s-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s-start_full_compilation -start_assembler:s-start_full_compilation -start_timing_analyzer:s-start_full_compilation +start_full_compilation:s:00:02:07 +start_analysis_synthesis:s:00:00:58-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:46-start_full_compilation +start_assembler:s:00:00:10-start_full_compilation +start_timing_analyzer:s:00:00:13-start_full_compilation diff --git a/db/lights.vpr.ammdb b/db/lights.vpr.ammdb index cd8485a..c5824e4 100644 --- a/db/lights.vpr.ammdb +++ b/db/lights.vpr.ammdb Binary files differ diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index 8ae4343..43cd21a 100644 --- a/db/logic_util_heursitic.dat +++ b/db/logic_util_heursitic.dat Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.cdb b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.cdb index 609cc54..41f2979 100644 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.cdb +++ b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.cdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.dpi b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.dpi index 97c335e..621683f 100644 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.dpi +++ b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.dpi Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.hdb b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.hdb index e1c7b0e..7845a71 100644 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.hdb +++ b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.hdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.kpt b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.kpt index 1fbf9ec..e797630 100644 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.kpt +++ b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.kpt Binary files differ diff --git a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.logdb b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.logdb index 626799f..d45424f 100644 --- a/incremental_db/compiled_partitions/lights.autoh_e40e1.map.logdb +++ b/incremental_db/compiled_partitions/lights.autoh_e40e1.map.logdb @@ -1 +1 @@ -v1 +v1 diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.ammdb index 74e1f97..0f7344e 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.ammdb +++ b/incremental_db/compiled_partitions/lights.root_partition.cmp.ammdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.cdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.cdb index c2d311e..2825e6c 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.cdb +++ b/incremental_db/compiled_partitions/lights.root_partition.cmp.cdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.hdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.hdb index 8e61d41..13d1bb1 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.hdb +++ b/incremental_db/compiled_partitions/lights.root_partition.cmp.hdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.logdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.logdb index 626799f..d45424f 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.logdb +++ b/incremental_db/compiled_partitions/lights.root_partition.cmp.logdb @@ -1 +1 @@ -v1 +v1 diff --git a/incremental_db/compiled_partitions/lights.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/lights.root_partition.cmp.rcfdb index 299f581..0e23f08 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.cmp.rcfdb +++ b/incremental_db/compiled_partitions/lights.root_partition.cmp.rcfdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.cdb b/incremental_db/compiled_partitions/lights.root_partition.map.cdb index 9d3cbf3..715b56d 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.map.cdb +++ b/incremental_db/compiled_partitions/lights.root_partition.map.cdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.dpi b/incremental_db/compiled_partitions/lights.root_partition.map.dpi index f89f5aa..4fa1f93 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.map.dpi +++ b/incremental_db/compiled_partitions/lights.root_partition.map.dpi Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.cdb index 7d769ac..ba9ddbf 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.cdb +++ b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.cdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hdb index 6406ae7..2eacc54 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hdb +++ b/incremental_db/compiled_partitions/lights.root_partition.map.hbdb.hdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.hdb b/incremental_db/compiled_partitions/lights.root_partition.map.hdb index 21fe60d..bd3d356 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.map.hdb +++ b/incremental_db/compiled_partitions/lights.root_partition.map.hdb Binary files differ diff --git a/incremental_db/compiled_partitions/lights.root_partition.map.kpt b/incremental_db/compiled_partitions/lights.root_partition.map.kpt index c3e7ea2..9cf8527 100644 --- a/incremental_db/compiled_partitions/lights.root_partition.map.kpt +++ b/incremental_db/compiled_partitions/lights.root_partition.map.kpt Binary files differ diff --git a/lights.qsf b/lights.qsf index 3254d51..33167d9 100644 --- a/lights.qsf +++ b/lights.qsf @@ -1,1107 +1,1107 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 15:50:27 October 13, 2016 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# lights_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name TOP_LEVEL_ENTITY lights -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:50:27 OCTOBER 13, 2016" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_location_assignment PIN_D2 -to AUD_ADCDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -set_location_assignment PIN_C2 -to AUD_ADCLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -set_location_assignment PIN_F2 -to AUD_BCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -set_location_assignment PIN_D1 -to AUD_DACDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -set_location_assignment PIN_E3 -to AUD_DACLRCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -set_location_assignment PIN_E1 -to AUD_XCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK -set_location_assignment PIN_AG14 -to CLOCK2_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 -set_location_assignment PIN_AG15 -to CLOCK3_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 -set_location_assignment PIN_Y2 -to CLOCK_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 -set_location_assignment PIN_Y7 -to DRAM_ADDR[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] -set_location_assignment PIN_AA5 -to DRAM_ADDR[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] -set_location_assignment PIN_R5 -to DRAM_ADDR[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] -set_location_assignment PIN_Y6 -to DRAM_ADDR[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] -set_location_assignment PIN_Y5 -to DRAM_ADDR[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] -set_location_assignment PIN_AA7 -to DRAM_ADDR[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] -set_location_assignment PIN_W7 -to DRAM_ADDR[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] -set_location_assignment PIN_W8 -to DRAM_ADDR[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] -set_location_assignment PIN_V5 -to DRAM_ADDR[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] -set_location_assignment PIN_P1 -to DRAM_ADDR[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] -set_location_assignment PIN_U8 -to DRAM_ADDR[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] -set_location_assignment PIN_V8 -to DRAM_ADDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] -set_location_assignment PIN_R6 -to DRAM_ADDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] -set_location_assignment PIN_R4 -to DRAM_BA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] -set_location_assignment PIN_U7 -to DRAM_BA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] -set_location_assignment PIN_V7 -to DRAM_CAS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N -set_location_assignment PIN_AA6 -to DRAM_CKE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE -set_location_assignment PIN_AE5 -to DRAM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK -set_location_assignment PIN_T4 -to DRAM_CS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N -set_location_assignment PIN_U1 -to DRAM_DQ[31] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] -set_location_assignment PIN_U4 -to DRAM_DQ[30] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] -set_location_assignment PIN_T3 -to DRAM_DQ[29] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] -set_location_assignment PIN_R3 -to DRAM_DQ[28] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] -set_location_assignment PIN_R2 -to DRAM_DQ[27] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] -set_location_assignment PIN_R1 -to DRAM_DQ[26] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] -set_location_assignment PIN_R7 -to DRAM_DQ[25] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] -set_location_assignment PIN_U5 -to DRAM_DQ[24] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] -set_location_assignment PIN_L7 -to DRAM_DQ[23] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] -set_location_assignment PIN_M7 -to DRAM_DQ[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] -set_location_assignment PIN_M4 -to DRAM_DQ[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] -set_location_assignment PIN_N4 -to DRAM_DQ[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] -set_location_assignment PIN_N3 -to DRAM_DQ[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] -set_location_assignment PIN_P2 -to DRAM_DQ[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] -set_location_assignment PIN_L8 -to DRAM_DQ[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] -set_location_assignment PIN_M8 -to DRAM_DQ[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] -set_location_assignment PIN_AC2 -to DRAM_DQ[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] -set_location_assignment PIN_AB3 -to DRAM_DQ[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] -set_location_assignment PIN_AC1 -to DRAM_DQ[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] -set_location_assignment PIN_AB2 -to DRAM_DQ[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] -set_location_assignment PIN_AA3 -to DRAM_DQ[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] -set_location_assignment PIN_AB1 -to DRAM_DQ[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] -set_location_assignment PIN_Y4 -to DRAM_DQ[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] -set_location_assignment PIN_Y3 -to DRAM_DQ[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] -set_location_assignment PIN_U3 -to DRAM_DQ[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] -set_location_assignment PIN_V1 -to DRAM_DQ[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] -set_location_assignment PIN_V2 -to DRAM_DQ[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] -set_location_assignment PIN_V3 -to DRAM_DQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] -set_location_assignment PIN_W1 -to DRAM_DQ[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] -set_location_assignment PIN_V4 -to DRAM_DQ[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] -set_location_assignment PIN_W2 -to DRAM_DQ[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] -set_location_assignment PIN_W3 -to DRAM_DQ[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] -set_location_assignment PIN_N8 -to DRAM_DQM[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] -set_location_assignment PIN_K8 -to DRAM_DQM[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] -set_location_assignment PIN_W4 -to DRAM_DQM[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] -set_location_assignment PIN_U2 -to DRAM_DQM[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] -set_location_assignment PIN_U6 -to DRAM_RAS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N -set_location_assignment PIN_V6 -to DRAM_WE_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N -set_location_assignment PIN_D14 -to EEP_I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK -set_location_assignment PIN_E14 -to EEP_I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT -set_location_assignment PIN_A17 -to ENET0_GTX_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK -set_location_assignment PIN_A21 -to ENET0_INT_N -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N -set_location_assignment PIN_C14 -to ENET0_LINK100 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 -set_location_assignment PIN_C20 -to ENET0_MDC -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC -set_location_assignment PIN_B21 -to ENET0_MDIO -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO -set_location_assignment PIN_C19 -to ENET0_RST_N -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N -set_location_assignment PIN_A15 -to ENET0_RX_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK -set_location_assignment PIN_E15 -to ENET0_RX_COL -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL -set_location_assignment PIN_D15 -to ENET0_RX_CRS -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS -set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] -set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] -set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] -set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] -set_location_assignment PIN_C17 -to ENET0_RX_DV -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV -set_location_assignment PIN_D18 -to ENET0_RX_ER -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER -set_location_assignment PIN_B17 -to ENET0_TX_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK -set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] -set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] -set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] -set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] -set_location_assignment PIN_A18 -to ENET0_TX_EN -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN -set_location_assignment PIN_B18 -to ENET0_TX_ER -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER -set_location_assignment PIN_C23 -to ENET1_GTX_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK -set_location_assignment PIN_D24 -to ENET1_INT_N -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N -set_location_assignment PIN_D13 -to ENET1_LINK100 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 -set_location_assignment PIN_D23 -to ENET1_MDC -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC -set_location_assignment PIN_D25 -to ENET1_MDIO -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO -set_location_assignment PIN_D22 -to ENET1_RST_N -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N -set_location_assignment PIN_B15 -to ENET1_RX_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK -set_location_assignment PIN_B22 -to ENET1_RX_COL -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL -set_location_assignment PIN_D20 -to ENET1_RX_CRS -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS -set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] -set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] -set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] -set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] -set_location_assignment PIN_A22 -to ENET1_RX_DV -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV -set_location_assignment PIN_C24 -to ENET1_RX_ER -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER -set_location_assignment PIN_C22 -to ENET1_TX_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK -set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] -set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] -set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] -set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] -set_location_assignment PIN_B25 -to ENET1_TX_EN -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN -set_location_assignment PIN_A25 -to ENET1_TX_ER -set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER -set_location_assignment PIN_A14 -to ENETCLK_25 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 -set_location_assignment PIN_D9 -to EX_IO[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] -set_location_assignment PIN_E10 -to EX_IO[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] -set_location_assignment PIN_F14 -to EX_IO[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] -set_location_assignment PIN_H14 -to EX_IO[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] -set_location_assignment PIN_H13 -to EX_IO[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] -set_location_assignment PIN_J14 -to EX_IO[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] -set_location_assignment PIN_J10 -to EX_IO[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] -set_location_assignment PIN_AD11 -to FL_ADDR[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] -set_location_assignment PIN_AD10 -to FL_ADDR[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] -set_location_assignment PIN_AE10 -to FL_ADDR[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] -set_location_assignment PIN_AD12 -to FL_ADDR[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] -set_location_assignment PIN_AC12 -to FL_ADDR[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] -set_location_assignment PIN_AH12 -to FL_ADDR[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] -set_location_assignment PIN_AA8 -to FL_ADDR[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] -set_location_assignment PIN_Y10 -to FL_ADDR[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] -set_location_assignment PIN_AC8 -to FL_ADDR[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] -set_location_assignment PIN_AD8 -to FL_ADDR[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] -set_location_assignment PIN_AA10 -to FL_ADDR[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] -set_location_assignment PIN_AF9 -to FL_ADDR[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] -set_location_assignment PIN_AE9 -to FL_ADDR[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] -set_location_assignment PIN_AB10 -to FL_ADDR[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] -set_location_assignment PIN_AB12 -to FL_ADDR[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] -set_location_assignment PIN_AB13 -to FL_ADDR[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] -set_location_assignment PIN_AA12 -to FL_ADDR[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] -set_location_assignment PIN_AA13 -to FL_ADDR[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] -set_location_assignment PIN_Y12 -to FL_ADDR[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] -set_location_assignment PIN_Y14 -to FL_ADDR[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] -set_location_assignment PIN_Y13 -to FL_ADDR[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] -set_location_assignment PIN_AH7 -to FL_ADDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] -set_location_assignment PIN_AG12 -to FL_ADDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] -set_location_assignment PIN_AG7 -to FL_CE_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N -set_location_assignment PIN_AF12 -to FL_DQ[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] -set_location_assignment PIN_AH11 -to FL_DQ[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] -set_location_assignment PIN_AG11 -to FL_DQ[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] -set_location_assignment PIN_AF11 -to FL_DQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] -set_location_assignment PIN_AH10 -to FL_DQ[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] -set_location_assignment PIN_AG10 -to FL_DQ[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] -set_location_assignment PIN_AF10 -to FL_DQ[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] -set_location_assignment PIN_AH8 -to FL_DQ[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] -set_location_assignment PIN_AG8 -to FL_OE_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N -set_location_assignment PIN_AE11 -to FL_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N -set_location_assignment PIN_Y1 -to FL_RY -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY -set_location_assignment PIN_AC10 -to FL_WE_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N -set_location_assignment PIN_AE12 -to FL_WP_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N -set_location_assignment PIN_AG26 -to GPIO[35] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] -set_location_assignment PIN_AH23 -to GPIO[34] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] -set_location_assignment PIN_AH26 -to GPIO[33] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] -set_location_assignment PIN_AF20 -to GPIO[32] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] -set_location_assignment PIN_AG23 -to GPIO[31] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] -set_location_assignment PIN_AE20 -to GPIO[30] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] -set_location_assignment PIN_AF26 -to GPIO[29] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] -set_location_assignment PIN_AH22 -to GPIO[28] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] -set_location_assignment PIN_AE24 -to GPIO[27] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] -set_location_assignment PIN_AG22 -to GPIO[26] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] -set_location_assignment PIN_AE25 -to GPIO[25] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] -set_location_assignment PIN_AH25 -to GPIO[24] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] -set_location_assignment PIN_AD25 -to GPIO[23] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] -set_location_assignment PIN_AG25 -to GPIO[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] -set_location_assignment PIN_AD22 -to GPIO[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] -set_location_assignment PIN_AF22 -to GPIO[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] -set_location_assignment PIN_AF21 -to GPIO[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] -set_location_assignment PIN_AE22 -to GPIO[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] -set_location_assignment PIN_AC22 -to GPIO[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] -set_location_assignment PIN_AF25 -to GPIO[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] -set_location_assignment PIN_AE21 -to GPIO[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] -set_location_assignment PIN_AF24 -to GPIO[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] -set_location_assignment PIN_AF15 -to GPIO[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] -set_location_assignment PIN_AD19 -to GPIO[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] -set_location_assignment PIN_AF16 -to GPIO[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] -set_location_assignment PIN_AC19 -to GPIO[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] -set_location_assignment PIN_AE15 -to GPIO[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] -set_location_assignment PIN_AD15 -to GPIO[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] -set_location_assignment PIN_AE16 -to GPIO[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] -set_location_assignment PIN_AD21 -to GPIO[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] -set_location_assignment PIN_Y16 -to GPIO[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] -set_location_assignment PIN_AC21 -to GPIO[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] -set_location_assignment PIN_Y17 -to GPIO[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] -set_location_assignment PIN_AB21 -to GPIO[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] -set_location_assignment PIN_AC15 -to GPIO[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] -set_location_assignment PIN_AB22 -to GPIO[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] -set_location_assignment PIN_H22 -to HEX0[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] -set_location_assignment PIN_J22 -to HEX0[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] -set_location_assignment PIN_L25 -to HEX0[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] -set_location_assignment PIN_L26 -to HEX0[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] -set_location_assignment PIN_E17 -to HEX0[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] -set_location_assignment PIN_F22 -to HEX0[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] -set_location_assignment PIN_G18 -to HEX0[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] -set_location_assignment PIN_U24 -to HEX1[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] -set_location_assignment PIN_U23 -to HEX1[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] -set_location_assignment PIN_W25 -to HEX1[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] -set_location_assignment PIN_W22 -to HEX1[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] -set_location_assignment PIN_W21 -to HEX1[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] -set_location_assignment PIN_Y22 -to HEX1[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] -set_location_assignment PIN_M24 -to HEX1[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] -set_location_assignment PIN_W28 -to HEX2[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] -set_location_assignment PIN_W27 -to HEX2[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] -set_location_assignment PIN_Y26 -to HEX2[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] -set_location_assignment PIN_W26 -to HEX2[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] -set_location_assignment PIN_Y25 -to HEX2[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] -set_location_assignment PIN_AA26 -to HEX2[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] -set_location_assignment PIN_AA25 -to HEX2[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] -set_location_assignment PIN_Y19 -to HEX3[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] -set_location_assignment PIN_AF23 -to HEX3[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] -set_location_assignment PIN_AD24 -to HEX3[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] -set_location_assignment PIN_AA21 -to HEX3[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] -set_location_assignment PIN_AB20 -to HEX3[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] -set_location_assignment PIN_U21 -to HEX3[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] -set_location_assignment PIN_V21 -to HEX3[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] -set_location_assignment PIN_AE18 -to HEX4[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] -set_location_assignment PIN_AF19 -to HEX4[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] -set_location_assignment PIN_AE19 -to HEX4[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] -set_location_assignment PIN_AH21 -to HEX4[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] -set_location_assignment PIN_AG21 -to HEX4[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] -set_location_assignment PIN_AA19 -to HEX4[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] -set_location_assignment PIN_AB19 -to HEX4[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] -set_location_assignment PIN_AH18 -to HEX5[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] -set_location_assignment PIN_AF18 -to HEX5[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] -set_location_assignment PIN_AG19 -to HEX5[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] -set_location_assignment PIN_AH19 -to HEX5[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] -set_location_assignment PIN_AB18 -to HEX5[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] -set_location_assignment PIN_AC18 -to HEX5[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] -set_location_assignment PIN_AD18 -to HEX5[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] -set_location_assignment PIN_AC17 -to HEX6[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] -set_location_assignment PIN_AA15 -to HEX6[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] -set_location_assignment PIN_AB15 -to HEX6[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] -set_location_assignment PIN_AB17 -to HEX6[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] -set_location_assignment PIN_AA16 -to HEX6[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] -set_location_assignment PIN_AB16 -to HEX6[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] -set_location_assignment PIN_AA17 -to HEX6[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] -set_location_assignment PIN_AA14 -to HEX7[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] -set_location_assignment PIN_AG18 -to HEX7[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] -set_location_assignment PIN_AF17 -to HEX7[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] -set_location_assignment PIN_AH17 -to HEX7[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] -set_location_assignment PIN_AG17 -to HEX7[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] -set_location_assignment PIN_AE17 -to HEX7[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] -set_location_assignment PIN_AD17 -to HEX7[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] -set_location_assignment PIN_AH15 -to HSMC_CLKIN0 -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 -set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 -set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 -set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 -set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 -set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 -set_location_assignment PIN_AF27 -to HSMC_D[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] -set_location_assignment PIN_AE27 -to HSMC_D[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] -set_location_assignment PIN_AE28 -to HSMC_D[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] -set_location_assignment PIN_AE26 -to HSMC_D[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] -set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] -set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] -set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] -set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] -set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] -set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] -set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] -set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] -set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] -set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] -set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] -set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] -set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] -set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] -set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] -set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] -set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] -set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] -set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] -set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] -set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] -set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] -set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] -set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] -set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] -set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] -set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] -set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] -set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] -set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] -set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] -set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] -set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] -set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] -set_location_assignment PIN_B7 -to I2C_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK -set_location_assignment PIN_A8 -to I2C_SDAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT -set_location_assignment PIN_Y15 -to IRDA_RXD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD -set_location_assignment PIN_R24 -to KEY[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] -set_location_assignment PIN_N21 -to KEY[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] -set_location_assignment PIN_M21 -to KEY[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] -set_location_assignment PIN_M23 -to KEY[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] -set_location_assignment PIN_L6 -to LCD_BLON -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON -set_location_assignment PIN_M5 -to LCD_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] -set_location_assignment PIN_M3 -to LCD_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] -set_location_assignment PIN_K2 -to LCD_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] -set_location_assignment PIN_K1 -to LCD_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] -set_location_assignment PIN_K7 -to LCD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] -set_location_assignment PIN_L2 -to LCD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] -set_location_assignment PIN_L1 -to LCD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] -set_location_assignment PIN_L3 -to LCD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] -set_location_assignment PIN_L4 -to LCD_EN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN -set_location_assignment PIN_L5 -to LCD_ON -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON -set_location_assignment PIN_M2 -to LCD_RS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS -set_location_assignment PIN_M1 -to LCD_RW -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW -set_location_assignment PIN_F17 -to LEDG[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] -set_location_assignment PIN_G21 -to LEDG[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] -set_location_assignment PIN_G22 -to LEDG[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] -set_location_assignment PIN_G20 -to LEDG[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] -set_location_assignment PIN_H21 -to LEDG[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] -set_location_assignment PIN_E24 -to LEDG[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] -set_location_assignment PIN_E25 -to LEDG[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] -set_location_assignment PIN_E22 -to LEDG[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] -set_location_assignment PIN_E21 -to LEDG[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] -set_location_assignment PIN_H15 -to LEDR[17] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] -set_location_assignment PIN_G16 -to LEDR[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] -set_location_assignment PIN_G15 -to LEDR[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] -set_location_assignment PIN_F15 -to LEDR[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] -set_location_assignment PIN_H17 -to LEDR[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] -set_location_assignment PIN_J16 -to LEDR[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] -set_location_assignment PIN_H16 -to LEDR[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] -set_location_assignment PIN_J15 -to LEDR[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] -set_location_assignment PIN_G17 -to LEDR[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] -set_location_assignment PIN_J17 -to LEDR[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] -set_location_assignment PIN_H19 -to LEDR[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] -set_location_assignment PIN_J19 -to LEDR[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] -set_location_assignment PIN_E18 -to LEDR[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] -set_location_assignment PIN_F18 -to LEDR[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] -set_location_assignment PIN_F21 -to LEDR[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] -set_location_assignment PIN_E19 -to LEDR[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] -set_location_assignment PIN_F19 -to LEDR[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] -set_location_assignment PIN_G19 -to LEDR[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] -set_location_assignment PIN_C3 -to OTG_ADDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] -set_location_assignment PIN_H7 -to OTG_ADDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] -set_location_assignment PIN_A3 -to OTG_CS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N -set_location_assignment PIN_D4 -to OTG_DACK_N[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1] -set_location_assignment PIN_C4 -to OTG_DACK_N[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0] -set_location_assignment PIN_G4 -to OTG_DATA[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] -set_location_assignment PIN_F3 -to OTG_DATA[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] -set_location_assignment PIN_F1 -to OTG_DATA[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] -set_location_assignment PIN_G3 -to OTG_DATA[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] -set_location_assignment PIN_G2 -to OTG_DATA[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] -set_location_assignment PIN_G1 -to OTG_DATA[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] -set_location_assignment PIN_H4 -to OTG_DATA[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] -set_location_assignment PIN_H3 -to OTG_DATA[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] -set_location_assignment PIN_H6 -to OTG_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] -set_location_assignment PIN_J7 -to OTG_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] -set_location_assignment PIN_J3 -to OTG_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] -set_location_assignment PIN_J4 -to OTG_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] -set_location_assignment PIN_K3 -to OTG_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] -set_location_assignment PIN_J5 -to OTG_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] -set_location_assignment PIN_K4 -to OTG_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] -set_location_assignment PIN_J6 -to OTG_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] -set_location_assignment PIN_B4 -to OTG_DREQ[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1] -set_location_assignment PIN_J1 -to OTG_DREQ[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0] -set_location_assignment PIN_C6 -to OTG_FSPEED -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED -set_location_assignment PIN_D5 -to OTG_INT[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1] -set_location_assignment PIN_A6 -to OTG_INT[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0] -set_location_assignment PIN_B6 -to OTG_LSPEED -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED -set_location_assignment PIN_B3 -to OTG_RD_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N -set_location_assignment PIN_C5 -to OTG_RST_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N -set_location_assignment PIN_A4 -to OTG_WR_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N -set_location_assignment PIN_G6 -to PS2_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK -set_location_assignment PIN_G5 -to PS2_CLK2 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 -set_location_assignment PIN_H5 -to PS2_DAT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT -set_location_assignment PIN_F5 -to PS2_DAT2 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 -set_location_assignment PIN_AE13 -to SD_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK -set_location_assignment PIN_AD14 -to SD_CMD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD -set_location_assignment PIN_AC14 -to SD_DAT[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] -set_location_assignment PIN_AB14 -to SD_DAT[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] -set_location_assignment PIN_AF13 -to SD_DAT[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] -set_location_assignment PIN_AE14 -to SD_DAT[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] -set_location_assignment PIN_AF14 -to SD_WP_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N -set_location_assignment PIN_AH14 -to SMA_CLKIN -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN -set_location_assignment PIN_AE23 -to SMA_CLKOUT -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT -set_location_assignment PIN_T8 -to SRAM_ADDR[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] -set_location_assignment PIN_AB8 -to SRAM_ADDR[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] -set_location_assignment PIN_AB9 -to SRAM_ADDR[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] -set_location_assignment PIN_AC11 -to SRAM_ADDR[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] -set_location_assignment PIN_AB11 -to SRAM_ADDR[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] -set_location_assignment PIN_AA4 -to SRAM_ADDR[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] -set_location_assignment PIN_AC3 -to SRAM_ADDR[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] -set_location_assignment PIN_AB4 -to SRAM_ADDR[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] -set_location_assignment PIN_AD3 -to SRAM_ADDR[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] -set_location_assignment PIN_AF2 -to SRAM_ADDR[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] -set_location_assignment PIN_T7 -to SRAM_ADDR[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] -set_location_assignment PIN_AF5 -to SRAM_ADDR[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] -set_location_assignment PIN_AC5 -to SRAM_ADDR[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] -set_location_assignment PIN_AB5 -to SRAM_ADDR[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] -set_location_assignment PIN_AE6 -to SRAM_ADDR[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] -set_location_assignment PIN_AB6 -to SRAM_ADDR[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] -set_location_assignment PIN_AC7 -to SRAM_ADDR[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] -set_location_assignment PIN_AE7 -to SRAM_ADDR[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] -set_location_assignment PIN_AD7 -to SRAM_ADDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] -set_location_assignment PIN_AB7 -to SRAM_ADDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] -set_location_assignment PIN_AF8 -to SRAM_CE_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N -set_location_assignment PIN_AG3 -to SRAM_DQ[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] -set_location_assignment PIN_AF3 -to SRAM_DQ[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] -set_location_assignment PIN_AE4 -to SRAM_DQ[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] -set_location_assignment PIN_AE3 -to SRAM_DQ[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] -set_location_assignment PIN_AE1 -to SRAM_DQ[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] -set_location_assignment PIN_AE2 -to SRAM_DQ[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] -set_location_assignment PIN_AD2 -to SRAM_DQ[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] -set_location_assignment PIN_AD1 -to SRAM_DQ[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] -set_location_assignment PIN_AF7 -to SRAM_DQ[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] -set_location_assignment PIN_AH6 -to SRAM_DQ[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] -set_location_assignment PIN_AG6 -to SRAM_DQ[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] -set_location_assignment PIN_AF6 -to SRAM_DQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] -set_location_assignment PIN_AH4 -to SRAM_DQ[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] -set_location_assignment PIN_AG4 -to SRAM_DQ[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] -set_location_assignment PIN_AF4 -to SRAM_DQ[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] -set_location_assignment PIN_AH3 -to SRAM_DQ[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] -set_location_assignment PIN_AD4 -to SRAM_LB_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N -set_location_assignment PIN_AD5 -to SRAM_OE_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N -set_location_assignment PIN_AC4 -to SRAM_UB_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N -set_location_assignment PIN_AE8 -to SRAM_WE_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N -set_location_assignment PIN_Y23 -to SW[17] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] -set_location_assignment PIN_Y24 -to SW[16] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] -set_location_assignment PIN_AA22 -to SW[15] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] -set_location_assignment PIN_AA23 -to SW[14] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] -set_location_assignment PIN_AA24 -to SW[13] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] -set_location_assignment PIN_AB23 -to SW[12] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] -set_location_assignment PIN_AB24 -to SW[11] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] -set_location_assignment PIN_AC24 -to SW[10] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] -set_location_assignment PIN_AB25 -to SW[9] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] -set_location_assignment PIN_AC25 -to SW[8] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] -set_location_assignment PIN_AB26 -to SW[7] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] -set_location_assignment PIN_AD26 -to SW[6] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] -set_location_assignment PIN_AC26 -to SW[5] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] -set_location_assignment PIN_AB27 -to SW[4] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] -set_location_assignment PIN_AD27 -to SW[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] -set_location_assignment PIN_AC27 -to SW[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] -set_location_assignment PIN_AC28 -to SW[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] -set_location_assignment PIN_AB28 -to SW[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] -set_location_assignment PIN_B14 -to TD_CLK27 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 -set_location_assignment PIN_F7 -to TD_DATA[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] -set_location_assignment PIN_E7 -to TD_DATA[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] -set_location_assignment PIN_D6 -to TD_DATA[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] -set_location_assignment PIN_D7 -to TD_DATA[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] -set_location_assignment PIN_C7 -to TD_DATA[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] -set_location_assignment PIN_D8 -to TD_DATA[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] -set_location_assignment PIN_A7 -to TD_DATA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] -set_location_assignment PIN_E8 -to TD_DATA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] -set_location_assignment PIN_E5 -to TD_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS -set_location_assignment PIN_G7 -to TD_RESET_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N -set_location_assignment PIN_E4 -to TD_VS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS -set_location_assignment PIN_G14 -to UART_CTS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS -set_location_assignment PIN_J13 -to UART_RTS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS -set_location_assignment PIN_G12 -to UART_RXD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD -set_location_assignment PIN_G9 -to UART_TXD -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD -set_location_assignment PIN_D12 -to VGA_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -set_location_assignment PIN_D11 -to VGA_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -set_location_assignment PIN_C12 -to VGA_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -set_location_assignment PIN_A11 -to VGA_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -set_location_assignment PIN_B11 -to VGA_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -set_location_assignment PIN_C11 -to VGA_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -set_location_assignment PIN_A10 -to VGA_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -set_location_assignment PIN_B10 -to VGA_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -set_location_assignment PIN_F11 -to VGA_BLANK_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N -set_location_assignment PIN_A12 -to VGA_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -set_location_assignment PIN_C9 -to VGA_G[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -set_location_assignment PIN_F10 -to VGA_G[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -set_location_assignment PIN_B8 -to VGA_G[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -set_location_assignment PIN_C8 -to VGA_G[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -set_location_assignment PIN_H12 -to VGA_G[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -set_location_assignment PIN_F8 -to VGA_G[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -set_location_assignment PIN_G11 -to VGA_G[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -set_location_assignment PIN_G8 -to VGA_G[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -set_location_assignment PIN_G13 -to VGA_HS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -set_location_assignment PIN_H10 -to VGA_R[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -set_location_assignment PIN_H8 -to VGA_R[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -set_location_assignment PIN_J12 -to VGA_R[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -set_location_assignment PIN_G10 -to VGA_R[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -set_location_assignment PIN_F12 -to VGA_R[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -set_location_assignment PIN_D10 -to VGA_R[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -set_location_assignment PIN_E11 -to VGA_R[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -set_location_assignment PIN_E12 -to VGA_R[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -set_location_assignment PIN_C10 -to VGA_SYNC_N -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N -set_location_assignment PIN_C13 -to VGA_VS -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS -set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 -set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 -set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] -set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] -set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] -set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] -set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] -set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] -set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] -set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] -set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] -set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] -set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] -set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] -set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] -set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] -set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] -set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] -set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] -set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] -set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] -set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] -set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] -set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] -set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] -set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] -set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] -set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] -set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] -set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] -set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] -set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] -set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] -set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] -set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] -set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] -set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 -set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 -set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 -set_global_assignment -name QSYS_FILE nios_system.qsys -set_global_assignment -name SOURCE_FILE nios_system.cmp -set_global_assignment -name VHDL_FILE lights.vhd -set_global_assignment -name VERILOG_FILE nios_system/synthesis/nios_system.v +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:50:27 October 13, 2016 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# lights_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY lights +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:50:27 OCTOBER 13, 2016" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_location_assignment PIN_E1 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 +set_location_assignment PIN_Y2 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_location_assignment PIN_T4 -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_location_assignment PIN_V6 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_location_assignment PIN_A21 -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 +set_location_assignment PIN_C20 -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO +set_location_assignment PIN_C19 -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_location_assignment PIN_D24 -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 +set_location_assignment PIN_D23 -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO +set_location_assignment PIN_D22 -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_location_assignment PIN_A14 -to ENETCLK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_location_assignment PIN_D9 -to EX_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] +set_location_assignment PIN_E10 -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_location_assignment PIN_F14 -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_location_assignment PIN_H14 -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_location_assignment PIN_H13 -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_location_assignment PIN_J14 -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_location_assignment PIN_J10 -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_location_assignment PIN_AG7 -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_location_assignment PIN_AG8 -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N +set_location_assignment PIN_AG26 -to GPIO[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_AH23 -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_location_assignment PIN_AH26 -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_location_assignment PIN_AF20 -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_location_assignment PIN_AG23 -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_location_assignment PIN_AE20 -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_location_assignment PIN_AF26 -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_location_assignment PIN_AH22 -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_location_assignment PIN_AE24 -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_location_assignment PIN_AG22 -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_location_assignment PIN_AE25 -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_location_assignment PIN_AH25 -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_location_assignment PIN_AD25 -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_location_assignment PIN_AG25 -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_location_assignment PIN_AD22 -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_location_assignment PIN_AF22 -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_location_assignment PIN_AF21 -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_location_assignment PIN_AE22 -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_location_assignment PIN_AC22 -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_location_assignment PIN_AF25 -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_location_assignment PIN_AE21 -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_location_assignment PIN_AF24 -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_location_assignment PIN_AF15 -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_location_assignment PIN_AD19 -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_location_assignment PIN_AF16 -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_location_assignment PIN_AC19 -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_location_assignment PIN_AE15 -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_location_assignment PIN_AD15 -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_location_assignment PIN_AE16 -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_location_assignment PIN_AD21 -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_location_assignment PIN_Y16 -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_location_assignment PIN_AC21 -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_location_assignment PIN_Y17 -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_location_assignment PIN_AB21 -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_location_assignment PIN_AC15 -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_location_assignment PIN_AB22 -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_location_assignment PIN_H22 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] +set_location_assignment PIN_J22 -to HEX0[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] +set_location_assignment PIN_L25 -to HEX0[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] +set_location_assignment PIN_L26 -to HEX0[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] +set_location_assignment PIN_E17 -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_location_assignment PIN_F22 -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_location_assignment PIN_G18 -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_location_assignment PIN_U24 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] +set_location_assignment PIN_U23 -to HEX1[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] +set_location_assignment PIN_W25 -to HEX1[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] +set_location_assignment PIN_W22 -to HEX1[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] +set_location_assignment PIN_W21 -to HEX1[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] +set_location_assignment PIN_Y22 -to HEX1[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] +set_location_assignment PIN_M24 -to HEX1[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] +set_location_assignment PIN_W28 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] +set_location_assignment PIN_W27 -to HEX2[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] +set_location_assignment PIN_Y26 -to HEX2[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] +set_location_assignment PIN_W26 -to HEX2[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] +set_location_assignment PIN_Y25 -to HEX2[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] +set_location_assignment PIN_AA26 -to HEX2[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] +set_location_assignment PIN_AA25 -to HEX2[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] +set_location_assignment PIN_Y19 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_location_assignment PIN_AF23 -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_location_assignment PIN_AD24 -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_location_assignment PIN_AA21 -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_location_assignment PIN_AB20 -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_location_assignment PIN_U21 -to HEX3[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] +set_location_assignment PIN_V21 -to HEX3[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] +set_location_assignment PIN_AE18 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_location_assignment PIN_AF19 -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_location_assignment PIN_AE19 -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_location_assignment PIN_AH21 -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_location_assignment PIN_AG21 -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_location_assignment PIN_AA19 -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_location_assignment PIN_AB19 -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_location_assignment PIN_AH18 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_location_assignment PIN_AF18 -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_location_assignment PIN_AG19 -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_location_assignment PIN_AH19 -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_location_assignment PIN_AB18 -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_location_assignment PIN_AC18 -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_location_assignment PIN_AD18 -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_location_assignment PIN_AC17 -to HEX6[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] +set_location_assignment PIN_AA15 -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_location_assignment PIN_AB15 -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_location_assignment PIN_AB17 -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_location_assignment PIN_AA16 -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_location_assignment PIN_AB16 -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_location_assignment PIN_AA17 -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_location_assignment PIN_AA14 -to HEX7[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] +set_location_assignment PIN_AG18 -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_location_assignment PIN_AF17 -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_location_assignment PIN_AH17 -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_location_assignment PIN_AG17 -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_location_assignment PIN_AE17 -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_location_assignment PIN_AD17 -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] +set_location_assignment PIN_B7 -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT +set_location_assignment PIN_Y15 -to IRDA_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD +set_location_assignment PIN_R24 -to KEY[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] +set_location_assignment PIN_N21 -to KEY[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] +set_location_assignment PIN_M21 -to KEY[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] +set_location_assignment PIN_M23 -to KEY[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] +set_location_assignment PIN_L6 -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_location_assignment PIN_L4 -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_location_assignment PIN_L5 -to LCD_ON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON +set_location_assignment PIN_M2 -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_location_assignment PIN_M1 -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_location_assignment PIN_F17 -to LEDG[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] +set_location_assignment PIN_G21 -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_location_assignment PIN_G22 -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_location_assignment PIN_G20 -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_location_assignment PIN_H21 -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_location_assignment PIN_E24 -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_location_assignment PIN_E25 -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_location_assignment PIN_E22 -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_location_assignment PIN_E21 -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_location_assignment PIN_H15 -to LEDR[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] +set_location_assignment PIN_G16 -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_location_assignment PIN_G15 -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_location_assignment PIN_F15 -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_location_assignment PIN_H17 -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_location_assignment PIN_J16 -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_location_assignment PIN_H16 -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_location_assignment PIN_J15 -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_location_assignment PIN_G17 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_location_assignment PIN_J17 -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_location_assignment PIN_H19 -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_location_assignment PIN_J19 -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_location_assignment PIN_E18 -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_location_assignment PIN_F18 -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_location_assignment PIN_F21 -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_location_assignment PIN_E19 -to LEDR[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_location_assignment PIN_F19 -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_location_assignment PIN_G19 -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_location_assignment PIN_D4 -to OTG_DACK_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1] +set_location_assignment PIN_C4 -to OTG_DACK_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_location_assignment PIN_B4 -to OTG_DREQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0] +set_location_assignment PIN_C6 -to OTG_FSPEED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED +set_location_assignment PIN_D5 -to OTG_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1] +set_location_assignment PIN_A6 -to OTG_INT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0] +set_location_assignment PIN_B6 -to OTG_LSPEED +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED +set_location_assignment PIN_B3 -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_location_assignment PIN_C5 -to OTG_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N +set_location_assignment PIN_G6 -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_location_assignment PIN_G5 -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_location_assignment PIN_H5 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_location_assignment PIN_F5 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 +set_location_assignment PIN_AE13 -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_location_assignment PIN_AF14 -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N +set_location_assignment PIN_Y23 -to SW[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] +set_location_assignment PIN_Y24 -to SW[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] +set_location_assignment PIN_AA22 -to SW[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] +set_location_assignment PIN_AA23 -to SW[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] +set_location_assignment PIN_AA24 -to SW[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] +set_location_assignment PIN_AB23 -to SW[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] +set_location_assignment PIN_AB24 -to SW[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] +set_location_assignment PIN_AC24 -to SW[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] +set_location_assignment PIN_AB25 -to SW[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] +set_location_assignment PIN_AC25 -to SW[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] +set_location_assignment PIN_AB26 -to SW[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] +set_location_assignment PIN_AD26 -to SW[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] +set_location_assignment PIN_AC26 -to SW[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] +set_location_assignment PIN_AB27 -to SW[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] +set_location_assignment PIN_AD27 -to SW[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] +set_location_assignment PIN_AC27 -to SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] +set_location_assignment PIN_AC28 -to SW[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] +set_location_assignment PIN_AB28 -to SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] +set_location_assignment PIN_B14 -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_location_assignment PIN_F7 -to TD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_location_assignment PIN_E8 -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_location_assignment PIN_E5 -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_location_assignment PIN_G7 -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_location_assignment PIN_E4 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_location_assignment PIN_G14 -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS +set_location_assignment PIN_G12 -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_location_assignment PIN_G9 -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_location_assignment PIN_D12 -to VGA_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] +set_location_assignment PIN_D11 -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_location_assignment PIN_C12 -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_location_assignment PIN_A11 -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_location_assignment PIN_B11 -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_location_assignment PIN_C11 -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_location_assignment PIN_A10 -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_location_assignment PIN_B10 -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_location_assignment PIN_A12 -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_location_assignment PIN_C9 -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_location_assignment PIN_F10 -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_location_assignment PIN_B8 -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_location_assignment PIN_C8 -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_location_assignment PIN_H12 -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_location_assignment PIN_F8 -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_location_assignment PIN_G11 -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_location_assignment PIN_G8 -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_location_assignment PIN_G13 -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_location_assignment PIN_H10 -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_location_assignment PIN_H8 -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_location_assignment PIN_J12 -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_location_assignment PIN_G10 -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_location_assignment PIN_F12 -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_location_assignment PIN_D10 -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_location_assignment PIN_E11 -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_location_assignment PIN_E12 -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_location_assignment PIN_C13 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 +set_global_assignment -name QSYS_FILE nios_system.qsys +set_global_assignment -name SOURCE_FILE nios_system.cmp +set_global_assignment -name VHDL_FILE lights.vhd +set_global_assignment -name VERILOG_FILE nios_system/synthesis/nios_system.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/nios_system.bsf b/nios_system.bsf index b495623..dac37b1 100644 --- a/nios_system.bsf +++ b/nios_system.bsf @@ -1,248 +1,248 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 384 792) - (text "nios_system" (rect 155 -1 206 11)(font "Arial" (font_size 10))) - (text "inst" (rect 8 776 20 788)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) - (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 160 72)(line_width 1)) - ) - (port - (pt 0 152) - (input) - (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) - (text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 160 152)(line_width 1)) - ) - (port - (pt 0 232) - (input) - (text "switches_export[17..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) - (text "switches_export[17..0]" (rect 4 221 136 232)(font "Arial" (font_size 8))) - (line (pt 0 232)(pt 160 232)(line_width 3)) - ) - (port - (pt 0 272) - (input) - (text "push_switches_export[2..0]" (rect 0 0 108 12)(font "Arial" (font_size 8))) - (text "push_switches_export[2..0]" (rect 4 261 160 272)(font "Arial" (font_size 8))) - (line (pt 0 272)(pt 160 272)(line_width 3)) - ) - (port - (pt 0 112) - (output) - (text "leds_export[7..0]" (rect 0 0 66 12)(font "Arial" (font_size 8))) - (text "leds_export[7..0]" (rect 4 101 106 112)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 160 112)(line_width 3)) - ) - (port - (pt 0 192) - (output) - (text "ledrs_export[17..0]" (rect 0 0 73 12)(font "Arial" (font_size 8))) - (text "ledrs_export[17..0]" (rect 4 181 118 192)(font "Arial" (font_size 8))) - (line (pt 0 192)(pt 160 192)(line_width 3)) - ) - (port - (pt 0 312) - (output) - (text "hex0_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) - (text "hex0_export[6..0]" (rect 4 301 106 312)(font "Arial" (font_size 8))) - (line (pt 0 312)(pt 160 312)(line_width 3)) - ) - (port - (pt 0 352) - (output) - (text "hex1_export[6..0]" (rect 0 0 68 12)(font "Arial" (font_size 8))) - (text "hex1_export[6..0]" (rect 4 341 106 352)(font "Arial" (font_size 8))) - (line (pt 0 352)(pt 160 352)(line_width 3)) - ) - (port - (pt 0 392) - (output) - (text "hex2_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) - (text "hex2_export[6..0]" (rect 4 381 106 392)(font "Arial" (font_size 8))) - (line (pt 0 392)(pt 160 392)(line_width 3)) - ) - (port - (pt 0 432) - (output) - (text "hex3_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) - (text "hex3_export[6..0]" (rect 4 421 106 432)(font "Arial" (font_size 8))) - (line (pt 0 432)(pt 160 432)(line_width 3)) - ) - (port - (pt 0 472) - (output) - (text "hex4_export[6..0]" (rect 0 0 70 12)(font "Arial" (font_size 8))) - (text "hex4_export[6..0]" (rect 4 461 106 472)(font "Arial" (font_size 8))) - (line (pt 0 472)(pt 160 472)(line_width 3)) - ) - (port - (pt 0 512) - (output) - (text "hex5_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) - (text "hex5_export[6..0]" (rect 4 501 106 512)(font "Arial" (font_size 8))) - (line (pt 0 512)(pt 160 512)(line_width 3)) - ) - (port - (pt 0 552) - (output) - (text "hex6_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) - (text "hex6_export[6..0]" (rect 4 541 106 552)(font "Arial" (font_size 8))) - (line (pt 0 552)(pt 160 552)(line_width 3)) - ) - (port - (pt 0 592) - (output) - (text "hex7_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) - (text "hex7_export[6..0]" (rect 4 581 106 592)(font "Arial" (font_size 8))) - (line (pt 0 592)(pt 160 592)(line_width 3)) - ) - (port - (pt 0 632) - (output) - (text "lcd_16207_0_RS" (rect 0 0 69 12)(font "Arial" (font_size 8))) - (text "lcd_16207_0_RS" (rect 4 621 88 632)(font "Arial" (font_size 8))) - (line (pt 0 632)(pt 160 632)(line_width 1)) - ) - (port - (pt 0 648) - (output) - (text "lcd_16207_0_RW" (rect 0 0 74 12)(font "Arial" (font_size 8))) - (text "lcd_16207_0_RW" (rect 4 637 88 648)(font "Arial" (font_size 8))) - (line (pt 0 648)(pt 160 648)(line_width 1)) - ) - (port - (pt 0 680) - (output) - (text "lcd_16207_0_E" (rect 0 0 62 12)(font "Arial" (font_size 8))) - (text "lcd_16207_0_E" (rect 4 669 82 680)(font "Arial" (font_size 8))) - (line (pt 0 680)(pt 160 680)(line_width 1)) - ) - (port - (pt 0 720) - (output) - (text "lcd_on_export" (rect 0 0 56 12)(font "Arial" (font_size 8))) - (text "lcd_on_export" (rect 4 709 82 720)(font "Arial" (font_size 8))) - (line (pt 0 720)(pt 160 720)(line_width 1)) - ) - (port - (pt 0 760) - (output) - (text "lcd_blon_export" (rect 0 0 62 12)(font "Arial" (font_size 8))) - (text "lcd_blon_export" (rect 4 749 94 760)(font "Arial" (font_size 8))) - (line (pt 0 760)(pt 160 760)(line_width 1)) - ) - (port - (pt 0 664) - (bidir) - (text "lcd_16207_0_data[7..0]" (rect 0 0 92 12)(font "Arial" (font_size 8))) - (text "lcd_16207_0_data[7..0]" (rect 4 653 136 664)(font "Arial" (font_size 8))) - (line (pt 0 664)(pt 160 664)(line_width 3)) - ) - (drawing - (text "clk" (rect 145 43 308 99)(font "Arial" (color 128 0 0)(font_size 9))) - (text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0))) - (text "leds" (rect 137 83 298 179)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 107 366 224)(font "Arial" (color 0 0 0))) - (text "reset" (rect 131 123 292 259)(font "Arial" (color 128 0 0)(font_size 9))) - (text "reset_n" (rect 165 147 372 304)(font "Arial" (color 0 0 0))) - (text "ledrs" (rect 132 163 294 339)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 187 366 384)(font "Arial" (color 0 0 0))) - (text "switches" (rect 110 203 268 419)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 227 366 464)(font "Arial" (color 0 0 0))) - (text "push_switches" (rect 74 243 226 499)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 267 366 544)(font "Arial" (color 0 0 0))) - (text "hex0" (rect 134 283 292 579)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 307 366 624)(font "Arial" (color 0 0 0))) - (text "hex1" (rect 136 323 296 659)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 347 366 704)(font "Arial" (color 0 0 0))) - (text "hex2" (rect 134 363 292 739)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 387 366 784)(font "Arial" (color 0 0 0))) - (text "hex3" (rect 134 403 292 819)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 427 366 864)(font "Arial" (color 0 0 0))) - (text "hex4" (rect 134 443 292 899)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 467 366 944)(font "Arial" (color 0 0 0))) - (text "hex5" (rect 134 483 292 979)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 507 366 1024)(font "Arial" (color 0 0 0))) - (text "hex6" (rect 134 523 292 1059)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 547 366 1104)(font "Arial" (color 0 0 0))) - (text "hex7" (rect 134 563 292 1139)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 587 366 1184)(font "Arial" (color 0 0 0))) - (text "lcd_16207_0" (rect 89 603 244 1219)(font "Arial" (color 128 0 0)(font_size 9))) - (text "RS" (rect 165 627 342 1264)(font "Arial" (color 0 0 0))) - (text "RW" (rect 165 643 342 1296)(font "Arial" (color 0 0 0))) - (text "data" (rect 165 659 354 1328)(font "Arial" (color 0 0 0))) - (text "E" (rect 165 675 336 1360)(font "Arial" (color 0 0 0))) - (text "lcd_on" (rect 123 691 282 1395)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 715 366 1440)(font "Arial" (color 0 0 0))) - (text "lcd_blon" (rect 113 731 274 1475)(font "Arial" (color 128 0 0)(font_size 9))) - (text "export" (rect 165 755 366 1520)(font "Arial" (color 0 0 0))) - (text " nios_system " (rect 326 776 730 1562)(font "Arial" )) - (line (pt 161 52)(pt 161 76)(line_width 1)) - (line (pt 162 52)(pt 162 76)(line_width 1)) - (line (pt 161 92)(pt 161 116)(line_width 1)) - (line (pt 162 92)(pt 162 116)(line_width 1)) - (line (pt 161 132)(pt 161 156)(line_width 1)) - (line (pt 162 132)(pt 162 156)(line_width 1)) - (line (pt 161 172)(pt 161 196)(line_width 1)) - (line (pt 162 172)(pt 162 196)(line_width 1)) - (line (pt 161 212)(pt 161 236)(line_width 1)) - (line (pt 162 212)(pt 162 236)(line_width 1)) - (line (pt 161 252)(pt 161 276)(line_width 1)) - (line (pt 162 252)(pt 162 276)(line_width 1)) - (line (pt 161 292)(pt 161 316)(line_width 1)) - (line (pt 162 292)(pt 162 316)(line_width 1)) - (line (pt 161 332)(pt 161 356)(line_width 1)) - (line (pt 162 332)(pt 162 356)(line_width 1)) - (line (pt 161 372)(pt 161 396)(line_width 1)) - (line (pt 162 372)(pt 162 396)(line_width 1)) - (line (pt 161 412)(pt 161 436)(line_width 1)) - (line (pt 162 412)(pt 162 436)(line_width 1)) - (line (pt 161 452)(pt 161 476)(line_width 1)) - (line (pt 162 452)(pt 162 476)(line_width 1)) - (line (pt 161 492)(pt 161 516)(line_width 1)) - (line (pt 162 492)(pt 162 516)(line_width 1)) - (line (pt 161 532)(pt 161 556)(line_width 1)) - (line (pt 162 532)(pt 162 556)(line_width 1)) - (line (pt 161 572)(pt 161 596)(line_width 1)) - (line (pt 162 572)(pt 162 596)(line_width 1)) - (line (pt 161 612)(pt 161 684)(line_width 1)) - (line (pt 162 612)(pt 162 684)(line_width 1)) - (line (pt 161 700)(pt 161 724)(line_width 1)) - (line (pt 162 700)(pt 162 724)(line_width 1)) - (line (pt 161 740)(pt 161 764)(line_width 1)) - (line (pt 162 740)(pt 162 764)(line_width 1)) - (line (pt 160 32)(pt 224 32)(line_width 1)) - (line (pt 224 32)(pt 224 776)(line_width 1)) - (line (pt 160 776)(pt 224 776)(line_width 1)) - (line (pt 160 32)(pt 160 776)(line_width 1)) - (line (pt 0 0)(pt 384 0)(line_width 1)) - (line (pt 384 0)(pt 384 792)(line_width 1)) - (line (pt 0 792)(pt 384 792)(line_width 1)) - (line (pt 0 0)(pt 0 792)(line_width 1)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 384 792) + (text "nios_system" (rect 155 -1 206 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 776 20 788)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 160 72)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 160 152)(line_width 1)) + ) + (port + (pt 0 232) + (input) + (text "switches_export[17..0]" (rect 0 0 87 12)(font "Arial" (font_size 8))) + (text "switches_export[17..0]" (rect 4 221 136 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 160 232)(line_width 3)) + ) + (port + (pt 0 272) + (input) + (text "push_switches_export[2..0]" (rect 0 0 108 12)(font "Arial" (font_size 8))) + (text "push_switches_export[2..0]" (rect 4 261 160 272)(font "Arial" (font_size 8))) + (line (pt 0 272)(pt 160 272)(line_width 3)) + ) + (port + (pt 0 112) + (output) + (text "leds_export[7..0]" (rect 0 0 66 12)(font "Arial" (font_size 8))) + (text "leds_export[7..0]" (rect 4 101 106 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 160 112)(line_width 3)) + ) + (port + (pt 0 192) + (output) + (text "ledrs_export[17..0]" (rect 0 0 73 12)(font "Arial" (font_size 8))) + (text "ledrs_export[17..0]" (rect 4 181 118 192)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 160 192)(line_width 3)) + ) + (port + (pt 0 312) + (output) + (text "hex0_export[6..0]" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "hex0_export[6..0]" (rect 4 301 106 312)(font "Arial" (font_size 8))) + (line (pt 0 312)(pt 160 312)(line_width 3)) + ) + (port + (pt 0 352) + (output) + (text "hex1_export[6..0]" (rect 0 0 68 12)(font "Arial" (font_size 8))) + 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9))) + (text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0))) + (text "leds" (rect 137 83 298 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 107 366 224)(font "Arial" (color 0 0 0))) + (text "reset" (rect 131 123 292 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 165 147 372 304)(font "Arial" (color 0 0 0))) + (text "ledrs" (rect 132 163 294 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 187 366 384)(font "Arial" (color 0 0 0))) + (text "switches" (rect 110 203 268 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 227 366 464)(font "Arial" (color 0 0 0))) + (text "push_switches" (rect 74 243 226 499)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 267 366 544)(font "Arial" (color 0 0 0))) + (text "hex0" (rect 134 283 292 579)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 165 307 366 624)(font "Arial" (color 0 0 0))) + (text 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2016.12.02.01:19:322016.12.22.10:06:15 Datasheet
@@ -4855,7 +4855,7 @@ - +
generation took 0.00 secondsrendering took 0.15 secondsrendering took 0.17 seconds
diff --git a/nios_system.sopcinfo b/nios_system.sopcinfo index a899da0..100a9b4 100644 --- a/nios_system.sopcinfo +++ b/nios_system.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1480609931 + 1482368837 false true false @@ -18031,22 +18031,6 @@ 1 - nios_custom_instruction_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Custom Instruction Master - 13.0 - - - 14 - altera_avalon_pio - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - PIO (Parallel I/O) - 13.0.1.99.2 - - - 1 altera_avalon_onchip_memory2 com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule @@ -18054,51 +18038,27 @@ 13.0.1.99.2 - 18 - clock + 15 + conduit_end com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit 13.0 1 - reset_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output - 13.0 - - - 2 - avalon_master - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Master - 13.0 - - - 20 - avalon - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection - 13.0 - - - 1 - interrupt_sender - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender - 13.0 - - - 1 - clock_source + altera_avalon_jtag_uart com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - Clock Source + JTAG UART + 13.0.1.99.2 + + + 36 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection 13.0 @@ -18111,37 +18071,29 @@ 1 - reset_source + interrupt_receiver com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output + Interrupt Receiver 13.0 - 1 - clock_source - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output - 13.0 - - - 1 - altera_avalon_jtag_uart - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - JTAG UART - 13.0.1.99.2 - - - 1 - interrupt + 18 + clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection - Interrupt Connection + Clock Connection 13.0 + 14 + altera_avalon_pio + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + PIO (Parallel I/O) + 13.0.1.99.2 + + 1 clock_sink com.altera.entityinterfaces.IElementClass @@ -18150,35 +18102,11 @@ 13.0 - 15 - conduit_end - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit - 13.0 - - - 18 - reset_sink - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 13.0 - - 1 - interrupt_receiver + nios_custom_instruction_master com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver - 13.0 - - - 36 - reset - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Reset Connection + Custom Instruction Master 13.0 @@ -18191,6 +18119,22 @@ 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.0 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 13.0 + + + 1 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -18198,6 +18142,46 @@ 13.0 + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 13.0 + + + 1 + altera_avalon_lcd_16207 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Altera Avalon LCD 16207 + 13.0.1.99.2 + + + 2 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 13.0 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 13.0 + + + 1 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 13.0 + + 18 clock_sink com.altera.entityinterfaces.IElementClass @@ -18207,11 +18191,27 @@ 1 - altera_avalon_lcd_16207 + clock_source com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Altera Avalon LCD 16207 - 13.0.1.99.2 + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 13.0 + + + 18 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 13.0 + + + 20 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 13.0 13.0sp1 232 diff --git a/nios_system/synthesis/nios_system.qip b/nios_system/synthesis/nios_system.qip index 239526d..76e2e7b 100644 --- a/nios_system/synthesis/nios_system.qip +++ b/nios_system/synthesis/nios_system.qip @@ -2,7 +2,7 @@ set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_VERSION "13.0sp1" set_global_assignment -entity "nios_system" -library "nios_system" -name IP_TOOL_ENV "Qsys" set_global_assignment -library "nios_system" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../nios_system.sopcinfo"] -set_instance_assignment -entity "nios_system" -library "nios_system" -name SLD_INFO "QSYS_NAME nios_system HAS_SOPCINFO 1 GENERATION_ID 1480609171" +set_instance_assignment -entity "nios_system" -library "nios_system" -name SLD_INFO "QSYS_NAME nios_system HAS_SOPCINFO 1 GENERATION_ID 1482368774" set_global_assignment -library "nios_system" -name MISC_FILE [file join $::quartus(qip_path) "../../nios_system.cmp"] set_global_assignment -name SYNTHESIS_ONLY_QIP ON set_global_assignment -library "nios_system" -name MISC_FILE [file join $::quartus(qip_path) "../../nios_system.qsys"] diff --git a/nios_system/synthesis/nios_system.v b/nios_system/synthesis/nios_system.v index 3044723..4626fed 100644 --- a/nios_system/synthesis/nios_system.v +++ b/nios_system/synthesis/nios_system.v @@ -1,9 +1,9 @@ -// nios_system.v - -// Generated using ACDS version 13.0sp1 232 at 2016.12.02.01:19:35 - +// nios_system.v + +// Generated using ACDS version 13.0sp1 232 at 2016.12.22.10:06:19 + `timescale 1 ps / 1 ps -module nios_system ( +module nios_system ( input wire clk_clk, // clk.clk output wire [7:0] leds_export, // leds.export input wire reset_reset_n, // reset.reset_n @@ -24,1056 +24,1056 @@ output wire lcd_16207_0_E, // .E output wire lcd_on_export, // lcd_on.export output wire lcd_blon_export // lcd_blon.export - ); - - wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest - wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address - wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read - wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata - wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest - wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata - wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address - wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write - wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read - wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata - wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess - wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata - wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata - wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address - wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect - wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken - wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write - wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata - wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable - wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata - wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address - wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect - wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n - wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata - wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n - wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata - wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address - wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect - wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n - wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata - wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address - wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata - wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address - wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata - wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address - wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect - wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n - wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata - wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address - wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect - wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n - wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata - wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address - wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect - wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n - wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata - wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address - wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect - wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n - wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata - wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address - wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect - wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n - wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata - wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address - wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect - wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n - wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata - wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address - wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect - wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n - wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata - wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address - wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect - wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n - wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata - wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read - wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata - wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata - wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address - wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect - wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n - wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata - wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address - wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect - wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n - wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest - wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid - wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest - wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata - wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address - wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock - wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write - wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read - wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata - wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess - wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable - wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata - wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read - wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess - wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata - wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read - wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess - wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata - wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read - wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess - wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata - wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read - wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess - wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata - wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read - wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess - wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata - wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read - wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess - wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata - wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read - wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess - wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata - wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read - wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess - wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata - wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read - wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess - wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata - wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read - wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess - wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata - wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read - wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess - wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata - wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read - wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess - wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata - wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read - wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess - wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata - wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read - wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess - wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata - wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read - wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess - wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata - wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read - wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess - wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata - wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read - wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess - wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest - wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata - wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read - wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess - wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket - wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid - wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket - wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data - wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket - wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data - wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket - wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data - wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket - wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data - wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket - wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data - wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket - wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data - wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket - wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data - wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket - wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data - wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket - wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data - wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket - wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data - wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket - wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data - wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket - wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data - wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket - wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data - wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket - wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data - wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket - wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data - wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket - wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data - wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket - wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data - wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket - wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data - wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket - wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data - wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket - wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data - wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready - wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] - wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req - wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 - wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket - wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid - wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data - wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel - wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready - wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket - wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid - wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket - wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data - wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel - wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready - wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket - wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid - wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data - wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel - wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready - wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket - wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid - wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket - wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data - wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel - wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready - wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket - wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid - wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data - wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel - wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready - wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket - wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid - wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket - wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data - wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel - wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready - wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket - wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid - wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data - wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel - wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready - wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket - wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid - wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket - wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data - wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel - wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready - wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket - wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid - wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket - wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data - wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel - wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready - wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket - wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid - wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket - wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data - wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel - wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready - wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket - wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid - wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket - wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data - wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel - wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready - wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket - wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid - wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket - wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data - wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel - wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready - wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket - wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid - wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket - wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data - wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel - wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready - wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket - wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid - wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket - wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data - wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel - wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready - wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket - wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid - wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket - wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data - wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel - wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready - wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket - wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid - wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket - wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data - wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel - wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready - wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket - wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid - wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket - wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data - wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel - wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready - wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket - wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid - wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket - wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data - wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel - wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready - wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket - wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid - wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket - wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data - wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel - wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready - wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket - wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid - wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket - wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data - wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel - wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready - wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket - wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid - wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket - wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data - wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel - wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready - wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket - wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid - wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket - wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data - wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel - wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready - wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket - wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid - wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket - wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data - wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel - wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready - wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket - wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid - wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket - wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data - wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel - wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready - wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket - wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid - wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket - wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data - wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel - wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready - wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready - wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket - wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid - wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket - wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data - wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel - wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready - wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket - wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid - wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket - wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data - wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel - wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready - wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready - wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket - wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid - wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket - wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data - wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel - wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready - wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket - wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid - wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket - wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data - wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel - wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready - wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket - wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid - wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket - wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data - wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel - wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready - wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready - wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket - wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid - wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket - wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data - wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel - wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready - wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready - wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket - wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid - wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket - wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data - wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel - wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready - wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready - wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket - wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid - wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket - wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data - wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel - wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready - wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready - wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket - wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid - wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket - wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data - wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel - wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready - wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready - wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket - wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid - wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket - wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data - wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel - wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready - wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready - wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket - wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid - wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket - wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data - wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel - wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready - wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready - wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket - wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid - wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket - wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data - wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel - wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready - wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready - wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket - wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid - wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket - wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data - wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel - wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready - wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready - wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket - wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid - wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket - wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data - wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel - wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready - wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready - wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket - wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid - wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket - wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data - wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel - wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready - wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready - wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket - wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid - wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket - wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data - wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel - wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready - wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready - wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket - wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid - wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket - wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data - wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel - wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready - wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready - wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket - wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid - wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket - wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data - wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel - wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready - wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready - wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket - wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid - wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket - wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data - wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel - wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready - wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready - wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket - wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid - wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket - wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data - wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel - wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready - wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready - wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket - wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid - wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket - wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data - wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel - wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready - wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq - wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq - + ); + + wire nios2_processor_instruction_master_waitrequest; // nios2_processor_instruction_master_translator:av_waitrequest -> nios2_processor:i_waitrequest + wire [18:0] nios2_processor_instruction_master_address; // nios2_processor:i_address -> nios2_processor_instruction_master_translator:av_address + wire nios2_processor_instruction_master_read; // nios2_processor:i_read -> nios2_processor_instruction_master_translator:av_read + wire [31:0] nios2_processor_instruction_master_readdata; // nios2_processor_instruction_master_translator:av_readdata -> nios2_processor:i_readdata + wire nios2_processor_data_master_waitrequest; // nios2_processor_data_master_translator:av_waitrequest -> nios2_processor:d_waitrequest + wire [31:0] nios2_processor_data_master_writedata; // nios2_processor:d_writedata -> nios2_processor_data_master_translator:av_writedata + wire [18:0] nios2_processor_data_master_address; // nios2_processor:d_address -> nios2_processor_data_master_translator:av_address + wire nios2_processor_data_master_write; // nios2_processor:d_write -> nios2_processor_data_master_translator:av_write + wire nios2_processor_data_master_read; // nios2_processor:d_read -> nios2_processor_data_master_translator:av_read + wire [31:0] nios2_processor_data_master_readdata; // nios2_processor_data_master_translator:av_readdata -> nios2_processor:d_readdata + wire nios2_processor_data_master_debugaccess; // nios2_processor:jtag_debug_module_debugaccess_to_roms -> nios2_processor_data_master_translator:av_debugaccess + wire [3:0] nios2_processor_data_master_byteenable; // nios2_processor:d_byteenable -> nios2_processor_data_master_translator:av_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_processor:jtag_debug_module_waitrequest -> nios2_processor_jtag_debug_module_translator:av_waitrequest + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_processor_jtag_debug_module_translator:av_writedata -> nios2_processor:jtag_debug_module_writedata + wire [8:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_processor_jtag_debug_module_translator:av_address -> nios2_processor:jtag_debug_module_address + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_processor_jtag_debug_module_translator:av_write -> nios2_processor:jtag_debug_module_write + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_processor_jtag_debug_module_translator:av_read -> nios2_processor:jtag_debug_module_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_processor:jtag_debug_module_readdata -> nios2_processor_jtag_debug_module_translator:av_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_processor_jtag_debug_module_translator:av_debugaccess -> nios2_processor:jtag_debug_module_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_processor_jtag_debug_module_translator:av_byteenable -> nios2_processor:jtag_debug_module_byteenable + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory_s1_translator:av_writedata -> onchip_memory:writedata + wire [15:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // onchip_memory_s1_translator:av_address -> onchip_memory:address + wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory_s1_translator:av_chipselect -> onchip_memory:chipselect + wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // onchip_memory_s1_translator:av_clken -> onchip_memory:clken + wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // onchip_memory_s1_translator:av_write -> onchip_memory:write + wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory:readdata -> onchip_memory_s1_translator:av_readdata + wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory_s1_translator:av_byteenable -> onchip_memory:byteenable + wire [31:0] leds_s1_translator_avalon_anti_slave_0_writedata; // LEDs_s1_translator:av_writedata -> LEDs:writedata + wire [1:0] leds_s1_translator_avalon_anti_slave_0_address; // LEDs_s1_translator:av_address -> LEDs:address + wire leds_s1_translator_avalon_anti_slave_0_chipselect; // LEDs_s1_translator:av_chipselect -> LEDs:chipselect + wire leds_s1_translator_avalon_anti_slave_0_write; // LEDs_s1_translator:av_write -> LEDs:write_n + wire [31:0] leds_s1_translator_avalon_anti_slave_0_readdata; // LEDs:readdata -> LEDs_s1_translator:av_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata + wire [0:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n + wire jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_writedata; // LEDRs_s1_translator:av_writedata -> LEDRs:writedata + wire [1:0] ledrs_s1_translator_avalon_anti_slave_0_address; // LEDRs_s1_translator:av_address -> LEDRs:address + wire ledrs_s1_translator_avalon_anti_slave_0_chipselect; // LEDRs_s1_translator:av_chipselect -> LEDRs:chipselect + wire ledrs_s1_translator_avalon_anti_slave_0_write; // LEDRs_s1_translator:av_write -> LEDRs:write_n + wire [31:0] ledrs_s1_translator_avalon_anti_slave_0_readdata; // LEDRs:readdata -> LEDRs_s1_translator:av_readdata + wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address + wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata + wire [1:0] push_switches_s1_translator_avalon_anti_slave_0_address; // push_switches_s1_translator:av_address -> push_switches:address + wire [31:0] push_switches_s1_translator_avalon_anti_slave_0_readdata; // push_switches:readdata -> push_switches_s1_translator:av_readdata + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_writedata; // hex0_s1_translator:av_writedata -> hex0:writedata + wire [1:0] hex0_s1_translator_avalon_anti_slave_0_address; // hex0_s1_translator:av_address -> hex0:address + wire hex0_s1_translator_avalon_anti_slave_0_chipselect; // hex0_s1_translator:av_chipselect -> hex0:chipselect + wire hex0_s1_translator_avalon_anti_slave_0_write; // hex0_s1_translator:av_write -> hex0:write_n + wire [31:0] hex0_s1_translator_avalon_anti_slave_0_readdata; // hex0:readdata -> hex0_s1_translator:av_readdata + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_writedata; // hex1_s1_translator:av_writedata -> hex1:writedata + wire [1:0] hex1_s1_translator_avalon_anti_slave_0_address; // hex1_s1_translator:av_address -> hex1:address + wire hex1_s1_translator_avalon_anti_slave_0_chipselect; // hex1_s1_translator:av_chipselect -> hex1:chipselect + wire hex1_s1_translator_avalon_anti_slave_0_write; // hex1_s1_translator:av_write -> hex1:write_n + wire [31:0] hex1_s1_translator_avalon_anti_slave_0_readdata; // hex1:readdata -> hex1_s1_translator:av_readdata + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_writedata; // hex2_s1_translator:av_writedata -> hex2:writedata + wire [1:0] hex2_s1_translator_avalon_anti_slave_0_address; // hex2_s1_translator:av_address -> hex2:address + wire hex2_s1_translator_avalon_anti_slave_0_chipselect; // hex2_s1_translator:av_chipselect -> hex2:chipselect + wire hex2_s1_translator_avalon_anti_slave_0_write; // hex2_s1_translator:av_write -> hex2:write_n + wire [31:0] hex2_s1_translator_avalon_anti_slave_0_readdata; // hex2:readdata -> hex2_s1_translator:av_readdata + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_writedata; // hex3_s1_translator:av_writedata -> hex3:writedata + wire [1:0] hex3_s1_translator_avalon_anti_slave_0_address; // hex3_s1_translator:av_address -> hex3:address + wire hex3_s1_translator_avalon_anti_slave_0_chipselect; // hex3_s1_translator:av_chipselect -> hex3:chipselect + wire hex3_s1_translator_avalon_anti_slave_0_write; // hex3_s1_translator:av_write -> hex3:write_n + wire [31:0] hex3_s1_translator_avalon_anti_slave_0_readdata; // hex3:readdata -> hex3_s1_translator:av_readdata + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_writedata; // hex4_s1_translator:av_writedata -> hex4:writedata + wire [1:0] hex4_s1_translator_avalon_anti_slave_0_address; // hex4_s1_translator:av_address -> hex4:address + wire hex4_s1_translator_avalon_anti_slave_0_chipselect; // hex4_s1_translator:av_chipselect -> hex4:chipselect + wire hex4_s1_translator_avalon_anti_slave_0_write; // hex4_s1_translator:av_write -> hex4:write_n + wire [31:0] hex4_s1_translator_avalon_anti_slave_0_readdata; // hex4:readdata -> hex4_s1_translator:av_readdata + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_writedata; // hex5_s1_translator:av_writedata -> hex5:writedata + wire [1:0] hex5_s1_translator_avalon_anti_slave_0_address; // hex5_s1_translator:av_address -> hex5:address + wire hex5_s1_translator_avalon_anti_slave_0_chipselect; // hex5_s1_translator:av_chipselect -> hex5:chipselect + wire hex5_s1_translator_avalon_anti_slave_0_write; // hex5_s1_translator:av_write -> hex5:write_n + wire [31:0] hex5_s1_translator_avalon_anti_slave_0_readdata; // hex5:readdata -> hex5_s1_translator:av_readdata + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_writedata; // hex6_s1_translator:av_writedata -> hex6:writedata + wire [1:0] hex6_s1_translator_avalon_anti_slave_0_address; // hex6_s1_translator:av_address -> hex6:address + wire hex6_s1_translator_avalon_anti_slave_0_chipselect; // hex6_s1_translator:av_chipselect -> hex6:chipselect + wire hex6_s1_translator_avalon_anti_slave_0_write; // hex6_s1_translator:av_write -> hex6:write_n + wire [31:0] hex6_s1_translator_avalon_anti_slave_0_readdata; // hex6:readdata -> hex6_s1_translator:av_readdata + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_writedata; // hex7_s1_translator:av_writedata -> hex7:writedata + wire [1:0] hex7_s1_translator_avalon_anti_slave_0_address; // hex7_s1_translator:av_address -> hex7:address + wire hex7_s1_translator_avalon_anti_slave_0_chipselect; // hex7_s1_translator:av_chipselect -> hex7:chipselect + wire hex7_s1_translator_avalon_anti_slave_0_write; // hex7_s1_translator:av_write -> hex7:write_n + wire [31:0] hex7_s1_translator_avalon_anti_slave_0_readdata; // hex7:readdata -> hex7_s1_translator:av_readdata + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_writedata; // lcd_16207_0_control_slave_translator:av_writedata -> lcd_16207_0:writedata + wire [1:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_address; // lcd_16207_0_control_slave_translator:av_address -> lcd_16207_0:address + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_write; // lcd_16207_0_control_slave_translator:av_write -> lcd_16207_0:write + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_read; // lcd_16207_0_control_slave_translator:av_read -> lcd_16207_0:read + wire [7:0] lcd_16207_0_control_slave_translator_avalon_anti_slave_0_readdata; // lcd_16207_0:readdata -> lcd_16207_0_control_slave_translator:av_readdata + wire lcd_16207_0_control_slave_translator_avalon_anti_slave_0_begintransfer; // lcd_16207_0_control_slave_translator:av_begintransfer -> lcd_16207_0:begintransfer + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_writedata; // lcd_on_s1_translator:av_writedata -> lcd_on:writedata + wire [1:0] lcd_on_s1_translator_avalon_anti_slave_0_address; // lcd_on_s1_translator:av_address -> lcd_on:address + wire lcd_on_s1_translator_avalon_anti_slave_0_chipselect; // lcd_on_s1_translator:av_chipselect -> lcd_on:chipselect + wire lcd_on_s1_translator_avalon_anti_slave_0_write; // lcd_on_s1_translator:av_write -> lcd_on:write_n + wire [31:0] lcd_on_s1_translator_avalon_anti_slave_0_readdata; // lcd_on:readdata -> lcd_on_s1_translator:av_readdata + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_writedata; // lcd_blon_s1_translator:av_writedata -> lcd_blon:writedata + wire [1:0] lcd_blon_s1_translator_avalon_anti_slave_0_address; // lcd_blon_s1_translator:av_address -> lcd_blon:address + wire lcd_blon_s1_translator_avalon_anti_slave_0_chipselect; // lcd_blon_s1_translator:av_chipselect -> lcd_blon:chipselect + wire lcd_blon_s1_translator_avalon_anti_slave_0_write; // lcd_blon_s1_translator:av_write -> lcd_blon:write_n + wire [31:0] lcd_blon_s1_translator_avalon_anti_slave_0_readdata; // lcd_blon:readdata -> lcd_blon_s1_translator:av_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_instruction_master_translator:uav_waitrequest + wire [2:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_instruction_master_translator:uav_burstcount -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_processor_instruction_master_translator:uav_writedata -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_address; // nios2_processor_instruction_master_translator:uav_address -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_lock; // nios2_processor_instruction_master_translator:uav_lock -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_write; // nios2_processor_instruction_master_translator:uav_write -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_read; // nios2_processor_instruction_master_translator:uav_read -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_instruction_master_translator:uav_readdata + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_instruction_master_translator:uav_debugaccess -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_instruction_master_translator:uav_byteenable -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_instruction_master_translator:uav_readdatavalid + wire nios2_processor_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_processor_data_master_translator:uav_waitrequest + wire [2:0] nios2_processor_data_master_translator_avalon_universal_master_0_burstcount; // nios2_processor_data_master_translator:uav_burstcount -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_writedata; // nios2_processor_data_master_translator:uav_writedata -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_writedata + wire [18:0] nios2_processor_data_master_translator_avalon_universal_master_0_address; // nios2_processor_data_master_translator:uav_address -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_address + wire nios2_processor_data_master_translator_avalon_universal_master_0_lock; // nios2_processor_data_master_translator:uav_lock -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_lock + wire nios2_processor_data_master_translator_avalon_universal_master_0_write; // nios2_processor_data_master_translator:uav_write -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_write + wire nios2_processor_data_master_translator_avalon_universal_master_0_read; // nios2_processor_data_master_translator:uav_read -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] nios2_processor_data_master_translator_avalon_universal_master_0_readdata; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_processor_data_master_translator:uav_readdata + wire nios2_processor_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_processor_data_master_translator:uav_debugaccess -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] nios2_processor_data_master_translator_avalon_universal_master_0_byteenable; // nios2_processor_data_master_translator:uav_byteenable -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_byteenable + wire nios2_processor_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_processor_data_master_translator:uav_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_processor_jtag_debug_module_translator:uav_waitrequest -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_processor_jtag_debug_module_translator:uav_burstcount + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_processor_jtag_debug_module_translator:uav_writedata + wire [18:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_processor_jtag_debug_module_translator:uav_address + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_processor_jtag_debug_module_translator:uav_write + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_processor_jtag_debug_module_translator:uav_lock + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_processor_jtag_debug_module_translator:uav_read + wire [31:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_processor_jtag_debug_module_translator:uav_readdata -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_processor_jtag_debug_module_translator:uav_readdatavalid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_processor_jtag_debug_module_translator:uav_debugaccess + wire [3:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_processor_jtag_debug_module_translator:uav_byteenable + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata + wire [18:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory_s1_translator:uav_address + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory_s1_translator:uav_write + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory_s1_translator:uav_lock + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory_s1_translator:uav_read + wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess + wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDs_s1_translator:uav_writedata + wire [18:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDs_s1_translator:uav_address + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDs_s1_translator:uav_write + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDs_s1_translator:uav_lock + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDs_s1_translator:uav_read + wire [31:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess + wire [3:0] leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata + wire [18:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read + wire [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess + wire [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LEDRs_s1_translator:uav_waitrequest -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LEDRs_s1_translator:uav_burstcount + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LEDRs_s1_translator:uav_writedata + wire [18:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_address; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_address -> LEDRs_s1_translator:uav_address + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_write; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_write -> LEDRs_s1_translator:uav_write + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LEDRs_s1_translator:uav_lock + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_read; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_read -> LEDRs_s1_translator:uav_read + wire [31:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LEDRs_s1_translator:uav_readdata -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LEDRs_s1_translator:uav_readdatavalid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LEDRs_s1_translator:uav_debugaccess + wire [3:0] ledrs_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LEDRs_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LEDRs_s1_translator:uav_byteenable + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata + wire [18:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read + wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess + wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // push_switches_s1_translator:uav_waitrequest -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> push_switches_s1_translator:uav_burstcount + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> push_switches_s1_translator:uav_writedata + wire [18:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> push_switches_s1_translator:uav_address + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> push_switches_s1_translator:uav_write + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> push_switches_s1_translator:uav_lock + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> push_switches_s1_translator:uav_read + wire [31:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // push_switches_s1_translator:uav_readdata -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // push_switches_s1_translator:uav_readdatavalid -> push_switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> push_switches_s1_translator:uav_debugaccess + wire [3:0] push_switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // push_switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> push_switches_s1_translator:uav_byteenable + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex0_s1_translator:uav_writedata + wire [18:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex0_s1_translator:uav_address + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex0_s1_translator:uav_write + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex0_s1_translator:uav_lock + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex0_s1_translator:uav_read + wire [31:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess + wire [3:0] hex0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex1_s1_translator:uav_writedata + wire [18:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex1_s1_translator:uav_address + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex1_s1_translator:uav_write + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex1_s1_translator:uav_lock + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex1_s1_translator:uav_read + wire [31:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess + wire [3:0] hex1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex2_s1_translator:uav_writedata + wire [18:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex2_s1_translator:uav_address + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex2_s1_translator:uav_write + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex2_s1_translator:uav_lock + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex2_s1_translator:uav_read + wire [31:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess + wire [3:0] hex2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex3_s1_translator:uav_writedata + wire [18:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex3_s1_translator:uav_address + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex3_s1_translator:uav_write + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex3_s1_translator:uav_lock + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex3_s1_translator:uav_read + wire [31:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex3_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess + wire [3:0] hex3_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex3_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex4_s1_translator:uav_writedata + wire [18:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex4_s1_translator:uav_address + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex4_s1_translator:uav_write + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex4_s1_translator:uav_lock + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex4_s1_translator:uav_read + wire [31:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex4_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess + wire [3:0] hex4_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex4_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex5_s1_translator:uav_writedata + wire [18:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex5_s1_translator:uav_address + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex5_s1_translator:uav_write + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex5_s1_translator:uav_lock + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex5_s1_translator:uav_read + wire [31:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex5_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess + wire [3:0] hex5_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex5_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex6_s1_translator:uav_waitrequest -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex6_s1_translator:uav_burstcount + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex6_s1_translator:uav_writedata + wire [18:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex6_s1_translator:uav_address + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex6_s1_translator:uav_write + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex6_s1_translator:uav_lock + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex6_s1_translator:uav_read + wire [31:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex6_s1_translator:uav_readdata -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex6_s1_translator:uav_readdatavalid -> hex6_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex6_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex6_s1_translator:uav_debugaccess + wire [3:0] hex6_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex6_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex6_s1_translator:uav_byteenable + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hex7_s1_translator:uav_waitrequest -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hex7_s1_translator:uav_burstcount + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hex7_s1_translator:uav_writedata + wire [18:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_address; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_address -> hex7_s1_translator:uav_address + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_write; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_write -> hex7_s1_translator:uav_write + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_lock; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hex7_s1_translator:uav_lock + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_read; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_read -> hex7_s1_translator:uav_read + wire [31:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // hex7_s1_translator:uav_readdata -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hex7_s1_translator:uav_readdatavalid -> hex7_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire hex7_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hex7_s1_translator:uav_debugaccess + wire [3:0] hex7_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // hex7_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hex7_s1_translator:uav_byteenable + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_16207_0_control_slave_translator:uav_waitrequest -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_16207_0_control_slave_translator:uav_burstcount + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_16207_0_control_slave_translator:uav_writedata + wire [18:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> lcd_16207_0_control_slave_translator:uav_address + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> lcd_16207_0_control_slave_translator:uav_write + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_16207_0_control_slave_translator:uav_lock + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> lcd_16207_0_control_slave_translator:uav_read + wire [31:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_16207_0_control_slave_translator:uav_readdata -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_16207_0_control_slave_translator:uav_readdatavalid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_16207_0_control_slave_translator:uav_debugaccess + wire [3:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_16207_0_control_slave_translator:uav_byteenable + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_on_s1_translator:uav_waitrequest -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_on_s1_translator:uav_burstcount + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_on_s1_translator:uav_writedata + wire [18:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_on_s1_translator:uav_address + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_on_s1_translator:uav_write + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_on_s1_translator:uav_lock + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_on_s1_translator:uav_read + wire [31:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_on_s1_translator:uav_readdata -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_on_s1_translator:uav_readdatavalid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_on_s1_translator:uav_debugaccess + wire [3:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_on_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_on_s1_translator:uav_byteenable + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lcd_blon_s1_translator:uav_waitrequest -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> lcd_blon_s1_translator:uav_burstcount + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> lcd_blon_s1_translator:uav_writedata + wire [18:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_address; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_address -> lcd_blon_s1_translator:uav_address + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_write; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_write -> lcd_blon_s1_translator:uav_write + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_lock; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_lock -> lcd_blon_s1_translator:uav_lock + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_read; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_read -> lcd_blon_s1_translator:uav_read + wire [31:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // lcd_blon_s1_translator:uav_readdata -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lcd_blon_s1_translator:uav_readdatavalid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lcd_blon_s1_translator:uav_debugaccess + wire [3:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> lcd_blon_s1_translator:uav_byteenable + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [96:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [33:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket + wire [95:0] nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data + wire nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket + wire [95:0] nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data + wire nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:cp_ready + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket + wire [95:0] nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data + wire nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket + wire [95:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data + wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket + wire [95:0] leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data + wire leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> LEDs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket + wire [95:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data + wire jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket + wire [95:0] ledrs_s1_translator_avalon_universal_slave_0_agent_rp_data; // LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data + wire ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> LEDRs_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket + wire [95:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data + wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket + wire [95:0] push_switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // push_switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data + wire push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> push_switches_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket + wire [95:0] hex0_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data + wire hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hex0_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket + wire [95:0] hex1_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data + wire hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> hex1_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket + wire [95:0] hex2_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data + wire hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> hex2_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket + wire [95:0] hex3_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex3_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data + wire hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> hex3_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket + wire [95:0] hex4_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex4_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data + wire hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_011:sink_ready -> hex4_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket + wire [95:0] hex5_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex5_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data + wire hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_012:sink_ready -> hex5_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket + wire [95:0] hex6_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex6_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data + wire hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_013:sink_ready -> hex6_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket + wire [95:0] hex7_s1_translator_avalon_universal_slave_0_agent_rp_data; // hex7_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data + wire hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_014:sink_ready -> hex7_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket + wire [95:0] lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data + wire lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_015:sink_ready -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket + wire [95:0] lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data + wire lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_016:sink_ready -> lcd_on_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket + wire [95:0] lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_data; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data + wire lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_017:sink_ready -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDRs:reset_n, LEDRs_s1_translator:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent:reset, LEDRs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, LEDs:reset_n, LEDs_s1_translator:reset, LEDs_s1_translator_avalon_universal_slave_0_agent:reset, LEDs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, hex0:reset_n, hex0_s1_translator:reset, hex0_s1_translator_avalon_universal_slave_0_agent:reset, hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex1:reset_n, hex1_s1_translator:reset, hex1_s1_translator_avalon_universal_slave_0_agent:reset, hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex2:reset_n, hex2_s1_translator:reset, hex2_s1_translator_avalon_universal_slave_0_agent:reset, hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex3:reset_n, hex3_s1_translator:reset, hex3_s1_translator_avalon_universal_slave_0_agent:reset, hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex4:reset_n, hex4_s1_translator:reset, hex4_s1_translator_avalon_universal_slave_0_agent:reset, hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex5:reset_n, hex5_s1_translator:reset, hex5_s1_translator_avalon_universal_slave_0_agent:reset, hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex6:reset_n, hex6_s1_translator:reset, hex6_s1_translator_avalon_universal_slave_0_agent:reset, hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hex7:reset_n, hex7_s1_translator:reset, hex7_s1_translator_avalon_universal_slave_0_agent:reset, hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, irq_mapper:reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_16207_0:reset_n, lcd_16207_0_control_slave_translator:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:reset, lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_blon:reset_n, lcd_blon_s1_translator:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent:reset, lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lcd_on:reset_n, lcd_on_s1_translator:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent:reset, lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_processor:reset_n, nios2_processor_data_master_translator:reset, nios2_processor_data_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_instruction_master_translator:reset, nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_processor_jtag_debug_module_translator:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory:reset, onchip_memory_s1_translator:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, push_switches:reset_n, push_switches_s1_translator:reset, push_switches_s1_translator_avalon_universal_slave_0_agent:reset, push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset] + wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory:reset_req + wire nios2_processor_jtag_debug_module_reset_reset; // nios2_processor:jtag_debug_module_resetrequest -> rst_controller:reset_in1 + wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket + wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid + wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data + wire [17:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel + wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready + wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket + wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid + wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket + wire [95:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data + wire [17:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel + wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready + wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket + wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid + wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data + wire [17:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel + wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready + wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket + wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid + wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket + wire [95:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data + wire [17:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel + wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready + wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> LEDs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> push_switches_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hex0_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> hex1_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> hex2_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> hex3_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src11_endofpacket; // cmd_xbar_demux_001:src11_endofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src11_valid; // cmd_xbar_demux_001:src11_valid -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src11_startofpacket; // cmd_xbar_demux_001:src11_startofpacket -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src11_data; // cmd_xbar_demux_001:src11_data -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src11_channel; // cmd_xbar_demux_001:src11_channel -> hex4_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src12_endofpacket; // cmd_xbar_demux_001:src12_endofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src12_valid; // cmd_xbar_demux_001:src12_valid -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src12_startofpacket; // cmd_xbar_demux_001:src12_startofpacket -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src12_data; // cmd_xbar_demux_001:src12_data -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src12_channel; // cmd_xbar_demux_001:src12_channel -> hex5_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src13_endofpacket; // cmd_xbar_demux_001:src13_endofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src13_valid; // cmd_xbar_demux_001:src13_valid -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src13_startofpacket; // cmd_xbar_demux_001:src13_startofpacket -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src13_data; // cmd_xbar_demux_001:src13_data -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src13_channel; // cmd_xbar_demux_001:src13_channel -> hex6_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src14_endofpacket; // cmd_xbar_demux_001:src14_endofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src14_valid; // cmd_xbar_demux_001:src14_valid -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src14_startofpacket; // cmd_xbar_demux_001:src14_startofpacket -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src14_data; // cmd_xbar_demux_001:src14_data -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src14_channel; // cmd_xbar_demux_001:src14_channel -> hex7_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src15_endofpacket; // cmd_xbar_demux_001:src15_endofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src15_valid; // cmd_xbar_demux_001:src15_valid -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src15_startofpacket; // cmd_xbar_demux_001:src15_startofpacket -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src15_data; // cmd_xbar_demux_001:src15_data -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src15_channel; // cmd_xbar_demux_001:src15_channel -> lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src16_endofpacket; // cmd_xbar_demux_001:src16_endofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src16_valid; // cmd_xbar_demux_001:src16_valid -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src16_startofpacket; // cmd_xbar_demux_001:src16_startofpacket -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src16_data; // cmd_xbar_demux_001:src16_data -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src16_channel; // cmd_xbar_demux_001:src16_channel -> lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src17_endofpacket; // cmd_xbar_demux_001:src17_endofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src17_valid; // cmd_xbar_demux_001:src17_valid -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src17_startofpacket; // cmd_xbar_demux_001:src17_startofpacket -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_demux_001_src17_data; // cmd_xbar_demux_001:src17_data -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_demux_001_src17_channel; // cmd_xbar_demux_001:src17_channel -> lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket + wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid + wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data + wire [17:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel + wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready + wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket + wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid + wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket + wire [95:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data + wire [17:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel + wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready + wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket + wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid + wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data + wire [17:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel + wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready + wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket + wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid + wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket + wire [95:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data + wire [17:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel + wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready + wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket + wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid + wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket + wire [95:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data + wire [17:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel + wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready + wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket + wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid + wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket + wire [95:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data + wire [17:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel + wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready + wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket + wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid + wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket + wire [95:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data + wire [17:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel + wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready + wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket + wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid + wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket + wire [95:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data + wire [17:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel + wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready + wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket + wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid + wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket + wire [95:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data + wire [17:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel + wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready + wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket + wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid + wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket + wire [95:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data + wire [17:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel + wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready + wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket + wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid + wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket + wire [95:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data + wire [17:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel + wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready + wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket + wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid + wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket + wire [95:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data + wire [17:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel + wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready + wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket + wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid + wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket + wire [95:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data + wire [17:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel + wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready + wire rsp_xbar_demux_011_src0_endofpacket; // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket + wire rsp_xbar_demux_011_src0_valid; // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid + wire rsp_xbar_demux_011_src0_startofpacket; // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket + wire [95:0] rsp_xbar_demux_011_src0_data; // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data + wire [17:0] rsp_xbar_demux_011_src0_channel; // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel + wire rsp_xbar_demux_011_src0_ready; // rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready + wire rsp_xbar_demux_012_src0_endofpacket; // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket + wire rsp_xbar_demux_012_src0_valid; // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid + wire rsp_xbar_demux_012_src0_startofpacket; // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket + wire [95:0] rsp_xbar_demux_012_src0_data; // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data + wire [17:0] rsp_xbar_demux_012_src0_channel; // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel + wire rsp_xbar_demux_012_src0_ready; // rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready + wire rsp_xbar_demux_013_src0_endofpacket; // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_001:sink13_endofpacket + wire rsp_xbar_demux_013_src0_valid; // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_001:sink13_valid + wire rsp_xbar_demux_013_src0_startofpacket; // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_001:sink13_startofpacket + wire [95:0] rsp_xbar_demux_013_src0_data; // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_001:sink13_data + wire [17:0] rsp_xbar_demux_013_src0_channel; // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_001:sink13_channel + wire rsp_xbar_demux_013_src0_ready; // rsp_xbar_mux_001:sink13_ready -> rsp_xbar_demux_013:src0_ready + wire rsp_xbar_demux_014_src0_endofpacket; // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_001:sink14_endofpacket + wire rsp_xbar_demux_014_src0_valid; // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_001:sink14_valid + wire rsp_xbar_demux_014_src0_startofpacket; // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_001:sink14_startofpacket + wire [95:0] rsp_xbar_demux_014_src0_data; // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_001:sink14_data + wire [17:0] rsp_xbar_demux_014_src0_channel; // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_001:sink14_channel + wire rsp_xbar_demux_014_src0_ready; // rsp_xbar_mux_001:sink14_ready -> rsp_xbar_demux_014:src0_ready + wire rsp_xbar_demux_015_src0_endofpacket; // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_001:sink15_endofpacket + wire rsp_xbar_demux_015_src0_valid; // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_001:sink15_valid + wire rsp_xbar_demux_015_src0_startofpacket; // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_001:sink15_startofpacket + wire [95:0] rsp_xbar_demux_015_src0_data; // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_001:sink15_data + wire [17:0] rsp_xbar_demux_015_src0_channel; // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_001:sink15_channel + wire rsp_xbar_demux_015_src0_ready; // rsp_xbar_mux_001:sink15_ready -> rsp_xbar_demux_015:src0_ready + wire rsp_xbar_demux_016_src0_endofpacket; // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_001:sink16_endofpacket + wire rsp_xbar_demux_016_src0_valid; // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_001:sink16_valid + wire rsp_xbar_demux_016_src0_startofpacket; // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_001:sink16_startofpacket + wire [95:0] rsp_xbar_demux_016_src0_data; // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_001:sink16_data + wire [17:0] rsp_xbar_demux_016_src0_channel; // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_001:sink16_channel + wire rsp_xbar_demux_016_src0_ready; // rsp_xbar_mux_001:sink16_ready -> rsp_xbar_demux_016:src0_ready + wire rsp_xbar_demux_017_src0_endofpacket; // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_001:sink17_endofpacket + wire rsp_xbar_demux_017_src0_valid; // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_001:sink17_valid + wire rsp_xbar_demux_017_src0_startofpacket; // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_001:sink17_startofpacket + wire [95:0] rsp_xbar_demux_017_src0_data; // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_001:sink17_data + wire [17:0] rsp_xbar_demux_017_src0_channel; // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_001:sink17_channel + wire rsp_xbar_demux_017_src0_ready; // rsp_xbar_mux_001:sink17_ready -> rsp_xbar_demux_017:src0_ready + wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket + wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid + wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket + wire [95:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data + wire [17:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel + wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready + wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_src_ready; // nios2_processor_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready + wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket + wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid + wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket + wire [95:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data + wire [17:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel + wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready + wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_valid + wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [95:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_data + wire [17:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_channel + wire rsp_xbar_mux_001_src_ready; // nios2_processor_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready + wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_src_ready; // nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready + wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket + wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid + wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket + wire [95:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data + wire [17:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel + wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready + wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [95:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [17:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_001_src_ready; // onchip_memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready + wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket + wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid + wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket + wire [95:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data + wire [17:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel + wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready + wire cmd_xbar_demux_001_src2_ready; // LEDs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready + wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket + wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid + wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket + wire [95:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data + wire [17:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel + wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready + wire cmd_xbar_demux_001_src3_ready; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready + wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket + wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid + wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket + wire [95:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data + wire [17:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel + wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready + wire cmd_xbar_demux_001_src4_ready; // LEDRs_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready + wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket + wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid + wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket + wire [95:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data + wire [17:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel + wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready + wire cmd_xbar_demux_001_src5_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready + wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket + wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid + wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket + wire [95:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data + wire [17:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel + wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready + wire cmd_xbar_demux_001_src6_ready; // push_switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready + wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket + wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid + wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket + wire [95:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data + wire [17:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel + wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready + wire cmd_xbar_demux_001_src7_ready; // hex0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready + wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket + wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid + wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket + wire [95:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data + wire [17:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel + wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready + wire cmd_xbar_demux_001_src8_ready; // hex1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready + wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket + wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid + wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket + wire [95:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data + wire [17:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel + wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready + wire cmd_xbar_demux_001_src9_ready; // hex2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready + wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket + wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid + wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket + wire [95:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data + wire [17:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel + wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready + wire cmd_xbar_demux_001_src10_ready; // hex3_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready + wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket + wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid + wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket + wire [95:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data + wire [17:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel + wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready + wire cmd_xbar_demux_001_src11_ready; // hex4_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready + wire id_router_011_src_endofpacket; // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket + wire id_router_011_src_valid; // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid + wire id_router_011_src_startofpacket; // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket + wire [95:0] id_router_011_src_data; // id_router_011:src_data -> rsp_xbar_demux_011:sink_data + wire [17:0] id_router_011_src_channel; // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel + wire id_router_011_src_ready; // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready + wire cmd_xbar_demux_001_src12_ready; // hex5_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready + wire id_router_012_src_endofpacket; // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket + wire id_router_012_src_valid; // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid + wire id_router_012_src_startofpacket; // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket + wire [95:0] id_router_012_src_data; // id_router_012:src_data -> rsp_xbar_demux_012:sink_data + wire [17:0] id_router_012_src_channel; // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel + wire id_router_012_src_ready; // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready + wire cmd_xbar_demux_001_src13_ready; // hex6_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src13_ready + wire id_router_013_src_endofpacket; // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket + wire id_router_013_src_valid; // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid + wire id_router_013_src_startofpacket; // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket + wire [95:0] id_router_013_src_data; // id_router_013:src_data -> rsp_xbar_demux_013:sink_data + wire [17:0] id_router_013_src_channel; // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel + wire id_router_013_src_ready; // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready + wire cmd_xbar_demux_001_src14_ready; // hex7_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src14_ready + wire id_router_014_src_endofpacket; // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket + wire id_router_014_src_valid; // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid + wire id_router_014_src_startofpacket; // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket + wire [95:0] id_router_014_src_data; // id_router_014:src_data -> rsp_xbar_demux_014:sink_data + wire [17:0] id_router_014_src_channel; // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel + wire id_router_014_src_ready; // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready + wire cmd_xbar_demux_001_src15_ready; // lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src15_ready + wire id_router_015_src_endofpacket; // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket + wire id_router_015_src_valid; // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid + wire id_router_015_src_startofpacket; // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket + wire [95:0] id_router_015_src_data; // id_router_015:src_data -> rsp_xbar_demux_015:sink_data + wire [17:0] id_router_015_src_channel; // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel + wire id_router_015_src_ready; // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready + wire cmd_xbar_demux_001_src16_ready; // lcd_on_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src16_ready + wire id_router_016_src_endofpacket; // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket + wire id_router_016_src_valid; // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid + wire id_router_016_src_startofpacket; // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket + wire [95:0] id_router_016_src_data; // id_router_016:src_data -> rsp_xbar_demux_016:sink_data + wire [17:0] id_router_016_src_channel; // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel + wire id_router_016_src_ready; // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready + wire cmd_xbar_demux_001_src17_ready; // lcd_blon_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src17_ready + wire id_router_017_src_endofpacket; // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket + wire id_router_017_src_valid; // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid + wire id_router_017_src_startofpacket; // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket + wire [95:0] id_router_017_src_data; // id_router_017:src_data -> rsp_xbar_demux_017:sink_data + wire [17:0] id_router_017_src_channel; // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel + wire id_router_017_src_ready; // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready + wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> irq_mapper:receiver0_irq + wire [31:0] nios2_processor_d_irq_irq; // irq_mapper:sender_irq -> nios2_processor:d_irq + nios_system_nios2_processor nios2_processor ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n @@ -1100,8 +1100,8 @@ .jtag_debug_module_write (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write .jtag_debug_module_writedata (nios2_processor_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata .no_ci_readra () // custom_instruction_master.readra - ); - + ); + nios_system_onchip_memory onchip_memory ( .clk (clk_clk), // clk1.clk .address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address @@ -1113,8 +1113,8 @@ .byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable .reset (rst_controller_reset_out_reset), // reset1.reset .reset_req (rst_controller_reset_out_reset_req) // .reset_req - ); - + ); + nios_system_jtag_uart jtag_uart ( .clk (clk_clk), // clk.clk .rst_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1126,8 +1126,8 @@ .av_writedata (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata .av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest .av_irq (irq_mapper_receiver0_irq) // irq.irq - ); - + ); + nios_system_LEDs leds ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1137,8 +1137,8 @@ .chipselect (leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (leds_export) // external_connection.export - ); - + ); + nios_system_LEDRs ledrs ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1148,24 +1148,24 @@ .chipselect (ledrs_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (ledrs_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (ledrs_export) // external_connection.export - ); - + ); + nios_system_switches switches ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address .readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata .in_port (switches_export) // external_connection.export - ); - + ); + nios_system_push_switches push_switches ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .address (push_switches_s1_translator_avalon_anti_slave_0_address), // s1.address .readdata (push_switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata .in_port (push_switches_export) // external_connection.export - ); - + ); + nios_system_hex0 hex0 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1175,8 +1175,8 @@ .chipselect (hex0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex0_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex0_export) // external_connection.export - ); - + ); + nios_system_hex0 hex1 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1186,8 +1186,8 @@ .chipselect (hex1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex1_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex1_export) // external_connection.export - ); - + ); + nios_system_hex0 hex2 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1197,8 +1197,8 @@ .chipselect (hex2_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex2_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex2_export) // external_connection.export - ); - + ); + nios_system_hex0 hex3 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1208,8 +1208,8 @@ .chipselect (hex3_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex3_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex3_export) // external_connection.export - ); - + ); + nios_system_hex0 hex4 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1219,8 +1219,8 @@ .chipselect (hex4_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex4_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex4_export) // external_connection.export - ); - + ); + nios_system_hex0 hex5 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1230,8 +1230,8 @@ .chipselect (hex5_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex5_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex5_export) // external_connection.export - ); - + ); + nios_system_hex0 hex6 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1241,8 +1241,8 @@ .chipselect (hex6_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex6_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex6_export) // external_connection.export - ); - + ); + nios_system_hex0 hex7 ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1252,8 +1252,8 @@ .chipselect (hex7_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (hex7_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (hex7_export) // external_connection.export - ); - + ); + nios_system_lcd_16207_0 lcd_16207_0 ( .reset_n (~rst_controller_reset_out_reset), // reset.reset_n .clk (clk_clk), // clk.clk @@ -1267,8 +1267,8 @@ .LCD_RW (lcd_16207_0_RW), // .export .LCD_data (lcd_16207_0_data), // .export .LCD_E (lcd_16207_0_E) // .export - ); - + ); + nios_system_lcd_on lcd_on ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1278,8 +1278,8 @@ .chipselect (lcd_on_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (lcd_on_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (lcd_on_export) // external_connection.export - ); - + ); + nios_system_lcd_on lcd_blon ( .clk (clk_clk), // clk.clk .reset_n (~rst_controller_reset_out_reset), // reset.reset_n @@ -1289,32 +1289,32 @@ .chipselect (lcd_blon_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect .readdata (lcd_blon_s1_translator_avalon_anti_slave_0_readdata), // .readdata .out_port (lcd_blon_export) // external_connection.export - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (0), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (1), - .AV_REGISTERINCOMINGSIGNALS (0) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (0), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (1), + .AV_REGISTERINCOMINGSIGNALS (0) ) nios2_processor_instruction_master_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1351,32 +1351,32 @@ .uav_writeresponsevalid (1'b0), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_translator #( - .AV_ADDRESS_W (19), - .AV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .USE_READ (1), - .USE_WRITE (1), - .USE_BEGINBURSTTRANSFER (0), - .USE_BEGINTRANSFER (0), - .USE_CHIPSELECT (0), - .USE_BURSTCOUNT (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (1), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_LINEWRAPBURSTS (0), - .AV_REGISTERINCOMINGSIGNALS (1) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (19), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (1) ) nios2_processor_data_master_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1413,34 +1413,34 @@ .uav_writeresponsevalid (1'b0), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (9), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (9), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) nios2_processor_jtag_debug_module_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1479,34 +1479,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (16), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (4), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (1), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (0), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (16), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) onchip_memory_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1545,34 +1545,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) leds_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1611,34 +1611,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (1), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (1), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (1), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) jtag_uart_avalon_jtag_slave_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1677,34 +1677,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) ledrs_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1743,34 +1743,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) switches_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1809,34 +1809,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) push_switches_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1875,34 +1875,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex0_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -1941,34 +1941,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex1_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2007,34 +2007,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex2_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2073,34 +2073,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex3_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2139,34 +2139,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex4_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2205,34 +2205,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex5_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2271,34 +2271,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex6_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2337,34 +2337,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) hex7_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2403,34 +2403,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (8), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (13), - .AV_WRITE_WAIT_CYCLES (13), - .AV_SETUP_WAIT_CYCLES (13), - .AV_DATA_HOLD_CYCLES (13) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (8), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (13), + .AV_WRITE_WAIT_CYCLES (13), + .AV_SETUP_WAIT_CYCLES (13), + .AV_DATA_HOLD_CYCLES (13) ) lcd_16207_0_control_slave_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2469,34 +2469,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) lcd_on_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2535,34 +2535,34 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_slave_translator #( - .AV_ADDRESS_W (2), - .AV_DATA_W (32), - .UAV_DATA_W (32), - .AV_BURSTCOUNT_W (1), - .AV_BYTEENABLE_W (1), - .UAV_BYTEENABLE_W (4), - .UAV_ADDRESS_W (19), - .UAV_BURSTCOUNT_W (3), - .AV_READLATENCY (0), - .USE_READDATAVALID (0), - .USE_WAITREQUEST (0), - .USE_UAV_CLKEN (0), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0), - .AV_SYMBOLS_PER_WORD (4), - .AV_ADDRESS_SYMBOLS (0), - .AV_BURSTCOUNT_SYMBOLS (0), - .AV_CONSTANT_BURST_BEHAVIOR (0), - .UAV_CONSTANT_BURST_BEHAVIOR (0), - .AV_REQUIRE_UNALIGNED_ADDRESSES (0), - .CHIPSELECT_THROUGH_READLATENCY (0), - .AV_READ_WAIT_CYCLES (1), - .AV_WRITE_WAIT_CYCLES (0), - .AV_SETUP_WAIT_CYCLES (0), - .AV_DATA_HOLD_CYCLES (0) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (19), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) ) lcd_blon_s1_translator ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // reset.reset @@ -2601,58 +2601,58 @@ .uav_writeresponsevalid (), // (terminated) .av_writeresponserequest (), // (terminated) .av_writeresponsevalid (1'b0) // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (1), - .BURSTWRAP_VALUE (3), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (1), + .BURSTWRAP_VALUE (3), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2681,58 +2681,58 @@ .av_response (), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_master_agent #( - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_BEGIN_BURST (74), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .PKT_BURST_TYPE_H (71), - .PKT_BURST_TYPE_L (70), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_TRANS_EXCLUSIVE (60), - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_THREAD_ID_H (86), - .PKT_THREAD_ID_L (86), - .PKT_CACHE_H (93), - .PKT_CACHE_L (90), - .PKT_DATA_SIDEBAND_H (73), - .PKT_DATA_SIDEBAND_L (73), - .PKT_QOS_H (75), - .PKT_QOS_L (75), - .PKT_ADDR_SIDEBAND_H (72), - .PKT_ADDR_SIDEBAND_L (72), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .ST_DATA_W (96), - .ST_CHANNEL_W (18), - .AV_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_RSP (0), - .ID (0), - .BURSTWRAP_VALUE (7), - .CACHE_VALUE (0), - .SECURE_ACCESS_BIT (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_BEGIN_BURST (74), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .PKT_BURST_TYPE_H (71), + .PKT_BURST_TYPE_L (70), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_TRANS_EXCLUSIVE (60), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_THREAD_ID_H (86), + .PKT_THREAD_ID_L (86), + .PKT_CACHE_H (93), + .PKT_CACHE_L (90), + .PKT_DATA_SIDEBAND_H (73), + .PKT_DATA_SIDEBAND_L (73), + .PKT_QOS_H (75), + .PKT_QOS_L (75), + .PKT_ADDR_SIDEBAND_H (72), + .PKT_ADDR_SIDEBAND_L (72), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .ST_DATA_W (96), + .ST_CHANNEL_W (18), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (0), + .BURSTWRAP_VALUE (7), + .CACHE_VALUE (0), + .SECURE_ACCESS_BIT (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) nios2_processor_data_master_translator_avalon_universal_master_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2761,43 +2761,43 @@ .av_response (), // (terminated) .av_writeresponserequest (1'b0), // (terminated) .av_writeresponsevalid () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2842,21 +2842,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2883,43 +2883,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) onchip_memory_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -2964,21 +2964,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3005,43 +3005,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) leds_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3086,21 +3086,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3127,43 +3127,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3208,21 +3208,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3249,43 +3249,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) ledrs_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3330,21 +3330,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3371,43 +3371,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) switches_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3452,21 +3452,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3493,43 +3493,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) push_switches_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3574,21 +3574,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3615,43 +3615,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex0_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3696,21 +3696,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3737,43 +3737,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex1_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3818,21 +3818,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3859,43 +3859,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex2_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3940,21 +3940,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -3981,43 +3981,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex3_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4062,21 +4062,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4103,43 +4103,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex4_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4184,21 +4184,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4225,43 +4225,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex5_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4306,21 +4306,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4347,43 +4347,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex6_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4428,21 +4428,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4469,43 +4469,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) hex7_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4550,21 +4550,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4591,43 +4591,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4672,21 +4672,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4713,43 +4713,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) lcd_on_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4794,21 +4794,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4835,43 +4835,43 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - - altera_merlin_slave_agent #( - .PKT_DATA_H (31), - .PKT_DATA_L (0), - .PKT_BEGIN_BURST (74), - .PKT_SYMBOL_W (8), - .PKT_BYTEEN_H (35), - .PKT_BYTEEN_L (32), - .PKT_ADDR_H (54), - .PKT_ADDR_L (36), - .PKT_TRANS_COMPRESSED_READ (55), - .PKT_TRANS_POSTED (56), - .PKT_TRANS_WRITE (57), - .PKT_TRANS_READ (58), - .PKT_TRANS_LOCK (59), - .PKT_SRC_ID_H (80), - .PKT_SRC_ID_L (76), - .PKT_DEST_ID_H (85), - .PKT_DEST_ID_L (81), - .PKT_BURSTWRAP_H (66), - .PKT_BURSTWRAP_L (64), - .PKT_BYTE_CNT_H (63), - .PKT_BYTE_CNT_L (61), - .PKT_PROTECTION_H (89), - .PKT_PROTECTION_L (87), - .PKT_RESPONSE_STATUS_H (95), - .PKT_RESPONSE_STATUS_L (94), - .PKT_BURST_SIZE_H (69), - .PKT_BURST_SIZE_L (67), - .ST_CHANNEL_W (18), - .ST_DATA_W (96), - .AVS_BURSTCOUNT_W (3), - .SUPPRESS_0_BYTEEN_CMD (0), - .PREVENT_FIFO_OVERFLOW (1), - .USE_READRESPONSE (0), - .USE_WRITERESPONSE (0) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (74), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (54), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (55), + .PKT_TRANS_POSTED (56), + .PKT_TRANS_WRITE (57), + .PKT_TRANS_READ (58), + .PKT_TRANS_LOCK (59), + .PKT_SRC_ID_H (80), + .PKT_SRC_ID_L (76), + .PKT_DEST_ID_H (85), + .PKT_DEST_ID_L (81), + .PKT_BURSTWRAP_H (66), + .PKT_BURSTWRAP_L (64), + .PKT_BYTE_CNT_H (63), + .PKT_BYTE_CNT_L (61), + .PKT_PROTECTION_H (89), + .PKT_PROTECTION_L (87), + .PKT_RESPONSE_STATUS_H (95), + .PKT_RESPONSE_STATUS_L (94), + .PKT_BURST_SIZE_H (69), + .PKT_BURST_SIZE_L (67), + .ST_CHANNEL_W (18), + .ST_DATA_W (96), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0) ) lcd_blon_s1_translator_avalon_universal_slave_0_agent ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4916,21 +4916,21 @@ .m0_response (2'b00), // (terminated) .m0_writeresponserequest (), // (terminated) .m0_writeresponsevalid (1'b0) // (terminated) - ); - - altera_avalon_sc_fifo #( - .SYMBOLS_PER_BEAT (1), - .BITS_PER_SYMBOL (97), - .FIFO_DEPTH (2), - .CHANNEL_WIDTH (0), - .ERROR_WIDTH (0), - .USE_PACKETS (1), - .USE_FILL_LEVEL (0), - .EMPTY_LATENCY (1), - .USE_MEMORY_BLOCKS (0), - .USE_STORE_FORWARD (0), - .USE_ALMOST_FULL_IF (0), - .USE_ALMOST_EMPTY_IF (0) + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (97), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) ) lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -4957,8 +4957,8 @@ .out_error (), // (terminated) .in_channel (1'b0), // (terminated) .out_channel () // (terminated) - ); - + ); + nios_system_addr_router addr_router ( .sink_ready (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_processor_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid @@ -4973,8 +4973,8 @@ .src_channel (addr_router_src_channel), // .channel .src_startofpacket (addr_router_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_src_endofpacket) // .endofpacket - ); - + ); + nios_system_addr_router_001 addr_router_001 ( .sink_ready (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready .sink_valid (nios2_processor_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid @@ -4989,8 +4989,8 @@ .src_channel (addr_router_001_src_channel), // .channel .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router id_router ( .sink_ready (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5005,8 +5005,8 @@ .src_channel (id_router_src_channel), // .channel .src_startofpacket (id_router_src_startofpacket), // .startofpacket .src_endofpacket (id_router_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router id_router_001 ( .sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5021,8 +5021,8 @@ .src_channel (id_router_001_src_channel), // .channel .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_002 ( .sink_ready (leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5037,8 +5037,8 @@ .src_channel (id_router_002_src_channel), // .channel .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_003 ( .sink_ready (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5053,8 +5053,8 @@ .src_channel (id_router_003_src_channel), // .channel .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_004 ( .sink_ready (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (ledrs_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5069,8 +5069,8 @@ .src_channel (id_router_004_src_channel), // .channel .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_005 ( .sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5085,8 +5085,8 @@ .src_channel (id_router_005_src_channel), // .channel .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_006 ( .sink_ready (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (push_switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5101,8 +5101,8 @@ .src_channel (id_router_006_src_channel), // .channel .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_007 ( .sink_ready (hex0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5117,8 +5117,8 @@ .src_channel (id_router_007_src_channel), // .channel .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_008 ( .sink_ready (hex1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5133,8 +5133,8 @@ .src_channel (id_router_008_src_channel), // .channel .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_009 ( .sink_ready (hex2_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex2_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5149,8 +5149,8 @@ .src_channel (id_router_009_src_channel), // .channel .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_010 ( .sink_ready (hex3_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex3_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5165,8 +5165,8 @@ .src_channel (id_router_010_src_channel), // .channel .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_011 ( .sink_ready (hex4_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex4_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5181,8 +5181,8 @@ .src_channel (id_router_011_src_channel), // .channel .src_startofpacket (id_router_011_src_startofpacket), // .startofpacket .src_endofpacket (id_router_011_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_012 ( .sink_ready (hex5_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex5_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5197,8 +5197,8 @@ .src_channel (id_router_012_src_channel), // .channel .src_startofpacket (id_router_012_src_startofpacket), // .startofpacket .src_endofpacket (id_router_012_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_013 ( .sink_ready (hex6_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex6_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5213,8 +5213,8 @@ .src_channel (id_router_013_src_channel), // .channel .src_startofpacket (id_router_013_src_startofpacket), // .startofpacket .src_endofpacket (id_router_013_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_014 ( .sink_ready (hex7_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (hex7_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5229,8 +5229,8 @@ .src_channel (id_router_014_src_channel), // .channel .src_startofpacket (id_router_014_src_startofpacket), // .startofpacket .src_endofpacket (id_router_014_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_015 ( .sink_ready (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5245,8 +5245,8 @@ .src_channel (id_router_015_src_channel), // .channel .src_startofpacket (id_router_015_src_startofpacket), // .startofpacket .src_endofpacket (id_router_015_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_016 ( .sink_ready (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (lcd_on_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5261,8 +5261,8 @@ .src_channel (id_router_016_src_channel), // .channel .src_startofpacket (id_router_016_src_startofpacket), // .startofpacket .src_endofpacket (id_router_016_src_endofpacket) // .endofpacket - ); - + ); + nios_system_id_router_002 id_router_017 ( .sink_ready (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready .sink_valid (lcd_blon_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid @@ -5277,13 +5277,13 @@ .src_channel (id_router_017_src_channel), // .channel .src_startofpacket (id_router_017_src_startofpacket), // .startofpacket .src_endofpacket (id_router_017_src_endofpacket) // .endofpacket - ); - - altera_reset_controller #( - .NUM_RESET_INPUTS (2), - .OUTPUT_RESET_SYNC_EDGES ("deassert"), - .SYNC_DEPTH (2), - .RESET_REQUEST_PRESENT (1) + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (2), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (1) ) rst_controller ( .reset_in0 (~reset_reset_n), // reset_in0.reset .reset_in1 (nios2_processor_jtag_debug_module_reset_reset), // reset_in1.reset @@ -5304,8 +5304,8 @@ .reset_in13 (1'b0), // (terminated) .reset_in14 (1'b0), // (terminated) .reset_in15 (1'b0) // (terminated) - ); - + ); + nios_system_cmd_xbar_demux cmd_xbar_demux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5327,8 +5327,8 @@ .src1_channel (cmd_xbar_demux_src1_channel), // .channel .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5446,8 +5446,8 @@ .src17_channel (cmd_xbar_demux_001_src17_channel), // .channel .src17_startofpacket (cmd_xbar_demux_001_src17_startofpacket), // .startofpacket .src17_endofpacket (cmd_xbar_demux_001_src17_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_mux cmd_xbar_mux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5469,8 +5469,8 @@ .sink1_data (cmd_xbar_demux_001_src0_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_mux cmd_xbar_mux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5492,8 +5492,8 @@ .sink1_data (cmd_xbar_demux_001_src1_data), // .data .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_demux rsp_xbar_demux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5515,8 +5515,8 @@ .src1_channel (rsp_xbar_demux_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_cmd_xbar_demux rsp_xbar_demux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5538,8 +5538,8 @@ .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_002 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5555,8 +5555,8 @@ .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_003 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5572,8 +5572,8 @@ .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_004 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5589,8 +5589,8 @@ .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_005 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5606,8 +5606,8 @@ .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_006 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5623,8 +5623,8 @@ .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_007 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5640,8 +5640,8 @@ .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_008 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5657,8 +5657,8 @@ .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_009 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5674,8 +5674,8 @@ .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_010 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5691,8 +5691,8 @@ .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_011 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5708,8 +5708,8 @@ .src0_channel (rsp_xbar_demux_011_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_011_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_012 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5725,8 +5725,8 @@ .src0_channel (rsp_xbar_demux_012_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_012_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_013 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5742,8 +5742,8 @@ .src0_channel (rsp_xbar_demux_013_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_013_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_014 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5759,8 +5759,8 @@ .src0_channel (rsp_xbar_demux_014_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_014_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_015 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5776,8 +5776,8 @@ .src0_channel (rsp_xbar_demux_015_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_015_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_016 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5793,8 +5793,8 @@ .src0_channel (rsp_xbar_demux_016_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_016_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_demux_002 rsp_xbar_demux_017 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5810,8 +5810,8 @@ .src0_channel (rsp_xbar_demux_017_src0_channel), // .channel .src0_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket .src0_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_mux rsp_xbar_mux ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5833,8 +5833,8 @@ .sink1_data (rsp_xbar_demux_001_src0_data), // .data .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset @@ -5952,13 +5952,13 @@ .sink17_data (rsp_xbar_demux_017_src0_data), // .data .sink17_startofpacket (rsp_xbar_demux_017_src0_startofpacket), // .startofpacket .sink17_endofpacket (rsp_xbar_demux_017_src0_endofpacket) // .endofpacket - ); - + ); + nios_system_irq_mapper irq_mapper ( .clk (clk_clk), // clk.clk .reset (rst_controller_reset_out_reset), // clk_reset.reset .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq .sender_irq (nios2_processor_d_irq_irq) // sender.irq - ); - -endmodule + ); + +endmodule diff --git a/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v b/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v index 8f846b8..94e2787 100644 --- a/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v +++ b/nios_system/synthesis/submodules/altera_avalon_sc_fifo.v @@ -1,877 +1,877 @@ -// ----------------------------------------------------------- -// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your -// use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any -// output files any of the foregoing (including device programming or -// simulation files), and any associated documentation or information are -// expressly subject to the terms and conditions of the Altera Program -// License Subscription Agreement or other applicable license agreement, -// including, without limitation, that your use is for the sole purpose -// of programming logic devices manufactured by Altera and sold by Altera -// or its authorized distributors. Please refer to the applicable -// agreement for further details. -// -// Description: Single clock Avalon-ST FIFO. -// ----------------------------------------------------------- - -`timescale 1 ns / 1 ns - - -//altera message_off 10036 -module altera_avalon_sc_fifo -#( - // -------------------------------------------------- - // Parameters - // -------------------------------------------------- - parameter SYMBOLS_PER_BEAT = 1, - parameter BITS_PER_SYMBOL = 8, - parameter FIFO_DEPTH = 16, - parameter CHANNEL_WIDTH = 0, - parameter ERROR_WIDTH = 0, - parameter USE_PACKETS = 0, - parameter USE_FILL_LEVEL = 0, - parameter USE_STORE_FORWARD = 0, - parameter USE_ALMOST_FULL_IF = 0, - parameter USE_ALMOST_EMPTY_IF = 0, - - // -------------------------------------------------- - // Empty latency is defined as the number of cycles - // required for a write to deassert the empty flag. - // For example, a latency of 1 means that the empty - // flag is deasserted on the cycle after a write. - // - // Another way to think of it is the latency for a - // write to propagate to the output. - // - // An empty latency of 0 implies lookahead, which is - // only implemented for the register-based FIFO. - // -------------------------------------------------- - parameter EMPTY_LATENCY = 3, - parameter USE_MEMORY_BLOCKS = 1, - - // -------------------------------------------------- - // Internal Parameters - // -------------------------------------------------- - parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, - parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) -) -( - // -------------------------------------------------- - // Ports - // -------------------------------------------------- - input clk, - input reset, - - input [DATA_WIDTH-1: 0] in_data, - input in_valid, - input in_startofpacket, - input in_endofpacket, - input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, - input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, - input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, - output in_ready, - - output [DATA_WIDTH-1 : 0] out_data, - output reg out_valid, - output out_startofpacket, - output out_endofpacket, - output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, - output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, - output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, - input out_ready, - - input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, - input csr_write, - input csr_read, - input [31 : 0] csr_writedata, - output reg [31 : 0] csr_readdata, - - output wire almost_full_data, - output wire almost_empty_data -); - - // -------------------------------------------------- - // Local Parameters - // -------------------------------------------------- - localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); - localparam DEPTH = FIFO_DEPTH; - localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; - localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? - 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: - DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; - - // -------------------------------------------------- - // Internal Signals - // -------------------------------------------------- - genvar i; - - reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; - reg [ADDR_WIDTH-1 : 0] wr_ptr; - reg [ADDR_WIDTH-1 : 0] rd_ptr; - reg [DEPTH-1 : 0] mem_used; - - wire [ADDR_WIDTH-1 : 0] next_wr_ptr; - wire [ADDR_WIDTH-1 : 0] next_rd_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; - wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; - - wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; - - wire read; - wire write; - - reg empty; - reg next_empty; - reg full; - reg next_full; - - wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; - wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; - wire [PAYLOAD_WIDTH-1 : 0] in_payload; - reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; - reg [PAYLOAD_WIDTH-1 : 0] out_payload; - - reg internal_out_valid; - wire internal_out_ready; - - reg [ADDR_WIDTH : 0] fifo_fill_level; - reg [ADDR_WIDTH : 0] fill_level; - - reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; - reg [23:0] almost_full_threshold; - reg [23:0] almost_empty_threshold; - reg [23:0] cut_through_threshold; - reg [15:0] pkt_cnt; - reg [15:0] pkt_cnt_r; - reg [15:0] pkt_cnt_plusone; - reg [15:0] pkt_cnt_minusone; - reg drop_on_error_en; - reg error_in_pkt; - reg pkt_has_started; - reg sop_has_left_fifo; - reg fifo_too_small_r; - reg pkt_cnt_eq_zero; - reg pkt_cnt_eq_one; - reg pkt_cnt_changed; - - wire wait_for_threshold; - reg pkt_mode; - wire wait_for_pkt; - wire ok_to_forward; - wire in_pkt_eop_arrive; - wire out_pkt_leave; - wire in_pkt_start; - wire in_pkt_error; - wire drop_on_error; - wire fifo_too_small; - wire out_pkt_sop_leave; - wire [31:0] max_fifo_size; - reg fifo_fill_level_lt_cut_through_threshold; - - // -------------------------------------------------- - // Define Payload - // - // Icky part where we decide which signals form the - // payload to the FIFO with generate blocks. - // -------------------------------------------------- - generate - if (EMPTY_WIDTH > 0) begin - assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; - assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; - end - else begin - assign out_empty = in_error; - assign in_packet_signals = {in_startofpacket, in_endofpacket}; - assign {out_startofpacket, out_endofpacket} = out_packet_signals; - end - endgenerate - - generate - if (USE_PACKETS) begin - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; - assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data, in_error}; - assign {out_packet_signals, out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_packet_signals, in_data, in_channel}; - assign {out_packet_signals, out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_packet_signals, in_data}; - assign {out_packet_signals, out_data} = out_payload; - end - end - end - else begin - assign out_packet_signals = 0; - if (ERROR_WIDTH > 0) begin - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_error, in_channel}; - assign {out_data, out_error, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = {in_data, in_error}; - assign {out_data, out_error} = out_payload; - end - end - else begin - assign out_error = in_error; - if (CHANNEL_WIDTH > 0) begin - assign in_payload = {in_data, in_channel}; - assign {out_data, out_channel} = out_payload; - end - else begin - assign out_channel = in_channel; - assign in_payload = in_data; - assign out_data = out_payload; - end - end - end - endgenerate - - // -------------------------------------------------- - // Memory-based FIFO storage - // - // To allow a ready latency of 0, the read index is - // obtained from the next read pointer and memory - // outputs are unregistered. - // - // If the empty latency is 1, we infer bypass logic - // around the memory so writes propagate to the - // outputs on the next cycle. - // - // Do not change the way this is coded: Quartus needs - // a perfect match to the template, and any attempt to - // refactor the two always blocks into one will break - // memory inference. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - if (EMPTY_LATENCY == 1) begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] = in_payload; - - internal_out_payload = mem[mem_rd_ptr]; - end - - end else begin - - always @(posedge clk) begin - if (in_valid && in_ready) - mem[wr_ptr] <= in_payload; - - internal_out_payload <= mem[mem_rd_ptr]; - end - - end - - assign mem_rd_ptr = next_rd_ptr; - - end else begin - - // -------------------------------------------------- - // Register-based FIFO storage - // - // Uses a shift register as the storage element. Each - // shift register slot has a bit which indicates if - // the slot is occupied (credit to Sam H for the idea). - // The occupancy bits are contiguous and start from the - // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep - // FIFO. - // - // Each slot is enabled during a read or when it - // is unoccupied. New data is always written to every - // going-to-be-empty slot (we keep track of which ones - // are actually useful with the occupancy bits). On a - // read we shift occupied slots. - // - // The exception is the last slot, which always gets - // new data when it is unoccupied. - // -------------------------------------------------- - for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg - always @(posedge clk or posedge reset) begin - if (reset) begin - mem[i] <= 0; - end - else if (read || !mem_used[i]) begin - if (!mem_used[i+1]) - mem[i] <= in_payload; - else - mem[i] <= mem[i+1]; - end - end - end - - always @(posedge clk, posedge reset) begin - if (reset) begin - mem[DEPTH-1] <= 0; - end - else begin - if (!mem_used[DEPTH-1]) - mem[DEPTH-1] <= in_payload; - - if (DEPTH == 1) begin - if (write) - mem[DEPTH-1] <= in_payload; - end - end - end - - end - endgenerate - - assign read = internal_out_ready && internal_out_valid && ok_to_forward; - assign write = in_ready && in_valid; - - // -------------------------------------------------- - // Pointer Management - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - assign incremented_wr_ptr = wr_ptr + 1'b1; - assign incremented_rd_ptr = rd_ptr + 1'b1; - assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; - assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; - - always @(posedge clk or posedge reset) begin - if (reset) begin - wr_ptr <= 0; - rd_ptr <= 0; - end - else begin - wr_ptr <= next_wr_ptr; - rd_ptr <= next_rd_ptr; - end - end - - end else begin - - // -------------------------------------------------- - // Shift Register Occupancy Bits - // - // Consider a 4-deep FIFO with 2 entries: 0011 - // On a read and write, do not modify the bits. - // On a write, left-shift the bits to get 0111. - // On a read, right-shift the bits to get 0001. - // - // Also, on a write we set bit0 (the head), while - // clearing the tail on a read. - // -------------------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[0] <= 0; - end - else begin - if (write ^ read) begin - if (read) begin - if (DEPTH > 1) - mem_used[0] <= mem_used[1]; - else - mem_used[0] <= 0; - end - if (write) - mem_used[0] <= 1; - end - end - end - - if (DEPTH > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - mem_used[DEPTH-1] <= 0; - end - else begin - if (write ^ read) begin - mem_used[DEPTH-1] <= 0; - if (write) - mem_used[DEPTH-1] <= mem_used[DEPTH-2]; - end - end - end - end - - for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic - always @(posedge clk, posedge reset) begin - if (reset) begin - mem_used[i] <= 0; - end - else begin - if (write ^ read) begin - if (read) - mem_used[i] <= mem_used[i+1]; - if (write) - mem_used[i] <= mem_used[i-1]; - end - end - end - end - - end - endgenerate - - - // -------------------------------------------------- - // Memory FIFO Status Management - // - // Generates the full and empty signals from the - // pointers. The FIFO is full when the next write - // pointer will be equal to the read pointer after - // a write. Reading from a FIFO clears full. - // - // The FIFO is empty when the next read pointer will - // be equal to the write pointer after a read. Writing - // to a FIFO clears empty. - // - // A simultaneous read and write must not change any of - // the empty or full flags unless there is a drop on error event. - // -------------------------------------------------- - generate if (USE_MEMORY_BLOCKS == 1) begin - - always @* begin - next_full = full; - next_empty = empty; - - if (read && !write) begin - next_full = 1'b0; - - if (incremented_rd_ptr == wr_ptr) - next_empty = 1'b1; - end - - if (write && !read) begin - if (!drop_on_error) - next_empty = 1'b0; - else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo - next_empty = 1'b1; - - if (incremented_wr_ptr == rd_ptr && !drop_on_error) - next_full = 1'b1; - end - - if (write && read && drop_on_error) begin - if (sop_ptr == next_rd_ptr) - next_empty = 1'b1; - end - end - - always @(posedge clk or posedge reset) begin - if (reset) begin - empty <= 1; - full <= 0; - end - else begin - empty <= next_empty; - full <= next_full; - end - end - - end else begin - // -------------------------------------------------- - // Register FIFO Status Management - // - // Full when the tail occupancy bit is 1. Empty when - // the head occupancy bit is 0. - // -------------------------------------------------- - always @* begin - full = mem_used[DEPTH-1]; - empty = !mem_used[0]; - - // ------------------------------------------ - // For a single slot FIFO, reading clears the - // full status immediately. - // ------------------------------------------ - if (DEPTH == 1) - full = mem_used[0] && !read; - - internal_out_payload = mem[0]; - - // ------------------------------------------ - // Writes clear empty immediately for lookahead modes. - // Note that we use in_valid instead of write to avoid - // combinational loops (in lookahead mode, qualifying - // with in_ready is meaningless). - // - // In a 1-deep FIFO, a possible combinational loop runs - // from write -> out_valid -> out_ready -> write - // ------------------------------------------ - if (EMPTY_LATENCY == 0) begin - empty = !mem_used[0] && !in_valid; - - if (!mem_used[0] && in_valid) - internal_out_payload = in_payload; - end - end - - end - endgenerate - - // -------------------------------------------------- - // Avalon-ST Signals - // - // The in_ready signal is straightforward. - // - // To match memory latency when empty latency > 1, - // out_valid assertions must be delayed by one clock - // cycle. - // - // Note: out_valid deassertions must not be delayed or - // the FIFO will underflow. - // -------------------------------------------------- - assign in_ready = !full; - assign internal_out_ready = out_ready || !out_valid; - - generate if (EMPTY_LATENCY > 1) begin - always @(posedge clk or posedge reset) begin - if (reset) - internal_out_valid <= 0; - else begin - internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; - - if (read) begin - if (incremented_rd_ptr == wr_ptr) - internal_out_valid <= 1'b0; - end - end - end - end else begin - always @* begin - internal_out_valid = !empty & ok_to_forward; - end - end - endgenerate - - // -------------------------------------------------- - // Single Output Pipeline Stage - // - // This output pipeline stage is enabled if the FIFO's - // empty latency is set to 3 (default). It is disabled - // for all other allowed latencies. - // - // Reason: The memory outputs are unregistered, so we have to - // register the output or fmax will drop if combinatorial - // logic is present on the output datapath. - // - // Q: The Avalon-ST spec says that I have to register my outputs - // But isn't the memory counted as a register? - // A: The path from the address lookup to the memory output is - // slow. Registering the memory outputs is a good idea. - // - // The registers get packed into the memory by the fitter - // which means minimal resources are consumed (the result - // is a altsyncram with registered outputs, available on - // all modern Altera devices). - // - // This output stage acts as an extra slot in the FIFO, - // and complicates the fill level. - // -------------------------------------------------- - generate if (EMPTY_LATENCY == 3) begin - always @(posedge clk or posedge reset) begin - if (reset) begin - out_valid <= 0; - out_payload <= 0; - end - else begin - if (internal_out_ready) begin - out_valid <= internal_out_valid & ok_to_forward; - out_payload <= internal_out_payload; - end - end - end - end - else begin - always @* begin - out_valid = internal_out_valid; - out_payload = internal_out_payload; - end - end - endgenerate - - // -------------------------------------------------- - // Fill Level - // - // The fill level is calculated from the next write - // and read pointers to avoid unnecessary latency. - // - // If the output pipeline is enabled, the fill level - // must account for it, or we'll always be off by one. - // This may, or may not be important depending on the - // application. - // - // For now, we'll always calculate the exact fill level - // at the cost of an extra adder when the output stage - // is enabled. - // -------------------------------------------------- - generate if (USE_FILL_LEVEL) begin - wire [31:0] depth32; - assign depth32 = DEPTH; - always @(posedge clk or posedge reset) begin - if (reset) - fifo_fill_level <= 0; - else if (next_full & !drop_on_error) - fifo_fill_level <= depth32[ADDR_WIDTH:0]; - else begin - fifo_fill_level[ADDR_WIDTH] <= 1'b0; - fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; - end - end - - always @* begin - fill_level = fifo_fill_level; - - if (EMPTY_LATENCY == 3) - fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; - end - end - else begin - initial fill_level = 0; - end - endgenerate - - generate if (USE_ALMOST_FULL_IF) begin - assign almost_full_data = (fill_level >= almost_full_threshold); - end - else - assign almost_full_data = 0; - endgenerate - - generate if (USE_ALMOST_EMPTY_IF) begin - assign almost_empty_data = (fill_level <= almost_empty_threshold); - end - else - assign almost_empty_data = 0; - endgenerate - - // -------------------------------------------------- - // Avalon-MM Status & Control Connection Point - // - // Register map: - // - // | Addr | RW | 31 - 0 | - // | 0 | R | Fill level | - // - // The registering of this connection point means - // that there is a cycle of latency between - // reads/writes and the updating of the fill level. - // -------------------------------------------------- - generate if (USE_STORE_FORWARD) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - cut_through_threshold <= 0; - drop_on_error_en <= 0; - csr_readdata <= 0; - pkt_mode <= 1'b1; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b100) begin - cut_through_threshold <= csr_writedata[23:0]; - pkt_mode <= (csr_writedata[23:0] == 0); - end - if(csr_address == 3'b101) - drop_on_error_en <= csr_writedata[0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - if (csr_address == 4) - csr_readdata <= {8'b0, cut_through_threshold}; - if (csr_address == 5) - csr_readdata <= {31'b0, drop_on_error_en}; - end - end - end - end - else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin - assign max_fifo_size = FIFO_DEPTH - 1; - always @(posedge clk or posedge reset) begin - if (reset) begin - almost_full_threshold <= max_fifo_size[23 : 0]; - almost_empty_threshold <= 0; - csr_readdata <= 0; - end - else begin - if (csr_write) begin - if(csr_address == 3'b010) - almost_full_threshold <= csr_writedata[23:0]; - if(csr_address == 3'b011) - almost_empty_threshold <= csr_writedata[23:0]; - end - - if (csr_read) begin - csr_readdata <= 32'b0; - if (csr_address == 0) - csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; - if (csr_address == 2) - csr_readdata <= {8'b0, almost_full_threshold}; - if (csr_address == 3) - csr_readdata <= {8'b0, almost_empty_threshold}; - end - end - end - end - else begin - always @(posedge clk or posedge reset) begin - if (reset) begin - csr_readdata <= 0; - end - else if (csr_read) begin - csr_readdata <= 0; - - if (csr_address == 0) - csr_readdata <= fill_level; - end - end - end - endgenerate - - // -------------------------------------------------- - // Store and forward logic - // -------------------------------------------------- - // if the fifo gets full before the entire packet or the - // cut-threshold condition is met then start sending out - // data in order to avoid dead-lock situation - - generate if (USE_STORE_FORWARD) begin - assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; - assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); - assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : - ~wait_for_threshold) | fifo_too_small_r; - assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; - assign in_pkt_start = in_valid & in_ready & in_startofpacket; - assign in_pkt_error = in_valid & in_ready & |in_error; - assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; - assign out_pkt_leave = out_valid & out_ready & out_endofpacket; - assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; - - // count packets coming and going into the fifo - always @(posedge clk or posedge reset) begin - if (reset) begin - pkt_cnt <= 0; - pkt_cnt_r <= 0; - pkt_cnt_plusone <= 1; - pkt_cnt_minusone <= 0; - pkt_cnt_changed <= 0; - pkt_has_started <= 0; - sop_has_left_fifo <= 0; - fifo_too_small_r <= 0; - pkt_cnt_eq_zero <= 1'b1; - pkt_cnt_eq_one <= 1'b0; - fifo_fill_level_lt_cut_through_threshold <= 1'b1; - end - else begin - fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; - fifo_too_small_r <= fifo_too_small; - pkt_cnt_plusone <= pkt_cnt + 1'b1; - pkt_cnt_minusone <= pkt_cnt - 1'b1; - pkt_cnt_r <= pkt_cnt; - pkt_cnt_changed <= 1'b0; - - if( in_pkt_eop_arrive ) - sop_has_left_fifo <= 1'b0; - else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) - sop_has_left_fifo <= 1'b1; - - if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; - pkt_cnt_eq_zero <= 0; - if (pkt_cnt == 0) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin - pkt_cnt_changed <= 1'b1; - pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; - if (pkt_cnt == 1) - pkt_cnt_eq_zero <= 1'b1; - else - pkt_cnt_eq_zero <= 1'b0; - if (pkt_cnt == 2) - pkt_cnt_eq_one <= 1'b1; - else - pkt_cnt_eq_one <= 1'b0; - end - - if (in_pkt_start) - pkt_has_started <= 1'b1; - else if (in_pkt_eop_arrive) - pkt_has_started <= 1'b0; - end - end - - // drop on error logic - always @(posedge clk or posedge reset) begin - if (reset) begin - sop_ptr <= 0; - error_in_pkt <= 0; - end - else begin - // save the location of the SOP - if ( in_pkt_start ) - sop_ptr <= wr_ptr; - - // remember if error in pkt - // log error only if packet has already started - if (in_pkt_eop_arrive) - error_in_pkt <= 1'b0; - else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) - error_in_pkt <= 1'b1; - end - end - assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & - ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); - - end - else begin - assign ok_to_forward = 1'b1; - assign drop_on_error = 1'b0; - end - endgenerate - - - // -------------------------------------------------- - // Calculates the log2ceil of the input value - // -------------------------------------------------- - function integer log2ceil; - input integer val; - integer i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule +// ----------------------------------------------------------- +// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your +// use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any +// output files any of the foregoing (including device programming or +// simulation files), and any associated documentation or information are +// expressly subject to the terms and conditions of the Altera Program +// License Subscription Agreement or other applicable license agreement, +// including, without limitation, that your use is for the sole purpose +// of programming logic devices manufactured by Altera and sold by Altera +// or its authorized distributors. Please refer to the applicable +// agreement for further details. +// +// Description: Single clock Avalon-ST FIFO. +// ----------------------------------------------------------- + +`timescale 1 ns / 1 ns + + +//altera message_off 10036 +module altera_avalon_sc_fifo +#( + // -------------------------------------------------- + // Parameters + // -------------------------------------------------- + parameter SYMBOLS_PER_BEAT = 1, + parameter BITS_PER_SYMBOL = 8, + parameter FIFO_DEPTH = 16, + parameter CHANNEL_WIDTH = 0, + parameter ERROR_WIDTH = 0, + parameter USE_PACKETS = 0, + parameter USE_FILL_LEVEL = 0, + parameter USE_STORE_FORWARD = 0, + parameter USE_ALMOST_FULL_IF = 0, + parameter USE_ALMOST_EMPTY_IF = 0, + + // -------------------------------------------------- + // Empty latency is defined as the number of cycles + // required for a write to deassert the empty flag. + // For example, a latency of 1 means that the empty + // flag is deasserted on the cycle after a write. + // + // Another way to think of it is the latency for a + // write to propagate to the output. + // + // An empty latency of 0 implies lookahead, which is + // only implemented for the register-based FIFO. + // -------------------------------------------------- + parameter EMPTY_LATENCY = 3, + parameter USE_MEMORY_BLOCKS = 1, + + // -------------------------------------------------- + // Internal Parameters + // -------------------------------------------------- + parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) +) +( + // -------------------------------------------------- + // Ports + // -------------------------------------------------- + input clk, + input reset, + + input [DATA_WIDTH-1: 0] in_data, + input in_valid, + input in_startofpacket, + input in_endofpacket, + input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, + input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, + input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, + output in_ready, + + output [DATA_WIDTH-1 : 0] out_data, + output reg out_valid, + output out_startofpacket, + output out_endofpacket, + output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, + output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, + output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, + input out_ready, + + input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, + input csr_write, + input csr_read, + input [31 : 0] csr_writedata, + output reg [31 : 0] csr_readdata, + + output wire almost_full_data, + output wire almost_empty_data +); + + // -------------------------------------------------- + // Local Parameters + // -------------------------------------------------- + localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); + localparam DEPTH = FIFO_DEPTH; + localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; + localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? + 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; + + // -------------------------------------------------- + // Internal Signals + // -------------------------------------------------- + genvar i; + + reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; + reg [ADDR_WIDTH-1 : 0] wr_ptr; + reg [ADDR_WIDTH-1 : 0] rd_ptr; + reg [DEPTH-1 : 0] mem_used; + + wire [ADDR_WIDTH-1 : 0] next_wr_ptr; + wire [ADDR_WIDTH-1 : 0] next_rd_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; + + wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; + + wire read; + wire write; + + reg empty; + reg next_empty; + reg full; + reg next_full; + + wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; + wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; + wire [PAYLOAD_WIDTH-1 : 0] in_payload; + reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; + reg [PAYLOAD_WIDTH-1 : 0] out_payload; + + reg internal_out_valid; + wire internal_out_ready; + + reg [ADDR_WIDTH : 0] fifo_fill_level; + reg [ADDR_WIDTH : 0] fill_level; + + reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; + reg [23:0] almost_full_threshold; + reg [23:0] almost_empty_threshold; + reg [23:0] cut_through_threshold; + reg [15:0] pkt_cnt; + reg [15:0] pkt_cnt_r; + reg [15:0] pkt_cnt_plusone; + reg [15:0] pkt_cnt_minusone; + reg drop_on_error_en; + reg error_in_pkt; + reg pkt_has_started; + reg sop_has_left_fifo; + reg fifo_too_small_r; + reg pkt_cnt_eq_zero; + reg pkt_cnt_eq_one; + reg pkt_cnt_changed; + + wire wait_for_threshold; + reg pkt_mode; + wire wait_for_pkt; + wire ok_to_forward; + wire in_pkt_eop_arrive; + wire out_pkt_leave; + wire in_pkt_start; + wire in_pkt_error; + wire drop_on_error; + wire fifo_too_small; + wire out_pkt_sop_leave; + wire [31:0] max_fifo_size; + reg fifo_fill_level_lt_cut_through_threshold; + + // -------------------------------------------------- + // Define Payload + // + // Icky part where we decide which signals form the + // payload to the FIFO with generate blocks. + // -------------------------------------------------- + generate + if (EMPTY_WIDTH > 0) begin + assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; + assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; + end + else begin + assign out_empty = in_error; + assign in_packet_signals = {in_startofpacket, in_endofpacket}; + assign {out_startofpacket, out_endofpacket} = out_packet_signals; + end + endgenerate + + generate + if (USE_PACKETS) begin + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; + assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data, in_error}; + assign {out_packet_signals, out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_channel}; + assign {out_packet_signals, out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data}; + assign {out_packet_signals, out_data} = out_payload; + end + end + end + else begin + assign out_packet_signals = 0; + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_error, in_channel}; + assign {out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_data, in_error}; + assign {out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_channel}; + assign {out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = in_data; + assign out_data = out_payload; + end + end + end + endgenerate + + // -------------------------------------------------- + // Memory-based FIFO storage + // + // To allow a ready latency of 0, the read index is + // obtained from the next read pointer and memory + // outputs are unregistered. + // + // If the empty latency is 1, we infer bypass logic + // around the memory so writes propagate to the + // outputs on the next cycle. + // + // Do not change the way this is coded: Quartus needs + // a perfect match to the template, and any attempt to + // refactor the two always blocks into one will break + // memory inference. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + if (EMPTY_LATENCY == 1) begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] = in_payload; + + internal_out_payload = mem[mem_rd_ptr]; + end + + end else begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] <= in_payload; + + internal_out_payload <= mem[mem_rd_ptr]; + end + + end + + assign mem_rd_ptr = next_rd_ptr; + + end else begin + + // -------------------------------------------------- + // Register-based FIFO storage + // + // Uses a shift register as the storage element. Each + // shift register slot has a bit which indicates if + // the slot is occupied (credit to Sam H for the idea). + // The occupancy bits are contiguous and start from the + // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep + // FIFO. + // + // Each slot is enabled during a read or when it + // is unoccupied. New data is always written to every + // going-to-be-empty slot (we keep track of which ones + // are actually useful with the occupancy bits). On a + // read we shift occupied slots. + // + // The exception is the last slot, which always gets + // new data when it is unoccupied. + // -------------------------------------------------- + for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg + always @(posedge clk or posedge reset) begin + if (reset) begin + mem[i] <= 0; + end + else if (read || !mem_used[i]) begin + if (!mem_used[i+1]) + mem[i] <= in_payload; + else + mem[i] <= mem[i+1]; + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + mem[DEPTH-1] <= 0; + end + else begin + if (!mem_used[DEPTH-1]) + mem[DEPTH-1] <= in_payload; + + if (DEPTH == 1) begin + if (write) + mem[DEPTH-1] <= in_payload; + end + end + end + + end + endgenerate + + assign read = internal_out_ready && internal_out_valid && ok_to_forward; + assign write = in_ready && in_valid; + + // -------------------------------------------------- + // Pointer Management + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + + end else begin + + // -------------------------------------------------- + // Shift Register Occupancy Bits + // + // Consider a 4-deep FIFO with 2 entries: 0011 + // On a read and write, do not modify the bits. + // On a write, left-shift the bits to get 0111. + // On a read, right-shift the bits to get 0001. + // + // Also, on a write we set bit0 (the head), while + // clearing the tail on a read. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[0] <= 0; + end + else begin + if (write ^ read) begin + if (read) begin + if (DEPTH > 1) + mem_used[0] <= mem_used[1]; + else + mem_used[0] <= 0; + end + if (write) + mem_used[0] <= 1; + end + end + end + + if (DEPTH > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[DEPTH-1] <= 0; + end + else begin + if (write ^ read) begin + mem_used[DEPTH-1] <= 0; + if (write) + mem_used[DEPTH-1] <= mem_used[DEPTH-2]; + end + end + end + end + + for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic + always @(posedge clk, posedge reset) begin + if (reset) begin + mem_used[i] <= 0; + end + else begin + if (write ^ read) begin + if (read) + mem_used[i] <= mem_used[i+1]; + if (write) + mem_used[i] <= mem_used[i-1]; + end + end + end + end + + end + endgenerate + + + // -------------------------------------------------- + // Memory FIFO Status Management + // + // Generates the full and empty signals from the + // pointers. The FIFO is full when the next write + // pointer will be equal to the read pointer after + // a write. Reading from a FIFO clears full. + // + // The FIFO is empty when the next read pointer will + // be equal to the write pointer after a read. Writing + // to a FIFO clears empty. + // + // A simultaneous read and write must not change any of + // the empty or full flags unless there is a drop on error event. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + always @* begin + next_full = full; + next_empty = empty; + + if (read && !write) begin + next_full = 1'b0; + + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + + if (write && !read) begin + if (!drop_on_error) + next_empty = 1'b0; + else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo + next_empty = 1'b1; + + if (incremented_wr_ptr == rd_ptr && !drop_on_error) + next_full = 1'b1; + end + + if (write && read && drop_on_error) begin + if (sop_ptr == next_rd_ptr) + next_empty = 1'b1; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + empty <= 1; + full <= 0; + end + else begin + empty <= next_empty; + full <= next_full; + end + end + + end else begin + // -------------------------------------------------- + // Register FIFO Status Management + // + // Full when the tail occupancy bit is 1. Empty when + // the head occupancy bit is 0. + // -------------------------------------------------- + always @* begin + full = mem_used[DEPTH-1]; + empty = !mem_used[0]; + + // ------------------------------------------ + // For a single slot FIFO, reading clears the + // full status immediately. + // ------------------------------------------ + if (DEPTH == 1) + full = mem_used[0] && !read; + + internal_out_payload = mem[0]; + + // ------------------------------------------ + // Writes clear empty immediately for lookahead modes. + // Note that we use in_valid instead of write to avoid + // combinational loops (in lookahead mode, qualifying + // with in_ready is meaningless). + // + // In a 1-deep FIFO, a possible combinational loop runs + // from write -> out_valid -> out_ready -> write + // ------------------------------------------ + if (EMPTY_LATENCY == 0) begin + empty = !mem_used[0] && !in_valid; + + if (!mem_used[0] && in_valid) + internal_out_payload = in_payload; + end + end + + end + endgenerate + + // -------------------------------------------------- + // Avalon-ST Signals + // + // The in_ready signal is straightforward. + // + // To match memory latency when empty latency > 1, + // out_valid assertions must be delayed by one clock + // cycle. + // + // Note: out_valid deassertions must not be delayed or + // the FIFO will underflow. + // -------------------------------------------------- + assign in_ready = !full; + assign internal_out_ready = out_ready || !out_valid; + + generate if (EMPTY_LATENCY > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) + internal_out_valid <= 0; + else begin + internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; + + if (read) begin + if (incremented_rd_ptr == wr_ptr) + internal_out_valid <= 1'b0; + end + end + end + end else begin + always @* begin + internal_out_valid = !empty & ok_to_forward; + end + end + endgenerate + + // -------------------------------------------------- + // Single Output Pipeline Stage + // + // This output pipeline stage is enabled if the FIFO's + // empty latency is set to 3 (default). It is disabled + // for all other allowed latencies. + // + // Reason: The memory outputs are unregistered, so we have to + // register the output or fmax will drop if combinatorial + // logic is present on the output datapath. + // + // Q: The Avalon-ST spec says that I have to register my outputs + // But isn't the memory counted as a register? + // A: The path from the address lookup to the memory output is + // slow. Registering the memory outputs is a good idea. + // + // The registers get packed into the memory by the fitter + // which means minimal resources are consumed (the result + // is a altsyncram with registered outputs, available on + // all modern Altera devices). + // + // This output stage acts as an extra slot in the FIFO, + // and complicates the fill level. + // -------------------------------------------------- + generate if (EMPTY_LATENCY == 3) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + out_valid <= 0; + out_payload <= 0; + end + else begin + if (internal_out_ready) begin + out_valid <= internal_out_valid & ok_to_forward; + out_payload <= internal_out_payload; + end + end + end + end + else begin + always @* begin + out_valid = internal_out_valid; + out_payload = internal_out_payload; + end + end + endgenerate + + // -------------------------------------------------- + // Fill Level + // + // The fill level is calculated from the next write + // and read pointers to avoid unnecessary latency. + // + // If the output pipeline is enabled, the fill level + // must account for it, or we'll always be off by one. + // This may, or may not be important depending on the + // application. + // + // For now, we'll always calculate the exact fill level + // at the cost of an extra adder when the output stage + // is enabled. + // -------------------------------------------------- + generate if (USE_FILL_LEVEL) begin + wire [31:0] depth32; + assign depth32 = DEPTH; + always @(posedge clk or posedge reset) begin + if (reset) + fifo_fill_level <= 0; + else if (next_full & !drop_on_error) + fifo_fill_level <= depth32[ADDR_WIDTH:0]; + else begin + fifo_fill_level[ADDR_WIDTH] <= 1'b0; + fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; + end + end + + always @* begin + fill_level = fifo_fill_level; + + if (EMPTY_LATENCY == 3) + fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; + end + end + else begin + initial fill_level = 0; + end + endgenerate + + generate if (USE_ALMOST_FULL_IF) begin + assign almost_full_data = (fill_level >= almost_full_threshold); + end + else + assign almost_full_data = 0; + endgenerate + + generate if (USE_ALMOST_EMPTY_IF) begin + assign almost_empty_data = (fill_level <= almost_empty_threshold); + end + else + assign almost_empty_data = 0; + endgenerate + + // -------------------------------------------------- + // Avalon-MM Status & Control Connection Point + // + // Register map: + // + // | Addr | RW | 31 - 0 | + // | 0 | R | Fill level | + // + // The registering of this connection point means + // that there is a cycle of latency between + // reads/writes and the updating of the fill level. + // -------------------------------------------------- + generate if (USE_STORE_FORWARD) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + cut_through_threshold <= 0; + drop_on_error_en <= 0; + csr_readdata <= 0; + pkt_mode <= 1'b1; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b100) begin + cut_through_threshold <= csr_writedata[23:0]; + pkt_mode <= (csr_writedata[23:0] == 0); + end + if(csr_address == 3'b101) + drop_on_error_en <= csr_writedata[0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + if (csr_address == 4) + csr_readdata <= {8'b0, cut_through_threshold}; + if (csr_address == 5) + csr_readdata <= {31'b0, drop_on_error_en}; + end + end + end + end + else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + csr_readdata <= 0; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + end + end + end + end + else begin + always @(posedge clk or posedge reset) begin + if (reset) begin + csr_readdata <= 0; + end + else if (csr_read) begin + csr_readdata <= 0; + + if (csr_address == 0) + csr_readdata <= fill_level; + end + end + end + endgenerate + + // -------------------------------------------------- + // Store and forward logic + // -------------------------------------------------- + // if the fifo gets full before the entire packet or the + // cut-threshold condition is met then start sending out + // data in order to avoid dead-lock situation + + generate if (USE_STORE_FORWARD) begin + assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; + assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); + assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : + ~wait_for_threshold) | fifo_too_small_r; + assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; + assign in_pkt_start = in_valid & in_ready & in_startofpacket; + assign in_pkt_error = in_valid & in_ready & |in_error; + assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; + assign out_pkt_leave = out_valid & out_ready & out_endofpacket; + assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; + + // count packets coming and going into the fifo + always @(posedge clk or posedge reset) begin + if (reset) begin + pkt_cnt <= 0; + pkt_cnt_r <= 0; + pkt_cnt_plusone <= 1; + pkt_cnt_minusone <= 0; + pkt_cnt_changed <= 0; + pkt_has_started <= 0; + sop_has_left_fifo <= 0; + fifo_too_small_r <= 0; + pkt_cnt_eq_zero <= 1'b1; + pkt_cnt_eq_one <= 1'b0; + fifo_fill_level_lt_cut_through_threshold <= 1'b1; + end + else begin + fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; + fifo_too_small_r <= fifo_too_small; + pkt_cnt_plusone <= pkt_cnt + 1'b1; + pkt_cnt_minusone <= pkt_cnt - 1'b1; + pkt_cnt_r <= pkt_cnt; + pkt_cnt_changed <= 1'b0; + + if( in_pkt_eop_arrive ) + sop_has_left_fifo <= 1'b0; + else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) + sop_has_left_fifo <= 1'b1; + + if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; + pkt_cnt_eq_zero <= 0; + if (pkt_cnt == 0) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; + if (pkt_cnt == 1) + pkt_cnt_eq_zero <= 1'b1; + else + pkt_cnt_eq_zero <= 1'b0; + if (pkt_cnt == 2) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + + if (in_pkt_start) + pkt_has_started <= 1'b1; + else if (in_pkt_eop_arrive) + pkt_has_started <= 1'b0; + end + end + + // drop on error logic + always @(posedge clk or posedge reset) begin + if (reset) begin + sop_ptr <= 0; + error_in_pkt <= 0; + end + else begin + // save the location of the SOP + if ( in_pkt_start ) + sop_ptr <= wr_ptr; + + // remember if error in pkt + // log error only if packet has already started + if (in_pkt_eop_arrive) + error_in_pkt <= 1'b0; + else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) + error_in_pkt <= 1'b1; + end + end + assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & + ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); + + end + else begin + assign ok_to_forward = 1'b1; + assign drop_on_error = 1'b0; + end + endgenerate + + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + integer i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv b/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv index 9edba1d..00dc788 100644 --- a/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv +++ b/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv @@ -11,260 +11,260 @@ // agreement for further details. -// (C) 2001-2010 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ -// $Revision: #3 $ -// $Date: 2010/07/07 $ -// $Author: jyeap $ - -/* ----------------------------------------------------------------------- -Round-robin/fixed arbitration implementation. - -Q: how do you find the least-significant set-bit in an n-bit binary number, X? - -A: M = X & (~X + 1) - -Example: X = 101000100 - 101000100 & - 010111011 + 1 = - - 101000100 & - 010111100 = - ----------- - 000000100 - -The method can be generalized to find the first set-bit -at a bit index no lower than bit-index N, simply by adding -2**N rather than 1. - - -Q: how does this relate to round-robin arbitration? -A: -Let X be the concatenation of all request signals. -Let the number to be added to X (hereafter called the -top_priority) initialize to 1, and be assigned from the -concatenation of the previous saved-grant, left-rotated -by one position, each time arbitration occurs. The -concatenation of grants is then M. - -Problem: consider this case: - -top_priority = 010000 -request = 001001 -~request + top_priority = 000110 -next_grant = 000000 <- no one is granted! - -There was no "set bit at a bit index no lower than bit-index 4", so -the result was 0. - -We need to propagate the carry out from (~request + top_priority) to the LSB, so -that the sum becomes 000111, and next_grant is 000001. This operation could be -called a "circular add". - -A bit of experimentation on the circular add reveals a significant amount of -delay in exiting and re-entering the carry chain - this will vary with device -family. Quartus also reports a combinational loop warning. Finally, -Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But -Modelsim _doesn't_ report a combinational loop!) - -An alternate solution: concatenate the request vector with itself, and OR -corresponding bits from the top and bottom halves to determine next_grant. - -Example: - -top_priority = 010000 -{request, request} = 001001 001001 -{~request, ~request} + top_priority = 110111 000110 -result of & operation = 000001 000000 -next_grant = 000001 - -Notice that if request = 0, the sum operation will overflow, but we can ignore -this; the next_grant result is 0 (no one granted), as you might expect. -In the implementation, the last-granted value must be maintained as -a non-zero value - best probably simply not to update it when no requests -occur. - ------------------------------------------------------------------------ */ - -`timescale 1 ns / 1 ns - -module altera_merlin_arbitrator -#( - parameter NUM_REQUESTERS = 8, - // -------------------------------------- - // Implemented schemes - // "round-robin" - // "fixed-priority" - // "no-arb" - // -------------------------------------- - parameter SCHEME = "round-robin", - parameter PIPELINE = 0 -) -( - input clk, - input reset, - - // -------------------------------------- - // Requests - // -------------------------------------- - input [NUM_REQUESTERS-1:0] request, - - // -------------------------------------- - // Grants - // -------------------------------------- - output [NUM_REQUESTERS-1:0] grant, - - // -------------------------------------- - // Control Signals - // -------------------------------------- - input increment_top_priority, - input save_top_priority -); - - // -------------------------------------- - // Signals - // -------------------------------------- - wire [NUM_REQUESTERS-1:0] top_priority; - reg [NUM_REQUESTERS-1:0] top_priority_reg; - reg [NUM_REQUESTERS-1:0] last_grant; - wire [2*NUM_REQUESTERS-1:0] result; - - // -------------------------------------- - // Scheme Selection - // -------------------------------------- - generate - if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin - assign top_priority = top_priority_reg; - end - else begin - // Fixed arbitration (or single-requester corner case) - assign top_priority = 1'b1; - end - endgenerate - - // -------------------------------------- - // Decision Logic - // -------------------------------------- - altera_merlin_arb_adder - #( - .WIDTH (2 * NUM_REQUESTERS) - ) - adder - ( - .a ({ ~request, ~request }), - .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), - .sum (result) - ); - - - generate if (SCHEME == "no-arb") begin - - // -------------------------------------- - // No arbitration: just wire request directly to grant - // -------------------------------------- - assign grant = request; - - end else begin - // Do the math in double-vector domain - wire [2*NUM_REQUESTERS-1:0] grant_double_vector; - assign grant_double_vector = {request, request} & result; - - // -------------------------------------- - // Extract grant from the top and bottom halves - // of the double vector. - // -------------------------------------- - assign grant = - grant_double_vector[NUM_REQUESTERS - 1 : 0] | - grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; - - end - endgenerate - - // -------------------------------------- - // Left-rotate the last grant vector to create top_priority. - // -------------------------------------- - always @(posedge clk or posedge reset) begin - if (reset) begin - top_priority_reg <= 1'b1; - end - else begin - if (PIPELINE) begin - if (increment_top_priority) begin - top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1]} : top_priority_reg; - end - end else begin - if (save_top_priority) begin - top_priority_reg <= grant; - end - if (increment_top_priority) begin - if (|request) - top_priority_reg <= { grant[NUM_REQUESTERS-2:0], - grant[NUM_REQUESTERS-1] }; - else - top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; - end - end - end - end - -endmodule - -// ---------------------------------------------- -// Adder for the standard arbitrator -// ---------------------------------------------- -module altera_merlin_arb_adder -#( - parameter WIDTH = 8 -) -( - input [WIDTH-1:0] a, - input [WIDTH-1:0] b, - - output [WIDTH-1:0] sum -); - - // ---------------------------------------------- - // Benchmarks indicate that for small widths, the full - // adder has higher fmax because synthesis can merge - // it with the mux, allowing partial decisions to be - // made early. - // - // The magic number is 4 requesters, which means an - // 8 bit adder. - // ---------------------------------------------- - genvar i; - generate if (WIDTH <= 8) begin : full_adder - - wire cout[WIDTH-1:0]; - - assign sum[0] = (a[0] ^ b[0]); - assign cout[0] = (a[0] & b[0]); - - for (i = 1; i < WIDTH; i = i+1) begin : arb - - assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; - assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); - - end - - end else begin : carry_chain - - assign sum = a + b; - - end - endgenerate - -endmodule +// (C) 2001-2010 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ +// $Revision: #3 $ +// $Date: 2010/07/07 $ +// $Author: jyeap $ + +/* ----------------------------------------------------------------------- +Round-robin/fixed arbitration implementation. + +Q: how do you find the least-significant set-bit in an n-bit binary number, X? + +A: M = X & (~X + 1) + +Example: X = 101000100 + 101000100 & + 010111011 + 1 = + + 101000100 & + 010111100 = + ----------- + 000000100 + +The method can be generalized to find the first set-bit +at a bit index no lower than bit-index N, simply by adding +2**N rather than 1. + + +Q: how does this relate to round-robin arbitration? +A: +Let X be the concatenation of all request signals. +Let the number to be added to X (hereafter called the +top_priority) initialize to 1, and be assigned from the +concatenation of the previous saved-grant, left-rotated +by one position, each time arbitration occurs. The +concatenation of grants is then M. + +Problem: consider this case: + +top_priority = 010000 +request = 001001 +~request + top_priority = 000110 +next_grant = 000000 <- no one is granted! + +There was no "set bit at a bit index no lower than bit-index 4", so +the result was 0. + +We need to propagate the carry out from (~request + top_priority) to the LSB, so +that the sum becomes 000111, and next_grant is 000001. This operation could be +called a "circular add". + +A bit of experimentation on the circular add reveals a significant amount of +delay in exiting and re-entering the carry chain - this will vary with device +family. Quartus also reports a combinational loop warning. Finally, +Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But +Modelsim _doesn't_ report a combinational loop!) + +An alternate solution: concatenate the request vector with itself, and OR +corresponding bits from the top and bottom halves to determine next_grant. + +Example: + +top_priority = 010000 +{request, request} = 001001 001001 +{~request, ~request} + top_priority = 110111 000110 +result of & operation = 000001 000000 +next_grant = 000001 + +Notice that if request = 0, the sum operation will overflow, but we can ignore +this; the next_grant result is 0 (no one granted), as you might expect. +In the implementation, the last-granted value must be maintained as +a non-zero value - best probably simply not to update it when no requests +occur. + +----------------------------------------------------------------------- */ + +`timescale 1 ns / 1 ns + +module altera_merlin_arbitrator +#( + parameter NUM_REQUESTERS = 8, + // -------------------------------------- + // Implemented schemes + // "round-robin" + // "fixed-priority" + // "no-arb" + // -------------------------------------- + parameter SCHEME = "round-robin", + parameter PIPELINE = 0 +) +( + input clk, + input reset, + + // -------------------------------------- + // Requests + // -------------------------------------- + input [NUM_REQUESTERS-1:0] request, + + // -------------------------------------- + // Grants + // -------------------------------------- + output [NUM_REQUESTERS-1:0] grant, + + // -------------------------------------- + // Control Signals + // -------------------------------------- + input increment_top_priority, + input save_top_priority +); + + // -------------------------------------- + // Signals + // -------------------------------------- + wire [NUM_REQUESTERS-1:0] top_priority; + reg [NUM_REQUESTERS-1:0] top_priority_reg; + reg [NUM_REQUESTERS-1:0] last_grant; + wire [2*NUM_REQUESTERS-1:0] result; + + // -------------------------------------- + // Scheme Selection + // -------------------------------------- + generate + if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin + assign top_priority = top_priority_reg; + end + else begin + // Fixed arbitration (or single-requester corner case) + assign top_priority = 1'b1; + end + endgenerate + + // -------------------------------------- + // Decision Logic + // -------------------------------------- + altera_merlin_arb_adder + #( + .WIDTH (2 * NUM_REQUESTERS) + ) + adder + ( + .a ({ ~request, ~request }), + .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), + .sum (result) + ); + + + generate if (SCHEME == "no-arb") begin + + // -------------------------------------- + // No arbitration: just wire request directly to grant + // -------------------------------------- + assign grant = request; + + end else begin + // Do the math in double-vector domain + wire [2*NUM_REQUESTERS-1:0] grant_double_vector; + assign grant_double_vector = {request, request} & result; + + // -------------------------------------- + // Extract grant from the top and bottom halves + // of the double vector. + // -------------------------------------- + assign grant = + grant_double_vector[NUM_REQUESTERS - 1 : 0] | + grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; + + end + endgenerate + + // -------------------------------------- + // Left-rotate the last grant vector to create top_priority. + // -------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + top_priority_reg <= 1'b1; + end + else begin + if (PIPELINE) begin + if (increment_top_priority) begin + top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1]} : top_priority_reg; + end + end else begin + if (save_top_priority) begin + top_priority_reg <= grant; + end + if (increment_top_priority) begin + if (|request) + top_priority_reg <= { grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1] }; + else + top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; + end + end + end + end + +endmodule + +// ---------------------------------------------- +// Adder for the standard arbitrator +// ---------------------------------------------- +module altera_merlin_arb_adder +#( + parameter WIDTH = 8 +) +( + input [WIDTH-1:0] a, + input [WIDTH-1:0] b, + + output [WIDTH-1:0] sum +); + + // ---------------------------------------------- + // Benchmarks indicate that for small widths, the full + // adder has higher fmax because synthesis can merge + // it with the mux, allowing partial decisions to be + // made early. + // + // The magic number is 4 requesters, which means an + // 8 bit adder. + // ---------------------------------------------- + genvar i; + generate if (WIDTH <= 8) begin : full_adder + + wire cout[WIDTH-1:0]; + + assign sum[0] = (a[0] ^ b[0]); + assign cout[0] = (a[0] & b[0]); + + for (i = 1; i < WIDTH; i = i+1) begin : arb + + assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; + assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); + + end + + end else begin : carry_chain + + assign sum = a + b; + + end + endgenerate + +endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv b/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv index 30eaf7d..9b49c44 100644 --- a/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +++ b/nios_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv @@ -11,276 +11,276 @@ // agreement for further details. -// (C) 2001-2012 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Burst Uncompressor -// -// Compressed read bursts -> uncompressed -// ------------------------------------------ - -`timescale 1 ns / 1 ns - -module altera_merlin_burst_uncompressor -#( - parameter ADDR_W = 16, - parameter BURSTWRAP_W = 3, - parameter BYTE_CNT_W = 4, - parameter PKT_SYMBOLS = 4, - parameter BURST_SIZE_W = 3 -) -( - input clk, - input reset, - - // sink ST signals - input sink_startofpacket, - input sink_endofpacket, - input sink_valid, - output sink_ready, - - // sink ST "data" - input [ADDR_W - 1: 0] sink_addr, - input [BURSTWRAP_W - 1 : 0] sink_burstwrap, - input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, - input sink_is_compressed, - input [BURST_SIZE_W-1 : 0] sink_burstsize, - - // source ST signals - output source_startofpacket, - output source_endofpacket, - output source_valid, - input source_ready, - - // source ST "data" - output [ADDR_W - 1: 0] source_addr, - output [BURSTWRAP_W - 1 : 0] source_burstwrap, - output [BYTE_CNT_W - 1 : 0] source_byte_cnt, - - // Note: in the slave agent, the output should always be uncompressed. In - // other applications, it may be required to leave-compressed or not. How to - // control? Seems like a simple mux - pass-through if no uncompression is - // required. - output source_is_compressed, - output [BURST_SIZE_W-1 : 0] source_burstsize -); - -//---------------------------------------------------- -// AXSIZE decoding -// -// Turns the axsize value into the actual number of bytes -// being transferred. -// --------------------------------------------------- -function reg[63:0] bytes_in_transfer; - input [2:0] axsize; - case (axsize) - 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; - 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; - 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; - 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; - 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; - 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; - 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; - default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; - endcase - -endfunction - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - // def: Burst Compression. In a merlin network, a compressed burst is one - // which is transmitted in a single beat. Example: read burst. In - // constrast, an uncompressed burst (example: write burst) is transmitted in - // one beat per writedata item. - // - // For compressed bursts which require response packets, burst - // uncompression is required. Concrete example: a read burst of size 8 - // occupies one response-fifo position. When that fifo position reaches the - // front of the FIFO, the slave starts providing the required 8 readdatavalid - // pulses. The 8 return response beats must be provided in a single packet, - // with incrementing address and decrementing byte_cnt fields. Upon receipt - // of the final readdata item of the burst, the response FIFO item is - // retired. - // Burst uncompression logic provides: - // a) 2-state FSM (idle, busy) - // reset to idle state - // transition to busy state for 2nd and subsequent rdv pulses - // - a single-cycle burst (aka non-burst read) causes no transition to - // busy state. - // b) response startofpacket/endofpacket logic. The response FIFO item - // will have sop asserted, and may have eop asserted. (In the case of - // multiple read bursts transmit in the command fabric in a single packet, - // the eop assertion will come in a later FIFO item.) To support packet - // conservation, and emit a well-formed packet on the response fabric, - // i) response fabric startofpacket is asserted only for the first resp. - // beat; - // ii) response fabric endofpacket is asserted only for the last resp. - // beat. - // c) response address field. The response address field contains an - // incrementing sequence, such that each readdata item is associated with - // its slave-map location. N.b. a) computing the address correctly requires - // knowledge of burstwrap behavior b) there may be no clients of the address - // field, which makes this field a good target for optimization. See - // burst_uncompress_address_counter below. - // d) response byte_cnt field. The response byte_cnt field contains a - // decrementing sequence, such that each beat of the response contains the - // count of bytes to follow. In the case of sub-bursts in a single packet, - // the byte_cnt field may decrement down to num_symbols, then back up to - // some value, multiple times in the packet. - - reg burst_uncompress_busy; - reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; - wire first_packet_beat; - wire last_packet_beat; - - assign first_packet_beat = sink_valid & ~burst_uncompress_busy; - - // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to - // the output. - assign source_byte_cnt = - first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; - assign source_valid = sink_valid; - - // Last packet beat is set throughout receipt of an uncompressed read burst - // from the response FIFO - this forces all the burst uncompression machinery - // idle. - assign last_packet_beat = ~sink_is_compressed | - ( - burst_uncompress_busy ? - (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : - sink_valid & (sink_byte_cnt == num_symbols) - ); - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (source_valid & source_ready & sink_valid) begin - // No matter what the current state, last_packet_beat leads to - // idle. - if (last_packet_beat) begin - burst_uncompress_busy <= '0; - burst_uncompress_byte_counter <= '0; - end - else begin - if (burst_uncompress_busy) begin - burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? - (burst_uncompress_byte_counter - num_symbols) : - (sink_byte_cnt - num_symbols); - end - else begin // not busy, at least one more beat to go - burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; - // To do: should busy go true for numsymbols-size compressed - // bursts? - burst_uncompress_busy <= '1; - end - end - end - end - end - - wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; - reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; - reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; - - wire [63:0] decoded_burstsize_wire; - wire [ADDR_W-1:0] decoded_burstsize; - - // The input burstwrap value can be used as a mask against address values, - // but with one caveat: the address width may be (probably is) wider than - // the burstwrap width. The spec says: extend the msb of the burstwrap - // value out over the entire address width (but only if the address width - // actually is wider than the burstwrap width; otherwise it's a 0-width or - // negative range and concatenation multiplier). - assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; - generate - if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend - // Sign-extend, just wires: - assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = - {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; - end - endgenerate - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_base <= '0; - end - else if (first_packet_beat & source_ready) begin - burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; - end - end - - assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits - assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed - - wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = - ( - (first_packet_beat ? - sink_addr : - burst_uncompress_address_offset) + decoded_burstsize - ) & - addr_width_burstwrap; - - always @(posedge clk or posedge reset) begin - if (reset) begin - burst_uncompress_address_offset <= '0; - end - else begin - if (source_ready & source_valid) begin - burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; - // if (first_packet_beat) begin - // burst_uncompress_address_offset <= - // (sink_addr + num_symbols) & addr_width_burstwrap; - // end - // else begin - // burst_uncompress_address_offset <= - // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; - // end - end - end - end - - // On the first packet beat, send the input address out unchanged, - // while values are computed/registered for 2nd and subsequent beats. - assign source_addr = first_packet_beat ? sink_addr : - burst_uncompress_address_base | burst_uncompress_address_offset; - assign source_burstwrap = sink_burstwrap; - assign source_burstsize = sink_burstsize; - - //------------------------------------------------------------------- - // A single (compressed) read burst will have sop/eop in the same beat. - // A sequence of read sub-bursts emitted by a burst adapter in response to a - // single read burst will have sop on the first sub-burst, eop on the last. - // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve - // packet conservation. - assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; - assign source_endofpacket = sink_endofpacket & last_packet_beat; - assign sink_ready = source_valid & source_ready & last_packet_beat; - - // This is correct for the slave agent usage, but won't always be true in the - // width adapter. To do: add an "please uncompress" input, and use it to - // pass-through or modify, and set source_is_compressed accordingly. - assign source_is_compressed = 1'b0; -endmodule - +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Burst Uncompressor +// +// Compressed read bursts -> uncompressed +// ------------------------------------------ + +`timescale 1 ns / 1 ns + +module altera_merlin_burst_uncompressor +#( + parameter ADDR_W = 16, + parameter BURSTWRAP_W = 3, + parameter BYTE_CNT_W = 4, + parameter PKT_SYMBOLS = 4, + parameter BURST_SIZE_W = 3 +) +( + input clk, + input reset, + + // sink ST signals + input sink_startofpacket, + input sink_endofpacket, + input sink_valid, + output sink_ready, + + // sink ST "data" + input [ADDR_W - 1: 0] sink_addr, + input [BURSTWRAP_W - 1 : 0] sink_burstwrap, + input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, + input sink_is_compressed, + input [BURST_SIZE_W-1 : 0] sink_burstsize, + + // source ST signals + output source_startofpacket, + output source_endofpacket, + output source_valid, + input source_ready, + + // source ST "data" + output [ADDR_W - 1: 0] source_addr, + output [BURSTWRAP_W - 1 : 0] source_burstwrap, + output [BYTE_CNT_W - 1 : 0] source_byte_cnt, + + // Note: in the slave agent, the output should always be uncompressed. In + // other applications, it may be required to leave-compressed or not. How to + // control? Seems like a simple mux - pass-through if no uncompression is + // required. + output source_is_compressed, + output [BURST_SIZE_W-1 : 0] source_burstsize +); + +//---------------------------------------------------- +// AXSIZE decoding +// +// Turns the axsize value into the actual number of bytes +// being transferred. +// --------------------------------------------------- +function reg[63:0] bytes_in_transfer; + input [2:0] axsize; + case (axsize) + 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; + 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; + 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; + 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; + 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; + 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; + 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; + default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + endcase + +endfunction + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + // def: Burst Compression. In a merlin network, a compressed burst is one + // which is transmitted in a single beat. Example: read burst. In + // constrast, an uncompressed burst (example: write burst) is transmitted in + // one beat per writedata item. + // + // For compressed bursts which require response packets, burst + // uncompression is required. Concrete example: a read burst of size 8 + // occupies one response-fifo position. When that fifo position reaches the + // front of the FIFO, the slave starts providing the required 8 readdatavalid + // pulses. The 8 return response beats must be provided in a single packet, + // with incrementing address and decrementing byte_cnt fields. Upon receipt + // of the final readdata item of the burst, the response FIFO item is + // retired. + // Burst uncompression logic provides: + // a) 2-state FSM (idle, busy) + // reset to idle state + // transition to busy state for 2nd and subsequent rdv pulses + // - a single-cycle burst (aka non-burst read) causes no transition to + // busy state. + // b) response startofpacket/endofpacket logic. The response FIFO item + // will have sop asserted, and may have eop asserted. (In the case of + // multiple read bursts transmit in the command fabric in a single packet, + // the eop assertion will come in a later FIFO item.) To support packet + // conservation, and emit a well-formed packet on the response fabric, + // i) response fabric startofpacket is asserted only for the first resp. + // beat; + // ii) response fabric endofpacket is asserted only for the last resp. + // beat. + // c) response address field. The response address field contains an + // incrementing sequence, such that each readdata item is associated with + // its slave-map location. N.b. a) computing the address correctly requires + // knowledge of burstwrap behavior b) there may be no clients of the address + // field, which makes this field a good target for optimization. See + // burst_uncompress_address_counter below. + // d) response byte_cnt field. The response byte_cnt field contains a + // decrementing sequence, such that each beat of the response contains the + // count of bytes to follow. In the case of sub-bursts in a single packet, + // the byte_cnt field may decrement down to num_symbols, then back up to + // some value, multiple times in the packet. + + reg burst_uncompress_busy; + reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; + wire first_packet_beat; + wire last_packet_beat; + + assign first_packet_beat = sink_valid & ~burst_uncompress_busy; + + // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to + // the output. + assign source_byte_cnt = + first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; + assign source_valid = sink_valid; + + // Last packet beat is set throughout receipt of an uncompressed read burst + // from the response FIFO - this forces all the burst uncompression machinery + // idle. + assign last_packet_beat = ~sink_is_compressed | + ( + burst_uncompress_busy ? + (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : + sink_valid & (sink_byte_cnt == num_symbols) + ); + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (source_valid & source_ready & sink_valid) begin + // No matter what the current state, last_packet_beat leads to + // idle. + if (last_packet_beat) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (burst_uncompress_busy) begin + burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? + (burst_uncompress_byte_counter - num_symbols) : + (sink_byte_cnt - num_symbols); + end + else begin // not busy, at least one more beat to go + burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; + // To do: should busy go true for numsymbols-size compressed + // bursts? + burst_uncompress_busy <= '1; + end + end + end + end + end + + wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; + reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; + reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; + + wire [63:0] decoded_burstsize_wire; + wire [ADDR_W-1:0] decoded_burstsize; + + // The input burstwrap value can be used as a mask against address values, + // but with one caveat: the address width may be (probably is) wider than + // the burstwrap width. The spec says: extend the msb of the burstwrap + // value out over the entire address width (but only if the address width + // actually is wider than the burstwrap width; otherwise it's a 0-width or + // negative range and concatenation multiplier). + assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; + generate + if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend + // Sign-extend, just wires: + assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = + {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; + end + endgenerate + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_base <= '0; + end + else if (first_packet_beat & source_ready) begin + burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; + end + end + + assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits + assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed + + wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = + ( + (first_packet_beat ? + sink_addr : + burst_uncompress_address_offset) + decoded_burstsize + ) & + addr_width_burstwrap; + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_offset <= '0; + end + else begin + if (source_ready & source_valid) begin + burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; + // if (first_packet_beat) begin + // burst_uncompress_address_offset <= + // (sink_addr + num_symbols) & addr_width_burstwrap; + // end + // else begin + // burst_uncompress_address_offset <= + // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; + // end + end + end + end + + // On the first packet beat, send the input address out unchanged, + // while values are computed/registered for 2nd and subsequent beats. + assign source_addr = first_packet_beat ? sink_addr : + burst_uncompress_address_base | burst_uncompress_address_offset; + assign source_burstwrap = sink_burstwrap; + assign source_burstsize = sink_burstsize; + + //------------------------------------------------------------------- + // A single (compressed) read burst will have sop/eop in the same beat. + // A sequence of read sub-bursts emitted by a burst adapter in response to a + // single read burst will have sop on the first sub-burst, eop on the last. + // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve + // packet conservation. + assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; + assign source_endofpacket = sink_endofpacket & last_packet_beat; + assign sink_ready = source_valid & source_ready & last_packet_beat; + + // This is correct for the slave agent usage, but won't always be true in the + // width adapter. To do: add an "please uncompress" input, and use it to + // pass-through or modify, and set source_is_compressed accordingly. + assign source_is_compressed = 1'b0; +endmodule + diff --git a/nios_system/synthesis/submodules/altera_merlin_master_agent.sv b/nios_system/synthesis/submodules/altera_merlin_master_agent.sv index 305107d..070f26f 100644 --- a/nios_system/synthesis/submodules/altera_merlin_master_agent.sv +++ b/nios_system/synthesis/submodules/altera_merlin_master_agent.sv @@ -11,299 +11,299 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Agent -// -// Converts Avalon-MM transactions into -// Merlin network packets. -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_merlin_master_agent -#( - // ------------------- - // Packet Format Parameters - // ------------------- - parameter PKT_QOS_H = 109, - PKT_QOS_L = 106, - PKT_DATA_SIDEBAND_H = 105, - PKT_DATA_SIDEBAND_L = 98, - PKT_ADDR_SIDEBAND_H = 97, - PKT_ADDR_SIDEBAND_L = 93, - PKT_CACHE_H = 92, - PKT_CACHE_L = 89, - PKT_THREAD_ID_H = 88, - PKT_THREAD_ID_L = 87, - PKT_BEGIN_BURST = 81, - PKT_PROTECTION_H = 80, - PKT_PROTECTION_L = 80, - PKT_BURSTWRAP_H = 79, - PKT_BURSTWRAP_L = 77, - PKT_BYTE_CNT_H = 76, - PKT_BYTE_CNT_L = 74, - PKT_ADDR_H = 73, - PKT_ADDR_L = 42, - PKT_BURST_SIZE_H = 86, - PKT_BURST_SIZE_L = 84, - PKT_BURST_TYPE_H = 94, - PKT_BURST_TYPE_L = 93, - PKT_TRANS_EXCLUSIVE = 83, - PKT_TRANS_LOCK = 82, - PKT_TRANS_COMPRESSED_READ = 41, - PKT_TRANS_POSTED = 40, - PKT_TRANS_WRITE = 39, - PKT_TRANS_READ = 38, - PKT_DATA_H = 37, - PKT_DATA_L = 6, - PKT_BYTEEN_H = 5, - PKT_BYTEEN_L = 2, - PKT_SRC_ID_H = 1, - PKT_SRC_ID_L = 1, - PKT_DEST_ID_H = 0, - PKT_DEST_ID_L = 0, - PKT_RESPONSE_STATUS_L = 110, - PKT_RESPONSE_STATUS_H = 111, - ST_DATA_W = 112, - ST_CHANNEL_W = 1, - - // ------------------- - // Agent Parameters - // ------------------- - AV_BURSTCOUNT_W = 3, - ID = 1, - SUPPRESS_0_BYTEEN_RSP = 1, - BURSTWRAP_VALUE = 4, - CACHE_VALUE = 0, - SECURE_ACCESS_BIT = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - // ------------------- - // Derived Parameters - // ------------------- - PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, - PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, - PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, - PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, - PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 -) -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Avalon-MM Anti-Master - // ------------------- - input [PKT_ADDR_W-1 : 0] av_address, - input av_write, - input av_read, - input [PKT_DATA_W-1 : 0] av_writedata, - output reg [PKT_DATA_W-1 : 0] av_readdata, - output reg av_waitrequest, - output reg av_readdatavalid, - input [PKT_BYTEEN_W-1 : 0] av_byteenable, - input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, - input av_debugaccess, - input av_lock, - output reg [1:0] av_response, - input av_writeresponserequest, - output reg av_writeresponsevalid, - - // ------------------- - // Command Source - // ------------------- - output reg cp_valid, - output reg [ST_DATA_W-1 : 0] cp_data, - output wire cp_startofpacket, - output wire cp_endofpacket, - input cp_ready, - - // ------------------- - // Response Sink - // ------------------- - input rp_valid, - input [ST_DATA_W-1 : 0] rp_data, - input [ST_CHANNEL_W-1 : 0] rp_channel, - input rp_startofpacket, - input rp_endofpacket, - output reg rp_ready -); - // ------------------------------------------------------------ - // Utility Functions - // ------------------------------------------------------------ - function integer clogb2; - input [31:0] value; - begin - for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) - value = value >> 1; - clogb2 = clogb2 - 1; - end - endfunction // clogb2 - - localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); - localparam NUMSYMBOLS = PKT_BYTEEN_W; - localparam BURSTING = (MAX_BURST > NUMSYMBOLS); - localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); - localparam BURST_SIZE = clogb2(NUMSYMBOLS); - - typedef enum bit [1:0] - { - FIXED = 2'b00, - INCR = 2'b01, - WRAP = 2'b10, - OTHER_WRAP = 2'b11 - } MerlinBurstType; - - // -------------------------------------- - // Potential optimization: compare in words to save bits? - // -------------------------------------- - wire is_burst; - assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); - - wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; - wire [31:0] id_int = ID; - wire [2:0] burstsize_sig = BURST_SIZE[2:0]; - wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; - - // -------------------------------------- - // Address alignment - // - // The packet format requires that addresses be aligned to - // the transaction size. - // -------------------------------------- - wire [PKT_ADDR_W-1 : 0] av_address_aligned; - generate - if (NUMSYMBOLS > 1) begin - assign av_address_aligned = - {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; - end - else begin - assign av_address_aligned = av_address; - end - endgenerate - - // -------------------------------------- - // Command & Response Construction - // -------------------------------------- - always @* begin - cp_data = '0; // default assignment; override below as needed. - - cp_data[PKT_PROTECTION_L] = av_debugaccess; - cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) - cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) - cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; - cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; - cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; - cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; - cp_data[PKT_TRANS_LOCK ] = av_lock; - cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; - cp_data[PKT_TRANS_READ ] = av_read; - cp_data[PKT_TRANS_WRITE ] = av_write; - // posted and non-posted write avaiable now - cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; - cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; - cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; - cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; - cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; - cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; - cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; - cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; - cp_data[PKT_QOS_H : PKT_QOS_L] = '0; - cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; - cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; - - av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; - if (USE_WRITERESPONSE || USE_READRESPONSE) - av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; - else - av_response = '0; - - end - - // -------------------------------------- - // Command Control - // -------------------------------------- - always @* begin - cp_valid = 0; - - if (av_write || av_read) - cp_valid = 1; - end - - generate if (BURSTING) begin - reg sop_enable; - - always @(posedge clk, posedge reset) begin - if (reset) begin - sop_enable <= 1'b1; - end - else begin - if (cp_valid && cp_ready) begin - sop_enable <= 1'b0; - if (cp_endofpacket) - sop_enable <= 1'b1; - end - end - end - - assign cp_startofpacket = sop_enable; - assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); - - end - else begin - - assign cp_startofpacket = 1'b1; - assign cp_endofpacket = 1'b1; - - end - endgenerate - - // -------------------------------------- - // Backpressure & Readdatavalid - // -------------------------------------- - reg hold_waitrequest; - - always @ (posedge clk, posedge reset) begin - if (reset) - hold_waitrequest <= 1'b1; - else - hold_waitrequest <= 1'b0; - end - - always @* begin - rp_ready = 1; - av_readdatavalid = 0; - av_writeresponsevalid = 0; - av_waitrequest = hold_waitrequest | !cp_ready; - - // -------------------------------------- - // Currently, responses are _always_ read responses because - // this Avalon agent only issues posted writes, which do - // not have responses. -> not true for now - // Now Avalon supports response, so based on type of transaction - // return, assert correct thing - // -------------------------------------- - if (rp_data[PKT_TRANS_WRITE] == 1) - av_writeresponsevalid = rp_valid; - else - av_readdatavalid = rp_valid; - - if (SUPPRESS_0_BYTEEN_RSP) begin - if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) - av_readdatavalid = 0; - end - end - -endmodule +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Agent +// +// Converts Avalon-MM transactions into +// Merlin network packets. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_agent +#( + // ------------------- + // Packet Format Parameters + // ------------------- + parameter PKT_QOS_H = 109, + PKT_QOS_L = 106, + PKT_DATA_SIDEBAND_H = 105, + PKT_DATA_SIDEBAND_L = 98, + PKT_ADDR_SIDEBAND_H = 97, + PKT_ADDR_SIDEBAND_L = 93, + PKT_CACHE_H = 92, + PKT_CACHE_L = 89, + PKT_THREAD_ID_H = 88, + PKT_THREAD_ID_L = 87, + PKT_BEGIN_BURST = 81, + PKT_PROTECTION_H = 80, + PKT_PROTECTION_L = 80, + PKT_BURSTWRAP_H = 79, + PKT_BURSTWRAP_L = 77, + PKT_BYTE_CNT_H = 76, + PKT_BYTE_CNT_L = 74, + PKT_ADDR_H = 73, + PKT_ADDR_L = 42, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + PKT_BURST_TYPE_H = 94, + PKT_BURST_TYPE_L = 93, + PKT_TRANS_EXCLUSIVE = 83, + PKT_TRANS_LOCK = 82, + PKT_TRANS_COMPRESSED_READ = 41, + PKT_TRANS_POSTED = 40, + PKT_TRANS_WRITE = 39, + PKT_TRANS_READ = 38, + PKT_DATA_H = 37, + PKT_DATA_L = 6, + PKT_BYTEEN_H = 5, + PKT_BYTEEN_L = 2, + PKT_SRC_ID_H = 1, + PKT_SRC_ID_L = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + PKT_RESPONSE_STATUS_L = 110, + PKT_RESPONSE_STATUS_H = 111, + ST_DATA_W = 112, + ST_CHANNEL_W = 1, + + // ------------------- + // Agent Parameters + // ------------------- + AV_BURSTCOUNT_W = 3, + ID = 1, + SUPPRESS_0_BYTEEN_RSP = 1, + BURSTWRAP_VALUE = 4, + CACHE_VALUE = 0, + SECURE_ACCESS_BIT = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + // ------------------- + // Derived Parameters + // ------------------- + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_PROTECTION_W= PKT_PROTECTION_H - PKT_PROTECTION_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, + PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 +) +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Avalon-MM Anti-Master + // ------------------- + input [PKT_ADDR_W-1 : 0] av_address, + input av_write, + input av_read, + input [PKT_DATA_W-1 : 0] av_writedata, + output reg [PKT_DATA_W-1 : 0] av_readdata, + output reg av_waitrequest, + output reg av_readdatavalid, + input [PKT_BYTEEN_W-1 : 0] av_byteenable, + input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, + input av_debugaccess, + input av_lock, + output reg [1:0] av_response, + input av_writeresponserequest, + output reg av_writeresponsevalid, + + // ------------------- + // Command Source + // ------------------- + output reg cp_valid, + output reg [ST_DATA_W-1 : 0] cp_data, + output wire cp_startofpacket, + output wire cp_endofpacket, + input cp_ready, + + // ------------------- + // Response Sink + // ------------------- + input rp_valid, + input [ST_DATA_W-1 : 0] rp_data, + input [ST_CHANNEL_W-1 : 0] rp_channel, + input rp_startofpacket, + input rp_endofpacket, + output reg rp_ready +); + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + function integer clogb2; + input [31:0] value; + begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); + localparam NUMSYMBOLS = PKT_BYTEEN_W; + localparam BURSTING = (MAX_BURST > NUMSYMBOLS); + localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); + localparam BURST_SIZE = clogb2(NUMSYMBOLS); + + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + OTHER_WRAP = 2'b11 + } MerlinBurstType; + + // -------------------------------------- + // Potential optimization: compare in words to save bits? + // -------------------------------------- + wire is_burst; + assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); + + wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; + wire [31:0] id_int = ID; + wire [2:0] burstsize_sig = BURST_SIZE[2:0]; + wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; + + // -------------------------------------- + // Address alignment + // + // The packet format requires that addresses be aligned to + // the transaction size. + // -------------------------------------- + wire [PKT_ADDR_W-1 : 0] av_address_aligned; + generate + if (NUMSYMBOLS > 1) begin + assign av_address_aligned = + {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; + end + else begin + assign av_address_aligned = av_address; + end + endgenerate + + // -------------------------------------- + // Command & Response Construction + // -------------------------------------- + always @* begin + cp_data = '0; // default assignment; override below as needed. + + cp_data[PKT_PROTECTION_L] = av_debugaccess; + cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // Default Non-secured (AXI) + cp_data[PKT_PROTECTION_L+2] = 1'b0; // Default Data access (AXI) + cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; + cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; + cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; + cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; + cp_data[PKT_TRANS_LOCK ] = av_lock; + cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; + cp_data[PKT_TRANS_READ ] = av_read; + cp_data[PKT_TRANS_WRITE ] = av_write; + // posted and non-posted write avaiable now + cp_data[PKT_TRANS_POSTED ] = av_write & !av_writeresponserequest; + cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; + cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; + cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; + cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; + cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; + cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; + cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE[3:0]; + cp_data[PKT_QOS_H : PKT_QOS_L] = '0; + cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; + cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; + + av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; + if (USE_WRITERESPONSE || USE_READRESPONSE) + av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L]; + else + av_response = '0; + + end + + // -------------------------------------- + // Command Control + // -------------------------------------- + always @* begin + cp_valid = 0; + + if (av_write || av_read) + cp_valid = 1; + end + + generate if (BURSTING) begin + reg sop_enable; + + always @(posedge clk, posedge reset) begin + if (reset) begin + sop_enable <= 1'b1; + end + else begin + if (cp_valid && cp_ready) begin + sop_enable <= 1'b0; + if (cp_endofpacket) + sop_enable <= 1'b1; + end + end + end + + assign cp_startofpacket = sop_enable; + assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); + + end + else begin + + assign cp_startofpacket = 1'b1; + assign cp_endofpacket = 1'b1; + + end + endgenerate + + // -------------------------------------- + // Backpressure & Readdatavalid + // -------------------------------------- + reg hold_waitrequest; + + always @ (posedge clk, posedge reset) begin + if (reset) + hold_waitrequest <= 1'b1; + else + hold_waitrequest <= 1'b0; + end + + always @* begin + rp_ready = 1; + av_readdatavalid = 0; + av_writeresponsevalid = 0; + av_waitrequest = hold_waitrequest | !cp_ready; + + // -------------------------------------- + // Currently, responses are _always_ read responses because + // this Avalon agent only issues posted writes, which do + // not have responses. -> not true for now + // Now Avalon supports response, so based on type of transaction + // return, assert correct thing + // -------------------------------------- + if (rp_data[PKT_TRANS_WRITE] == 1) + av_writeresponsevalid = rp_valid; + else + av_readdatavalid = rp_valid; + + if (SUPPRESS_0_BYTEEN_RSP) begin + if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) + av_readdatavalid = 0; + end + end + +endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_master_translator.sv b/nios_system/synthesis/submodules/altera_merlin_master_translator.sv index b2be2d2..a43760f 100644 --- a/nios_system/synthesis/submodules/altera_merlin_master_translator.sv +++ b/nios_system/synthesis/submodules/altera_merlin_master_translator.sv @@ -11,544 +11,544 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// -------------------------------------- -// Merlin Master Translator -// -// Converts Avalon-MM Master Interfaces into -// Avalon-MM Universal Master Interfaces -// -------------------------------------- - -`timescale 1 ns / 1 ns - - - -module altera_merlin_master_translator #( - parameter - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - - //Optional Port Declarations - - USE_BURSTCOUNT = 1, - USE_BEGINBURSTTRANSFER = 0, - USE_BEGINTRANSFER = 0, - USE_CHIPSELECT = 0, - USE_READ = 1, - USE_READDATAVALID = 1, - USE_WRITE = 1, - USE_WAITREQUEST = 1, - USE_WRITERESPONSE = 0, - USE_READRESPONSE = 0, - - AV_REGISTERINCOMINGSIGNALS = 0, - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_CONSTANT_BURST_BEHAVIOR = 1, - AV_BURSTCOUNT_SYMBOLS = 0, - AV_LINEWRAPBURSTS = 0, - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_CONSTANT_BURST_BEHAVIOR = 0 - )( - //Universal Avalon Master - input wire clk, - input wire reset, - output reg uav_write, - output reg uav_read, - output reg [UAV_ADDRESS_W -1 : 0] uav_address, - output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, - output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, - output wire [AV_DATA_W -1 : 0] uav_writedata, - output wire uav_lock, - output wire uav_debugaccess, - output wire uav_clken, - - input wire [ AV_DATA_W -1 : 0] uav_readdata, - input wire uav_readdatavalid, - input wire uav_waitrequest, - input wire [1:0] uav_response, - output reg uav_writeresponserequest, - input wire uav_writeresponsevalid, - - //Avalon-MM !Master - input reg av_write, - input reg av_read, - input wire [AV_ADDRESS_W -1 : 0] av_address, - input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, - input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, - input wire [AV_DATA_W -1 : 0] av_writedata, - input wire av_begintransfer, - input wire av_beginbursttransfer, - input wire av_lock, - input wire av_chipselect, - input wire av_debugaccess, - input wire av_clken, - - output wire [AV_DATA_W -1 : 0] av_readdata, - output wire av_readdatavalid, - output reg av_waitrequest, - output reg [1:0] av_response, - input wire av_writeresponserequest, - output reg av_writeresponsevalid - - ); - - - localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); - localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); - localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; - - localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; - localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; - - - // -1 for burstcount restriction 2^(n-1) - - localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; - localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; - - localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; - localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; - - localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; - localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; - - function integer flog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - if ( i <= 0 ) flog2 = 0; - else begin - for(flog2 = -1; i > 0; flog2 = flog2 + 1) - i = i >> 1; - end - end - - endfunction // flog2 - - function integer clog2; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2 = 0; i > 0; clog2 = clog2 + 1) - i = i >> 1; - end - - endfunction - - function integer pow2; - input [31:0] toShift; - begin - pow2=1; - pow2= pow2 << toShift; - end - endfunction // pow2 - - // ------------------------------------------------- - // Assign some constants to appropriately-sized signals to - // avoid synthesis warnings. This also helps some simulators - // with their inferred sensitivity lists. - // ------------------------------------------------- - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); - wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; - - - reg internal_beginbursttransfer; - reg internal_begintransfer; - reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; - reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; - - - - reg uav_read_pre; - reg uav_write_pre; - reg read_accepted; - - //Passthru assignmenst - - assign uav_writedata = av_writedata; - assign av_readdata = uav_readdata; - assign uav_byteenable = av_byteenable; - assign uav_lock = av_lock; - assign av_readdatavalid = uav_readdatavalid; - assign uav_debugaccess = av_debugaccess; - assign uav_clken = av_clken; - - //Response signals - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) - av_response = '0; - else - av_response = uav_response; - if (USE_WRITERESPONSE) begin - uav_writeresponserequest = av_writeresponserequest; - av_writeresponsevalid = uav_writeresponsevalid; - end else begin - uav_writeresponserequest = '0; - av_writeresponsevalid = '0; - end - end - - //address + burstcount assignment - - reg [UAV_ADDRESS_W - 1 : 0] address_register; - reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; - - always @* begin - uav_address=uav_address_pre; - uav_burstcount=uav_burstcount_pre; - - if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin - uav_address=address_register; - uav_burstcount=burstcount_register; - end - end - - reg first_burst_stalled; - reg burst_stalled; - - - wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; - wire [UAV_ADDRESS_W-1:0] combi_addr_reg; - generate - if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin - if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; - end - else begin - assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; - end - end - else begin - assign combi_burst_addr_reg = - uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - assign combi_addr_reg = - address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; - end - endgenerate - - always@(posedge clk, posedge reset) begin - - if(reset) begin - address_register <= '0; - burstcount_register <= '0; - first_burst_stalled <= 1'b0; - burst_stalled <= 1'b0; - end - else begin - address_register <= address_register; - burstcount_register <= burstcount_register; - - if(internal_beginbursttransfer||first_burst_stalled) begin - - if(av_waitrequest) begin - first_burst_stalled <= 1'b1; - address_register <= uav_address_pre; - burstcount_register <= uav_burstcount_pre; - end else begin - first_burst_stalled <= 1'b0; - address_register <= combi_burst_addr_reg; - burstcount_register <= uav_burstcount_pre - symbols_per_word; - end - end - - else if(internal_begintransfer || burst_stalled) begin - if(~av_waitrequest) begin - burst_stalled <= 1'b0; - address_register <= combi_addr_reg; - burstcount_register <= burstcount_register - symbols_per_word; - end else - burst_stalled<=1'b1; - end - end - - end - - //Address - always @* begin - uav_address_pre = '0; - - if(AV_ADDRESS_SYMBOLS) - uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; - else begin - uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; - end - end - - //Burstcount - always@* begin - uav_burstcount_pre = symbols_per_word; // default to a single transfer - - if(USE_BURSTCOUNT) begin - uav_burstcount_pre = '0; - - if(AV_BURSTCOUNT_SYMBOLS) - uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; - else begin - uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; - end - - end - - end - - - //waitrequest translation - - always@(posedge clk, posedge reset) begin - if(reset) - read_accepted <= 1'b0; - else begin - read_accepted <= read_accepted; - - if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives - read_accepted <= 1'b0; - - if(read_accepted == 0) - read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; - end - - end - - reg write_accepted = 0; - generate if (AV_REGISTERINCOMINGSIGNALS) begin - always@(posedge clk, posedge reset) begin - if(reset) - write_accepted <= 1'b0; - else begin - write_accepted <= - ~av_waitrequest ? 1'b0 : - uav_write & ~uav_waitrequest? 1'b1 : - write_accepted; - end - end - end endgenerate - - always@* begin - av_waitrequest = uav_waitrequest; - - if(USE_READDATAVALID == 0 ) begin - av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; - end - - if (AV_REGISTERINCOMINGSIGNALS) begin - av_waitrequest = - uav_read_pre ? ~uav_readdatavalid : - uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : - 1'b1; - end - - if(USE_WAITREQUEST == 0) begin - av_waitrequest = 0; - end - end - - //read/write generation - always@* begin - - uav_write = 1'b0; - uav_write_pre = 1'b0; - uav_read = 1'b0; - uav_read_pre = 1'b0; - - if(!USE_CHIPSELECT) begin - if (USE_READ) begin - uav_read_pre=av_read; - end - - if (USE_WRITE) begin - uav_write_pre=av_write; - end - end - else begin - if(!USE_WRITE && USE_READ) begin - uav_read_pre=av_read; - uav_write_pre=av_chipselect & ~av_read; - end - else if(!USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre = av_chipselect & ~av_write; - end - else if (USE_READ && USE_WRITE) begin - uav_write_pre=av_write; - uav_read_pre=av_read; - end - end - - if(USE_READDATAVALID == 0) - uav_read = uav_read_pre & ~read_accepted; - else - uav_read = uav_read_pre; - - if(AV_REGISTERINCOMINGSIGNALS == 0) - uav_write=uav_write_pre; - else - uav_write=uav_write_pre & ~write_accepted; - - - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - if(USE_BEGINTRANSFER) begin - internal_begintransfer = av_begintransfer; - end else begin - internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(internal_begintransfer == 1 && uav_waitrequest) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - wire last_burst_transfer_pre; - wire last_burst_transfer_reg; - wire last_burst_transfer; - - // compare values before the mux to shorten critical path; benchmark before changing - assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); - assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); - assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; - - always@* begin - if(USE_BEGINBURSTTRANSFER) begin - internal_beginbursttransfer = av_beginbursttransfer; - end else begin - internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; - end - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_beginbursttransfer <= 1'b0; - end - else begin - end_beginbursttransfer <= end_beginbursttransfer; - if( last_burst_transfer && internal_begintransfer || uav_read ) begin - end_beginbursttransfer <= 1'b0; - end - else if(uav_write && internal_begintransfer) begin - end_beginbursttransfer <= 1'b1; - end - end - - end - - // synthesis translate_off - - // ------------------------------------------------ - // check_1 : for waitrequest signal violation - // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls - // Exception : begintransfer / beginbursttransfer - // : previously not in any transaction (idle) - // Note : Not checking clken which is not exactly part of Avalon controls/inputs - // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE - // ------------------------------------------------ - - reg av_waitrequest_r; - reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; - reg [AV_ADDRESS_W-1:0] av_address_r; - reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; - reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; - reg [AV_DATA_W-1:0] av_writedata_r; - - always @(posedge clk or posedge reset) begin - if (reset) begin - av_waitrequest_r <= '0; - av_write_r <= '0; - av_writeresponserequest_r <= '0; - av_read_r <= '0; - av_lock_r <= '0; - av_chipselect_r <= '0; - av_debugaccess_r <= '0; - av_address_r <= '0; - av_byteenable_r <= '0; - av_burstcount_r <= '0; - av_writedata_r <= '0; - - end - else begin - av_waitrequest_r <= av_waitrequest; - av_write_r <= av_write; - av_writeresponserequest_r <= av_writeresponserequest; - av_read_r <= av_read; - av_lock_r <= av_lock; - av_chipselect_r <= av_chipselect; - av_debugaccess_r <= av_debugaccess; - av_address_r <= av_address; - av_byteenable_r <= av_byteenable; - av_burstcount_r <= av_burstcount; - av_writedata_r <= av_writedata; - - if ( av_waitrequest_r && // When waitrequest is asserted - ( (av_write != av_write_r) || // Checks that : Input controls/data does not change - (av_writeresponserequest != av_writeresponserequest_r) || - (av_read != av_read_r) || - (av_lock != av_lock_r) || - (av_debugaccess != av_debugaccess_r) || - (av_address != av_address_r) || - (av_byteenable != av_byteenable_r) || - (av_burstcount != av_burstcount_r) - ) && - (av_write_r | av_read_r) && // Check only when : previously initiated a write/read - (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) - ) - $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), - av_address_r , av_address, - av_byteenable_r , av_byteenable, - av_burstcount_r , av_burstcount, - av_writedata_r , av_writedata, - av_writeresponserequest_r, av_writeresponserequest, - av_write_r , av_write, - av_read_r , av_read, - av_lock_r , av_lock, - av_chipselect_r, av_chipselect, - av_debugaccess_r, av_debugaccess); - end - - // end check_1 - - end - - // synthesis translate_on - - - endmodule +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Translator +// +// Converts Avalon-MM Master Interfaces into +// Avalon-MM Universal Master Interfaces +// -------------------------------------- + +`timescale 1 ns / 1 ns + + + +module altera_merlin_master_translator #( + parameter + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + + //Optional Port Declarations + + USE_BURSTCOUNT = 1, + USE_BEGINBURSTTRANSFER = 0, + USE_BEGINTRANSFER = 0, + USE_CHIPSELECT = 0, + USE_READ = 1, + USE_READDATAVALID = 1, + USE_WRITE = 1, + USE_WAITREQUEST = 1, + USE_WRITERESPONSE = 0, + USE_READRESPONSE = 0, + + AV_REGISTERINCOMINGSIGNALS = 0, + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_CONSTANT_BURST_BEHAVIOR = 1, + AV_BURSTCOUNT_SYMBOLS = 0, + AV_LINEWRAPBURSTS = 0, + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_CONSTANT_BURST_BEHAVIOR = 0 + )( + //Universal Avalon Master + input wire clk, + input wire reset, + output reg uav_write, + output reg uav_read, + output reg [UAV_ADDRESS_W -1 : 0] uav_address, + output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, + output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, + output wire [AV_DATA_W -1 : 0] uav_writedata, + output wire uav_lock, + output wire uav_debugaccess, + output wire uav_clken, + + input wire [ AV_DATA_W -1 : 0] uav_readdata, + input wire uav_readdatavalid, + input wire uav_waitrequest, + input wire [1:0] uav_response, + output reg uav_writeresponserequest, + input wire uav_writeresponsevalid, + + //Avalon-MM !Master + input reg av_write, + input reg av_read, + input wire [AV_ADDRESS_W -1 : 0] av_address, + input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, + input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, + input wire [AV_DATA_W -1 : 0] av_writedata, + input wire av_begintransfer, + input wire av_beginbursttransfer, + input wire av_lock, + input wire av_chipselect, + input wire av_debugaccess, + input wire av_clken, + + output wire [AV_DATA_W -1 : 0] av_readdata, + output wire av_readdatavalid, + output reg av_waitrequest, + output reg [1:0] av_response, + input wire av_writeresponserequest, + output reg av_writeresponsevalid + + ); + + + localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); + localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); + localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; + + localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; + localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; + + + // -1 for burstcount restriction 2^(n-1) + + localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; + localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; + + localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; + localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; + + localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; + localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; + + function integer flog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + if ( i <= 0 ) flog2 = 0; + else begin + for(flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + + endfunction // flog2 + + function integer clog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2 = 0; i > 0; clog2 = clog2 + 1) + i = i >> 1; + end + + endfunction + + function integer pow2; + input [31:0] toShift; + begin + pow2=1; + pow2= pow2 << toShift; + end + endfunction // pow2 + + // ------------------------------------------------- + // Assign some constants to appropriately-sized signals to + // avoid synthesis warnings. This also helps some simulators + // with their inferred sensitivity lists. + // ------------------------------------------------- + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); + wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; + + + reg internal_beginbursttransfer; + reg internal_begintransfer; + reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; + reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; + + + + reg uav_read_pre; + reg uav_write_pre; + reg read_accepted; + + //Passthru assignmenst + + assign uav_writedata = av_writedata; + assign av_readdata = uav_readdata; + assign uav_byteenable = av_byteenable; + assign uav_lock = av_lock; + assign av_readdatavalid = uav_readdatavalid; + assign uav_debugaccess = av_debugaccess; + assign uav_clken = av_clken; + + //Response signals + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) + av_response = '0; + else + av_response = uav_response; + if (USE_WRITERESPONSE) begin + uav_writeresponserequest = av_writeresponserequest; + av_writeresponsevalid = uav_writeresponsevalid; + end else begin + uav_writeresponserequest = '0; + av_writeresponsevalid = '0; + end + end + + //address + burstcount assignment + + reg [UAV_ADDRESS_W - 1 : 0] address_register; + reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; + + always @* begin + uav_address=uav_address_pre; + uav_burstcount=uav_burstcount_pre; + + if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin + uav_address=address_register; + uav_burstcount=burstcount_register; + end + end + + reg first_burst_stalled; + reg burst_stalled; + + + wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; + wire [UAV_ADDRESS_W-1:0] combi_addr_reg; + generate + if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin + if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + end + else begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + end + end + else begin + assign combi_burst_addr_reg = + uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + assign combi_addr_reg = + address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + end + endgenerate + + always@(posedge clk, posedge reset) begin + + if(reset) begin + address_register <= '0; + burstcount_register <= '0; + first_burst_stalled <= 1'b0; + burst_stalled <= 1'b0; + end + else begin + address_register <= address_register; + burstcount_register <= burstcount_register; + + if(internal_beginbursttransfer||first_burst_stalled) begin + + if(av_waitrequest) begin + first_burst_stalled <= 1'b1; + address_register <= uav_address_pre; + burstcount_register <= uav_burstcount_pre; + end else begin + first_burst_stalled <= 1'b0; + address_register <= combi_burst_addr_reg; + burstcount_register <= uav_burstcount_pre - symbols_per_word; + end + end + + else if(internal_begintransfer || burst_stalled) begin + if(~av_waitrequest) begin + burst_stalled <= 1'b0; + address_register <= combi_addr_reg; + burstcount_register <= burstcount_register - symbols_per_word; + end else + burst_stalled<=1'b1; + end + end + + end + + //Address + always @* begin + uav_address_pre = '0; + + if(AV_ADDRESS_SYMBOLS) + uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; + else begin + uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; + end + end + + //Burstcount + always@* begin + uav_burstcount_pre = symbols_per_word; // default to a single transfer + + if(USE_BURSTCOUNT) begin + uav_burstcount_pre = '0; + + if(AV_BURSTCOUNT_SYMBOLS) + uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; + else begin + uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; + end + + end + + end + + + //waitrequest translation + + always@(posedge clk, posedge reset) begin + if(reset) + read_accepted <= 1'b0; + else begin + read_accepted <= read_accepted; + + if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives + read_accepted <= 1'b0; + + if(read_accepted == 0) + read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; + end + + end + + reg write_accepted = 0; + generate if (AV_REGISTERINCOMINGSIGNALS) begin + always@(posedge clk, posedge reset) begin + if(reset) + write_accepted <= 1'b0; + else begin + write_accepted <= + ~av_waitrequest ? 1'b0 : + uav_write & ~uav_waitrequest? 1'b1 : + write_accepted; + end + end + end endgenerate + + always@* begin + av_waitrequest = uav_waitrequest; + + if(USE_READDATAVALID == 0 ) begin + av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; + end + + if (AV_REGISTERINCOMINGSIGNALS) begin + av_waitrequest = + uav_read_pre ? ~uav_readdatavalid : + uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : + 1'b1; + end + + if(USE_WAITREQUEST == 0) begin + av_waitrequest = 0; + end + end + + //read/write generation + always@* begin + + uav_write = 1'b0; + uav_write_pre = 1'b0; + uav_read = 1'b0; + uav_read_pre = 1'b0; + + if(!USE_CHIPSELECT) begin + if (USE_READ) begin + uav_read_pre=av_read; + end + + if (USE_WRITE) begin + uav_write_pre=av_write; + end + end + else begin + if(!USE_WRITE && USE_READ) begin + uav_read_pre=av_read; + uav_write_pre=av_chipselect & ~av_read; + end + else if(!USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre = av_chipselect & ~av_write; + end + else if (USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre=av_read; + end + end + + if(USE_READDATAVALID == 0) + uav_read = uav_read_pre & ~read_accepted; + else + uav_read = uav_read_pre; + + if(AV_REGISTERINCOMINGSIGNALS == 0) + uav_write=uav_write_pre; + else + uav_write=uav_write_pre & ~write_accepted; + + + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + if(USE_BEGINTRANSFER) begin + internal_begintransfer = av_begintransfer; + end else begin + internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(internal_begintransfer == 1 && uav_waitrequest) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + wire last_burst_transfer_pre; + wire last_burst_transfer_reg; + wire last_burst_transfer; + + // compare values before the mux to shorten critical path; benchmark before changing + assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); + assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); + assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; + + always@* begin + if(USE_BEGINBURSTTRANSFER) begin + internal_beginbursttransfer = av_beginbursttransfer; + end else begin + internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_beginbursttransfer <= 1'b0; + end + else begin + end_beginbursttransfer <= end_beginbursttransfer; + if( last_burst_transfer && internal_begintransfer || uav_read ) begin + end_beginbursttransfer <= 1'b0; + end + else if(uav_write && internal_begintransfer) begin + end_beginbursttransfer <= 1'b1; + end + end + + end + + // synthesis translate_off + + // ------------------------------------------------ + // check_1 : for waitrequest signal violation + // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls + // Exception : begintransfer / beginbursttransfer + // : previously not in any transaction (idle) + // Note : Not checking clken which is not exactly part of Avalon controls/inputs + // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE + // ------------------------------------------------ + + reg av_waitrequest_r; + reg av_write_r,av_writeresponserequest_r,av_read_r,av_lock_r,av_chipselect_r,av_debugaccess_r; + reg [AV_ADDRESS_W-1:0] av_address_r; + reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; + reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; + reg [AV_DATA_W-1:0] av_writedata_r; + + always @(posedge clk or posedge reset) begin + if (reset) begin + av_waitrequest_r <= '0; + av_write_r <= '0; + av_writeresponserequest_r <= '0; + av_read_r <= '0; + av_lock_r <= '0; + av_chipselect_r <= '0; + av_debugaccess_r <= '0; + av_address_r <= '0; + av_byteenable_r <= '0; + av_burstcount_r <= '0; + av_writedata_r <= '0; + + end + else begin + av_waitrequest_r <= av_waitrequest; + av_write_r <= av_write; + av_writeresponserequest_r <= av_writeresponserequest; + av_read_r <= av_read; + av_lock_r <= av_lock; + av_chipselect_r <= av_chipselect; + av_debugaccess_r <= av_debugaccess; + av_address_r <= av_address; + av_byteenable_r <= av_byteenable; + av_burstcount_r <= av_burstcount; + av_writedata_r <= av_writedata; + + if ( av_waitrequest_r && // When waitrequest is asserted + ( (av_write != av_write_r) || // Checks that : Input controls/data does not change + (av_writeresponserequest != av_writeresponserequest_r) || + (av_read != av_read_r) || + (av_lock != av_lock_r) || + (av_debugaccess != av_debugaccess_r) || + (av_address != av_address_r) || + (av_byteenable != av_byteenable_r) || + (av_burstcount != av_burstcount_r) + ) && + (av_write_r | av_read_r) && // Check only when : previously initiated a write/read + (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) + ) + $display("%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.\nav_address %x --> %x\nav_byteenable %x --> %x\nav_burstcount %x --> %x\nav_writedata %x --> %x\nav_writeresponserequest %x --> %x\nav_write %x --> %x\nav_read %x --> %x\nav_lock %x --> %x\nav_chipselect %x --> %x\nav_debugaccess %x --> %x ", $time(), + av_address_r , av_address, + av_byteenable_r , av_byteenable, + av_burstcount_r , av_burstcount, + av_writedata_r , av_writedata, + av_writeresponserequest_r, av_writeresponserequest, + av_write_r , av_write, + av_read_r , av_read, + av_lock_r , av_lock, + av_chipselect_r, av_chipselect, + av_debugaccess_r, av_debugaccess); + end + + // end check_1 + + end + + // synthesis translate_on + + + endmodule diff --git a/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv b/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv index e7c183d..ea599eb 100644 --- a/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv +++ b/nios_system/synthesis/submodules/altera_merlin_slave_agent.sv @@ -11,578 +11,578 @@ // agreement for further details. -// (C) 2001-2011 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_agent -#( - // Packet parameters - parameter PKT_BEGIN_BURST = 81, - parameter PKT_DATA_H = 31, - parameter PKT_DATA_L = 0, - parameter PKT_SYMBOL_W = 8, - parameter PKT_BYTEEN_H = 71, - parameter PKT_BYTEEN_L = 68, - parameter PKT_ADDR_H = 63, - parameter PKT_ADDR_L = 32, - parameter PKT_TRANS_LOCK = 87, - parameter PKT_TRANS_COMPRESSED_READ = 67, - parameter PKT_TRANS_POSTED = 66, - parameter PKT_TRANS_WRITE = 65, - parameter PKT_TRANS_READ = 64, - parameter PKT_SRC_ID_H = 74, - parameter PKT_SRC_ID_L = 72, - parameter PKT_DEST_ID_H = 77, - parameter PKT_DEST_ID_L = 75, - parameter PKT_BURSTWRAP_H = 85, - parameter PKT_BURSTWRAP_L = 82, - parameter PKT_BYTE_CNT_H = 81, - parameter PKT_BYTE_CNT_L = 78, - parameter PKT_PROTECTION_H = 86, - parameter PKT_PROTECTION_L = 86, - parameter PKT_RESPONSE_STATUS_H = 89, - parameter PKT_RESPONSE_STATUS_L = 88, - parameter PKT_BURST_SIZE_H = 92, - parameter PKT_BURST_SIZE_L = 90, - parameter ST_DATA_W = 93, - parameter ST_CHANNEL_W = 32, - - // Slave parameters - parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, - parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, - parameter AVS_BURSTCOUNT_W = 4, - parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, - - // Slave agent parameters - parameter PREVENT_FIFO_OVERFLOW = 0, - parameter SUPPRESS_0_BYTEEN_CMD = 1, - parameter USE_READRESPONSE = 0, - parameter USE_WRITERESPONSE = 0, - - // Derived slave parameters - parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, - parameter BURST_SIZE_W = 3, - - // Derived FIFO width - parameter FIFO_DATA_W = ST_DATA_W + 1 -) -( - - input clk, - input reset, - - // Universal-Avalon anti-slave - output [ADDR_W-1:0] m0_address, - output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, - output [AVS_BE_W-1:0] m0_byteenable, - output m0_read, - input [AVS_DATA_W-1:0] m0_readdata, - input m0_waitrequest, - output m0_write, - output [AVS_DATA_W-1:0] m0_writedata, - input m0_readdatavalid, - output m0_debugaccess, - output m0_lock, - input [1:0] m0_response, - output m0_writeresponserequest, - input m0_writeresponsevalid, - - // Avalon-ST FIFO interfaces. - // Note: there's no need to include the "data" field here, at least for - // reads, since readdata is filled in from slave info. To keep life - // simple, have a data field, but fill it with 0s. - // Av-st response fifo source interface - output reg [FIFO_DATA_W-1:0] rf_source_data, - output rf_source_valid, - output rf_source_startofpacket, - output rf_source_endofpacket, - input rf_source_ready, - - // Av-st response fifo sink interface - input [FIFO_DATA_W-1:0] rf_sink_data, - input rf_sink_valid, - input rf_sink_startofpacket, - input rf_sink_endofpacket, - output rf_sink_ready, - - // Av-st readdata fifo src interface, data and response - // extra 2 bits for storing RESPONSE STATUS - output [AVS_DATA_W+1:0] rdata_fifo_src_data, - output rdata_fifo_src_valid, - input rdata_fifo_src_ready, - - // Av-st readdata fifo sink interface - input [AVS_DATA_W+1:0] rdata_fifo_sink_data, - input rdata_fifo_sink_valid, - output rdata_fifo_sink_ready, - - // Av-st sink command packet interface - output cp_ready, - input cp_valid, - input [ST_DATA_W-1:0] cp_data, - input [ST_CHANNEL_W-1:0] cp_channel, - input cp_startofpacket, - input cp_endofpacket, - - // Av-st source response packet interface - input rp_ready, - output reg rp_valid, - output reg [ST_DATA_W-1:0] rp_data, - output rp_startofpacket, - output rp_endofpacket -); - - // -------------------------------------------------- - // Ceil(log2()) function log2ceil of 4 = 2 - // -------------------------------------------------- - function integer log2ceil; - input reg[63:0] val; - reg [63:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - - // ------------------------------------------------ - // Local Parameters - // ------------------------------------------------ - localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; - localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; - localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; - localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; - localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; - localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; - localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; - localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); - - // ------------------------------------------------ - // Signals - // ------------------------------------------------ - wire [DATA_W-1:0] cmd_data; - wire [BE_W-1:0] cmd_byteen; - wire [ADDR_W-1:0] cmd_addr; - wire [MID_W-1:0] cmd_mid; - wire [SID_W-1:0] cmd_sid; - wire cmd_read; - wire cmd_write; - wire cmd_compressed; - wire cmd_posted; - wire [BYTE_CNT_W-1:0] cmd_byte_cnt; - wire [BURSTWRAP_W-1:0] cmd_burstwrap; - wire [BURSTSIZE_W-1:0] cmd_burstsize; - wire cmd_debugaccess; - - wire byteen_asserted; - wire needs_response_synthesis; - wire generate_response; - - // Assign command fields - assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; - assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; - assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; - assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; - assign cmd_posted = cp_data[PKT_TRANS_POSTED]; - assign cmd_write = cp_data[PKT_TRANS_WRITE]; - assign cmd_read = cp_data[PKT_TRANS_READ]; - assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; - assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; - assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; - - // Local "ready_for_command" signal: deasserted when the agent is unable to accept - // another command, e.g. rdv FIFO is full, (local readdata storage is full && - // ~rp_ready), ... - // Say, this could depend on the type of command, for example, even if the - // rdv FIFO is full, a write request can be accepted. For later. - wire ready_for_command; - - wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; - wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; - wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; - wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; - wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; - - // num_symbols is PKT_SYMBOLS, appropriately sized. - wire [31:0] int_num_symbols = PKT_SYMBOLS; - wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; - - generate - if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow - // --------------------------------------------------- - // Backpressure if the slave says to, or if FIFO overflow may occur. - // - // All commands are backpressured once the FIFO is full - // even if they don't need storage. This breaks a long - // combinatorial path from the master read/write through - // this logic and back to the master via the backpressure - // path. - // - // To avoid a loss of throughput the FIFO will be parameterized - // one slot deeper. The extra slot should never be used in normal - // operation, but should a slave misbehave and accept one more - // read than it should then backpressure will kick in. - // - // An example: assume a slave with MPRT = 2. It can accept a - // command sequence RRWW without backpressuring. If the FIFO is - // only 2 deep, we'd backpressure the writes leading to loss of - // throughput. If the FIFO is 3 deep, we'll only backpressure when - // RRR... which is an illegal condition anyway. - // --------------------------------------------------- - - assign ready_for_command = rf_source_ready; - assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; - - end else begin : no_prevent_fifo_overflow - - // Do not suppress the command or the slave will - // not be able to waitrequest - assign ready_for_command = 1'b1; - // Backpressure only if the slave says to. - assign cp_ready = ~m0_waitrequest | ~byteen_asserted; - - end - endgenerate - - generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd - assign byteen_asserted = |cmd_byteen; - end else begin : no_suppress_0_byteen_cmd - assign byteen_asserted = 1'b1; - end - endgenerate - - // ------------------------------------------------------------------- - // Extract avalon signals from command packet. - // ------------------------------------------------------------------- - // Mask off the lower bits of address. - // The burst adapter before this component will break narrow sized packets - // into sub-bursts of length 1. However, the packet addresses are preserved, - // which means this component may see size-aligned addresses. - // - // Masking ensures that the addresses seen by an Avalon slave are aligned to - // the full data width instead of the size. - // - // Example: - // output from burst adapter (datawidth=4, size=2 bytes): - // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 - // expected output from slave agent: - // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 - generate - if (BITS_TO_MASK > 0) begin : mask_address - - assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; - - end else begin : no_mask_address - - assign m0_address = cmd_addr; - - end - endgenerate - - assign m0_byteenable = cmd_byteen; - assign m0_writedata = cmd_data; - - // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - - // this sort of burst exists only in merlin fabric ST packets. What to do - // if we see such a burst? All beats in that burst need to be transmitted - // to the slave so we have enough space-time for byteenable expression. - // - // There can be multiple bursts in a packet, but only one beat per burst - // in cases. The exception is when we've decided not to insert a - // burst adapter for efficiency reasons, in which case this agent is also - // responsible for driving burstcount to 1 on each beat of an uncompressed - // read burst. - - assign m0_read = ready_for_command & byteen_asserted & - (local_compressed_read | local_read); - - generate - begin : m0_burstcount_zero_pad - // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount - // from a sub-range, or 0-pad, as appropriate. - if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin - wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = - {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; - assign m0_burstcount = (local_read & ~local_compressed_read) ? - {zero_pad, num_symbols} : - {zero_pad, cmd_byte_cnt}; - end - else begin : m0_burstcount_no_pad - assign m0_burstcount = (local_read & ~local_compressed_read) ? - num_symbols[AVS_BURSTCOUNT_W-1:0] : - cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; - end - end - endgenerate - - assign m0_write = ready_for_command & local_write & byteen_asserted; - assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); - assign m0_debugaccess = cmd_debugaccess; - // For now, to support write response - assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; - //assign m0_writeresponserequest = '0; - - // ------------------------------------------------------------------- - // Indirection layer for response packet values. Some may always wire - // directly from the slave translator; others will no doubt emerge from - // various FIFOs. - // What to put in resp_data when a write occured? Answer: it does not - // matter, because only response status is needed for non-posted writes, - // and the packet already has a field for that. - - // tgngo:Use the rdata_fifo to store write response as well - // So that we wont lost response if master can back-pressured - // as well as it needs for write response merging - assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; - //assign rdata_fifo_src_valid = m0_readdatavalid; - assign rdata_fifo_src_data = {m0_response,m0_readdata}; - - // ------------------------------------------------------------------ - // Generate a token when read commands are suppressed. The token - // is stored in the response FIFO, and will be used to synthesize - // a read response. The same token is used for non-posted write - // response synthesis. - // - // Note: this token is not generated for suppressed uncompressed read cycles; - // the burst uncompression logic at the read side of the response FIFO - // generates the correct number of responses. - // ------------------------------------------------------------------ - // When the slave can return the response, let it does its works. Dont generate sysnthesis response - assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); - - // Avalon-ST interfaces to external response fifo: - // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write - // To support response from slave, we need to store each sub-burst of write command into fifo. - // Each sub-burst will return a response and these two command and response are popped out together - // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write - // the slave agent will send out the final merged response - - wire internal_cp_endofburst; - wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning - wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; - assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; - assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); - wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; - wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; - - assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) - & ready_for_command & cp_ready; - assign rf_source_startofpacket = cp_startofpacket; - assign rf_source_endofpacket = cp_endofpacket; - always @* begin - // default: assign every command packet field to the response FIFO... - rf_source_data = {1'b0, cp_data}; - - // ... and override select fields as needed. - rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; - rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; - rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; - rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; - //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; - rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; - rf_source_data[PKT_TRANS_POSTED] = cmd_posted; - rf_source_data[PKT_TRANS_WRITE] = cmd_write; - rf_source_data[PKT_TRANS_READ] = cmd_read; - rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; - rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; - rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; - rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; - rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; - rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; - rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; - end - - wire uncompressor_source_valid; - wire [BURSTSIZE_W-1:0] uncompressor_burstsize; - - //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) - // at this time, the final response merged will send out, and rp_valid is only asserted - // for one response for whole burst - generate - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; - always @* begin - if (rf_sink_data[PKT_TRANS_WRITE] == 1) - rp_valid = rdata_fifo_sink_valid & last_write_response; - else - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end else begin - always @* begin - rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; - end - end - endgenerate - // ------------------------------------------------------------------ - // Response merging - // ------------------------------------------------------------------ - wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; - reg [1:0] response_merged; - generate - begin: response_merging - if (USE_READRESPONSE & USE_WRITERESPONSE) begin - reg first_write_response; - reg reset_merged_output; - reg [1:0] previous_response_in; - reg [1:0] previous_response; - - always_ff @(posedge clk, posedge reset) begin - if (reset) begin - first_write_response <= 1'b1; - end - else begin // Merging work for write response, for read: previous_response_in = current_response - if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin - first_write_response <= 1'b0; - if (rf_sink_endofpacket) - first_write_response <= 1'b1; - end - end - end - - always_comb begin - reset_merged_output = first_write_response && rdata_fifo_sink_valid; - previous_response_in = reset_merged_output ? current_response : previous_response; - response_merged = current_response >= previous_response ? current_response: previous_response_in; - end - - always_ff @(posedge clk or posedge reset) begin - if (reset) begin - previous_response <= 2'b00; - end - else begin - if (rf_sink_valid & rdata_fifo_sink_valid) begin - previous_response <= response_merged; - end - end - end - end else begin - always @* begin - response_merged = current_response; - end - end - end - endgenerate - - assign generate_response = rf_sink_data[FIFO_DATA_W-1]; - - wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; - wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; - wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; - wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; - // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo - wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; - - wire [BYTE_CNT_W-1:0] burst_byte_cnt; - wire [BURSTWRAP_W-1:0] rp_burstwrap; - wire [ADDR_W-1:0] rp_address; - wire rp_is_compressed; - - // ------------------------------------------------------------------ - // Backpressure the readdata fifo if we're supposed to synthesize a response. - // This may be a read response (for suppressed reads) or a write response - // (for non-posted writes). - // ------------------------------------------------------------------ - assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); - - always @* begin - // By default, return all fields... - rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; - - // ... and override specific fields. - rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; - // Assignments directly from the response fifo. - rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; - rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; - rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; - rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; - rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; - - // Burst uncompressor assignments - rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; - rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; - rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; - rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; - rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; - - // avalon slaves always respond with "okay" -> not true for now - //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; - rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; - rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; - end - - // ------------------------------------------------------------------ - // Note: the burst uncompressor may be asked to generate responses for - // write packets; these are treated the same as single-cycle uncompressed - // reads. - // ------------------------------------------------------------------ - altera_merlin_burst_uncompressor #( - .ADDR_W (ADDR_W), - .BURSTWRAP_W (BURSTWRAP_W), - .BYTE_CNT_W (BYTE_CNT_W), - .PKT_SYMBOLS (PKT_SYMBOLS) - ) uncompressor - ( - .clk (clk), - .reset (reset), - .sink_startofpacket (rf_sink_startofpacket_wire), - .sink_endofpacket (rf_sink_endofpacket), - .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), - .sink_ready (rf_sink_ready), - .sink_addr (rf_sink_addr), - .sink_burstwrap (rf_sink_burstwrap), - .sink_byte_cnt (rf_sink_byte_cnt), - .sink_is_compressed (rf_sink_compressed), - .sink_burstsize (rf_sink_burstsize), - - .source_startofpacket (rp_startofpacket), - .source_endofpacket (rp_endofpacket), - .source_valid (uncompressor_source_valid), - .source_ready (rp_ready), - .source_addr (rp_address), - .source_burstwrap (rp_burstwrap), - .source_byte_cnt (burst_byte_cnt), - .source_is_compressed (rp_is_compressed), - .source_burstsize (uncompressor_burstsize) - ); - -//-------------------------------------- -// Assertion: In case slave support response. Yhe slave needs return response in order -// Ex: non-posted write followed by a read: write response must complete before read data -//-------------------------------------- -// synthesis translate_off -ERROR_write_response_and_read_response_cannot_happen_same_time: - assert property ( @(posedge clk) - disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) - ); - -// synthesis translate_on -endmodule - +// (C) 2001-2011 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_agent +#( + // Packet parameters + parameter PKT_BEGIN_BURST = 81, + parameter PKT_DATA_H = 31, + parameter PKT_DATA_L = 0, + parameter PKT_SYMBOL_W = 8, + parameter PKT_BYTEEN_H = 71, + parameter PKT_BYTEEN_L = 68, + parameter PKT_ADDR_H = 63, + parameter PKT_ADDR_L = 32, + parameter PKT_TRANS_LOCK = 87, + parameter PKT_TRANS_COMPRESSED_READ = 67, + parameter PKT_TRANS_POSTED = 66, + parameter PKT_TRANS_WRITE = 65, + parameter PKT_TRANS_READ = 64, + parameter PKT_SRC_ID_H = 74, + parameter PKT_SRC_ID_L = 72, + parameter PKT_DEST_ID_H = 77, + parameter PKT_DEST_ID_L = 75, + parameter PKT_BURSTWRAP_H = 85, + parameter PKT_BURSTWRAP_L = 82, + parameter PKT_BYTE_CNT_H = 81, + parameter PKT_BYTE_CNT_L = 78, + parameter PKT_PROTECTION_H = 86, + parameter PKT_PROTECTION_L = 86, + parameter PKT_RESPONSE_STATUS_H = 89, + parameter PKT_RESPONSE_STATUS_L = 88, + parameter PKT_BURST_SIZE_H = 92, + parameter PKT_BURST_SIZE_L = 90, + parameter ST_DATA_W = 93, + parameter ST_CHANNEL_W = 32, + + // Slave parameters + parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + parameter AVS_BURSTCOUNT_W = 4, + parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, + + // Slave agent parameters + parameter PREVENT_FIFO_OVERFLOW = 0, + parameter SUPPRESS_0_BYTEEN_CMD = 1, + parameter USE_READRESPONSE = 0, + parameter USE_WRITERESPONSE = 0, + + // Derived slave parameters + parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + parameter BURST_SIZE_W = 3, + + // Derived FIFO width + parameter FIFO_DATA_W = ST_DATA_W + 1 +) +( + + input clk, + input reset, + + // Universal-Avalon anti-slave + output [ADDR_W-1:0] m0_address, + output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, + output [AVS_BE_W-1:0] m0_byteenable, + output m0_read, + input [AVS_DATA_W-1:0] m0_readdata, + input m0_waitrequest, + output m0_write, + output [AVS_DATA_W-1:0] m0_writedata, + input m0_readdatavalid, + output m0_debugaccess, + output m0_lock, + input [1:0] m0_response, + output m0_writeresponserequest, + input m0_writeresponsevalid, + + // Avalon-ST FIFO interfaces. + // Note: there's no need to include the "data" field here, at least for + // reads, since readdata is filled in from slave info. To keep life + // simple, have a data field, but fill it with 0s. + // Av-st response fifo source interface + output reg [FIFO_DATA_W-1:0] rf_source_data, + output rf_source_valid, + output rf_source_startofpacket, + output rf_source_endofpacket, + input rf_source_ready, + + // Av-st response fifo sink interface + input [FIFO_DATA_W-1:0] rf_sink_data, + input rf_sink_valid, + input rf_sink_startofpacket, + input rf_sink_endofpacket, + output rf_sink_ready, + + // Av-st readdata fifo src interface, data and response + // extra 2 bits for storing RESPONSE STATUS + output [AVS_DATA_W+1:0] rdata_fifo_src_data, + output rdata_fifo_src_valid, + input rdata_fifo_src_ready, + + // Av-st readdata fifo sink interface + input [AVS_DATA_W+1:0] rdata_fifo_sink_data, + input rdata_fifo_sink_valid, + output rdata_fifo_sink_ready, + + // Av-st sink command packet interface + output cp_ready, + input cp_valid, + input [ST_DATA_W-1:0] cp_data, + input [ST_CHANNEL_W-1:0] cp_channel, + input cp_startofpacket, + input cp_endofpacket, + + // Av-st source response packet interface + input rp_ready, + output reg rp_valid, + output reg [ST_DATA_W-1:0] rp_data, + output rp_startofpacket, + output rp_endofpacket +); + + // -------------------------------------------------- + // Ceil(log2()) function log2ceil of 4 = 2 + // -------------------------------------------------- + function integer log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + // ------------------------------------------------ + // Local Parameters + // ------------------------------------------------ + localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; + localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; + localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; + localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; + localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); + + // ------------------------------------------------ + // Signals + // ------------------------------------------------ + wire [DATA_W-1:0] cmd_data; + wire [BE_W-1:0] cmd_byteen; + wire [ADDR_W-1:0] cmd_addr; + wire [MID_W-1:0] cmd_mid; + wire [SID_W-1:0] cmd_sid; + wire cmd_read; + wire cmd_write; + wire cmd_compressed; + wire cmd_posted; + wire [BYTE_CNT_W-1:0] cmd_byte_cnt; + wire [BURSTWRAP_W-1:0] cmd_burstwrap; + wire [BURSTSIZE_W-1:0] cmd_burstsize; + wire cmd_debugaccess; + + wire byteen_asserted; + wire needs_response_synthesis; + wire generate_response; + + // Assign command fields + assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; + assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; + assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; + assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; + assign cmd_posted = cp_data[PKT_TRANS_POSTED]; + assign cmd_write = cp_data[PKT_TRANS_WRITE]; + assign cmd_read = cp_data[PKT_TRANS_READ]; + assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; + assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; + + // Local "ready_for_command" signal: deasserted when the agent is unable to accept + // another command, e.g. rdv FIFO is full, (local readdata storage is full && + // ~rp_ready), ... + // Say, this could depend on the type of command, for example, even if the + // rdv FIFO is full, a write request can be accepted. For later. + wire ready_for_command; + + wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; + wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; + wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; + wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; + wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + generate + if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow + // --------------------------------------------------- + // Backpressure if the slave says to, or if FIFO overflow may occur. + // + // All commands are backpressured once the FIFO is full + // even if they don't need storage. This breaks a long + // combinatorial path from the master read/write through + // this logic and back to the master via the backpressure + // path. + // + // To avoid a loss of throughput the FIFO will be parameterized + // one slot deeper. The extra slot should never be used in normal + // operation, but should a slave misbehave and accept one more + // read than it should then backpressure will kick in. + // + // An example: assume a slave with MPRT = 2. It can accept a + // command sequence RRWW without backpressuring. If the FIFO is + // only 2 deep, we'd backpressure the writes leading to loss of + // throughput. If the FIFO is 3 deep, we'll only backpressure when + // RRR... which is an illegal condition anyway. + // --------------------------------------------------- + + assign ready_for_command = rf_source_ready; + assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; + + end else begin : no_prevent_fifo_overflow + + // Do not suppress the command or the slave will + // not be able to waitrequest + assign ready_for_command = 1'b1; + // Backpressure only if the slave says to. + assign cp_ready = ~m0_waitrequest | ~byteen_asserted; + + end + endgenerate + + generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd + assign byteen_asserted = |cmd_byteen; + end else begin : no_suppress_0_byteen_cmd + assign byteen_asserted = 1'b1; + end + endgenerate + + // ------------------------------------------------------------------- + // Extract avalon signals from command packet. + // ------------------------------------------------------------------- + // Mask off the lower bits of address. + // The burst adapter before this component will break narrow sized packets + // into sub-bursts of length 1. However, the packet addresses are preserved, + // which means this component may see size-aligned addresses. + // + // Masking ensures that the addresses seen by an Avalon slave are aligned to + // the full data width instead of the size. + // + // Example: + // output from burst adapter (datawidth=4, size=2 bytes): + // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 + // expected output from slave agent: + // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 + generate + if (BITS_TO_MASK > 0) begin : mask_address + + assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; + + end else begin : no_mask_address + + assign m0_address = cmd_addr; + + end + endgenerate + + assign m0_byteenable = cmd_byteen; + assign m0_writedata = cmd_data; + + // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - + // this sort of burst exists only in merlin fabric ST packets. What to do + // if we see such a burst? All beats in that burst need to be transmitted + // to the slave so we have enough space-time for byteenable expression. + // + // There can be multiple bursts in a packet, but only one beat per burst + // in cases. The exception is when we've decided not to insert a + // burst adapter for efficiency reasons, in which case this agent is also + // responsible for driving burstcount to 1 on each beat of an uncompressed + // read burst. + + assign m0_read = ready_for_command & byteen_asserted & + (local_compressed_read | local_read); + + generate + begin : m0_burstcount_zero_pad + // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount + // from a sub-range, or 0-pad, as appropriate. + if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin + wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = + {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; + assign m0_burstcount = (local_read & ~local_compressed_read) ? + {zero_pad, num_symbols} : + {zero_pad, cmd_byte_cnt}; + end + else begin : m0_burstcount_no_pad + assign m0_burstcount = (local_read & ~local_compressed_read) ? + num_symbols[AVS_BURSTCOUNT_W-1:0] : + cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; + end + end + endgenerate + + assign m0_write = ready_for_command & local_write & byteen_asserted; + assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); + assign m0_debugaccess = cmd_debugaccess; + // For now, to support write response + assign m0_writeresponserequest = ready_for_command & local_write & byteen_asserted & !cmd_posted; + //assign m0_writeresponserequest = '0; + + // ------------------------------------------------------------------- + // Indirection layer for response packet values. Some may always wire + // directly from the slave translator; others will no doubt emerge from + // various FIFOs. + // What to put in resp_data when a write occured? Answer: it does not + // matter, because only response status is needed for non-posted writes, + // and the packet already has a field for that. + + // tgngo:Use the rdata_fifo to store write response as well + // So that we wont lost response if master can back-pressured + // as well as it needs for write response merging + assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid; + //assign rdata_fifo_src_valid = m0_readdatavalid; + assign rdata_fifo_src_data = {m0_response,m0_readdata}; + + // ------------------------------------------------------------------ + // Generate a token when read commands are suppressed. The token + // is stored in the response FIFO, and will be used to synthesize + // a read response. The same token is used for non-posted write + // response synthesis. + // + // Note: this token is not generated for suppressed uncompressed read cycles; + // the burst uncompression logic at the read side of the response FIFO + // generates the correct number of responses. + // ------------------------------------------------------------------ + // When the slave can return the response, let it does its works. Dont generate sysnthesis response + assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | (nonposted_write_endofpacket && !USE_WRITERESPONSE); + + // Avalon-ST interfaces to external response fifo: + // tgngo:Currently, with "generate response synthesis", only one write command is allowed to write in at eop of non-posted write + // To support response from slave, we need to store each sub-burst of write command into fifo. + // Each sub-burst will return a response and these two command and response are popped out together + // Resposne merging will happen and at end_of_packet of the command - the last sub-burst write + // the slave agent will send out the final merged response + + wire internal_cp_endofburst; + wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning + wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount; + assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0]; + assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount); + wire local_nonposted_write = ~cp_data[PKT_TRANS_POSTED] & local_write; + wire nonposted_end_of_subburst = local_nonposted_write & internal_cp_endofburst; + + assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && nonposted_end_of_subburst)) + & ready_for_command & cp_ready; + assign rf_source_startofpacket = cp_startofpacket; + assign rf_source_endofpacket = cp_endofpacket; + always @* begin + // default: assign every command packet field to the response FIFO... + rf_source_data = {1'b0, cp_data}; + + // ... and override select fields as needed. + rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; + rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; + rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; + rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; + //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; + rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; + rf_source_data[PKT_TRANS_POSTED] = cmd_posted; + rf_source_data[PKT_TRANS_WRITE] = cmd_write; + rf_source_data[PKT_TRANS_READ] = cmd_read; + rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; + rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; + rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; + rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; + rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; + rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; + rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; + end + + wire uncompressor_source_valid; + wire [BURSTSIZE_W-1:0] uncompressor_burstsize; + + //assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + // tgngo: last_write_response indicates the last response of the burst (incase need sub-burst) + // at this time, the final response merged will send out, and rp_valid is only asserted + // for one response for whole burst + generate + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + wire last_write_response = rf_sink_data[PKT_TRANS_WRITE] & !rf_sink_data[PKT_TRANS_POSTED] & rf_sink_endofpacket; + always @* begin + if (rf_sink_data[PKT_TRANS_WRITE] == 1) + rp_valid = rdata_fifo_sink_valid & last_write_response; + else + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end else begin + always @* begin + rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + end + end + endgenerate + // ------------------------------------------------------------------ + // Response merging + // ------------------------------------------------------------------ + wire [1:0] current_response = rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W]; + reg [1:0] response_merged; + generate + begin: response_merging + if (USE_READRESPONSE & USE_WRITERESPONSE) begin + reg first_write_response; + reg reset_merged_output; + reg [1:0] previous_response_in; + reg [1:0] previous_response; + + always_ff @(posedge clk, posedge reset) begin + if (reset) begin + first_write_response <= 1'b1; + end + else begin // Merging work for write response, for read: previous_response_in = current_response + if (rf_sink_valid & rdata_fifo_sink_valid & rf_sink_data[PKT_TRANS_WRITE]) begin + first_write_response <= 1'b0; + if (rf_sink_endofpacket) + first_write_response <= 1'b1; + end + end + end + + always_comb begin + reset_merged_output = first_write_response && rdata_fifo_sink_valid; + previous_response_in = reset_merged_output ? current_response : previous_response; + response_merged = current_response >= previous_response ? current_response: previous_response_in; + end + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + previous_response <= 2'b00; + end + else begin + if (rf_sink_valid & rdata_fifo_sink_valid) begin + previous_response <= response_merged; + end + end + end + end else begin + always @* begin + response_merged = current_response; + end + end + end + endgenerate + + assign generate_response = rf_sink_data[FIFO_DATA_W-1]; + + wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; + // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo + wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; + + wire [BYTE_CNT_W-1:0] burst_byte_cnt; + wire [BURSTWRAP_W-1:0] rp_burstwrap; + wire [ADDR_W-1:0] rp_address; + wire rp_is_compressed; + + // ------------------------------------------------------------------ + // Backpressure the readdata fifo if we're supposed to synthesize a response. + // This may be a read response (for suppressed reads) or a write response + // (for non-posted writes). + // ------------------------------------------------------------------ + assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); + + always @* begin + // By default, return all fields... + rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; + + // ... and override specific fields. + rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data[AVS_DATA_W-1:0]; + // Assignments directly from the response fifo. + rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; + rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; + rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; + rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; + + // Burst uncompressor assignments + rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; + rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; + rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; + rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; + + // avalon slaves always respond with "okay" -> not true for now + //rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; + rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = response_merged; + rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; + end + + // ------------------------------------------------------------------ + // Note: the burst uncompressor may be asked to generate responses for + // write packets; these are treated the same as single-cycle uncompressed + // reads. + // ------------------------------------------------------------------ + altera_merlin_burst_uncompressor #( + .ADDR_W (ADDR_W), + .BURSTWRAP_W (BURSTWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (PKT_SYMBOLS) + ) uncompressor + ( + .clk (clk), + .reset (reset), + .sink_startofpacket (rf_sink_startofpacket_wire), + .sink_endofpacket (rf_sink_endofpacket), + .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), + .sink_ready (rf_sink_ready), + .sink_addr (rf_sink_addr), + .sink_burstwrap (rf_sink_burstwrap), + .sink_byte_cnt (rf_sink_byte_cnt), + .sink_is_compressed (rf_sink_compressed), + .sink_burstsize (rf_sink_burstsize), + + .source_startofpacket (rp_startofpacket), + .source_endofpacket (rp_endofpacket), + .source_valid (uncompressor_source_valid), + .source_ready (rp_ready), + .source_addr (rp_address), + .source_burstwrap (rp_burstwrap), + .source_byte_cnt (burst_byte_cnt), + .source_is_compressed (rp_is_compressed), + .source_burstsize (uncompressor_burstsize) + ); + +//-------------------------------------- +// Assertion: In case slave support response. Yhe slave needs return response in order +// Ex: non-posted write followed by a read: write response must complete before read data +//-------------------------------------- +// synthesis translate_off +ERROR_write_response_and_read_response_cannot_happen_same_time: + assert property ( @(posedge clk) + disable iff (reset) !(m0_writeresponsevalid && m0_readdatavalid) + ); + +// synthesis translate_on +endmodule + diff --git a/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv b/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv index d5bd6e9..bcb2311 100644 --- a/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv +++ b/nios_system/synthesis/submodules/altera_merlin_slave_translator.sv @@ -11,523 +11,523 @@ // agreement for further details. - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Slave Translator -// -// Translates Universal Avalon MM Slave -// to any Avalon MM Slave -// ------------------------------------- -// -//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one -//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero -//The key feature here is that no same cycle turnaround data is processed through the fabric. - -//import avalon_utilities_pkg::*; - -`timescale 1 ns / 1 ns - -module altera_merlin_slave_translator - #( - parameter - //Widths - AV_ADDRESS_W = 32, - AV_DATA_W = 32, - AV_BURSTCOUNT_W = 4, - AV_BYTEENABLE_W = 4, - UAV_BYTEENABLE_W = 4, - - //Read Latency - AV_READLATENCY = 1, - - //Timing - AV_READ_WAIT_CYCLES = 0, - AV_WRITE_WAIT_CYCLES = 0, - AV_SETUP_WAIT_CYCLES = 0, - AV_DATA_HOLD_CYCLES = 0, - - //Optional Port Declarations - USE_READDATAVALID = 1, - USE_WAITREQUEST = 1, - USE_READRESPONSE = 0, - USE_WRITERESPONSE = 0, - - //Variable Addressing - AV_SYMBOLS_PER_WORD = 4, - AV_ADDRESS_SYMBOLS = 0, - AV_BURSTCOUNT_SYMBOLS = 0, - BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), - UAV_ADDRESS_W = 38, - UAV_BURSTCOUNT_W = 10, - UAV_DATA_W = 32, - - AV_CONSTANT_BURST_BEHAVIOR = 0, - UAV_CONSTANT_BURST_BEHAVIOR = 0, - CHIPSELECT_THROUGH_READLATENCY = 0, - - // Tightly-Coupled Options - USE_UAV_CLKEN = 0, - AV_REQUIRE_UNALIGNED_ADDRESSES = 0 - ) - ( - - // ------------------- - // Clock & Reset - // ------------------- - input wire clk, - input wire reset, - - // ------------------- - // Universal Avalon Slave - // ------------------- - - input wire [UAV_ADDRESS_W - 1 : 0] uav_address, - input wire [UAV_DATA_W - 1 : 0] uav_writedata, - input wire uav_write, - input wire uav_read, - input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, - input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, - input wire uav_lock, - input wire uav_debugaccess, - input wire uav_clken, - - output logic uav_readdatavalid, - output logic uav_waitrequest, - output logic [UAV_DATA_W - 1 : 0] uav_readdata, - output logic [1:0] uav_response, - input wire uav_writeresponserequest, - output logic uav_writeresponsevalid, - - // ------------------- - // Customizable Avalon Master - // ------------------- - output logic [AV_ADDRESS_W - 1 : 0] av_address, - output logic [AV_DATA_W - 1 : 0] av_writedata, - output logic av_write, - output logic av_read, - output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, - output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, - output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, - output logic av_begintransfer, - output wire av_chipselect, - output logic av_beginbursttransfer, - output logic av_lock, - output wire av_clken, - output wire av_debugaccess, - output wire av_outputenable, - - input logic [AV_DATA_W - 1 : 0] av_readdata, - input logic av_readdatavalid, - input logic av_waitrequest, - - input logic [1:0] av_response, - output logic av_writeresponserequest, - input wire av_writeresponsevalid - - ); - - function integer clog2_plusone; - input [31:0] Depth; - integer i; - begin - i = Depth; - for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) - i = i >> 1; - end - - endfunction - - function integer max; - //returns the larger of two passed arguments - input [31:0] one; - input [31:0] two; - - if(one > two) - max=one; - else - max=two; - endfunction // int - - localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); - localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); - localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); - localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); - localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; - localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; - - localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? - AV_ADDRESS_W : - UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; - - localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? - AV_BURSTCOUNT_W : - UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; - localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; - - - // Calculate the symbols per word as the power of 2 extended symbols per word - wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); - wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; - - // +-------------------------------- - // |Backwards Compatibility Signals - // +-------------------------------- - assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; - assign av_debugaccess = uav_debugaccess; - - // +------------------- - // |Passthru Signals - // +------------------- - always_comb - begin - if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin - uav_response = '0; - end else begin - uav_response = av_response; - end - end - assign av_writeresponserequest = uav_writeresponserequest; - assign uav_writeresponsevalid = av_writeresponsevalid; - - //------------------------- - //Writedata and Byteenable - //------------------------- - - always@* begin - av_byteenable = '0; - av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; - end - - always@* begin - av_writedata = '0; - av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; - end - - // +------------------- - // |Calculated Signals - // +------------------- - - logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; - - function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; - input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; - - for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin - if(byteenable[i] == 1) begin - return i; - end - end - - return '0; - - endfunction - - reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; - reg [AV_ADDRESS_W - 1 : 0] address_reg; - - - always@(posedge clk, posedge reset) begin - if(reset) begin - burstcount_reg <= '0; - address_reg <= '0; - end - else begin - burstcount_reg <= burstcount_reg; - address_reg <= address_reg; - - if(av_beginbursttransfer) begin - burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - end - end - end - - - logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; - - always@* begin - if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin - temp_wire = decode_byteenable(uav_byteenable); - - real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; - end - else begin - real_uav_address = uav_address; - end - - av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_address = address_reg; - end - - always@* begin - av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; - - if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) - av_burstcount = burstcount_reg; - end - - always@* begin - av_lock = uav_lock; - end - - // ------------------- - // Writebyteenable Assignment - // ------------------- - -always@* begin - av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; -end - - // ------------------- - // Waitrequest Assignment - // ------------------- - - reg av_waitrequest_generated; - reg av_waitrequest_generated_read; - reg av_waitrequest_generated_write; - reg waitrequest_reset_override; - - reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; - - always@(posedge reset, posedge clk) begin - - if(reset) begin - wait_latency_counter <= '0; - waitrequest_reset_override <= 1'h1; - end - else begin - waitrequest_reset_override <= 1'h0; - - wait_latency_counter <= '0; - - if( uav_read | uav_write ) - wait_latency_counter <= wait_latency_counter + 1'h1; - - if( ~uav_waitrequest | waitrequest_reset_override ) - wait_latency_counter <= '0; - - end - - end - - - always @* begin - - av_read = uav_read; - av_write = uav_write; - - av_waitrequest_generated = 1'h1; - av_waitrequest_generated_read = 1'h1; - av_waitrequest_generated_write = 1'h1; - - if(LOG2_OF_LATENCY_SUM == 1) - av_waitrequest_generated = 0; - - if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin - av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; - av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; - - av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; - av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; - - if(uav_write) - av_waitrequest_generated = av_waitrequest_generated_write; - else - av_waitrequest_generated = av_waitrequest_generated_read; - - end - - if(USE_WAITREQUEST) begin - uav_waitrequest = av_waitrequest; - end - else begin - uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; - end - - end - - // -------------- - // Readdata Assignment - // -------------- - - reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; - - always@(posedge clk, posedge reset) begin - if(reset) - av_readdata_pre <= 'b0; - else - av_readdata_pre <= av_readdata; - end - - always@* begin - uav_readdata = '0; - - if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin - uav_readdata = av_readdata; - end - else begin - uav_readdata = av_readdata_pre; - end - end - // ------------------- - // Readdatavalid Assigment - // ------------------- - - reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; - reg top_read_latency_shift_reg; - - - - always@* begin - - uav_readdatavalid=top_read_latency_shift_reg; - - if(USE_READDATAVALID) begin - uav_readdatavalid = av_readdatavalid; - end - - end - - always@* begin - - top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; - - if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin - top_read_latency_shift_reg=read_latency_shift_reg; - end - - if (AV_READLATENCY > 1) begin - top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; - end - - end - - always@(posedge reset, posedge clk) begin - - if (reset) begin - read_latency_shift_reg <= '0; - end - else if (av_clken) begin - - read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; - - for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin - read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; - end - - end - - end - - // ------------ - // Chipselect and OutputEnable - // ------------ - - reg av_chipselect_pre; - wire cs_extension; - reg av_outputenable_pre; - - - assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; - assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); - - assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; - - always@(posedge reset, posedge clk) begin - if(reset) - av_outputenable_pre <= 1'b0; - else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) - av_outputenable_pre <= 0; - else - av_outputenable_pre <= cs_extension | uav_read; - end - - always@(posedge reset, posedge clk) begin - if(reset) begin - av_chipselect_pre <= 1'b0; - end - else begin - av_chipselect_pre <= 1'b0; - - if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin - //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. - //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. - if(uav_read) begin - av_chipselect_pre <= 1'b1; - end - else if(cs_extension == 1) begin - av_chipselect_pre <= 1'b1; - end - - end - end - end - - // ------------------- - // Begintransfer Assigment - // ------------------- - - reg end_begintransfer; - - always@* begin - av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; - end - - always@ ( posedge clk or posedge reset ) begin - - if(reset) begin - end_begintransfer <= 1'b0; - end - else begin - - if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) - end_begintransfer <= 1'b1; - else if(uav_waitrequest) - end_begintransfer <= end_begintransfer; - else - end_begintransfer <= 1'b0; - - end - - end - - // ------------------- - // Beginbursttransfer Assigment - // ------------------- - - reg end_beginbursttransfer; - reg in_transfer; - - - - always@* begin - av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); - end - - always@ ( posedge clk or posedge reset ) begin - if(reset) begin - end_beginbursttransfer <= 1'b0; - in_transfer <= 1'b0; - end - else begin - - end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); - - if(uav_write && uav_burstcount == symbols_per_word) - in_transfer <=1'b0; - else if(uav_write) - in_transfer <=1'b1; - - end - - end - -endmodule + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Slave Translator +// +// Translates Universal Avalon MM Slave +// to any Avalon MM Slave +// ------------------------------------- +// +//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one +//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero +//The key feature here is that no same cycle turnaround data is processed through the fabric. + +//import avalon_utilities_pkg::*; + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_translator + #( + parameter + //Widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + UAV_BYTEENABLE_W = 4, + + //Read Latency + AV_READLATENCY = 1, + + //Timing + AV_READ_WAIT_CYCLES = 0, + AV_WRITE_WAIT_CYCLES = 0, + AV_SETUP_WAIT_CYCLES = 0, + AV_DATA_HOLD_CYCLES = 0, + + //Optional Port Declarations + USE_READDATAVALID = 1, + USE_WAITREQUEST = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + //Variable Addressing + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_DATA_W = 32, + + AV_CONSTANT_BURST_BEHAVIOR = 0, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + CHIPSELECT_THROUGH_READLATENCY = 0, + + // Tightly-Coupled Options + USE_UAV_CLKEN = 0, + AV_REQUIRE_UNALIGNED_ADDRESSES = 0 + ) + ( + + // ------------------- + // Clock & Reset + // ------------------- + input wire clk, + input wire reset, + + // ------------------- + // Universal Avalon Slave + // ------------------- + + input wire [UAV_ADDRESS_W - 1 : 0] uav_address, + input wire [UAV_DATA_W - 1 : 0] uav_writedata, + input wire uav_write, + input wire uav_read, + input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, + input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, + input wire uav_lock, + input wire uav_debugaccess, + input wire uav_clken, + + output logic uav_readdatavalid, + output logic uav_waitrequest, + output logic [UAV_DATA_W - 1 : 0] uav_readdata, + output logic [1:0] uav_response, + input wire uav_writeresponserequest, + output logic uav_writeresponsevalid, + + // ------------------- + // Customizable Avalon Master + // ------------------- + output logic [AV_ADDRESS_W - 1 : 0] av_address, + output logic [AV_DATA_W - 1 : 0] av_writedata, + output logic av_write, + output logic av_read, + output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, + output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, + output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, + output logic av_begintransfer, + output wire av_chipselect, + output logic av_beginbursttransfer, + output logic av_lock, + output wire av_clken, + output wire av_debugaccess, + output wire av_outputenable, + + input logic [AV_DATA_W - 1 : 0] av_readdata, + input logic av_readdatavalid, + input logic av_waitrequest, + + input logic [1:0] av_response, + output logic av_writeresponserequest, + input wire av_writeresponsevalid + + ); + + function integer clog2_plusone; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) + i = i >> 1; + end + + endfunction + + function integer max; + //returns the larger of two passed arguments + input [31:0] one; + input [31:0] two; + + if(one > two) + max=one; + else + max=two; + endfunction // int + + localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); + localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); + localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); + localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); + localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; + + localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? + AV_ADDRESS_W : + UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; + + localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? + AV_BURSTCOUNT_W : + UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; + localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; + + + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); + wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; + + // +-------------------------------- + // |Backwards Compatibility Signals + // +-------------------------------- + assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; + assign av_debugaccess = uav_debugaccess; + + // +------------------- + // |Passthru Signals + // +------------------- + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin + uav_response = '0; + end else begin + uav_response = av_response; + end + end + assign av_writeresponserequest = uav_writeresponserequest; + assign uav_writeresponsevalid = av_writeresponsevalid; + + //------------------------- + //Writedata and Byteenable + //------------------------- + + always@* begin + av_byteenable = '0; + av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + always@* begin + av_writedata = '0; + av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; + end + + // +------------------- + // |Calculated Signals + // +------------------- + + logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; + + function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; + input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; + + for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin + if(byteenable[i] == 1) begin + return i; + end + end + + return '0; + + endfunction + + reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; + reg [AV_ADDRESS_W - 1 : 0] address_reg; + + + always@(posedge clk, posedge reset) begin + if(reset) begin + burstcount_reg <= '0; + address_reg <= '0; + end + else begin + burstcount_reg <= burstcount_reg; + address_reg <= address_reg; + + if(av_beginbursttransfer) begin + burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + end + end + end + + + logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; + + always@* begin + if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin + temp_wire = decode_byteenable(uav_byteenable); + + real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; + end + else begin + real_uav_address = uav_address; + end + + av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_address = address_reg; + end + + always@* begin + av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_burstcount = burstcount_reg; + end + + always@* begin + av_lock = uav_lock; + end + + // ------------------- + // Writebyteenable Assignment + // ------------------- + +always@* begin + av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; +end + + // ------------------- + // Waitrequest Assignment + // ------------------- + + reg av_waitrequest_generated; + reg av_waitrequest_generated_read; + reg av_waitrequest_generated_write; + reg waitrequest_reset_override; + + reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; + + always@(posedge reset, posedge clk) begin + + if(reset) begin + wait_latency_counter <= '0; + waitrequest_reset_override <= 1'h1; + end + else begin + waitrequest_reset_override <= 1'h0; + + wait_latency_counter <= '0; + + if( uav_read | uav_write ) + wait_latency_counter <= wait_latency_counter + 1'h1; + + if( ~uav_waitrequest | waitrequest_reset_override ) + wait_latency_counter <= '0; + + end + + end + + + always @* begin + + av_read = uav_read; + av_write = uav_write; + + av_waitrequest_generated = 1'h1; + av_waitrequest_generated_read = 1'h1; + av_waitrequest_generated_write = 1'h1; + + if(LOG2_OF_LATENCY_SUM == 1) + av_waitrequest_generated = 0; + + if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin + av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; + av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; + + av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; + av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; + + if(uav_write) + av_waitrequest_generated = av_waitrequest_generated_write; + else + av_waitrequest_generated = av_waitrequest_generated_read; + + end + + if(USE_WAITREQUEST) begin + uav_waitrequest = av_waitrequest; + end + else begin + uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; + end + + end + + // -------------- + // Readdata Assignment + // -------------- + + reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; + + always@(posedge clk, posedge reset) begin + if(reset) + av_readdata_pre <= 'b0; + else + av_readdata_pre <= av_readdata; + end + + always@* begin + uav_readdata = '0; + + if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin + uav_readdata = av_readdata; + end + else begin + uav_readdata = av_readdata_pre; + end + end + // ------------------- + // Readdatavalid Assigment + // ------------------- + + reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; + reg top_read_latency_shift_reg; + + + + always@* begin + + uav_readdatavalid=top_read_latency_shift_reg; + + if(USE_READDATAVALID) begin + uav_readdatavalid = av_readdatavalid; + end + + end + + always@* begin + + top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; + + if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin + top_read_latency_shift_reg=read_latency_shift_reg; + end + + if (AV_READLATENCY > 1) begin + top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; + end + + end + + always@(posedge reset, posedge clk) begin + + if (reset) begin + read_latency_shift_reg <= '0; + end + else if (av_clken) begin + + read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; + + for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin + read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; + end + + end + + end + + // ------------ + // Chipselect and OutputEnable + // ------------ + + reg av_chipselect_pre; + wire cs_extension; + reg av_outputenable_pre; + + + assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; + assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); + + assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; + + always@(posedge reset, posedge clk) begin + if(reset) + av_outputenable_pre <= 1'b0; + else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) + av_outputenable_pre <= 0; + else + av_outputenable_pre <= cs_extension | uav_read; + end + + always@(posedge reset, posedge clk) begin + if(reset) begin + av_chipselect_pre <= 1'b0; + end + else begin + av_chipselect_pre <= 1'b0; + + if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin + //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. + //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. + if(uav_read) begin + av_chipselect_pre <= 1'b1; + end + else if(cs_extension == 1) begin + av_chipselect_pre <= 1'b1; + end + + end + end + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + reg in_transfer; + + + + always@* begin + av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_beginbursttransfer <= 1'b0; + in_transfer <= 1'b0; + end + else begin + + end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); + + if(uav_write && uav_burstcount == symbols_per_word) + in_transfer <=1'b0; + else if(uav_write) + in_transfer <=1'b1; + + end + + end + +endmodule diff --git a/nios_system/synthesis/submodules/altera_reset_controller.sdc b/nios_system/synthesis/submodules/altera_reset_controller.sdc index 28476af..d58dd05 100644 --- a/nios_system/synthesis/submodules/altera_reset_controller.sdc +++ b/nios_system/synthesis/submodules/altera_reset_controller.sdc @@ -11,23 +11,23 @@ # agreement for further details. -# +--------------------------------------------------- -# | Cut the async clear paths -# +--------------------------------------------------- -set aclr_counter 0 -set clrn_counter 0 -set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -foreach_in_collection aclr_pin $aclr_collection { - set aclr_counter [expr $aclr_counter + 1] -} -foreach_in_collection clrn_pin $clrn_collection { - set clrn_counter [expr $clrn_counter + 1] -} -if {$aclr_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] -} - -if {$clrn_counter > 0} { - set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] -} +# +--------------------------------------------------- +# | Cut the async clear paths +# +--------------------------------------------------- +set aclr_counter 0 +set clrn_counter 0 +set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +foreach_in_collection aclr_pin $aclr_collection { + set aclr_counter [expr $aclr_counter + 1] +} +foreach_in_collection clrn_pin $clrn_collection { + set clrn_counter [expr $clrn_counter + 1] +} +if {$aclr_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +} + +if {$clrn_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +} diff --git a/nios_system/synthesis/submodules/altera_reset_controller.v b/nios_system/synthesis/submodules/altera_reset_controller.v index 05dd901..7c250c7 100644 --- a/nios_system/synthesis/submodules/altera_reset_controller.v +++ b/nios_system/synthesis/submodules/altera_reset_controller.v @@ -11,196 +11,196 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ -// $Revision: #2 $ -// $Date: 2013/06/03 $ -// $Author: wkleong $ - -// -------------------------------------- -// Reset controller -// -// Combines all the input resets and synchronizes -// the result to the clk. -// ACDS13.1 - Added reset request as part of reset sequencing -// -------------------------------------- - -`timescale 1 ns / 1 ns - -module altera_reset_controller -#( - parameter NUM_RESET_INPUTS = 6, - parameter OUTPUT_RESET_SYNC_EDGES = "deassert", - parameter SYNC_DEPTH = 2, - parameter RESET_REQUEST_PRESENT = 0 -) -( - // -------------------------------------- - // We support up to 16 reset inputs, for now - // -------------------------------------- - input reset_in0, - input reset_in1, - input reset_in2, - input reset_in3, - input reset_in4, - input reset_in5, - input reset_in6, - input reset_in7, - input reset_in8, - input reset_in9, - input reset_in10, - input reset_in11, - input reset_in12, - input reset_in13, - input reset_in14, - input reset_in15, - - input clk, - output reg reset_out, - output reg reset_req -); - - localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); - - localparam DEPTH = 2; - localparam CLKEN_LAGS_RESET = 0; - localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; - - wire merged_reset; - wire reset_out_pre; - - // Registers and Interconnect - (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; - reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; - reg r_sync_rst_dly; - reg r_sync_rst; - reg r_early_rst; - - // -------------------------------------- - // "Or" all the input resets together - // -------------------------------------- - assign merged_reset = ( - reset_in0 | - reset_in1 | - reset_in2 | - reset_in3 | - reset_in4 | - reset_in5 | - reset_in6 | - reset_in7 | - reset_in8 | - reset_in9 | - reset_in10 | - reset_in11 | - reset_in12 | - reset_in13 | - reset_in14 | - reset_in15 - ); - - // -------------------------------------- - // And if required, synchronize it to the required clock domain, - // with the correct synchronization type - // -------------------------------------- - generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin - - assign reset_out_pre = merged_reset; - - end else begin - - altera_reset_synchronizer - #( - .DEPTH (SYNC_DEPTH), - .ASYNC_RESET(ASYNC_RESET) - ) - alt_rst_sync_uq1 - ( - .clk (clk), - .reset_in (merged_reset), - .reset_out (reset_out_pre) - ); - - end - endgenerate - - generate if (RESET_REQUEST_PRESENT == 0) begin - always @* begin - reset_out = reset_out_pre; - reset_req = 1'b0; - end - end - else begin - - // 3-FF Metastability Synchronizer - initial - begin - altera_reset_synchronizer_int_chain <= 3'b111; - end - - always @(posedge clk) - begin - altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; - end - - - // Synchronous reset pipe - initial - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - - always @(posedge clk) - begin - if (altera_reset_synchronizer_int_chain[2] == 1'b1) - begin - r_sync_rst_chain <= {DEPTH{1'b1}}; - end - else - begin - r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; - end - end - - // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition - // matches the early input. - initial - begin - r_sync_rst_dly <= 1'b1; - r_sync_rst <= 1'b1; - r_early_rst <= 1'b1; - end - - always @(posedge clk) - begin - // Delayed reset pipeline register - r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; - - case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) - 3'b000: r_sync_rst <= 1'b0; // Not reset - 3'b001: r_sync_rst <= 1'b0; - 3'b010: r_sync_rst <= 1'b0; - 3'b011: r_sync_rst <= 1'b1; - 3'b100: r_sync_rst <= 1'b1; - 3'b101: r_sync_rst <= 1'b1; - 3'b110: r_sync_rst <= 1'b1; - 3'b111: r_sync_rst <= 1'b1; // In Reset - default: r_sync_rst <= 1'b1; - endcase - - case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) - 2'b00: r_early_rst <= 1'b0; // Not reset - 2'b01: r_early_rst <= 1'b1; // Coming out of reset - 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. - 2'b11: r_early_rst <= 1'b1; // Held in reset - default: r_early_rst <= 1'b1; - endcase - end - - always @* begin - reset_out = r_sync_rst; - reset_req = r_early_rst; - end - - end - endgenerate - -endmodule +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#2 $ +// $Revision: #2 $ +// $Date: 2013/06/03 $ +// $Author: wkleong $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// ACDS13.1 - Added reset request as part of reset sequencing +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2, + parameter RESET_REQUEST_PRESENT = 0 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + + input clk, + output reg reset_out, + output reg reset_req +); + + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + localparam DEPTH = 2; + localparam CLKEN_LAGS_RESET = 0; + localparam EARLY_RST_TAP = (CLKEN_LAGS_RESET != 0) ? 0 : 1; + + wire merged_reset; + wire reset_out_pre; + + // Registers and Interconnect + (*preserve*) reg [SYNC_DEPTH: 0] altera_reset_synchronizer_int_chain; + reg [(SYNC_DEPTH-1): 0] r_sync_rst_chain; + reg r_sync_rst_dly; + reg r_sync_rst; + reg r_early_rst; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin + + assign reset_out_pre = merged_reset; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out_pre) + ); + + end + endgenerate + + generate if (RESET_REQUEST_PRESENT == 0) begin + always @* begin + reset_out = reset_out_pre; + reset_req = 1'b0; + end + end + else begin + + // 3-FF Metastability Synchronizer + initial + begin + altera_reset_synchronizer_int_chain <= 3'b111; + end + + always @(posedge clk) + begin + altera_reset_synchronizer_int_chain[2:0] <= {altera_reset_synchronizer_int_chain[1:0], reset_out_pre}; + end + + + // Synchronous reset pipe + initial + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + + always @(posedge clk) + begin + if (altera_reset_synchronizer_int_chain[2] == 1'b1) + begin + r_sync_rst_chain <= {DEPTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[DEPTH-1:1]}; + end + end + + // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition + // matches the early input. + initial + begin + r_sync_rst_dly <= 1'b1; + r_sync_rst <= 1'b1; + r_early_rst <= 1'b1; + end + + always @(posedge clk) + begin + // Delayed reset pipeline register + r_sync_rst_dly <= r_sync_rst_chain[DEPTH-1]; + + case ({r_sync_rst_dly, r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; // Not reset + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; // In Reset + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[DEPTH-1], r_sync_rst_chain[EARLY_RST_TAP]}) + 2'b00: r_early_rst <= 1'b0; // Not reset + 2'b01: r_early_rst <= 1'b1; // Coming out of reset + 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. + 2'b11: r_early_rst <= 1'b1; // Held in reset + default: r_early_rst <= 1'b1; + endcase + end + + always @* begin + reset_out = r_sync_rst; + reset_req = r_early_rst; + end + + end + endgenerate + +endmodule diff --git a/nios_system/synthesis/submodules/altera_reset_synchronizer.v b/nios_system/synthesis/submodules/altera_reset_synchronizer.v index 5e24fe7..14936c3 100644 --- a/nios_system/synthesis/submodules/altera_reset_synchronizer.v +++ b/nios_system/synthesis/submodules/altera_reset_synchronizer.v @@ -11,77 +11,77 @@ // agreement for further details. -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ----------------------------------------------- -// Reset Synchronizer -// ----------------------------------------------- -`timescale 1 ns / 1 ns - -module altera_reset_synchronizer -#( - parameter ASYNC_RESET = 1, - parameter DEPTH = 2 -) -( - input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, - - input clk, - output reset_out -); - - // ----------------------------------------------- - // Synchronizer register chain. We cannot reuse the - // standard synchronizer in this implementation - // because our timing constraints are different. - // - // Instead of cutting the timing path to the d-input - // on the first flop we need to cut the aclr input. - // - // We omit the "preserve" attribute on the final - // output register, so that the synthesis tool can - // duplicate it where needed. - // ----------------------------------------------- - (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; - reg altera_reset_synchronizer_int_chain_out; - - generate if (ASYNC_RESET) begin - - // ----------------------------------------------- - // Assert asynchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk or posedge reset_in) begin - if (reset_in) begin - altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; - altera_reset_synchronizer_int_chain_out <= 1'b1; - end - else begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end else begin - - // ----------------------------------------------- - // Assert synchronously, deassert synchronously. - // ----------------------------------------------- - always @(posedge clk) begin - altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; - altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; - altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; - end - - assign reset_out = altera_reset_synchronizer_int_chain_out; - - end - endgenerate - -endmodule - +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_LEDRs.v b/nios_system/synthesis/submodules/nios_system_LEDRs.v index 142f077..63ed909 100644 --- a/nios_system/synthesis/submodules/nios_system_LEDRs.v +++ b/nios_system/synthesis/submodules/nios_system_LEDRs.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDRs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 17: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 17: 0] data_out; - wire [ 17: 0] out_port; - wire [ 17: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[17 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDRs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 17: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 17: 0] data_out; + wire [ 17: 0] out_port; + wire [ 17: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[17 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_LEDs.v b/nios_system/synthesis/submodules/nios_system_LEDs.v index 6c38eeb..4e22fe4 100644 --- a/nios_system/synthesis/submodules/nios_system_LEDs.v +++ b/nios_system/synthesis/submodules/nios_system_LEDs.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_LEDs ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 7: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 7: 0] data_out; - wire [ 7: 0] out_port; - wire [ 7: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {8 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[7 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_LEDs ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 7: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 7: 0] data_out; + wire [ 7: 0] out_port; + wire [ 7: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {8 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[7 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_addr_router.sv b/nios_system/synthesis/submodules/nios_system_addr_router.sv index 005a859..3c8760e 100644 --- a/nios_system/synthesis/submodules/nios_system_addr_router.sv +++ b/nios_system/synthesis/submodules/nios_system_addr_router.sv @@ -1,224 +1,224 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41000; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b10; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b01; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41000; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b10; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b01; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_addr_router_001.sv b/nios_system/synthesis/submodules/nios_system_addr_router_001.sv index 73a4ee3..7b8c2d0 100644 --- a/nios_system/synthesis/submodules/nios_system_addr_router_001.sv +++ b/nios_system/synthesis/submodules/nios_system_addr_router_001.sv @@ -1,336 +1,336 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_addr_router_001_default_decode - #( - parameter DEFAULT_CHANNEL = 1, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 15 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_addr_router_001 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 0; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - localparam PAD0 = log2ceil(64'h40000 - 64'h0); - localparam PAD1 = log2ceil(64'h41000 - 64'h40800); - localparam PAD2 = log2ceil(64'h41020 - 64'h41010); - localparam PAD3 = log2ceil(64'h41030 - 64'h41020); - localparam PAD4 = log2ceil(64'h41040 - 64'h41030); - localparam PAD5 = log2ceil(64'h41050 - 64'h41040); - localparam PAD6 = log2ceil(64'h41060 - 64'h41050); - localparam PAD7 = log2ceil(64'h41070 - 64'h41060); - localparam PAD8 = log2ceil(64'h41080 - 64'h41070); - localparam PAD9 = log2ceil(64'h41090 - 64'h41080); - localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); - localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); - localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); - localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); - localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); - localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); - localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); - localparam PAD17 = log2ceil(64'h41108 - 64'h41100); - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h41108; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH-1; - - wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_addr_router_001_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; - - // -------------------------------------------------- - // Address Decoder - // Sets the channel and destination ID based on the address - // -------------------------------------------------- - - // ( 0x0 .. 0x40000 ) - if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin - src_channel = 18'b000000000000000010; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; - end - - // ( 0x40800 .. 0x41000 ) - if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin - src_channel = 18'b000000000000000001; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; - end - - // ( 0x41010 .. 0x41020 ) - if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin - src_channel = 18'b010000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; - end - - // ( 0x41020 .. 0x41030 ) - if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin - src_channel = 18'b100000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; - end - - // ( 0x41030 .. 0x41040 ) - if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin - src_channel = 18'b001000000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; - end - - // ( 0x41040 .. 0x41050 ) - if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin - src_channel = 18'b000100000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; - end - - // ( 0x41050 .. 0x41060 ) - if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin - src_channel = 18'b000010000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; - end - - // ( 0x41060 .. 0x41070 ) - if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin - src_channel = 18'b000001000000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; - end - - // ( 0x41070 .. 0x41080 ) - if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin - src_channel = 18'b000000100000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; - end - - // ( 0x41080 .. 0x41090 ) - if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin - src_channel = 18'b000000010000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; - end - - // ( 0x41090 .. 0x410a0 ) - if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin - src_channel = 18'b000000001000000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; - end - - // ( 0x410a0 .. 0x410b0 ) - if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin - src_channel = 18'b000000000100000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; - end - - // ( 0x410b0 .. 0x410c0 ) - if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin - src_channel = 18'b000000000010000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; - end - - // ( 0x410c0 .. 0x410d0 ) - if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin - src_channel = 18'b000000000001000000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; - end - - // ( 0x410d0 .. 0x410e0 ) - if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin - src_channel = 18'b000000000000100000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; - end - - // ( 0x410e0 .. 0x410f0 ) - if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin - src_channel = 18'b000000000000010000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; - end - - // ( 0x410f0 .. 0x41100 ) - if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin - src_channel = 18'b000000000000000100; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; - end - - // ( 0x41100 .. 0x41108 ) - if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin - src_channel = 18'b000000000000001000; - src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; - end - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_addr_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 15 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_addr_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h40000 - 64'h0); + localparam PAD1 = log2ceil(64'h41000 - 64'h40800); + localparam PAD2 = log2ceil(64'h41020 - 64'h41010); + localparam PAD3 = log2ceil(64'h41030 - 64'h41020); + localparam PAD4 = log2ceil(64'h41040 - 64'h41030); + localparam PAD5 = log2ceil(64'h41050 - 64'h41040); + localparam PAD6 = log2ceil(64'h41060 - 64'h41050); + localparam PAD7 = log2ceil(64'h41070 - 64'h41060); + localparam PAD8 = log2ceil(64'h41080 - 64'h41070); + localparam PAD9 = log2ceil(64'h41090 - 64'h41080); + localparam PAD10 = log2ceil(64'h410a0 - 64'h41090); + localparam PAD11 = log2ceil(64'h410b0 - 64'h410a0); + localparam PAD12 = log2ceil(64'h410c0 - 64'h410b0); + localparam PAD13 = log2ceil(64'h410d0 - 64'h410c0); + localparam PAD14 = log2ceil(64'h410e0 - 64'h410d0); + localparam PAD15 = log2ceil(64'h410f0 - 64'h410e0); + localparam PAD16 = log2ceil(64'h41100 - 64'h410f0); + localparam PAD17 = log2ceil(64'h41108 - 64'h41100); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h41108; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_addr_router_001_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x0 .. 0x40000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 19'h0 ) begin + src_channel = 18'b000000000000000010; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 15; + end + + // ( 0x40800 .. 0x41000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 19'h40800 ) begin + src_channel = 18'b000000000000000001; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 14; + end + + // ( 0x41010 .. 0x41020 ) + if ( {address[RG:PAD2],{PAD2{1'b0}}} == 19'h41010 ) begin + src_channel = 18'b010000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 13; + end + + // ( 0x41020 .. 0x41030 ) + if ( {address[RG:PAD3],{PAD3{1'b0}}} == 19'h41020 ) begin + src_channel = 18'b100000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 12; + end + + // ( 0x41030 .. 0x41040 ) + if ( {address[RG:PAD4],{PAD4{1'b0}}} == 19'h41030 ) begin + src_channel = 18'b001000000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 11; + end + + // ( 0x41040 .. 0x41050 ) + if ( {address[RG:PAD5],{PAD5{1'b0}}} == 19'h41040 ) begin + src_channel = 18'b000100000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; + end + + // ( 0x41050 .. 0x41060 ) + if ( {address[RG:PAD6],{PAD6{1'b0}}} == 19'h41050 ) begin + src_channel = 18'b000010000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; + end + + // ( 0x41060 .. 0x41070 ) + if ( {address[RG:PAD7],{PAD7{1'b0}}} == 19'h41060 ) begin + src_channel = 18'b000001000000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; + end + + // ( 0x41070 .. 0x41080 ) + if ( {address[RG:PAD8],{PAD8{1'b0}}} == 19'h41070 ) begin + src_channel = 18'b000000100000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; + end + + // ( 0x41080 .. 0x41090 ) + if ( {address[RG:PAD9],{PAD9{1'b0}}} == 19'h41080 ) begin + src_channel = 18'b000000010000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; + end + + // ( 0x41090 .. 0x410a0 ) + if ( {address[RG:PAD10],{PAD10{1'b0}}} == 19'h41090 ) begin + src_channel = 18'b000000001000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; + end + + // ( 0x410a0 .. 0x410b0 ) + if ( {address[RG:PAD11],{PAD11{1'b0}}} == 19'h410a0 ) begin + src_channel = 18'b000000000100000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; + end + + // ( 0x410b0 .. 0x410c0 ) + if ( {address[RG:PAD12],{PAD12{1'b0}}} == 19'h410b0 ) begin + src_channel = 18'b000000000010000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; + end + + // ( 0x410c0 .. 0x410d0 ) + if ( {address[RG:PAD13],{PAD13{1'b0}}} == 19'h410c0 ) begin + src_channel = 18'b000000000001000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 16; + end + + // ( 0x410d0 .. 0x410e0 ) + if ( {address[RG:PAD14],{PAD14{1'b0}}} == 19'h410d0 ) begin + src_channel = 18'b000000000000100000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 17; + end + + // ( 0x410e0 .. 0x410f0 ) + if ( {address[RG:PAD15],{PAD15{1'b0}}} == 19'h410e0 ) begin + src_channel = 18'b000000000000010000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + + // ( 0x410f0 .. 0x41100 ) + if ( {address[RG:PAD16],{PAD16{1'b0}}} == 19'h410f0 ) begin + src_channel = 18'b000000000000000100; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x41100 .. 0x41108 ) + if ( {address[RG:PAD17],{PAD17{1'b0}}} == 19'h41100 ) begin + src_channel = 18'b000000000000001000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv index d833b2f..0aef300 100644 --- a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv +++ b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux.sv @@ -1,116 +1,116 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 2 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 2; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - - assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{16{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv index 61d921c..433e8d0 100644 --- a/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv +++ b/nios_system/synthesis/submodules/nios_system_cmd_xbar_demux_001.sv @@ -1,356 +1,356 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_demux_001 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 18 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_cmd_xbar_demux_001 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - output reg src1_valid, - output reg [96-1 : 0] src1_data, // ST_DATA_W=96 - output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 - output reg src1_startofpacket, - output reg src1_endofpacket, - input src1_ready, - - output reg src2_valid, - output reg [96-1 : 0] src2_data, // ST_DATA_W=96 - output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 - output reg src2_startofpacket, - output reg src2_endofpacket, - input src2_ready, - - output reg src3_valid, - output reg [96-1 : 0] src3_data, // ST_DATA_W=96 - output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 - output reg src3_startofpacket, - output reg src3_endofpacket, - input src3_ready, - - output reg src4_valid, - output reg [96-1 : 0] src4_data, // ST_DATA_W=96 - output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 - output reg src4_startofpacket, - output reg src4_endofpacket, - input src4_ready, - - output reg src5_valid, - output reg [96-1 : 0] src5_data, // ST_DATA_W=96 - output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 - output reg src5_startofpacket, - output reg src5_endofpacket, - input src5_ready, - - output reg src6_valid, - output reg [96-1 : 0] src6_data, // ST_DATA_W=96 - output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 - output reg src6_startofpacket, - output reg src6_endofpacket, - input src6_ready, - - output reg src7_valid, - output reg [96-1 : 0] src7_data, // ST_DATA_W=96 - output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 - output reg src7_startofpacket, - output reg src7_endofpacket, - input src7_ready, - - output reg src8_valid, - output reg [96-1 : 0] src8_data, // ST_DATA_W=96 - output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 - output reg src8_startofpacket, - output reg src8_endofpacket, - input src8_ready, - - output reg src9_valid, - output reg [96-1 : 0] src9_data, // ST_DATA_W=96 - output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 - output reg src9_startofpacket, - output reg src9_endofpacket, - input src9_ready, - - output reg src10_valid, - output reg [96-1 : 0] src10_data, // ST_DATA_W=96 - output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 - output reg src10_startofpacket, - output reg src10_endofpacket, - input src10_ready, - - output reg src11_valid, - output reg [96-1 : 0] src11_data, // ST_DATA_W=96 - output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 - output reg src11_startofpacket, - output reg src11_endofpacket, - input src11_ready, - - output reg src12_valid, - output reg [96-1 : 0] src12_data, // ST_DATA_W=96 - output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 - output reg src12_startofpacket, - output reg src12_endofpacket, - input src12_ready, - - output reg src13_valid, - output reg [96-1 : 0] src13_data, // ST_DATA_W=96 - output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 - output reg src13_startofpacket, - output reg src13_endofpacket, - input src13_ready, - - output reg src14_valid, - output reg [96-1 : 0] src14_data, // ST_DATA_W=96 - output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 - output reg src14_startofpacket, - output reg src14_endofpacket, - input src14_ready, - - output reg src15_valid, - output reg [96-1 : 0] src15_data, // ST_DATA_W=96 - output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 - output reg src15_startofpacket, - output reg src15_endofpacket, - input src15_ready, - - output reg src16_valid, - output reg [96-1 : 0] src16_data, // ST_DATA_W=96 - output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 - output reg src16_startofpacket, - output reg src16_endofpacket, - input src16_ready, - - output reg src17_valid, - output reg [96-1 : 0] src17_data, // ST_DATA_W=96 - output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 - output reg src17_startofpacket, - output reg src17_endofpacket, - input src17_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 18; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - src1_data = sink_data; - src1_startofpacket = sink_startofpacket; - src1_endofpacket = sink_endofpacket; - src1_channel = sink_channel >> NUM_OUTPUTS; - - src1_valid = sink_channel[1] && sink_valid; - - src2_data = sink_data; - src2_startofpacket = sink_startofpacket; - src2_endofpacket = sink_endofpacket; - src2_channel = sink_channel >> NUM_OUTPUTS; - - src2_valid = sink_channel[2] && sink_valid; - - src3_data = sink_data; - src3_startofpacket = sink_startofpacket; - src3_endofpacket = sink_endofpacket; - src3_channel = sink_channel >> NUM_OUTPUTS; - - src3_valid = sink_channel[3] && sink_valid; - - src4_data = sink_data; - src4_startofpacket = sink_startofpacket; - src4_endofpacket = sink_endofpacket; - src4_channel = sink_channel >> NUM_OUTPUTS; - - src4_valid = sink_channel[4] && sink_valid; - - src5_data = sink_data; - src5_startofpacket = sink_startofpacket; - src5_endofpacket = sink_endofpacket; - src5_channel = sink_channel >> NUM_OUTPUTS; - - src5_valid = sink_channel[5] && sink_valid; - - src6_data = sink_data; - src6_startofpacket = sink_startofpacket; - src6_endofpacket = sink_endofpacket; - src6_channel = sink_channel >> NUM_OUTPUTS; - - src6_valid = sink_channel[6] && sink_valid; - - src7_data = sink_data; - src7_startofpacket = sink_startofpacket; - src7_endofpacket = sink_endofpacket; - src7_channel = sink_channel >> NUM_OUTPUTS; - - src7_valid = sink_channel[7] && sink_valid; - - src8_data = sink_data; - src8_startofpacket = sink_startofpacket; - src8_endofpacket = sink_endofpacket; - src8_channel = sink_channel >> NUM_OUTPUTS; - - src8_valid = sink_channel[8] && sink_valid; - - src9_data = sink_data; - src9_startofpacket = sink_startofpacket; - src9_endofpacket = sink_endofpacket; - src9_channel = sink_channel >> NUM_OUTPUTS; - - src9_valid = sink_channel[9] && sink_valid; - - src10_data = sink_data; - src10_startofpacket = sink_startofpacket; - src10_endofpacket = sink_endofpacket; - src10_channel = sink_channel >> NUM_OUTPUTS; - - src10_valid = sink_channel[10] && sink_valid; - - src11_data = sink_data; - src11_startofpacket = sink_startofpacket; - src11_endofpacket = sink_endofpacket; - src11_channel = sink_channel >> NUM_OUTPUTS; - - src11_valid = sink_channel[11] && sink_valid; - - src12_data = sink_data; - src12_startofpacket = sink_startofpacket; - src12_endofpacket = sink_endofpacket; - src12_channel = sink_channel >> NUM_OUTPUTS; - - src12_valid = sink_channel[12] && sink_valid; - - src13_data = sink_data; - src13_startofpacket = sink_startofpacket; - src13_endofpacket = sink_endofpacket; - src13_channel = sink_channel >> NUM_OUTPUTS; - - src13_valid = sink_channel[13] && sink_valid; - - src14_data = sink_data; - src14_startofpacket = sink_startofpacket; - src14_endofpacket = sink_endofpacket; - src14_channel = sink_channel >> NUM_OUTPUTS; - - src14_valid = sink_channel[14] && sink_valid; - - src15_data = sink_data; - src15_startofpacket = sink_startofpacket; - src15_endofpacket = sink_endofpacket; - src15_channel = sink_channel >> NUM_OUTPUTS; - - src15_valid = sink_channel[15] && sink_valid; - - src16_data = sink_data; - src16_startofpacket = sink_startofpacket; - src16_endofpacket = sink_endofpacket; - src16_channel = sink_channel >> NUM_OUTPUTS; - - src16_valid = sink_channel[16] && sink_valid; - - src17_data = sink_data; - src17_startofpacket = sink_startofpacket; - src17_endofpacket = sink_endofpacket; - src17_channel = sink_channel >> NUM_OUTPUTS; - - src17_valid = sink_channel[17] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - assign ready_vector[1] = src1_ready; - assign ready_vector[2] = src2_ready; - assign ready_vector[3] = src3_ready; - assign ready_vector[4] = src4_ready; - assign ready_vector[5] = src5_ready; - assign ready_vector[6] = src6_ready; - assign ready_vector[7] = src7_ready; - assign ready_vector[8] = src8_ready; - assign ready_vector[9] = src9_ready; - assign ready_vector[10] = src10_ready; - assign ready_vector[11] = src11_ready; - assign ready_vector[12] = src12_ready; - assign ready_vector[13] = src13_ready; - assign ready_vector[14] = src14_ready; - assign ready_vector[15] = src15_ready; - assign ready_vector[16] = src16_ready; - assign ready_vector[17] = src17_ready; - - assign sink_ready = |(sink_channel & ready_vector); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_demux_001 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 18 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_cmd_xbar_demux_001 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [96-1 : 0] src1_data, // ST_DATA_W=96 + output reg [18-1 : 0] src1_channel, // ST_CHANNEL_W=18 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + output reg src2_valid, + output reg [96-1 : 0] src2_data, // ST_DATA_W=96 + output reg [18-1 : 0] src2_channel, // ST_CHANNEL_W=18 + output reg src2_startofpacket, + output reg src2_endofpacket, + input src2_ready, + + output reg src3_valid, + output reg [96-1 : 0] src3_data, // ST_DATA_W=96 + output reg [18-1 : 0] src3_channel, // ST_CHANNEL_W=18 + output reg src3_startofpacket, + output reg src3_endofpacket, + input src3_ready, + + output reg src4_valid, + output reg [96-1 : 0] src4_data, // ST_DATA_W=96 + output reg [18-1 : 0] src4_channel, // ST_CHANNEL_W=18 + output reg src4_startofpacket, + output reg src4_endofpacket, + input src4_ready, + + output reg src5_valid, + output reg [96-1 : 0] src5_data, // ST_DATA_W=96 + output reg [18-1 : 0] src5_channel, // ST_CHANNEL_W=18 + output reg src5_startofpacket, + output reg src5_endofpacket, + input src5_ready, + + output reg src6_valid, + output reg [96-1 : 0] src6_data, // ST_DATA_W=96 + output reg [18-1 : 0] src6_channel, // ST_CHANNEL_W=18 + output reg src6_startofpacket, + output reg src6_endofpacket, + input src6_ready, + + output reg src7_valid, + output reg [96-1 : 0] src7_data, // ST_DATA_W=96 + output reg [18-1 : 0] src7_channel, // ST_CHANNEL_W=18 + output reg src7_startofpacket, + output reg src7_endofpacket, + input src7_ready, + + output reg src8_valid, + output reg [96-1 : 0] src8_data, // ST_DATA_W=96 + output reg [18-1 : 0] src8_channel, // ST_CHANNEL_W=18 + output reg src8_startofpacket, + output reg src8_endofpacket, + input src8_ready, + + output reg src9_valid, + output reg [96-1 : 0] src9_data, // ST_DATA_W=96 + output reg [18-1 : 0] src9_channel, // ST_CHANNEL_W=18 + output reg src9_startofpacket, + output reg src9_endofpacket, + input src9_ready, + + output reg src10_valid, + output reg [96-1 : 0] src10_data, // ST_DATA_W=96 + output reg [18-1 : 0] src10_channel, // ST_CHANNEL_W=18 + output reg src10_startofpacket, + output reg src10_endofpacket, + input src10_ready, + + output reg src11_valid, + output reg [96-1 : 0] src11_data, // ST_DATA_W=96 + output reg [18-1 : 0] src11_channel, // ST_CHANNEL_W=18 + output reg src11_startofpacket, + output reg src11_endofpacket, + input src11_ready, + + output reg src12_valid, + output reg [96-1 : 0] src12_data, // ST_DATA_W=96 + output reg [18-1 : 0] src12_channel, // ST_CHANNEL_W=18 + output reg src12_startofpacket, + output reg src12_endofpacket, + input src12_ready, + + output reg src13_valid, + output reg [96-1 : 0] src13_data, // ST_DATA_W=96 + output reg [18-1 : 0] src13_channel, // ST_CHANNEL_W=18 + output reg src13_startofpacket, + output reg src13_endofpacket, + input src13_ready, + + output reg src14_valid, + output reg [96-1 : 0] src14_data, // ST_DATA_W=96 + output reg [18-1 : 0] src14_channel, // ST_CHANNEL_W=18 + output reg src14_startofpacket, + output reg src14_endofpacket, + input src14_ready, + + output reg src15_valid, + output reg [96-1 : 0] src15_data, // ST_DATA_W=96 + output reg [18-1 : 0] src15_channel, // ST_CHANNEL_W=18 + output reg src15_startofpacket, + output reg src15_endofpacket, + input src15_ready, + + output reg src16_valid, + output reg [96-1 : 0] src16_data, // ST_DATA_W=96 + output reg [18-1 : 0] src16_channel, // ST_CHANNEL_W=18 + output reg src16_startofpacket, + output reg src16_endofpacket, + input src16_ready, + + output reg src17_valid, + output reg [96-1 : 0] src17_data, // ST_DATA_W=96 + output reg [18-1 : 0] src17_channel, // ST_CHANNEL_W=18 + output reg src17_startofpacket, + output reg src17_endofpacket, + input src17_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 18; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + src2_data = sink_data; + src2_startofpacket = sink_startofpacket; + src2_endofpacket = sink_endofpacket; + src2_channel = sink_channel >> NUM_OUTPUTS; + + src2_valid = sink_channel[2] && sink_valid; + + src3_data = sink_data; + src3_startofpacket = sink_startofpacket; + src3_endofpacket = sink_endofpacket; + src3_channel = sink_channel >> NUM_OUTPUTS; + + src3_valid = sink_channel[3] && sink_valid; + + src4_data = sink_data; + src4_startofpacket = sink_startofpacket; + src4_endofpacket = sink_endofpacket; + src4_channel = sink_channel >> NUM_OUTPUTS; + + src4_valid = sink_channel[4] && sink_valid; + + src5_data = sink_data; + src5_startofpacket = sink_startofpacket; + src5_endofpacket = sink_endofpacket; + src5_channel = sink_channel >> NUM_OUTPUTS; + + src5_valid = sink_channel[5] && sink_valid; + + src6_data = sink_data; + src6_startofpacket = sink_startofpacket; + src6_endofpacket = sink_endofpacket; + src6_channel = sink_channel >> NUM_OUTPUTS; + + src6_valid = sink_channel[6] && sink_valid; + + src7_data = sink_data; + src7_startofpacket = sink_startofpacket; + src7_endofpacket = sink_endofpacket; + src7_channel = sink_channel >> NUM_OUTPUTS; + + src7_valid = sink_channel[7] && sink_valid; + + src8_data = sink_data; + src8_startofpacket = sink_startofpacket; + src8_endofpacket = sink_endofpacket; + src8_channel = sink_channel >> NUM_OUTPUTS; + + src8_valid = sink_channel[8] && sink_valid; + + src9_data = sink_data; + src9_startofpacket = sink_startofpacket; + src9_endofpacket = sink_endofpacket; + src9_channel = sink_channel >> NUM_OUTPUTS; + + src9_valid = sink_channel[9] && sink_valid; + + src10_data = sink_data; + src10_startofpacket = sink_startofpacket; + src10_endofpacket = sink_endofpacket; + src10_channel = sink_channel >> NUM_OUTPUTS; + + src10_valid = sink_channel[10] && sink_valid; + + src11_data = sink_data; + src11_startofpacket = sink_startofpacket; + src11_endofpacket = sink_endofpacket; + src11_channel = sink_channel >> NUM_OUTPUTS; + + src11_valid = sink_channel[11] && sink_valid; + + src12_data = sink_data; + src12_startofpacket = sink_startofpacket; + src12_endofpacket = sink_endofpacket; + src12_channel = sink_channel >> NUM_OUTPUTS; + + src12_valid = sink_channel[12] && sink_valid; + + src13_data = sink_data; + src13_startofpacket = sink_startofpacket; + src13_endofpacket = sink_endofpacket; + src13_channel = sink_channel >> NUM_OUTPUTS; + + src13_valid = sink_channel[13] && sink_valid; + + src14_data = sink_data; + src14_startofpacket = sink_startofpacket; + src14_endofpacket = sink_endofpacket; + src14_channel = sink_channel >> NUM_OUTPUTS; + + src14_valid = sink_channel[14] && sink_valid; + + src15_data = sink_data; + src15_startofpacket = sink_startofpacket; + src15_endofpacket = sink_endofpacket; + src15_channel = sink_channel >> NUM_OUTPUTS; + + src15_valid = sink_channel[15] && sink_valid; + + src16_data = sink_data; + src16_startofpacket = sink_startofpacket; + src16_endofpacket = sink_endofpacket; + src16_channel = sink_channel >> NUM_OUTPUTS; + + src16_valid = sink_channel[16] && sink_valid; + + src17_data = sink_data; + src17_startofpacket = sink_startofpacket; + src17_endofpacket = sink_endofpacket; + src17_channel = sink_channel >> NUM_OUTPUTS; + + src17_valid = sink_channel[17] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + assign ready_vector[2] = src2_ready; + assign ready_vector[3] = src3_ready; + assign ready_vector[4] = src4_ready; + assign ready_vector[5] = src5_ready; + assign ready_vector[6] = src6_ready; + assign ready_vector[7] = src7_ready; + assign ready_vector[8] = src8_ready; + assign ready_vector[9] = src9_ready; + assign ready_vector[10] = src10_ready; + assign ready_vector[11] = src11_ready; + assign ready_vector[12] = src12_ready; + assign ready_vector[13] = src13_ready; + assign ready_vector[14] = src14_ready; + assign ready_vector[15] = src15_ready; + assign ready_vector[16] = src16_ready; + assign ready_vector[17] = src17_ready; + + assign sink_ready = |(sink_channel & ready_vector); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv b/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv index 494c070..76ec5b4 100644 --- a/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv +++ b/nios_system/synthesis/submodules/nios_system_cmd_xbar_mux.sv @@ -1,308 +1,308 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_cmd_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "round-robin" -// PIPELINE_ARB: 1 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_cmd_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 1; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - wire [NUM_INPUTS - 1 : 0] eop; - assign eop[0] = sink0_endofpacket; - assign eop[1] = sink1_endofpacket; - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - reg [NUM_INPUTS - 1 : 0] locked = '0; - always @(posedge clk or posedge reset) begin - if (reset) begin - locked <= '0; - end - else begin - locked <= next_grant & lock; - end - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (update_grant) begin - share_count <= next_grant_share; - share_count_zero_flag <= (next_grant_share == '0); - end - else if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // The pipeline delays grant by one cycle, so - // we have to calculate the update_grant signal - // one cycle ahead of time. - // - // Possible optimization: omit the first clause - // "if (!packet_in_progress & ~src_valid) ..." - // cost: one idle cycle at the the beginning of each - // grant cycle. - // benefit: save a small amount of logic. - // ------------------------------------------ - if (!packet_in_progress & !src_valid) - update_grant = 1; - if (last_cycle && share_count_zero_flag) - update_grant = 1; - end - - wire save_grant; - assign save_grant = update_grant; - assign grant = saved_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] prev_request; - always @(posedge clk, posedge reset) begin - if (reset) - prev_request <= '0; - else - prev_request <= request & ~(valid & eop); - end - - assign request = (PIPELINE_ARB == 1) ? valid | locked : - prev_request | valid | locked; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("round-robin"), - .PIPELINE (1) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_cmd_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 1 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_cmd_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 1; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + wire [NUM_INPUTS - 1 : 0] eop; + assign eop[0] = sink0_endofpacket; + assign eop[1] = sink1_endofpacket; + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + reg [NUM_INPUTS - 1 : 0] locked = '0; + always @(posedge clk or posedge reset) begin + if (reset) begin + locked <= '0; + end + else begin + locked <= next_grant & lock; + end + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (update_grant) begin + share_count <= next_grant_share; + share_count_zero_flag <= (next_grant_share == '0); + end + else if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // The pipeline delays grant by one cycle, so + // we have to calculate the update_grant signal + // one cycle ahead of time. + // + // Possible optimization: omit the first clause + // "if (!packet_in_progress & ~src_valid) ..." + // cost: one idle cycle at the the beginning of each + // grant cycle. + // benefit: save a small amount of logic. + // ------------------------------------------ + if (!packet_in_progress & !src_valid) + update_grant = 1; + if (last_cycle && share_count_zero_flag) + update_grant = 1; + end + + wire save_grant; + assign save_grant = update_grant; + assign grant = saved_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] prev_request; + always @(posedge clk, posedge reset) begin + if (reset) + prev_request <= '0; + else + prev_request <= request & ~(valid & eop); + end + + assign request = (PIPELINE_ARB == 1) ? valid | locked : + prev_request | valid | locked; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("round-robin"), + .PIPELINE (1) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/nios_system/synthesis/submodules/nios_system_hex0.v b/nios_system/synthesis/submodules/nios_system_hex0.v index ec4cd20..365eed9 100644 --- a/nios_system/synthesis/submodules/nios_system_hex0.v +++ b/nios_system/synthesis/submodules/nios_system_hex0.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_hex0 ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output [ 6: 0] out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg [ 6: 0] data_out; - wire [ 6: 0] out_port; - wire [ 6: 0] read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {7 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata[6 : 0]; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_hex0 ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 6: 0] out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 6: 0] data_out; + wire [ 6: 0] out_port; + wire [ 6: 0] read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {7 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata[6 : 0]; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_id_router.sv b/nios_system/synthesis/submodules/nios_system_id_router.sv index cb46634..90937e8 100644 --- a/nios_system/synthesis/submodules/nios_system_id_router.sv +++ b/nios_system/synthesis/submodules/nios_system_id_router.sv @@ -1,221 +1,221 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 1 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 1 ) begin - src_channel = 18'b01; - end - - if (destid == 0 ) begin - src_channel = 18'b10; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 1 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 1 ) begin + src_channel = 18'b01; + end + + if (destid == 0 ) begin + src_channel = 18'b10; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_id_router_002.sv b/nios_system/synthesis/submodules/nios_system_id_router_002.sv index 6006063..a80e831 100644 --- a/nios_system/synthesis/submodules/nios_system_id_router_002.sv +++ b/nios_system/synthesis/submodules/nios_system_id_router_002.sv @@ -1,217 +1,217 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Merlin Router -// -// Asserts the appropriate one-hot encoded channel based on -// either (a) the address or (b) the dest id. The DECODER_TYPE -// parameter controls this behaviour. 0 means address decoder, -// 1 means dest id decoder. -// -// In the case of (a), it also sets the destination id. -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_id_router_002_default_decode - #( - parameter DEFAULT_CHANNEL = 0, - DEFAULT_WR_CHANNEL = -1, - DEFAULT_RD_CHANNEL = -1, - DEFAULT_DESTID = 0 - ) - (output [85 - 81 : 0] default_destination_id, - output [18-1 : 0] default_wr_channel, - output [18-1 : 0] default_rd_channel, - output [18-1 : 0] default_src_channel - ); - - assign default_destination_id = - DEFAULT_DESTID[85 - 81 : 0]; - - generate begin : default_decode - if (DEFAULT_CHANNEL == -1) begin - assign default_src_channel = '0; - end - else begin - assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; - end - end - endgenerate - - generate begin : default_decode_rw - if (DEFAULT_RD_CHANNEL == -1) begin - assign default_wr_channel = '0; - assign default_rd_channel = '0; - end - else begin - assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; - assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; - end - end - endgenerate - -endmodule - - -module nios_system_id_router_002 -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // Command Sink (Input) - // ------------------- - input sink_valid, - input [96-1 : 0] sink_data, - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Command Source (Output) - // ------------------- - output src_valid, - output reg [96-1 : 0] src_data, - output reg [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready -); - - // ------------------------------------------------------- - // Local parameters and variables - // ------------------------------------------------------- - localparam PKT_ADDR_H = 54; - localparam PKT_ADDR_L = 36; - localparam PKT_DEST_ID_H = 85; - localparam PKT_DEST_ID_L = 81; - localparam PKT_PROTECTION_H = 89; - localparam PKT_PROTECTION_L = 87; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam DECODER_TYPE = 1; - - localparam PKT_TRANS_WRITE = 57; - localparam PKT_TRANS_READ = 58; - - localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; - localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; - - - - // ------------------------------------------------------- - // Figure out the number of bits to mask off for each slave span - // during address decoding - // ------------------------------------------------------- - // ------------------------------------------------------- - // Work out which address bits are significant based on the - // address range of the slaves. If the required width is too - // large or too small, we use the address field width instead. - // ------------------------------------------------------- - localparam ADDR_RANGE = 64'h0; - localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); - localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || - (RANGE_ADDR_WIDTH == 0) ? - PKT_ADDR_H : - PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; - - localparam RG = RANGE_ADDR_WIDTH; - - reg [PKT_DEST_ID_W-1 : 0] destid; - - // ------------------------------------------------------- - // Pass almost everything through, untouched - // ------------------------------------------------------- - assign sink_ready = src_ready; - assign src_valid = sink_valid; - assign src_startofpacket = sink_startofpacket; - assign src_endofpacket = sink_endofpacket; - - wire [PKT_DEST_ID_W-1:0] default_destid; - wire [18-1 : 0] default_src_channel; - - - - - - nios_system_id_router_002_default_decode the_default_decode( - .default_destination_id (default_destid), - .default_wr_channel (), - .default_rd_channel (), - .default_src_channel (default_src_channel) - ); - - always @* begin - src_data = sink_data; - src_channel = default_src_channel; - - // -------------------------------------------------- - // DestinationID Decoder - // Sets the channel based on the destination ID. - // -------------------------------------------------- - destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; - - - - if (destid == 0 ) begin - src_channel = 18'b1; - end - - -end - - - // -------------------------------------------------- - // Ceil(log2()) function - // -------------------------------------------------- - function integer log2ceil; - input reg[65:0] val; - reg [65:0] i; - - begin - i = 1; - log2ceil = 0; - - while (i < val) begin - log2ceil = log2ceil + 1; - i = i << 1; - end - end - endfunction - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_id_router_002_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_WR_CHANNEL = -1, + DEFAULT_RD_CHANNEL = -1, + DEFAULT_DESTID = 0 + ) + (output [85 - 81 : 0] default_destination_id, + output [18-1 : 0] default_wr_channel, + output [18-1 : 0] default_rd_channel, + output [18-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[85 - 81 : 0]; + + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) begin + assign default_src_channel = '0; + end + else begin + assign default_src_channel = 18'b1 << DEFAULT_CHANNEL; + end + end + endgenerate + + generate begin : default_decode_rw + if (DEFAULT_RD_CHANNEL == -1) begin + assign default_wr_channel = '0; + assign default_rd_channel = '0; + end + else begin + assign default_wr_channel = 18'b1 << DEFAULT_WR_CHANNEL; + assign default_rd_channel = 18'b1 << DEFAULT_RD_CHANNEL; + end + end + endgenerate + +endmodule + + +module nios_system_id_router_002 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [96-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [96-1 : 0] src_data, + output reg [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 54; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 85; + localparam PKT_DEST_ID_L = 81; + localparam PKT_PROTECTION_H = 89; + localparam PKT_PROTECTION_L = 87; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 57; + localparam PKT_TRANS_READ = 58; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + + localparam RG = RANGE_ADDR_WIDTH; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [18-1 : 0] default_src_channel; + + + + + + nios_system_id_router_002_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_wr_channel (), + .default_rd_channel (), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + + if (destid == 0 ) begin + src_channel = 18'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_irq_mapper.sv b/nios_system/synthesis/submodules/nios_system_irq_mapper.sv index d318630..cc0a8bb 100644 --- a/nios_system/synthesis/submodules/nios_system_irq_mapper.sv +++ b/nios_system/synthesis/submodules/nios_system_irq_mapper.sv @@ -1,59 +1,59 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------------------- -// Altera IRQ Mapper -// -// Parameters -// NUM_RCVRS : 1 -// SENDER_IRW_WIDTH : 32 -// IRQ_MAP : 0:5 -// -// ------------------------------------------------------- - -`timescale 1 ns / 1 ns - -module nios_system_irq_mapper -( - // ------------------- - // Clock & Reset - // ------------------- - input clk, - input reset, - - // ------------------- - // IRQ Receivers - // ------------------- - input receiver0_irq, - - // ------------------- - // Command Source (Output) - // ------------------- - output reg [31 : 0] sender_irq -); - - - always @* begin - sender_irq = 0; - - sender_irq[5] = receiver0_irq; - end - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 1 +// SENDER_IRW_WIDTH : 32 +// IRQ_MAP : 0:5 +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module nios_system_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + input receiver0_irq, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [31 : 0] sender_irq +); + + + always @* begin + sender_irq = 0; + + sender_irq[5] = receiver0_irq; + end + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_jtag_uart.v b/nios_system/synthesis/submodules/nios_system_jtag_uart.v index 11ff56f..0d02445 100644 --- a/nios_system/synthesis/submodules/nios_system_jtag_uart.v +++ b/nios_system/synthesis/submodules/nios_system_jtag_uart.v @@ -1,583 +1,583 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_w ( - // inputs: - clk, - fifo_wdata, - fifo_wr, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input [ 7: 0] fifo_wdata; - input fifo_wr; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - always @(posedge clk) - begin - if (fifo_wr) - $write("%c", fifo_wdata); - end - - - assign wfifo_used = {6{1'b0}}; - assign r_dat = {8{1'b0}}; - assign fifo_FF = 1'b0; - assign wfifo_empty = 1'b1; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_w ( - // inputs: - clk, - fifo_clear, - fifo_wdata, - fifo_wr, - rd_wfifo, - - // outputs: - fifo_FF, - r_dat, - wfifo_empty, - wfifo_used - ) -; - - output fifo_FF; - output [ 7: 0] r_dat; - output wfifo_empty; - output [ 5: 0] wfifo_used; - input clk; - input fifo_clear; - input [ 7: 0] fifo_wdata; - input fifo_wr; - input rd_wfifo; - - wire fifo_FF; - wire [ 7: 0] r_dat; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo wfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (fifo_wdata), -// .empty (wfifo_empty), -// .full (fifo_FF), -// .q (r_dat), -// .rdreq (rd_wfifo), -// .usedw (wfifo_used), -// .wrreq (fifo_wr) -// ); -// -// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// wfifo.lpm_numwords = 64, -// wfifo.lpm_showahead = "OFF", -// wfifo.lpm_type = "scfifo", -// wfifo.lpm_width = 8, -// wfifo.lpm_widthu = 6, -// wfifo.overflow_checking = "OFF", -// wfifo.underflow_checking = "OFF", -// wfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_sim_scfifo_r ( - // inputs: - clk, - fifo_rd, - rst_n, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_rd; - input rst_n; - - reg [ 31: 0] bytes_left; - wire fifo_EF; - reg fifo_rd_d; - wire [ 7: 0] fifo_rdata; - wire new_rom; - wire [ 31: 0] num_bytes; - wire [ 6: 0] rfifo_entries; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Generate rfifo_entries for simulation - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - bytes_left <= 32'h0; - fifo_rd_d <= 1'b0; - end - else - begin - fifo_rd_d <= fifo_rd; - // decrement on read - if (fifo_rd_d) - bytes_left <= bytes_left - 1'b1; - // catch new contents - if (new_rom) - bytes_left <= num_bytes; - end - end - - - assign fifo_EF = bytes_left == 32'b0; - assign rfifo_full = bytes_left > 7'h40; - assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; - assign rfifo_used = rfifo_entries[5 : 0]; - assign new_rom = 1'b0; - assign num_bytes = 32'b0; - assign fifo_rdata = 8'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart_scfifo_r ( - // inputs: - clk, - fifo_clear, - fifo_rd, - rst_n, - t_dat, - wr_rfifo, - - // outputs: - fifo_EF, - fifo_rdata, - rfifo_full, - rfifo_used - ) -; - - output fifo_EF; - output [ 7: 0] fifo_rdata; - output rfifo_full; - output [ 5: 0] rfifo_used; - input clk; - input fifo_clear; - input fifo_rd; - input rst_n; - input [ 7: 0] t_dat; - input wr_rfifo; - - wire fifo_EF; - wire [ 7: 0] fifo_rdata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n) - ); - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// scfifo rfifo -// ( -// .aclr (fifo_clear), -// .clock (clk), -// .data (t_dat), -// .empty (fifo_EF), -// .full (rfifo_full), -// .q (fifo_rdata), -// .rdreq (fifo_rd), -// .usedw (rfifo_used), -// .wrreq (wr_rfifo) -// ); -// -// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", -// rfifo.lpm_numwords = 64, -// rfifo.lpm_showahead = "OFF", -// rfifo.lpm_type = "scfifo", -// rfifo.lpm_width = 8, -// rfifo.lpm_widthu = 6, -// rfifo.overflow_checking = "OFF", -// rfifo.underflow_checking = "OFF", -// rfifo.use_eab = "ON"; -// -//synthesis read_comments_as_HDL off - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_jtag_uart ( - // inputs: - av_address, - av_chipselect, - av_read_n, - av_write_n, - av_writedata, - clk, - rst_n, - - // outputs: - av_irq, - av_readdata, - av_waitrequest, - dataavailable, - readyfordata - ) - /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; - - output av_irq; - output [ 31: 0] av_readdata; - output av_waitrequest; - output dataavailable; - output readyfordata; - input av_address; - input av_chipselect; - input av_read_n; - input av_write_n; - input [ 31: 0] av_writedata; - input clk; - input rst_n; - - reg ac; - wire activity; - wire av_irq; - wire [ 31: 0] av_readdata; - reg av_waitrequest; - reg dataavailable; - reg fifo_AE; - reg fifo_AF; - wire fifo_EF; - wire fifo_FF; - wire fifo_clear; - wire fifo_rd; - wire [ 7: 0] fifo_rdata; - wire [ 7: 0] fifo_wdata; - reg fifo_wr; - reg ien_AE; - reg ien_AF; - wire ipen_AE; - wire ipen_AF; - reg pause_irq; - wire [ 7: 0] r_dat; - wire r_ena; - reg r_val; - wire rd_wfifo; - reg read_0; - reg readyfordata; - wire rfifo_full; - wire [ 5: 0] rfifo_used; - reg rvalid; - reg sim_r_ena; - reg sim_t_dat; - reg sim_t_ena; - reg sim_t_pause; - wire [ 7: 0] t_dat; - reg t_dav; - wire t_ena; - wire t_pause; - wire wfifo_empty; - wire [ 5: 0] wfifo_used; - reg woverflow; - wire wr_rfifo; - //avalon_jtag_slave, which is an e_avalon_slave - assign rd_wfifo = r_ena & ~wfifo_empty; - assign wr_rfifo = t_ena & ~rfifo_full; - assign fifo_clear = ~rst_n; - nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w - ( - .clk (clk), - .fifo_FF (fifo_FF), - .fifo_clear (fifo_clear), - .fifo_wdata (fifo_wdata), - .fifo_wr (fifo_wr), - .r_dat (r_dat), - .rd_wfifo (rd_wfifo), - .wfifo_empty (wfifo_empty), - .wfifo_used (wfifo_used) - ); - - nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r - ( - .clk (clk), - .fifo_EF (fifo_EF), - .fifo_clear (fifo_clear), - .fifo_rd (fifo_rd), - .fifo_rdata (fifo_rdata), - .rfifo_full (rfifo_full), - .rfifo_used (rfifo_used), - .rst_n (rst_n), - .t_dat (t_dat), - .wr_rfifo (wr_rfifo) - ); - - assign ipen_AE = ien_AE & fifo_AE; - assign ipen_AF = ien_AF & (pause_irq | fifo_AF); - assign av_irq = ipen_AE | ipen_AF; - assign activity = t_pause | t_ena; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - pause_irq <= 1'b0; - else // only if fifo is not empty... - if (t_pause & ~fifo_EF) - pause_irq <= 1'b1; - else if (read_0) - pause_irq <= 1'b0; - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - r_val <= 1'b0; - t_dav <= 1'b1; - end - else - begin - r_val <= r_ena & ~wfifo_empty; - t_dav <= ~rfifo_full; - end - end - - - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - begin - fifo_AE <= 1'b0; - fifo_AF <= 1'b0; - fifo_wr <= 1'b0; - rvalid <= 1'b0; - read_0 <= 1'b0; - ien_AE <= 1'b0; - ien_AF <= 1'b0; - ac <= 1'b0; - woverflow <= 1'b0; - av_waitrequest <= 1'b1; - end - else - begin - fifo_AE <= {fifo_FF,wfifo_used} <= 8; - fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; - fifo_wr <= 1'b0; - read_0 <= 1'b0; - av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); - if (activity) - ac <= 1'b1; - // write - if (av_chipselect & ~av_write_n & av_waitrequest) - // addr 1 is control; addr 0 is data - if (av_address) - begin - ien_AF <= av_writedata[0]; - ien_AE <= av_writedata[1]; - if (av_writedata[10] & ~activity) - ac <= 1'b0; - end - else - begin - fifo_wr <= ~fifo_FF; - woverflow <= fifo_FF; - end - // read - if (av_chipselect & ~av_read_n & av_waitrequest) - begin - // addr 1 is interrupt; addr 0 is data - if (~av_address) - rvalid <= ~fifo_EF; - read_0 <= ~av_address; - end - end - end - - - assign fifo_wdata = av_writedata[7 : 0]; - assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; - assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; - always @(posedge clk or negedge rst_n) - begin - if (rst_n == 0) - readyfordata <= 0; - else - readyfordata <= ~fifo_FF; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - // Tie off Atlantic Interface signals not used for simulation - always @(posedge clk) - begin - sim_t_pause <= 1'b0; - sim_t_ena <= 1'b0; - sim_t_dat <= t_dav ? r_dat : {8{r_val}}; - sim_r_ena <= 1'b0; - end - - - assign r_ena = sim_r_ena; - assign t_ena = sim_t_ena; - assign t_dat = sim_t_dat; - assign t_pause = sim_t_pause; - always @(fifo_EF) - begin - dataavailable = ~fifo_EF; - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic -// ( -// .clk (clk), -// .r_dat (r_dat), -// .r_ena (r_ena), -// .r_val (r_val), -// .rst_n (rst_n), -// .t_dat (t_dat), -// .t_dav (t_dav), -// .t_ena (t_ena), -// .t_pause (t_pause) -// ); -// -// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, -// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; -// -// always @(posedge clk or negedge rst_n) -// begin -// if (rst_n == 0) -// dataavailable <= 0; -// else -// dataavailable <= ~fifo_EF; -// end -// -// -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_w ( + // inputs: + clk, + fifo_wdata, + fifo_wr, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input [ 7: 0] fifo_wdata; + input fifo_wr; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + always @(posedge clk) + begin + if (fifo_wr) + $write("%c", fifo_wdata); + end + + + assign wfifo_used = {6{1'b0}}; + assign r_dat = {8{1'b0}}; + assign fifo_FF = 1'b0; + assign wfifo_empty = 1'b1; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_w ( + // inputs: + clk, + fifo_clear, + fifo_wdata, + fifo_wr, + rd_wfifo, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input fifo_clear; + input [ 7: 0] fifo_wdata; + input fifo_wr; + input rd_wfifo; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_w the_nios_system_jtag_uart_sim_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo wfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (fifo_wdata), +// .empty (wfifo_empty), +// .full (fifo_FF), +// .q (r_dat), +// .rdreq (rd_wfifo), +// .usedw (wfifo_used), +// .wrreq (fifo_wr) +// ); +// +// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// wfifo.lpm_numwords = 64, +// wfifo.lpm_showahead = "OFF", +// wfifo.lpm_type = "scfifo", +// wfifo.lpm_width = 8, +// wfifo.lpm_widthu = 6, +// wfifo.overflow_checking = "OFF", +// wfifo.underflow_checking = "OFF", +// wfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_sim_scfifo_r ( + // inputs: + clk, + fifo_rd, + rst_n, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_rd; + input rst_n; + + reg [ 31: 0] bytes_left; + wire fifo_EF; + reg fifo_rd_d; + wire [ 7: 0] fifo_rdata; + wire new_rom; + wire [ 31: 0] num_bytes; + wire [ 6: 0] rfifo_entries; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Generate rfifo_entries for simulation + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + bytes_left <= 32'h0; + fifo_rd_d <= 1'b0; + end + else + begin + fifo_rd_d <= fifo_rd; + // decrement on read + if (fifo_rd_d) + bytes_left <= bytes_left - 1'b1; + // catch new contents + if (new_rom) + bytes_left <= num_bytes; + end + end + + + assign fifo_EF = bytes_left == 32'b0; + assign rfifo_full = bytes_left > 7'h40; + assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; + assign rfifo_used = rfifo_entries[5 : 0]; + assign new_rom = 1'b0; + assign num_bytes = 32'b0; + assign fifo_rdata = 8'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart_scfifo_r ( + // inputs: + clk, + fifo_clear, + fifo_rd, + rst_n, + t_dat, + wr_rfifo, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_clear; + input fifo_rd; + input rst_n; + input [ 7: 0] t_dat; + input wr_rfifo; + + wire fifo_EF; + wire [ 7: 0] fifo_rdata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + nios_system_jtag_uart_sim_scfifo_r the_nios_system_jtag_uart_sim_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo rfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (t_dat), +// .empty (fifo_EF), +// .full (rfifo_full), +// .q (fifo_rdata), +// .rdreq (fifo_rd), +// .usedw (rfifo_used), +// .wrreq (wr_rfifo) +// ); +// +// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// rfifo.lpm_numwords = 64, +// rfifo.lpm_showahead = "OFF", +// rfifo.lpm_type = "scfifo", +// rfifo.lpm_width = 8, +// rfifo.lpm_widthu = 6, +// rfifo.overflow_checking = "OFF", +// rfifo.underflow_checking = "OFF", +// rfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_jtag_uart ( + // inputs: + av_address, + av_chipselect, + av_read_n, + av_write_n, + av_writedata, + clk, + rst_n, + + // outputs: + av_irq, + av_readdata, + av_waitrequest, + dataavailable, + readyfordata + ) + /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; + + output av_irq; + output [ 31: 0] av_readdata; + output av_waitrequest; + output dataavailable; + output readyfordata; + input av_address; + input av_chipselect; + input av_read_n; + input av_write_n; + input [ 31: 0] av_writedata; + input clk; + input rst_n; + + reg ac; + wire activity; + wire av_irq; + wire [ 31: 0] av_readdata; + reg av_waitrequest; + reg dataavailable; + reg fifo_AE; + reg fifo_AF; + wire fifo_EF; + wire fifo_FF; + wire fifo_clear; + wire fifo_rd; + wire [ 7: 0] fifo_rdata; + wire [ 7: 0] fifo_wdata; + reg fifo_wr; + reg ien_AE; + reg ien_AF; + wire ipen_AE; + wire ipen_AF; + reg pause_irq; + wire [ 7: 0] r_dat; + wire r_ena; + reg r_val; + wire rd_wfifo; + reg read_0; + reg readyfordata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + reg rvalid; + reg sim_r_ena; + reg sim_t_dat; + reg sim_t_ena; + reg sim_t_pause; + wire [ 7: 0] t_dat; + reg t_dav; + wire t_ena; + wire t_pause; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + reg woverflow; + wire wr_rfifo; + //avalon_jtag_slave, which is an e_avalon_slave + assign rd_wfifo = r_ena & ~wfifo_empty; + assign wr_rfifo = t_ena & ~rfifo_full; + assign fifo_clear = ~rst_n; + nios_system_jtag_uart_scfifo_w the_nios_system_jtag_uart_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_clear (fifo_clear), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .rd_wfifo (rd_wfifo), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + nios_system_jtag_uart_scfifo_r the_nios_system_jtag_uart_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_clear (fifo_clear), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n), + .t_dat (t_dat), + .wr_rfifo (wr_rfifo) + ); + + assign ipen_AE = ien_AE & fifo_AE; + assign ipen_AF = ien_AF & (pause_irq | fifo_AF); + assign av_irq = ipen_AE | ipen_AF; + assign activity = t_pause | t_ena; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + pause_irq <= 1'b0; + else // only if fifo is not empty... + if (t_pause & ~fifo_EF) + pause_irq <= 1'b1; + else if (read_0) + pause_irq <= 1'b0; + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + r_val <= 1'b0; + t_dav <= 1'b1; + end + else + begin + r_val <= r_ena & ~wfifo_empty; + t_dav <= ~rfifo_full; + end + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + fifo_AE <= 1'b0; + fifo_AF <= 1'b0; + fifo_wr <= 1'b0; + rvalid <= 1'b0; + read_0 <= 1'b0; + ien_AE <= 1'b0; + ien_AF <= 1'b0; + ac <= 1'b0; + woverflow <= 1'b0; + av_waitrequest <= 1'b1; + end + else + begin + fifo_AE <= {fifo_FF,wfifo_used} <= 8; + fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; + fifo_wr <= 1'b0; + read_0 <= 1'b0; + av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); + if (activity) + ac <= 1'b1; + // write + if (av_chipselect & ~av_write_n & av_waitrequest) + // addr 1 is control; addr 0 is data + if (av_address) + begin + ien_AF <= av_writedata[0]; + ien_AE <= av_writedata[1]; + if (av_writedata[10] & ~activity) + ac <= 1'b0; + end + else + begin + fifo_wr <= ~fifo_FF; + woverflow <= fifo_FF; + end + // read + if (av_chipselect & ~av_read_n & av_waitrequest) + begin + // addr 1 is interrupt; addr 0 is data + if (~av_address) + rvalid <= ~fifo_EF; + read_0 <= ~av_address; + end + end + end + + + assign fifo_wdata = av_writedata[7 : 0]; + assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; + assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + readyfordata <= 0; + else + readyfordata <= ~fifo_FF; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Tie off Atlantic Interface signals not used for simulation + always @(posedge clk) + begin + sim_t_pause <= 1'b0; + sim_t_ena <= 1'b0; + sim_t_dat <= t_dav ? r_dat : {8{r_val}}; + sim_r_ena <= 1'b0; + end + + + assign r_ena = sim_r_ena; + assign t_ena = sim_t_ena; + assign t_dat = sim_t_dat; + assign t_pause = sim_t_pause; + always @(fifo_EF) + begin + dataavailable = ~fifo_EF; + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// alt_jtag_atlantic nios_system_jtag_uart_alt_jtag_atlantic +// ( +// .clk (clk), +// .r_dat (r_dat), +// .r_ena (r_ena), +// .r_val (r_val), +// .rst_n (rst_n), +// .t_dat (t_dat), +// .t_dav (t_dav), +// .t_ena (t_ena), +// .t_pause (t_pause) +// ); +// +// defparam nios_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, +// nios_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; +// +// always @(posedge clk or negedge rst_n) +// begin +// if (rst_n == 0) +// dataavailable <= 0; +// else +// dataavailable <= ~fifo_EF; +// end +// +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v b/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v index 221f3db..f58d30f 100644 --- a/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v +++ b/nios_system/synthesis/submodules/nios_system_lcd_16207_0.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_16207_0 ( - // inputs: - address, - begintransfer, - clk, - read, - reset_n, - write, - writedata, - - // outputs: - LCD_E, - LCD_RS, - LCD_RW, - LCD_data, - readdata - ) -; - - output LCD_E; - output LCD_RS; - output LCD_RW; - inout [ 7: 0] LCD_data; - output [ 7: 0] readdata; - input [ 1: 0] address; - input begintransfer; - input clk; - input read; - input reset_n; - input write; - input [ 7: 0] writedata; - - wire LCD_E; - wire LCD_RS; - wire LCD_RW; - wire [ 7: 0] LCD_data; - wire [ 7: 0] readdata; - assign LCD_RW = address[0]; - assign LCD_RS = address[1]; - assign LCD_E = read | write; - assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; - assign readdata = LCD_data; - //control_slave, which is an e_avalon_slave - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_16207_0 ( + // inputs: + address, + begintransfer, + clk, + read, + reset_n, + write, + writedata, + + // outputs: + LCD_E, + LCD_RS, + LCD_RW, + LCD_data, + readdata + ) +; + + output LCD_E; + output LCD_RS; + output LCD_RW; + inout [ 7: 0] LCD_data; + output [ 7: 0] readdata; + input [ 1: 0] address; + input begintransfer; + input clk; + input read; + input reset_n; + input write; + input [ 7: 0] writedata; + + wire LCD_E; + wire LCD_RS; + wire LCD_RW; + wire [ 7: 0] LCD_data; + wire [ 7: 0] readdata; + assign LCD_RW = address[0]; + assign LCD_RS = address[1]; + assign LCD_E = read | write; + assign LCD_data = (address[0]) ? {8{1'bz}} : writedata; + assign readdata = LCD_data; + //control_slave, which is an e_avalon_slave + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_lcd_on.v b/nios_system/synthesis/submodules/nios_system_lcd_on.v index ed02e25..4e9a8dc 100644 --- a/nios_system/synthesis/submodules/nios_system_lcd_on.v +++ b/nios_system/synthesis/submodules/nios_system_lcd_on.v @@ -1,66 +1,66 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_lcd_on ( - // inputs: - address, - chipselect, - clk, - reset_n, - write_n, - writedata, - - // outputs: - out_port, - readdata - ) -; - - output out_port; - output [ 31: 0] readdata; - input [ 1: 0] address; - input chipselect; - input clk; - input reset_n; - input write_n; - input [ 31: 0] writedata; - - wire clk_en; - reg data_out; - wire out_port; - wire read_mux_out; - wire [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {1 {(address == 0)}} & data_out; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - data_out <= 0; - else if (chipselect && ~write_n && (address == 0)) - data_out <= writedata; - end - - - assign readdata = {32'b0 | read_mux_out}; - assign out_port = data_out; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_lcd_on ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc b/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc index 41645ff..4848c5a 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor.sdc @@ -1,53 +1,53 @@ -# Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -# use of Altera Corporation's design tools, logic functions and other -# software and tools, and its AMPP partner logic functions, and any -# output files any of the foregoing (including device programming or -# simulation files), and any associated documentation or information are -# expressly subject to the terms and conditions of the Altera Program -# License Subscription Agreement or other applicable license agreement, -# including, without limitation, that your use is for the sole purpose -# of programming logic devices manufactured by Altera and sold by Altera -# or its authorized distributors. Please refer to the applicable -# agreement for further details. - -#************************************************************** -# Timequest JTAG clock definition -# Uncommenting the following lines will define the JTAG -# clock in TimeQuest Timing Analyzer -#************************************************************** - -#create_clock -period 10MHz {altera_reserved_tck} -#set_clock_groups -asynchronous -group {altera_reserved_tck} - -#************************************************************** -# Set TCL Path Variables -#************************************************************** - -set nios_system_nios2_processor nios_system_nios2_processor:* -set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci -set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break -set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem -set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug -set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper -set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck -set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk -set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] -set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] -set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] -set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] -set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] -set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] -set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] - -#************************************************************** -# Set False Paths -#************************************************************** - -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] -set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] -set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* -set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* -set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go +# Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +# use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any +# output files any of the foregoing (including device programming or +# simulation files), and any associated documentation or information are +# expressly subject to the terms and conditions of the Altera Program +# License Subscription Agreement or other applicable license agreement, +# including, without limitation, that your use is for the sole purpose +# of programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +#************************************************************** +# Timequest JTAG clock definition +# Uncommenting the following lines will define the JTAG +# clock in TimeQuest Timing Analyzer +#************************************************************** + +#create_clock -period 10MHz {altera_reserved_tck} +#set_clock_groups -asynchronous -group {altera_reserved_tck} + +#************************************************************** +# Set TCL Path Variables +#************************************************************** + +set nios_system_nios2_processor nios_system_nios2_processor:* +set nios_system_nios2_processor_oci nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci +set nios_system_nios2_processor_oci_break nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break +set nios_system_nios2_processor_ocimem nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem +set nios_system_nios2_processor_oci_debug nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug +set nios_system_nios2_processor_wrapper nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper +set nios_system_nios2_processor_jtag_tck nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck +set nios_system_nios2_processor_jtag_sysclk nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk +set nios_system_nios2_processor_oci_path [format "%s|%s" $nios_system_nios2_processor $nios_system_nios2_processor_oci] +set nios_system_nios2_processor_oci_break_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_break] +set nios_system_nios2_processor_ocimem_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_ocimem] +set nios_system_nios2_processor_oci_debug_path [format "%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_oci_debug] +set nios_system_nios2_processor_jtag_tck_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_tck] +set nios_system_nios2_processor_jtag_sysclk_path [format "%s|%s|%s" $nios_system_nios2_processor_oci_path $nios_system_nios2_processor_wrapper $nios_system_nios2_processor_jtag_sysclk] +set nios_system_nios2_processor_jtag_sr [format "%s|*sr" $nios_system_nios2_processor_jtag_tck_path] + +#************************************************************** +# Set False Paths +#************************************************************** + +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_break_path|break_readreg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|*resetlatch] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[33]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_ready] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[0]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_oci_debug_path|monitor_error] -to [get_keepers *$nios_system_nios2_processor_jtag_sr[34]] +set_false_path -from [get_keepers *$nios_system_nios2_processor_ocimem_path|*MonDReg*] -to [get_keepers *$nios_system_nios2_processor_jtag_sr*] +set_false_path -from *$nios_system_nios2_processor_jtag_sr* -to *$nios_system_nios2_processor_jtag_sysclk_path|*jdo* +set_false_path -from sld_hub:*|irf_reg* -to *$nios_system_nios2_processor_jtag_sysclk_path|ir* +set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$nios_system_nios2_processor_oci_debug_path|monitor_go diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor.v b/nios_system/synthesis/submodules/nios_system_nios2_processor.v index e1640d4..7e8e063 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor.v +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor.v @@ -1,5672 +1,5672 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_a_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_register_bank_b_module ( - // inputs: - clock, - data, - rdaddress, - wraddress, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input clock; - input [ 31: 0] data; - input [ 4: 0] rdaddress; - input [ 4: 0] wraddress; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (wraddress), - .address_b (rdaddress), - .clock0 (clock), - .data_a (data), - .q_b (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.address_reg_b = "CLOCK0", - the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 32, - the_altsyncram.numwords_b = 32, - the_altsyncram.operation_mode = "DUAL_PORT", - the_altsyncram.outdata_reg_b = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.rdcontrol_reg_b = "CLOCK0", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_b = 32, - the_altsyncram.widthad_a = 5, - the_altsyncram.widthad_b = 5; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_debug ( - // inputs: - clk, - dbrk_break, - debugreq, - hbreak_enabled, - jdo, - jrst_n, - ocireg_ers, - ocireg_mrs, - reset, - st_ready_test_idle, - take_action_ocimem_a, - take_action_ocireg, - xbrk_break, - - // outputs: - debugack, - monitor_error, - monitor_go, - monitor_ready, - oci_hbreak_req, - resetlatch, - resetrequest - ) -; - - output debugack; - output monitor_error; - output monitor_go; - output monitor_ready; - output oci_hbreak_req; - output resetlatch; - output resetrequest; - input clk; - input dbrk_break; - input debugreq; - input hbreak_enabled; - input [ 37: 0] jdo; - input jrst_n; - input ocireg_ers; - input ocireg_mrs; - input reset; - input st_ready_test_idle; - input take_action_ocimem_a; - input take_action_ocireg; - input xbrk_break; - - reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire debugack; - reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire oci_hbreak_req; - wire reset_sync; - reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire unxcomplemented_resetxx0; - assign unxcomplemented_resetxx0 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer - ( - .clk (clk), - .din (reset), - .dout (reset_sync), - .reset_n (unxcomplemented_resetxx0) - ); - - defparam the_altera_std_synchronizer.depth = 2; - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - break_on_reset <= 1'b0; - resetrequest <= 1'b0; - jtag_break <= 1'b0; - end - else if (take_action_ocimem_a) - begin - resetrequest <= jdo[22]; - jtag_break <= jdo[21] ? 1 - : jdo[20] ? 0 - : jtag_break; - - break_on_reset <= jdo[19] ? 1 - : jdo[18] ? 0 - : break_on_reset; - - resetlatch <= jdo[24] ? 0 : resetlatch; - end - else if (reset_sync) - begin - jtag_break <= break_on_reset; - resetlatch <= 1; - end - else if (debugreq & ~debugack & break_on_reset) - jtag_break <= 1'b1; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - monitor_ready <= 1'b0; - monitor_error <= 1'b0; - monitor_go <= 1'b0; - end - else - begin - if (take_action_ocimem_a && jdo[25]) - monitor_ready <= 1'b0; - else if (take_action_ocireg && ocireg_mrs) - monitor_ready <= 1'b1; - if (take_action_ocimem_a && jdo[25]) - monitor_error <= 1'b0; - else if (take_action_ocireg && ocireg_ers) - monitor_error <= 1'b1; - if (take_action_ocimem_a && jdo[23]) - monitor_go <= 1'b1; - else if (st_ready_test_idle) - monitor_go <= 1'b0; - end - end - - - assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; - assign debugack = ~hbreak_enabled; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_ociram_sp_ram_module ( - // inputs: - address, - byteenable, - clock, - data, - wren, - - // outputs: - q - ) -; - - parameter lpm_file = "UNUSED"; - - - output [ 31: 0] q; - input [ 7: 0] address; - input [ 3: 0] byteenable; - input clock; - input [ 31: 0] data; - input wren; - - wire [ 31: 0] q; - wire [ 31: 0] ram_q; - assign q = ram_q; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clock), - .data_a (data), - .q_a (ram_q), - .wren_a (wren) - ); - - defparam the_altsyncram.init_file = lpm_file, - the_altsyncram.maximum_depth = 0, - the_altsyncram.numwords_a = 256, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 8; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_ocimem ( - // inputs: - address, - byteenable, - clk, - debugaccess, - jdo, - jrst_n, - read, - take_action_ocimem_a, - take_action_ocimem_b, - take_no_action_ocimem_a, - write, - writedata, - - // outputs: - MonDReg, - ociram_readdata, - waitrequest - ) -; - - output [ 31: 0] MonDReg; - output [ 31: 0] ociram_readdata; - output waitrequest; - input [ 8: 0] address; - input [ 3: 0] byteenable; - input clk; - input debugaccess; - input [ 37: 0] jdo; - input jrst_n; - input read; - input take_action_ocimem_a; - input take_action_ocimem_b; - input take_no_action_ocimem_a; - input write; - input [ 31: 0] writedata; - - reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 8: 0] MonARegAddrInc; - wire MonARegAddrIncAccessingRAM; - reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire avalon_ram_wr; - wire [ 31: 0] cfgrom_readdata; - reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 7: 0] ociram_addr; - wire [ 3: 0] ociram_byteenable; - wire [ 31: 0] ociram_readdata; - wire [ 31: 0] ociram_wr_data; - wire ociram_wr_en; - reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - jtag_rd <= 1'b0; - jtag_rd_d1 <= 1'b0; - jtag_ram_wr <= 1'b0; - jtag_ram_rd <= 1'b0; - jtag_ram_rd_d1 <= 1'b0; - jtag_ram_access <= 1'b0; - MonAReg <= 0; - MonDReg <= 0; - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else - begin - if (take_no_action_ocimem_a) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - jtag_rd <= 1'b1; - jtag_ram_rd <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else if (take_action_ocimem_a) - begin - MonAReg[10 : 2] <= { jdo[17], - jdo[33 : 26] }; - - jtag_rd <= 1'b1; - jtag_ram_rd <= ~jdo[17]; - jtag_ram_access <= ~jdo[17]; - end - else if (take_action_ocimem_b) - begin - MonAReg[10 : 2] <= MonARegAddrInc; - MonDReg <= jdo[34 : 3]; - jtag_ram_wr <= MonARegAddrIncAccessingRAM; - jtag_ram_access <= MonARegAddrIncAccessingRAM; - end - else - begin - jtag_rd <= 0; - jtag_ram_wr <= 0; - jtag_ram_rd <= 0; - jtag_ram_access <= 0; - if (jtag_rd_d1) - MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; - end - jtag_rd_d1 <= jtag_rd; - jtag_ram_rd_d1 <= jtag_ram_rd; - if (~waitrequest) - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - else if (write) - waitrequest <= ~address[8] & jtag_ram_access; - else if (read) - begin - avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); - waitrequest <= ~avalon_ociram_readdata_ready; - end - else - begin - waitrequest <= 1'b1; - avalon_ociram_readdata_ready <= 1'b0; - end - end - end - - - assign MonARegAddrInc = MonAReg[10 : 2]+1; - assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; - assign avalon_ram_wr = write & ~address[8] & debugaccess; - assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; - assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; - assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; - assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; -//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram -nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram - ( - .address (ociram_addr), - .byteenable (ociram_byteenable), - .clock (clk), - .data (ociram_wr_data), - .q (ociram_readdata), - .wren (ociram_wr_en) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; -`else -defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; -//synthesis read_comments_as_HDL off - assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : - (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : - (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : - (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : - (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : - (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : - 32'h00000000; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_avalon_reg ( - // inputs: - address, - clk, - debugaccess, - monitor_error, - monitor_go, - monitor_ready, - reset_n, - write, - writedata, - - // outputs: - oci_ienable, - oci_reg_readdata, - oci_single_step_mode, - ocireg_ers, - ocireg_mrs, - take_action_ocireg - ) -; - - output [ 31: 0] oci_ienable; - output [ 31: 0] oci_reg_readdata; - output oci_single_step_mode; - output ocireg_ers; - output ocireg_mrs; - output take_action_ocireg; - input [ 8: 0] address; - input clk; - input debugaccess; - input monitor_error; - input monitor_go; - input monitor_ready; - input reset_n; - input write; - input [ 31: 0] writedata; - - reg [ 31: 0] oci_ienable; - wire oci_reg_00_addressed; - wire oci_reg_01_addressed; - wire [ 31: 0] oci_reg_readdata; - reg oci_single_step_mode; - wire ocireg_ers; - wire ocireg_mrs; - wire ocireg_sstep; - wire take_action_oci_intr_mask_reg; - wire take_action_ocireg; - wire write_strobe; - assign oci_reg_00_addressed = address == 9'h100; - assign oci_reg_01_addressed = address == 9'h101; - assign write_strobe = write & debugaccess; - assign take_action_ocireg = write_strobe & oci_reg_00_addressed; - assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; - assign ocireg_ers = writedata[1]; - assign ocireg_mrs = writedata[0]; - assign ocireg_sstep = writedata[3]; - assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, - monitor_ready, monitor_error} : - oci_reg_01_addressed ? oci_ienable : - 32'b0; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_single_step_mode <= 1'b0; - else if (take_action_ocireg) - oci_single_step_mode <= ocireg_sstep; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - oci_ienable <= 32'b00000000000000000000000000100000; - else if (take_action_oci_intr_mask_reg) - oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_break ( - // inputs: - clk, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - jdo, - jrst_n, - reset_n, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - xbrk_goto0, - xbrk_goto1, - - // outputs: - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - trigbrktype, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3 - ) -; - - output [ 31: 0] break_readreg; - output dbrk_hit0_latch; - output dbrk_hit1_latch; - output dbrk_hit2_latch; - output dbrk_hit3_latch; - output trigbrktype; - output trigger_state_0; - output trigger_state_1; - output [ 7: 0] xbrk_ctrl0; - output [ 7: 0] xbrk_ctrl1; - output [ 7: 0] xbrk_ctrl2; - output [ 7: 0] xbrk_ctrl3; - input clk; - input dbrk_break; - input dbrk_goto0; - input dbrk_goto1; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_break_a; - input take_action_break_b; - input take_action_break_c; - input take_no_action_break_a; - input take_no_action_break_b; - input take_no_action_break_c; - input xbrk_goto0; - input xbrk_goto1; - - wire [ 3: 0] break_a_wpr; - wire [ 1: 0] break_a_wpr_high_bits; - wire [ 1: 0] break_a_wpr_low_bits; - wire [ 1: 0] break_b_rr; - wire [ 1: 0] break_c_rr; - reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - wire dbrk0_high_value; - wire dbrk0_low_value; - wire dbrk1_high_value; - wire dbrk1_low_value; - wire dbrk2_high_value; - wire dbrk2_low_value; - wire dbrk3_high_value; - wire dbrk3_low_value; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire take_action_any_break; - reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg trigger_state; - wire trigger_state_0; - wire trigger_state_1; - wire [ 31: 0] xbrk0_value; - wire [ 31: 0] xbrk1_value; - wire [ 31: 0] xbrk2_value; - wire [ 31: 0] xbrk3_value; - reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - assign break_a_wpr = jdo[35 : 32]; - assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; - assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; - assign break_b_rr = jdo[33 : 32]; - assign break_c_rr = jdo[33 : 32]; - assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - xbrk_ctrl0 <= 0; - xbrk_ctrl1 <= 0; - xbrk_ctrl2 <= 0; - xbrk_ctrl3 <= 0; - trigbrktype <= 0; - end - else - begin - if (take_action_any_break) - trigbrktype <= 0; - else if (dbrk_break) - trigbrktype <= 1; - if (take_action_break_b) - begin - if ((break_b_rr == 2'b00) && (0 >= 1)) - begin - xbrk_ctrl0[0] <= jdo[27]; - xbrk_ctrl0[1] <= jdo[28]; - xbrk_ctrl0[2] <= jdo[29]; - xbrk_ctrl0[3] <= jdo[30]; - xbrk_ctrl0[4] <= jdo[21]; - xbrk_ctrl0[5] <= jdo[20]; - xbrk_ctrl0[6] <= jdo[19]; - xbrk_ctrl0[7] <= jdo[18]; - end - if ((break_b_rr == 2'b01) && (0 >= 2)) - begin - xbrk_ctrl1[0] <= jdo[27]; - xbrk_ctrl1[1] <= jdo[28]; - xbrk_ctrl1[2] <= jdo[29]; - xbrk_ctrl1[3] <= jdo[30]; - xbrk_ctrl1[4] <= jdo[21]; - xbrk_ctrl1[5] <= jdo[20]; - xbrk_ctrl1[6] <= jdo[19]; - xbrk_ctrl1[7] <= jdo[18]; - end - if ((break_b_rr == 2'b10) && (0 >= 3)) - begin - xbrk_ctrl2[0] <= jdo[27]; - xbrk_ctrl2[1] <= jdo[28]; - xbrk_ctrl2[2] <= jdo[29]; - xbrk_ctrl2[3] <= jdo[30]; - xbrk_ctrl2[4] <= jdo[21]; - xbrk_ctrl2[5] <= jdo[20]; - xbrk_ctrl2[6] <= jdo[19]; - xbrk_ctrl2[7] <= jdo[18]; - end - if ((break_b_rr == 2'b11) && (0 >= 4)) - begin - xbrk_ctrl3[0] <= jdo[27]; - xbrk_ctrl3[1] <= jdo[28]; - xbrk_ctrl3[2] <= jdo[29]; - xbrk_ctrl3[3] <= jdo[30]; - xbrk_ctrl3[4] <= jdo[21]; - xbrk_ctrl3[5] <= jdo[20]; - xbrk_ctrl3[6] <= jdo[19]; - xbrk_ctrl3[7] <= jdo[18]; - end - end - end - end - - - assign dbrk_hit0_latch = 1'b0; - assign dbrk0_low_value = 0; - assign dbrk0_high_value = 0; - assign dbrk_hit1_latch = 1'b0; - assign dbrk1_low_value = 0; - assign dbrk1_high_value = 0; - assign dbrk_hit2_latch = 1'b0; - assign dbrk2_low_value = 0; - assign dbrk2_high_value = 0; - assign dbrk_hit3_latch = 1'b0; - assign dbrk3_low_value = 0; - assign dbrk3_high_value = 0; - assign xbrk0_value = 32'b0; - assign xbrk1_value = 32'b0; - assign xbrk2_value = 32'b0; - assign xbrk3_value = 32'b0; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - break_readreg <= 32'b0; - else if (take_action_any_break) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_a) - case (break_a_wpr_high_bits) - - 2'd0: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= xbrk0_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= xbrk1_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= xbrk2_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= xbrk3_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd0 - - 2'd1: begin - break_readreg <= 32'b0; - end // 2'd1 - - 2'd2: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_low_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_low_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_low_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_low_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd2 - - 2'd3: begin - case (break_a_wpr_low_bits) // synthesis full_case - - 2'd0: begin - break_readreg <= dbrk0_high_value; - end // 2'd0 - - 2'd1: begin - break_readreg <= dbrk1_high_value; - end // 2'd1 - - 2'd2: begin - break_readreg <= dbrk2_high_value; - end // 2'd2 - - 2'd3: begin - break_readreg <= dbrk3_high_value; - end // 2'd3 - - endcase // break_a_wpr_low_bits - end // 2'd3 - - endcase // break_a_wpr_high_bits - else if (take_no_action_break_b) - break_readreg <= jdo[31 : 0]; - else if (take_no_action_break_c) - break_readreg <= jdo[31 : 0]; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trigger_state <= 0; - else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) - trigger_state <= 0; - else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) - trigger_state <= -1; - end - - - assign trigger_state_0 = ~trigger_state; - assign trigger_state_1 = trigger_state; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_xbrk ( - // inputs: - D_valid, - E_valid, - F_pc, - clk, - reset_n, - trigger_state_0, - trigger_state_1, - xbrk_ctrl0, - xbrk_ctrl1, - xbrk_ctrl2, - xbrk_ctrl3, - - // outputs: - xbrk_break, - xbrk_goto0, - xbrk_goto1, - xbrk_traceoff, - xbrk_traceon, - xbrk_trigout - ) -; - - output xbrk_break; - output xbrk_goto0; - output xbrk_goto1; - output xbrk_traceoff; - output xbrk_traceon; - output xbrk_trigout; - input D_valid; - input E_valid; - input [ 16: 0] F_pc; - input clk; - input reset_n; - input trigger_state_0; - input trigger_state_1; - input [ 7: 0] xbrk_ctrl0; - input [ 7: 0] xbrk_ctrl1; - input [ 7: 0] xbrk_ctrl2; - input [ 7: 0] xbrk_ctrl3; - - wire D_cpu_addr_en; - wire E_cpu_addr_en; - reg E_xbrk_goto0; - reg E_xbrk_goto1; - reg E_xbrk_traceoff; - reg E_xbrk_traceon; - reg E_xbrk_trigout; - wire [ 18: 0] cpu_i_address; - wire xbrk0_armed; - wire xbrk0_break_hit; - wire xbrk0_goto0_hit; - wire xbrk0_goto1_hit; - wire xbrk0_toff_hit; - wire xbrk0_ton_hit; - wire xbrk0_tout_hit; - wire xbrk1_armed; - wire xbrk1_break_hit; - wire xbrk1_goto0_hit; - wire xbrk1_goto1_hit; - wire xbrk1_toff_hit; - wire xbrk1_ton_hit; - wire xbrk1_tout_hit; - wire xbrk2_armed; - wire xbrk2_break_hit; - wire xbrk2_goto0_hit; - wire xbrk2_goto1_hit; - wire xbrk2_toff_hit; - wire xbrk2_ton_hit; - wire xbrk2_tout_hit; - wire xbrk3_armed; - wire xbrk3_break_hit; - wire xbrk3_goto0_hit; - wire xbrk3_goto1_hit; - wire xbrk3_toff_hit; - wire xbrk3_ton_hit; - wire xbrk3_tout_hit; - reg xbrk_break; - wire xbrk_break_hit; - wire xbrk_goto0; - wire xbrk_goto0_hit; - wire xbrk_goto1; - wire xbrk_goto1_hit; - wire xbrk_toff_hit; - wire xbrk_ton_hit; - wire xbrk_tout_hit; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - assign cpu_i_address = {F_pc, 2'b00}; - assign D_cpu_addr_en = D_valid; - assign E_cpu_addr_en = E_valid; - assign xbrk0_break_hit = 0; - assign xbrk0_ton_hit = 0; - assign xbrk0_toff_hit = 0; - assign xbrk0_tout_hit = 0; - assign xbrk0_goto0_hit = 0; - assign xbrk0_goto1_hit = 0; - assign xbrk1_break_hit = 0; - assign xbrk1_ton_hit = 0; - assign xbrk1_toff_hit = 0; - assign xbrk1_tout_hit = 0; - assign xbrk1_goto0_hit = 0; - assign xbrk1_goto1_hit = 0; - assign xbrk2_break_hit = 0; - assign xbrk2_ton_hit = 0; - assign xbrk2_toff_hit = 0; - assign xbrk2_tout_hit = 0; - assign xbrk2_goto0_hit = 0; - assign xbrk2_goto1_hit = 0; - assign xbrk3_break_hit = 0; - assign xbrk3_ton_hit = 0; - assign xbrk3_toff_hit = 0; - assign xbrk3_tout_hit = 0; - assign xbrk3_goto0_hit = 0; - assign xbrk3_goto1_hit = 0; - assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); - assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); - assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); - assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); - assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); - assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - xbrk_break <= 0; - else if (E_cpu_addr_en) - xbrk_break <= xbrk_break_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceon <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceon <= xbrk_ton_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_traceoff <= 0; - else if (E_cpu_addr_en) - E_xbrk_traceoff <= xbrk_toff_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_trigout <= 0; - else if (E_cpu_addr_en) - E_xbrk_trigout <= xbrk_tout_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto0 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto0 <= xbrk_goto0_hit; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_xbrk_goto1 <= 0; - else if (E_cpu_addr_en) - E_xbrk_goto1 <= xbrk_goto1_hit; - end - - - assign xbrk_traceon = 1'b0; - assign xbrk_traceoff = 1'b0; - assign xbrk_trigout = 1'b0; - assign xbrk_goto0 = 1'b0; - assign xbrk_goto1 = 1'b0; - assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || - (xbrk_ctrl0[5] & trigger_state_1); - - assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || - (xbrk_ctrl1[5] & trigger_state_1); - - assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || - (xbrk_ctrl2[5] & trigger_state_1); - - assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || - (xbrk_ctrl3[5] & trigger_state_1); - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dbrk ( - // inputs: - E_st_data, - av_ld_data_aligned_filtered, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugack, - reset_n, - - // outputs: - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - dbrk_break, - dbrk_goto0, - dbrk_goto1, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dbrk_trigout - ) -; - - output [ 18: 0] cpu_d_address; - output cpu_d_read; - output [ 31: 0] cpu_d_readdata; - output cpu_d_wait; - output cpu_d_write; - output [ 31: 0] cpu_d_writedata; - output dbrk_break; - output dbrk_goto0; - output dbrk_goto1; - output dbrk_traceme; - output dbrk_traceoff; - output dbrk_traceon; - output dbrk_trigout; - input [ 31: 0] E_st_data; - input [ 31: 0] av_ld_data_aligned_filtered; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugack; - input reset_n; - - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk0_armed; - wire dbrk0_break_pulse; - wire dbrk0_goto0; - wire dbrk0_goto1; - wire dbrk0_traceme; - wire dbrk0_traceoff; - wire dbrk0_traceon; - wire dbrk0_trigout; - wire dbrk1_armed; - wire dbrk1_break_pulse; - wire dbrk1_goto0; - wire dbrk1_goto1; - wire dbrk1_traceme; - wire dbrk1_traceoff; - wire dbrk1_traceon; - wire dbrk1_trigout; - wire dbrk2_armed; - wire dbrk2_break_pulse; - wire dbrk2_goto0; - wire dbrk2_goto1; - wire dbrk2_traceme; - wire dbrk2_traceoff; - wire dbrk2_traceon; - wire dbrk2_trigout; - wire dbrk3_armed; - wire dbrk3_break_pulse; - wire dbrk3_goto0; - wire dbrk3_goto1; - wire dbrk3_traceme; - wire dbrk3_traceoff; - wire dbrk3_traceon; - wire dbrk3_trigout; - reg dbrk_break; - reg dbrk_break_pulse; - wire [ 31: 0] dbrk_data; - reg dbrk_goto0; - reg dbrk_goto1; - reg dbrk_traceme; - reg dbrk_traceoff; - reg dbrk_traceon; - reg dbrk_trigout; - assign cpu_d_address = d_address; - assign cpu_d_readdata = av_ld_data_aligned_filtered; - assign cpu_d_read = d_read; - assign cpu_d_writedata = E_st_data; - assign cpu_d_write = d_write; - assign cpu_d_wait = d_waitrequest; - assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - dbrk_break <= 0; - else - dbrk_break <= dbrk_break ? ~debugack - : dbrk_break_pulse; - - end - - - assign dbrk0_armed = 1'b0; - assign dbrk0_trigout = 1'b0; - assign dbrk0_break_pulse = 1'b0; - assign dbrk0_traceoff = 1'b0; - assign dbrk0_traceon = 1'b0; - assign dbrk0_traceme = 1'b0; - assign dbrk0_goto0 = 1'b0; - assign dbrk0_goto1 = 1'b0; - assign dbrk1_armed = 1'b0; - assign dbrk1_trigout = 1'b0; - assign dbrk1_break_pulse = 1'b0; - assign dbrk1_traceoff = 1'b0; - assign dbrk1_traceon = 1'b0; - assign dbrk1_traceme = 1'b0; - assign dbrk1_goto0 = 1'b0; - assign dbrk1_goto1 = 1'b0; - assign dbrk2_armed = 1'b0; - assign dbrk2_trigout = 1'b0; - assign dbrk2_break_pulse = 1'b0; - assign dbrk2_traceoff = 1'b0; - assign dbrk2_traceon = 1'b0; - assign dbrk2_traceme = 1'b0; - assign dbrk2_goto0 = 1'b0; - assign dbrk2_goto1 = 1'b0; - assign dbrk3_armed = 1'b0; - assign dbrk3_trigout = 1'b0; - assign dbrk3_break_pulse = 1'b0; - assign dbrk3_traceoff = 1'b0; - assign dbrk3_traceon = 1'b0; - assign dbrk3_traceme = 1'b0; - assign dbrk3_goto0 = 1'b0; - assign dbrk3_goto1 = 1'b0; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - dbrk_trigout <= 0; - dbrk_break_pulse <= 0; - dbrk_traceoff <= 0; - dbrk_traceon <= 0; - dbrk_traceme <= 0; - dbrk_goto0 <= 0; - dbrk_goto1 <= 0; - end - else - begin - dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; - dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; - dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; - dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; - dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; - dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; - dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_itrace ( - // inputs: - clk, - dbrk_traceoff, - dbrk_traceon, - jdo, - jrst_n, - take_action_tracectrl, - trc_enb, - xbrk_traceoff, - xbrk_traceon, - xbrk_wrap_traceoff, - - // outputs: - dct_buffer, - dct_count, - itm, - trc_ctrl, - trc_on - ) -; - - output [ 29: 0] dct_buffer; - output [ 3: 0] dct_count; - output [ 35: 0] itm; - output [ 15: 0] trc_ctrl; - output trc_on; - input clk; - input dbrk_traceoff; - input dbrk_traceon; - input [ 15: 0] jdo; - input jrst_n; - input take_action_tracectrl; - input trc_enb; - input xbrk_traceoff; - input xbrk_traceon; - input xbrk_wrap_traceoff; - - wire curr_pid; - reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] dct_code; - reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire dct_is_taken; - wire [ 31: 0] excaddr; - wire instr_retired; - wire is_advanced_exception; - wire is_cond_dct; - wire is_dct; - wire is_exception_no_break; - wire is_fast_tlb_miss_exception; - wire is_idct; - reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire not_in_debug_mode; - reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_dct_outcome_in_sync; - wire record_itrace; - wire [ 31: 0] retired_pcb; - reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 1: 0] sync_code; - wire [ 6: 0] sync_interval; - wire sync_pending; - reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 6: 0] sync_timer_next; - reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire [ 15: 0] trc_ctrl; - reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire trc_on; - assign is_cond_dct = 1'b0; - assign is_dct = 1'b0; - assign dct_is_taken = 1'b0; - assign is_idct = 1'b0; - assign retired_pcb = 32'b0; - assign not_in_debug_mode = 1'b0; - assign instr_retired = 1'b0; - assign is_advanced_exception = 1'b0; - assign is_exception_no_break = 1'b0; - assign is_fast_tlb_miss_exception = 1'b0; - assign curr_pid = 1'b0; - assign excaddr = 32'b0; - assign sync_code = trc_ctrl[3 : 2]; - assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; - assign sync_pending = sync_timer == 0; - assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; - assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); - assign record_itrace = trc_on & trc_ctrl[4]; - assign dct_code = {is_cond_dct, dct_is_taken}; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - trc_clear <= 0; - else - trc_clear <= ~trc_enb & - take_action_tracectrl & jdo[4]; - - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else if (trc_clear || (!0 && !0)) - begin - itm <= 0; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= 0; - pending_frametype <= 4'b0000; - pending_exctype <= 1'b0; - pending_excaddr <= 0; - prev_pid <= 0; - prev_pid_valid <= 0; - snapped_pid <= 0; - snapped_curr_pid <= 0; - snapped_prev_pid <= 0; - pending_curr_pid <= 0; - pending_prev_pid <= 0; - end - else - begin - if (!prev_pid_valid) - begin - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - prev_pid <= curr_pid; - prev_pid_valid <= 1; - end - if (instr_retired | is_advanced_exception) - begin - if (~record_itrace) - pending_frametype <= 4'b1010; - else if (is_exception_no_break) - begin - pending_frametype <= 4'b0010; - pending_excaddr <= excaddr; - if (is_fast_tlb_miss_exception) - pending_exctype <= 1'b1; - else - pending_exctype <= 1'b0; - end - else if (is_idct) - pending_frametype <= 4'b1001; - else if (record_dct_outcome_in_sync) - pending_frametype <= 4'b1000; - else if (!is_dct & snapped_pid) - begin - pending_frametype <= 4'b0011; - pending_curr_pid <= snapped_curr_pid; - pending_prev_pid <= snapped_prev_pid; - snapped_pid <= 0; - end - else - pending_frametype <= 4'b0000; - if ((dct_count != 0) & - (~record_itrace | - is_exception_no_break | - is_idct | - record_dct_outcome_in_sync | - (!is_dct & snapped_pid))) - begin - itm <= {4'b0001, dct_buffer, 2'b00}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - begin - if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) - begin - dct_buffer <= {dct_code, dct_buffer[29 : 2]}; - dct_count <= dct_count + 1; - end - if (record_itrace & (pending_frametype == 4'b0010)) - itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; - else if (record_itrace & ( - (pending_frametype == 4'b1000) | - (pending_frametype == 4'b1010) | - (pending_frametype == 4'b1001))) - begin - itm <= {pending_frametype, retired_pcb}; - sync_timer <= sync_interval; - if (0 & - ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & - !snapped_pid & prev_pid_valid) - begin - snapped_pid <= 1; - snapped_curr_pid <= curr_pid; - snapped_prev_pid <= prev_pid; - end - end - else if (record_itrace & - 0 & (pending_frametype == 4'b0011)) - itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; - else if (record_itrace & is_dct) - begin - if (dct_count == 4'd15) - begin - itm <= {4'b0001, dct_code, dct_buffer}; - dct_buffer <= 0; - dct_count <= 0; - sync_timer <= sync_timer_next; - end - else - itm <= 4'b0000; - end - else - itm <= {4'b0000, 32'b0}; - end - end - else - itm <= {4'b0000, 32'b0}; - end - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_ctrl_reg[0] <= 1'b0; - trc_ctrl_reg[1] <= 1'b0; - trc_ctrl_reg[3 : 2] <= 2'b00; - trc_ctrl_reg[4] <= 1'b0; - trc_ctrl_reg[7 : 5] <= 3'b000; - trc_ctrl_reg[8] <= 0; - trc_ctrl_reg[9] <= 1'b0; - trc_ctrl_reg[10] <= 1'b0; - end - else if (take_action_tracectrl) - begin - trc_ctrl_reg[0] <= jdo[5]; - trc_ctrl_reg[1] <= jdo[6]; - trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; - trc_ctrl_reg[4] <= jdo[9]; - trc_ctrl_reg[9] <= jdo[14]; - trc_ctrl_reg[10] <= jdo[2]; - if (0) - trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; - if (0 & 0) - trc_ctrl_reg[8] <= jdo[13]; - end - else if (xbrk_wrap_traceoff) - begin - trc_ctrl_reg[1] <= 0; - trc_ctrl_reg[0] <= 0; - end - else if (dbrk_traceoff | xbrk_traceoff) - trc_ctrl_reg[1] <= 0; - else if (trc_ctrl_reg[0] & - (dbrk_traceon | xbrk_traceon)) - trc_ctrl_reg[1] <= 1; - end - - - assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; - assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_td_mode ( - // inputs: - ctrl, - - // outputs: - td_mode - ) -; - - output [ 3: 0] td_mode; - input [ 8: 0] ctrl; - - wire [ 2: 0] ctrl_bits_for_mux; - reg [ 3: 0] td_mode; - assign ctrl_bits_for_mux = ctrl[7 : 5]; - always @(ctrl_bits_for_mux) - begin - case (ctrl_bits_for_mux) - - 3'b000: begin - td_mode = 4'b0000; - end // 3'b000 - - 3'b001: begin - td_mode = 4'b1000; - end // 3'b001 - - 3'b010: begin - td_mode = 4'b0100; - end // 3'b010 - - 3'b011: begin - td_mode = 4'b1100; - end // 3'b011 - - 3'b100: begin - td_mode = 4'b0010; - end // 3'b100 - - 3'b101: begin - td_mode = 4'b1010; - end // 3'b101 - - 3'b110: begin - td_mode = 4'b0101; - end // 3'b110 - - 3'b111: begin - td_mode = 4'b1111; - end // 3'b111 - - endcase // ctrl_bits_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_dtrace ( - // inputs: - clk, - cpu_d_address, - cpu_d_read, - cpu_d_readdata, - cpu_d_wait, - cpu_d_write, - cpu_d_writedata, - jrst_n, - trc_ctrl, - - // outputs: - atm, - dtm - ) -; - - output [ 35: 0] atm; - output [ 35: 0] dtm; - input clk; - input [ 18: 0] cpu_d_address; - input cpu_d_read; - input [ 31: 0] cpu_d_readdata; - input cpu_d_wait; - input cpu_d_write; - input [ 31: 0] cpu_d_writedata; - input jrst_n; - input [ 15: 0] trc_ctrl; - - reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 31: 0] cpu_d_address_0_padded; - wire [ 31: 0] cpu_d_readdata_0_padded; - wire [ 31: 0] cpu_d_writedata_0_padded; - reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire record_load_addr; - wire record_load_data; - wire record_store_addr; - wire record_store_data; - wire [ 3: 0] td_mode_trc_ctrl; - assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; - assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; - assign cpu_d_address_0_padded = cpu_d_address | 32'b0; - //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance - nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode - ( - .ctrl (trc_ctrl[8 : 0]), - .td_mode (td_mode_trc_ctrl) - ); - - assign {record_load_addr, record_store_addr, - record_load_data, record_store_data} = td_mode_trc_ctrl; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - atm <= 0; - dtm <= 0; - end - else if (0) - begin - if (cpu_d_write & ~cpu_d_wait & record_store_addr) - atm <= {4'b0101, cpu_d_address_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_addr) - atm <= {4'b0100, cpu_d_address_0_padded}; - else - atm <= {4'b0000, cpu_d_address_0_padded}; - if (cpu_d_write & ~cpu_d_wait & record_store_data) - dtm <= {4'b0111, cpu_d_writedata_0_padded}; - else if (cpu_d_read & ~cpu_d_wait & record_load_data) - dtm <= {4'b0110, cpu_d_readdata_0_padded}; - else - dtm <= {4'b0000, cpu_d_readdata_0_padded}; - end - else - begin - atm <= 0; - dtm <= 0; - end - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_compute_tm_count ( - // inputs: - atm_valid, - dtm_valid, - itm_valid, - - // outputs: - compute_tm_count - ) -; - - output [ 1: 0] compute_tm_count; - input atm_valid; - input dtm_valid; - input itm_valid; - - reg [ 1: 0] compute_tm_count; - wire [ 2: 0] switch_for_mux; - assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; - always @(switch_for_mux) - begin - case (switch_for_mux) - - 3'b000: begin - compute_tm_count = 0; - end // 3'b000 - - 3'b001: begin - compute_tm_count = 1; - end // 3'b001 - - 3'b010: begin - compute_tm_count = 1; - end // 3'b010 - - 3'b011: begin - compute_tm_count = 2; - end // 3'b011 - - 3'b100: begin - compute_tm_count = 1; - end // 3'b100 - - 3'b101: begin - compute_tm_count = 2; - end // 3'b101 - - 3'b110: begin - compute_tm_count = 2; - end // 3'b110 - - 3'b111: begin - compute_tm_count = 3; - end // 3'b111 - - endcase // switch_for_mux - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifowp_inc ( - // inputs: - free2, - free3, - tm_count, - - // outputs: - fifowp_inc - ) -; - - output [ 3: 0] fifowp_inc; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 3: 0] fifowp_inc; - always @(free2 or free3 or tm_count) - begin - if (free3 & (tm_count == 3)) - fifowp_inc = 3; - else if (free2 & (tm_count >= 2)) - fifowp_inc = 2; - else if (tm_count >= 1) - fifowp_inc = 1; - else - fifowp_inc = 0; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifocount_inc ( - // inputs: - empty, - free2, - free3, - tm_count, - - // outputs: - fifocount_inc - ) -; - - output [ 4: 0] fifocount_inc; - input empty; - input free2; - input free3; - input [ 1: 0] tm_count; - - reg [ 4: 0] fifocount_inc; - always @(empty or free2 or free3 or tm_count) - begin - if (empty) - fifocount_inc = tm_count[1 : 0]; - else if (free3 & (tm_count == 3)) - fifocount_inc = 2; - else if (free2 & (tm_count >= 2)) - fifocount_inc = 1; - else if (tm_count >= 1) - fifocount_inc = 0; - else - fifocount_inc = {5{1'b1}}; - end - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_fifo ( - // inputs: - atm, - clk, - dbrk_traceme, - dbrk_traceoff, - dbrk_traceon, - dct_buffer, - dct_count, - dtm, - itm, - jrst_n, - reset_n, - test_ending, - test_has_ended, - trc_on, - - // outputs: - tw - ) -; - - output [ 35: 0] tw; - input [ 35: 0] atm; - input clk; - input dbrk_traceme; - input dbrk_traceoff; - input dbrk_traceon; - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input [ 35: 0] dtm; - input [ 35: 0] itm; - input jrst_n; - input reset_n; - input test_ending; - input test_has_ended; - input trc_on; - - wire atm_valid; - wire [ 1: 0] compute_tm_count_tm_count; - wire dtm_valid; - wire empty; - reg [ 35: 0] fifo_0; - wire fifo_0_enable; - wire [ 35: 0] fifo_0_mux; - reg [ 35: 0] fifo_1; - reg [ 35: 0] fifo_10; - wire fifo_10_enable; - wire [ 35: 0] fifo_10_mux; - reg [ 35: 0] fifo_11; - wire fifo_11_enable; - wire [ 35: 0] fifo_11_mux; - reg [ 35: 0] fifo_12; - wire fifo_12_enable; - wire [ 35: 0] fifo_12_mux; - reg [ 35: 0] fifo_13; - wire fifo_13_enable; - wire [ 35: 0] fifo_13_mux; - reg [ 35: 0] fifo_14; - wire fifo_14_enable; - wire [ 35: 0] fifo_14_mux; - reg [ 35: 0] fifo_15; - wire fifo_15_enable; - wire [ 35: 0] fifo_15_mux; - wire fifo_1_enable; - wire [ 35: 0] fifo_1_mux; - reg [ 35: 0] fifo_2; - wire fifo_2_enable; - wire [ 35: 0] fifo_2_mux; - reg [ 35: 0] fifo_3; - wire fifo_3_enable; - wire [ 35: 0] fifo_3_mux; - reg [ 35: 0] fifo_4; - wire fifo_4_enable; - wire [ 35: 0] fifo_4_mux; - reg [ 35: 0] fifo_5; - wire fifo_5_enable; - wire [ 35: 0] fifo_5_mux; - reg [ 35: 0] fifo_6; - wire fifo_6_enable; - wire [ 35: 0] fifo_6_mux; - reg [ 35: 0] fifo_7; - wire fifo_7_enable; - wire [ 35: 0] fifo_7_mux; - reg [ 35: 0] fifo_8; - wire fifo_8_enable; - wire [ 35: 0] fifo_8_mux; - reg [ 35: 0] fifo_9; - wire fifo_9_enable; - wire [ 35: 0] fifo_9_mux; - wire [ 35: 0] fifo_read_mux; - reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 4: 0] fifocount_inc_fifocount; - wire [ 35: 0] fifohead; - reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 3: 0] fifowp1; - wire [ 3: 0] fifowp2; - wire [ 3: 0] fifowp_inc_fifowp; - wire free2; - wire free3; - wire itm_valid; - reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 35: 0] ovr_pending_atm; - wire [ 35: 0] ovr_pending_dtm; - wire [ 1: 0] tm_count; - wire tm_count_ge1; - wire tm_count_ge2; - wire tm_count_ge3; - wire trc_this; - wire [ 35: 0] tw; - assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; - assign itm_valid = |itm[35 : 32]; - assign atm_valid = |atm[35 : 32] & trc_this; - assign dtm_valid = |dtm[35 : 32] & trc_this; - assign free2 = ~fifocount[4]; - assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; - assign empty = ~|fifocount; - assign fifowp1 = fifowp + 1; - assign fifowp2 = fifowp + 2; - //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance - nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count - ( - .atm_valid (atm_valid), - .compute_tm_count (compute_tm_count_tm_count), - .dtm_valid (dtm_valid), - .itm_valid (itm_valid) - ); - - assign tm_count = compute_tm_count_tm_count; - //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp - ( - .fifowp_inc (fifowp_inc_fifowp), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance - nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount - ( - .empty (empty), - .fifocount_inc (fifocount_inc_fifocount), - .free2 (free2), - .free3 (free3), - .tm_count (tm_count) - ); - - //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance - nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench - ( - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .test_ending (test_ending), - .test_has_ended (test_has_ended) - ); - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - fiforp <= 0; - fifowp <= 0; - fifocount <= 0; - ovf_pending <= 1; - end - else - begin - fifowp <= fifowp + fifowp_inc_fifowp; - fifocount <= fifocount + fifocount_inc_fifocount; - if (~empty) - fiforp <= fiforp + 1; - if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) - ovf_pending <= 1; - else if (atm_valid | dtm_valid) - ovf_pending <= 0; - end - end - - - assign fifohead = fifo_read_mux; - assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; - assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_0 <= 0; - else if (fifo_0_enable) - fifo_0 <= fifo_0_mux; - end - - - assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : - (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_1 <= 0; - else if (fifo_1_enable) - fifo_1 <= fifo_1_mux; - end - - - assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : - (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_2 <= 0; - else if (fifo_2_enable) - fifo_2 <= fifo_2_mux; - end - - - assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : - (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_3 <= 0; - else if (fifo_3_enable) - fifo_3 <= fifo_3_mux; - end - - - assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : - (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_4 <= 0; - else if (fifo_4_enable) - fifo_4 <= fifo_4_mux; - end - - - assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : - (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_5 <= 0; - else if (fifo_5_enable) - fifo_5 <= fifo_5_mux; - end - - - assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : - (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_6 <= 0; - else if (fifo_6_enable) - fifo_6 <= fifo_6_mux; - end - - - assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : - (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_7 <= 0; - else if (fifo_7_enable) - fifo_7 <= fifo_7_mux; - end - - - assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : - (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_8 <= 0; - else if (fifo_8_enable) - fifo_8 <= fifo_8_mux; - end - - - assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : - (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_9 <= 0; - else if (fifo_9_enable) - fifo_9 <= fifo_9_mux; - end - - - assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : - (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_10 <= 0; - else if (fifo_10_enable) - fifo_10 <= fifo_10_mux; - end - - - assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : - (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_11 <= 0; - else if (fifo_11_enable) - fifo_11 <= fifo_11_mux; - end - - - assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : - (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_12 <= 0; - else if (fifo_12_enable) - fifo_12 <= fifo_12_mux; - end - - - assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : - (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_13 <= 0; - else if (fifo_13_enable) - fifo_13 <= fifo_13_mux; - end - - - assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : - (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_14 <= 0; - else if (fifo_14_enable) - fifo_14 <= fifo_14_mux; - end - - - assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : - (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - fifo_15 <= 0; - else if (fifo_15_enable) - fifo_15 <= fifo_15_mux; - end - - - assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : - (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : - (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : - (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : - (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : - ovr_pending_dtm; - - assign tm_count_ge1 = |tm_count; - assign tm_count_ge2 = tm_count[1]; - assign tm_count_ge3 = &tm_count; - assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; - assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; - assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : - (fiforp == 4'd1)? fifo_1 : - (fiforp == 4'd2)? fifo_2 : - (fiforp == 4'd3)? fifo_3 : - (fiforp == 4'd4)? fifo_4 : - (fiforp == 4'd5)? fifo_5 : - (fiforp == 4'd6)? fifo_6 : - (fiforp == 4'd7)? fifo_7 : - (fiforp == 4'd8)? fifo_8 : - (fiforp == 4'd9)? fifo_9 : - (fiforp == 4'd10)? fifo_10 : - (fiforp == 4'd11)? fifo_11 : - (fiforp == 4'd12)? fifo_12 : - (fiforp == 4'd13)? fifo_13 : - (fiforp == 4'd14)? fifo_14 : - fifo_15; - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_pib ( - // inputs: - clk, - clkx2, - jrst_n, - tw, - - // outputs: - tr_clk, - tr_data - ) -; - - output tr_clk; - output [ 17: 0] tr_data; - input clk; - input clkx2; - input jrst_n; - input [ 35: 0] tw; - - wire phase; - wire tr_clk; - reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - wire [ 17: 0] tr_data; - reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; - assign phase = x1^x2; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - x1 <= 0; - else - x1 <= ~x1; - end - - - always @(posedge clkx2 or negedge jrst_n) - begin - if (jrst_n == 0) - begin - x2 <= 0; - tr_clk_reg <= 0; - tr_data_reg <= 0; - end - else - begin - x2 <= x1; - tr_clk_reg <= ~phase; - tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; - end - end - - - assign tr_clk = 0 ? tr_clk_reg : 0; - assign tr_data = 0 ? tr_data_reg : 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci_im ( - // inputs: - clk, - jdo, - jrst_n, - reset_n, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_tracemem_a, - trc_ctrl, - tw, - - // outputs: - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_enb, - trc_im_addr, - trc_wrap, - xbrk_wrap_traceoff - ) -; - - output tracemem_on; - output [ 35: 0] tracemem_trcdata; - output tracemem_tw; - output trc_enb; - output [ 6: 0] trc_im_addr; - output trc_wrap; - output xbrk_wrap_traceoff; - input clk; - input [ 37: 0] jdo; - input jrst_n; - input reset_n; - input take_action_tracectrl; - input take_action_tracemem_a; - input take_action_tracemem_b; - input take_no_action_tracemem_a; - input [ 15: 0] trc_ctrl; - input [ 35: 0] tw; - - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire trc_enb; - reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire [ 35: 0] trc_im_data; - reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; - wire trc_on_chip; - reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire tw_valid; - wire xbrk_wrap_traceoff; - assign trc_im_data = tw; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (!0) - begin - trc_im_addr <= 0; - trc_wrap <= 0; - end - else if (take_action_tracectrl && - (jdo[4] | jdo[3])) - begin - if (jdo[4]) - trc_im_addr <= 0; - if (jdo[3]) - trc_wrap <= 0; - end - else if (trc_enb & trc_on_chip & tw_valid) - begin - trc_im_addr <= trc_im_addr+1; - if (&trc_im_addr) - trc_wrap <= 1; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - trc_jtag_addr <= 0; - else if (take_action_tracemem_a || - take_no_action_tracemem_a || - take_action_tracemem_b) - trc_jtag_addr <= take_action_tracemem_a ? - jdo[35 : 19] : - trc_jtag_addr + 1; - - end - - - assign trc_enb = trc_ctrl[0]; - assign trc_on_chip = ~trc_ctrl[8]; - assign tw_valid = |trc_im_data[35 : 32]; - assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; - assign tracemem_tw = trc_wrap; - assign tracemem_on = trc_enb; - assign tracemem_trcdata = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_performance_monitors -; - - - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_nios2_oci ( - // inputs: - D_valid, - E_st_data, - E_valid, - F_pc, - address_nxt, - av_ld_data_aligned_filtered, - byteenable_nxt, - clk, - d_address, - d_read, - d_waitrequest, - d_write, - debugaccess_nxt, - hbreak_enabled, - read_nxt, - reset, - reset_n, - test_ending, - test_has_ended, - write_nxt, - writedata_nxt, - - // outputs: - jtag_debug_module_debugaccess_to_roms, - oci_hbreak_req, - oci_ienable, - oci_single_step_mode, - readdata, - resetrequest, - waitrequest - ) -; - - output jtag_debug_module_debugaccess_to_roms; - output oci_hbreak_req; - output [ 31: 0] oci_ienable; - output oci_single_step_mode; - output [ 31: 0] readdata; - output resetrequest; - output waitrequest; - input D_valid; - input [ 31: 0] E_st_data; - input E_valid; - input [ 16: 0] F_pc; - input [ 8: 0] address_nxt; - input [ 31: 0] av_ld_data_aligned_filtered; - input [ 3: 0] byteenable_nxt; - input clk; - input [ 18: 0] d_address; - input d_read; - input d_waitrequest; - input d_write; - input debugaccess_nxt; - input hbreak_enabled; - input read_nxt; - input reset; - input reset_n; - input test_ending; - input test_has_ended; - input write_nxt; - input [ 31: 0] writedata_nxt; - - wire [ 31: 0] MonDReg; - reg [ 8: 0] address; - wire [ 35: 0] atm; - wire [ 31: 0] break_readreg; - reg [ 3: 0] byteenable; - wire clkx2; - wire [ 18: 0] cpu_d_address; - wire cpu_d_read; - wire [ 31: 0] cpu_d_readdata; - wire cpu_d_wait; - wire cpu_d_write; - wire [ 31: 0] cpu_d_writedata; - wire dbrk_break; - wire dbrk_goto0; - wire dbrk_goto1; - wire dbrk_hit0_latch; - wire dbrk_hit1_latch; - wire dbrk_hit2_latch; - wire dbrk_hit3_latch; - wire dbrk_traceme; - wire dbrk_traceoff; - wire dbrk_traceon; - wire dbrk_trigout; - wire [ 29: 0] dct_buffer; - wire [ 3: 0] dct_count; - reg debugaccess; - wire debugack; - wire debugreq; - wire [ 35: 0] dtm; - wire dummy_sink; - wire [ 35: 0] itm; - wire [ 37: 0] jdo; - wire jrst_n; - wire jtag_debug_module_debugaccess_to_roms; - wire monitor_error; - wire monitor_go; - wire monitor_ready; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire [ 31: 0] oci_reg_readdata; - wire oci_single_step_mode; - wire [ 31: 0] ociram_readdata; - wire ocireg_ers; - wire ocireg_mrs; - reg read; - reg [ 31: 0] readdata; - wire resetlatch; - wire resetrequest; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_ocireg; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire tr_clk; - wire [ 17: 0] tr_data; - wire tracemem_on; - wire [ 35: 0] tracemem_trcdata; - wire tracemem_tw; - wire [ 15: 0] trc_ctrl; - wire trc_enb; - wire [ 6: 0] trc_im_addr; - wire trc_on; - wire trc_wrap; - wire trigbrktype; - wire trigger_state_0; - wire trigger_state_1; - wire trigout; - wire [ 35: 0] tw; - wire waitrequest; - reg write; - reg [ 31: 0] writedata; - wire xbrk_break; - wire [ 7: 0] xbrk_ctrl0; - wire [ 7: 0] xbrk_ctrl1; - wire [ 7: 0] xbrk_ctrl2; - wire [ 7: 0] xbrk_ctrl3; - wire xbrk_goto0; - wire xbrk_goto1; - wire xbrk_traceoff; - wire xbrk_traceon; - wire xbrk_trigout; - wire xbrk_wrap_traceoff; - nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug - ( - .clk (clk), - .dbrk_break (dbrk_break), - .debugack (debugack), - .debugreq (debugreq), - .hbreak_enabled (hbreak_enabled), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_hbreak_req (oci_hbreak_req), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset (reset), - .resetlatch (resetlatch), - .resetrequest (resetrequest), - .st_ready_test_idle (st_ready_test_idle), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocireg (take_action_ocireg), - .xbrk_break (xbrk_break) - ); - - nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem - ( - .MonDReg (MonDReg), - .address (address), - .byteenable (byteenable), - .clk (clk), - .debugaccess (debugaccess), - .jdo (jdo), - .jrst_n (jrst_n), - .ociram_readdata (ociram_readdata), - .read (read), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .waitrequest (waitrequest), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg - ( - .address (address), - .clk (clk), - .debugaccess (debugaccess), - .monitor_error (monitor_error), - .monitor_go (monitor_go), - .monitor_ready (monitor_ready), - .oci_ienable (oci_ienable), - .oci_reg_readdata (oci_reg_readdata), - .oci_single_step_mode (oci_single_step_mode), - .ocireg_ers (ocireg_ers), - .ocireg_mrs (ocireg_mrs), - .reset_n (reset_n), - .take_action_ocireg (take_action_ocireg), - .write (write), - .writedata (writedata) - ); - - nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break - ( - .break_readreg (break_readreg), - .clk (clk), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .trigbrktype (trigbrktype), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1) - ); - - nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk - ( - .D_valid (D_valid), - .E_valid (E_valid), - .F_pc (F_pc), - .clk (clk), - .reset_n (reset_n), - .trigger_state_0 (trigger_state_0), - .trigger_state_1 (trigger_state_1), - .xbrk_break (xbrk_break), - .xbrk_ctrl0 (xbrk_ctrl0), - .xbrk_ctrl1 (xbrk_ctrl1), - .xbrk_ctrl2 (xbrk_ctrl2), - .xbrk_ctrl3 (xbrk_ctrl3), - .xbrk_goto0 (xbrk_goto0), - .xbrk_goto1 (xbrk_goto1), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_trigout (xbrk_trigout) - ); - - nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk - ( - .E_st_data (E_st_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .dbrk_break (dbrk_break), - .dbrk_goto0 (dbrk_goto0), - .dbrk_goto1 (dbrk_goto1), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dbrk_trigout (dbrk_trigout), - .debugack (debugack), - .reset_n (reset_n) - ); - - nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace - ( - .clk (clk), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .itm (itm), - .jdo (jdo), - .jrst_n (jrst_n), - .take_action_tracectrl (take_action_tracectrl), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_on (trc_on), - .xbrk_traceoff (xbrk_traceoff), - .xbrk_traceon (xbrk_traceon), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace - ( - .atm (atm), - .clk (clk), - .cpu_d_address (cpu_d_address), - .cpu_d_read (cpu_d_read), - .cpu_d_readdata (cpu_d_readdata), - .cpu_d_wait (cpu_d_wait), - .cpu_d_write (cpu_d_write), - .cpu_d_writedata (cpu_d_writedata), - .dtm (dtm), - .jrst_n (jrst_n), - .trc_ctrl (trc_ctrl) - ); - - nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo - ( - .atm (atm), - .clk (clk), - .dbrk_traceme (dbrk_traceme), - .dbrk_traceoff (dbrk_traceoff), - .dbrk_traceon (dbrk_traceon), - .dct_buffer (dct_buffer), - .dct_count (dct_count), - .dtm (dtm), - .itm (itm), - .jrst_n (jrst_n), - .reset_n (reset_n), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .trc_on (trc_on), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib - ( - .clk (clk), - .clkx2 (clkx2), - .jrst_n (jrst_n), - .tr_clk (tr_clk), - .tr_data (tr_data), - .tw (tw) - ); - - nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im - ( - .clk (clk), - .jdo (jdo), - .jrst_n (jrst_n), - .reset_n (reset_n), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_ctrl (trc_ctrl), - .trc_enb (trc_enb), - .trc_im_addr (trc_im_addr), - .trc_wrap (trc_wrap), - .tw (tw), - .xbrk_wrap_traceoff (xbrk_wrap_traceoff) - ); - - assign trigout = dbrk_trigout | xbrk_trigout; - assign jtag_debug_module_debugaccess_to_roms = debugack; - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - address <= 0; - else - address <= address_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - byteenable <= 0; - else - byteenable <= byteenable_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - writedata <= 0; - else - writedata <= writedata_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - debugaccess <= 0; - else - debugaccess <= debugaccess_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - read <= 0; - else - read <= read ? waitrequest : read_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - write <= 0; - else - write <= write ? waitrequest : write_nxt; - end - - - always @(posedge clk or negedge jrst_n) - begin - if (jrst_n == 0) - readdata <= 0; - else - readdata <= address[8] ? oci_reg_readdata : ociram_readdata; - end - - - nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .clk (clk), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .jdo (jdo), - .jrst_n (jrst_n), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .st_ready_test_idle (st_ready_test_idle), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1) - ); - - //dummy sink, which is an e_mux - assign dummy_sink = tr_clk | - tr_data | - trigout | - debugack; - - assign debugreq = 0; - assign clkx2 = 0; - -endmodule - - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor ( - // inputs: - clk, - d_irq, - d_readdata, - d_waitrequest, - i_readdata, - i_waitrequest, - jtag_debug_module_address, - jtag_debug_module_byteenable, - jtag_debug_module_debugaccess, - jtag_debug_module_read, - jtag_debug_module_write, - jtag_debug_module_writedata, - reset_n, - - // outputs: - d_address, - d_byteenable, - d_read, - d_write, - d_writedata, - i_address, - i_read, - jtag_debug_module_debugaccess_to_roms, - jtag_debug_module_readdata, - jtag_debug_module_resetrequest, - jtag_debug_module_waitrequest, - no_ci_readra - ) -; - - output [ 18: 0] d_address; - output [ 3: 0] d_byteenable; - output d_read; - output d_write; - output [ 31: 0] d_writedata; - output [ 18: 0] i_address; - output i_read; - output jtag_debug_module_debugaccess_to_roms; - output [ 31: 0] jtag_debug_module_readdata; - output jtag_debug_module_resetrequest; - output jtag_debug_module_waitrequest; - output no_ci_readra; - input clk; - input [ 31: 0] d_irq; - input [ 31: 0] d_readdata; - input d_waitrequest; - input [ 31: 0] i_readdata; - input i_waitrequest; - input [ 8: 0] jtag_debug_module_address; - input [ 3: 0] jtag_debug_module_byteenable; - input jtag_debug_module_debugaccess; - input jtag_debug_module_read; - input jtag_debug_module_write; - input [ 31: 0] jtag_debug_module_writedata; - input reset_n; - - wire [ 1: 0] D_compare_op; - wire D_ctrl_alu_force_xor; - wire D_ctrl_alu_signed_comparison; - wire D_ctrl_alu_subtract; - wire D_ctrl_b_is_dst; - wire D_ctrl_br; - wire D_ctrl_br_cmp; - wire D_ctrl_br_uncond; - wire D_ctrl_break; - wire D_ctrl_crst; - wire D_ctrl_custom; - wire D_ctrl_custom_multi; - wire D_ctrl_exception; - wire D_ctrl_force_src2_zero; - wire D_ctrl_hi_imm16; - wire D_ctrl_ignore_dst; - wire D_ctrl_implicit_dst_eretaddr; - wire D_ctrl_implicit_dst_retaddr; - wire D_ctrl_jmp_direct; - wire D_ctrl_jmp_indirect; - wire D_ctrl_ld; - wire D_ctrl_ld_io; - wire D_ctrl_ld_non_io; - wire D_ctrl_ld_signed; - wire D_ctrl_logic; - wire D_ctrl_rdctl_inst; - wire D_ctrl_retaddr; - wire D_ctrl_rot_right; - wire D_ctrl_shift_logical; - wire D_ctrl_shift_right_arith; - wire D_ctrl_shift_rot; - wire D_ctrl_shift_rot_right; - wire D_ctrl_src2_choose_imm; - wire D_ctrl_st; - wire D_ctrl_uncond_cti_non_br; - wire D_ctrl_unsigned_lo_imm16; - wire D_ctrl_wrctl_inst; - wire [ 4: 0] D_dst_regnum; - wire [ 55: 0] D_inst; - reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 4: 0] D_iw_a; - wire [ 4: 0] D_iw_b; - wire [ 4: 0] D_iw_c; - wire [ 2: 0] D_iw_control_regnum; - wire [ 7: 0] D_iw_custom_n; - wire D_iw_custom_readra; - wire D_iw_custom_readrb; - wire D_iw_custom_writerc; - wire [ 15: 0] D_iw_imm16; - wire [ 25: 0] D_iw_imm26; - wire [ 4: 0] D_iw_imm5; - wire [ 1: 0] D_iw_memsz; - wire [ 5: 0] D_iw_op; - wire [ 5: 0] D_iw_opx; - wire [ 4: 0] D_iw_shift_imm5; - wire [ 4: 0] D_iw_trap_break_imm5; - wire [ 16: 0] D_jmp_direct_target_waddr; - wire [ 1: 0] D_logic_op; - wire [ 1: 0] D_logic_op_raw; - wire D_mem16; - wire D_mem32; - wire D_mem8; - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - reg D_valid; - wire [ 55: 0] D_vinst; - wire D_wr_dst_reg; - wire [ 31: 0] E_alu_result; - reg E_alu_sub; - wire [ 32: 0] E_arith_result; - wire [ 31: 0] E_arith_src1; - wire [ 31: 0] E_arith_src2; - wire E_ci_multi_stall; - wire [ 31: 0] E_ci_result; - wire E_cmp_result; - wire [ 31: 0] E_control_rd_data; - wire E_eq; - reg E_invert_arith_src_msb; - wire E_ld_stall; - wire [ 31: 0] E_logic_result; - wire E_logic_result_is_0; - wire E_lt; - wire [ 18: 0] E_mem_baddr; - wire [ 3: 0] E_mem_byte_en; - reg E_new_inst; - reg [ 4: 0] E_shift_rot_cnt; - wire [ 4: 0] E_shift_rot_cnt_nxt; - wire E_shift_rot_done; - wire E_shift_rot_fill_bit; - reg [ 31: 0] E_shift_rot_result; - wire [ 31: 0] E_shift_rot_result_nxt; - wire E_shift_rot_stall; - reg [ 31: 0] E_src1; - reg [ 31: 0] E_src2; - wire [ 31: 0] E_st_data; - wire E_st_stall; - wire E_stall; - reg E_valid; - wire [ 55: 0] E_vinst; - wire E_wrctl_bstatus; - wire E_wrctl_estatus; - wire E_wrctl_ienable; - wire E_wrctl_status; - wire [ 31: 0] F_av_iw; - wire [ 4: 0] F_av_iw_a; - wire [ 4: 0] F_av_iw_b; - wire [ 4: 0] F_av_iw_c; - wire [ 2: 0] F_av_iw_control_regnum; - wire [ 7: 0] F_av_iw_custom_n; - wire F_av_iw_custom_readra; - wire F_av_iw_custom_readrb; - wire F_av_iw_custom_writerc; - wire [ 15: 0] F_av_iw_imm16; - wire [ 25: 0] F_av_iw_imm26; - wire [ 4: 0] F_av_iw_imm5; - wire [ 1: 0] F_av_iw_memsz; - wire [ 5: 0] F_av_iw_op; - wire [ 5: 0] F_av_iw_opx; - wire [ 4: 0] F_av_iw_shift_imm5; - wire [ 4: 0] F_av_iw_trap_break_imm5; - wire F_av_mem16; - wire F_av_mem32; - wire F_av_mem8; - wire [ 55: 0] F_inst; - wire [ 31: 0] F_iw; - wire [ 4: 0] F_iw_a; - wire [ 4: 0] F_iw_b; - wire [ 4: 0] F_iw_c; - wire [ 2: 0] F_iw_control_regnum; - wire [ 7: 0] F_iw_custom_n; - wire F_iw_custom_readra; - wire F_iw_custom_readrb; - wire F_iw_custom_writerc; - wire [ 15: 0] F_iw_imm16; - wire [ 25: 0] F_iw_imm26; - wire [ 4: 0] F_iw_imm5; - wire [ 1: 0] F_iw_memsz; - wire [ 5: 0] F_iw_op; - wire [ 5: 0] F_iw_opx; - wire [ 4: 0] F_iw_shift_imm5; - wire [ 4: 0] F_iw_trap_break_imm5; - wire F_mem16; - wire F_mem32; - wire F_mem8; - wire F_op_add; - wire F_op_addi; - wire F_op_and; - wire F_op_andhi; - wire F_op_andi; - wire F_op_beq; - wire F_op_bge; - wire F_op_bgeu; - wire F_op_blt; - wire F_op_bltu; - wire F_op_bne; - wire F_op_br; - wire F_op_break; - wire F_op_bret; - wire F_op_call; - wire F_op_callr; - wire F_op_cmpeq; - wire F_op_cmpeqi; - wire F_op_cmpge; - wire F_op_cmpgei; - wire F_op_cmpgeu; - wire F_op_cmpgeui; - wire F_op_cmplt; - wire F_op_cmplti; - wire F_op_cmpltu; - wire F_op_cmpltui; - wire F_op_cmpne; - wire F_op_cmpnei; - wire F_op_crst; - wire F_op_custom; - wire F_op_div; - wire F_op_divu; - wire F_op_eret; - wire F_op_flushd; - wire F_op_flushda; - wire F_op_flushi; - wire F_op_flushp; - wire F_op_hbreak; - wire F_op_initd; - wire F_op_initda; - wire F_op_initi; - wire F_op_intr; - wire F_op_jmp; - wire F_op_jmpi; - wire F_op_ldb; - wire F_op_ldbio; - wire F_op_ldbu; - wire F_op_ldbuio; - wire F_op_ldh; - wire F_op_ldhio; - wire F_op_ldhu; - wire F_op_ldhuio; - wire F_op_ldl; - wire F_op_ldw; - wire F_op_ldwio; - wire F_op_mul; - wire F_op_muli; - wire F_op_mulxss; - wire F_op_mulxsu; - wire F_op_mulxuu; - wire F_op_nextpc; - wire F_op_nor; - wire F_op_opx; - wire F_op_or; - wire F_op_orhi; - wire F_op_ori; - wire F_op_rdctl; - wire F_op_rdprs; - wire F_op_ret; - wire F_op_rol; - wire F_op_roli; - wire F_op_ror; - wire F_op_rsv02; - wire F_op_rsv09; - wire F_op_rsv10; - wire F_op_rsv17; - wire F_op_rsv18; - wire F_op_rsv25; - wire F_op_rsv26; - wire F_op_rsv33; - wire F_op_rsv34; - wire F_op_rsv41; - wire F_op_rsv42; - wire F_op_rsv49; - wire F_op_rsv57; - wire F_op_rsv61; - wire F_op_rsv62; - wire F_op_rsv63; - wire F_op_rsvx00; - wire F_op_rsvx10; - wire F_op_rsvx15; - wire F_op_rsvx17; - wire F_op_rsvx21; - wire F_op_rsvx25; - wire F_op_rsvx33; - wire F_op_rsvx34; - wire F_op_rsvx35; - wire F_op_rsvx42; - wire F_op_rsvx43; - wire F_op_rsvx44; - wire F_op_rsvx47; - wire F_op_rsvx50; - wire F_op_rsvx51; - wire F_op_rsvx55; - wire F_op_rsvx56; - wire F_op_rsvx60; - wire F_op_rsvx63; - wire F_op_sll; - wire F_op_slli; - wire F_op_sra; - wire F_op_srai; - wire F_op_srl; - wire F_op_srli; - wire F_op_stb; - wire F_op_stbio; - wire F_op_stc; - wire F_op_sth; - wire F_op_sthio; - wire F_op_stw; - wire F_op_stwio; - wire F_op_sub; - wire F_op_sync; - wire F_op_trap; - wire F_op_wrctl; - wire F_op_wrprs; - wire F_op_xor; - wire F_op_xorhi; - wire F_op_xori; - reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire F_pc_en; - wire [ 16: 0] F_pc_no_crst_nxt; - wire [ 16: 0] F_pc_nxt; - wire [ 16: 0] F_pc_plus_one; - wire [ 1: 0] F_pc_sel_nxt; - wire [ 18: 0] F_pcb; - wire [ 18: 0] F_pcb_nxt; - wire [ 18: 0] F_pcb_plus_four; - wire F_valid; - wire [ 55: 0] F_vinst; - reg [ 1: 0] R_compare_op; - reg R_ctrl_alu_force_xor; - wire R_ctrl_alu_force_xor_nxt; - reg R_ctrl_alu_signed_comparison; - wire R_ctrl_alu_signed_comparison_nxt; - reg R_ctrl_alu_subtract; - wire R_ctrl_alu_subtract_nxt; - reg R_ctrl_b_is_dst; - wire R_ctrl_b_is_dst_nxt; - reg R_ctrl_br; - reg R_ctrl_br_cmp; - wire R_ctrl_br_cmp_nxt; - wire R_ctrl_br_nxt; - reg R_ctrl_br_uncond; - wire R_ctrl_br_uncond_nxt; - reg R_ctrl_break; - wire R_ctrl_break_nxt; - reg R_ctrl_crst; - wire R_ctrl_crst_nxt; - reg R_ctrl_custom; - reg R_ctrl_custom_multi; - wire R_ctrl_custom_multi_nxt; - wire R_ctrl_custom_nxt; - reg R_ctrl_exception; - wire R_ctrl_exception_nxt; - reg R_ctrl_force_src2_zero; - wire R_ctrl_force_src2_zero_nxt; - reg R_ctrl_hi_imm16; - wire R_ctrl_hi_imm16_nxt; - reg R_ctrl_ignore_dst; - wire R_ctrl_ignore_dst_nxt; - reg R_ctrl_implicit_dst_eretaddr; - wire R_ctrl_implicit_dst_eretaddr_nxt; - reg R_ctrl_implicit_dst_retaddr; - wire R_ctrl_implicit_dst_retaddr_nxt; - reg R_ctrl_jmp_direct; - wire R_ctrl_jmp_direct_nxt; - reg R_ctrl_jmp_indirect; - wire R_ctrl_jmp_indirect_nxt; - reg R_ctrl_ld; - reg R_ctrl_ld_io; - wire R_ctrl_ld_io_nxt; - reg R_ctrl_ld_non_io; - wire R_ctrl_ld_non_io_nxt; - wire R_ctrl_ld_nxt; - reg R_ctrl_ld_signed; - wire R_ctrl_ld_signed_nxt; - reg R_ctrl_logic; - wire R_ctrl_logic_nxt; - reg R_ctrl_rdctl_inst; - wire R_ctrl_rdctl_inst_nxt; - reg R_ctrl_retaddr; - wire R_ctrl_retaddr_nxt; - reg R_ctrl_rot_right; - wire R_ctrl_rot_right_nxt; - reg R_ctrl_shift_logical; - wire R_ctrl_shift_logical_nxt; - reg R_ctrl_shift_right_arith; - wire R_ctrl_shift_right_arith_nxt; - reg R_ctrl_shift_rot; - wire R_ctrl_shift_rot_nxt; - reg R_ctrl_shift_rot_right; - wire R_ctrl_shift_rot_right_nxt; - reg R_ctrl_src2_choose_imm; - wire R_ctrl_src2_choose_imm_nxt; - reg R_ctrl_st; - wire R_ctrl_st_nxt; - reg R_ctrl_uncond_cti_non_br; - wire R_ctrl_uncond_cti_non_br_nxt; - reg R_ctrl_unsigned_lo_imm16; - wire R_ctrl_unsigned_lo_imm16_nxt; - reg R_ctrl_wrctl_inst; - wire R_ctrl_wrctl_inst_nxt; - reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire R_en; - reg [ 1: 0] R_logic_op; - wire [ 31: 0] R_rf_a; - wire [ 31: 0] R_rf_b; - wire [ 31: 0] R_src1; - wire [ 31: 0] R_src2; - wire [ 15: 0] R_src2_hi; - wire [ 15: 0] R_src2_lo; - reg R_src2_use_imm; - wire [ 7: 0] R_stb_data; - wire [ 15: 0] R_sth_data; - reg R_valid; - wire [ 55: 0] R_vinst; - reg R_wr_dst_reg; - reg [ 31: 0] W_alu_result; - wire W_br_taken; - reg W_bstatus_reg; - wire W_bstatus_reg_inst_nxt; - wire W_bstatus_reg_nxt; - reg W_cmp_result; - reg [ 31: 0] W_control_rd_data; - reg W_estatus_reg; - wire W_estatus_reg_inst_nxt; - wire W_estatus_reg_nxt; - reg [ 31: 0] W_ienable_reg; - wire [ 31: 0] W_ienable_reg_nxt; - reg [ 31: 0] W_ipending_reg; - wire [ 31: 0] W_ipending_reg_nxt; - wire [ 18: 0] W_mem_baddr; - wire [ 31: 0] W_rf_wr_data; - wire W_rf_wren; - wire W_status_reg; - reg W_status_reg_pie; - wire W_status_reg_pie_inst_nxt; - wire W_status_reg_pie_nxt; - reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; - wire [ 55: 0] W_vinst; - wire [ 31: 0] W_wr_data; - wire [ 31: 0] W_wr_data_non_zero; - wire av_fill_bit; - reg [ 1: 0] av_ld_align_cycle; - wire [ 1: 0] av_ld_align_cycle_nxt; - wire av_ld_align_one_more_cycle; - reg av_ld_aligning_data; - wire av_ld_aligning_data_nxt; - reg [ 7: 0] av_ld_byte0_data; - wire [ 7: 0] av_ld_byte0_data_nxt; - reg [ 7: 0] av_ld_byte1_data; - wire av_ld_byte1_data_en; - wire [ 7: 0] av_ld_byte1_data_nxt; - reg [ 7: 0] av_ld_byte2_data; - wire [ 7: 0] av_ld_byte2_data_nxt; - reg [ 7: 0] av_ld_byte3_data; - wire [ 7: 0] av_ld_byte3_data_nxt; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire [ 31: 0] av_ld_data_aligned_unfiltered; - wire av_ld_done; - wire av_ld_extend; - wire av_ld_getting_data; - wire av_ld_rshift8; - reg av_ld_waiting_for_data; - wire av_ld_waiting_for_data_nxt; - wire av_sign_bit; - wire [ 18: 0] d_address; - reg [ 3: 0] d_byteenable; - reg d_read; - wire d_read_nxt; - wire d_write; - wire d_write_nxt; - reg [ 31: 0] d_writedata; - reg hbreak_enabled; - reg hbreak_pending; - wire hbreak_pending_nxt; - wire hbreak_req; - wire [ 18: 0] i_address; - reg i_read; - wire i_read_nxt; - wire [ 31: 0] iactive; - wire intr_req; - wire jtag_debug_module_clk; - wire jtag_debug_module_debugaccess_to_roms; - wire [ 31: 0] jtag_debug_module_readdata; - wire jtag_debug_module_reset; - wire jtag_debug_module_resetrequest; - wire jtag_debug_module_waitrequest; - wire no_ci_readra; - wire oci_hbreak_req; - wire [ 31: 0] oci_ienable; - wire oci_single_step_mode; - wire oci_tb_hbreak_req; - wire test_ending; - wire test_has_ended; - reg wait_for_one_post_bret_inst; - //the_nios_system_nios2_processor_test_bench, which is an e_instance - nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench - ( - .D_iw (D_iw), - .D_iw_op (D_iw_op), - .D_iw_opx (D_iw_opx), - .D_valid (D_valid), - .E_valid (E_valid), - .F_pcb (F_pcb), - .F_valid (F_valid), - .R_ctrl_ld (R_ctrl_ld), - .R_ctrl_ld_non_io (R_ctrl_ld_non_io), - .R_dst_regnum (R_dst_regnum), - .R_wr_dst_reg (R_wr_dst_reg), - .W_valid (W_valid), - .W_vinst (W_vinst), - .W_wr_data (W_wr_data), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), - .clk (clk), - .d_address (d_address), - .d_byteenable (d_byteenable), - .d_read (d_read), - .d_write (d_write), - .d_write_nxt (d_write_nxt), - .i_address (i_address), - .i_read (i_read), - .i_readdata (i_readdata), - .i_waitrequest (i_waitrequest), - .reset_n (reset_n), - .test_has_ended (test_has_ended) - ); - - assign F_av_iw_a = F_av_iw[31 : 27]; - assign F_av_iw_b = F_av_iw[26 : 22]; - assign F_av_iw_c = F_av_iw[21 : 17]; - assign F_av_iw_custom_n = F_av_iw[13 : 6]; - assign F_av_iw_custom_readra = F_av_iw[16]; - assign F_av_iw_custom_readrb = F_av_iw[15]; - assign F_av_iw_custom_writerc = F_av_iw[14]; - assign F_av_iw_opx = F_av_iw[16 : 11]; - assign F_av_iw_op = F_av_iw[5 : 0]; - assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm5 = F_av_iw[10 : 6]; - assign F_av_iw_imm16 = F_av_iw[21 : 6]; - assign F_av_iw_imm26 = F_av_iw[31 : 6]; - assign F_av_iw_memsz = F_av_iw[4 : 3]; - assign F_av_iw_control_regnum = F_av_iw[8 : 6]; - assign F_av_mem8 = F_av_iw_memsz == 2'b00; - assign F_av_mem16 = F_av_iw_memsz == 2'b01; - assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; - assign F_iw_a = F_iw[31 : 27]; - assign F_iw_b = F_iw[26 : 22]; - assign F_iw_c = F_iw[21 : 17]; - assign F_iw_custom_n = F_iw[13 : 6]; - assign F_iw_custom_readra = F_iw[16]; - assign F_iw_custom_readrb = F_iw[15]; - assign F_iw_custom_writerc = F_iw[14]; - assign F_iw_opx = F_iw[16 : 11]; - assign F_iw_op = F_iw[5 : 0]; - assign F_iw_shift_imm5 = F_iw[10 : 6]; - assign F_iw_trap_break_imm5 = F_iw[10 : 6]; - assign F_iw_imm5 = F_iw[10 : 6]; - assign F_iw_imm16 = F_iw[21 : 6]; - assign F_iw_imm26 = F_iw[31 : 6]; - assign F_iw_memsz = F_iw[4 : 3]; - assign F_iw_control_regnum = F_iw[8 : 6]; - assign F_mem8 = F_iw_memsz == 2'b00; - assign F_mem16 = F_iw_memsz == 2'b01; - assign F_mem32 = F_iw_memsz[1] == 1'b1; - assign D_iw_a = D_iw[31 : 27]; - assign D_iw_b = D_iw[26 : 22]; - assign D_iw_c = D_iw[21 : 17]; - assign D_iw_custom_n = D_iw[13 : 6]; - assign D_iw_custom_readra = D_iw[16]; - assign D_iw_custom_readrb = D_iw[15]; - assign D_iw_custom_writerc = D_iw[14]; - assign D_iw_opx = D_iw[16 : 11]; - assign D_iw_op = D_iw[5 : 0]; - assign D_iw_shift_imm5 = D_iw[10 : 6]; - assign D_iw_trap_break_imm5 = D_iw[10 : 6]; - assign D_iw_imm5 = D_iw[10 : 6]; - assign D_iw_imm16 = D_iw[21 : 6]; - assign D_iw_imm26 = D_iw[31 : 6]; - assign D_iw_memsz = D_iw[4 : 3]; - assign D_iw_control_regnum = D_iw[8 : 6]; - assign D_mem8 = D_iw_memsz == 2'b00; - assign D_mem16 = D_iw_memsz == 2'b01; - assign D_mem32 = D_iw_memsz[1] == 1'b1; - assign F_op_call = F_iw_op == 0; - assign F_op_jmpi = F_iw_op == 1; - assign F_op_ldbu = F_iw_op == 3; - assign F_op_addi = F_iw_op == 4; - assign F_op_stb = F_iw_op == 5; - assign F_op_br = F_iw_op == 6; - assign F_op_ldb = F_iw_op == 7; - assign F_op_cmpgei = F_iw_op == 8; - assign F_op_ldhu = F_iw_op == 11; - assign F_op_andi = F_iw_op == 12; - assign F_op_sth = F_iw_op == 13; - assign F_op_bge = F_iw_op == 14; - assign F_op_ldh = F_iw_op == 15; - assign F_op_cmplti = F_iw_op == 16; - assign F_op_initda = F_iw_op == 19; - assign F_op_ori = F_iw_op == 20; - assign F_op_stw = F_iw_op == 21; - assign F_op_blt = F_iw_op == 22; - assign F_op_ldw = F_iw_op == 23; - assign F_op_cmpnei = F_iw_op == 24; - assign F_op_flushda = F_iw_op == 27; - assign F_op_xori = F_iw_op == 28; - assign F_op_stc = F_iw_op == 29; - assign F_op_bne = F_iw_op == 30; - assign F_op_ldl = F_iw_op == 31; - assign F_op_cmpeqi = F_iw_op == 32; - assign F_op_ldbuio = F_iw_op == 35; - assign F_op_muli = F_iw_op == 36; - assign F_op_stbio = F_iw_op == 37; - assign F_op_beq = F_iw_op == 38; - assign F_op_ldbio = F_iw_op == 39; - assign F_op_cmpgeui = F_iw_op == 40; - assign F_op_ldhuio = F_iw_op == 43; - assign F_op_andhi = F_iw_op == 44; - assign F_op_sthio = F_iw_op == 45; - assign F_op_bgeu = F_iw_op == 46; - assign F_op_ldhio = F_iw_op == 47; - assign F_op_cmpltui = F_iw_op == 48; - assign F_op_initd = F_iw_op == 51; - assign F_op_orhi = F_iw_op == 52; - assign F_op_stwio = F_iw_op == 53; - assign F_op_bltu = F_iw_op == 54; - assign F_op_ldwio = F_iw_op == 55; - assign F_op_rdprs = F_iw_op == 56; - assign F_op_flushd = F_iw_op == 59; - assign F_op_xorhi = F_iw_op == 60; - assign F_op_rsv02 = F_iw_op == 2; - assign F_op_rsv09 = F_iw_op == 9; - assign F_op_rsv10 = F_iw_op == 10; - assign F_op_rsv17 = F_iw_op == 17; - assign F_op_rsv18 = F_iw_op == 18; - assign F_op_rsv25 = F_iw_op == 25; - assign F_op_rsv26 = F_iw_op == 26; - assign F_op_rsv33 = F_iw_op == 33; - assign F_op_rsv34 = F_iw_op == 34; - assign F_op_rsv41 = F_iw_op == 41; - assign F_op_rsv42 = F_iw_op == 42; - assign F_op_rsv49 = F_iw_op == 49; - assign F_op_rsv57 = F_iw_op == 57; - assign F_op_rsv61 = F_iw_op == 61; - assign F_op_rsv62 = F_iw_op == 62; - assign F_op_rsv63 = F_iw_op == 63; - assign F_op_eret = F_op_opx & (F_iw_opx == 1); - assign F_op_roli = F_op_opx & (F_iw_opx == 2); - assign F_op_rol = F_op_opx & (F_iw_opx == 3); - assign F_op_flushp = F_op_opx & (F_iw_opx == 4); - assign F_op_ret = F_op_opx & (F_iw_opx == 5); - assign F_op_nor = F_op_opx & (F_iw_opx == 6); - assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); - assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); - assign F_op_bret = F_op_opx & (F_iw_opx == 9); - assign F_op_ror = F_op_opx & (F_iw_opx == 11); - assign F_op_flushi = F_op_opx & (F_iw_opx == 12); - assign F_op_jmp = F_op_opx & (F_iw_opx == 13); - assign F_op_and = F_op_opx & (F_iw_opx == 14); - assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); - assign F_op_slli = F_op_opx & (F_iw_opx == 18); - assign F_op_sll = F_op_opx & (F_iw_opx == 19); - assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); - assign F_op_or = F_op_opx & (F_iw_opx == 22); - assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); - assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); - assign F_op_srli = F_op_opx & (F_iw_opx == 26); - assign F_op_srl = F_op_opx & (F_iw_opx == 27); - assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); - assign F_op_callr = F_op_opx & (F_iw_opx == 29); - assign F_op_xor = F_op_opx & (F_iw_opx == 30); - assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); - assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); - assign F_op_divu = F_op_opx & (F_iw_opx == 36); - assign F_op_div = F_op_opx & (F_iw_opx == 37); - assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); - assign F_op_mul = F_op_opx & (F_iw_opx == 39); - assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); - assign F_op_initi = F_op_opx & (F_iw_opx == 41); - assign F_op_trap = F_op_opx & (F_iw_opx == 45); - assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); - assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); - assign F_op_add = F_op_opx & (F_iw_opx == 49); - assign F_op_break = F_op_opx & (F_iw_opx == 52); - assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); - assign F_op_sync = F_op_opx & (F_iw_opx == 54); - assign F_op_sub = F_op_opx & (F_iw_opx == 57); - assign F_op_srai = F_op_opx & (F_iw_opx == 58); - assign F_op_sra = F_op_opx & (F_iw_opx == 59); - assign F_op_intr = F_op_opx & (F_iw_opx == 61); - assign F_op_crst = F_op_opx & (F_iw_opx == 62); - assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); - assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); - assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); - assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); - assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); - assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); - assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); - assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); - assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); - assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); - assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); - assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); - assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); - assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); - assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); - assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); - assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); - assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); - assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); - assign F_op_opx = F_iw_op == 58; - assign F_op_custom = F_iw_op == 50; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - assign R_en = 1'b1; - assign E_ci_result = 0; - //custom_instruction_master, which is an e_custom_instruction_master - assign no_ci_readra = 1'b0; - assign E_ci_multi_stall = 1'b0; - assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; - assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : - R_ctrl_break ? 2'b01 : - (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : - 2'b11; - - assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : - (F_pc_sel_nxt == 2'b01)? 66056 : - (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : - F_pc_plus_one; - - assign F_pc_nxt = F_pc_no_crst_nxt; - assign F_pcb_nxt = {F_pc_nxt, 2'b00}; - assign F_pc_en = W_valid; - assign F_pc_plus_one = F_pc + 1; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - F_pc <= 0; - else if (F_pc_en) - F_pc <= F_pc_nxt; - end - - - assign F_pcb = {F_pc, 2'b00}; - assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; - assign F_valid = i_read & ~i_waitrequest; - assign i_read_nxt = W_valid | (i_read & i_waitrequest); - assign i_address = {F_pc, 2'b00}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - i_read <= 1'b1; - else - i_read <= i_read_nxt; - end - - - assign oci_tb_hbreak_req = oci_hbreak_req; - assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); - assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled - : hbreak_req; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - wait_for_one_post_bret_inst <= 1'b0; - else - wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_pending <= 1'b0; - else - hbreak_pending <= hbreak_pending_nxt; - end - - - assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); - assign F_av_iw = i_readdata; - assign F_iw = hbreak_req ? 4040762 : - 1'b0 ? 127034 : - intr_req ? 3926074 : - F_av_iw; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_iw <= 0; - else if (F_valid) - D_iw <= F_iw; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - D_valid <= 0; - else - D_valid <= F_valid; - end - - - assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : - D_ctrl_implicit_dst_eretaddr ? 5'd29 : - D_ctrl_b_is_dst ? D_iw_b : - D_iw_c; - - assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; - assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; - assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : - D_iw_op[4 : 3]; - - assign D_jmp_direct_target_waddr = D_iw[31 : 6]; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_valid <= 0; - else - R_valid <= D_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_wr_dst_reg <= 0; - else - R_wr_dst_reg <= D_wr_dst_reg; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_dst_regnum <= 0; - else - R_dst_regnum <= D_dst_regnum; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_logic_op <= 0; - else - R_logic_op <= D_logic_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_compare_op <= 0; - else - R_compare_op <= D_compare_op; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_src2_use_imm <= 0; - else - R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); - end - - - assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; - assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; -//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_a), - .rdaddress (D_iw_a), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; -`else -defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; -//synthesis read_comments_as_HDL off -//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram -nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b - ( - .clock (clk), - .data (W_rf_wr_data), - .q (R_rf_b), - .rdaddress (D_iw_b), - .wraddress (R_dst_regnum), - .wren (W_rf_wren) - ); - -//synthesis translate_off -`ifdef NO_PLI -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; -`else -defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; -`endif -//synthesis translate_on -//synthesis read_comments_as_HDL on -//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; -//synthesis read_comments_as_HDL off - assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : - ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : - R_rf_a; - - assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : - (R_src2_use_imm)? D_iw_imm16 : - R_rf_b[15 : 0]; - - assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : - (R_ctrl_hi_imm16)? D_iw_imm16 : - (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : - R_rf_b[31 : 16]; - - assign R_src2 = {R_src2_hi, R_src2_lo}; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_valid <= 0; - else - E_valid <= R_valid | E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_new_inst <= 0; - else - E_new_inst <= R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src1 <= 0; - else - E_src1 <= R_src1; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_src2 <= 0; - else - E_src2 <= R_src2; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_invert_arith_src_msb <= 0; - else - E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_alu_sub <= 0; - else - E_alu_sub <= D_ctrl_alu_subtract & R_valid; - end - - - assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; - assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, - E_src1[30 : 0]}; - - assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, - E_src2[30 : 0]}; - - assign E_arith_result = E_alu_sub ? - E_arith_src1 - E_arith_src2 : - E_arith_src1 + E_arith_src2; - - assign E_mem_baddr = E_arith_result[18 : 0]; - assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : - (R_logic_op == 2'b01)? (E_src1 & E_src2) : - (R_logic_op == 2'b10)? (E_src1 | E_src2) : - (E_src1 ^ E_src2); - - assign E_logic_result_is_0 = E_logic_result == 0; - assign E_eq = E_logic_result_is_0; - assign E_lt = E_arith_result[32]; - assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : - (R_compare_op == 2'b01)? ~E_lt : - (R_compare_op == 2'b10)? E_lt : - ~E_eq; - - assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; - assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; - assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; - assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : - (R_ctrl_rot_right ? E_shift_rot_result[0] : - E_shift_rot_result[31]); - - assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : - (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : - {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_result <= 0; - else - E_shift_rot_result <= E_shift_rot_result_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - E_shift_rot_cnt <= 0; - else - E_shift_rot_cnt <= E_shift_rot_cnt_nxt; - end - - - assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : - (D_iw_control_regnum == 3'd1)? W_estatus_reg : - (D_iw_control_regnum == 3'd2)? W_bstatus_reg : - (D_iw_control_regnum == 3'd3)? W_ienable_reg : - (D_iw_control_regnum == 3'd4)? W_ipending_reg : - 0; - - assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : - (R_ctrl_shift_rot)? E_shift_rot_result : - (R_ctrl_logic)? E_logic_result : - (R_ctrl_custom)? E_ci_result : - E_arith_result; - - assign R_stb_data = R_rf_b[7 : 0]; - assign R_sth_data = R_rf_b[15 : 0]; - assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : - (D_mem16)? {R_sth_data, R_sth_data} : - R_rf_b; - - assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : - ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : - 4'b1111; - - assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); - assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); - assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); - assign E_st_stall = d_write_nxt; - assign d_address = W_mem_baddr; - assign av_ld_getting_data = d_read & ~d_waitrequest; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_read <= 0; - else - d_read <= d_read_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_writedata <= 0; - else - d_writedata <= E_st_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_byteenable <= 0; - else - d_byteenable <= E_mem_byte_en; - end - - - assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); - assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); - assign av_ld_aligning_data_nxt = av_ld_aligning_data ? - ~av_ld_align_one_more_cycle : - (~D_mem32 & av_ld_getting_data); - - assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? - ~av_ld_getting_data : - (R_ctrl_ld & E_new_inst); - - assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); - assign av_ld_rshift8 = av_ld_aligning_data & - (av_ld_align_cycle < (W_mem_baddr[1 : 0])); - - assign av_ld_extend = av_ld_aligning_data; - assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : - av_ld_extend ? av_ld_byte0_data : - d_readdata[7 : 0]; - - assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[15 : 8]; - - assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[23 : 16]; - - assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : - av_ld_extend ? {8 {av_fill_bit}} : - d_readdata[31 : 24]; - - assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); - assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, - av_ld_byte1_data, av_ld_byte0_data}; - - assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; - assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_align_cycle <= 0; - else - av_ld_align_cycle <= av_ld_align_cycle_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_waiting_for_data <= 0; - else - av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_aligning_data <= 0; - else - av_ld_aligning_data <= av_ld_aligning_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte0_data <= 0; - else - av_ld_byte0_data <= av_ld_byte0_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte1_data <= 0; - else if (av_ld_byte1_data_en) - av_ld_byte1_data <= av_ld_byte1_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte2_data <= 0; - else - av_ld_byte2_data <= av_ld_byte2_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - av_ld_byte3_data <= 0; - else - av_ld_byte3_data <= av_ld_byte3_data_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_valid <= 0; - else - W_valid <= E_valid & ~E_stall; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_control_rd_data <= 0; - else - W_control_rd_data <= E_control_rd_data; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_cmp_result <= 0; - else - W_cmp_result <= E_cmp_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_alu_result <= 0; - else - W_alu_result <= E_alu_result; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_status_reg_pie <= 0; - else - W_status_reg_pie <= W_status_reg_pie_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_estatus_reg <= 0; - else - W_estatus_reg <= W_estatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_bstatus_reg <= 0; - else - W_bstatus_reg <= W_bstatus_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ienable_reg <= 0; - else - W_ienable_reg <= W_ienable_reg_nxt; - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - W_ipending_reg <= 0; - else - W_ipending_reg <= W_ipending_reg_nxt; - end - - - assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : - R_ctrl_rdctl_inst ? W_control_rd_data : - W_alu_result[31 : 0]; - - assign W_wr_data = W_wr_data_non_zero; - assign W_br_taken = R_ctrl_br & W_cmp_result; - assign W_mem_baddr = W_alu_result[18 : 0]; - assign W_status_reg = W_status_reg_pie; - assign E_wrctl_status = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd0); - - assign E_wrctl_estatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd1); - - assign E_wrctl_bstatus = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd2); - - assign E_wrctl_ienable = R_ctrl_wrctl_inst & - (D_iw_control_regnum == 3'd3); - - assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : - (D_op_eret) ? W_estatus_reg : - (D_op_bret) ? W_bstatus_reg : - (E_wrctl_status) ? E_src1[0] : - W_status_reg_pie; - - assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; - assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : - (R_ctrl_exception) ? W_status_reg : - (E_wrctl_estatus) ? E_src1[0] : - W_estatus_reg; - - assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; - assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : - (E_wrctl_bstatus) ? E_src1[0] : - W_bstatus_reg; - - assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; - assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? - E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; - - assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - hbreak_enabled <= 1'b1; - else if (E_valid) - hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; - end - - - nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci - ( - .D_valid (D_valid), - .E_st_data (E_st_data), - .E_valid (E_valid), - .F_pc (F_pc), - .address_nxt (jtag_debug_module_address), - .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), - .byteenable_nxt (jtag_debug_module_byteenable), - .clk (jtag_debug_module_clk), - .d_address (d_address), - .d_read (d_read), - .d_waitrequest (d_waitrequest), - .d_write (d_write), - .debugaccess_nxt (jtag_debug_module_debugaccess), - .hbreak_enabled (hbreak_enabled), - .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), - .oci_hbreak_req (oci_hbreak_req), - .oci_ienable (oci_ienable), - .oci_single_step_mode (oci_single_step_mode), - .read_nxt (jtag_debug_module_read), - .readdata (jtag_debug_module_readdata), - .reset (jtag_debug_module_reset), - .reset_n (reset_n), - .resetrequest (jtag_debug_module_resetrequest), - .test_ending (test_ending), - .test_has_ended (test_has_ended), - .waitrequest (jtag_debug_module_waitrequest), - .write_nxt (jtag_debug_module_write), - .writedata_nxt (jtag_debug_module_writedata) - ); - - //jtag_debug_module, which is an e_avalon_slave - assign jtag_debug_module_clk = clk; - assign jtag_debug_module_reset = ~reset_n; - assign D_ctrl_custom = 1'b0; - assign R_ctrl_custom_nxt = D_ctrl_custom; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom <= 0; - else if (R_en) - R_ctrl_custom <= R_ctrl_custom_nxt; - end - - - assign D_ctrl_custom_multi = 1'b0; - assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_custom_multi <= 0; - else if (R_en) - R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; - end - - - assign D_ctrl_jmp_indirect = D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_indirect <= 0; - else if (R_en) - R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; - end - - - assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; - assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_jmp_direct <= 0; - else if (R_en) - R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; - end - - - assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; - assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_retaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; - end - - - assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; - assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_implicit_dst_eretaddr <= 0; - else if (R_en) - R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; - end - - - assign D_ctrl_exception = D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60; - - assign R_ctrl_exception_nxt = D_ctrl_exception; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_exception <= 0; - else if (R_en) - R_ctrl_exception <= R_ctrl_exception_nxt; - end - - - assign D_ctrl_break = D_op_break|D_op_hbreak; - assign R_ctrl_break_nxt = D_ctrl_break; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_break <= 0; - else if (R_en) - R_ctrl_break <= R_ctrl_break_nxt; - end - - - assign D_ctrl_crst = D_op_crst|D_op_rsvx63; - assign R_ctrl_crst_nxt = D_ctrl_crst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_crst <= 0; - else if (R_en) - R_ctrl_crst <= R_ctrl_crst_nxt; - end - - - assign D_ctrl_uncond_cti_non_br = D_op_call| - D_op_jmpi| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_callr; - - assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_uncond_cti_non_br <= 0; - else if (R_en) - R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; - end - - - assign D_ctrl_retaddr = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_div| - D_op_divu| - D_op_mul| - D_op_muli| - D_op_mulxss| - D_op_mulxsu| - D_op_mulxuu| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak; - - assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_retaddr <= 0; - else if (R_en) - R_ctrl_retaddr <= R_ctrl_retaddr_nxt; - end - - - assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; - assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_logical <= 0; - else if (R_en) - R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; - end - - - assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; - assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_right_arith <= 0; - else if (R_en) - R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; - end - - - assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; - assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rot_right <= 0; - else if (R_en) - R_ctrl_rot_right <= R_ctrl_rot_right_nxt; - end - - - assign D_ctrl_shift_rot_right = D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot_right <= 0; - else if (R_en) - R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; - end - - - assign D_ctrl_shift_rot = D_op_slli| - D_op_rsvx50| - D_op_sll| - D_op_rsvx51| - D_op_roli| - D_op_rsvx34| - D_op_rol| - D_op_rsvx35| - D_op_srli| - D_op_srl| - D_op_srai| - D_op_sra| - D_op_rsvx10| - D_op_ror| - D_op_rsvx42| - D_op_rsvx43; - - assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_shift_rot <= 0; - else if (R_en) - R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; - end - - - assign D_ctrl_logic = D_op_and| - D_op_or| - D_op_xor| - D_op_nor| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori; - - assign R_ctrl_logic_nxt = D_ctrl_logic; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_logic <= 0; - else if (R_en) - R_ctrl_logic <= R_ctrl_logic_nxt; - end - - - assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; - assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_hi_imm16 <= 0; - else if (R_en) - R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; - end - - - assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| - D_op_cmpltui| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_unsigned_lo_imm16 <= 0; - else if (R_en) - R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; - end - - - assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; - assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_uncond <= 0; - else if (R_en) - R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; - end - - - assign D_ctrl_br = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62; - - assign R_ctrl_br_nxt = D_ctrl_br; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br <= 0; - else if (R_en) - R_ctrl_br <= R_ctrl_br_nxt; - end - - - assign D_ctrl_alu_subtract = D_op_sub| - D_op_rsvx25| - D_op_cmplti| - D_op_cmpltui| - D_op_cmplt| - D_op_cmpltu| - D_op_blt| - D_op_bltu| - D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpge| - D_op_cmpgeu| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42; - - assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_subtract <= 0; - else if (R_en) - R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; - end - - - assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; - assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_signed_comparison <= 0; - else if (R_en) - R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; - end - - - assign D_ctrl_br_cmp = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_rsvx00| - D_op_cmpge| - D_op_cmplt| - D_op_cmpne| - D_op_cmpgeu| - D_op_cmpltu| - D_op_cmpeq| - D_op_rsvx56; - - assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_br_cmp <= 0; - else if (R_en) - R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; - end - - - assign D_ctrl_ld_signed = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63; - - assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_signed <= 0; - else if (R_en) - R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; - end - - - assign D_ctrl_ld = D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio; - - assign R_ctrl_ld_nxt = D_ctrl_ld; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld <= 0; - else if (R_en) - R_ctrl_ld <= R_ctrl_ld_nxt; - end - - - assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; - assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_non_io <= 0; - else if (R_en) - R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; - end - - - assign D_ctrl_st = D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61; - - assign R_ctrl_st_nxt = D_ctrl_st; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_st <= 0; - else if (R_en) - R_ctrl_st <= R_ctrl_st_nxt; - end - - - assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; - assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ld_io <= 0; - else if (R_en) - R_ctrl_ld_io <= R_ctrl_ld_io_nxt; - end - - - assign D_ctrl_b_is_dst = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda; - - assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_b_is_dst <= 0; - else if (R_en) - R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; - end - - - assign D_ctrl_ignore_dst = D_op_br| - D_op_bge| - D_op_blt| - D_op_bne| - D_op_beq| - D_op_bgeu| - D_op_bltu| - D_op_rsv62| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57; - - assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_ignore_dst <= 0; - else if (R_en) - R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; - end - - - assign D_ctrl_src2_choose_imm = D_op_addi| - D_op_andhi| - D_op_orhi| - D_op_xorhi| - D_op_andi| - D_op_ori| - D_op_xori| - D_op_call| - D_op_rdprs| - D_op_cmpgei| - D_op_cmplti| - D_op_cmpnei| - D_op_cmpgeui| - D_op_cmpltui| - D_op_cmpeqi| - D_op_jmpi| - D_op_rsv09| - D_op_rsv17| - D_op_rsv25| - D_op_rsv33| - D_op_rsv41| - D_op_rsv49| - D_op_rsv57| - D_op_ldb| - D_op_ldh| - D_op_ldl| - D_op_ldw| - D_op_ldbio| - D_op_ldhio| - D_op_ldwio| - D_op_rsv63| - D_op_ldbu| - D_op_ldhu| - D_op_ldbuio| - D_op_ldhuio| - D_op_initd| - D_op_initda| - D_op_flushd| - D_op_flushda| - D_op_stb| - D_op_sth| - D_op_stw| - D_op_stc| - D_op_stbio| - D_op_sthio| - D_op_stwio| - D_op_rsv61| - D_op_roli| - D_op_rsvx10| - D_op_slli| - D_op_srli| - D_op_rsvx34| - D_op_rsvx42| - D_op_rsvx50| - D_op_srai; - - assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_src2_choose_imm <= 0; - else if (R_en) - R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; - end - - - assign D_ctrl_wrctl_inst = D_op_wrctl; - assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_wrctl_inst <= 0; - else if (R_en) - R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; - end - - - assign D_ctrl_rdctl_inst = D_op_rdctl; - assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_rdctl_inst <= 0; - else if (R_en) - R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; - end - - - assign D_ctrl_force_src2_zero = D_op_call| - D_op_rsv02| - D_op_nextpc| - D_op_callr| - D_op_trap| - D_op_rsvx44| - D_op_intr| - D_op_rsvx60| - D_op_break| - D_op_hbreak| - D_op_eret| - D_op_bret| - D_op_rsvx17| - D_op_rsvx25| - D_op_ret| - D_op_jmp| - D_op_rsvx21| - D_op_jmpi; - - assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_force_src2_zero <= 0; - else if (R_en) - R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; - end - - - assign D_ctrl_alu_force_xor = D_op_cmpgei| - D_op_cmpgeui| - D_op_cmpeqi| - D_op_cmpge| - D_op_cmpgeu| - D_op_cmpeq| - D_op_cmpnei| - D_op_cmpne| - D_op_bge| - D_op_rsv10| - D_op_bgeu| - D_op_rsv42| - D_op_beq| - D_op_rsv34| - D_op_bne| - D_op_rsv62| - D_op_br| - D_op_rsv02; - - assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - R_ctrl_alu_force_xor <= 0; - else if (R_en) - R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; - end - - - //data_master, which is an e_avalon_master - //instruction_master, which is an e_avalon_master - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign F_inst = (F_op_call)? 56'h20202063616c6c : - (F_op_jmpi)? 56'h2020206a6d7069 : - (F_op_ldbu)? 56'h2020206c646275 : - (F_op_addi)? 56'h20202061646469 : - (F_op_stb)? 56'h20202020737462 : - (F_op_br)? 56'h20202020206272 : - (F_op_ldb)? 56'h202020206c6462 : - (F_op_cmpgei)? 56'h20636d70676569 : - (F_op_ldhu)? 56'h2020206c646875 : - (F_op_andi)? 56'h202020616e6469 : - (F_op_sth)? 56'h20202020737468 : - (F_op_bge)? 56'h20202020626765 : - (F_op_ldh)? 56'h202020206c6468 : - (F_op_cmplti)? 56'h20636d706c7469 : - (F_op_initda)? 56'h20696e69746461 : - (F_op_ori)? 56'h202020206f7269 : - (F_op_stw)? 56'h20202020737477 : - (F_op_blt)? 56'h20202020626c74 : - (F_op_ldw)? 56'h202020206c6477 : - (F_op_cmpnei)? 56'h20636d706e6569 : - (F_op_flushda)? 56'h666c7573686461 : - (F_op_xori)? 56'h202020786f7269 : - (F_op_bne)? 56'h20202020626e65 : - (F_op_cmpeqi)? 56'h20636d70657169 : - (F_op_ldbuio)? 56'h206c646275696f : - (F_op_muli)? 56'h2020206d756c69 : - (F_op_stbio)? 56'h2020737462696f : - (F_op_beq)? 56'h20202020626571 : - (F_op_ldbio)? 56'h20206c6462696f : - (F_op_cmpgeui)? 56'h636d7067657569 : - (F_op_ldhuio)? 56'h206c646875696f : - (F_op_andhi)? 56'h2020616e646869 : - (F_op_sthio)? 56'h2020737468696f : - (F_op_bgeu)? 56'h20202062676575 : - (F_op_ldhio)? 56'h20206c6468696f : - (F_op_cmpltui)? 56'h636d706c747569 : - (F_op_initd)? 56'h2020696e697464 : - (F_op_orhi)? 56'h2020206f726869 : - (F_op_stwio)? 56'h2020737477696f : - (F_op_bltu)? 56'h202020626c7475 : - (F_op_ldwio)? 56'h20206c6477696f : - (F_op_flushd)? 56'h20666c75736864 : - (F_op_xorhi)? 56'h2020786f726869 : - (F_op_eret)? 56'h20202065726574 : - (F_op_roli)? 56'h202020726f6c69 : - (F_op_rol)? 56'h20202020726f6c : - (F_op_flushp)? 56'h20666c75736870 : - (F_op_ret)? 56'h20202020726574 : - (F_op_nor)? 56'h202020206e6f72 : - (F_op_mulxuu)? 56'h206d756c787575 : - (F_op_cmpge)? 56'h2020636d706765 : - (F_op_bret)? 56'h20202062726574 : - (F_op_ror)? 56'h20202020726f72 : - (F_op_flushi)? 56'h20666c75736869 : - (F_op_jmp)? 56'h202020206a6d70 : - (F_op_and)? 56'h20202020616e64 : - (F_op_cmplt)? 56'h2020636d706c74 : - (F_op_slli)? 56'h202020736c6c69 : - (F_op_sll)? 56'h20202020736c6c : - (F_op_or)? 56'h20202020206f72 : - (F_op_mulxsu)? 56'h206d756c787375 : - (F_op_cmpne)? 56'h2020636d706e65 : - (F_op_srli)? 56'h20202073726c69 : - (F_op_srl)? 56'h2020202073726c : - (F_op_nextpc)? 56'h206e6578747063 : - (F_op_callr)? 56'h202063616c6c72 : - (F_op_xor)? 56'h20202020786f72 : - (F_op_mulxss)? 56'h206d756c787373 : - (F_op_cmpeq)? 56'h2020636d706571 : - (F_op_divu)? 56'h20202064697675 : - (F_op_div)? 56'h20202020646976 : - (F_op_rdctl)? 56'h2020726463746c : - (F_op_mul)? 56'h202020206d756c : - (F_op_cmpgeu)? 56'h20636d70676575 : - (F_op_initi)? 56'h2020696e697469 : - (F_op_trap)? 56'h20202074726170 : - (F_op_wrctl)? 56'h2020777263746c : - (F_op_cmpltu)? 56'h20636d706c7475 : - (F_op_add)? 56'h20202020616464 : - (F_op_break)? 56'h2020627265616b : - (F_op_hbreak)? 56'h2068627265616b : - (F_op_sync)? 56'h20202073796e63 : - (F_op_sub)? 56'h20202020737562 : - (F_op_srai)? 56'h20202073726169 : - (F_op_sra)? 56'h20202020737261 : - (F_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign D_inst = (D_op_call)? 56'h20202063616c6c : - (D_op_jmpi)? 56'h2020206a6d7069 : - (D_op_ldbu)? 56'h2020206c646275 : - (D_op_addi)? 56'h20202061646469 : - (D_op_stb)? 56'h20202020737462 : - (D_op_br)? 56'h20202020206272 : - (D_op_ldb)? 56'h202020206c6462 : - (D_op_cmpgei)? 56'h20636d70676569 : - (D_op_ldhu)? 56'h2020206c646875 : - (D_op_andi)? 56'h202020616e6469 : - (D_op_sth)? 56'h20202020737468 : - (D_op_bge)? 56'h20202020626765 : - (D_op_ldh)? 56'h202020206c6468 : - (D_op_cmplti)? 56'h20636d706c7469 : - (D_op_initda)? 56'h20696e69746461 : - (D_op_ori)? 56'h202020206f7269 : - (D_op_stw)? 56'h20202020737477 : - (D_op_blt)? 56'h20202020626c74 : - (D_op_ldw)? 56'h202020206c6477 : - (D_op_cmpnei)? 56'h20636d706e6569 : - (D_op_flushda)? 56'h666c7573686461 : - (D_op_xori)? 56'h202020786f7269 : - (D_op_bne)? 56'h20202020626e65 : - (D_op_cmpeqi)? 56'h20636d70657169 : - (D_op_ldbuio)? 56'h206c646275696f : - (D_op_muli)? 56'h2020206d756c69 : - (D_op_stbio)? 56'h2020737462696f : - (D_op_beq)? 56'h20202020626571 : - (D_op_ldbio)? 56'h20206c6462696f : - (D_op_cmpgeui)? 56'h636d7067657569 : - (D_op_ldhuio)? 56'h206c646875696f : - (D_op_andhi)? 56'h2020616e646869 : - (D_op_sthio)? 56'h2020737468696f : - (D_op_bgeu)? 56'h20202062676575 : - (D_op_ldhio)? 56'h20206c6468696f : - (D_op_cmpltui)? 56'h636d706c747569 : - (D_op_initd)? 56'h2020696e697464 : - (D_op_orhi)? 56'h2020206f726869 : - (D_op_stwio)? 56'h2020737477696f : - (D_op_bltu)? 56'h202020626c7475 : - (D_op_ldwio)? 56'h20206c6477696f : - (D_op_flushd)? 56'h20666c75736864 : - (D_op_xorhi)? 56'h2020786f726869 : - (D_op_eret)? 56'h20202065726574 : - (D_op_roli)? 56'h202020726f6c69 : - (D_op_rol)? 56'h20202020726f6c : - (D_op_flushp)? 56'h20666c75736870 : - (D_op_ret)? 56'h20202020726574 : - (D_op_nor)? 56'h202020206e6f72 : - (D_op_mulxuu)? 56'h206d756c787575 : - (D_op_cmpge)? 56'h2020636d706765 : - (D_op_bret)? 56'h20202062726574 : - (D_op_ror)? 56'h20202020726f72 : - (D_op_flushi)? 56'h20666c75736869 : - (D_op_jmp)? 56'h202020206a6d70 : - (D_op_and)? 56'h20202020616e64 : - (D_op_cmplt)? 56'h2020636d706c74 : - (D_op_slli)? 56'h202020736c6c69 : - (D_op_sll)? 56'h20202020736c6c : - (D_op_or)? 56'h20202020206f72 : - (D_op_mulxsu)? 56'h206d756c787375 : - (D_op_cmpne)? 56'h2020636d706e65 : - (D_op_srli)? 56'h20202073726c69 : - (D_op_srl)? 56'h2020202073726c : - (D_op_nextpc)? 56'h206e6578747063 : - (D_op_callr)? 56'h202063616c6c72 : - (D_op_xor)? 56'h20202020786f72 : - (D_op_mulxss)? 56'h206d756c787373 : - (D_op_cmpeq)? 56'h2020636d706571 : - (D_op_divu)? 56'h20202064697675 : - (D_op_div)? 56'h20202020646976 : - (D_op_rdctl)? 56'h2020726463746c : - (D_op_mul)? 56'h202020206d756c : - (D_op_cmpgeu)? 56'h20636d70676575 : - (D_op_initi)? 56'h2020696e697469 : - (D_op_trap)? 56'h20202074726170 : - (D_op_wrctl)? 56'h2020777263746c : - (D_op_cmpltu)? 56'h20636d706c7475 : - (D_op_add)? 56'h20202020616464 : - (D_op_break)? 56'h2020627265616b : - (D_op_hbreak)? 56'h2068627265616b : - (D_op_sync)? 56'h20202073796e63 : - (D_op_sub)? 56'h20202020737562 : - (D_op_srai)? 56'h20202073726169 : - (D_op_sra)? 56'h20202020737261 : - (D_op_intr)? 56'h202020696e7472 : - 56'h20202020424144; - - assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; - assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; - assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; - assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; - assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_a_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_register_bank_b_module ( + // inputs: + clock, + data, + rdaddress, + wraddress, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input clock; + input [ 31: 0] data; + input [ 4: 0] rdaddress; + input [ 4: 0] wraddress; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .q_b (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.address_reg_b = "CLOCK0", + the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 32, + the_altsyncram.numwords_b = 32, + the_altsyncram.operation_mode = "DUAL_PORT", + the_altsyncram.outdata_reg_b = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.rdcontrol_reg_b = "CLOCK0", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_b = 32, + the_altsyncram.widthad_a = 5, + the_altsyncram.widthad_b = 5; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_debug ( + // inputs: + clk, + dbrk_break, + debugreq, + hbreak_enabled, + jdo, + jrst_n, + ocireg_ers, + ocireg_mrs, + reset, + st_ready_test_idle, + take_action_ocimem_a, + take_action_ocireg, + xbrk_break, + + // outputs: + debugack, + monitor_error, + monitor_go, + monitor_ready, + oci_hbreak_req, + resetlatch, + resetrequest + ) +; + + output debugack; + output monitor_error; + output monitor_go; + output monitor_ready; + output oci_hbreak_req; + output resetlatch; + output resetrequest; + input clk; + input dbrk_break; + input debugreq; + input hbreak_enabled; + input [ 37: 0] jdo; + input jrst_n; + input ocireg_ers; + input ocireg_mrs; + input reset; + input st_ready_test_idle; + input take_action_ocimem_a; + input take_action_ocireg; + input xbrk_break; + + reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire debugack; + reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire oci_hbreak_req; + wire reset_sync; + reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire unxcomplemented_resetxx0; + assign unxcomplemented_resetxx0 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer + ( + .clk (clk), + .din (reset), + .dout (reset_sync), + .reset_n (unxcomplemented_resetxx0) + ); + + defparam the_altera_std_synchronizer.depth = 2; + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + break_on_reset <= 1'b0; + resetrequest <= 1'b0; + jtag_break <= 1'b0; + end + else if (take_action_ocimem_a) + begin + resetrequest <= jdo[22]; + jtag_break <= jdo[21] ? 1 + : jdo[20] ? 0 + : jtag_break; + + break_on_reset <= jdo[19] ? 1 + : jdo[18] ? 0 + : break_on_reset; + + resetlatch <= jdo[24] ? 0 : resetlatch; + end + else if (reset_sync) + begin + jtag_break <= break_on_reset; + resetlatch <= 1; + end + else if (debugreq & ~debugack & break_on_reset) + jtag_break <= 1'b1; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + monitor_ready <= 1'b0; + monitor_error <= 1'b0; + monitor_go <= 1'b0; + end + else + begin + if (take_action_ocimem_a && jdo[25]) + monitor_ready <= 1'b0; + else if (take_action_ocireg && ocireg_mrs) + monitor_ready <= 1'b1; + if (take_action_ocimem_a && jdo[25]) + monitor_error <= 1'b0; + else if (take_action_ocireg && ocireg_ers) + monitor_error <= 1'b1; + if (take_action_ocimem_a && jdo[23]) + monitor_go <= 1'b1; + else if (st_ready_test_idle) + monitor_go <= 1'b0; + end + end + + + assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq; + assign debugack = ~hbreak_enabled; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_ociram_sp_ram_module ( + // inputs: + address, + byteenable, + clock, + data, + wren, + + // outputs: + q + ) +; + + parameter lpm_file = "UNUSED"; + + + output [ 31: 0] q; + input [ 7: 0] address; + input [ 3: 0] byteenable; + input clock; + input [ 31: 0] data; + input wren; + + wire [ 31: 0] q; + wire [ 31: 0] ram_q; + assign q = ram_q; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clock), + .data_a (data), + .q_a (ram_q), + .wren_a (wren) + ); + + defparam the_altsyncram.init_file = lpm_file, + the_altsyncram.maximum_depth = 0, + the_altsyncram.numwords_a = 256, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 8; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_ocimem ( + // inputs: + address, + byteenable, + clk, + debugaccess, + jdo, + jrst_n, + read, + take_action_ocimem_a, + take_action_ocimem_b, + take_no_action_ocimem_a, + write, + writedata, + + // outputs: + MonDReg, + ociram_readdata, + waitrequest + ) +; + + output [ 31: 0] MonDReg; + output [ 31: 0] ociram_readdata; + output waitrequest; + input [ 8: 0] address; + input [ 3: 0] byteenable; + input clk; + input debugaccess; + input [ 37: 0] jdo; + input jrst_n; + input read; + input take_action_ocimem_a; + input take_action_ocimem_b; + input take_no_action_ocimem_a; + input write; + input [ 31: 0] writedata; + + reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 8: 0] MonARegAddrInc; + wire MonARegAddrIncAccessingRAM; + reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire avalon_ram_wr; + wire [ 31: 0] cfgrom_readdata; + reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 7: 0] ociram_addr; + wire [ 3: 0] ociram_byteenable; + wire [ 31: 0] ociram_readdata; + wire [ 31: 0] ociram_wr_data; + wire ociram_wr_en; + reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + jtag_rd <= 1'b0; + jtag_rd_d1 <= 1'b0; + jtag_ram_wr <= 1'b0; + jtag_ram_rd <= 1'b0; + jtag_ram_rd_d1 <= 1'b0; + jtag_ram_access <= 1'b0; + MonAReg <= 0; + MonDReg <= 0; + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else + begin + if (take_no_action_ocimem_a) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + jtag_rd <= 1'b1; + jtag_ram_rd <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else if (take_action_ocimem_a) + begin + MonAReg[10 : 2] <= { jdo[17], + jdo[33 : 26] }; + + jtag_rd <= 1'b1; + jtag_ram_rd <= ~jdo[17]; + jtag_ram_access <= ~jdo[17]; + end + else if (take_action_ocimem_b) + begin + MonAReg[10 : 2] <= MonARegAddrInc; + MonDReg <= jdo[34 : 3]; + jtag_ram_wr <= MonARegAddrIncAccessingRAM; + jtag_ram_access <= MonARegAddrIncAccessingRAM; + end + else + begin + jtag_rd <= 0; + jtag_ram_wr <= 0; + jtag_ram_rd <= 0; + jtag_ram_access <= 0; + if (jtag_rd_d1) + MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata; + end + jtag_rd_d1 <= jtag_rd; + jtag_ram_rd_d1 <= jtag_ram_rd; + if (~waitrequest) + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + else if (write) + waitrequest <= ~address[8] & jtag_ram_access; + else if (read) + begin + avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access); + waitrequest <= ~avalon_ociram_readdata_ready; + end + else + begin + waitrequest <= 1'b1; + avalon_ociram_readdata_ready <= 1'b0; + end + end + end + + + assign MonARegAddrInc = MonAReg[10 : 2]+1; + assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8]; + assign avalon_ram_wr = write & ~address[8] & debugaccess; + assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0]; + assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata; + assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable; + assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr; +//nios_system_nios2_processor_ociram_sp_ram, which is an nios_sp_ram +nios_system_nios2_processor_ociram_sp_ram_module nios_system_nios2_processor_ociram_sp_ram + ( + .address (ociram_addr), + .byteenable (ociram_byteenable), + .clock (clk), + .data (ociram_wr_data), + .q (ociram_readdata), + .wren (ociram_wr_en) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.dat"; +`else +defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_ociram_sp_ram.lpm_file = "nios_system_nios2_processor_ociram_default_contents.mif"; +//synthesis read_comments_as_HDL off + assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : + (MonAReg[4 : 2] == 3'd1)? 32'h00001313 : + (MonAReg[4 : 2] == 3'd2)? 32'h00040000 : + (MonAReg[4 : 2] == 3'd3)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd4)? 32'h20000000 : + (MonAReg[4 : 2] == 3'd5)? 32'h00000000 : + (MonAReg[4 : 2] == 3'd6)? 32'h00000000 : + 32'h00000000; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_avalon_reg ( + // inputs: + address, + clk, + debugaccess, + monitor_error, + monitor_go, + monitor_ready, + reset_n, + write, + writedata, + + // outputs: + oci_ienable, + oci_reg_readdata, + oci_single_step_mode, + ocireg_ers, + ocireg_mrs, + take_action_ocireg + ) +; + + output [ 31: 0] oci_ienable; + output [ 31: 0] oci_reg_readdata; + output oci_single_step_mode; + output ocireg_ers; + output ocireg_mrs; + output take_action_ocireg; + input [ 8: 0] address; + input clk; + input debugaccess; + input monitor_error; + input monitor_go; + input monitor_ready; + input reset_n; + input write; + input [ 31: 0] writedata; + + reg [ 31: 0] oci_ienable; + wire oci_reg_00_addressed; + wire oci_reg_01_addressed; + wire [ 31: 0] oci_reg_readdata; + reg oci_single_step_mode; + wire ocireg_ers; + wire ocireg_mrs; + wire ocireg_sstep; + wire take_action_oci_intr_mask_reg; + wire take_action_ocireg; + wire write_strobe; + assign oci_reg_00_addressed = address == 9'h100; + assign oci_reg_01_addressed = address == 9'h101; + assign write_strobe = write & debugaccess; + assign take_action_ocireg = write_strobe & oci_reg_00_addressed; + assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed; + assign ocireg_ers = writedata[1]; + assign ocireg_mrs = writedata[0]; + assign ocireg_sstep = writedata[3]; + assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go, + monitor_ready, monitor_error} : + oci_reg_01_addressed ? oci_ienable : + 32'b0; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_single_step_mode <= 1'b0; + else if (take_action_ocireg) + oci_single_step_mode <= ocireg_sstep; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + oci_ienable <= 32'b00000000000000000000000000100000; + else if (take_action_oci_intr_mask_reg) + oci_ienable <= writedata | ~(32'b00000000000000000000000000100000); + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_break ( + // inputs: + clk, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + jdo, + jrst_n, + reset_n, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + xbrk_goto0, + xbrk_goto1, + + // outputs: + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + trigbrktype, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3 + ) +; + + output [ 31: 0] break_readreg; + output dbrk_hit0_latch; + output dbrk_hit1_latch; + output dbrk_hit2_latch; + output dbrk_hit3_latch; + output trigbrktype; + output trigger_state_0; + output trigger_state_1; + output [ 7: 0] xbrk_ctrl0; + output [ 7: 0] xbrk_ctrl1; + output [ 7: 0] xbrk_ctrl2; + output [ 7: 0] xbrk_ctrl3; + input clk; + input dbrk_break; + input dbrk_goto0; + input dbrk_goto1; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_break_a; + input take_action_break_b; + input take_action_break_c; + input take_no_action_break_a; + input take_no_action_break_b; + input take_no_action_break_c; + input xbrk_goto0; + input xbrk_goto1; + + wire [ 3: 0] break_a_wpr; + wire [ 1: 0] break_a_wpr_high_bits; + wire [ 1: 0] break_a_wpr_low_bits; + wire [ 1: 0] break_b_rr; + wire [ 1: 0] break_c_rr; + reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + wire dbrk0_high_value; + wire dbrk0_low_value; + wire dbrk1_high_value; + wire dbrk1_low_value; + wire dbrk2_high_value; + wire dbrk2_low_value; + wire dbrk3_high_value; + wire dbrk3_low_value; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire take_action_any_break; + reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg trigger_state; + wire trigger_state_0; + wire trigger_state_1; + wire [ 31: 0] xbrk0_value; + wire [ 31: 0] xbrk1_value; + wire [ 31: 0] xbrk2_value; + wire [ 31: 0] xbrk3_value; + reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + assign break_a_wpr = jdo[35 : 32]; + assign break_a_wpr_high_bits = break_a_wpr[3 : 2]; + assign break_a_wpr_low_bits = break_a_wpr[1 : 0]; + assign break_b_rr = jdo[33 : 32]; + assign break_c_rr = jdo[33 : 32]; + assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + xbrk_ctrl0 <= 0; + xbrk_ctrl1 <= 0; + xbrk_ctrl2 <= 0; + xbrk_ctrl3 <= 0; + trigbrktype <= 0; + end + else + begin + if (take_action_any_break) + trigbrktype <= 0; + else if (dbrk_break) + trigbrktype <= 1; + if (take_action_break_b) + begin + if ((break_b_rr == 2'b00) && (0 >= 1)) + begin + xbrk_ctrl0[0] <= jdo[27]; + xbrk_ctrl0[1] <= jdo[28]; + xbrk_ctrl0[2] <= jdo[29]; + xbrk_ctrl0[3] <= jdo[30]; + xbrk_ctrl0[4] <= jdo[21]; + xbrk_ctrl0[5] <= jdo[20]; + xbrk_ctrl0[6] <= jdo[19]; + xbrk_ctrl0[7] <= jdo[18]; + end + if ((break_b_rr == 2'b01) && (0 >= 2)) + begin + xbrk_ctrl1[0] <= jdo[27]; + xbrk_ctrl1[1] <= jdo[28]; + xbrk_ctrl1[2] <= jdo[29]; + xbrk_ctrl1[3] <= jdo[30]; + xbrk_ctrl1[4] <= jdo[21]; + xbrk_ctrl1[5] <= jdo[20]; + xbrk_ctrl1[6] <= jdo[19]; + xbrk_ctrl1[7] <= jdo[18]; + end + if ((break_b_rr == 2'b10) && (0 >= 3)) + begin + xbrk_ctrl2[0] <= jdo[27]; + xbrk_ctrl2[1] <= jdo[28]; + xbrk_ctrl2[2] <= jdo[29]; + xbrk_ctrl2[3] <= jdo[30]; + xbrk_ctrl2[4] <= jdo[21]; + xbrk_ctrl2[5] <= jdo[20]; + xbrk_ctrl2[6] <= jdo[19]; + xbrk_ctrl2[7] <= jdo[18]; + end + if ((break_b_rr == 2'b11) && (0 >= 4)) + begin + xbrk_ctrl3[0] <= jdo[27]; + xbrk_ctrl3[1] <= jdo[28]; + xbrk_ctrl3[2] <= jdo[29]; + xbrk_ctrl3[3] <= jdo[30]; + xbrk_ctrl3[4] <= jdo[21]; + xbrk_ctrl3[5] <= jdo[20]; + xbrk_ctrl3[6] <= jdo[19]; + xbrk_ctrl3[7] <= jdo[18]; + end + end + end + end + + + assign dbrk_hit0_latch = 1'b0; + assign dbrk0_low_value = 0; + assign dbrk0_high_value = 0; + assign dbrk_hit1_latch = 1'b0; + assign dbrk1_low_value = 0; + assign dbrk1_high_value = 0; + assign dbrk_hit2_latch = 1'b0; + assign dbrk2_low_value = 0; + assign dbrk2_high_value = 0; + assign dbrk_hit3_latch = 1'b0; + assign dbrk3_low_value = 0; + assign dbrk3_high_value = 0; + assign xbrk0_value = 32'b0; + assign xbrk1_value = 32'b0; + assign xbrk2_value = 32'b0; + assign xbrk3_value = 32'b0; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + break_readreg <= 32'b0; + else if (take_action_any_break) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_a) + case (break_a_wpr_high_bits) + + 2'd0: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= xbrk0_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= xbrk1_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= xbrk2_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= xbrk3_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd0 + + 2'd1: begin + break_readreg <= 32'b0; + end // 2'd1 + + 2'd2: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_low_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_low_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_low_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_low_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd2 + + 2'd3: begin + case (break_a_wpr_low_bits) // synthesis full_case + + 2'd0: begin + break_readreg <= dbrk0_high_value; + end // 2'd0 + + 2'd1: begin + break_readreg <= dbrk1_high_value; + end // 2'd1 + + 2'd2: begin + break_readreg <= dbrk2_high_value; + end // 2'd2 + + 2'd3: begin + break_readreg <= dbrk3_high_value; + end // 2'd3 + + endcase // break_a_wpr_low_bits + end // 2'd3 + + endcase // break_a_wpr_high_bits + else if (take_no_action_break_b) + break_readreg <= jdo[31 : 0]; + else if (take_no_action_break_c) + break_readreg <= jdo[31 : 0]; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trigger_state <= 0; + else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0)) + trigger_state <= 0; + else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1)) + trigger_state <= -1; + end + + + assign trigger_state_0 = ~trigger_state; + assign trigger_state_1 = trigger_state; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_xbrk ( + // inputs: + D_valid, + E_valid, + F_pc, + clk, + reset_n, + trigger_state_0, + trigger_state_1, + xbrk_ctrl0, + xbrk_ctrl1, + xbrk_ctrl2, + xbrk_ctrl3, + + // outputs: + xbrk_break, + xbrk_goto0, + xbrk_goto1, + xbrk_traceoff, + xbrk_traceon, + xbrk_trigout + ) +; + + output xbrk_break; + output xbrk_goto0; + output xbrk_goto1; + output xbrk_traceoff; + output xbrk_traceon; + output xbrk_trigout; + input D_valid; + input E_valid; + input [ 16: 0] F_pc; + input clk; + input reset_n; + input trigger_state_0; + input trigger_state_1; + input [ 7: 0] xbrk_ctrl0; + input [ 7: 0] xbrk_ctrl1; + input [ 7: 0] xbrk_ctrl2; + input [ 7: 0] xbrk_ctrl3; + + wire D_cpu_addr_en; + wire E_cpu_addr_en; + reg E_xbrk_goto0; + reg E_xbrk_goto1; + reg E_xbrk_traceoff; + reg E_xbrk_traceon; + reg E_xbrk_trigout; + wire [ 18: 0] cpu_i_address; + wire xbrk0_armed; + wire xbrk0_break_hit; + wire xbrk0_goto0_hit; + wire xbrk0_goto1_hit; + wire xbrk0_toff_hit; + wire xbrk0_ton_hit; + wire xbrk0_tout_hit; + wire xbrk1_armed; + wire xbrk1_break_hit; + wire xbrk1_goto0_hit; + wire xbrk1_goto1_hit; + wire xbrk1_toff_hit; + wire xbrk1_ton_hit; + wire xbrk1_tout_hit; + wire xbrk2_armed; + wire xbrk2_break_hit; + wire xbrk2_goto0_hit; + wire xbrk2_goto1_hit; + wire xbrk2_toff_hit; + wire xbrk2_ton_hit; + wire xbrk2_tout_hit; + wire xbrk3_armed; + wire xbrk3_break_hit; + wire xbrk3_goto0_hit; + wire xbrk3_goto1_hit; + wire xbrk3_toff_hit; + wire xbrk3_ton_hit; + wire xbrk3_tout_hit; + reg xbrk_break; + wire xbrk_break_hit; + wire xbrk_goto0; + wire xbrk_goto0_hit; + wire xbrk_goto1; + wire xbrk_goto1_hit; + wire xbrk_toff_hit; + wire xbrk_ton_hit; + wire xbrk_tout_hit; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + assign cpu_i_address = {F_pc, 2'b00}; + assign D_cpu_addr_en = D_valid; + assign E_cpu_addr_en = E_valid; + assign xbrk0_break_hit = 0; + assign xbrk0_ton_hit = 0; + assign xbrk0_toff_hit = 0; + assign xbrk0_tout_hit = 0; + assign xbrk0_goto0_hit = 0; + assign xbrk0_goto1_hit = 0; + assign xbrk1_break_hit = 0; + assign xbrk1_ton_hit = 0; + assign xbrk1_toff_hit = 0; + assign xbrk1_tout_hit = 0; + assign xbrk1_goto0_hit = 0; + assign xbrk1_goto1_hit = 0; + assign xbrk2_break_hit = 0; + assign xbrk2_ton_hit = 0; + assign xbrk2_toff_hit = 0; + assign xbrk2_tout_hit = 0; + assign xbrk2_goto0_hit = 0; + assign xbrk2_goto1_hit = 0; + assign xbrk3_break_hit = 0; + assign xbrk3_ton_hit = 0; + assign xbrk3_toff_hit = 0; + assign xbrk3_tout_hit = 0; + assign xbrk3_goto0_hit = 0; + assign xbrk3_goto1_hit = 0; + assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit); + assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit); + assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit); + assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit); + assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit); + assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + xbrk_break <= 0; + else if (E_cpu_addr_en) + xbrk_break <= xbrk_break_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceon <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceon <= xbrk_ton_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_traceoff <= 0; + else if (E_cpu_addr_en) + E_xbrk_traceoff <= xbrk_toff_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_trigout <= 0; + else if (E_cpu_addr_en) + E_xbrk_trigout <= xbrk_tout_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto0 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto0 <= xbrk_goto0_hit; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_xbrk_goto1 <= 0; + else if (E_cpu_addr_en) + E_xbrk_goto1 <= xbrk_goto1_hit; + end + + + assign xbrk_traceon = 1'b0; + assign xbrk_traceoff = 1'b0; + assign xbrk_trigout = 1'b0; + assign xbrk_goto0 = 1'b0; + assign xbrk_goto1 = 1'b0; + assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) || + (xbrk_ctrl0[5] & trigger_state_1); + + assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) || + (xbrk_ctrl1[5] & trigger_state_1); + + assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) || + (xbrk_ctrl2[5] & trigger_state_1); + + assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) || + (xbrk_ctrl3[5] & trigger_state_1); + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dbrk ( + // inputs: + E_st_data, + av_ld_data_aligned_filtered, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugack, + reset_n, + + // outputs: + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + dbrk_break, + dbrk_goto0, + dbrk_goto1, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dbrk_trigout + ) +; + + output [ 18: 0] cpu_d_address; + output cpu_d_read; + output [ 31: 0] cpu_d_readdata; + output cpu_d_wait; + output cpu_d_write; + output [ 31: 0] cpu_d_writedata; + output dbrk_break; + output dbrk_goto0; + output dbrk_goto1; + output dbrk_traceme; + output dbrk_traceoff; + output dbrk_traceon; + output dbrk_trigout; + input [ 31: 0] E_st_data; + input [ 31: 0] av_ld_data_aligned_filtered; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugack; + input reset_n; + + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk0_armed; + wire dbrk0_break_pulse; + wire dbrk0_goto0; + wire dbrk0_goto1; + wire dbrk0_traceme; + wire dbrk0_traceoff; + wire dbrk0_traceon; + wire dbrk0_trigout; + wire dbrk1_armed; + wire dbrk1_break_pulse; + wire dbrk1_goto0; + wire dbrk1_goto1; + wire dbrk1_traceme; + wire dbrk1_traceoff; + wire dbrk1_traceon; + wire dbrk1_trigout; + wire dbrk2_armed; + wire dbrk2_break_pulse; + wire dbrk2_goto0; + wire dbrk2_goto1; + wire dbrk2_traceme; + wire dbrk2_traceoff; + wire dbrk2_traceon; + wire dbrk2_trigout; + wire dbrk3_armed; + wire dbrk3_break_pulse; + wire dbrk3_goto0; + wire dbrk3_goto1; + wire dbrk3_traceme; + wire dbrk3_traceoff; + wire dbrk3_traceon; + wire dbrk3_trigout; + reg dbrk_break; + reg dbrk_break_pulse; + wire [ 31: 0] dbrk_data; + reg dbrk_goto0; + reg dbrk_goto1; + reg dbrk_traceme; + reg dbrk_traceoff; + reg dbrk_traceon; + reg dbrk_trigout; + assign cpu_d_address = d_address; + assign cpu_d_readdata = av_ld_data_aligned_filtered; + assign cpu_d_read = d_read; + assign cpu_d_writedata = E_st_data; + assign cpu_d_write = d_write; + assign cpu_d_wait = d_waitrequest; + assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + dbrk_break <= 0; + else + dbrk_break <= dbrk_break ? ~debugack + : dbrk_break_pulse; + + end + + + assign dbrk0_armed = 1'b0; + assign dbrk0_trigout = 1'b0; + assign dbrk0_break_pulse = 1'b0; + assign dbrk0_traceoff = 1'b0; + assign dbrk0_traceon = 1'b0; + assign dbrk0_traceme = 1'b0; + assign dbrk0_goto0 = 1'b0; + assign dbrk0_goto1 = 1'b0; + assign dbrk1_armed = 1'b0; + assign dbrk1_trigout = 1'b0; + assign dbrk1_break_pulse = 1'b0; + assign dbrk1_traceoff = 1'b0; + assign dbrk1_traceon = 1'b0; + assign dbrk1_traceme = 1'b0; + assign dbrk1_goto0 = 1'b0; + assign dbrk1_goto1 = 1'b0; + assign dbrk2_armed = 1'b0; + assign dbrk2_trigout = 1'b0; + assign dbrk2_break_pulse = 1'b0; + assign dbrk2_traceoff = 1'b0; + assign dbrk2_traceon = 1'b0; + assign dbrk2_traceme = 1'b0; + assign dbrk2_goto0 = 1'b0; + assign dbrk2_goto1 = 1'b0; + assign dbrk3_armed = 1'b0; + assign dbrk3_trigout = 1'b0; + assign dbrk3_break_pulse = 1'b0; + assign dbrk3_traceoff = 1'b0; + assign dbrk3_traceon = 1'b0; + assign dbrk3_traceme = 1'b0; + assign dbrk3_goto0 = 1'b0; + assign dbrk3_goto1 = 1'b0; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + dbrk_trigout <= 0; + dbrk_break_pulse <= 0; + dbrk_traceoff <= 0; + dbrk_traceon <= 0; + dbrk_traceme <= 0; + dbrk_goto0 <= 0; + dbrk_goto1 <= 0; + end + else + begin + dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout; + dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse; + dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff; + dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon; + dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme; + dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0; + dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_itrace ( + // inputs: + clk, + dbrk_traceoff, + dbrk_traceon, + jdo, + jrst_n, + take_action_tracectrl, + trc_enb, + xbrk_traceoff, + xbrk_traceon, + xbrk_wrap_traceoff, + + // outputs: + dct_buffer, + dct_count, + itm, + trc_ctrl, + trc_on + ) +; + + output [ 29: 0] dct_buffer; + output [ 3: 0] dct_count; + output [ 35: 0] itm; + output [ 15: 0] trc_ctrl; + output trc_on; + input clk; + input dbrk_traceoff; + input dbrk_traceon; + input [ 15: 0] jdo; + input jrst_n; + input take_action_tracectrl; + input trc_enb; + input xbrk_traceoff; + input xbrk_traceon; + input xbrk_wrap_traceoff; + + wire curr_pid; + reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] dct_code; + reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire dct_is_taken; + wire [ 31: 0] excaddr; + wire instr_retired; + wire is_advanced_exception; + wire is_cond_dct; + wire is_dct; + wire is_exception_no_break; + wire is_fast_tlb_miss_exception; + wire is_idct; + reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire not_in_debug_mode; + reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_dct_outcome_in_sync; + wire record_itrace; + wire [ 31: 0] retired_pcb; + reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 1: 0] sync_code; + wire [ 6: 0] sync_interval; + wire sync_pending; + reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 6: 0] sync_timer_next; + reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire [ 15: 0] trc_ctrl; + reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire trc_on; + assign is_cond_dct = 1'b0; + assign is_dct = 1'b0; + assign dct_is_taken = 1'b0; + assign is_idct = 1'b0; + assign retired_pcb = 32'b0; + assign not_in_debug_mode = 1'b0; + assign instr_retired = 1'b0; + assign is_advanced_exception = 1'b0; + assign is_exception_no_break = 1'b0; + assign is_fast_tlb_miss_exception = 1'b0; + assign curr_pid = 1'b0; + assign excaddr = 32'b0; + assign sync_code = trc_ctrl[3 : 2]; + assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 }; + assign sync_pending = sync_timer == 0; + assign record_dct_outcome_in_sync = dct_is_taken & sync_pending; + assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1); + assign record_itrace = trc_on & trc_ctrl[4]; + assign dct_code = {is_cond_dct, dct_is_taken}; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + trc_clear <= 0; + else + trc_clear <= ~trc_enb & + take_action_tracectrl & jdo[4]; + + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else if (trc_clear || (!0 && !0)) + begin + itm <= 0; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= 0; + pending_frametype <= 4'b0000; + pending_exctype <= 1'b0; + pending_excaddr <= 0; + prev_pid <= 0; + prev_pid_valid <= 0; + snapped_pid <= 0; + snapped_curr_pid <= 0; + snapped_prev_pid <= 0; + pending_curr_pid <= 0; + pending_prev_pid <= 0; + end + else + begin + if (!prev_pid_valid) + begin + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + prev_pid <= curr_pid; + prev_pid_valid <= 1; + end + if (instr_retired | is_advanced_exception) + begin + if (~record_itrace) + pending_frametype <= 4'b1010; + else if (is_exception_no_break) + begin + pending_frametype <= 4'b0010; + pending_excaddr <= excaddr; + if (is_fast_tlb_miss_exception) + pending_exctype <= 1'b1; + else + pending_exctype <= 1'b0; + end + else if (is_idct) + pending_frametype <= 4'b1001; + else if (record_dct_outcome_in_sync) + pending_frametype <= 4'b1000; + else if (!is_dct & snapped_pid) + begin + pending_frametype <= 4'b0011; + pending_curr_pid <= snapped_curr_pid; + pending_prev_pid <= snapped_prev_pid; + snapped_pid <= 0; + end + else + pending_frametype <= 4'b0000; + if ((dct_count != 0) & + (~record_itrace | + is_exception_no_break | + is_idct | + record_dct_outcome_in_sync | + (!is_dct & snapped_pid))) + begin + itm <= {4'b0001, dct_buffer, 2'b00}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + begin + if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception) + begin + dct_buffer <= {dct_code, dct_buffer[29 : 2]}; + dct_count <= dct_count + 1; + end + if (record_itrace & (pending_frametype == 4'b0010)) + itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype}; + else if (record_itrace & ( + (pending_frametype == 4'b1000) | + (pending_frametype == 4'b1010) | + (pending_frametype == 4'b1001))) + begin + itm <= {pending_frametype, retired_pcb}; + sync_timer <= sync_interval; + if (0 & + ((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) & + !snapped_pid & prev_pid_valid) + begin + snapped_pid <= 1; + snapped_curr_pid <= curr_pid; + snapped_prev_pid <= prev_pid; + end + end + else if (record_itrace & + 0 & (pending_frametype == 4'b0011)) + itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid}; + else if (record_itrace & is_dct) + begin + if (dct_count == 4'd15) + begin + itm <= {4'b0001, dct_code, dct_buffer}; + dct_buffer <= 0; + dct_count <= 0; + sync_timer <= sync_timer_next; + end + else + itm <= 4'b0000; + end + else + itm <= {4'b0000, 32'b0}; + end + end + else + itm <= {4'b0000, 32'b0}; + end + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_ctrl_reg[0] <= 1'b0; + trc_ctrl_reg[1] <= 1'b0; + trc_ctrl_reg[3 : 2] <= 2'b00; + trc_ctrl_reg[4] <= 1'b0; + trc_ctrl_reg[7 : 5] <= 3'b000; + trc_ctrl_reg[8] <= 0; + trc_ctrl_reg[9] <= 1'b0; + trc_ctrl_reg[10] <= 1'b0; + end + else if (take_action_tracectrl) + begin + trc_ctrl_reg[0] <= jdo[5]; + trc_ctrl_reg[1] <= jdo[6]; + trc_ctrl_reg[3 : 2] <= jdo[8 : 7]; + trc_ctrl_reg[4] <= jdo[9]; + trc_ctrl_reg[9] <= jdo[14]; + trc_ctrl_reg[10] <= jdo[2]; + if (0) + trc_ctrl_reg[7 : 5] <= jdo[12 : 10]; + if (0 & 0) + trc_ctrl_reg[8] <= jdo[13]; + end + else if (xbrk_wrap_traceoff) + begin + trc_ctrl_reg[1] <= 0; + trc_ctrl_reg[0] <= 0; + end + else if (dbrk_traceoff | xbrk_traceoff) + trc_ctrl_reg[1] <= 0; + else if (trc_ctrl_reg[0] & + (dbrk_traceon | xbrk_traceon)) + trc_ctrl_reg[1] <= 1; + end + + + assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0; + assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode); + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_td_mode ( + // inputs: + ctrl, + + // outputs: + td_mode + ) +; + + output [ 3: 0] td_mode; + input [ 8: 0] ctrl; + + wire [ 2: 0] ctrl_bits_for_mux; + reg [ 3: 0] td_mode; + assign ctrl_bits_for_mux = ctrl[7 : 5]; + always @(ctrl_bits_for_mux) + begin + case (ctrl_bits_for_mux) + + 3'b000: begin + td_mode = 4'b0000; + end // 3'b000 + + 3'b001: begin + td_mode = 4'b1000; + end // 3'b001 + + 3'b010: begin + td_mode = 4'b0100; + end // 3'b010 + + 3'b011: begin + td_mode = 4'b1100; + end // 3'b011 + + 3'b100: begin + td_mode = 4'b0010; + end // 3'b100 + + 3'b101: begin + td_mode = 4'b1010; + end // 3'b101 + + 3'b110: begin + td_mode = 4'b0101; + end // 3'b110 + + 3'b111: begin + td_mode = 4'b1111; + end // 3'b111 + + endcase // ctrl_bits_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_dtrace ( + // inputs: + clk, + cpu_d_address, + cpu_d_read, + cpu_d_readdata, + cpu_d_wait, + cpu_d_write, + cpu_d_writedata, + jrst_n, + trc_ctrl, + + // outputs: + atm, + dtm + ) +; + + output [ 35: 0] atm; + output [ 35: 0] dtm; + input clk; + input [ 18: 0] cpu_d_address; + input cpu_d_read; + input [ 31: 0] cpu_d_readdata; + input cpu_d_wait; + input cpu_d_write; + input [ 31: 0] cpu_d_writedata; + input jrst_n; + input [ 15: 0] trc_ctrl; + + reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 31: 0] cpu_d_address_0_padded; + wire [ 31: 0] cpu_d_readdata_0_padded; + wire [ 31: 0] cpu_d_writedata_0_padded; + reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire record_load_addr; + wire record_load_data; + wire record_store_addr; + wire record_store_data; + wire [ 3: 0] td_mode_trc_ctrl; + assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0; + assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0; + assign cpu_d_address_0_padded = cpu_d_address | 32'b0; + //nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode, which is an e_instance + nios_system_nios2_processor_nios2_oci_td_mode nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode + ( + .ctrl (trc_ctrl[8 : 0]), + .td_mode (td_mode_trc_ctrl) + ); + + assign {record_load_addr, record_store_addr, + record_load_data, record_store_data} = td_mode_trc_ctrl; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + atm <= 0; + dtm <= 0; + end + else if (0) + begin + if (cpu_d_write & ~cpu_d_wait & record_store_addr) + atm <= {4'b0101, cpu_d_address_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_addr) + atm <= {4'b0100, cpu_d_address_0_padded}; + else + atm <= {4'b0000, cpu_d_address_0_padded}; + if (cpu_d_write & ~cpu_d_wait & record_store_data) + dtm <= {4'b0111, cpu_d_writedata_0_padded}; + else if (cpu_d_read & ~cpu_d_wait & record_load_data) + dtm <= {4'b0110, cpu_d_readdata_0_padded}; + else + dtm <= {4'b0000, cpu_d_readdata_0_padded}; + end + else + begin + atm <= 0; + dtm <= 0; + end + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_compute_tm_count ( + // inputs: + atm_valid, + dtm_valid, + itm_valid, + + // outputs: + compute_tm_count + ) +; + + output [ 1: 0] compute_tm_count; + input atm_valid; + input dtm_valid; + input itm_valid; + + reg [ 1: 0] compute_tm_count; + wire [ 2: 0] switch_for_mux; + assign switch_for_mux = {itm_valid, atm_valid, dtm_valid}; + always @(switch_for_mux) + begin + case (switch_for_mux) + + 3'b000: begin + compute_tm_count = 0; + end // 3'b000 + + 3'b001: begin + compute_tm_count = 1; + end // 3'b001 + + 3'b010: begin + compute_tm_count = 1; + end // 3'b010 + + 3'b011: begin + compute_tm_count = 2; + end // 3'b011 + + 3'b100: begin + compute_tm_count = 1; + end // 3'b100 + + 3'b101: begin + compute_tm_count = 2; + end // 3'b101 + + 3'b110: begin + compute_tm_count = 2; + end // 3'b110 + + 3'b111: begin + compute_tm_count = 3; + end // 3'b111 + + endcase // switch_for_mux + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifowp_inc ( + // inputs: + free2, + free3, + tm_count, + + // outputs: + fifowp_inc + ) +; + + output [ 3: 0] fifowp_inc; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 3: 0] fifowp_inc; + always @(free2 or free3 or tm_count) + begin + if (free3 & (tm_count == 3)) + fifowp_inc = 3; + else if (free2 & (tm_count >= 2)) + fifowp_inc = 2; + else if (tm_count >= 1) + fifowp_inc = 1; + else + fifowp_inc = 0; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifocount_inc ( + // inputs: + empty, + free2, + free3, + tm_count, + + // outputs: + fifocount_inc + ) +; + + output [ 4: 0] fifocount_inc; + input empty; + input free2; + input free3; + input [ 1: 0] tm_count; + + reg [ 4: 0] fifocount_inc; + always @(empty or free2 or free3 or tm_count) + begin + if (empty) + fifocount_inc = tm_count[1 : 0]; + else if (free3 & (tm_count == 3)) + fifocount_inc = 2; + else if (free2 & (tm_count >= 2)) + fifocount_inc = 1; + else if (tm_count >= 1) + fifocount_inc = 0; + else + fifocount_inc = {5{1'b1}}; + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_fifo ( + // inputs: + atm, + clk, + dbrk_traceme, + dbrk_traceoff, + dbrk_traceon, + dct_buffer, + dct_count, + dtm, + itm, + jrst_n, + reset_n, + test_ending, + test_has_ended, + trc_on, + + // outputs: + tw + ) +; + + output [ 35: 0] tw; + input [ 35: 0] atm; + input clk; + input dbrk_traceme; + input dbrk_traceoff; + input dbrk_traceon; + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input [ 35: 0] dtm; + input [ 35: 0] itm; + input jrst_n; + input reset_n; + input test_ending; + input test_has_ended; + input trc_on; + + wire atm_valid; + wire [ 1: 0] compute_tm_count_tm_count; + wire dtm_valid; + wire empty; + reg [ 35: 0] fifo_0; + wire fifo_0_enable; + wire [ 35: 0] fifo_0_mux; + reg [ 35: 0] fifo_1; + reg [ 35: 0] fifo_10; + wire fifo_10_enable; + wire [ 35: 0] fifo_10_mux; + reg [ 35: 0] fifo_11; + wire fifo_11_enable; + wire [ 35: 0] fifo_11_mux; + reg [ 35: 0] fifo_12; + wire fifo_12_enable; + wire [ 35: 0] fifo_12_mux; + reg [ 35: 0] fifo_13; + wire fifo_13_enable; + wire [ 35: 0] fifo_13_mux; + reg [ 35: 0] fifo_14; + wire fifo_14_enable; + wire [ 35: 0] fifo_14_mux; + reg [ 35: 0] fifo_15; + wire fifo_15_enable; + wire [ 35: 0] fifo_15_mux; + wire fifo_1_enable; + wire [ 35: 0] fifo_1_mux; + reg [ 35: 0] fifo_2; + wire fifo_2_enable; + wire [ 35: 0] fifo_2_mux; + reg [ 35: 0] fifo_3; + wire fifo_3_enable; + wire [ 35: 0] fifo_3_mux; + reg [ 35: 0] fifo_4; + wire fifo_4_enable; + wire [ 35: 0] fifo_4_mux; + reg [ 35: 0] fifo_5; + wire fifo_5_enable; + wire [ 35: 0] fifo_5_mux; + reg [ 35: 0] fifo_6; + wire fifo_6_enable; + wire [ 35: 0] fifo_6_mux; + reg [ 35: 0] fifo_7; + wire fifo_7_enable; + wire [ 35: 0] fifo_7_mux; + reg [ 35: 0] fifo_8; + wire fifo_8_enable; + wire [ 35: 0] fifo_8_mux; + reg [ 35: 0] fifo_9; + wire fifo_9_enable; + wire [ 35: 0] fifo_9_mux; + wire [ 35: 0] fifo_read_mux; + reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 4: 0] fifocount_inc_fifocount; + wire [ 35: 0] fifohead; + reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 3: 0] fifowp1; + wire [ 3: 0] fifowp2; + wire [ 3: 0] fifowp_inc_fifowp; + wire free2; + wire free3; + wire itm_valid; + reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 35: 0] ovr_pending_atm; + wire [ 35: 0] ovr_pending_dtm; + wire [ 1: 0] tm_count; + wire tm_count_ge1; + wire tm_count_ge2; + wire tm_count_ge3; + wire trc_this; + wire [ 35: 0] tw; + assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme; + assign itm_valid = |itm[35 : 32]; + assign atm_valid = |atm[35 : 32] & trc_this; + assign dtm_valid = |dtm[35 : 32] & trc_this; + assign free2 = ~fifocount[4]; + assign free3 = ~fifocount[4] & ~&fifocount[3 : 0]; + assign empty = ~|fifocount; + assign fifowp1 = fifowp + 1; + assign fifowp2 = fifowp + 2; + //nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count, which is an e_instance + nios_system_nios2_processor_nios2_oci_compute_tm_count nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count + ( + .atm_valid (atm_valid), + .compute_tm_count (compute_tm_count_tm_count), + .dtm_valid (dtm_valid), + .itm_valid (itm_valid) + ); + + assign tm_count = compute_tm_count_tm_count; + //nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifowp_inc nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp + ( + .fifowp_inc (fifowp_inc_fifowp), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount, which is an e_instance + nios_system_nios2_processor_nios2_oci_fifocount_inc nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount + ( + .empty (empty), + .fifocount_inc (fifocount_inc_fifocount), + .free2 (free2), + .free3 (free3), + .tm_count (tm_count) + ); + + //the_nios_system_nios2_processor_oci_test_bench, which is an e_instance + nios_system_nios2_processor_oci_test_bench the_nios_system_nios2_processor_oci_test_bench + ( + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .test_ending (test_ending), + .test_has_ended (test_has_ended) + ); + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + fiforp <= 0; + fifowp <= 0; + fifocount <= 0; + ovf_pending <= 1; + end + else + begin + fifowp <= fifowp + fifowp_inc_fifowp; + fifocount <= fifocount + fifocount_inc_fifocount; + if (~empty) + fiforp <= fiforp + 1; + if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count))) + ovf_pending <= 1; + else if (atm_valid | dtm_valid) + ovf_pending <= 0; + end + end + + + assign fifohead = fifo_read_mux; + assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm; + assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_0 <= 0; + else if (fifo_0_enable) + fifo_0 <= fifo_0_mux; + end + + + assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm : + (((fifowp == 4'd0) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_1 <= 0; + else if (fifo_1_enable) + fifo_1 <= fifo_1_mux; + end + + + assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm : + (((fifowp == 4'd1) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_2 <= 0; + else if (fifo_2_enable) + fifo_2 <= fifo_2_mux; + end + + + assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm : + (((fifowp == 4'd2) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_3 <= 0; + else if (fifo_3_enable) + fifo_3 <= fifo_3_mux; + end + + + assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm : + (((fifowp == 4'd3) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_4 <= 0; + else if (fifo_4_enable) + fifo_4 <= fifo_4_mux; + end + + + assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm : + (((fifowp == 4'd4) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_5 <= 0; + else if (fifo_5_enable) + fifo_5 <= fifo_5_mux; + end + + + assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm : + (((fifowp == 4'd5) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_6 <= 0; + else if (fifo_6_enable) + fifo_6 <= fifo_6_mux; + end + + + assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm : + (((fifowp == 4'd6) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_7 <= 0; + else if (fifo_7_enable) + fifo_7 <= fifo_7_mux; + end + + + assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm : + (((fifowp == 4'd7) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_8 <= 0; + else if (fifo_8_enable) + fifo_8 <= fifo_8_mux; + end + + + assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm : + (((fifowp == 4'd8) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_9 <= 0; + else if (fifo_9_enable) + fifo_9 <= fifo_9_mux; + end + + + assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm : + (((fifowp == 4'd9) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_10 <= 0; + else if (fifo_10_enable) + fifo_10 <= fifo_10_mux; + end + + + assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm : + (((fifowp == 4'd10) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_11 <= 0; + else if (fifo_11_enable) + fifo_11 <= fifo_11_mux; + end + + + assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm : + (((fifowp == 4'd11) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_12 <= 0; + else if (fifo_12_enable) + fifo_12 <= fifo_12_mux; + end + + + assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm : + (((fifowp == 4'd12) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_13 <= 0; + else if (fifo_13_enable) + fifo_13 <= fifo_13_mux; + end + + + assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm : + (((fifowp == 4'd13) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_14 <= 0; + else if (fifo_14_enable) + fifo_14 <= fifo_14_mux; + end + + + assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm : + (((fifowp == 4'd14) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + fifo_15 <= 0; + else if (fifo_15_enable) + fifo_15 <= fifo_15_mux; + end + + + assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm : + (((fifowp == 4'd15) && atm_valid))? ovr_pending_atm : + (((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm : + (((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm : + (((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm : + ovr_pending_dtm; + + assign tm_count_ge1 = |tm_count; + assign tm_count_ge2 = tm_count[1]; + assign tm_count_ge3 = &tm_count; + assign ovr_pending_atm = {ovf_pending, atm[34 : 0]}; + assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]}; + assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 : + (fiforp == 4'd1)? fifo_1 : + (fiforp == 4'd2)? fifo_2 : + (fiforp == 4'd3)? fifo_3 : + (fiforp == 4'd4)? fifo_4 : + (fiforp == 4'd5)? fifo_5 : + (fiforp == 4'd6)? fifo_6 : + (fiforp == 4'd7)? fifo_7 : + (fiforp == 4'd8)? fifo_8 : + (fiforp == 4'd9)? fifo_9 : + (fiforp == 4'd10)? fifo_10 : + (fiforp == 4'd11)? fifo_11 : + (fiforp == 4'd12)? fifo_12 : + (fiforp == 4'd13)? fifo_13 : + (fiforp == 4'd14)? fifo_14 : + fifo_15; + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_pib ( + // inputs: + clk, + clkx2, + jrst_n, + tw, + + // outputs: + tr_clk, + tr_data + ) +; + + output tr_clk; + output [ 17: 0] tr_data; + input clk; + input clkx2; + input jrst_n; + input [ 35: 0] tw; + + wire phase; + wire tr_clk; + reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + wire [ 17: 0] tr_data; + reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; + assign phase = x1^x2; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + x1 <= 0; + else + x1 <= ~x1; + end + + + always @(posedge clkx2 or negedge jrst_n) + begin + if (jrst_n == 0) + begin + x2 <= 0; + tr_clk_reg <= 0; + tr_data_reg <= 0; + end + else + begin + x2 <= x1; + tr_clk_reg <= ~phase; + tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18]; + end + end + + + assign tr_clk = 0 ? tr_clk_reg : 0; + assign tr_data = 0 ? tr_data_reg : 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci_im ( + // inputs: + clk, + jdo, + jrst_n, + reset_n, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_tracemem_a, + trc_ctrl, + tw, + + // outputs: + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_enb, + trc_im_addr, + trc_wrap, + xbrk_wrap_traceoff + ) +; + + output tracemem_on; + output [ 35: 0] tracemem_trcdata; + output tracemem_tw; + output trc_enb; + output [ 6: 0] trc_im_addr; + output trc_wrap; + output xbrk_wrap_traceoff; + input clk; + input [ 37: 0] jdo; + input jrst_n; + input reset_n; + input take_action_tracectrl; + input take_action_tracemem_a; + input take_action_tracemem_b; + input take_no_action_tracemem_a; + input [ 15: 0] trc_ctrl; + input [ 35: 0] tw; + + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire trc_enb; + reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire [ 35: 0] trc_im_data; + reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; + wire trc_on_chip; + reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire tw_valid; + wire xbrk_wrap_traceoff; + assign trc_im_data = tw; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (!0) + begin + trc_im_addr <= 0; + trc_wrap <= 0; + end + else if (take_action_tracectrl && + (jdo[4] | jdo[3])) + begin + if (jdo[4]) + trc_im_addr <= 0; + if (jdo[3]) + trc_wrap <= 0; + end + else if (trc_enb & trc_on_chip & tw_valid) + begin + trc_im_addr <= trc_im_addr+1; + if (&trc_im_addr) + trc_wrap <= 1; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + trc_jtag_addr <= 0; + else if (take_action_tracemem_a || + take_no_action_tracemem_a || + take_action_tracemem_b) + trc_jtag_addr <= take_action_tracemem_a ? + jdo[35 : 19] : + trc_jtag_addr + 1; + + end + + + assign trc_enb = trc_ctrl[0]; + assign trc_on_chip = ~trc_ctrl[8]; + assign tw_valid = |trc_im_data[35 : 32]; + assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap; + assign tracemem_tw = trc_wrap; + assign tracemem_on = trc_enb; + assign tracemem_trcdata = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_performance_monitors +; + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_nios2_oci ( + // inputs: + D_valid, + E_st_data, + E_valid, + F_pc, + address_nxt, + av_ld_data_aligned_filtered, + byteenable_nxt, + clk, + d_address, + d_read, + d_waitrequest, + d_write, + debugaccess_nxt, + hbreak_enabled, + read_nxt, + reset, + reset_n, + test_ending, + test_has_ended, + write_nxt, + writedata_nxt, + + // outputs: + jtag_debug_module_debugaccess_to_roms, + oci_hbreak_req, + oci_ienable, + oci_single_step_mode, + readdata, + resetrequest, + waitrequest + ) +; + + output jtag_debug_module_debugaccess_to_roms; + output oci_hbreak_req; + output [ 31: 0] oci_ienable; + output oci_single_step_mode; + output [ 31: 0] readdata; + output resetrequest; + output waitrequest; + input D_valid; + input [ 31: 0] E_st_data; + input E_valid; + input [ 16: 0] F_pc; + input [ 8: 0] address_nxt; + input [ 31: 0] av_ld_data_aligned_filtered; + input [ 3: 0] byteenable_nxt; + input clk; + input [ 18: 0] d_address; + input d_read; + input d_waitrequest; + input d_write; + input debugaccess_nxt; + input hbreak_enabled; + input read_nxt; + input reset; + input reset_n; + input test_ending; + input test_has_ended; + input write_nxt; + input [ 31: 0] writedata_nxt; + + wire [ 31: 0] MonDReg; + reg [ 8: 0] address; + wire [ 35: 0] atm; + wire [ 31: 0] break_readreg; + reg [ 3: 0] byteenable; + wire clkx2; + wire [ 18: 0] cpu_d_address; + wire cpu_d_read; + wire [ 31: 0] cpu_d_readdata; + wire cpu_d_wait; + wire cpu_d_write; + wire [ 31: 0] cpu_d_writedata; + wire dbrk_break; + wire dbrk_goto0; + wire dbrk_goto1; + wire dbrk_hit0_latch; + wire dbrk_hit1_latch; + wire dbrk_hit2_latch; + wire dbrk_hit3_latch; + wire dbrk_traceme; + wire dbrk_traceoff; + wire dbrk_traceon; + wire dbrk_trigout; + wire [ 29: 0] dct_buffer; + wire [ 3: 0] dct_count; + reg debugaccess; + wire debugack; + wire debugreq; + wire [ 35: 0] dtm; + wire dummy_sink; + wire [ 35: 0] itm; + wire [ 37: 0] jdo; + wire jrst_n; + wire jtag_debug_module_debugaccess_to_roms; + wire monitor_error; + wire monitor_go; + wire monitor_ready; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire [ 31: 0] oci_reg_readdata; + wire oci_single_step_mode; + wire [ 31: 0] ociram_readdata; + wire ocireg_ers; + wire ocireg_mrs; + reg read; + reg [ 31: 0] readdata; + wire resetlatch; + wire resetrequest; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_ocireg; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire tr_clk; + wire [ 17: 0] tr_data; + wire tracemem_on; + wire [ 35: 0] tracemem_trcdata; + wire tracemem_tw; + wire [ 15: 0] trc_ctrl; + wire trc_enb; + wire [ 6: 0] trc_im_addr; + wire trc_on; + wire trc_wrap; + wire trigbrktype; + wire trigger_state_0; + wire trigger_state_1; + wire trigout; + wire [ 35: 0] tw; + wire waitrequest; + reg write; + reg [ 31: 0] writedata; + wire xbrk_break; + wire [ 7: 0] xbrk_ctrl0; + wire [ 7: 0] xbrk_ctrl1; + wire [ 7: 0] xbrk_ctrl2; + wire [ 7: 0] xbrk_ctrl3; + wire xbrk_goto0; + wire xbrk_goto1; + wire xbrk_traceoff; + wire xbrk_traceon; + wire xbrk_trigout; + wire xbrk_wrap_traceoff; + nios_system_nios2_processor_nios2_oci_debug the_nios_system_nios2_processor_nios2_oci_debug + ( + .clk (clk), + .dbrk_break (dbrk_break), + .debugack (debugack), + .debugreq (debugreq), + .hbreak_enabled (hbreak_enabled), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_hbreak_req (oci_hbreak_req), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset (reset), + .resetlatch (resetlatch), + .resetrequest (resetrequest), + .st_ready_test_idle (st_ready_test_idle), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocireg (take_action_ocireg), + .xbrk_break (xbrk_break) + ); + + nios_system_nios2_processor_nios2_ocimem the_nios_system_nios2_processor_nios2_ocimem + ( + .MonDReg (MonDReg), + .address (address), + .byteenable (byteenable), + .clk (clk), + .debugaccess (debugaccess), + .jdo (jdo), + .jrst_n (jrst_n), + .ociram_readdata (ociram_readdata), + .read (read), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .waitrequest (waitrequest), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_avalon_reg the_nios_system_nios2_processor_nios2_avalon_reg + ( + .address (address), + .clk (clk), + .debugaccess (debugaccess), + .monitor_error (monitor_error), + .monitor_go (monitor_go), + .monitor_ready (monitor_ready), + .oci_ienable (oci_ienable), + .oci_reg_readdata (oci_reg_readdata), + .oci_single_step_mode (oci_single_step_mode), + .ocireg_ers (ocireg_ers), + .ocireg_mrs (ocireg_mrs), + .reset_n (reset_n), + .take_action_ocireg (take_action_ocireg), + .write (write), + .writedata (writedata) + ); + + nios_system_nios2_processor_nios2_oci_break the_nios_system_nios2_processor_nios2_oci_break + ( + .break_readreg (break_readreg), + .clk (clk), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .trigbrktype (trigbrktype), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1) + ); + + nios_system_nios2_processor_nios2_oci_xbrk the_nios_system_nios2_processor_nios2_oci_xbrk + ( + .D_valid (D_valid), + .E_valid (E_valid), + .F_pc (F_pc), + .clk (clk), + .reset_n (reset_n), + .trigger_state_0 (trigger_state_0), + .trigger_state_1 (trigger_state_1), + .xbrk_break (xbrk_break), + .xbrk_ctrl0 (xbrk_ctrl0), + .xbrk_ctrl1 (xbrk_ctrl1), + .xbrk_ctrl2 (xbrk_ctrl2), + .xbrk_ctrl3 (xbrk_ctrl3), + .xbrk_goto0 (xbrk_goto0), + .xbrk_goto1 (xbrk_goto1), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_trigout (xbrk_trigout) + ); + + nios_system_nios2_processor_nios2_oci_dbrk the_nios_system_nios2_processor_nios2_oci_dbrk + ( + .E_st_data (E_st_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .dbrk_break (dbrk_break), + .dbrk_goto0 (dbrk_goto0), + .dbrk_goto1 (dbrk_goto1), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dbrk_trigout (dbrk_trigout), + .debugack (debugack), + .reset_n (reset_n) + ); + + nios_system_nios2_processor_nios2_oci_itrace the_nios_system_nios2_processor_nios2_oci_itrace + ( + .clk (clk), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .itm (itm), + .jdo (jdo), + .jrst_n (jrst_n), + .take_action_tracectrl (take_action_tracectrl), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_on (trc_on), + .xbrk_traceoff (xbrk_traceoff), + .xbrk_traceon (xbrk_traceon), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + nios_system_nios2_processor_nios2_oci_dtrace the_nios_system_nios2_processor_nios2_oci_dtrace + ( + .atm (atm), + .clk (clk), + .cpu_d_address (cpu_d_address), + .cpu_d_read (cpu_d_read), + .cpu_d_readdata (cpu_d_readdata), + .cpu_d_wait (cpu_d_wait), + .cpu_d_write (cpu_d_write), + .cpu_d_writedata (cpu_d_writedata), + .dtm (dtm), + .jrst_n (jrst_n), + .trc_ctrl (trc_ctrl) + ); + + nios_system_nios2_processor_nios2_oci_fifo the_nios_system_nios2_processor_nios2_oci_fifo + ( + .atm (atm), + .clk (clk), + .dbrk_traceme (dbrk_traceme), + .dbrk_traceoff (dbrk_traceoff), + .dbrk_traceon (dbrk_traceon), + .dct_buffer (dct_buffer), + .dct_count (dct_count), + .dtm (dtm), + .itm (itm), + .jrst_n (jrst_n), + .reset_n (reset_n), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .trc_on (trc_on), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_pib the_nios_system_nios2_processor_nios2_oci_pib + ( + .clk (clk), + .clkx2 (clkx2), + .jrst_n (jrst_n), + .tr_clk (tr_clk), + .tr_data (tr_data), + .tw (tw) + ); + + nios_system_nios2_processor_nios2_oci_im the_nios_system_nios2_processor_nios2_oci_im + ( + .clk (clk), + .jdo (jdo), + .jrst_n (jrst_n), + .reset_n (reset_n), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_ctrl (trc_ctrl), + .trc_enb (trc_enb), + .trc_im_addr (trc_im_addr), + .trc_wrap (trc_wrap), + .tw (tw), + .xbrk_wrap_traceoff (xbrk_wrap_traceoff) + ); + + assign trigout = dbrk_trigout | xbrk_trigout; + assign jtag_debug_module_debugaccess_to_roms = debugack; + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + address <= 0; + else + address <= address_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + byteenable <= 0; + else + byteenable <= byteenable_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + writedata <= 0; + else + writedata <= writedata_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + debugaccess <= 0; + else + debugaccess <= debugaccess_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + read <= 0; + else + read <= read ? waitrequest : read_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + write <= 0; + else + write <= write ? waitrequest : write_nxt; + end + + + always @(posedge clk or negedge jrst_n) + begin + if (jrst_n == 0) + readdata <= 0; + else + readdata <= address[8] ? oci_reg_readdata : ociram_readdata; + end + + + nios_system_nios2_processor_jtag_debug_module_wrapper the_nios_system_nios2_processor_jtag_debug_module_wrapper + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .clk (clk), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .jdo (jdo), + .jrst_n (jrst_n), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .st_ready_test_idle (st_ready_test_idle), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1) + ); + + //dummy sink, which is an e_mux + assign dummy_sink = tr_clk | + tr_data | + trigout | + debugack; + + assign debugreq = 0; + assign clkx2 = 0; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor ( + // inputs: + clk, + d_irq, + d_readdata, + d_waitrequest, + i_readdata, + i_waitrequest, + jtag_debug_module_address, + jtag_debug_module_byteenable, + jtag_debug_module_debugaccess, + jtag_debug_module_read, + jtag_debug_module_write, + jtag_debug_module_writedata, + reset_n, + + // outputs: + d_address, + d_byteenable, + d_read, + d_write, + d_writedata, + i_address, + i_read, + jtag_debug_module_debugaccess_to_roms, + jtag_debug_module_readdata, + jtag_debug_module_resetrequest, + jtag_debug_module_waitrequest, + no_ci_readra + ) +; + + output [ 18: 0] d_address; + output [ 3: 0] d_byteenable; + output d_read; + output d_write; + output [ 31: 0] d_writedata; + output [ 18: 0] i_address; + output i_read; + output jtag_debug_module_debugaccess_to_roms; + output [ 31: 0] jtag_debug_module_readdata; + output jtag_debug_module_resetrequest; + output jtag_debug_module_waitrequest; + output no_ci_readra; + input clk; + input [ 31: 0] d_irq; + input [ 31: 0] d_readdata; + input d_waitrequest; + input [ 31: 0] i_readdata; + input i_waitrequest; + input [ 8: 0] jtag_debug_module_address; + input [ 3: 0] jtag_debug_module_byteenable; + input jtag_debug_module_debugaccess; + input jtag_debug_module_read; + input jtag_debug_module_write; + input [ 31: 0] jtag_debug_module_writedata; + input reset_n; + + wire [ 1: 0] D_compare_op; + wire D_ctrl_alu_force_xor; + wire D_ctrl_alu_signed_comparison; + wire D_ctrl_alu_subtract; + wire D_ctrl_b_is_dst; + wire D_ctrl_br; + wire D_ctrl_br_cmp; + wire D_ctrl_br_uncond; + wire D_ctrl_break; + wire D_ctrl_crst; + wire D_ctrl_custom; + wire D_ctrl_custom_multi; + wire D_ctrl_exception; + wire D_ctrl_force_src2_zero; + wire D_ctrl_hi_imm16; + wire D_ctrl_ignore_dst; + wire D_ctrl_implicit_dst_eretaddr; + wire D_ctrl_implicit_dst_retaddr; + wire D_ctrl_jmp_direct; + wire D_ctrl_jmp_indirect; + wire D_ctrl_ld; + wire D_ctrl_ld_io; + wire D_ctrl_ld_non_io; + wire D_ctrl_ld_signed; + wire D_ctrl_logic; + wire D_ctrl_rdctl_inst; + wire D_ctrl_retaddr; + wire D_ctrl_rot_right; + wire D_ctrl_shift_logical; + wire D_ctrl_shift_right_arith; + wire D_ctrl_shift_rot; + wire D_ctrl_shift_rot_right; + wire D_ctrl_src2_choose_imm; + wire D_ctrl_st; + wire D_ctrl_uncond_cti_non_br; + wire D_ctrl_unsigned_lo_imm16; + wire D_ctrl_wrctl_inst; + wire [ 4: 0] D_dst_regnum; + wire [ 55: 0] D_inst; + reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 4: 0] D_iw_a; + wire [ 4: 0] D_iw_b; + wire [ 4: 0] D_iw_c; + wire [ 2: 0] D_iw_control_regnum; + wire [ 7: 0] D_iw_custom_n; + wire D_iw_custom_readra; + wire D_iw_custom_readrb; + wire D_iw_custom_writerc; + wire [ 15: 0] D_iw_imm16; + wire [ 25: 0] D_iw_imm26; + wire [ 4: 0] D_iw_imm5; + wire [ 1: 0] D_iw_memsz; + wire [ 5: 0] D_iw_op; + wire [ 5: 0] D_iw_opx; + wire [ 4: 0] D_iw_shift_imm5; + wire [ 4: 0] D_iw_trap_break_imm5; + wire [ 16: 0] D_jmp_direct_target_waddr; + wire [ 1: 0] D_logic_op; + wire [ 1: 0] D_logic_op_raw; + wire D_mem16; + wire D_mem32; + wire D_mem8; + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + reg D_valid; + wire [ 55: 0] D_vinst; + wire D_wr_dst_reg; + wire [ 31: 0] E_alu_result; + reg E_alu_sub; + wire [ 32: 0] E_arith_result; + wire [ 31: 0] E_arith_src1; + wire [ 31: 0] E_arith_src2; + wire E_ci_multi_stall; + wire [ 31: 0] E_ci_result; + wire E_cmp_result; + wire [ 31: 0] E_control_rd_data; + wire E_eq; + reg E_invert_arith_src_msb; + wire E_ld_stall; + wire [ 31: 0] E_logic_result; + wire E_logic_result_is_0; + wire E_lt; + wire [ 18: 0] E_mem_baddr; + wire [ 3: 0] E_mem_byte_en; + reg E_new_inst; + reg [ 4: 0] E_shift_rot_cnt; + wire [ 4: 0] E_shift_rot_cnt_nxt; + wire E_shift_rot_done; + wire E_shift_rot_fill_bit; + reg [ 31: 0] E_shift_rot_result; + wire [ 31: 0] E_shift_rot_result_nxt; + wire E_shift_rot_stall; + reg [ 31: 0] E_src1; + reg [ 31: 0] E_src2; + wire [ 31: 0] E_st_data; + wire E_st_stall; + wire E_stall; + reg E_valid; + wire [ 55: 0] E_vinst; + wire E_wrctl_bstatus; + wire E_wrctl_estatus; + wire E_wrctl_ienable; + wire E_wrctl_status; + wire [ 31: 0] F_av_iw; + wire [ 4: 0] F_av_iw_a; + wire [ 4: 0] F_av_iw_b; + wire [ 4: 0] F_av_iw_c; + wire [ 2: 0] F_av_iw_control_regnum; + wire [ 7: 0] F_av_iw_custom_n; + wire F_av_iw_custom_readra; + wire F_av_iw_custom_readrb; + wire F_av_iw_custom_writerc; + wire [ 15: 0] F_av_iw_imm16; + wire [ 25: 0] F_av_iw_imm26; + wire [ 4: 0] F_av_iw_imm5; + wire [ 1: 0] F_av_iw_memsz; + wire [ 5: 0] F_av_iw_op; + wire [ 5: 0] F_av_iw_opx; + wire [ 4: 0] F_av_iw_shift_imm5; + wire [ 4: 0] F_av_iw_trap_break_imm5; + wire F_av_mem16; + wire F_av_mem32; + wire F_av_mem8; + wire [ 55: 0] F_inst; + wire [ 31: 0] F_iw; + wire [ 4: 0] F_iw_a; + wire [ 4: 0] F_iw_b; + wire [ 4: 0] F_iw_c; + wire [ 2: 0] F_iw_control_regnum; + wire [ 7: 0] F_iw_custom_n; + wire F_iw_custom_readra; + wire F_iw_custom_readrb; + wire F_iw_custom_writerc; + wire [ 15: 0] F_iw_imm16; + wire [ 25: 0] F_iw_imm26; + wire [ 4: 0] F_iw_imm5; + wire [ 1: 0] F_iw_memsz; + wire [ 5: 0] F_iw_op; + wire [ 5: 0] F_iw_opx; + wire [ 4: 0] F_iw_shift_imm5; + wire [ 4: 0] F_iw_trap_break_imm5; + wire F_mem16; + wire F_mem32; + wire F_mem8; + wire F_op_add; + wire F_op_addi; + wire F_op_and; + wire F_op_andhi; + wire F_op_andi; + wire F_op_beq; + wire F_op_bge; + wire F_op_bgeu; + wire F_op_blt; + wire F_op_bltu; + wire F_op_bne; + wire F_op_br; + wire F_op_break; + wire F_op_bret; + wire F_op_call; + wire F_op_callr; + wire F_op_cmpeq; + wire F_op_cmpeqi; + wire F_op_cmpge; + wire F_op_cmpgei; + wire F_op_cmpgeu; + wire F_op_cmpgeui; + wire F_op_cmplt; + wire F_op_cmplti; + wire F_op_cmpltu; + wire F_op_cmpltui; + wire F_op_cmpne; + wire F_op_cmpnei; + wire F_op_crst; + wire F_op_custom; + wire F_op_div; + wire F_op_divu; + wire F_op_eret; + wire F_op_flushd; + wire F_op_flushda; + wire F_op_flushi; + wire F_op_flushp; + wire F_op_hbreak; + wire F_op_initd; + wire F_op_initda; + wire F_op_initi; + wire F_op_intr; + wire F_op_jmp; + wire F_op_jmpi; + wire F_op_ldb; + wire F_op_ldbio; + wire F_op_ldbu; + wire F_op_ldbuio; + wire F_op_ldh; + wire F_op_ldhio; + wire F_op_ldhu; + wire F_op_ldhuio; + wire F_op_ldl; + wire F_op_ldw; + wire F_op_ldwio; + wire F_op_mul; + wire F_op_muli; + wire F_op_mulxss; + wire F_op_mulxsu; + wire F_op_mulxuu; + wire F_op_nextpc; + wire F_op_nor; + wire F_op_opx; + wire F_op_or; + wire F_op_orhi; + wire F_op_ori; + wire F_op_rdctl; + wire F_op_rdprs; + wire F_op_ret; + wire F_op_rol; + wire F_op_roli; + wire F_op_ror; + wire F_op_rsv02; + wire F_op_rsv09; + wire F_op_rsv10; + wire F_op_rsv17; + wire F_op_rsv18; + wire F_op_rsv25; + wire F_op_rsv26; + wire F_op_rsv33; + wire F_op_rsv34; + wire F_op_rsv41; + wire F_op_rsv42; + wire F_op_rsv49; + wire F_op_rsv57; + wire F_op_rsv61; + wire F_op_rsv62; + wire F_op_rsv63; + wire F_op_rsvx00; + wire F_op_rsvx10; + wire F_op_rsvx15; + wire F_op_rsvx17; + wire F_op_rsvx21; + wire F_op_rsvx25; + wire F_op_rsvx33; + wire F_op_rsvx34; + wire F_op_rsvx35; + wire F_op_rsvx42; + wire F_op_rsvx43; + wire F_op_rsvx44; + wire F_op_rsvx47; + wire F_op_rsvx50; + wire F_op_rsvx51; + wire F_op_rsvx55; + wire F_op_rsvx56; + wire F_op_rsvx60; + wire F_op_rsvx63; + wire F_op_sll; + wire F_op_slli; + wire F_op_sra; + wire F_op_srai; + wire F_op_srl; + wire F_op_srli; + wire F_op_stb; + wire F_op_stbio; + wire F_op_stc; + wire F_op_sth; + wire F_op_sthio; + wire F_op_stw; + wire F_op_stwio; + wire F_op_sub; + wire F_op_sync; + wire F_op_trap; + wire F_op_wrctl; + wire F_op_wrprs; + wire F_op_xor; + wire F_op_xorhi; + wire F_op_xori; + reg [ 16: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire F_pc_en; + wire [ 16: 0] F_pc_no_crst_nxt; + wire [ 16: 0] F_pc_nxt; + wire [ 16: 0] F_pc_plus_one; + wire [ 1: 0] F_pc_sel_nxt; + wire [ 18: 0] F_pcb; + wire [ 18: 0] F_pcb_nxt; + wire [ 18: 0] F_pcb_plus_four; + wire F_valid; + wire [ 55: 0] F_vinst; + reg [ 1: 0] R_compare_op; + reg R_ctrl_alu_force_xor; + wire R_ctrl_alu_force_xor_nxt; + reg R_ctrl_alu_signed_comparison; + wire R_ctrl_alu_signed_comparison_nxt; + reg R_ctrl_alu_subtract; + wire R_ctrl_alu_subtract_nxt; + reg R_ctrl_b_is_dst; + wire R_ctrl_b_is_dst_nxt; + reg R_ctrl_br; + reg R_ctrl_br_cmp; + wire R_ctrl_br_cmp_nxt; + wire R_ctrl_br_nxt; + reg R_ctrl_br_uncond; + wire R_ctrl_br_uncond_nxt; + reg R_ctrl_break; + wire R_ctrl_break_nxt; + reg R_ctrl_crst; + wire R_ctrl_crst_nxt; + reg R_ctrl_custom; + reg R_ctrl_custom_multi; + wire R_ctrl_custom_multi_nxt; + wire R_ctrl_custom_nxt; + reg R_ctrl_exception; + wire R_ctrl_exception_nxt; + reg R_ctrl_force_src2_zero; + wire R_ctrl_force_src2_zero_nxt; + reg R_ctrl_hi_imm16; + wire R_ctrl_hi_imm16_nxt; + reg R_ctrl_ignore_dst; + wire R_ctrl_ignore_dst_nxt; + reg R_ctrl_implicit_dst_eretaddr; + wire R_ctrl_implicit_dst_eretaddr_nxt; + reg R_ctrl_implicit_dst_retaddr; + wire R_ctrl_implicit_dst_retaddr_nxt; + reg R_ctrl_jmp_direct; + wire R_ctrl_jmp_direct_nxt; + reg R_ctrl_jmp_indirect; + wire R_ctrl_jmp_indirect_nxt; + reg R_ctrl_ld; + reg R_ctrl_ld_io; + wire R_ctrl_ld_io_nxt; + reg R_ctrl_ld_non_io; + wire R_ctrl_ld_non_io_nxt; + wire R_ctrl_ld_nxt; + reg R_ctrl_ld_signed; + wire R_ctrl_ld_signed_nxt; + reg R_ctrl_logic; + wire R_ctrl_logic_nxt; + reg R_ctrl_rdctl_inst; + wire R_ctrl_rdctl_inst_nxt; + reg R_ctrl_retaddr; + wire R_ctrl_retaddr_nxt; + reg R_ctrl_rot_right; + wire R_ctrl_rot_right_nxt; + reg R_ctrl_shift_logical; + wire R_ctrl_shift_logical_nxt; + reg R_ctrl_shift_right_arith; + wire R_ctrl_shift_right_arith_nxt; + reg R_ctrl_shift_rot; + wire R_ctrl_shift_rot_nxt; + reg R_ctrl_shift_rot_right; + wire R_ctrl_shift_rot_right_nxt; + reg R_ctrl_src2_choose_imm; + wire R_ctrl_src2_choose_imm_nxt; + reg R_ctrl_st; + wire R_ctrl_st_nxt; + reg R_ctrl_uncond_cti_non_br; + wire R_ctrl_uncond_cti_non_br_nxt; + reg R_ctrl_unsigned_lo_imm16; + wire R_ctrl_unsigned_lo_imm16_nxt; + reg R_ctrl_wrctl_inst; + wire R_ctrl_wrctl_inst_nxt; + reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire R_en; + reg [ 1: 0] R_logic_op; + wire [ 31: 0] R_rf_a; + wire [ 31: 0] R_rf_b; + wire [ 31: 0] R_src1; + wire [ 31: 0] R_src2; + wire [ 15: 0] R_src2_hi; + wire [ 15: 0] R_src2_lo; + reg R_src2_use_imm; + wire [ 7: 0] R_stb_data; + wire [ 15: 0] R_sth_data; + reg R_valid; + wire [ 55: 0] R_vinst; + reg R_wr_dst_reg; + reg [ 31: 0] W_alu_result; + wire W_br_taken; + reg W_bstatus_reg; + wire W_bstatus_reg_inst_nxt; + wire W_bstatus_reg_nxt; + reg W_cmp_result; + reg [ 31: 0] W_control_rd_data; + reg W_estatus_reg; + wire W_estatus_reg_inst_nxt; + wire W_estatus_reg_nxt; + reg [ 31: 0] W_ienable_reg; + wire [ 31: 0] W_ienable_reg_nxt; + reg [ 31: 0] W_ipending_reg; + wire [ 31: 0] W_ipending_reg_nxt; + wire [ 18: 0] W_mem_baddr; + wire [ 31: 0] W_rf_wr_data; + wire W_rf_wren; + wire W_status_reg; + reg W_status_reg_pie; + wire W_status_reg_pie_inst_nxt; + wire W_status_reg_pie_nxt; + reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; + wire [ 55: 0] W_vinst; + wire [ 31: 0] W_wr_data; + wire [ 31: 0] W_wr_data_non_zero; + wire av_fill_bit; + reg [ 1: 0] av_ld_align_cycle; + wire [ 1: 0] av_ld_align_cycle_nxt; + wire av_ld_align_one_more_cycle; + reg av_ld_aligning_data; + wire av_ld_aligning_data_nxt; + reg [ 7: 0] av_ld_byte0_data; + wire [ 7: 0] av_ld_byte0_data_nxt; + reg [ 7: 0] av_ld_byte1_data; + wire av_ld_byte1_data_en; + wire [ 7: 0] av_ld_byte1_data_nxt; + reg [ 7: 0] av_ld_byte2_data; + wire [ 7: 0] av_ld_byte2_data_nxt; + reg [ 7: 0] av_ld_byte3_data; + wire [ 7: 0] av_ld_byte3_data_nxt; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire [ 31: 0] av_ld_data_aligned_unfiltered; + wire av_ld_done; + wire av_ld_extend; + wire av_ld_getting_data; + wire av_ld_rshift8; + reg av_ld_waiting_for_data; + wire av_ld_waiting_for_data_nxt; + wire av_sign_bit; + wire [ 18: 0] d_address; + reg [ 3: 0] d_byteenable; + reg d_read; + wire d_read_nxt; + wire d_write; + wire d_write_nxt; + reg [ 31: 0] d_writedata; + reg hbreak_enabled; + reg hbreak_pending; + wire hbreak_pending_nxt; + wire hbreak_req; + wire [ 18: 0] i_address; + reg i_read; + wire i_read_nxt; + wire [ 31: 0] iactive; + wire intr_req; + wire jtag_debug_module_clk; + wire jtag_debug_module_debugaccess_to_roms; + wire [ 31: 0] jtag_debug_module_readdata; + wire jtag_debug_module_reset; + wire jtag_debug_module_resetrequest; + wire jtag_debug_module_waitrequest; + wire no_ci_readra; + wire oci_hbreak_req; + wire [ 31: 0] oci_ienable; + wire oci_single_step_mode; + wire oci_tb_hbreak_req; + wire test_ending; + wire test_has_ended; + reg wait_for_one_post_bret_inst; + //the_nios_system_nios2_processor_test_bench, which is an e_instance + nios_system_nios2_processor_test_bench the_nios_system_nios2_processor_test_bench + ( + .D_iw (D_iw), + .D_iw_op (D_iw_op), + .D_iw_opx (D_iw_opx), + .D_valid (D_valid), + .E_valid (E_valid), + .F_pcb (F_pcb), + .F_valid (F_valid), + .R_ctrl_ld (R_ctrl_ld), + .R_ctrl_ld_non_io (R_ctrl_ld_non_io), + .R_dst_regnum (R_dst_regnum), + .R_wr_dst_reg (R_wr_dst_reg), + .W_valid (W_valid), + .W_vinst (W_vinst), + .W_wr_data (W_wr_data), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered), + .clk (clk), + .d_address (d_address), + .d_byteenable (d_byteenable), + .d_read (d_read), + .d_write (d_write), + .d_write_nxt (d_write_nxt), + .i_address (i_address), + .i_read (i_read), + .i_readdata (i_readdata), + .i_waitrequest (i_waitrequest), + .reset_n (reset_n), + .test_has_ended (test_has_ended) + ); + + assign F_av_iw_a = F_av_iw[31 : 27]; + assign F_av_iw_b = F_av_iw[26 : 22]; + assign F_av_iw_c = F_av_iw[21 : 17]; + assign F_av_iw_custom_n = F_av_iw[13 : 6]; + assign F_av_iw_custom_readra = F_av_iw[16]; + assign F_av_iw_custom_readrb = F_av_iw[15]; + assign F_av_iw_custom_writerc = F_av_iw[14]; + assign F_av_iw_opx = F_av_iw[16 : 11]; + assign F_av_iw_op = F_av_iw[5 : 0]; + assign F_av_iw_shift_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm5 = F_av_iw[10 : 6]; + assign F_av_iw_imm16 = F_av_iw[21 : 6]; + assign F_av_iw_imm26 = F_av_iw[31 : 6]; + assign F_av_iw_memsz = F_av_iw[4 : 3]; + assign F_av_iw_control_regnum = F_av_iw[8 : 6]; + assign F_av_mem8 = F_av_iw_memsz == 2'b00; + assign F_av_mem16 = F_av_iw_memsz == 2'b01; + assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1; + assign F_iw_a = F_iw[31 : 27]; + assign F_iw_b = F_iw[26 : 22]; + assign F_iw_c = F_iw[21 : 17]; + assign F_iw_custom_n = F_iw[13 : 6]; + assign F_iw_custom_readra = F_iw[16]; + assign F_iw_custom_readrb = F_iw[15]; + assign F_iw_custom_writerc = F_iw[14]; + assign F_iw_opx = F_iw[16 : 11]; + assign F_iw_op = F_iw[5 : 0]; + assign F_iw_shift_imm5 = F_iw[10 : 6]; + assign F_iw_trap_break_imm5 = F_iw[10 : 6]; + assign F_iw_imm5 = F_iw[10 : 6]; + assign F_iw_imm16 = F_iw[21 : 6]; + assign F_iw_imm26 = F_iw[31 : 6]; + assign F_iw_memsz = F_iw[4 : 3]; + assign F_iw_control_regnum = F_iw[8 : 6]; + assign F_mem8 = F_iw_memsz == 2'b00; + assign F_mem16 = F_iw_memsz == 2'b01; + assign F_mem32 = F_iw_memsz[1] == 1'b1; + assign D_iw_a = D_iw[31 : 27]; + assign D_iw_b = D_iw[26 : 22]; + assign D_iw_c = D_iw[21 : 17]; + assign D_iw_custom_n = D_iw[13 : 6]; + assign D_iw_custom_readra = D_iw[16]; + assign D_iw_custom_readrb = D_iw[15]; + assign D_iw_custom_writerc = D_iw[14]; + assign D_iw_opx = D_iw[16 : 11]; + assign D_iw_op = D_iw[5 : 0]; + assign D_iw_shift_imm5 = D_iw[10 : 6]; + assign D_iw_trap_break_imm5 = D_iw[10 : 6]; + assign D_iw_imm5 = D_iw[10 : 6]; + assign D_iw_imm16 = D_iw[21 : 6]; + assign D_iw_imm26 = D_iw[31 : 6]; + assign D_iw_memsz = D_iw[4 : 3]; + assign D_iw_control_regnum = D_iw[8 : 6]; + assign D_mem8 = D_iw_memsz == 2'b00; + assign D_mem16 = D_iw_memsz == 2'b01; + assign D_mem32 = D_iw_memsz[1] == 1'b1; + assign F_op_call = F_iw_op == 0; + assign F_op_jmpi = F_iw_op == 1; + assign F_op_ldbu = F_iw_op == 3; + assign F_op_addi = F_iw_op == 4; + assign F_op_stb = F_iw_op == 5; + assign F_op_br = F_iw_op == 6; + assign F_op_ldb = F_iw_op == 7; + assign F_op_cmpgei = F_iw_op == 8; + assign F_op_ldhu = F_iw_op == 11; + assign F_op_andi = F_iw_op == 12; + assign F_op_sth = F_iw_op == 13; + assign F_op_bge = F_iw_op == 14; + assign F_op_ldh = F_iw_op == 15; + assign F_op_cmplti = F_iw_op == 16; + assign F_op_initda = F_iw_op == 19; + assign F_op_ori = F_iw_op == 20; + assign F_op_stw = F_iw_op == 21; + assign F_op_blt = F_iw_op == 22; + assign F_op_ldw = F_iw_op == 23; + assign F_op_cmpnei = F_iw_op == 24; + assign F_op_flushda = F_iw_op == 27; + assign F_op_xori = F_iw_op == 28; + assign F_op_stc = F_iw_op == 29; + assign F_op_bne = F_iw_op == 30; + assign F_op_ldl = F_iw_op == 31; + assign F_op_cmpeqi = F_iw_op == 32; + assign F_op_ldbuio = F_iw_op == 35; + assign F_op_muli = F_iw_op == 36; + assign F_op_stbio = F_iw_op == 37; + assign F_op_beq = F_iw_op == 38; + assign F_op_ldbio = F_iw_op == 39; + assign F_op_cmpgeui = F_iw_op == 40; + assign F_op_ldhuio = F_iw_op == 43; + assign F_op_andhi = F_iw_op == 44; + assign F_op_sthio = F_iw_op == 45; + assign F_op_bgeu = F_iw_op == 46; + assign F_op_ldhio = F_iw_op == 47; + assign F_op_cmpltui = F_iw_op == 48; + assign F_op_initd = F_iw_op == 51; + assign F_op_orhi = F_iw_op == 52; + assign F_op_stwio = F_iw_op == 53; + assign F_op_bltu = F_iw_op == 54; + assign F_op_ldwio = F_iw_op == 55; + assign F_op_rdprs = F_iw_op == 56; + assign F_op_flushd = F_iw_op == 59; + assign F_op_xorhi = F_iw_op == 60; + assign F_op_rsv02 = F_iw_op == 2; + assign F_op_rsv09 = F_iw_op == 9; + assign F_op_rsv10 = F_iw_op == 10; + assign F_op_rsv17 = F_iw_op == 17; + assign F_op_rsv18 = F_iw_op == 18; + assign F_op_rsv25 = F_iw_op == 25; + assign F_op_rsv26 = F_iw_op == 26; + assign F_op_rsv33 = F_iw_op == 33; + assign F_op_rsv34 = F_iw_op == 34; + assign F_op_rsv41 = F_iw_op == 41; + assign F_op_rsv42 = F_iw_op == 42; + assign F_op_rsv49 = F_iw_op == 49; + assign F_op_rsv57 = F_iw_op == 57; + assign F_op_rsv61 = F_iw_op == 61; + assign F_op_rsv62 = F_iw_op == 62; + assign F_op_rsv63 = F_iw_op == 63; + assign F_op_eret = F_op_opx & (F_iw_opx == 1); + assign F_op_roli = F_op_opx & (F_iw_opx == 2); + assign F_op_rol = F_op_opx & (F_iw_opx == 3); + assign F_op_flushp = F_op_opx & (F_iw_opx == 4); + assign F_op_ret = F_op_opx & (F_iw_opx == 5); + assign F_op_nor = F_op_opx & (F_iw_opx == 6); + assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7); + assign F_op_cmpge = F_op_opx & (F_iw_opx == 8); + assign F_op_bret = F_op_opx & (F_iw_opx == 9); + assign F_op_ror = F_op_opx & (F_iw_opx == 11); + assign F_op_flushi = F_op_opx & (F_iw_opx == 12); + assign F_op_jmp = F_op_opx & (F_iw_opx == 13); + assign F_op_and = F_op_opx & (F_iw_opx == 14); + assign F_op_cmplt = F_op_opx & (F_iw_opx == 16); + assign F_op_slli = F_op_opx & (F_iw_opx == 18); + assign F_op_sll = F_op_opx & (F_iw_opx == 19); + assign F_op_wrprs = F_op_opx & (F_iw_opx == 20); + assign F_op_or = F_op_opx & (F_iw_opx == 22); + assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23); + assign F_op_cmpne = F_op_opx & (F_iw_opx == 24); + assign F_op_srli = F_op_opx & (F_iw_opx == 26); + assign F_op_srl = F_op_opx & (F_iw_opx == 27); + assign F_op_nextpc = F_op_opx & (F_iw_opx == 28); + assign F_op_callr = F_op_opx & (F_iw_opx == 29); + assign F_op_xor = F_op_opx & (F_iw_opx == 30); + assign F_op_mulxss = F_op_opx & (F_iw_opx == 31); + assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32); + assign F_op_divu = F_op_opx & (F_iw_opx == 36); + assign F_op_div = F_op_opx & (F_iw_opx == 37); + assign F_op_rdctl = F_op_opx & (F_iw_opx == 38); + assign F_op_mul = F_op_opx & (F_iw_opx == 39); + assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40); + assign F_op_initi = F_op_opx & (F_iw_opx == 41); + assign F_op_trap = F_op_opx & (F_iw_opx == 45); + assign F_op_wrctl = F_op_opx & (F_iw_opx == 46); + assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48); + assign F_op_add = F_op_opx & (F_iw_opx == 49); + assign F_op_break = F_op_opx & (F_iw_opx == 52); + assign F_op_hbreak = F_op_opx & (F_iw_opx == 53); + assign F_op_sync = F_op_opx & (F_iw_opx == 54); + assign F_op_sub = F_op_opx & (F_iw_opx == 57); + assign F_op_srai = F_op_opx & (F_iw_opx == 58); + assign F_op_sra = F_op_opx & (F_iw_opx == 59); + assign F_op_intr = F_op_opx & (F_iw_opx == 61); + assign F_op_crst = F_op_opx & (F_iw_opx == 62); + assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0); + assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10); + assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15); + assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17); + assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21); + assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25); + assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33); + assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34); + assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35); + assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42); + assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43); + assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44); + assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47); + assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50); + assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51); + assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55); + assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56); + assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60); + assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63); + assign F_op_opx = F_iw_op == 58; + assign F_op_custom = F_iw_op == 50; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + assign R_en = 1'b1; + assign E_ci_result = 0; + //custom_instruction_master, which is an e_custom_instruction_master + assign no_ci_readra = 1'b0; + assign E_ci_multi_stall = 1'b0; + assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000100000; + assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 : + R_ctrl_break ? 2'b01 : + (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 : + 2'b11; + + assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : + (F_pc_sel_nxt == 2'b01)? 66056 : + (F_pc_sel_nxt == 2'b10)? E_arith_result[18 : 2] : + F_pc_plus_one; + + assign F_pc_nxt = F_pc_no_crst_nxt; + assign F_pcb_nxt = {F_pc_nxt, 2'b00}; + assign F_pc_en = W_valid; + assign F_pc_plus_one = F_pc + 1; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + F_pc <= 0; + else if (F_pc_en) + F_pc <= F_pc_nxt; + end + + + assign F_pcb = {F_pc, 2'b00}; + assign F_pcb_plus_four = {F_pc_plus_one, 2'b00}; + assign F_valid = i_read & ~i_waitrequest; + assign i_read_nxt = W_valid | (i_read & i_waitrequest); + assign i_address = {F_pc, 2'b00}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + i_read <= 1'b1; + else + i_read <= i_read_nxt; + end + + + assign oci_tb_hbreak_req = oci_hbreak_req; + assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid); + assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled + : hbreak_req; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + wait_for_one_post_bret_inst <= 1'b0; + else + wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_pending <= 1'b0; + else + hbreak_pending <= hbreak_pending_nxt; + end + + + assign intr_req = W_status_reg_pie & (W_ipending_reg != 0); + assign F_av_iw = i_readdata; + assign F_iw = hbreak_req ? 4040762 : + 1'b0 ? 127034 : + intr_req ? 3926074 : + F_av_iw; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_iw <= 0; + else if (F_valid) + D_iw <= F_iw; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + D_valid <= 0; + else + D_valid <= F_valid; + end + + + assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 : + D_ctrl_implicit_dst_eretaddr ? 5'd29 : + D_ctrl_b_is_dst ? D_iw_b : + D_iw_c; + + assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst; + assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw; + assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] : + D_iw_op[4 : 3]; + + assign D_jmp_direct_target_waddr = D_iw[31 : 6]; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_valid <= 0; + else + R_valid <= D_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_wr_dst_reg <= 0; + else + R_wr_dst_reg <= D_wr_dst_reg; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_dst_regnum <= 0; + else + R_dst_regnum <= D_dst_regnum; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_logic_op <= 0; + else + R_logic_op <= D_logic_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_compare_op <= 0; + else + R_compare_op <= D_compare_op; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_src2_use_imm <= 0; + else + R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid); + end + + + assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n; + assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data; +//nios_system_nios2_processor_register_bank_a, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_a_module nios_system_nios2_processor_register_bank_a + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_a), + .rdaddress (D_iw_a), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.dat"; +`else +defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_a.lpm_file = "nios_system_nios2_processor_rf_ram_a.mif"; +//synthesis read_comments_as_HDL off +//nios_system_nios2_processor_register_bank_b, which is an nios_sdp_ram +nios_system_nios2_processor_register_bank_b_module nios_system_nios2_processor_register_bank_b + ( + .clock (clk), + .data (W_rf_wr_data), + .q (R_rf_b), + .rdaddress (D_iw_b), + .wraddress (R_dst_regnum), + .wren (W_rf_wren) + ); + +//synthesis translate_off +`ifdef NO_PLI +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.dat"; +`else +defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.hex"; +`endif +//synthesis translate_on +//synthesis read_comments_as_HDL on +//defparam nios_system_nios2_processor_register_bank_b.lpm_file = "nios_system_nios2_processor_rf_ram_b.mif"; +//synthesis read_comments_as_HDL off + assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} : + ((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} : + R_rf_a; + + assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 : + (R_src2_use_imm)? D_iw_imm16 : + R_rf_b[15 : 0]; + + assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 : + (R_ctrl_hi_imm16)? D_iw_imm16 : + (R_src2_use_imm)? {16 {D_iw_imm16[15]}} : + R_rf_b[31 : 16]; + + assign R_src2 = {R_src2_hi, R_src2_lo}; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_valid <= 0; + else + E_valid <= R_valid | E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_new_inst <= 0; + else + E_new_inst <= R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src1 <= 0; + else + E_src1 <= R_src1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_src2 <= 0; + else + E_src2 <= R_src2; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_invert_arith_src_msb <= 0; + else + E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_alu_sub <= 0; + else + E_alu_sub <= D_ctrl_alu_subtract & R_valid; + end + + + assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall; + assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb, + E_src1[30 : 0]}; + + assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb, + E_src2[30 : 0]}; + + assign E_arith_result = E_alu_sub ? + E_arith_src1 - E_arith_src2 : + E_arith_src1 + E_arith_src2; + + assign E_mem_baddr = E_arith_result[18 : 0]; + assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : + (R_logic_op == 2'b01)? (E_src1 & E_src2) : + (R_logic_op == 2'b10)? (E_src1 | E_src2) : + (E_src1 ^ E_src2); + + assign E_logic_result_is_0 = E_logic_result == 0; + assign E_eq = E_logic_result_is_0; + assign E_lt = E_arith_result[32]; + assign E_cmp_result = (R_compare_op == 2'b00)? E_eq : + (R_compare_op == 2'b01)? ~E_lt : + (R_compare_op == 2'b10)? E_lt : + ~E_eq; + + assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1; + assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst; + assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done; + assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 : + (R_ctrl_rot_right ? E_shift_rot_result[0] : + E_shift_rot_result[31]); + + assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 : + (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} : + {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit}; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_result <= 0; + else + E_shift_rot_result <= E_shift_rot_result_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + E_shift_rot_cnt <= 0; + else + E_shift_rot_cnt <= E_shift_rot_cnt_nxt; + end + + + assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg : + (D_iw_control_regnum == 3'd1)? W_estatus_reg : + (D_iw_control_regnum == 3'd2)? W_bstatus_reg : + (D_iw_control_regnum == 3'd3)? W_ienable_reg : + (D_iw_control_regnum == 3'd4)? W_ipending_reg : + 0; + + assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 : + (R_ctrl_shift_rot)? E_shift_rot_result : + (R_ctrl_logic)? E_logic_result : + (R_ctrl_custom)? E_ci_result : + E_arith_result; + + assign R_stb_data = R_rf_b[7 : 0]; + assign R_sth_data = R_rf_b[15 : 0]; + assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} : + (D_mem16)? {R_sth_data, R_sth_data} : + R_rf_b; + + assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 : + ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 : + 4'b1111; + + assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest); + assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst); + assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest); + assign E_st_stall = d_write_nxt; + assign d_address = W_mem_baddr; + assign av_ld_getting_data = d_read & ~d_waitrequest; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_read <= 0; + else + d_read <= d_read_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_writedata <= 0; + else + d_writedata <= E_st_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_byteenable <= 0; + else + d_byteenable <= E_mem_byte_en; + end + + + assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1); + assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3); + assign av_ld_aligning_data_nxt = av_ld_aligning_data ? + ~av_ld_align_one_more_cycle : + (~D_mem32 & av_ld_getting_data); + + assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ? + ~av_ld_getting_data : + (R_ctrl_ld & E_new_inst); + + assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt); + assign av_ld_rshift8 = av_ld_aligning_data & + (av_ld_align_cycle < (W_mem_baddr[1 : 0])); + + assign av_ld_extend = av_ld_aligning_data; + assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data : + av_ld_extend ? av_ld_byte0_data : + d_readdata[7 : 0]; + + assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[15 : 8]; + + assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[23 : 16]; + + assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data : + av_ld_extend ? {8 {av_fill_bit}} : + d_readdata[31 : 24]; + + assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8); + assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data, + av_ld_byte1_data, av_ld_byte0_data}; + + assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7]; + assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_align_cycle <= 0; + else + av_ld_align_cycle <= av_ld_align_cycle_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_waiting_for_data <= 0; + else + av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_aligning_data <= 0; + else + av_ld_aligning_data <= av_ld_aligning_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte0_data <= 0; + else + av_ld_byte0_data <= av_ld_byte0_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte1_data <= 0; + else if (av_ld_byte1_data_en) + av_ld_byte1_data <= av_ld_byte1_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte2_data <= 0; + else + av_ld_byte2_data <= av_ld_byte2_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + av_ld_byte3_data <= 0; + else + av_ld_byte3_data <= av_ld_byte3_data_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_valid <= 0; + else + W_valid <= E_valid & ~E_stall; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_control_rd_data <= 0; + else + W_control_rd_data <= E_control_rd_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_cmp_result <= 0; + else + W_cmp_result <= E_cmp_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_alu_result <= 0; + else + W_alu_result <= E_alu_result; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_status_reg_pie <= 0; + else + W_status_reg_pie <= W_status_reg_pie_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_estatus_reg <= 0; + else + W_estatus_reg <= W_estatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_bstatus_reg <= 0; + else + W_bstatus_reg <= W_bstatus_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ienable_reg <= 0; + else + W_ienable_reg <= W_ienable_reg_nxt; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + W_ipending_reg <= 0; + else + W_ipending_reg <= W_ipending_reg_nxt; + end + + + assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result : + R_ctrl_rdctl_inst ? W_control_rd_data : + W_alu_result[31 : 0]; + + assign W_wr_data = W_wr_data_non_zero; + assign W_br_taken = R_ctrl_br & W_cmp_result; + assign W_mem_baddr = W_alu_result[18 : 0]; + assign W_status_reg = W_status_reg_pie; + assign E_wrctl_status = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd0); + + assign E_wrctl_estatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd1); + + assign E_wrctl_bstatus = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd2); + + assign E_wrctl_ienable = R_ctrl_wrctl_inst & + (D_iw_control_regnum == 3'd3); + + assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 : + (D_op_eret) ? W_estatus_reg : + (D_op_bret) ? W_bstatus_reg : + (E_wrctl_status) ? E_src1[0] : + W_status_reg_pie; + + assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie; + assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 : + (R_ctrl_exception) ? W_status_reg : + (E_wrctl_estatus) ? E_src1[0] : + W_estatus_reg; + + assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg; + assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg : + (E_wrctl_bstatus) ? E_src1[0] : + W_bstatus_reg; + + assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg; + assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ? + E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000100000; + + assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000100000; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + hbreak_enabled <= 1'b1; + else if (E_valid) + hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled; + end + + + nios_system_nios2_processor_nios2_oci the_nios_system_nios2_processor_nios2_oci + ( + .D_valid (D_valid), + .E_st_data (E_st_data), + .E_valid (E_valid), + .F_pc (F_pc), + .address_nxt (jtag_debug_module_address), + .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered), + .byteenable_nxt (jtag_debug_module_byteenable), + .clk (jtag_debug_module_clk), + .d_address (d_address), + .d_read (d_read), + .d_waitrequest (d_waitrequest), + .d_write (d_write), + .debugaccess_nxt (jtag_debug_module_debugaccess), + .hbreak_enabled (hbreak_enabled), + .jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms), + .oci_hbreak_req (oci_hbreak_req), + .oci_ienable (oci_ienable), + .oci_single_step_mode (oci_single_step_mode), + .read_nxt (jtag_debug_module_read), + .readdata (jtag_debug_module_readdata), + .reset (jtag_debug_module_reset), + .reset_n (reset_n), + .resetrequest (jtag_debug_module_resetrequest), + .test_ending (test_ending), + .test_has_ended (test_has_ended), + .waitrequest (jtag_debug_module_waitrequest), + .write_nxt (jtag_debug_module_write), + .writedata_nxt (jtag_debug_module_writedata) + ); + + //jtag_debug_module, which is an e_avalon_slave + assign jtag_debug_module_clk = clk; + assign jtag_debug_module_reset = ~reset_n; + assign D_ctrl_custom = 1'b0; + assign R_ctrl_custom_nxt = D_ctrl_custom; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom <= 0; + else if (R_en) + R_ctrl_custom <= R_ctrl_custom_nxt; + end + + + assign D_ctrl_custom_multi = 1'b0; + assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_custom_multi <= 0; + else if (R_en) + R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt; + end + + + assign D_ctrl_jmp_indirect = D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_indirect <= 0; + else if (R_en) + R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt; + end + + + assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi; + assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_jmp_direct <= 0; + else if (R_en) + R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt; + end + + + assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02; + assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_retaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt; + end + + + assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu; + assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_implicit_dst_eretaddr <= 0; + else if (R_en) + R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt; + end + + + assign D_ctrl_exception = D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60; + + assign R_ctrl_exception_nxt = D_ctrl_exception; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_exception <= 0; + else if (R_en) + R_ctrl_exception <= R_ctrl_exception_nxt; + end + + + assign D_ctrl_break = D_op_break|D_op_hbreak; + assign R_ctrl_break_nxt = D_ctrl_break; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_break <= 0; + else if (R_en) + R_ctrl_break <= R_ctrl_break_nxt; + end + + + assign D_ctrl_crst = D_op_crst|D_op_rsvx63; + assign R_ctrl_crst_nxt = D_ctrl_crst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_crst <= 0; + else if (R_en) + R_ctrl_crst <= R_ctrl_crst_nxt; + end + + + assign D_ctrl_uncond_cti_non_br = D_op_call| + D_op_jmpi| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_callr; + + assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_uncond_cti_non_br <= 0; + else if (R_en) + R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt; + end + + + assign D_ctrl_retaddr = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_div| + D_op_divu| + D_op_mul| + D_op_muli| + D_op_mulxss| + D_op_mulxsu| + D_op_mulxuu| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak; + + assign R_ctrl_retaddr_nxt = D_ctrl_retaddr; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_retaddr <= 0; + else if (R_en) + R_ctrl_retaddr <= R_ctrl_retaddr_nxt; + end + + + assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl; + assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_logical <= 0; + else if (R_en) + R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt; + end + + + assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra; + assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_right_arith <= 0; + else if (R_en) + R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt; + end + + + assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43; + assign R_ctrl_rot_right_nxt = D_ctrl_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rot_right <= 0; + else if (R_en) + R_ctrl_rot_right <= R_ctrl_rot_right_nxt; + end + + + assign D_ctrl_shift_rot_right = D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot_right <= 0; + else if (R_en) + R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt; + end + + + assign D_ctrl_shift_rot = D_op_slli| + D_op_rsvx50| + D_op_sll| + D_op_rsvx51| + D_op_roli| + D_op_rsvx34| + D_op_rol| + D_op_rsvx35| + D_op_srli| + D_op_srl| + D_op_srai| + D_op_sra| + D_op_rsvx10| + D_op_ror| + D_op_rsvx42| + D_op_rsvx43; + + assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_shift_rot <= 0; + else if (R_en) + R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt; + end + + + assign D_ctrl_logic = D_op_and| + D_op_or| + D_op_xor| + D_op_nor| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori; + + assign R_ctrl_logic_nxt = D_ctrl_logic; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_logic <= 0; + else if (R_en) + R_ctrl_logic <= R_ctrl_logic_nxt; + end + + + assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi; + assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_hi_imm16 <= 0; + else if (R_en) + R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt; + end + + + assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui| + D_op_cmpltui| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_unsigned_lo_imm16 <= 0; + else if (R_en) + R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt; + end + + + assign D_ctrl_br_uncond = D_op_br|D_op_rsv02; + assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_uncond <= 0; + else if (R_en) + R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt; + end + + + assign D_ctrl_br = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62; + + assign R_ctrl_br_nxt = D_ctrl_br; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br <= 0; + else if (R_en) + R_ctrl_br <= R_ctrl_br_nxt; + end + + + assign D_ctrl_alu_subtract = D_op_sub| + D_op_rsvx25| + D_op_cmplti| + D_op_cmpltui| + D_op_cmplt| + D_op_cmpltu| + D_op_blt| + D_op_bltu| + D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpge| + D_op_cmpgeu| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42; + + assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_subtract <= 0; + else if (R_en) + R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt; + end + + + assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt; + assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_signed_comparison <= 0; + else if (R_en) + R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt; + end + + + assign D_ctrl_br_cmp = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_rsvx00| + D_op_cmpge| + D_op_cmplt| + D_op_cmpne| + D_op_cmpgeu| + D_op_cmpltu| + D_op_cmpeq| + D_op_rsvx56; + + assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_br_cmp <= 0; + else if (R_en) + R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt; + end + + + assign D_ctrl_ld_signed = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63; + + assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_signed <= 0; + else if (R_en) + R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt; + end + + + assign D_ctrl_ld = D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio; + + assign R_ctrl_ld_nxt = D_ctrl_ld; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld <= 0; + else if (R_en) + R_ctrl_ld <= R_ctrl_ld_nxt; + end + + + assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl; + assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_non_io <= 0; + else if (R_en) + R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt; + end + + + assign D_ctrl_st = D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61; + + assign R_ctrl_st_nxt = D_ctrl_st; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_st <= 0; + else if (R_en) + R_ctrl_st <= R_ctrl_st_nxt; + end + + + assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63; + assign R_ctrl_ld_io_nxt = D_ctrl_ld_io; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ld_io <= 0; + else if (R_en) + R_ctrl_ld_io <= R_ctrl_ld_io_nxt; + end + + + assign D_ctrl_b_is_dst = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda; + + assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_b_is_dst <= 0; + else if (R_en) + R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt; + end + + + assign D_ctrl_ignore_dst = D_op_br| + D_op_bge| + D_op_blt| + D_op_bne| + D_op_beq| + D_op_bgeu| + D_op_bltu| + D_op_rsv62| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57; + + assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_ignore_dst <= 0; + else if (R_en) + R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt; + end + + + assign D_ctrl_src2_choose_imm = D_op_addi| + D_op_andhi| + D_op_orhi| + D_op_xorhi| + D_op_andi| + D_op_ori| + D_op_xori| + D_op_call| + D_op_rdprs| + D_op_cmpgei| + D_op_cmplti| + D_op_cmpnei| + D_op_cmpgeui| + D_op_cmpltui| + D_op_cmpeqi| + D_op_jmpi| + D_op_rsv09| + D_op_rsv17| + D_op_rsv25| + D_op_rsv33| + D_op_rsv41| + D_op_rsv49| + D_op_rsv57| + D_op_ldb| + D_op_ldh| + D_op_ldl| + D_op_ldw| + D_op_ldbio| + D_op_ldhio| + D_op_ldwio| + D_op_rsv63| + D_op_ldbu| + D_op_ldhu| + D_op_ldbuio| + D_op_ldhuio| + D_op_initd| + D_op_initda| + D_op_flushd| + D_op_flushda| + D_op_stb| + D_op_sth| + D_op_stw| + D_op_stc| + D_op_stbio| + D_op_sthio| + D_op_stwio| + D_op_rsv61| + D_op_roli| + D_op_rsvx10| + D_op_slli| + D_op_srli| + D_op_rsvx34| + D_op_rsvx42| + D_op_rsvx50| + D_op_srai; + + assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_src2_choose_imm <= 0; + else if (R_en) + R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt; + end + + + assign D_ctrl_wrctl_inst = D_op_wrctl; + assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_wrctl_inst <= 0; + else if (R_en) + R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt; + end + + + assign D_ctrl_rdctl_inst = D_op_rdctl; + assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_rdctl_inst <= 0; + else if (R_en) + R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt; + end + + + assign D_ctrl_force_src2_zero = D_op_call| + D_op_rsv02| + D_op_nextpc| + D_op_callr| + D_op_trap| + D_op_rsvx44| + D_op_intr| + D_op_rsvx60| + D_op_break| + D_op_hbreak| + D_op_eret| + D_op_bret| + D_op_rsvx17| + D_op_rsvx25| + D_op_ret| + D_op_jmp| + D_op_rsvx21| + D_op_jmpi; + + assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_force_src2_zero <= 0; + else if (R_en) + R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt; + end + + + assign D_ctrl_alu_force_xor = D_op_cmpgei| + D_op_cmpgeui| + D_op_cmpeqi| + D_op_cmpge| + D_op_cmpgeu| + D_op_cmpeq| + D_op_cmpnei| + D_op_cmpne| + D_op_bge| + D_op_rsv10| + D_op_bgeu| + D_op_rsv42| + D_op_beq| + D_op_rsv34| + D_op_bne| + D_op_rsv62| + D_op_br| + D_op_rsv02; + + assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + R_ctrl_alu_force_xor <= 0; + else if (R_en) + R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt; + end + + + //data_master, which is an e_avalon_master + //instruction_master, which is an e_avalon_master + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign F_inst = (F_op_call)? 56'h20202063616c6c : + (F_op_jmpi)? 56'h2020206a6d7069 : + (F_op_ldbu)? 56'h2020206c646275 : + (F_op_addi)? 56'h20202061646469 : + (F_op_stb)? 56'h20202020737462 : + (F_op_br)? 56'h20202020206272 : + (F_op_ldb)? 56'h202020206c6462 : + (F_op_cmpgei)? 56'h20636d70676569 : + (F_op_ldhu)? 56'h2020206c646875 : + (F_op_andi)? 56'h202020616e6469 : + (F_op_sth)? 56'h20202020737468 : + (F_op_bge)? 56'h20202020626765 : + (F_op_ldh)? 56'h202020206c6468 : + (F_op_cmplti)? 56'h20636d706c7469 : + (F_op_initda)? 56'h20696e69746461 : + (F_op_ori)? 56'h202020206f7269 : + (F_op_stw)? 56'h20202020737477 : + (F_op_blt)? 56'h20202020626c74 : + (F_op_ldw)? 56'h202020206c6477 : + (F_op_cmpnei)? 56'h20636d706e6569 : + (F_op_flushda)? 56'h666c7573686461 : + (F_op_xori)? 56'h202020786f7269 : + (F_op_bne)? 56'h20202020626e65 : + (F_op_cmpeqi)? 56'h20636d70657169 : + (F_op_ldbuio)? 56'h206c646275696f : + (F_op_muli)? 56'h2020206d756c69 : + (F_op_stbio)? 56'h2020737462696f : + (F_op_beq)? 56'h20202020626571 : + (F_op_ldbio)? 56'h20206c6462696f : + (F_op_cmpgeui)? 56'h636d7067657569 : + (F_op_ldhuio)? 56'h206c646875696f : + (F_op_andhi)? 56'h2020616e646869 : + (F_op_sthio)? 56'h2020737468696f : + (F_op_bgeu)? 56'h20202062676575 : + (F_op_ldhio)? 56'h20206c6468696f : + (F_op_cmpltui)? 56'h636d706c747569 : + (F_op_initd)? 56'h2020696e697464 : + (F_op_orhi)? 56'h2020206f726869 : + (F_op_stwio)? 56'h2020737477696f : + (F_op_bltu)? 56'h202020626c7475 : + (F_op_ldwio)? 56'h20206c6477696f : + (F_op_flushd)? 56'h20666c75736864 : + (F_op_xorhi)? 56'h2020786f726869 : + (F_op_eret)? 56'h20202065726574 : + (F_op_roli)? 56'h202020726f6c69 : + (F_op_rol)? 56'h20202020726f6c : + (F_op_flushp)? 56'h20666c75736870 : + (F_op_ret)? 56'h20202020726574 : + (F_op_nor)? 56'h202020206e6f72 : + (F_op_mulxuu)? 56'h206d756c787575 : + (F_op_cmpge)? 56'h2020636d706765 : + (F_op_bret)? 56'h20202062726574 : + (F_op_ror)? 56'h20202020726f72 : + (F_op_flushi)? 56'h20666c75736869 : + (F_op_jmp)? 56'h202020206a6d70 : + (F_op_and)? 56'h20202020616e64 : + (F_op_cmplt)? 56'h2020636d706c74 : + (F_op_slli)? 56'h202020736c6c69 : + (F_op_sll)? 56'h20202020736c6c : + (F_op_or)? 56'h20202020206f72 : + (F_op_mulxsu)? 56'h206d756c787375 : + (F_op_cmpne)? 56'h2020636d706e65 : + (F_op_srli)? 56'h20202073726c69 : + (F_op_srl)? 56'h2020202073726c : + (F_op_nextpc)? 56'h206e6578747063 : + (F_op_callr)? 56'h202063616c6c72 : + (F_op_xor)? 56'h20202020786f72 : + (F_op_mulxss)? 56'h206d756c787373 : + (F_op_cmpeq)? 56'h2020636d706571 : + (F_op_divu)? 56'h20202064697675 : + (F_op_div)? 56'h20202020646976 : + (F_op_rdctl)? 56'h2020726463746c : + (F_op_mul)? 56'h202020206d756c : + (F_op_cmpgeu)? 56'h20636d70676575 : + (F_op_initi)? 56'h2020696e697469 : + (F_op_trap)? 56'h20202074726170 : + (F_op_wrctl)? 56'h2020777263746c : + (F_op_cmpltu)? 56'h20636d706c7475 : + (F_op_add)? 56'h20202020616464 : + (F_op_break)? 56'h2020627265616b : + (F_op_hbreak)? 56'h2068627265616b : + (F_op_sync)? 56'h20202073796e63 : + (F_op_sub)? 56'h20202020737562 : + (F_op_srai)? 56'h20202073726169 : + (F_op_sra)? 56'h20202020737261 : + (F_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign D_inst = (D_op_call)? 56'h20202063616c6c : + (D_op_jmpi)? 56'h2020206a6d7069 : + (D_op_ldbu)? 56'h2020206c646275 : + (D_op_addi)? 56'h20202061646469 : + (D_op_stb)? 56'h20202020737462 : + (D_op_br)? 56'h20202020206272 : + (D_op_ldb)? 56'h202020206c6462 : + (D_op_cmpgei)? 56'h20636d70676569 : + (D_op_ldhu)? 56'h2020206c646875 : + (D_op_andi)? 56'h202020616e6469 : + (D_op_sth)? 56'h20202020737468 : + (D_op_bge)? 56'h20202020626765 : + (D_op_ldh)? 56'h202020206c6468 : + (D_op_cmplti)? 56'h20636d706c7469 : + (D_op_initda)? 56'h20696e69746461 : + (D_op_ori)? 56'h202020206f7269 : + (D_op_stw)? 56'h20202020737477 : + (D_op_blt)? 56'h20202020626c74 : + (D_op_ldw)? 56'h202020206c6477 : + (D_op_cmpnei)? 56'h20636d706e6569 : + (D_op_flushda)? 56'h666c7573686461 : + (D_op_xori)? 56'h202020786f7269 : + (D_op_bne)? 56'h20202020626e65 : + (D_op_cmpeqi)? 56'h20636d70657169 : + (D_op_ldbuio)? 56'h206c646275696f : + (D_op_muli)? 56'h2020206d756c69 : + (D_op_stbio)? 56'h2020737462696f : + (D_op_beq)? 56'h20202020626571 : + (D_op_ldbio)? 56'h20206c6462696f : + (D_op_cmpgeui)? 56'h636d7067657569 : + (D_op_ldhuio)? 56'h206c646875696f : + (D_op_andhi)? 56'h2020616e646869 : + (D_op_sthio)? 56'h2020737468696f : + (D_op_bgeu)? 56'h20202062676575 : + (D_op_ldhio)? 56'h20206c6468696f : + (D_op_cmpltui)? 56'h636d706c747569 : + (D_op_initd)? 56'h2020696e697464 : + (D_op_orhi)? 56'h2020206f726869 : + (D_op_stwio)? 56'h2020737477696f : + (D_op_bltu)? 56'h202020626c7475 : + (D_op_ldwio)? 56'h20206c6477696f : + (D_op_flushd)? 56'h20666c75736864 : + (D_op_xorhi)? 56'h2020786f726869 : + (D_op_eret)? 56'h20202065726574 : + (D_op_roli)? 56'h202020726f6c69 : + (D_op_rol)? 56'h20202020726f6c : + (D_op_flushp)? 56'h20666c75736870 : + (D_op_ret)? 56'h20202020726574 : + (D_op_nor)? 56'h202020206e6f72 : + (D_op_mulxuu)? 56'h206d756c787575 : + (D_op_cmpge)? 56'h2020636d706765 : + (D_op_bret)? 56'h20202062726574 : + (D_op_ror)? 56'h20202020726f72 : + (D_op_flushi)? 56'h20666c75736869 : + (D_op_jmp)? 56'h202020206a6d70 : + (D_op_and)? 56'h20202020616e64 : + (D_op_cmplt)? 56'h2020636d706c74 : + (D_op_slli)? 56'h202020736c6c69 : + (D_op_sll)? 56'h20202020736c6c : + (D_op_or)? 56'h20202020206f72 : + (D_op_mulxsu)? 56'h206d756c787375 : + (D_op_cmpne)? 56'h2020636d706e65 : + (D_op_srli)? 56'h20202073726c69 : + (D_op_srl)? 56'h2020202073726c : + (D_op_nextpc)? 56'h206e6578747063 : + (D_op_callr)? 56'h202063616c6c72 : + (D_op_xor)? 56'h20202020786f72 : + (D_op_mulxss)? 56'h206d756c787373 : + (D_op_cmpeq)? 56'h2020636d706571 : + (D_op_divu)? 56'h20202064697675 : + (D_op_div)? 56'h20202020646976 : + (D_op_rdctl)? 56'h2020726463746c : + (D_op_mul)? 56'h202020206d756c : + (D_op_cmpgeu)? 56'h20636d70676575 : + (D_op_initi)? 56'h2020696e697469 : + (D_op_trap)? 56'h20202074726170 : + (D_op_wrctl)? 56'h2020777263746c : + (D_op_cmpltu)? 56'h20636d706c7475 : + (D_op_add)? 56'h20202020616464 : + (D_op_break)? 56'h2020627265616b : + (D_op_hbreak)? 56'h2068627265616b : + (D_op_sync)? 56'h20202073796e63 : + (D_op_sub)? 56'h20202020737562 : + (D_op_srai)? 56'h20202073726169 : + (D_op_sra)? 56'h20202020737261 : + (D_op_intr)? 56'h202020696e7472 : + 56'h20202020424144; + + assign F_vinst = F_valid ? F_inst : {7{8'h2d}}; + assign D_vinst = D_valid ? D_inst : {7{8'h2d}}; + assign R_vinst = R_valid ? D_inst : {7{8'h2d}}; + assign E_vinst = E_valid ? D_inst : {7{8'h2d}}; + assign W_vinst = W_valid ? D_inst : {7{8'h2d}}; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v index 7eead98..7daaec7 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v @@ -1,181 +1,181 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_sysclk ( - // inputs: - clk, - ir_in, - sr, - vs_udr, - vs_uir, - - // outputs: - jdo, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input clk; - input [ 1: 0] ir_in; - input [ 37: 0] sr; - input vs_udr; - input vs_uir; - - reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; - reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - wire sync_udr; - wire sync_uir; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire unxunused_resetxx3; - wire unxunused_resetxx4; - reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; - assign unxunused_resetxx3 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer3 - ( - .clk (clk), - .din (vs_udr), - .dout (sync_udr), - .reset_n (unxunused_resetxx3) - ); - - defparam the_altera_std_synchronizer3.depth = 2; - - assign unxunused_resetxx4 = 1'b1; - altera_std_synchronizer the_altera_std_synchronizer4 - ( - .clk (clk), - .din (vs_uir), - .dout (sync_uir), - .reset_n (unxunused_resetxx4) - ); - - defparam the_altera_std_synchronizer4.depth = 2; - - always @(posedge clk) - begin - sync2_udr <= sync_udr; - update_jdo_strobe <= sync_udr & ~sync2_udr; - enable_action_strobe <= update_jdo_strobe; - sync2_uir <= sync_uir; - jxuir <= sync_uir & ~sync2_uir; - end - - - assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && jdo[34]; - - assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && - ~jdo[35] && ~jdo[34]; - - assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && - jdo[35]; - - assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - jdo[36]; - - assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && - ~jdo[37] && - ~jdo[36]; - - assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && - jdo[37]; - - assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - jdo[37]; - - assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && - ~jdo[36] && - ~jdo[37]; - - assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - jdo[37]; - - assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && - jdo[36] && ~jdo[35] && - ~jdo[37]; - - assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - jdo[37]; - - assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && - jdo[36] && jdo[35] && - ~jdo[37]; - - assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && - jdo[15]; - - always @(posedge clk) - begin - if (jxuir) - ir <= ir_in; - if (update_jdo_strobe) - jdo <= sr; - end - - - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_sysclk ( + // inputs: + clk, + ir_in, + sr, + vs_udr, + vs_uir, + + // outputs: + jdo, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input clk; + input [ 1: 0] ir_in; + input [ 37: 0] sr; + input vs_udr; + input vs_uir; + + reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + wire sync_udr; + wire sync_uir; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire unxunused_resetxx3; + wire unxunused_resetxx4; + reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + assign unxunused_resetxx3 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer3 + ( + .clk (clk), + .din (vs_udr), + .dout (sync_udr), + .reset_n (unxunused_resetxx3) + ); + + defparam the_altera_std_synchronizer3.depth = 2; + + assign unxunused_resetxx4 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer4 + ( + .clk (clk), + .din (vs_uir), + .dout (sync_uir), + .reset_n (unxunused_resetxx4) + ); + + defparam the_altera_std_synchronizer4.depth = 2; + + always @(posedge clk) + begin + sync2_udr <= sync_udr; + update_jdo_strobe <= sync_udr & ~sync2_udr; + enable_action_strobe <= update_jdo_strobe; + sync2_uir <= sync_uir; + jxuir <= sync_uir & ~sync2_uir; + end + + + assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && jdo[34]; + + assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && ~jdo[34]; + + assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && + jdo[35]; + + assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + jdo[36]; + + assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + ~jdo[36]; + + assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && + jdo[37]; + + assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + jdo[37]; + + assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + ~jdo[37]; + + assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + jdo[37]; + + assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + ~jdo[37]; + + assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + jdo[37]; + + assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + ~jdo[37]; + + assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && + jdo[15]; + + always @(posedge clk) + begin + if (jxuir) + ir <= ir_in; + if (update_jdo_strobe) + jdo <= sr; + end + + + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v index 09289db..8e3a593 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v @@ -1,239 +1,239 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_tck ( - // inputs: - MonDReg, - break_readreg, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - ir_in, - jtag_state_rti, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tck, - tdi, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - vs_cdr, - vs_sdr, - vs_uir, - - // outputs: - ir_out, - jrst_n, - sr, - st_ready_test_idle, - tdo - ) -; - - output [ 1: 0] ir_out; - output jrst_n; - output [ 37: 0] sr; - output st_ready_test_idle; - output tdo; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input [ 1: 0] ir_in; - input jtag_state_rti; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tck; - input tdi; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - input vs_cdr; - input vs_sdr; - input vs_uir; - - reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire debugack_sync; - reg [ 1: 0] ir_out; - wire jrst_n; - wire monitor_ready_sync; - reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; - wire st_ready_test_idle; - wire tdo; - wire unxcomplemented_resetxx1; - wire unxcomplemented_resetxx2; - always @(posedge tck) - begin - if (vs_cdr) - case (ir_in) - - 2'b00: begin - sr[35] <= debugack_sync; - sr[34] <= monitor_error; - sr[33] <= resetlatch; - sr[32 : 1] <= MonDReg; - sr[0] <= monitor_ready_sync; - end // 2'b00 - - 2'b01: begin - sr[35 : 0] <= tracemem_trcdata; - sr[37] <= tracemem_tw; - sr[36] <= tracemem_on; - end // 2'b01 - - 2'b10: begin - sr[37] <= trigger_state_1; - sr[36] <= dbrk_hit3_latch; - sr[35] <= dbrk_hit2_latch; - sr[34] <= dbrk_hit1_latch; - sr[33] <= dbrk_hit0_latch; - sr[32 : 1] <= break_readreg; - sr[0] <= trigbrktype; - end // 2'b10 - - 2'b11: begin - sr[15 : 12] <= 1'b0; - sr[11 : 2] <= trc_im_addr; - sr[1] <= trc_wrap; - sr[0] <= trc_on; - end // 2'b11 - - endcase // ir_in - if (vs_sdr) - case (DRsize) - - 3'b000: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // 3'b000 - - 3'b001: begin - sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; - end // 3'b001 - - 3'b010: begin - sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; - end // 3'b010 - - 3'b011: begin - sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; - end // 3'b011 - - 3'b100: begin - sr <= {tdi, sr[37], tdi, sr[35 : 1]}; - end // 3'b100 - - 3'b101: begin - sr <= {tdi, sr[37 : 1]}; - end // 3'b101 - - default: begin - sr <= {tdi, sr[37 : 2], tdi}; - end // default - - endcase // DRsize - if (vs_uir) - case (ir_in) - - 2'b00: begin - DRsize <= 3'b100; - end // 2'b00 - - 2'b01: begin - DRsize <= 3'b101; - end // 2'b01 - - 2'b10: begin - DRsize <= 3'b101; - end // 2'b10 - - 2'b11: begin - DRsize <= 3'b010; - end // 2'b11 - - endcase // ir_in - end - - - assign tdo = sr[0]; - assign st_ready_test_idle = jtag_state_rti; - assign unxcomplemented_resetxx1 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer1 - ( - .clk (tck), - .din (debugack), - .dout (debugack_sync), - .reset_n (unxcomplemented_resetxx1) - ); - - defparam the_altera_std_synchronizer1.depth = 2; - - assign unxcomplemented_resetxx2 = jrst_n; - altera_std_synchronizer the_altera_std_synchronizer2 - ( - .clk (tck), - .din (monitor_ready), - .dout (monitor_ready_sync), - .reset_n (unxcomplemented_resetxx2) - ); - - defparam the_altera_std_synchronizer2.depth = 2; - - always @(posedge tck or negedge jrst_n) - begin - if (jrst_n == 0) - ir_out <= 2'b0; - else - ir_out <= {debugack_sync, monitor_ready_sync}; - end - - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign jrst_n = reset_n; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// assign jrst_n = 1; -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_tck ( + // inputs: + MonDReg, + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + ir_in, + jtag_state_rti, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tck, + tdi, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + vs_cdr, + vs_sdr, + vs_uir, + + // outputs: + ir_out, + jrst_n, + sr, + st_ready_test_idle, + tdo + ) +; + + output [ 1: 0] ir_out; + output jrst_n; + output [ 37: 0] sr; + output st_ready_test_idle; + output tdo; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input [ 1: 0] ir_in; + input jtag_state_rti; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tck; + input tdi; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + input vs_cdr; + input vs_sdr; + input vs_uir; + + reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire debugack_sync; + reg [ 1: 0] ir_out; + wire jrst_n; + wire monitor_ready_sync; + reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire st_ready_test_idle; + wire tdo; + wire unxcomplemented_resetxx1; + wire unxcomplemented_resetxx2; + always @(posedge tck) + begin + if (vs_cdr) + case (ir_in) + + 2'b00: begin + sr[35] <= debugack_sync; + sr[34] <= monitor_error; + sr[33] <= resetlatch; + sr[32 : 1] <= MonDReg; + sr[0] <= monitor_ready_sync; + end // 2'b00 + + 2'b01: begin + sr[35 : 0] <= tracemem_trcdata; + sr[37] <= tracemem_tw; + sr[36] <= tracemem_on; + end // 2'b01 + + 2'b10: begin + sr[37] <= trigger_state_1; + sr[36] <= dbrk_hit3_latch; + sr[35] <= dbrk_hit2_latch; + sr[34] <= dbrk_hit1_latch; + sr[33] <= dbrk_hit0_latch; + sr[32 : 1] <= break_readreg; + sr[0] <= trigbrktype; + end // 2'b10 + + 2'b11: begin + sr[15 : 12] <= 1'b0; + sr[11 : 2] <= trc_im_addr; + sr[1] <= trc_wrap; + sr[0] <= trc_on; + end // 2'b11 + + endcase // ir_in + if (vs_sdr) + case (DRsize) + + 3'b000: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // 3'b000 + + 3'b001: begin + sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; + end // 3'b001 + + 3'b010: begin + sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; + end // 3'b010 + + 3'b011: begin + sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; + end // 3'b011 + + 3'b100: begin + sr <= {tdi, sr[37], tdi, sr[35 : 1]}; + end // 3'b100 + + 3'b101: begin + sr <= {tdi, sr[37 : 1]}; + end // 3'b101 + + default: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // default + + endcase // DRsize + if (vs_uir) + case (ir_in) + + 2'b00: begin + DRsize <= 3'b100; + end // 2'b00 + + 2'b01: begin + DRsize <= 3'b101; + end // 2'b01 + + 2'b10: begin + DRsize <= 3'b101; + end // 2'b10 + + 2'b11: begin + DRsize <= 3'b010; + end // 2'b11 + + endcase // ir_in + end + + + assign tdo = sr[0]; + assign st_ready_test_idle = jtag_state_rti; + assign unxcomplemented_resetxx1 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer1 + ( + .clk (tck), + .din (debugack), + .dout (debugack_sync), + .reset_n (unxcomplemented_resetxx1) + ); + + defparam the_altera_std_synchronizer1.depth = 2; + + assign unxcomplemented_resetxx2 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer2 + ( + .clk (tck), + .din (monitor_ready), + .dout (monitor_ready_sync), + .reset_n (unxcomplemented_resetxx2) + ); + + defparam the_altera_std_synchronizer2.depth = 2; + + always @(posedge tck or negedge jrst_n) + begin + if (jrst_n == 0) + ir_out <= 2'b0; + else + ir_out <= {debugack_sync, monitor_ready_sync}; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign jrst_n = reset_n; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// assign jrst_n = 1; +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v index 6a57330..1fd5cb7 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v @@ -1,233 +1,233 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_jtag_debug_module_wrapper ( - // inputs: - MonDReg, - break_readreg, - clk, - dbrk_hit0_latch, - dbrk_hit1_latch, - dbrk_hit2_latch, - dbrk_hit3_latch, - debugack, - monitor_error, - monitor_ready, - reset_n, - resetlatch, - tracemem_on, - tracemem_trcdata, - tracemem_tw, - trc_im_addr, - trc_on, - trc_wrap, - trigbrktype, - trigger_state_1, - - // outputs: - jdo, - jrst_n, - st_ready_test_idle, - take_action_break_a, - take_action_break_b, - take_action_break_c, - take_action_ocimem_a, - take_action_ocimem_b, - take_action_tracectrl, - take_action_tracemem_a, - take_action_tracemem_b, - take_no_action_break_a, - take_no_action_break_b, - take_no_action_break_c, - take_no_action_ocimem_a, - take_no_action_tracemem_a - ) -; - - output [ 37: 0] jdo; - output jrst_n; - output st_ready_test_idle; - output take_action_break_a; - output take_action_break_b; - output take_action_break_c; - output take_action_ocimem_a; - output take_action_ocimem_b; - output take_action_tracectrl; - output take_action_tracemem_a; - output take_action_tracemem_b; - output take_no_action_break_a; - output take_no_action_break_b; - output take_no_action_break_c; - output take_no_action_ocimem_a; - output take_no_action_tracemem_a; - input [ 31: 0] MonDReg; - input [ 31: 0] break_readreg; - input clk; - input dbrk_hit0_latch; - input dbrk_hit1_latch; - input dbrk_hit2_latch; - input dbrk_hit3_latch; - input debugack; - input monitor_error; - input monitor_ready; - input reset_n; - input resetlatch; - input tracemem_on; - input [ 35: 0] tracemem_trcdata; - input tracemem_tw; - input [ 6: 0] trc_im_addr; - input trc_on; - input trc_wrap; - input trigbrktype; - input trigger_state_1; - - wire [ 37: 0] jdo; - wire jrst_n; - wire [ 37: 0] sr; - wire st_ready_test_idle; - wire take_action_break_a; - wire take_action_break_b; - wire take_action_break_c; - wire take_action_ocimem_a; - wire take_action_ocimem_b; - wire take_action_tracectrl; - wire take_action_tracemem_a; - wire take_action_tracemem_b; - wire take_no_action_break_a; - wire take_no_action_break_b; - wire take_no_action_break_c; - wire take_no_action_ocimem_a; - wire take_no_action_tracemem_a; - wire vji_cdr; - wire [ 1: 0] vji_ir_in; - wire [ 1: 0] vji_ir_out; - wire vji_rti; - wire vji_sdr; - wire vji_tck; - wire vji_tdi; - wire vji_tdo; - wire vji_udr; - wire vji_uir; - //Change the sld_virtual_jtag_basic's defparams to - //switch between a regular Nios II or an internally embedded Nios II. - //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. - //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. - nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck - ( - .MonDReg (MonDReg), - .break_readreg (break_readreg), - .dbrk_hit0_latch (dbrk_hit0_latch), - .dbrk_hit1_latch (dbrk_hit1_latch), - .dbrk_hit2_latch (dbrk_hit2_latch), - .dbrk_hit3_latch (dbrk_hit3_latch), - .debugack (debugack), - .ir_in (vji_ir_in), - .ir_out (vji_ir_out), - .jrst_n (jrst_n), - .jtag_state_rti (vji_rti), - .monitor_error (monitor_error), - .monitor_ready (monitor_ready), - .reset_n (reset_n), - .resetlatch (resetlatch), - .sr (sr), - .st_ready_test_idle (st_ready_test_idle), - .tck (vji_tck), - .tdi (vji_tdi), - .tdo (vji_tdo), - .tracemem_on (tracemem_on), - .tracemem_trcdata (tracemem_trcdata), - .tracemem_tw (tracemem_tw), - .trc_im_addr (trc_im_addr), - .trc_on (trc_on), - .trc_wrap (trc_wrap), - .trigbrktype (trigbrktype), - .trigger_state_1 (trigger_state_1), - .vs_cdr (vji_cdr), - .vs_sdr (vji_sdr), - .vs_uir (vji_uir) - ); - - nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk - ( - .clk (clk), - .ir_in (vji_ir_in), - .jdo (jdo), - .sr (sr), - .take_action_break_a (take_action_break_a), - .take_action_break_b (take_action_break_b), - .take_action_break_c (take_action_break_c), - .take_action_ocimem_a (take_action_ocimem_a), - .take_action_ocimem_b (take_action_ocimem_b), - .take_action_tracectrl (take_action_tracectrl), - .take_action_tracemem_a (take_action_tracemem_a), - .take_action_tracemem_b (take_action_tracemem_b), - .take_no_action_break_a (take_no_action_break_a), - .take_no_action_break_b (take_no_action_break_b), - .take_no_action_break_c (take_no_action_break_c), - .take_no_action_ocimem_a (take_no_action_ocimem_a), - .take_no_action_tracemem_a (take_no_action_tracemem_a), - .vs_udr (vji_udr), - .vs_uir (vji_uir) - ); - - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - assign vji_tck = 1'b0; - assign vji_tdi = 1'b0; - assign vji_sdr = 1'b0; - assign vji_cdr = 1'b0; - assign vji_rti = 1'b0; - assign vji_uir = 1'b0; - assign vji_udr = 1'b0; - assign vji_ir_in = 2'b0; - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy -// ( -// .ir_in (vji_ir_in), -// .ir_out (vji_ir_out), -// .jtag_state_rti (vji_rti), -// .tck (vji_tck), -// .tdi (vji_tdi), -// .tdo (vji_tdo), -// .virtual_state_cdr (vji_cdr), -// .virtual_state_sdr (vji_sdr), -// .virtual_state_udr (vji_udr), -// .virtual_state_uir (vji_uir) -// ); -// -// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, -// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; -// -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_jtag_debug_module_wrapper ( + // inputs: + MonDReg, + break_readreg, + clk, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + + // outputs: + jdo, + jrst_n, + st_ready_test_idle, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output jrst_n; + output st_ready_test_idle; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input clk; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + + wire [ 37: 0] jdo; + wire jrst_n; + wire [ 37: 0] sr; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire vji_cdr; + wire [ 1: 0] vji_ir_in; + wire [ 1: 0] vji_ir_out; + wire vji_rti; + wire vji_sdr; + wire vji_tck; + wire vji_tdi; + wire vji_tdo; + wire vji_udr; + wire vji_uir; + //Change the sld_virtual_jtag_basic's defparams to + //switch between a regular Nios II or an internally embedded Nios II. + //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. + //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. + nios_system_nios2_processor_jtag_debug_module_tck the_nios_system_nios2_processor_jtag_debug_module_tck + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .ir_in (vji_ir_in), + .ir_out (vji_ir_out), + .jrst_n (jrst_n), + .jtag_state_rti (vji_rti), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .sr (sr), + .st_ready_test_idle (st_ready_test_idle), + .tck (vji_tck), + .tdi (vji_tdi), + .tdo (vji_tdo), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1), + .vs_cdr (vji_cdr), + .vs_sdr (vji_sdr), + .vs_uir (vji_uir) + ); + + nios_system_nios2_processor_jtag_debug_module_sysclk the_nios_system_nios2_processor_jtag_debug_module_sysclk + ( + .clk (clk), + .ir_in (vji_ir_in), + .jdo (jdo), + .sr (sr), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .vs_udr (vji_udr), + .vs_uir (vji_uir) + ); + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign vji_tck = 1'b0; + assign vji_tdi = 1'b0; + assign vji_sdr = 1'b0; + assign vji_cdr = 1'b0; + assign vji_rti = 1'b0; + assign vji_uir = 1'b0; + assign vji_udr = 1'b0; + assign vji_ir_in = 2'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// sld_virtual_jtag_basic nios_system_nios2_processor_jtag_debug_module_phy +// ( +// .ir_in (vji_ir_in), +// .ir_out (vji_ir_out), +// .jtag_state_rti (vji_rti), +// .tck (vji_tck), +// .tdi (vji_tdi), +// .tdo (vji_tdo), +// .virtual_state_cdr (vji_cdr), +// .virtual_state_sdr (vji_sdr), +// .virtual_state_udr (vji_udr), +// .virtual_state_uir (vji_uir) +// ); +// +// defparam nios_system_nios2_processor_jtag_debug_module_phy.sld_auto_instance_index = "YES", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_instance_index = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_ir_width = 2, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_mfg_id = 70, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_action = "", +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_n_scan = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_sim_total_length = 0, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_type_id = 34, +// nios_system_nios2_processor_jtag_debug_module_phy.sld_version = 3; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v index cf59495..0046686 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_oci_test_bench.v @@ -1,37 +1,37 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_oci_test_bench ( - // inputs: - dct_buffer, - dct_count, - test_ending, - test_has_ended - ) -; - - input [ 29: 0] dct_buffer; - input [ 3: 0] dct_count; - input test_ending; - input test_has_ended; - - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_oci_test_bench ( + // inputs: + dct_buffer, + dct_count, + test_ending, + test_has_ended + ) +; + + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input test_ending; + input test_has_ended; + + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif index aee33b3..44481aa 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_ociram_default_contents.mif @@ -1,267 +1,267 @@ --- Contents are randomly generated during RTL generation. -WIDTH=32; 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-7a : 74ede6d2; -7b : 080eafa5; -7c : f21052d8; -7d : cc0819fb; -7e : 8993e5b6; -7f : e20f2df6; -80 : 0f267a65; -81 : 7a8e8407; -82 : e7be656d; -83 : 01ba4ca3; -84 : 7f998e44; -85 : 29d83420; -86 : 149f9a73; -87 : 643ae51e; -88 : 125714d3; -89 : 6e49dc21; -8a : 0b227946; -8b : 360a837d; -8c : b2187074; -8d : 17b0bdbd; -8e : 938fc73d; -8f : e73f501e; -90 : 70b5b87e; -91 : 2a2aed8a; -92 : f96cc881; -93 : 021b49e1; -94 : 8691600d; -95 : b45e1d12; -96 : 64d9644e; -97 : 486cbaf9; -98 : 386acf20; -99 : 0d1384d4; -9a : 62455f77; -9b : 866fde20; -9c : 006fecec; -9d : 94e84514; -9e : 7babc333; -9f : afaa8445; -a0 : b1175e3a; -a1 : e08de629; -a2 : 7f12a52d; -a3 : 0e322909; -a4 : 18784dc6; -a5 : b23bcc20; -a6 : 266c9e34; -a7 : c857eaf3; -a8 : 2ae3b164; -a9 : 038acf2a; -aa : c1abc60d; -ab : 8af787bd; -ac : 043723a9; -ad : c37c952d; -ae : 693a361f; -af : da4b8e99; -b0 : fb8fdb10; -b1 : 4d6365f2; -b2 : 712358e9; -b3 : 85dae0fa; -b4 : 7e82a418; -b5 : d3493768; -b6 : 739c65ec; -b7 : 73b66b19; -b8 : 22142816; -b9 : ff498322; -ba : 3266495e; -bb : e26e8214; -bc : c8c47131; -bd : 660793d8; -be : 689f8d69; -bf : faae340b; -c0 : 37518ba7; -c1 : f2865fe5; -c2 : 1bb44f3d; -c3 : 3bce44c5; -c4 : aff2d188; -c5 : 985442da; -c6 : 85bb58bd; -c7 : 0c53135d; -c8 : 495f80bc; -c9 : 853c95dc; -ca : dde937f1; -cb : 418f9452; -cc : 7669641c; -cd : 0e752434; -ce : b0fe17a7; -cf : d1be9b88; -d0 : cfbfeb76; -d1 : 80b48a11; -d2 : 9327c69e; -d3 : beca5a88; -d4 : e71d428f; -d5 : b318d275; -d6 : 56fea35e; -d7 : 140cd6bd; -d8 : b8c937ce; -d9 : 540eea36; -da : ee58fc7f; -db : 5615c389; -dc : 46692ad0; -dd : 5c713e51; -de : 6ba95f60; -df : 0e166732; -e0 : ac0e49f5; -e1 : c9a5ea76; -e2 : 05b04d86; -e3 : b29ac712; -e4 : 4e344493; -e5 : d45ede48; -e6 : 3da7e426; -e7 : 4d6a8937; -e8 : 99b59bd4; -e9 : 1f8a5751; -ea : 8b07e64e; -eb : b4dcd496; -ec : 42f84fe6; -ed : f1d5952f; -ee : a2e5a42d; -ef : 15b1af16; -f0 : 168012bc; -f1 : 2e276612; -f2 : 89913eaa; -f3 : c607a1a2; -f4 : fd8b544d; -f5 : aec31a53; -f6 : 25f958ad; -f7 : 365903ec; -f8 : 14761865; -f9 : 568cc23b; -fa : b0386305; -fb : fb9ebd8a; -fc : a25911d4; -fd : 806e3fbb; -fe : 9df35264; -ff : d62b3814; - -END; +-- Contents are randomly generated during RTL generation. +WIDTH=32; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : 88997af9; +01 : abaae595; +02 : 32fd14d1; +03 : b66193c4; +04 : c6a6aa09; +05 : 0b43de5b; +06 : d1d93028; +07 : bcd08e2a; +08 : 1c8bae85; +09 : b11dad63; +0a : 864ddf62; +0b : 68301486; +0c : 51a3d8d0; +0d : 7af7d39e; +0e : 4761b503; +0f : 2a976e14; +10 : 98141041; +11 : 4c1f6471; +12 : 41dc0a35; +13 : 7d484ae3; +14 : 2a1329f3; +15 : 44ecf499; +16 : dccdd125; +17 : 240142e9; +18 : 3b7e4b05; +19 : bb92e762; +1a : 4594a3c5; +1b : ea0d940f; +1c : 66525d7c; +1d : 0f552242; +1e : 452bd52d; +1f : d1f4ed11; +20 : 5d590422; +21 : c8016b5f; +22 : 9ab94f07; +23 : 16bac9b4; +24 : fe569ae3; +25 : c6e1e6e7; +26 : 2ff19932; +27 : feb058ad; +28 : 1dcce651; +29 : e18b9bfb; +2a : e2f4fc64; +2b : 05d34847; +2c : 077a8143; +2d : 2ce4207f; +2e : 3f3e5113; +2f : c24d2803; +30 : e289b503; +31 : d16bcd4e; +32 : 57a841cf; +33 : 1194f754; +34 : 5c925a31; +35 : 40fd6946; +36 : e397e5d7; +37 : eada7553; +38 : eba8ec01; +39 : f5b39d0b; +3a : 88af39a3; +3b : 5b7f243e; +3c : 4f2bb4ba; +3d : 9451a234; +3e : 10fd984d; +3f : ad4ef4f7; +40 : 7fe97f8b; +41 : 08ea614d; +42 : 9f2c5cf4; +43 : 3f90b7a2; +44 : 8c2bc774; +45 : 45dd63a5; +46 : 3204329c; +47 : 9909be0d; +48 : be65c97b; +49 : 78f3d4a4; +4a : 3ee8b71c; +4b : 9e9a0de4; +4c : 56db426b; +4d : e6869d81; +4e : 20ab0652; +4f : 05d247ed; +50 : 1edccf12; +51 : 1e483b5a; +52 : 8e48ef1e; +53 : f19aefbf; +54 : 98335d23; +55 : 954ac923; +56 : 4679ced6; +57 : ae18d9b8; +58 : be57db48; +59 : 2af933e3; +5a : 3f04e244; +5b : 5d11c958; +5c : 65bda8cb; +5d : c53fe664; +5e : 797ceac8; +5f : aaa406e5; +60 : f785e24e; +61 : 95510077; +62 : 5b6f55a3; +63 : 2a3c749a; +64 : a92e6ae6; +65 : b2117fb0; +66 : 262a254e; +67 : b8c4da74; +68 : f69070ee; +69 : 9e7f80b8; +6a : 834528b4; +6b : 4aaf6d98; +6c : 96023372; +6d : d11663ed; +6e : 33a3c007; +6f : 0e7f06ee; +70 : 34385787; +71 : 2edfd7b0; +72 : 00d60e4b; +73 : 49535c30; +74 : e83f5c14; +75 : 5e0c4c59; +76 : 1d7b944a; +77 : 6ae69731; +78 : bf8414e4; +79 : 7451c212; +7a : 74ede6d2; +7b : 080eafa5; +7c : f21052d8; +7d : cc0819fb; +7e : 8993e5b6; +7f : e20f2df6; +80 : 0f267a65; +81 : 7a8e8407; +82 : e7be656d; +83 : 01ba4ca3; +84 : 7f998e44; +85 : 29d83420; +86 : 149f9a73; +87 : 643ae51e; +88 : 125714d3; +89 : 6e49dc21; +8a : 0b227946; +8b : 360a837d; +8c : b2187074; +8d : 17b0bdbd; +8e : 938fc73d; +8f : e73f501e; +90 : 70b5b87e; +91 : 2a2aed8a; +92 : f96cc881; +93 : 021b49e1; +94 : 8691600d; +95 : b45e1d12; +96 : 64d9644e; +97 : 486cbaf9; +98 : 386acf20; +99 : 0d1384d4; +9a : 62455f77; +9b : 866fde20; +9c : 006fecec; +9d : 94e84514; +9e : 7babc333; +9f : afaa8445; +a0 : b1175e3a; +a1 : e08de629; +a2 : 7f12a52d; +a3 : 0e322909; +a4 : 18784dc6; +a5 : b23bcc20; +a6 : 266c9e34; +a7 : c857eaf3; +a8 : 2ae3b164; +a9 : 038acf2a; +aa : c1abc60d; +ab : 8af787bd; +ac : 043723a9; +ad : c37c952d; +ae : 693a361f; +af : da4b8e99; +b0 : fb8fdb10; +b1 : 4d6365f2; +b2 : 712358e9; +b3 : 85dae0fa; +b4 : 7e82a418; +b5 : d3493768; +b6 : 739c65ec; +b7 : 73b66b19; +b8 : 22142816; +b9 : ff498322; +ba : 3266495e; +bb : e26e8214; +bc : c8c47131; +bd : 660793d8; +be : 689f8d69; +bf : faae340b; +c0 : 37518ba7; +c1 : f2865fe5; +c2 : 1bb44f3d; +c3 : 3bce44c5; +c4 : aff2d188; +c5 : 985442da; +c6 : 85bb58bd; +c7 : 0c53135d; +c8 : 495f80bc; +c9 : 853c95dc; +ca : dde937f1; +cb : 418f9452; +cc : 7669641c; +cd : 0e752434; +ce : b0fe17a7; +cf : d1be9b88; +d0 : cfbfeb76; +d1 : 80b48a11; +d2 : 9327c69e; +d3 : beca5a88; +d4 : e71d428f; +d5 : b318d275; +d6 : 56fea35e; +d7 : 140cd6bd; +d8 : b8c937ce; +d9 : 540eea36; +da : ee58fc7f; +db : 5615c389; +dc : 46692ad0; +dd : 5c713e51; +de : 6ba95f60; +df : 0e166732; +e0 : ac0e49f5; +e1 : c9a5ea76; +e2 : 05b04d86; +e3 : b29ac712; +e4 : 4e344493; +e5 : d45ede48; +e6 : 3da7e426; +e7 : 4d6a8937; +e8 : 99b59bd4; +e9 : 1f8a5751; +ea : 8b07e64e; +eb : b4dcd496; +ec : 42f84fe6; +ed : f1d5952f; +ee : a2e5a42d; +ef : 15b1af16; +f0 : 168012bc; +f1 : 2e276612; +f2 : 89913eaa; +f3 : c607a1a2; +f4 : fd8b544d; +f5 : aec31a53; +f6 : 25f958ad; +f7 : 365903ec; +f8 : 14761865; +f9 : 568cc23b; +fa : b0386305; +fb : fb9ebd8a; +fc : a25911d4; +fd : 806e3fbb; +fe : 9df35264; +ff : d62b3814; + +END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif index 644013a..7969f10 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_a.mif @@ -1,42 +1,42 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif index 644013a..7969f10 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_rf_ram_b.mif @@ -1,42 +1,42 @@ -WIDTH=32; -DEPTH=32; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - -00 : deadbeef; -01 : deadbeef; -02 : deadbeef; -03 : deadbeef; -04 : deadbeef; -05 : deadbeef; -06 : deadbeef; -07 : deadbeef; -08 : deadbeef; -09 : deadbeef; -0a : deadbeef; -0b : deadbeef; -0c : deadbeef; -0d : deadbeef; -0e : deadbeef; -0f : deadbeef; -10 : deadbeef; -11 : deadbeef; -12 : deadbeef; -13 : deadbeef; -14 : deadbeef; -15 : deadbeef; -16 : deadbeef; -17 : deadbeef; -18 : deadbeef; -19 : deadbeef; -1a : deadbeef; -1b : deadbeef; -1c : deadbeef; -1d : deadbeef; -1e : deadbeef; -1f : deadbeef; - -END; +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v b/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v index d707995..9ce093e 100644 --- a/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v +++ b/nios_system/synthesis/submodules/nios_system_nios2_processor_test_bench.v @@ -1,667 +1,667 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_nios2_processor_test_bench ( - // inputs: - D_iw, - D_iw_op, - D_iw_opx, - D_valid, - E_valid, - F_pcb, - F_valid, - R_ctrl_ld, - R_ctrl_ld_non_io, - R_dst_regnum, - R_wr_dst_reg, - W_valid, - W_vinst, - W_wr_data, - av_ld_data_aligned_unfiltered, - clk, - d_address, - d_byteenable, - d_read, - d_write_nxt, - i_address, - i_read, - i_readdata, - i_waitrequest, - reset_n, - - // outputs: - av_ld_data_aligned_filtered, - d_write, - test_has_ended - ) -; - - output [ 31: 0] av_ld_data_aligned_filtered; - output d_write; - output test_has_ended; - input [ 31: 0] D_iw; - input [ 5: 0] D_iw_op; - input [ 5: 0] D_iw_opx; - input D_valid; - input E_valid; - input [ 18: 0] F_pcb; - input F_valid; - input R_ctrl_ld; - input R_ctrl_ld_non_io; - input [ 4: 0] R_dst_regnum; - input R_wr_dst_reg; - input W_valid; - input [ 55: 0] W_vinst; - input [ 31: 0] W_wr_data; - input [ 31: 0] av_ld_data_aligned_unfiltered; - input clk; - input [ 18: 0] d_address; - input [ 3: 0] d_byteenable; - input d_read; - input d_write_nxt; - input [ 18: 0] i_address; - input i_read; - input [ 31: 0] i_readdata; - input i_waitrequest; - input reset_n; - - wire D_op_add; - wire D_op_addi; - wire D_op_and; - wire D_op_andhi; - wire D_op_andi; - wire D_op_beq; - wire D_op_bge; - wire D_op_bgeu; - wire D_op_blt; - wire D_op_bltu; - wire D_op_bne; - wire D_op_br; - wire D_op_break; - wire D_op_bret; - wire D_op_call; - wire D_op_callr; - wire D_op_cmpeq; - wire D_op_cmpeqi; - wire D_op_cmpge; - wire D_op_cmpgei; - wire D_op_cmpgeu; - wire D_op_cmpgeui; - wire D_op_cmplt; - wire D_op_cmplti; - wire D_op_cmpltu; - wire D_op_cmpltui; - wire D_op_cmpne; - wire D_op_cmpnei; - wire D_op_crst; - wire D_op_custom; - wire D_op_div; - wire D_op_divu; - wire D_op_eret; - wire D_op_flushd; - wire D_op_flushda; - wire D_op_flushi; - wire D_op_flushp; - wire D_op_hbreak; - wire D_op_initd; - wire D_op_initda; - wire D_op_initi; - wire D_op_intr; - wire D_op_jmp; - wire D_op_jmpi; - wire D_op_ldb; - wire D_op_ldbio; - wire D_op_ldbu; - wire D_op_ldbuio; - wire D_op_ldh; - wire D_op_ldhio; - wire D_op_ldhu; - wire D_op_ldhuio; - wire D_op_ldl; - wire D_op_ldw; - wire D_op_ldwio; - wire D_op_mul; - wire D_op_muli; - wire D_op_mulxss; - wire D_op_mulxsu; - wire D_op_mulxuu; - wire D_op_nextpc; - wire D_op_nor; - wire D_op_opx; - wire D_op_or; - wire D_op_orhi; - wire D_op_ori; - wire D_op_rdctl; - wire D_op_rdprs; - wire D_op_ret; - wire D_op_rol; - wire D_op_roli; - wire D_op_ror; - wire D_op_rsv02; - wire D_op_rsv09; - wire D_op_rsv10; - wire D_op_rsv17; - wire D_op_rsv18; - wire D_op_rsv25; - wire D_op_rsv26; - wire D_op_rsv33; - wire D_op_rsv34; - wire D_op_rsv41; - wire D_op_rsv42; - wire D_op_rsv49; - wire D_op_rsv57; - wire D_op_rsv61; - wire D_op_rsv62; - wire D_op_rsv63; - wire D_op_rsvx00; - wire D_op_rsvx10; - wire D_op_rsvx15; - wire D_op_rsvx17; - wire D_op_rsvx21; - wire D_op_rsvx25; - wire D_op_rsvx33; - wire D_op_rsvx34; - wire D_op_rsvx35; - wire D_op_rsvx42; - wire D_op_rsvx43; - wire D_op_rsvx44; - wire D_op_rsvx47; - wire D_op_rsvx50; - wire D_op_rsvx51; - wire D_op_rsvx55; - wire D_op_rsvx56; - wire D_op_rsvx60; - wire D_op_rsvx63; - wire D_op_sll; - wire D_op_slli; - wire D_op_sra; - wire D_op_srai; - wire D_op_srl; - wire D_op_srli; - wire D_op_stb; - wire D_op_stbio; - wire D_op_stc; - wire D_op_sth; - wire D_op_sthio; - wire D_op_stw; - wire D_op_stwio; - wire D_op_sub; - wire D_op_sync; - wire D_op_trap; - wire D_op_wrctl; - wire D_op_wrprs; - wire D_op_xor; - wire D_op_xorhi; - wire D_op_xori; - wire [ 31: 0] av_ld_data_aligned_filtered; - wire av_ld_data_aligned_unfiltered_0_is_x; - wire av_ld_data_aligned_unfiltered_10_is_x; - wire av_ld_data_aligned_unfiltered_11_is_x; - wire av_ld_data_aligned_unfiltered_12_is_x; - wire av_ld_data_aligned_unfiltered_13_is_x; - wire av_ld_data_aligned_unfiltered_14_is_x; - wire av_ld_data_aligned_unfiltered_15_is_x; - wire av_ld_data_aligned_unfiltered_16_is_x; - wire av_ld_data_aligned_unfiltered_17_is_x; - wire av_ld_data_aligned_unfiltered_18_is_x; - wire av_ld_data_aligned_unfiltered_19_is_x; - wire av_ld_data_aligned_unfiltered_1_is_x; - wire av_ld_data_aligned_unfiltered_20_is_x; - wire av_ld_data_aligned_unfiltered_21_is_x; - wire av_ld_data_aligned_unfiltered_22_is_x; - wire av_ld_data_aligned_unfiltered_23_is_x; - wire av_ld_data_aligned_unfiltered_24_is_x; - wire av_ld_data_aligned_unfiltered_25_is_x; - wire av_ld_data_aligned_unfiltered_26_is_x; - wire av_ld_data_aligned_unfiltered_27_is_x; - wire av_ld_data_aligned_unfiltered_28_is_x; - wire av_ld_data_aligned_unfiltered_29_is_x; - wire av_ld_data_aligned_unfiltered_2_is_x; - wire av_ld_data_aligned_unfiltered_30_is_x; - wire av_ld_data_aligned_unfiltered_31_is_x; - wire av_ld_data_aligned_unfiltered_3_is_x; - wire av_ld_data_aligned_unfiltered_4_is_x; - wire av_ld_data_aligned_unfiltered_5_is_x; - wire av_ld_data_aligned_unfiltered_6_is_x; - wire av_ld_data_aligned_unfiltered_7_is_x; - wire av_ld_data_aligned_unfiltered_8_is_x; - wire av_ld_data_aligned_unfiltered_9_is_x; - reg d_write; - wire test_has_ended; - assign D_op_call = D_iw_op == 0; - assign D_op_jmpi = D_iw_op == 1; - assign D_op_ldbu = D_iw_op == 3; - assign D_op_addi = D_iw_op == 4; - assign D_op_stb = D_iw_op == 5; - assign D_op_br = D_iw_op == 6; - assign D_op_ldb = D_iw_op == 7; - assign D_op_cmpgei = D_iw_op == 8; - assign D_op_ldhu = D_iw_op == 11; - assign D_op_andi = D_iw_op == 12; - assign D_op_sth = D_iw_op == 13; - assign D_op_bge = D_iw_op == 14; - assign D_op_ldh = D_iw_op == 15; - assign D_op_cmplti = D_iw_op == 16; - assign D_op_initda = D_iw_op == 19; - assign D_op_ori = D_iw_op == 20; - assign D_op_stw = D_iw_op == 21; - assign D_op_blt = D_iw_op == 22; - assign D_op_ldw = D_iw_op == 23; - assign D_op_cmpnei = D_iw_op == 24; - assign D_op_flushda = D_iw_op == 27; - assign D_op_xori = D_iw_op == 28; - assign D_op_stc = D_iw_op == 29; - assign D_op_bne = D_iw_op == 30; - assign D_op_ldl = D_iw_op == 31; - assign D_op_cmpeqi = D_iw_op == 32; - assign D_op_ldbuio = D_iw_op == 35; - assign D_op_muli = D_iw_op == 36; - assign D_op_stbio = D_iw_op == 37; - assign D_op_beq = D_iw_op == 38; - assign D_op_ldbio = D_iw_op == 39; - assign D_op_cmpgeui = D_iw_op == 40; - assign D_op_ldhuio = D_iw_op == 43; - assign D_op_andhi = D_iw_op == 44; - assign D_op_sthio = D_iw_op == 45; - assign D_op_bgeu = D_iw_op == 46; - assign D_op_ldhio = D_iw_op == 47; - assign D_op_cmpltui = D_iw_op == 48; - assign D_op_initd = D_iw_op == 51; - assign D_op_orhi = D_iw_op == 52; - assign D_op_stwio = D_iw_op == 53; - assign D_op_bltu = D_iw_op == 54; - assign D_op_ldwio = D_iw_op == 55; - assign D_op_rdprs = D_iw_op == 56; - assign D_op_flushd = D_iw_op == 59; - assign D_op_xorhi = D_iw_op == 60; - assign D_op_rsv02 = D_iw_op == 2; - assign D_op_rsv09 = D_iw_op == 9; - assign D_op_rsv10 = D_iw_op == 10; - assign D_op_rsv17 = D_iw_op == 17; - assign D_op_rsv18 = D_iw_op == 18; - assign D_op_rsv25 = D_iw_op == 25; - assign D_op_rsv26 = D_iw_op == 26; - assign D_op_rsv33 = D_iw_op == 33; - assign D_op_rsv34 = D_iw_op == 34; - assign D_op_rsv41 = D_iw_op == 41; - assign D_op_rsv42 = D_iw_op == 42; - assign D_op_rsv49 = D_iw_op == 49; - assign D_op_rsv57 = D_iw_op == 57; - assign D_op_rsv61 = D_iw_op == 61; - assign D_op_rsv62 = D_iw_op == 62; - assign D_op_rsv63 = D_iw_op == 63; - assign D_op_eret = D_op_opx & (D_iw_opx == 1); - assign D_op_roli = D_op_opx & (D_iw_opx == 2); - assign D_op_rol = D_op_opx & (D_iw_opx == 3); - assign D_op_flushp = D_op_opx & (D_iw_opx == 4); - assign D_op_ret = D_op_opx & (D_iw_opx == 5); - assign D_op_nor = D_op_opx & (D_iw_opx == 6); - assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); - assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); - assign D_op_bret = D_op_opx & (D_iw_opx == 9); - assign D_op_ror = D_op_opx & (D_iw_opx == 11); - assign D_op_flushi = D_op_opx & (D_iw_opx == 12); - assign D_op_jmp = D_op_opx & (D_iw_opx == 13); - assign D_op_and = D_op_opx & (D_iw_opx == 14); - assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); - assign D_op_slli = D_op_opx & (D_iw_opx == 18); - assign D_op_sll = D_op_opx & (D_iw_opx == 19); - assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); - assign D_op_or = D_op_opx & (D_iw_opx == 22); - assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); - assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); - assign D_op_srli = D_op_opx & (D_iw_opx == 26); - assign D_op_srl = D_op_opx & (D_iw_opx == 27); - assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); - assign D_op_callr = D_op_opx & (D_iw_opx == 29); - assign D_op_xor = D_op_opx & (D_iw_opx == 30); - assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); - assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); - assign D_op_divu = D_op_opx & (D_iw_opx == 36); - assign D_op_div = D_op_opx & (D_iw_opx == 37); - assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); - assign D_op_mul = D_op_opx & (D_iw_opx == 39); - assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); - assign D_op_initi = D_op_opx & (D_iw_opx == 41); - assign D_op_trap = D_op_opx & (D_iw_opx == 45); - assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); - assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); - assign D_op_add = D_op_opx & (D_iw_opx == 49); - assign D_op_break = D_op_opx & (D_iw_opx == 52); - assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); - assign D_op_sync = D_op_opx & (D_iw_opx == 54); - assign D_op_sub = D_op_opx & (D_iw_opx == 57); - assign D_op_srai = D_op_opx & (D_iw_opx == 58); - assign D_op_sra = D_op_opx & (D_iw_opx == 59); - assign D_op_intr = D_op_opx & (D_iw_opx == 61); - assign D_op_crst = D_op_opx & (D_iw_opx == 62); - assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); - assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); - assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); - assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); - assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); - assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); - assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); - assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); - assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); - assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); - assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); - assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); - assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); - assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); - assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); - assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); - assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); - assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); - assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); - assign D_op_opx = D_iw_op == 58; - assign D_op_custom = D_iw_op == 50; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - d_write <= 0; - else - d_write <= d_write_nxt; - end - - - assign test_has_ended = 1'b0; - -//synthesis translate_off -//////////////// SIMULATION-ONLY CONTENTS - //Clearing 'X' data bits - assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; - - assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; - assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; - assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; - assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; - assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; - assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; - assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; - assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; - assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; - assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; - assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; - assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; - assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; - assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; - assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; - assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; - assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; - assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; - assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; - assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; - assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; - assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; - assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; - assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; - assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; - assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; - assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; - assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; - assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; - assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; - assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; - assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; - assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; - assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; - assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; - assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; - assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; - assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; - assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; - assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; - assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; - assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; - assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; - assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; - assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; - assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; - assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; - assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; - assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; - assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; - assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; - assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; - assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; - assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; - assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; - assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; - assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; - assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; - assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; - assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; - assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; - assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; - assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; - always @(posedge clk) - begin - if (reset_n) - if (^(F_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(D_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(E_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(W_valid) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid) - if (^(R_wr_dst_reg) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(R_dst_regnum) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_write) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write) - if (^(d_byteenable) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (d_write | d_read) - if (^(d_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(d_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk) - begin - if (reset_n) - if (^(i_read) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read) - if (^(i_address) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (i_read & ~i_waitrequest) - if (^(i_readdata) === 1'bx) - begin - $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); - $stop; - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_ctrl_ld) - if (^(av_ld_data_aligned_unfiltered) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); - end - end - - - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - begin - end - else if (W_valid & R_wr_dst_reg) - if (^(W_wr_data) === 1'bx) - begin - $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); - end - end - - - -//////////////// END SIMULATION-ONLY CONTENTS - -//synthesis translate_on -//synthesis read_comments_as_HDL on -// -// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; -// -//synthesis read_comments_as_HDL off - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_nios2_processor_test_bench ( + // inputs: + D_iw, + D_iw_op, + D_iw_opx, + D_valid, + E_valid, + F_pcb, + F_valid, + R_ctrl_ld, + R_ctrl_ld_non_io, + R_dst_regnum, + R_wr_dst_reg, + W_valid, + W_vinst, + W_wr_data, + av_ld_data_aligned_unfiltered, + clk, + d_address, + d_byteenable, + d_read, + d_write_nxt, + i_address, + i_read, + i_readdata, + i_waitrequest, + reset_n, + + // outputs: + av_ld_data_aligned_filtered, + d_write, + test_has_ended + ) +; + + output [ 31: 0] av_ld_data_aligned_filtered; + output d_write; + output test_has_ended; + input [ 31: 0] D_iw; + input [ 5: 0] D_iw_op; + input [ 5: 0] D_iw_opx; + input D_valid; + input E_valid; + input [ 18: 0] F_pcb; + input F_valid; + input R_ctrl_ld; + input R_ctrl_ld_non_io; + input [ 4: 0] R_dst_regnum; + input R_wr_dst_reg; + input W_valid; + input [ 55: 0] W_vinst; + input [ 31: 0] W_wr_data; + input [ 31: 0] av_ld_data_aligned_unfiltered; + input clk; + input [ 18: 0] d_address; + input [ 3: 0] d_byteenable; + input d_read; + input d_write_nxt; + input [ 18: 0] i_address; + input i_read; + input [ 31: 0] i_readdata; + input i_waitrequest; + input reset_n; + + wire D_op_add; + wire D_op_addi; + wire D_op_and; + wire D_op_andhi; + wire D_op_andi; + wire D_op_beq; + wire D_op_bge; + wire D_op_bgeu; + wire D_op_blt; + wire D_op_bltu; + wire D_op_bne; + wire D_op_br; + wire D_op_break; + wire D_op_bret; + wire D_op_call; + wire D_op_callr; + wire D_op_cmpeq; + wire D_op_cmpeqi; + wire D_op_cmpge; + wire D_op_cmpgei; + wire D_op_cmpgeu; + wire D_op_cmpgeui; + wire D_op_cmplt; + wire D_op_cmplti; + wire D_op_cmpltu; + wire D_op_cmpltui; + wire D_op_cmpne; + wire D_op_cmpnei; + wire D_op_crst; + wire D_op_custom; + wire D_op_div; + wire D_op_divu; + wire D_op_eret; + wire D_op_flushd; + wire D_op_flushda; + wire D_op_flushi; + wire D_op_flushp; + wire D_op_hbreak; + wire D_op_initd; + wire D_op_initda; + wire D_op_initi; + wire D_op_intr; + wire D_op_jmp; + wire D_op_jmpi; + wire D_op_ldb; + wire D_op_ldbio; + wire D_op_ldbu; + wire D_op_ldbuio; + wire D_op_ldh; + wire D_op_ldhio; + wire D_op_ldhu; + wire D_op_ldhuio; + wire D_op_ldl; + wire D_op_ldw; + wire D_op_ldwio; + wire D_op_mul; + wire D_op_muli; + wire D_op_mulxss; + wire D_op_mulxsu; + wire D_op_mulxuu; + wire D_op_nextpc; + wire D_op_nor; + wire D_op_opx; + wire D_op_or; + wire D_op_orhi; + wire D_op_ori; + wire D_op_rdctl; + wire D_op_rdprs; + wire D_op_ret; + wire D_op_rol; + wire D_op_roli; + wire D_op_ror; + wire D_op_rsv02; + wire D_op_rsv09; + wire D_op_rsv10; + wire D_op_rsv17; + wire D_op_rsv18; + wire D_op_rsv25; + wire D_op_rsv26; + wire D_op_rsv33; + wire D_op_rsv34; + wire D_op_rsv41; + wire D_op_rsv42; + wire D_op_rsv49; + wire D_op_rsv57; + wire D_op_rsv61; + wire D_op_rsv62; + wire D_op_rsv63; + wire D_op_rsvx00; + wire D_op_rsvx10; + wire D_op_rsvx15; + wire D_op_rsvx17; + wire D_op_rsvx21; + wire D_op_rsvx25; + wire D_op_rsvx33; + wire D_op_rsvx34; + wire D_op_rsvx35; + wire D_op_rsvx42; + wire D_op_rsvx43; + wire D_op_rsvx44; + wire D_op_rsvx47; + wire D_op_rsvx50; + wire D_op_rsvx51; + wire D_op_rsvx55; + wire D_op_rsvx56; + wire D_op_rsvx60; + wire D_op_rsvx63; + wire D_op_sll; + wire D_op_slli; + wire D_op_sra; + wire D_op_srai; + wire D_op_srl; + wire D_op_srli; + wire D_op_stb; + wire D_op_stbio; + wire D_op_stc; + wire D_op_sth; + wire D_op_sthio; + wire D_op_stw; + wire D_op_stwio; + wire D_op_sub; + wire D_op_sync; + wire D_op_trap; + wire D_op_wrctl; + wire D_op_wrprs; + wire D_op_xor; + wire D_op_xorhi; + wire D_op_xori; + wire [ 31: 0] av_ld_data_aligned_filtered; + wire av_ld_data_aligned_unfiltered_0_is_x; + wire av_ld_data_aligned_unfiltered_10_is_x; + wire av_ld_data_aligned_unfiltered_11_is_x; + wire av_ld_data_aligned_unfiltered_12_is_x; + wire av_ld_data_aligned_unfiltered_13_is_x; + wire av_ld_data_aligned_unfiltered_14_is_x; + wire av_ld_data_aligned_unfiltered_15_is_x; + wire av_ld_data_aligned_unfiltered_16_is_x; + wire av_ld_data_aligned_unfiltered_17_is_x; + wire av_ld_data_aligned_unfiltered_18_is_x; + wire av_ld_data_aligned_unfiltered_19_is_x; + wire av_ld_data_aligned_unfiltered_1_is_x; + wire av_ld_data_aligned_unfiltered_20_is_x; + wire av_ld_data_aligned_unfiltered_21_is_x; + wire av_ld_data_aligned_unfiltered_22_is_x; + wire av_ld_data_aligned_unfiltered_23_is_x; + wire av_ld_data_aligned_unfiltered_24_is_x; + wire av_ld_data_aligned_unfiltered_25_is_x; + wire av_ld_data_aligned_unfiltered_26_is_x; + wire av_ld_data_aligned_unfiltered_27_is_x; + wire av_ld_data_aligned_unfiltered_28_is_x; + wire av_ld_data_aligned_unfiltered_29_is_x; + wire av_ld_data_aligned_unfiltered_2_is_x; + wire av_ld_data_aligned_unfiltered_30_is_x; + wire av_ld_data_aligned_unfiltered_31_is_x; + wire av_ld_data_aligned_unfiltered_3_is_x; + wire av_ld_data_aligned_unfiltered_4_is_x; + wire av_ld_data_aligned_unfiltered_5_is_x; + wire av_ld_data_aligned_unfiltered_6_is_x; + wire av_ld_data_aligned_unfiltered_7_is_x; + wire av_ld_data_aligned_unfiltered_8_is_x; + wire av_ld_data_aligned_unfiltered_9_is_x; + reg d_write; + wire test_has_ended; + assign D_op_call = D_iw_op == 0; + assign D_op_jmpi = D_iw_op == 1; + assign D_op_ldbu = D_iw_op == 3; + assign D_op_addi = D_iw_op == 4; + assign D_op_stb = D_iw_op == 5; + assign D_op_br = D_iw_op == 6; + assign D_op_ldb = D_iw_op == 7; + assign D_op_cmpgei = D_iw_op == 8; + assign D_op_ldhu = D_iw_op == 11; + assign D_op_andi = D_iw_op == 12; + assign D_op_sth = D_iw_op == 13; + assign D_op_bge = D_iw_op == 14; + assign D_op_ldh = D_iw_op == 15; + assign D_op_cmplti = D_iw_op == 16; + assign D_op_initda = D_iw_op == 19; + assign D_op_ori = D_iw_op == 20; + assign D_op_stw = D_iw_op == 21; + assign D_op_blt = D_iw_op == 22; + assign D_op_ldw = D_iw_op == 23; + assign D_op_cmpnei = D_iw_op == 24; + assign D_op_flushda = D_iw_op == 27; + assign D_op_xori = D_iw_op == 28; + assign D_op_stc = D_iw_op == 29; + assign D_op_bne = D_iw_op == 30; + assign D_op_ldl = D_iw_op == 31; + assign D_op_cmpeqi = D_iw_op == 32; + assign D_op_ldbuio = D_iw_op == 35; + assign D_op_muli = D_iw_op == 36; + assign D_op_stbio = D_iw_op == 37; + assign D_op_beq = D_iw_op == 38; + assign D_op_ldbio = D_iw_op == 39; + assign D_op_cmpgeui = D_iw_op == 40; + assign D_op_ldhuio = D_iw_op == 43; + assign D_op_andhi = D_iw_op == 44; + assign D_op_sthio = D_iw_op == 45; + assign D_op_bgeu = D_iw_op == 46; + assign D_op_ldhio = D_iw_op == 47; + assign D_op_cmpltui = D_iw_op == 48; + assign D_op_initd = D_iw_op == 51; + assign D_op_orhi = D_iw_op == 52; + assign D_op_stwio = D_iw_op == 53; + assign D_op_bltu = D_iw_op == 54; + assign D_op_ldwio = D_iw_op == 55; + assign D_op_rdprs = D_iw_op == 56; + assign D_op_flushd = D_iw_op == 59; + assign D_op_xorhi = D_iw_op == 60; + assign D_op_rsv02 = D_iw_op == 2; + assign D_op_rsv09 = D_iw_op == 9; + assign D_op_rsv10 = D_iw_op == 10; + assign D_op_rsv17 = D_iw_op == 17; + assign D_op_rsv18 = D_iw_op == 18; + assign D_op_rsv25 = D_iw_op == 25; + assign D_op_rsv26 = D_iw_op == 26; + assign D_op_rsv33 = D_iw_op == 33; + assign D_op_rsv34 = D_iw_op == 34; + assign D_op_rsv41 = D_iw_op == 41; + assign D_op_rsv42 = D_iw_op == 42; + assign D_op_rsv49 = D_iw_op == 49; + assign D_op_rsv57 = D_iw_op == 57; + assign D_op_rsv61 = D_iw_op == 61; + assign D_op_rsv62 = D_iw_op == 62; + assign D_op_rsv63 = D_iw_op == 63; + assign D_op_eret = D_op_opx & (D_iw_opx == 1); + assign D_op_roli = D_op_opx & (D_iw_opx == 2); + assign D_op_rol = D_op_opx & (D_iw_opx == 3); + assign D_op_flushp = D_op_opx & (D_iw_opx == 4); + assign D_op_ret = D_op_opx & (D_iw_opx == 5); + assign D_op_nor = D_op_opx & (D_iw_opx == 6); + assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7); + assign D_op_cmpge = D_op_opx & (D_iw_opx == 8); + assign D_op_bret = D_op_opx & (D_iw_opx == 9); + assign D_op_ror = D_op_opx & (D_iw_opx == 11); + assign D_op_flushi = D_op_opx & (D_iw_opx == 12); + assign D_op_jmp = D_op_opx & (D_iw_opx == 13); + assign D_op_and = D_op_opx & (D_iw_opx == 14); + assign D_op_cmplt = D_op_opx & (D_iw_opx == 16); + assign D_op_slli = D_op_opx & (D_iw_opx == 18); + assign D_op_sll = D_op_opx & (D_iw_opx == 19); + assign D_op_wrprs = D_op_opx & (D_iw_opx == 20); + assign D_op_or = D_op_opx & (D_iw_opx == 22); + assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23); + assign D_op_cmpne = D_op_opx & (D_iw_opx == 24); + assign D_op_srli = D_op_opx & (D_iw_opx == 26); + assign D_op_srl = D_op_opx & (D_iw_opx == 27); + assign D_op_nextpc = D_op_opx & (D_iw_opx == 28); + assign D_op_callr = D_op_opx & (D_iw_opx == 29); + assign D_op_xor = D_op_opx & (D_iw_opx == 30); + assign D_op_mulxss = D_op_opx & (D_iw_opx == 31); + assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32); + assign D_op_divu = D_op_opx & (D_iw_opx == 36); + assign D_op_div = D_op_opx & (D_iw_opx == 37); + assign D_op_rdctl = D_op_opx & (D_iw_opx == 38); + assign D_op_mul = D_op_opx & (D_iw_opx == 39); + assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40); + assign D_op_initi = D_op_opx & (D_iw_opx == 41); + assign D_op_trap = D_op_opx & (D_iw_opx == 45); + assign D_op_wrctl = D_op_opx & (D_iw_opx == 46); + assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48); + assign D_op_add = D_op_opx & (D_iw_opx == 49); + assign D_op_break = D_op_opx & (D_iw_opx == 52); + assign D_op_hbreak = D_op_opx & (D_iw_opx == 53); + assign D_op_sync = D_op_opx & (D_iw_opx == 54); + assign D_op_sub = D_op_opx & (D_iw_opx == 57); + assign D_op_srai = D_op_opx & (D_iw_opx == 58); + assign D_op_sra = D_op_opx & (D_iw_opx == 59); + assign D_op_intr = D_op_opx & (D_iw_opx == 61); + assign D_op_crst = D_op_opx & (D_iw_opx == 62); + assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0); + assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10); + assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15); + assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17); + assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21); + assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25); + assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33); + assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34); + assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35); + assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42); + assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43); + assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44); + assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47); + assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50); + assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51); + assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55); + assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56); + assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60); + assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63); + assign D_op_opx = D_iw_op == 58; + assign D_op_custom = D_iw_op == 50; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d_write <= 0; + else + d_write <= d_write_nxt; + end + + + assign test_has_ended = 1'b0; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //Clearing 'X' data bits + assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx; + + assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0]; + assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx; + assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1]; + assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx; + assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2]; + assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx; + assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3]; + assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx; + assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4]; + assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx; + assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5]; + assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx; + assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6]; + assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx; + assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7]; + assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx; + assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8]; + assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx; + assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9]; + assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx; + assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10]; + assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx; + assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11]; + assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx; + assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12]; + assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx; + assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13]; + assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx; + assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14]; + assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx; + assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15]; + assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx; + assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16]; + assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx; + assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17]; + assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx; + assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18]; + assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx; + assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19]; + assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx; + assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20]; + assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx; + assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21]; + assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx; + assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22]; + assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx; + assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23]; + assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx; + assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24]; + assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx; + assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25]; + assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx; + assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26]; + assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx; + assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27]; + assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx; + assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28]; + assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx; + assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29]; + assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx; + assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30]; + assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx; + assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31]; + always @(posedge clk) + begin + if (reset_n) + if (^(F_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/F_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(D_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/D_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(E_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/E_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(W_valid) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid) + if (^(R_wr_dst_reg) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_wr_dst_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(R_dst_regnum) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/R_dst_regnum is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_write) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_write is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write) + if (^(d_byteenable) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_byteenable is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write | d_read) + if (^(d_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/d_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(i_read) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read) + if (^(i_address) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read & ~i_waitrequest) + if (^(i_readdata) === 1'bx) + begin + $write("%0d ns: ERROR: nios_system_nios2_processor_test_bench/i_readdata is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_ctrl_ld) + if (^(av_ld_data_aligned_unfiltered) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time); + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid & R_wr_dst_reg) + if (^(W_wr_data) === 1'bx) + begin + $write("%0d ns: WARNING: nios_system_nios2_processor_test_bench/W_wr_data is 'x'\n", $time); + end + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// +// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_onchip_memory.hex b/nios_system/synthesis/submodules/nios_system_onchip_memory.hex index f996dcd..e265501 100644 --- a/nios_system/synthesis/submodules/nios_system_onchip_memory.hex +++ b/nios_system/synthesis/submodules/nios_system_onchip_memory.hex @@ -1,51201 +1,51201 @@ -:0400000000000000FC -:0400010000000000FB -:0400020000000000FA -:0400030000000000F9 -:0400040000000000F8 -:0400050000000000F7 -:0400060000000000F6 -:0400070000000000F5 -:0400080000000000F4 -:0400090000000000F3 -:04000A0000000000F2 -:04000B0000000000F1 -:04000C0000000000F0 -:04000D0000000000EF -:04000E0000000000EE -:04000F0000000000ED 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+:04C7EE000000000047 +:04C7EF000000000046 +:04C7F0000000000045 +:04C7F1000000000044 +:04C7F2000000000043 +:04C7F3000000000042 +:04C7F4000000000041 +:04C7F5000000000040 +:04C7F600000000003F +:04C7F700000000003E +:04C7F800000000003D +:04C7F900000000003C +:04C7FA00000000003B +:04C7FB00000000003A +:04C7FC000000000039 +:04C7FD000000000038 +:04C7FE000000000037 +:04C7FF000000000036 +:00000001ff diff --git a/nios_system/synthesis/submodules/nios_system_onchip_memory.v b/nios_system/synthesis/submodules/nios_system_onchip_memory.v index 685f015..c12e1cd 100644 --- a/nios_system/synthesis/submodules/nios_system_onchip_memory.v +++ b/nios_system/synthesis/submodules/nios_system_onchip_memory.v @@ -1,85 +1,85 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_onchip_memory ( - // inputs: - address, - byteenable, - chipselect, - clk, - clken, - reset, - reset_req, - write, - writedata, - - // outputs: - readdata - ) -; - - parameter INIT_FILE = "nios_system_onchip_memory.hex"; - - - output [ 31: 0] readdata; - input [ 15: 0] address; - input [ 3: 0] byteenable; - input chipselect; - input clk; - input clken; - input reset; - input reset_req; - input write; - input [ 31: 0] writedata; - - wire clocken0; - wire [ 31: 0] readdata; - wire wren; - assign wren = chipselect & write; - assign clocken0 = clken & ~reset_req; - altsyncram the_altsyncram - ( - .address_a (address), - .byteena_a (byteenable), - .clock0 (clk), - .clocken0 (clocken0), - .data_a (writedata), - .q_a (readdata), - .wren_a (wren) - ); - - defparam the_altsyncram.byte_size = 8, - the_altsyncram.init_file = INIT_FILE, - the_altsyncram.lpm_type = "altsyncram", - the_altsyncram.maximum_depth = 51200, - the_altsyncram.numwords_a = 51200, - the_altsyncram.operation_mode = "SINGLE_PORT", - the_altsyncram.outdata_reg_a = "UNREGISTERED", - the_altsyncram.ram_block_type = "AUTO", - the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", - the_altsyncram.width_a = 32, - the_altsyncram.width_byteena_a = 4, - the_altsyncram.widthad_a = 16; - - //s1, which is an e_avalon_slave - //s2, which is an e_avalon_slave - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_onchip_memory ( + // inputs: + address, + byteenable, + chipselect, + clk, + clken, + reset, + reset_req, + write, + writedata, + + // outputs: + readdata + ) +; + + parameter INIT_FILE = "nios_system_onchip_memory.hex"; + + + output [ 31: 0] readdata; + input [ 15: 0] address; + input [ 3: 0] byteenable; + input chipselect; + input clk; + input clken; + input reset; + input reset_req; + input write; + input [ 31: 0] writedata; + + wire clocken0; + wire [ 31: 0] readdata; + wire wren; + assign wren = chipselect & write; + assign clocken0 = clken & ~reset_req; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clk), + .clocken0 (clocken0), + .data_a (writedata), + .q_a (readdata), + .wren_a (wren) + ); + + defparam the_altsyncram.byte_size = 8, + the_altsyncram.init_file = INIT_FILE, + the_altsyncram.lpm_type = "altsyncram", + the_altsyncram.maximum_depth = 51200, + the_altsyncram.numwords_a = 51200, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 16; + + //s1, which is an e_avalon_slave + //s2, which is an e_avalon_slave + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_push_switches.v b/nios_system/synthesis/submodules/nios_system_push_switches.v index 381d964..5b3cb8d 100644 --- a/nios_system/synthesis/submodules/nios_system_push_switches.v +++ b/nios_system/synthesis/submodules/nios_system_push_switches.v @@ -1,58 +1,58 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_push_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 2: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 2: 0] data_in; - wire [ 2: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {3 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_push_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 2: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 2: 0] data_in; + wire [ 2: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {3 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv index d81d1d6..52411df 100644 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_demux_002.sv @@ -1,101 +1,101 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------- -// Merlin Demultiplexer -// -// Asserts valid on the appropriate output -// given a one-hot channel signal. -// ------------------------------------- - -`timescale 1 ns / 1 ns - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_demux_002 -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// NUM_OUTPUTS: 1 -// VALID_WIDTH: 1 -// ------------------------------------------ - -//------------------------------------------ -// Message Supression Used -// QIS Warnings -// 15610 - Warning: Design contains x input pin(s) that do not drive logic -//------------------------------------------ - -module nios_system_rsp_xbar_demux_002 -( - // ------------------- - // Sink - // ------------------- - input [1-1 : 0] sink_valid, - input [96-1 : 0] sink_data, // ST_DATA_W=96 - input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 - input sink_startofpacket, - input sink_endofpacket, - output sink_ready, - - // ------------------- - // Sources - // ------------------- - output reg src0_valid, - output reg [96-1 : 0] src0_data, // ST_DATA_W=96 - output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 - output reg src0_startofpacket, - output reg src0_endofpacket, - input src0_ready, - - - // ------------------- - // Clock & Reset - // ------------------- - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk - input clk, - (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset - input reset - -); - - localparam NUM_OUTPUTS = 1; - wire [NUM_OUTPUTS - 1 : 0] ready_vector; - - // ------------------- - // Demux - // ------------------- - always @* begin - src0_data = sink_data; - src0_startofpacket = sink_startofpacket; - src0_endofpacket = sink_endofpacket; - src0_channel = sink_channel >> NUM_OUTPUTS; - - src0_valid = sink_channel[0] && sink_valid; - - end - - // ------------------- - // Backpressure - // ------------------- - assign ready_vector[0] = src0_ready; - - assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); - -endmodule - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_demux_002 +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module nios_system_rsp_xbar_demux_002 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [96-1 : 0] sink_data, // ST_DATA_W=96 + input [18-1 : 0] sink_channel, // ST_CHANNEL_W=18 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [96-1 : 0] src0_data, // ST_DATA_W=96 + output reg [18-1 : 0] src0_channel, // ST_CHANNEL_W=18 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{17{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv index a829592..6f30bfb 100644 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux.sv @@ -1,331 +1,331 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux -// NUM_INPUTS: 2 -// ARBITRATION_SHARES: 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 2; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv index ab346d9..ce9f7a1 100644 --- a/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv +++ b/nios_system/synthesis/submodules/nios_system_rsp_xbar_mux_001.sv @@ -1,651 +1,651 @@ -// (C) 2001-2013 Altera Corporation. All rights reserved. -// Your use of Altera Corporation's design tools, logic functions and other -// software and tools, and its AMPP partner logic functions, and any output -// files any of the foregoing (including device programming or simulation -// files), and any associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License Subscription -// Agreement, Altera MegaCore Function License Agreement, or other applicable -// license agreement, including, without limitation, that your use is for the -// sole purpose of programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the applicable -// agreement for further details. - - -// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ -// $Revision: #1 $ -// $Date: 2013/03/07 $ -// $Author: swbranch $ - -// ------------------------------------------ -// Merlin Multiplexer -// ------------------------------------------ - -`timescale 1 ns / 1 ns - - -// ------------------------------------------ -// Generation parameters: -// output_name: nios_system_rsp_xbar_mux_001 -// NUM_INPUTS: 18 -// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -// ARBITRATION_SCHEME "no-arb" -// PIPELINE_ARB: 0 -// PKT_TRANS_LOCK: 59 (arbitration locking enabled) -// ST_DATA_W: 96 -// ST_CHANNEL_W: 18 -// ------------------------------------------ - -module nios_system_rsp_xbar_mux_001 -( - // ---------------------- - // Sinks - // ---------------------- - input sink0_valid, - input [96-1 : 0] sink0_data, - input [18-1: 0] sink0_channel, - input sink0_startofpacket, - input sink0_endofpacket, - output sink0_ready, - - input sink1_valid, - input [96-1 : 0] sink1_data, - input [18-1: 0] sink1_channel, - input sink1_startofpacket, - input sink1_endofpacket, - output sink1_ready, - - input sink2_valid, - input [96-1 : 0] sink2_data, - input [18-1: 0] sink2_channel, - input sink2_startofpacket, - input sink2_endofpacket, - output sink2_ready, - - input sink3_valid, - input [96-1 : 0] sink3_data, - input [18-1: 0] sink3_channel, - input sink3_startofpacket, - input sink3_endofpacket, - output sink3_ready, - - input sink4_valid, - input [96-1 : 0] sink4_data, - input [18-1: 0] sink4_channel, - input sink4_startofpacket, - input sink4_endofpacket, - output sink4_ready, - - input sink5_valid, - input [96-1 : 0] sink5_data, - input [18-1: 0] sink5_channel, - input sink5_startofpacket, - input sink5_endofpacket, - output sink5_ready, - - input sink6_valid, - input [96-1 : 0] sink6_data, - input [18-1: 0] sink6_channel, - input sink6_startofpacket, - input sink6_endofpacket, - output sink6_ready, - - input sink7_valid, - input [96-1 : 0] sink7_data, - input [18-1: 0] sink7_channel, - input sink7_startofpacket, - input sink7_endofpacket, - output sink7_ready, - - input sink8_valid, - input [96-1 : 0] sink8_data, - input [18-1: 0] sink8_channel, - input sink8_startofpacket, - input sink8_endofpacket, - output sink8_ready, - - input sink9_valid, - input [96-1 : 0] sink9_data, - input [18-1: 0] sink9_channel, - input sink9_startofpacket, - input sink9_endofpacket, - output sink9_ready, - - input sink10_valid, - input [96-1 : 0] sink10_data, - input [18-1: 0] sink10_channel, - input sink10_startofpacket, - input sink10_endofpacket, - output sink10_ready, - - input sink11_valid, - input [96-1 : 0] sink11_data, - input [18-1: 0] sink11_channel, - input sink11_startofpacket, - input sink11_endofpacket, - output sink11_ready, - - input sink12_valid, - input [96-1 : 0] sink12_data, - input [18-1: 0] sink12_channel, - input sink12_startofpacket, - input sink12_endofpacket, - output sink12_ready, - - input sink13_valid, - input [96-1 : 0] sink13_data, - input [18-1: 0] sink13_channel, - input sink13_startofpacket, - input sink13_endofpacket, - output sink13_ready, - - input sink14_valid, - input [96-1 : 0] sink14_data, - input [18-1: 0] sink14_channel, - input sink14_startofpacket, - input sink14_endofpacket, - output sink14_ready, - - input sink15_valid, - input [96-1 : 0] sink15_data, - input [18-1: 0] sink15_channel, - input sink15_startofpacket, - input sink15_endofpacket, - output sink15_ready, - - input sink16_valid, - input [96-1 : 0] sink16_data, - input [18-1: 0] sink16_channel, - input sink16_startofpacket, - input sink16_endofpacket, - output sink16_ready, - - input sink17_valid, - input [96-1 : 0] sink17_data, - input [18-1: 0] sink17_channel, - input sink17_startofpacket, - input sink17_endofpacket, - output sink17_ready, - - - // ---------------------- - // Source - // ---------------------- - output src_valid, - output [96-1 : 0] src_data, - output [18-1 : 0] src_channel, - output src_startofpacket, - output src_endofpacket, - input src_ready, - - // ---------------------- - // Clock & Reset - // ---------------------- - input clk, - input reset -); - localparam PAYLOAD_W = 96 + 18 + 2; - localparam NUM_INPUTS = 18; - localparam SHARE_COUNTER_W = 1; - localparam PIPELINE_ARB = 0; - localparam ST_DATA_W = 96; - localparam ST_CHANNEL_W = 18; - localparam PKT_TRANS_LOCK = 59; - - // ------------------------------------------ - // Signals - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] request; - wire [NUM_INPUTS - 1 : 0] valid; - wire [NUM_INPUTS - 1 : 0] grant; - wire [NUM_INPUTS - 1 : 0] next_grant; - reg [NUM_INPUTS - 1 : 0] saved_grant; - reg [PAYLOAD_W - 1 : 0] src_payload; - wire last_cycle; - reg packet_in_progress; - reg update_grant; - - wire [PAYLOAD_W - 1 : 0] sink0_payload; - wire [PAYLOAD_W - 1 : 0] sink1_payload; - wire [PAYLOAD_W - 1 : 0] sink2_payload; - wire [PAYLOAD_W - 1 : 0] sink3_payload; - wire [PAYLOAD_W - 1 : 0] sink4_payload; - wire [PAYLOAD_W - 1 : 0] sink5_payload; - wire [PAYLOAD_W - 1 : 0] sink6_payload; - wire [PAYLOAD_W - 1 : 0] sink7_payload; - wire [PAYLOAD_W - 1 : 0] sink8_payload; - wire [PAYLOAD_W - 1 : 0] sink9_payload; - wire [PAYLOAD_W - 1 : 0] sink10_payload; - wire [PAYLOAD_W - 1 : 0] sink11_payload; - wire [PAYLOAD_W - 1 : 0] sink12_payload; - wire [PAYLOAD_W - 1 : 0] sink13_payload; - wire [PAYLOAD_W - 1 : 0] sink14_payload; - wire [PAYLOAD_W - 1 : 0] sink15_payload; - wire [PAYLOAD_W - 1 : 0] sink16_payload; - wire [PAYLOAD_W - 1 : 0] sink17_payload; - - assign valid[0] = sink0_valid; - assign valid[1] = sink1_valid; - assign valid[2] = sink2_valid; - assign valid[3] = sink3_valid; - assign valid[4] = sink4_valid; - assign valid[5] = sink5_valid; - assign valid[6] = sink6_valid; - assign valid[7] = sink7_valid; - assign valid[8] = sink8_valid; - assign valid[9] = sink9_valid; - assign valid[10] = sink10_valid; - assign valid[11] = sink11_valid; - assign valid[12] = sink12_valid; - assign valid[13] = sink13_valid; - assign valid[14] = sink14_valid; - assign valid[15] = sink15_valid; - assign valid[16] = sink16_valid; - assign valid[17] = sink17_valid; - - - // ------------------------------------------ - // ------------------------------------------ - // Grant Logic & Updates - // ------------------------------------------ - // ------------------------------------------ - reg [NUM_INPUTS - 1 : 0] lock; - always @* begin - lock[0] = sink0_data[59]; - lock[1] = sink1_data[59]; - lock[2] = sink2_data[59]; - lock[3] = sink3_data[59]; - lock[4] = sink4_data[59]; - lock[5] = sink5_data[59]; - lock[6] = sink6_data[59]; - lock[7] = sink7_data[59]; - lock[8] = sink8_data[59]; - lock[9] = sink9_data[59]; - lock[10] = sink10_data[59]; - lock[11] = sink11_data[59]; - lock[12] = sink12_data[59]; - lock[13] = sink13_data[59]; - lock[14] = sink14_data[59]; - lock[15] = sink15_data[59]; - lock[16] = sink16_data[59]; - lock[17] = sink17_data[59]; - end - - assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); - - // ------------------------------------------ - // We're working on a packet at any time valid is high, except - // when this is the endofpacket. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - packet_in_progress <= 1'b0; - end - else begin - if (src_valid) - packet_in_progress <= 1'b1; - if (last_cycle) - packet_in_progress <= 1'b0; - end - end - - - // ------------------------------------------ - // Shares - // - // Special case: all-equal shares _should_ be optimized into assigning a - // constant to next_grant_share. - // Special case: all-1's shares _should_ result in the share counter - // being optimized away. - // ------------------------------------------ - // Input | arb shares | counter load value - // 0 | 1 | 0 - // 1 | 1 | 0 - // 2 | 1 | 0 - // 3 | 1 | 0 - // 4 | 1 | 0 - // 5 | 1 | 0 - // 6 | 1 | 0 - // 7 | 1 | 0 - // 8 | 1 | 0 - // 9 | 1 | 0 - // 10 | 1 | 0 - // 11 | 1 | 0 - // 12 | 1 | 0 - // 13 | 1 | 0 - // 14 | 1 | 0 - // 15 | 1 | 0 - // 16 | 1 | 0 - // 17 | 1 | 0 - wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; - wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; - - // ------------------------------------------ - // Choose the share value corresponding to the grant. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; - always @* begin - next_grant_share = - share_0 & { SHARE_COUNTER_W {next_grant[0]} } | - share_1 & { SHARE_COUNTER_W {next_grant[1]} } | - share_2 & { SHARE_COUNTER_W {next_grant[2]} } | - share_3 & { SHARE_COUNTER_W {next_grant[3]} } | - share_4 & { SHARE_COUNTER_W {next_grant[4]} } | - share_5 & { SHARE_COUNTER_W {next_grant[5]} } | - share_6 & { SHARE_COUNTER_W {next_grant[6]} } | - share_7 & { SHARE_COUNTER_W {next_grant[7]} } | - share_8 & { SHARE_COUNTER_W {next_grant[8]} } | - share_9 & { SHARE_COUNTER_W {next_grant[9]} } | - share_10 & { SHARE_COUNTER_W {next_grant[10]} } | - share_11 & { SHARE_COUNTER_W {next_grant[11]} } | - share_12 & { SHARE_COUNTER_W {next_grant[12]} } | - share_13 & { SHARE_COUNTER_W {next_grant[13]} } | - share_14 & { SHARE_COUNTER_W {next_grant[14]} } | - share_15 & { SHARE_COUNTER_W {next_grant[15]} } | - share_16 & { SHARE_COUNTER_W {next_grant[16]} } | - share_17 & { SHARE_COUNTER_W {next_grant[17]} }; - end - - // ------------------------------------------ - // Flag to indicate first packet of an arb sequence. - // ------------------------------------------ - wire grant_changed = ~packet_in_progress && !(saved_grant & valid); - reg first_packet_r; - wire first_packet = grant_changed | first_packet_r; - always @(posedge clk or posedge reset) begin - if (reset) begin - first_packet_r <= 1'b0; - end - else begin - if (update_grant) - first_packet_r <= 1'b1; - else if (last_cycle) - first_packet_r <= 1'b0; - else if (grant_changed) - first_packet_r <= 1'b1; - end - end - - // ------------------------------------------ - // Compute the next share-count value. - // ------------------------------------------ - reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; - reg [SHARE_COUNTER_W - 1 : 0] share_count; - reg share_count_zero_flag; - - always @* begin - if (first_packet) begin - p1_share_count = next_grant_share; - end - else begin - // Update the counter, but don't decrement below 0. - p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; - end - end - - // ------------------------------------------ - // Update the share counter and share-counter=zero flag. - // ------------------------------------------ - always @(posedge clk or posedge reset) begin - if (reset) begin - share_count <= '0; - share_count_zero_flag <= 1'b1; - end - else begin - if (last_cycle) begin - share_count <= p1_share_count; - share_count_zero_flag <= (p1_share_count == '0); - end - end - end - - // ------------------------------------------ - // For each input, maintain a final_packet signal which goes active for the - // last packet of a full-share packet sequence. Example: if I have 4 - // shares and I'm continuously requesting, final_packet is active in the - // 4th packet. - // ------------------------------------------ - wire final_packet_0 = 1'b1; - - wire final_packet_1 = 1'b1; - - wire final_packet_2 = 1'b1; - - wire final_packet_3 = 1'b1; - - wire final_packet_4 = 1'b1; - - wire final_packet_5 = 1'b1; - - wire final_packet_6 = 1'b1; - - wire final_packet_7 = 1'b1; - - wire final_packet_8 = 1'b1; - - wire final_packet_9 = 1'b1; - - wire final_packet_10 = 1'b1; - - wire final_packet_11 = 1'b1; - - wire final_packet_12 = 1'b1; - - wire final_packet_13 = 1'b1; - - wire final_packet_14 = 1'b1; - - wire final_packet_15 = 1'b1; - - wire final_packet_16 = 1'b1; - - wire final_packet_17 = 1'b1; - - - // ------------------------------------------ - // Concatenate all final_packet signals (wire or reg) into a handy vector. - // ------------------------------------------ - wire [NUM_INPUTS - 1 : 0] final_packet = { - final_packet_17, - final_packet_16, - final_packet_15, - final_packet_14, - final_packet_13, - final_packet_12, - final_packet_11, - final_packet_10, - final_packet_9, - final_packet_8, - final_packet_7, - final_packet_6, - final_packet_5, - final_packet_4, - final_packet_3, - final_packet_2, - final_packet_1, - final_packet_0 - }; - - // ------------------------------------------ - // ------------------------------------------ - wire p1_done = |(final_packet & grant); - - // ------------------------------------------ - // Flag for the first cycle of packets within an - // arb sequence - // ------------------------------------------ - reg first_cycle; - always @(posedge clk, posedge reset) begin - if (reset) - first_cycle <= 0; - else - first_cycle <= last_cycle && ~p1_done; - end - - - always @* begin - update_grant = 0; - - // ------------------------------------------ - // No arbitration pipeline, update grant whenever - // the current arb winner has consumed all shares, - // or all requests are low - // ------------------------------------------ - update_grant = (last_cycle && p1_done) || (first_cycle && !valid); - update_grant = last_cycle; - end - - wire save_grant; - assign save_grant = 1; - assign grant = next_grant; - - always @(posedge clk, posedge reset) begin - if (reset) - saved_grant <= '0; - else if (save_grant) - saved_grant <= next_grant; - end - - // ------------------------------------------ - // ------------------------------------------ - // Arbitrator - // ------------------------------------------ - // ------------------------------------------ - - // ------------------------------------------ - // Create a request vector that stays high during - // the packet for unpipelined arbitration. - // - // The pipelined arbitration scheme does not require - // request to be held high during the packet. - // ------------------------------------------ - assign request = valid; - - - altera_merlin_arbitrator - #( - .NUM_REQUESTERS(NUM_INPUTS), - .SCHEME ("no-arb"), - .PIPELINE (0) - ) arb ( - .clk (clk), - .reset (reset), - .request (request), - .grant (next_grant), - .save_top_priority (src_valid), - .increment_top_priority (update_grant) - ); - - // ------------------------------------------ - // ------------------------------------------ - // Mux - // - // Implemented as a sum of products. - // ------------------------------------------ - // ------------------------------------------ - - assign sink0_ready = src_ready && grant[0]; - assign sink1_ready = src_ready && grant[1]; - assign sink2_ready = src_ready && grant[2]; - assign sink3_ready = src_ready && grant[3]; - assign sink4_ready = src_ready && grant[4]; - assign sink5_ready = src_ready && grant[5]; - assign sink6_ready = src_ready && grant[6]; - assign sink7_ready = src_ready && grant[7]; - assign sink8_ready = src_ready && grant[8]; - assign sink9_ready = src_ready && grant[9]; - assign sink10_ready = src_ready && grant[10]; - assign sink11_ready = src_ready && grant[11]; - assign sink12_ready = src_ready && grant[12]; - assign sink13_ready = src_ready && grant[13]; - assign sink14_ready = src_ready && grant[14]; - assign sink15_ready = src_ready && grant[15]; - assign sink16_ready = src_ready && grant[16]; - assign sink17_ready = src_ready && grant[17]; - - assign src_valid = |(grant & valid); - - always @* begin - src_payload = - sink0_payload & {PAYLOAD_W {grant[0]} } | - sink1_payload & {PAYLOAD_W {grant[1]} } | - sink2_payload & {PAYLOAD_W {grant[2]} } | - sink3_payload & {PAYLOAD_W {grant[3]} } | - sink4_payload & {PAYLOAD_W {grant[4]} } | - sink5_payload & {PAYLOAD_W {grant[5]} } | - sink6_payload & {PAYLOAD_W {grant[6]} } | - sink7_payload & {PAYLOAD_W {grant[7]} } | - sink8_payload & {PAYLOAD_W {grant[8]} } | - sink9_payload & {PAYLOAD_W {grant[9]} } | - sink10_payload & {PAYLOAD_W {grant[10]} } | - sink11_payload & {PAYLOAD_W {grant[11]} } | - sink12_payload & {PAYLOAD_W {grant[12]} } | - sink13_payload & {PAYLOAD_W {grant[13]} } | - sink14_payload & {PAYLOAD_W {grant[14]} } | - sink15_payload & {PAYLOAD_W {grant[15]} } | - sink16_payload & {PAYLOAD_W {grant[16]} } | - sink17_payload & {PAYLOAD_W {grant[17]} }; - end - - // ------------------------------------------ - // Mux Payload Mapping - // ------------------------------------------ - - assign sink0_payload = {sink0_channel,sink0_data, - sink0_startofpacket,sink0_endofpacket}; - assign sink1_payload = {sink1_channel,sink1_data, - sink1_startofpacket,sink1_endofpacket}; - assign sink2_payload = {sink2_channel,sink2_data, - sink2_startofpacket,sink2_endofpacket}; - assign sink3_payload = {sink3_channel,sink3_data, - sink3_startofpacket,sink3_endofpacket}; - assign sink4_payload = {sink4_channel,sink4_data, - sink4_startofpacket,sink4_endofpacket}; - assign sink5_payload = {sink5_channel,sink5_data, - sink5_startofpacket,sink5_endofpacket}; - assign sink6_payload = {sink6_channel,sink6_data, - sink6_startofpacket,sink6_endofpacket}; - assign sink7_payload = {sink7_channel,sink7_data, - sink7_startofpacket,sink7_endofpacket}; - assign sink8_payload = {sink8_channel,sink8_data, - sink8_startofpacket,sink8_endofpacket}; - assign sink9_payload = {sink9_channel,sink9_data, - sink9_startofpacket,sink9_endofpacket}; - assign sink10_payload = {sink10_channel,sink10_data, - sink10_startofpacket,sink10_endofpacket}; - assign sink11_payload = {sink11_channel,sink11_data, - sink11_startofpacket,sink11_endofpacket}; - assign sink12_payload = {sink12_channel,sink12_data, - sink12_startofpacket,sink12_endofpacket}; - assign sink13_payload = {sink13_channel,sink13_data, - sink13_startofpacket,sink13_endofpacket}; - assign sink14_payload = {sink14_channel,sink14_data, - sink14_startofpacket,sink14_endofpacket}; - assign sink15_payload = {sink15_channel,sink15_data, - sink15_startofpacket,sink15_endofpacket}; - assign sink16_payload = {sink16_channel,sink16_data, - sink16_startofpacket,sink16_endofpacket}; - assign sink17_payload = {sink17_channel,sink17_data, - sink17_startofpacket,sink17_endofpacket}; - - assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; - -endmodule - - - +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/13.0sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2013/03/07 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: nios_system_rsp_xbar_mux_001 +// NUM_INPUTS: 18 +// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 59 (arbitration locking enabled) +// ST_DATA_W: 96 +// ST_CHANNEL_W: 18 +// ------------------------------------------ + +module nios_system_rsp_xbar_mux_001 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [96-1 : 0] sink0_data, + input [18-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [96-1 : 0] sink1_data, + input [18-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + input sink2_valid, + input [96-1 : 0] sink2_data, + input [18-1: 0] sink2_channel, + input sink2_startofpacket, + input sink2_endofpacket, + output sink2_ready, + + input sink3_valid, + input [96-1 : 0] sink3_data, + input [18-1: 0] sink3_channel, + input sink3_startofpacket, + input sink3_endofpacket, + output sink3_ready, + + input sink4_valid, + input [96-1 : 0] sink4_data, + input [18-1: 0] sink4_channel, + input sink4_startofpacket, + input sink4_endofpacket, + output sink4_ready, + + input sink5_valid, + input [96-1 : 0] sink5_data, + input [18-1: 0] sink5_channel, + input sink5_startofpacket, + input sink5_endofpacket, + output sink5_ready, + + input sink6_valid, + input [96-1 : 0] sink6_data, + input [18-1: 0] sink6_channel, + input sink6_startofpacket, + input sink6_endofpacket, + output sink6_ready, + + input sink7_valid, + input [96-1 : 0] sink7_data, + input [18-1: 0] sink7_channel, + input sink7_startofpacket, + input sink7_endofpacket, + output sink7_ready, + + input sink8_valid, + input [96-1 : 0] sink8_data, + input [18-1: 0] sink8_channel, + input sink8_startofpacket, + input sink8_endofpacket, + output sink8_ready, + + input sink9_valid, + input [96-1 : 0] sink9_data, + input [18-1: 0] sink9_channel, + input sink9_startofpacket, + input sink9_endofpacket, + output sink9_ready, + + input sink10_valid, + input [96-1 : 0] sink10_data, + input [18-1: 0] sink10_channel, + input sink10_startofpacket, + input sink10_endofpacket, + output sink10_ready, + + input sink11_valid, + input [96-1 : 0] sink11_data, + input [18-1: 0] sink11_channel, + input sink11_startofpacket, + input sink11_endofpacket, + output sink11_ready, + + input sink12_valid, + input [96-1 : 0] sink12_data, + input [18-1: 0] sink12_channel, + input sink12_startofpacket, + input sink12_endofpacket, + output sink12_ready, + + input sink13_valid, + input [96-1 : 0] sink13_data, + input [18-1: 0] sink13_channel, + input sink13_startofpacket, + input sink13_endofpacket, + output sink13_ready, + + input sink14_valid, + input [96-1 : 0] sink14_data, + input [18-1: 0] sink14_channel, + input sink14_startofpacket, + input sink14_endofpacket, + output sink14_ready, + + input sink15_valid, + input [96-1 : 0] sink15_data, + input [18-1: 0] sink15_channel, + input sink15_startofpacket, + input sink15_endofpacket, + output sink15_ready, + + input sink16_valid, + input [96-1 : 0] sink16_data, + input [18-1: 0] sink16_channel, + input sink16_startofpacket, + input sink16_endofpacket, + output sink16_ready, + + input sink17_valid, + input [96-1 : 0] sink17_data, + input [18-1: 0] sink17_channel, + input sink17_startofpacket, + input sink17_endofpacket, + output sink17_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [96-1 : 0] src_data, + output [18-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 96 + 18 + 2; + localparam NUM_INPUTS = 18; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 96; + localparam ST_CHANNEL_W = 18; + localparam PKT_TRANS_LOCK = 59; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + wire [PAYLOAD_W - 1 : 0] sink2_payload; + wire [PAYLOAD_W - 1 : 0] sink3_payload; + wire [PAYLOAD_W - 1 : 0] sink4_payload; + wire [PAYLOAD_W - 1 : 0] sink5_payload; + wire [PAYLOAD_W - 1 : 0] sink6_payload; + wire [PAYLOAD_W - 1 : 0] sink7_payload; + wire [PAYLOAD_W - 1 : 0] sink8_payload; + wire [PAYLOAD_W - 1 : 0] sink9_payload; + wire [PAYLOAD_W - 1 : 0] sink10_payload; + wire [PAYLOAD_W - 1 : 0] sink11_payload; + wire [PAYLOAD_W - 1 : 0] sink12_payload; + wire [PAYLOAD_W - 1 : 0] sink13_payload; + wire [PAYLOAD_W - 1 : 0] sink14_payload; + wire [PAYLOAD_W - 1 : 0] sink15_payload; + wire [PAYLOAD_W - 1 : 0] sink16_payload; + wire [PAYLOAD_W - 1 : 0] sink17_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + assign valid[2] = sink2_valid; + assign valid[3] = sink3_valid; + assign valid[4] = sink4_valid; + assign valid[5] = sink5_valid; + assign valid[6] = sink6_valid; + assign valid[7] = sink7_valid; + assign valid[8] = sink8_valid; + assign valid[9] = sink9_valid; + assign valid[10] = sink10_valid; + assign valid[11] = sink11_valid; + assign valid[12] = sink12_valid; + assign valid[13] = sink13_valid; + assign valid[14] = sink14_valid; + assign valid[15] = sink15_valid; + assign valid[16] = sink16_valid; + assign valid[17] = sink17_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[59]; + lock[1] = sink1_data[59]; + lock[2] = sink2_data[59]; + lock[3] = sink3_data[59]; + lock[4] = sink4_data[59]; + lock[5] = sink5_data[59]; + lock[6] = sink6_data[59]; + lock[7] = sink7_data[59]; + lock[8] = sink8_data[59]; + lock[9] = sink9_data[59]; + lock[10] = sink10_data[59]; + lock[11] = sink11_data[59]; + lock[12] = sink12_data[59]; + lock[13] = sink13_data[59]; + lock[14] = sink14_data[59]; + lock[15] = sink15_data[59]; + lock[16] = sink16_data[59]; + lock[17] = sink17_data[59]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + // 2 | 1 | 0 + // 3 | 1 | 0 + // 4 | 1 | 0 + // 5 | 1 | 0 + // 6 | 1 | 0 + // 7 | 1 | 0 + // 8 | 1 | 0 + // 9 | 1 | 0 + // 10 | 1 | 0 + // 11 | 1 | 0 + // 12 | 1 | 0 + // 13 | 1 | 0 + // 14 | 1 | 0 + // 15 | 1 | 0 + // 16 | 1 | 0 + // 17 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_11 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_12 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_13 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_14 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_15 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_16 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_17 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} } | + share_2 & { SHARE_COUNTER_W {next_grant[2]} } | + share_3 & { SHARE_COUNTER_W {next_grant[3]} } | + share_4 & { SHARE_COUNTER_W {next_grant[4]} } | + share_5 & { SHARE_COUNTER_W {next_grant[5]} } | + share_6 & { SHARE_COUNTER_W {next_grant[6]} } | + share_7 & { SHARE_COUNTER_W {next_grant[7]} } | + share_8 & { SHARE_COUNTER_W {next_grant[8]} } | + share_9 & { SHARE_COUNTER_W {next_grant[9]} } | + share_10 & { SHARE_COUNTER_W {next_grant[10]} } | + share_11 & { SHARE_COUNTER_W {next_grant[11]} } | + share_12 & { SHARE_COUNTER_W {next_grant[12]} } | + share_13 & { SHARE_COUNTER_W {next_grant[13]} } | + share_14 & { SHARE_COUNTER_W {next_grant[14]} } | + share_15 & { SHARE_COUNTER_W {next_grant[15]} } | + share_16 & { SHARE_COUNTER_W {next_grant[16]} } | + share_17 & { SHARE_COUNTER_W {next_grant[17]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + wire final_packet_2 = 1'b1; + + wire final_packet_3 = 1'b1; + + wire final_packet_4 = 1'b1; + + wire final_packet_5 = 1'b1; + + wire final_packet_6 = 1'b1; + + wire final_packet_7 = 1'b1; + + wire final_packet_8 = 1'b1; + + wire final_packet_9 = 1'b1; + + wire final_packet_10 = 1'b1; + + wire final_packet_11 = 1'b1; + + wire final_packet_12 = 1'b1; + + wire final_packet_13 = 1'b1; + + wire final_packet_14 = 1'b1; + + wire final_packet_15 = 1'b1; + + wire final_packet_16 = 1'b1; + + wire final_packet_17 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_17, + final_packet_16, + final_packet_15, + final_packet_14, + final_packet_13, + final_packet_12, + final_packet_11, + final_packet_10, + final_packet_9, + final_packet_8, + final_packet_7, + final_packet_6, + final_packet_5, + final_packet_4, + final_packet_3, + final_packet_2, + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + assign sink2_ready = src_ready && grant[2]; + assign sink3_ready = src_ready && grant[3]; + assign sink4_ready = src_ready && grant[4]; + assign sink5_ready = src_ready && grant[5]; + assign sink6_ready = src_ready && grant[6]; + assign sink7_ready = src_ready && grant[7]; + assign sink8_ready = src_ready && grant[8]; + assign sink9_ready = src_ready && grant[9]; + assign sink10_ready = src_ready && grant[10]; + assign sink11_ready = src_ready && grant[11]; + assign sink12_ready = src_ready && grant[12]; + assign sink13_ready = src_ready && grant[13]; + assign sink14_ready = src_ready && grant[14]; + assign sink15_ready = src_ready && grant[15]; + assign sink16_ready = src_ready && grant[16]; + assign sink17_ready = src_ready && grant[17]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} } | + sink2_payload & {PAYLOAD_W {grant[2]} } | + sink3_payload & {PAYLOAD_W {grant[3]} } | + sink4_payload & {PAYLOAD_W {grant[4]} } | + sink5_payload & {PAYLOAD_W {grant[5]} } | + sink6_payload & {PAYLOAD_W {grant[6]} } | + sink7_payload & {PAYLOAD_W {grant[7]} } | + sink8_payload & {PAYLOAD_W {grant[8]} } | + sink9_payload & {PAYLOAD_W {grant[9]} } | + sink10_payload & {PAYLOAD_W {grant[10]} } | + sink11_payload & {PAYLOAD_W {grant[11]} } | + sink12_payload & {PAYLOAD_W {grant[12]} } | + sink13_payload & {PAYLOAD_W {grant[13]} } | + sink14_payload & {PAYLOAD_W {grant[14]} } | + sink15_payload & {PAYLOAD_W {grant[15]} } | + sink16_payload & {PAYLOAD_W {grant[16]} } | + sink17_payload & {PAYLOAD_W {grant[17]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + assign sink2_payload = {sink2_channel,sink2_data, + sink2_startofpacket,sink2_endofpacket}; + assign sink3_payload = {sink3_channel,sink3_data, + sink3_startofpacket,sink3_endofpacket}; + assign sink4_payload = {sink4_channel,sink4_data, + sink4_startofpacket,sink4_endofpacket}; + assign sink5_payload = {sink5_channel,sink5_data, + sink5_startofpacket,sink5_endofpacket}; + assign sink6_payload = {sink6_channel,sink6_data, + sink6_startofpacket,sink6_endofpacket}; + assign sink7_payload = {sink7_channel,sink7_data, + sink7_startofpacket,sink7_endofpacket}; + assign sink8_payload = {sink8_channel,sink8_data, + sink8_startofpacket,sink8_endofpacket}; + assign sink9_payload = {sink9_channel,sink9_data, + sink9_startofpacket,sink9_endofpacket}; + assign sink10_payload = {sink10_channel,sink10_data, + sink10_startofpacket,sink10_endofpacket}; + assign sink11_payload = {sink11_channel,sink11_data, + sink11_startofpacket,sink11_endofpacket}; + assign sink12_payload = {sink12_channel,sink12_data, + sink12_startofpacket,sink12_endofpacket}; + assign sink13_payload = {sink13_channel,sink13_data, + sink13_startofpacket,sink13_endofpacket}; + assign sink14_payload = {sink14_channel,sink14_data, + sink14_startofpacket,sink14_endofpacket}; + assign sink15_payload = {sink15_channel,sink15_data, + sink15_startofpacket,sink15_endofpacket}; + assign sink16_payload = {sink16_channel,sink16_data, + sink16_startofpacket,sink16_endofpacket}; + assign sink17_payload = {sink17_channel,sink17_data, + sink17_startofpacket,sink17_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/nios_system/synthesis/submodules/nios_system_switches.v b/nios_system/synthesis/submodules/nios_system_switches.v index 5121337..1fd0e98 100644 --- a/nios_system/synthesis/submodules/nios_system_switches.v +++ b/nios_system/synthesis/submodules/nios_system_switches.v @@ -1,58 +1,58 @@ -//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your -//use of Altera Corporation's design tools, logic functions and other -//software and tools, and its AMPP partner logic functions, and any -//output files any of the foregoing (including device programming or -//simulation files), and any associated documentation or information are -//expressly subject to the terms and conditions of the Altera Program -//License Subscription Agreement or other applicable license agreement, -//including, without limitation, that your use is for the sole purpose -//of programming logic devices manufactured by Altera and sold by Altera -//or its authorized distributors. Please refer to the applicable -//agreement for further details. - -// synthesis translate_off -`timescale 1ns / 1ps -// synthesis translate_on - -// turn off superfluous verilog processor warnings -// altera message_level Level1 -// altera message_off 10034 10035 10036 10037 10230 10240 10030 - -module nios_system_switches ( - // inputs: - address, - clk, - in_port, - reset_n, - - // outputs: - readdata - ) -; - - output [ 31: 0] readdata; - input [ 1: 0] address; - input clk; - input [ 17: 0] in_port; - input reset_n; - - wire clk_en; - wire [ 17: 0] data_in; - wire [ 17: 0] read_mux_out; - reg [ 31: 0] readdata; - assign clk_en = 1; - //s1, which is an e_avalon_slave - assign read_mux_out = {18 {(address == 0)}} & data_in; - always @(posedge clk or negedge reset_n) - begin - if (reset_n == 0) - readdata <= 0; - else if (clk_en) - readdata <= {32'b0 | read_mux_out}; - end - - - assign data_in = in_port; - -endmodule - +//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module nios_system_switches ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 17: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 17: 0] data_in; + wire [ 17: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {18 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/nios_system_generation.rpt b/nios_system_generation.rpt index 512cd5a..b559a41 100644 --- a/nios_system_generation.rpt +++ b/nios_system_generation.rpt @@ -1,5 +1,5 @@ Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys +Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys Progress: Loading qsys_tutorial/nios_system.qsys Progress: Reading input file Progress: Adding clk_0 [clock_source 13.0] @@ -8,22 +8,49 @@ Progress: Parameterizing module nios2_processor Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] Progress: Parameterizing module jtag_uart Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] Progress: Parameterizing module LEDs +Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module LEDRs +Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module switches +Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module push_switches +Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex0 +Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex1 +Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex2 +Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex3 +Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex4 +Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex5 +Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex6 +Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex7 +Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] +Progress: Parameterizing module lcd_16207_0 +Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_on +Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_blon Progress: Building connections Progress: Parameterizing connections Progress: Validating Progress: Done reading input file Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: ip-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys --language=VERILOG +Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG Progress: Loading qsys_tutorial/nios_system.qsys Progress: Reading input file Progress: Adding clk_0 [clock_source 13.0] @@ -32,27 +59,145 @@ Progress: Parameterizing module nios2_processor Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] Progress: Parameterizing module jtag_uart Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] Progress: Parameterizing module LEDs +Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module LEDRs +Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module switches +Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module push_switches +Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex0 +Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex1 +Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex2 +Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex3 +Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex4 +Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex5 +Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex6 +Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module hex7 +Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] +Progress: Parameterizing module lcd_16207_0 +Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_on +Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] +Progress: Parameterizing module lcd_blon Progress: Building connections Progress: Parameterizing connections Progress: Validating Progress: Done reading input file Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 6 modules, 23 connections +Info: pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 13 modules, 51 connections -Info: merlin_domain_transform: After transform: 26 modules, 137 connections -Info: merlin_router_transform: After transform: 33 modules, 165 connections -Info: reset_adaptation_transform: After transform: 34 modules, 130 connections -Info: merlin_network_to_switch_transform: After transform: 47 modules, 158 connections -Info: merlin_mm_transform: After transform: 47 modules, 158 connections -Info: merlin_interrupt_mapper_transform: After transform: 48 modules, 161 connections +Info: merlin_translator_transform: After transform: 39 modules, 155 connections +Info: merlin_domain_transform: After transform: 78 modules, 423 connections +Info: merlin_router_transform: After transform: 98 modules, 503 connections +Info: reset_adaptation_transform: After transform: 99 modules, 390 connections +Info: merlin_network_to_switch_transform: After transform: 138 modules, 470 connections +Info: merlin_mm_transform: After transform: 138 modules, 470 connections +Info: merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" @@ -99,37 +244,57 @@ Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.10.13 16:14:14 (*) Starting Nios II generation -Info: nios2_processor: # 2016.10.13 16:14:14 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.10.13 16:14:14 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.10.13 16:14:14 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.10.13 16:14:14 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.10.13 16:14:14 (*) Plaintext license not found. -Info: nios2_processor: # 2016.10.13 16:14:14 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.10.13 16:14:14 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.10.13 16:14:14 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.10.13 16:14:16 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.10.13 16:14:16 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.10.13 16:14:18 (*) Done Nios II generation +Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: nios2_processor: # 2016.12.22 10:06:19 (*) Starting Nios II generation +Info: nios2_processor: # 2016.12.22 10:06:19 (*) Checking for plaintext license. +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: nios2_processor: # 2016.12.22 10:06:20 (*) LM_LICENSE_FILE environment variable is empty +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Plaintext license not found. +Info: nios2_processor: # 2016.12.22 10:06:20 (*) No license required to generate encrypted Nios II/e. +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Elaborating CPU configuration settings +Info: nios2_processor: # 2016.12.22 10:06:20 (*) Creating all objects for CPU +Info: nios2_processor: # 2016.12.22 10:06:21 (*) Generating RTL from CPU objects +Info: nios2_processor: # 2016.12.22 10:06:21 (*) Creating plain-text RTL +Info: nios2_processor: # 2016.12.22 10:06:23 (*) Done Nios II generation Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] +Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0003_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0003_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0004_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0004_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] +Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0005_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_588662107794788817.dir/0005_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] +Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] Info: LEDs: Done RTL generation for module 'nios_system_LEDs' Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" +Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' +Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] +Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' +Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" +Info: switches: Starting RTL generation for module 'nios_system_switches' +Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] +Info: switches: Done RTL generation for module 'nios_system_switches' +Info: switches: "nios_system" instantiated altera_avalon_pio "switches" +Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' +Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] +Info: push_switches: Done RTL generation for module 'nios_system_push_switches' +Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" +Info: hex0: Starting RTL generation for module 'nios_system_hex0' +Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] +Info: hex0: Done RTL generation for module 'nios_system_hex0' +Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" +Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' +Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] +Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' +Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" +Info: lcd_on: Starting RTL generation for module 'nios_system_lcd_on' +Info: lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_1122251059548229496.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] +Info: lcd_on: Done RTL generation for module 'nios_system_lcd_on' +Info: lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" @@ -145,10 +310,10 @@ Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 23 modules, 64 files, 1233875 bytes +Info: nios_system: Done nios_system" with 28 modules, 155 files, 4086283 bytes Info: ip-generate succeeded. Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_1.rpt b/nios_system_generation_1.rpt deleted file mode 100644 index 2896051..0000000 --- a/nios_system_generation_1.rpt +++ /dev/null @@ -1,154 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 6 modules, 23 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 13 modules, 51 connections -Info: merlin_domain_transform: After transform: 26 modules, 137 connections -Info: merlin_router_transform: After transform: 33 modules, 165 connections -Info: reset_adaptation_transform: After transform: 34 modules, 130 connections -Info: merlin_network_to_switch_transform: After transform: 47 modules, 158 connections -Info: merlin_mm_transform: After transform: 47 modules, 158 connections -Info: merlin_interrupt_mapper_transform: After transform: 48 modules, 161 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.10.13 16:58:12 (*) Starting Nios II generation -Info: nios2_processor: # 2016.10.13 16:58:12 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.10.13 16:58:12 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.10.13 16:58:12 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.10.13 16:58:12 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.10.13 16:58:12 (*) Plaintext license not found. -Info: nios2_processor: # 2016.10.13 16:58:12 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.10.13 16:58:12 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.10.13 16:58:12 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.10.13 16:58:13 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.10.13 16:58:13 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.10.13 16:58:15 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0003_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0003_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0004_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0004_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0005_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7087_8164123695301960079.dir/0005_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 23 modules, 64 files, 1233875 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_10.rpt b/nios_system_generation_10.rpt deleted file mode 100644 index d44873f..0000000 --- a/nios_system_generation_10.rpt +++ /dev/null @@ -1,186 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 8 modules, 31 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 17 modules, 67 connections -Info: merlin_domain_transform: After transform: 34 modules, 181 connections -Info: merlin_router_transform: After transform: 43 modules, 217 connections -Info: reset_adaptation_transform: After transform: 44 modules, 170 connections -Info: merlin_network_to_switch_transform: After transform: 61 modules, 206 connections -Info: merlin_mm_transform: After transform: 61 modules, 206 connections -Info: merlin_interrupt_mapper_transform: After transform: 62 modules, 209 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0068_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0068_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.11.10 10:13:30 (*) Starting Nios II generation -Info: nios2_processor: # 2016.11.10 10:13:30 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.11.10 10:13:30 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.11.10 10:13:30 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.11.10 10:13:30 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.11.10 10:13:30 (*) Plaintext license not found. -Info: nios2_processor: # 2016.11.10 10:13:30 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.11.10 10:13:30 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.11.10 10:13:30 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.11.10 10:13:31 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.11.10 10:13:31 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.11.10 10:13:33 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0069_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0069_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0070_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0070_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0071_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0071_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0072_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0072_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0073_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0073_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0074_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0074_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 25 modules, 78 files, 1510254 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_11.rpt b/nios_system_generation_11.rpt deleted file mode 100644 index 2175699..0000000 --- a/nios_system_generation_11.rpt +++ /dev/null @@ -1,186 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 8 modules, 31 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 17 modules, 67 connections -Info: merlin_domain_transform: After transform: 34 modules, 181 connections -Info: merlin_router_transform: After transform: 43 modules, 217 connections -Info: reset_adaptation_transform: After transform: 44 modules, 170 connections -Info: merlin_network_to_switch_transform: After transform: 61 modules, 206 connections -Info: merlin_mm_transform: After transform: 61 modules, 206 connections -Info: merlin_interrupt_mapper_transform: After transform: 62 modules, 209 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0091_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0091_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.11.10 10:40:15 (*) Starting Nios II generation -Info: nios2_processor: # 2016.11.10 10:40:15 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.11.10 10:40:15 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.11.10 10:40:15 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.11.10 10:40:15 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.11.10 10:40:15 (*) Plaintext license not found. -Info: nios2_processor: # 2016.11.10 10:40:15 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.11.10 10:40:15 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.11.10 10:40:15 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.11.10 10:40:16 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.11.10 10:40:16 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.11.10 10:40:19 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0092_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0092_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0093_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0093_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0094_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0094_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0095_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0095_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0096_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0096_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0097_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0097_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 25 modules, 78 files, 1510254 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_12.rpt b/nios_system_generation_12.rpt deleted file mode 100644 index 7c54d23..0000000 --- a/nios_system_generation_12.rpt +++ /dev/null @@ -1,278 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 16 modules, 63 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 33 modules, 131 connections -Info: merlin_domain_transform: After transform: 66 modules, 357 connections -Info: merlin_router_transform: After transform: 83 modules, 425 connections -Info: reset_adaptation_transform: After transform: 84 modules, 330 connections -Info: merlin_network_to_switch_transform: After transform: 117 modules, 398 connections -Info: merlin_mm_transform: After transform: 117 modules, 398 connections -Info: merlin_interrupt_mapper_transform: After transform: 118 modules, 401 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.11.17 09:23:48 (*) Starting Nios II generation -Info: nios2_processor: # 2016.11.17 09:23:48 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.11.17 09:23:49 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.11.17 09:23:49 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.11.17 09:23:49 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.11.17 09:23:49 (*) Plaintext license not found. -Info: nios2_processor: # 2016.11.17 09:23:49 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.11.17 09:23:49 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.11.17 09:23:49 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.11.17 09:23:50 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.11.17 09:23:50 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.11.17 09:23:52 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7122_4250281716460532653.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 26 modules, 134 files, 2613303 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_13.rpt b/nios_system_generation_13.rpt deleted file mode 100644 index c5494fe..0000000 --- a/nios_system_generation_13.rpt +++ /dev/null @@ -1,278 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 16 modules, 63 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 33 modules, 131 connections -Info: merlin_domain_transform: After transform: 66 modules, 357 connections -Info: merlin_router_transform: After transform: 83 modules, 425 connections -Info: reset_adaptation_transform: After transform: 84 modules, 330 connections -Info: merlin_network_to_switch_transform: After transform: 117 modules, 398 connections -Info: merlin_mm_transform: After transform: 117 modules, 398 connections -Info: merlin_interrupt_mapper_transform: After transform: 118 modules, 401 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.11.25 16:56:17 (*) Starting Nios II generation -Info: nios2_processor: # 2016.11.25 16:56:17 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.11.25 16:56:18 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.11.25 16:56:18 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.11.25 16:56:18 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.11.25 16:56:18 (*) Plaintext license not found. -Info: nios2_processor: # 2016.11.25 16:56:18 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.11.25 16:56:18 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.11.25 16:56:18 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.11.25 16:56:19 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.11.25 16:56:19 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.11.25 16:56:21 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7130_2991110928299906872.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 26 modules, 134 files, 2677815 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_14.rpt b/nios_system_generation_14.rpt deleted file mode 100644 index e784d71..0000000 --- a/nios_system_generation_14.rpt +++ /dev/null @@ -1,293 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 17 modules, 67 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 35 modules, 139 connections -Info: merlin_domain_transform: After transform: 70 modules, 379 connections -Info: merlin_router_transform: After transform: 88 modules, 451 connections -Info: reset_adaptation_transform: After transform: 89 modules, 350 connections -Info: merlin_network_to_switch_transform: After transform: 124 modules, 422 connections -Info: merlin_mm_transform: After transform: 124 modules, 422 connections -Info: merlin_interrupt_mapper_transform: After transform: 125 modules, 425 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.01 22:08:05 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.01 22:08:05 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.01 22:08:06 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.01 22:08:06 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.01 22:08:06 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.01 22:08:06 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.01 22:08:06 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.01 22:08:06 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.01 22:08:06 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.01 22:08:07 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.01 22:08:07 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.01 22:08:09 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd: Starting RTL generation for module 'nios_system_lcd' -Info: lcd: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0009_lcd_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0009_lcd_gen//nios_system_lcd_component_configuration.pl --do_build_sim=0 ] -Info: lcd: Done RTL generation for module 'nios_system_lcd' -Info: lcd: "nios_system" instantiated altera_avalon_lcd_16207 "lcd" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 27 modules, 141 files, 2818453 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_15.rpt b/nios_system_generation_15.rpt deleted file mode 100644 index afb37ec..0000000 --- a/nios_system_generation_15.rpt +++ /dev/null @@ -1,293 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 17 modules, 67 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 35 modules, 139 connections -Info: merlin_domain_transform: After transform: 70 modules, 379 connections -Info: merlin_router_transform: After transform: 88 modules, 451 connections -Info: reset_adaptation_transform: After transform: 89 modules, 350 connections -Info: merlin_network_to_switch_transform: After transform: 124 modules, 422 connections -Info: merlin_mm_transform: After transform: 124 modules, 422 connections -Info: merlin_interrupt_mapper_transform: After transform: 125 modules, 425 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0026_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0026_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.01 22:29:13 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.01 22:29:13 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.01 22:29:13 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.01 22:29:13 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.01 22:29:13 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.01 22:29:13 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.01 22:29:13 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.01 22:29:13 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.01 22:29:13 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.01 22:29:15 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.01 22:29:15 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.01 22:29:17 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0027_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0027_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0028_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0028_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0029_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0029_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0030_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0030_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0031_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0031_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0032_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0032_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0033_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0033_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd: Starting RTL generation for module 'nios_system_lcd' -Info: lcd: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0034_lcd_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0034_lcd_gen//nios_system_lcd_component_configuration.pl --do_build_sim=0 ] -Info: lcd: Done RTL generation for module 'nios_system_lcd' -Info: lcd: "nios_system" instantiated altera_avalon_lcd_16207 "lcd" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 27 modules, 141 files, 2818453 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_16.rpt b/nios_system_generation_16.rpt deleted file mode 100644 index 7328a6e..0000000 --- a/nios_system_generation_16.rpt +++ /dev/null @@ -1,326 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 20 modules, 79 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 41 modules, 163 connections -Info: merlin_domain_transform: After transform: 82 modules, 445 connections -Info: merlin_router_transform: After transform: 103 modules, 529 connections -Info: reset_adaptation_transform: After transform: 104 modules, 410 connections -Info: merlin_network_to_switch_transform: After transform: 145 modules, 494 connections -Info: merlin_mm_transform: After transform: 145 modules, 494 connections -Info: merlin_interrupt_mapper_transform: After transform: 146 modules, 497 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0051_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0051_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.01 23:13:10 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.01 23:13:10 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.01 23:13:10 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.01 23:13:10 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.01 23:13:10 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.01 23:13:10 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.01 23:13:10 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.01 23:13:10 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.01 23:13:10 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.01 23:13:11 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.01 23:13:11 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.01 23:13:13 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0052_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0052_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0053_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0053_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0054_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0054_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0055_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0055_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0056_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0056_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0057_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0057_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0058_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0058_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_E: Starting RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_E --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0059_lcd_E_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0059_lcd_E_gen//nios_system_lcd_E_component_configuration.pl --do_build_sim=0 ] -Info: lcd_E: Done RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: "nios_system" instantiated altera_avalon_pio "lcd_E" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 27 modules, 162 files, 3231032 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_17.rpt b/nios_system_generation_17.rpt deleted file mode 100644 index b1bbf7e..0000000 --- a/nios_system_generation_17.rpt +++ /dev/null @@ -1,337 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Warning: nios_system.lcd_16207_0: lcd_16207_0.external must be exported, or connected to a matching conduit. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Warning: nios_system.lcd_16207_0: lcd_16207_0.external must be exported, or connected to a matching conduit. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 21 modules, 82 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 42 modules, 166 connections -Info: merlin_domain_transform: After transform: 83 modules, 448 connections -Info: merlin_router_transform: After transform: 104 modules, 532 connections -Info: reset_adaptation_transform: After transform: 105 modules, 412 connections -Info: merlin_network_to_switch_transform: After transform: 146 modules, 496 connections -Info: merlin_mm_transform: After transform: 146 modules, 496 connections -Info: merlin_interrupt_mapper_transform: After transform: 147 modules, 499 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0076_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0076_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.01 23:35:35 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.01 23:35:35 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.01 23:35:35 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.01 23:35:35 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.01 23:35:35 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.01 23:35:35 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.01 23:35:35 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.01 23:35:35 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.01 23:35:35 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.01 23:35:37 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.01 23:35:37 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.01 23:35:39 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0077_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0077_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0078_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0078_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0079_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0079_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0080_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0080_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0081_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0081_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0082_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0082_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0083_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0083_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_E: Starting RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_E --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0084_lcd_E_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0084_lcd_E_gen//nios_system_lcd_E_component_configuration.pl --do_build_sim=0 ] -Info: lcd_E: Done RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: "nios_system" instantiated altera_avalon_pio "lcd_E" -Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0085_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0085_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 28 modules, 163 files, 3234959 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_18.rpt b/nios_system_generation_18.rpt deleted file mode 100644 index d42ec4f..0000000 --- a/nios_system_generation_18.rpt +++ /dev/null @@ -1,344 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Warning: nios_system.lcd_16207_0: lcd_16207_0.external must be exported, or connected to a matching conduit. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Warning: nios_system.lcd_16207_0: lcd_16207_0.external must be exported, or connected to a matching conduit. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 21 modules, 84 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 43 modules, 172 connections -Info: merlin_domain_transform: After transform: 86 modules, 467 connections -Info: merlin_router_transform: After transform: 108 modules, 555 connections -Info: reset_adaptation_transform: After transform: 109 modules, 430 connections -Info: merlin_network_to_switch_transform: After transform: 152 modules, 520 connections -Info: merlin_mm_transform: After transform: 152 modules, 520 connections -Info: merlin_interrupt_mapper_transform: After transform: 153 modules, 523 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0102_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0102_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.01 23:42:50 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.01 23:42:50 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.01 23:42:51 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.01 23:42:51 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.01 23:42:51 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.01 23:42:51 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.01 23:42:51 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.01 23:42:51 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.01 23:42:51 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.01 23:42:52 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.01 23:42:52 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.01 23:42:54 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0103_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0103_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0104_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0104_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0105_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0105_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0106_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0106_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0107_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0107_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0108_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0108_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0109_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0109_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_E: Starting RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_E --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0110_lcd_E_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0110_lcd_E_gen//nios_system_lcd_E_component_configuration.pl --do_build_sim=0 ] -Info: lcd_E: Done RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: "nios_system" instantiated altera_avalon_pio "lcd_E" -Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0111_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0111_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_003: "nios_system" instantiated altera_merlin_router "id_router_003" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" -Info: rsp_xbar_demux_003: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_003" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 29 modules, 171 files, 3402353 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_19.rpt b/nios_system_generation_19.rpt deleted file mode 100644 index c624b77..0000000 --- a/nios_system_generation_19.rpt +++ /dev/null @@ -1,342 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Adding lcd_data [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_data -Progress: Adding lcd_E [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_E -Progress: Adding lcd_RS [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RS -Progress: Adding lcd_RW [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_RW -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 21 modules, 84 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 43 modules, 172 connections -Info: merlin_domain_transform: After transform: 86 modules, 467 connections -Info: merlin_router_transform: After transform: 108 modules, 555 connections -Info: reset_adaptation_transform: After transform: 109 modules, 430 connections -Info: merlin_network_to_switch_transform: After transform: 152 modules, 520 connections -Info: merlin_mm_transform: After transform: 152 modules, 520 connections -Info: merlin_interrupt_mapper_transform: After transform: 153 modules, 523 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0129_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0129_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.01 23:44:38 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.01 23:44:38 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.01 23:44:39 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.01 23:44:39 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.01 23:44:39 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.01 23:44:39 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.01 23:44:39 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.01 23:44:39 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.01 23:44:39 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.01 23:44:40 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.01 23:44:40 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.01 23:44:42 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0130_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0130_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0131_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0131_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0132_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0132_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0133_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0133_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0134_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0134_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0135_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0135_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0136_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0136_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_E: Starting RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_E --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0137_lcd_E_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0137_lcd_E_gen//nios_system_lcd_E_component_configuration.pl --do_build_sim=0 ] -Info: lcd_E: Done RTL generation for module 'nios_system_lcd_E' -Info: lcd_E: "nios_system" instantiated altera_avalon_pio "lcd_E" -Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0138_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0138_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_003: "nios_system" instantiated altera_merlin_router "id_router_003" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" -Info: rsp_xbar_demux_003: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_003" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 29 modules, 171 files, 3402606 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_2.rpt b/nios_system_generation_2.rpt deleted file mode 100644 index ecb627d..0000000 --- a/nios_system_generation_2.rpt +++ /dev/null @@ -1,154 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 6 modules, 23 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 13 modules, 51 connections -Info: merlin_domain_transform: After transform: 26 modules, 137 connections -Info: merlin_router_transform: After transform: 33 modules, 165 connections -Info: reset_adaptation_transform: After transform: 34 modules, 130 connections -Info: merlin_network_to_switch_transform: After transform: 47 modules, 158 connections -Info: merlin_mm_transform: After transform: 47 modules, 158 connections -Info: merlin_interrupt_mapper_transform: After transform: 48 modules, 161 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.10.20 10:19:05 (*) Starting Nios II generation -Info: nios2_processor: # 2016.10.20 10:19:05 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.10.20 10:19:06 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.10.20 10:19:06 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.10.20 10:19:06 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.10.20 10:19:06 (*) Plaintext license not found. -Info: nios2_processor: # 2016.10.20 10:19:06 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.10.20 10:19:06 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.10.20 10:19:06 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.10.20 10:19:07 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.10.20 10:19:07 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.10.20 10:19:10 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0003_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0003_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0004_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0004_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0005_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7094_7381845228037269778.dir/0005_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 23 modules, 64 files, 1233875 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_20.rpt b/nios_system_generation_20.rpt deleted file mode 100644 index c84387e..0000000 --- a/nios_system_generation_20.rpt +++ /dev/null @@ -1,320 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 19 modules, 76 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 39 modules, 156 connections -Info: merlin_domain_transform: After transform: 78 modules, 423 connections -Info: merlin_router_transform: After transform: 98 modules, 503 connections -Info: reset_adaptation_transform: After transform: 99 modules, 390 connections -Info: merlin_network_to_switch_transform: After transform: 138 modules, 472 connections -Info: merlin_mm_transform: After transform: 138 modules, 472 connections -Info: merlin_interrupt_mapper_transform: After transform: 139 modules, 475 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0156_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0156_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.01 23:49:05 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.01 23:49:05 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.01 23:49:06 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.01 23:49:06 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.01 23:49:06 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.01 23:49:06 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.01 23:49:06 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.01 23:49:06 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.01 23:49:06 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.01 23:49:07 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.01 23:49:07 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.01 23:49:09 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0157_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0157_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0158_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0158_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0159_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0159_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0160_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0160_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0161_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0161_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0162_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0162_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0163_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0163_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0164_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0164_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info: lcd_on: Starting RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0165_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0165_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] -Info: lcd_on: Done RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_003: "nios_system" instantiated altera_merlin_router "id_router_003" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" -Info: rsp_xbar_demux_003: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_003" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 29 modules, 157 files, 3126120 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_21.rpt b/nios_system_generation_21.rpt deleted file mode 100644 index ea0520b..0000000 --- a/nios_system_generation_21.rpt +++ /dev/null @@ -1,320 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 19 modules, 76 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 39 modules, 156 connections -Info: merlin_domain_transform: After transform: 78 modules, 423 connections -Info: merlin_router_transform: After transform: 98 modules, 503 connections -Info: reset_adaptation_transform: After transform: 99 modules, 390 connections -Info: merlin_network_to_switch_transform: After transform: 138 modules, 472 connections -Info: merlin_mm_transform: After transform: 138 modules, 472 connections -Info: merlin_interrupt_mapper_transform: After transform: 139 modules, 475 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0183_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0183_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.02 01:03:07 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.02 01:03:07 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.02 01:03:08 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.02 01:03:08 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.02 01:03:08 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.02 01:03:08 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.02 01:03:08 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.02 01:03:08 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.02 01:03:08 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.02 01:03:09 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.02 01:03:09 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.02 01:03:11 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0184_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0184_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0185_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0185_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0186_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0186_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0187_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0187_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0188_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0188_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0189_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0189_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0190_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0190_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0191_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0191_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info: lcd_on: Starting RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0192_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0192_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] -Info: lcd_on: Done RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_003: "nios_system" instantiated altera_merlin_router "id_router_003" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" -Info: rsp_xbar_demux_003: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_003" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 29 modules, 157 files, 4115408 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_22.rpt b/nios_system_generation_22.rpt deleted file mode 100644 index 786b4c2..0000000 --- a/nios_system_generation_22.rpt +++ /dev/null @@ -1,319 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex0 -Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex1 -Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex2 -Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex3 -Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex4 -Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex5 -Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex6 -Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module hex7 -Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Progress: Parameterizing module lcd_16207_0 -Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_on -Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module lcd_blon -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 39 modules, 155 connections -Info: merlin_domain_transform: After transform: 78 modules, 423 connections -Info: merlin_router_transform: After transform: 98 modules, 503 connections -Info: reset_adaptation_transform: After transform: 99 modules, 390 connections -Info: merlin_network_to_switch_transform: After transform: 138 modules, 470 connections -Info: merlin_mm_transform: After transform: 138 modules, 470 connections -Info: merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0210_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0210_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.12.02 01:19:36 (*) Starting Nios II generation -Info: nios2_processor: # 2016.12.02 01:19:36 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.12.02 01:19:36 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.12.02 01:19:36 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.12.02 01:19:36 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.12.02 01:19:36 (*) Plaintext license not found. -Info: nios2_processor: # 2016.12.02 01:19:36 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.12.02 01:19:36 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.12.02 01:19:36 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.12.02 01:19:37 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.12.02 01:19:37 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.12.02 01:19:40 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0211_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0211_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0212_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0212_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0213_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0213_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0214_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0214_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0215_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0215_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0216_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0216_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: hex0: Starting RTL generation for module 'nios_system_hex0' -Info: hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0217_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0217_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info: hex0: Done RTL generation for module 'nios_system_hex0' -Info: hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info: lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0218_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0218_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info: lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info: lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info: lcd_on: Starting RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0219_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_4389524620788569279.dir/0219_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] -Info: lcd_on: Done RTL generation for module 'nios_system_lcd_on' -Info: lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 28 modules, 155 files, 4086283 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_3.rpt b/nios_system_generation_3.rpt deleted file mode 100644 index faa6ad7..0000000 --- a/nios_system_generation_3.rpt +++ /dev/null @@ -1,169 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 7 modules, 27 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 15 modules, 59 connections -Info: merlin_domain_transform: After transform: 30 modules, 159 connections -Info: merlin_router_transform: After transform: 38 modules, 191 connections -Info: reset_adaptation_transform: After transform: 39 modules, 150 connections -Info: merlin_network_to_switch_transform: After transform: 54 modules, 182 connections -Info: merlin_mm_transform: After transform: 54 modules, 182 connections -Info: merlin_interrupt_mapper_transform: After transform: 55 modules, 185 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.10.27 10:06:29 (*) Starting Nios II generation -Info: nios2_processor: # 2016.10.27 10:06:29 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.10.27 10:06:30 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.10.27 10:06:30 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.10.27 10:06:30 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.10.27 10:06:30 (*) Plaintext license not found. -Info: nios2_processor: # 2016.10.27 10:06:30 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.10.27 10:06:30 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.10.27 10:06:30 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.10.27 10:06:31 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.10.27 10:06:31 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.10.27 10:06:33 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0003_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0003_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0004_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0004_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0005_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0005_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0006_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_5652275834961544250.dir/0006_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 24 modules, 71 files, 1371812 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_4.rpt b/nios_system_generation_4.rpt deleted file mode 100644 index 1973cdc..0000000 --- a/nios_system_generation_4.rpt +++ /dev/null @@ -1,169 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 7 modules, 27 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 15 modules, 59 connections -Info: merlin_domain_transform: After transform: 30 modules, 159 connections -Info: merlin_router_transform: After transform: 38 modules, 191 connections -Info: reset_adaptation_transform: After transform: 39 modules, 150 connections -Info: merlin_network_to_switch_transform: After transform: 54 modules, 182 connections -Info: merlin_mm_transform: After transform: 54 modules, 182 connections -Info: merlin_interrupt_mapper_transform: After transform: 55 modules, 185 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.10.27 10:23:09 (*) Starting Nios II generation -Info: nios2_processor: # 2016.10.27 10:23:09 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.10.27 10:23:09 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.10.27 10:23:09 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.10.27 10:23:09 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.10.27 10:23:09 (*) Plaintext license not found. -Info: nios2_processor: # 2016.10.27 10:23:09 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.10.27 10:23:09 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.10.27 10:23:09 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.10.27 10:23:10 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.10.27 10:23:10 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.10.27 10:23:12 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0003_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0003_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0004_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0004_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0005_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0005_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0006_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0006_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 24 modules, 71 files, 1371812 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_5.rpt b/nios_system_generation_5.rpt deleted file mode 100644 index a713582..0000000 --- a/nios_system_generation_5.rpt +++ /dev/null @@ -1,169 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 7 modules, 27 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 15 modules, 59 connections -Info: merlin_domain_transform: After transform: 30 modules, 159 connections -Info: merlin_router_transform: After transform: 38 modules, 191 connections -Info: reset_adaptation_transform: After transform: 39 modules, 150 connections -Info: merlin_network_to_switch_transform: After transform: 54 modules, 182 connections -Info: merlin_mm_transform: After transform: 54 modules, 182 connections -Info: merlin_interrupt_mapper_transform: After transform: 55 modules, 185 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0023_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0023_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.10.27 10:33:36 (*) Starting Nios II generation -Info: nios2_processor: # 2016.10.27 10:33:36 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.10.27 10:33:36 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.10.27 10:33:36 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.10.27 10:33:36 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.10.27 10:33:36 (*) Plaintext license not found. -Info: nios2_processor: # 2016.10.27 10:33:36 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.10.27 10:33:36 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.10.27 10:33:36 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.10.27 10:33:37 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.10.27 10:33:37 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.10.27 10:33:40 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0024_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0024_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0025_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0025_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0026_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0026_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0027_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0027_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0028_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0028_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 24 modules, 71 files, 1371812 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_6.rpt b/nios_system_generation_6.rpt deleted file mode 100644 index e42c807..0000000 --- a/nios_system_generation_6.rpt +++ /dev/null @@ -1,169 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Desktop/qsys_tutorial/ --output-directory=C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Desktop/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Desktop/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 7 modules, 27 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 15 modules, 59 connections -Info: merlin_domain_transform: After transform: 30 modules, 159 connections -Info: merlin_router_transform: After transform: 38 modules, 191 connections -Info: reset_adaptation_transform: After transform: 39 modules, 150 connections -Info: merlin_network_to_switch_transform: After transform: 54 modules, 182 connections -Info: merlin_mm_transform: After transform: 54 modules, 182 connections -Info: merlin_interrupt_mapper_transform: After transform: 55 modules, 185 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0045_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0045_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.10.27 10:38:02 (*) Starting Nios II generation -Info: nios2_processor: # 2016.10.27 10:38:02 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.10.27 10:38:02 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.10.27 10:38:02 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.10.27 10:38:02 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.10.27 10:38:02 (*) Plaintext license not found. -Info: nios2_processor: # 2016.10.27 10:38:02 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.10.27 10:38:02 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.10.27 10:38:02 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.10.27 10:38:04 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.10.27 10:38:04 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.10.27 10:38:06 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0046_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0046_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0047_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0047_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0048_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0048_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0049_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0049_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0050_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7101_4069057683900320684.dir/0050_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Desktop/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 24 modules, 71 files, 1371812 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_7.rpt b/nios_system_generation_7.rpt deleted file mode 100644 index d6874bd..0000000 --- a/nios_system_generation_7.rpt +++ /dev/null @@ -1,169 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.pio_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.pio_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 7 modules, 27 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 15 modules, 59 connections -Info: merlin_domain_transform: After transform: 30 modules, 159 connections -Info: merlin_router_transform: After transform: 38 modules, 191 connections -Info: reset_adaptation_transform: After transform: 39 modules, 150 connections -Info: merlin_network_to_switch_transform: After transform: 54 modules, 182 connections -Info: merlin_mm_transform: After transform: 54 modules, 182 connections -Info: merlin_interrupt_mapper_transform: After transform: 55 modules, 185 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.11.10 09:12:21 (*) Starting Nios II generation -Info: nios2_processor: # 2016.11.10 09:12:21 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.11.10 09:12:22 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.11.10 09:12:22 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.11.10 09:12:22 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.11.10 09:12:22 (*) Plaintext license not found. -Info: nios2_processor: # 2016.11.10 09:12:22 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.11.10 09:12:22 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.11.10 09:12:22 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.11.10 09:12:23 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.11.10 09:12:23 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.11.10 09:12:25 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: pio_0: Starting RTL generation for module 'nios_system_pio_0' -Info: pio_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_pio_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0006_pio_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0006_pio_0_gen//nios_system_pio_0_component_configuration.pl --do_build_sim=0 ] -Info: pio_0: Done RTL generation for module 'nios_system_pio_0' -Info: pio_0: "nios_system" instantiated altera_avalon_pio "pio_0" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 24 modules, 71 files, 1372825 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_8.rpt b/nios_system_generation_8.rpt deleted file mode 100644 index 6f090ae..0000000 --- a/nios_system_generation_8.rpt +++ /dev/null @@ -1,169 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.pio_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding pio_0 [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module pio_0 -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.pio_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 7 modules, 27 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 15 modules, 59 connections -Info: merlin_domain_transform: After transform: 30 modules, 159 connections -Info: merlin_router_transform: After transform: 38 modules, 191 connections -Info: reset_adaptation_transform: After transform: 39 modules, 150 connections -Info: merlin_network_to_switch_transform: After transform: 54 modules, 182 connections -Info: merlin_mm_transform: After transform: 54 modules, 182 connections -Info: merlin_interrupt_mapper_transform: After transform: 55 modules, 185 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0023_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0023_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.11.10 09:19:44 (*) Starting Nios II generation -Info: nios2_processor: # 2016.11.10 09:19:44 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.11.10 09:19:44 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.11.10 09:19:44 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.11.10 09:19:44 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.11.10 09:19:44 (*) Plaintext license not found. -Info: nios2_processor: # 2016.11.10 09:19:44 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.11.10 09:19:44 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.11.10 09:19:45 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.11.10 09:19:46 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.11.10 09:19:46 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.11.10 09:19:48 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0024_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0024_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0025_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0025_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0026_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0026_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0027_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0027_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: pio_0: Starting RTL generation for module 'nios_system_pio_0' -Info: pio_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_pio_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0028_pio_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0028_pio_0_gen//nios_system_pio_0_component_configuration.pl --do_build_sim=0 ] -Info: pio_0: Done RTL generation for module 'nios_system_pio_0' -Info: pio_0: "nios_system" instantiated altera_avalon_pio "pio_0" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 24 modules, 71 files, 1371201 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/nios_system_generation_9.rpt b/nios_system_generation_9.rpt deleted file mode 100644 index a941e9c..0000000 --- a/nios_system_generation_9.rpt +++ /dev/null @@ -1,186 +0,0 @@ -Info: Starting: Create block symbol file (.bsf) -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/ --report-file=bsf:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: ip-generate succeeded. -Info: Finished: Create block symbol file (.bsf) -Info: -Info: Starting: Create HDL design files for synthesis -Info: ip-generate --project-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/ --output-directory=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo --report-file=html:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.html --report-file=qip:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.qip --report-file=cmp:C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.cmp --report-file=svd --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.qsys --language=VERILOG -Progress: Loading qsys_tutorial/nios_system.qsys -Progress: Reading input file -Progress: Adding clk_0 [clock_source 13.0] -Progress: Parameterizing module clk_0 -Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Progress: Parameterizing module nios2_processor -Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Progress: Parameterizing module onchip_memory -Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Progress: Parameterizing module jtag_uart -Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDs -Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module LEDRs -Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module switches -Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Progress: Parameterizing module push_switches -Progress: Building connections -Progress: Parameterizing connections -Progress: Validating -Progress: Done reading input file -Info: nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info: nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info: pipeline_bridge_swap_transform: After transform: 8 modules, 31 connections -Info: No custom instruction connections, skipping transform -Info: merlin_translator_transform: After transform: 17 modules, 67 connections -Info: merlin_domain_transform: After transform: 34 modules, 181 connections -Info: merlin_router_transform: After transform: 43 modules, 217 connections -Info: reset_adaptation_transform: After transform: 44 modules, 170 connections -Info: merlin_network_to_switch_transform: After transform: 61 modules, 206 connections -Info: merlin_mm_transform: After transform: 61 modules, 206 connections -Info: merlin_interrupt_mapper_transform: After transform: 62 modules, 209 connections -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning: nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info: nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0045_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0045_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info: nios2_processor: # 2016.11.10 10:03:01 (*) Starting Nios II generation -Info: nios2_processor: # 2016.11.10 10:03:01 (*) Checking for plaintext license. -Info: nios2_processor: # 2016.11.10 10:03:02 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info: nios2_processor: # 2016.11.10 10:03:02 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info: nios2_processor: # 2016.11.10 10:03:02 (*) LM_LICENSE_FILE environment variable is empty -Info: nios2_processor: # 2016.11.10 10:03:02 (*) Plaintext license not found. -Info: nios2_processor: # 2016.11.10 10:03:02 (*) No license required to generate encrypted Nios II/e. -Info: nios2_processor: # 2016.11.10 10:03:02 (*) Elaborating CPU configuration settings -Info: nios2_processor: # 2016.11.10 10:03:02 (*) Creating all objects for CPU -Info: nios2_processor: # 2016.11.10 10:03:03 (*) Generating RTL from CPU objects -Info: nios2_processor: # 2016.11.10 10:03:03 (*) Creating plain-text RTL -Info: nios2_processor: # 2016.11.10 10:03:05 (*) Done Nios II generation -Info: nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info: nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info: onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0046_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0046_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info: onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info: onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info: jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0047_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0047_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info: jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info: jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info: LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info: LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0048_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0048_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info: LEDs: Done RTL generation for module 'nios_system_LEDs' -Info: LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info: LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0049_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0049_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info: LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info: LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info: switches: Starting RTL generation for module 'nios_system_switches' -Info: switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0050_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0050_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info: switches: Done RTL generation for module 'nios_system_switches' -Info: switches: "nios_system" instantiated altera_avalon_pio "switches" -Info: push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info: push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0051_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7115_95487825793286862.dir/0051_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info: push_switches: Done RTL generation for module 'nios_system_push_switches' -Info: push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info: nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info: nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info: nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info: nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info: addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info: addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info: id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info: id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info: rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info: cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info: cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info: cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info: rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info: rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info: Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/submodules/altera_merlin_arbitrator.sv -Info: irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info: nios_system: Done nios_system" with 25 modules, 78 files, 1510254 bytes -Info: ip-generate succeeded. -Info: Finished: Create HDL design files for synthesis diff --git a/output_files/lights.asm.rpt b/output_files/lights.asm.rpt index 82bb4a8..3c1b293 100644 --- a/output_files/lights.asm.rpt +++ b/output_files/lights.asm.rpt @@ -1,127 +1,127 @@ -Assembler report for lights -Fri Dec 02 01:33:21 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Encrypted IP Cores Summary - 5. Assembler Generated Files - 6. Assembler Device Options: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Fri Dec 02 01:33:21 2016 ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Device ; EP4CE115F29C7 ; -+-----------------------+---------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+----------+---------------+ -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; On ; On ; -; Use configuration device ; Off ; Off ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File start address ; 0 ; 0 ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Enable OCT_DONE ; Off ; Off ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+----------+---------------+ - - -+------------------------------------------------+ -; Assembler Encrypted IP Cores Summary ; -+--------+------------------------+--------------+ -; Vendor ; IP Core Name ; License Type ; -+--------+------------------------+--------------+ -; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ; -; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ; -+--------+------------------------+--------------+ - - -+--------------------------------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------------------------------+ -; File Name ; -+--------------------------------------------------------------------------+ -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof ; -+--------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------+ -; Assembler Device Options: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof ; -+----------------+-----------------------------------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------------------------------+ -; Device ; EP4CE115F29C7 ; -; JTAG usercode ; 0x0079493A ; -; Checksum ; 0x0079493A ; -+----------------+-----------------------------------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit Assembler - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Dec 02 01:33:14 2016 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights -Info (115031): Writing out detailed assembly data for power analysis -Info (115030): Assembler is generating device programming files -Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 477 megabytes - Info: Processing ended: Fri Dec 02 01:33:21 2016 - Info: Elapsed time: 00:00:07 - Info: Total CPU time (on all processors): 00:00:06 - - +Assembler report for lights +Thu Dec 22 10:08:41 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Encrypted IP Cores Summary + 5. Assembler Generated Files + 6. Assembler Device Options: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Dec 22 10:08:41 2016 ; +; Revision Name ; lights ; +; Top-level Entity Name ; lights ; +; Family ; Cyclone IV E ; +; Device ; EP4CE115F29C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++------------------------------------------------+ +; Assembler Encrypted IP Cores Summary ; ++--------+------------------------+--------------+ +; Vendor ; IP Core Name ; License Type ; ++--------+------------------------+--------------+ +; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ; +; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ; ++--------+------------------------+--------------+ + + ++--------------------------------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------------------------------+ +; File Name ; ++--------------------------------------------------------------------------+ +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof ; ++--------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.sof ; ++----------------+-----------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------------------------------------+ +; Device ; EP4CE115F29C7 ; +; JTAG usercode ; 0x0079E234 ; +; Checksum ; 0x0079E234 ; ++----------------+-----------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Thu Dec 22 10:08:34 2016 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 481 megabytes + Info: Processing ended: Thu Dec 22 10:08:41 2016 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:07 + + diff --git a/output_files/lights.done b/output_files/lights.done index 033af12..354d5fa 100644 --- a/output_files/lights.done +++ b/output_files/lights.done @@ -1 +1 @@ -Fri Dec 02 01:33:29 2016 +Thu Dec 22 10:08:49 2016 diff --git a/output_files/lights.fit.rpt b/output_files/lights.fit.rpt index a9a8fe4..0fee99a 100644 --- a/output_files/lights.fit.rpt +++ b/output_files/lights.fit.rpt @@ -1,11508 +1,11511 @@ -Fitter report for lights -Fri Dec 02 01:33:11 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. I/O Assignment Warnings - 6. Fitter Netlist Optimizations - 7. Ignored Assignments - 8. Incremental Compilation Preservation Summary - 9. Incremental Compilation Partition Settings - 10. Incremental Compilation Placement Preservation - 11. Pin-Out File - 12. Fitter Resource Usage Summary - 13. Fitter Partition Statistics - 14. Input Pins - 15. Output Pins - 16. Dual Purpose and Dedicated Pins - 17. I/O Bank Usage - 18. All Package Pins - 19. Fitter Resource Utilization by Entity - 20. Delay Chain Summary - 21. Pad To Core Delay Chain Fanout - 22. Control Signals - 23. Global & Other Fast Signals - 24. Non-Global High Fan-Out Signals - 25. Fitter RAM Summary - 26. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM - 27. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM - 28. |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM - 29. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM - 30. Other Routing Usage Summary - 31. LAB Logic Elements - 32. LAB-wide Signals - 33. LAB Signals Sourced - 34. LAB Signals Sourced Out - 35. LAB Distinct Inputs - 36. I/O Rules Summary - 37. I/O Rules Details - 38. I/O Rules Matrix - 39. Fitter Device Options - 40. Operating Settings and Conditions - 41. Fitter Messages - 42. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Fri Dec 02 01:33:11 2016 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Device ; EP4CE115F29C7 ; -; Timing Models ; Final ; -; Total logic elements ; 2,232 / 114,480 ( 2 % ) ; -; Total combinational functions ; 2,062 / 114,480 ( 2 % ) ; -; Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; -; Total registers ; 1204 ; -; Total pins ; 118 / 529 ( 22 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; -+------------------------------------+-------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Device ; EP4CE115F29C7 ; ; -; Nominal Core Supply Voltage ; 1.2V ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Auto Merge PLLs ; On ; On ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Perform Clocking Topology Analysis During Routing ; Off ; Off ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Optimize Hold Timing ; All Paths ; All Paths ; -; Optimize Multi-Corner Timing ; On ; On ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; SSN Optimization ; Off ; Off ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; -; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; -; Treat Bidirectional Pin as Output Pin ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; -; Synchronizer Identification ; Off ; Off ; -; Enable Beneficial Skew Optimization ; On ; On ; -; Optimize Design for Metastability ; On ; On ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+----------------------------------------------------+ -; I/O Assignment Warnings ; -+-------------+--------------------------------------+ -; Pin Name ; Reason ; -+-------------+--------------------------------------+ -; LEDG[0] ; Missing drive strength and slew rate ; -; LEDG[1] ; Missing drive strength and slew rate ; -; LEDG[2] ; Missing drive strength and slew rate ; -; LEDG[3] ; Missing drive strength and slew rate ; -; LEDG[4] ; Missing drive strength and slew rate ; -; LEDG[5] ; Missing drive strength and slew rate ; -; LEDG[6] ; Missing drive strength and slew rate ; -; LEDG[7] ; Missing drive strength and slew rate ; -; LEDR[0] ; Missing drive strength and slew rate ; -; LEDR[1] ; Missing drive strength and slew rate ; -; LEDR[2] ; Missing drive strength and slew rate ; -; LEDR[3] ; Missing drive strength and slew rate ; -; LEDR[4] ; Missing drive strength and slew rate ; -; LEDR[5] ; Missing drive strength and slew rate ; -; LEDR[6] ; Missing drive strength and slew rate ; -; LEDR[7] ; Missing drive strength and slew rate ; -; LEDR[8] ; Missing drive strength and slew rate ; -; LEDR[9] ; Missing drive strength and slew rate ; -; LEDR[10] ; Missing drive strength and slew rate ; -; LEDR[11] ; Missing drive strength and slew rate ; -; LEDR[12] ; Missing drive strength and slew rate ; -; LEDR[13] ; Missing drive strength and slew rate ; -; LEDR[14] ; Missing drive strength and slew rate ; -; LEDR[15] ; Missing drive strength and slew rate ; -; LEDR[16] ; Missing drive strength and slew rate ; -; LEDR[17] ; Missing drive strength and slew rate ; -; HEX0[0] ; Missing drive strength and slew rate ; -; HEX0[1] ; Missing drive strength and slew rate ; -; HEX0[2] ; Missing drive strength and slew rate ; -; HEX0[3] ; Missing drive strength and slew rate ; -; HEX0[4] ; Missing drive strength and slew rate ; -; HEX0[5] ; Missing drive strength and slew rate ; -; HEX0[6] ; Missing drive strength and slew rate ; -; HEX1[0] ; Missing drive strength and slew rate ; -; HEX1[1] ; Missing drive strength and slew rate ; -; HEX1[2] ; Missing drive strength and slew rate ; -; HEX1[3] ; Missing drive strength and slew rate ; -; HEX1[4] ; Missing drive strength and slew rate ; -; HEX1[5] ; Missing drive strength and slew rate ; -; HEX1[6] ; Missing drive strength and slew rate ; -; HEX2[0] ; Missing drive strength and slew rate ; -; HEX2[1] ; Missing drive strength and slew rate ; -; HEX2[2] ; Missing drive strength and slew rate ; -; HEX2[3] ; Missing drive strength and slew rate ; -; HEX2[4] ; Missing drive strength and slew rate ; -; HEX2[5] ; Missing drive strength and slew rate ; -; HEX2[6] ; Missing drive strength and slew rate ; -; HEX3[0] ; Missing drive strength and slew rate ; -; HEX3[1] ; Missing drive strength and slew rate ; -; HEX3[2] ; Missing drive strength ; -; HEX3[3] ; Missing drive strength ; -; HEX3[4] ; Missing drive strength ; -; HEX3[5] ; Missing drive strength ; -; HEX3[6] ; Missing drive strength ; -; HEX4[0] ; Missing drive strength ; -; HEX4[1] ; Missing drive strength ; -; HEX4[2] ; Missing drive strength ; -; HEX4[3] ; Missing drive strength ; -; HEX4[4] ; Missing drive strength ; -; HEX4[5] ; Missing drive strength ; -; HEX4[6] ; Missing drive strength ; -; HEX5[0] ; Missing drive strength ; -; HEX5[1] ; Missing drive strength ; -; HEX5[2] ; Missing drive strength ; -; HEX5[3] ; Missing drive strength ; -; HEX5[4] ; Missing drive strength ; -; HEX5[5] ; Missing drive strength ; -; HEX5[6] ; Missing drive strength ; -; HEX6[0] ; Missing drive strength ; -; HEX6[1] ; Missing drive strength ; -; HEX6[2] ; Missing drive strength ; -; HEX6[3] ; Missing drive strength ; -; HEX6[4] ; Missing drive strength ; -; HEX6[5] ; Missing drive strength ; -; HEX6[6] ; Missing drive strength ; -; HEX7[0] ; Missing drive strength ; -; HEX7[1] ; Missing drive strength ; -; HEX7[2] ; Missing drive strength ; -; HEX7[3] ; Missing drive strength ; -; HEX7[4] ; Missing drive strength ; -; HEX7[5] ; Missing drive strength ; -; HEX7[6] ; Missing drive strength ; -; LCD_RS ; Missing drive strength ; -; LCD_RW ; Missing drive strength ; -; LCD_data[0] ; Missing drive strength ; -; LCD_data[1] ; Missing drive strength ; -; LCD_data[2] ; Missing drive strength ; -; LCD_data[3] ; Missing drive strength ; -; LCD_data[4] ; Missing drive strength ; -; LCD_data[5] ; Missing drive strength ; -; LCD_data[6] ; Missing drive strength ; -; LCD_data[7] ; Missing drive strength ; -; LCD_EN ; Missing drive strength ; -; LCD_ON ; Missing drive strength ; -; LCD_BLON ; Missing drive strength ; -+-------------+--------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Netlist Optimizations ; -+-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; -+-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[0] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[1] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[2] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[3] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[4] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[5] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[6] ; PORTBDATAOUT ; ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[7] ; PORTBDATAOUT ; ; -+-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Ignored Assignments ; -+--------------+----------------+--------------+------------------+---------------+----------------+ -; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; -+--------------+----------------+--------------+------------------+---------------+----------------+ -; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ; -; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ; -; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ; -; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ; -; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ; -; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ; -; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ; -; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ; -; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ; -; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ; -; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ; -; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ; -; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ; -; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ; -; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ; -; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ; -; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ; -; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ; -; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ; -; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ; -; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ; -; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ; -; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ; -; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ; -; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ; -; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ; -; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ; -; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ; -; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ; -; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ; -; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ; -; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ; -; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ; -; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ; -; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ; -; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ; -; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ; -; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ; -; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ; -; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ; -; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ; -; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ; -; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ; -; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ; -; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ; -; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ; -; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ; -; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ; -; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ; -; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ; -; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ; -; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ; -; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ; -; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ; -; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ; -; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ; -; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ; -; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ; -; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ; -; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ; -; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ; -; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ; -; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ; -; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ; -; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ; -; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ; -; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ; -; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ; -; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ; -; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ; -; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ; -; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ; -; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ; -; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ; -; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ; -; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ; -; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ; -; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ; -; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ; -; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ; -; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ; -; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ; -; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ; -; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ; -; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ; -; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ; -; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ; -; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ; -; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ; -; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ; -; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ; -; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ; -; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ; -; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ; -; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ; -; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ; -; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ; -; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ; -; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ; -; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ; -; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ; -; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ; -; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ; -; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ; -; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ; -; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ; -; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ; -; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ; -; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ; -; Location ; ; ; OTG_DACK_N[0] ; PIN_C4 ; QSF Assignment ; -; Location ; ; ; OTG_DACK_N[1] ; PIN_D4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ; -; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ; -; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ; -; Location ; ; ; OTG_DREQ[1] ; PIN_B4 ; QSF Assignment ; -; Location ; ; ; OTG_FSPEED ; PIN_C6 ; QSF Assignment ; -; Location ; ; ; OTG_INT[0] ; PIN_A6 ; QSF Assignment ; -; Location ; ; ; OTG_INT[1] ; PIN_D5 ; QSF Assignment ; -; Location ; ; ; OTG_LSPEED ; PIN_B6 ; QSF Assignment ; -; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ; -; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ; -; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ; -; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ; -; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ; -; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ; -; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ; -; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ; -; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ; -; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ; -; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ; -; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ; -; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ; -; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ; -; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ; -; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ; -; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ; -; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ; -; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ; -; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ; -; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ; -; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ; -; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ; -; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ; -; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ; -; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ; -; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ; -; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ; -; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ; -; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ; -; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ; -; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ; -; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ; -; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ; -; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ; -; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ; -; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ; -; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ; -; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ; -; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ; -; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ; -; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ; -; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ; -; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ; -; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ; -; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ; -; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ; -; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ; -; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ; -; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ; -; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ; -; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ; -; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ; -; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ; -; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ; -; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ; -; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ; -; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ; -; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ; -; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ; -; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ; -; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ; -; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ; -; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ; -; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ; -; I/O Standard ; ; ; AUD_ADCDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_ADCLRCK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_BCLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_DACDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_DACLRCK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; AUD_XCK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; CLOCK2_50 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; CLOCK3_50 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_BA[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_BA[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CAS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CKE ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_CS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQM[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[23] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[24] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[25] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[26] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[27] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[28] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[29] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[30] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[31] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_RAS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; DRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EEP_I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EEP_I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_GTX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_INT_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_LINK100 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_MDC ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_MDIO ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RST_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_COL ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_CRS ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_DV ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_RX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_EN ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET0_TX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_GTX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_INT_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_LINK100 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_MDC ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_MDIO ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RST_N ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_COL ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_CRS ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_DV ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_RX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_CLK ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_DATA[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_EN ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENET1_TX_ER ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; ENETCLK_25 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; EX_IO[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_CE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_OE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_RST_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_RY ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; FL_WP_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[20] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[21] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[22] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[23] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[24] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[25] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[26] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[27] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[28] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[29] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[30] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[31] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[32] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[33] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[34] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[35] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; GPIO[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN0 ; 3.0-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_N1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_N2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_P1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKIN_P2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT0 ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_N1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_N2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_P1 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_CLKOUT_P2 ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[0] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[1] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[2] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_D[3] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_N[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_RX_D_P[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_N[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[0] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[10] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[11] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[12] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[13] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[14] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[15] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[16] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[1] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[2] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[3] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[4] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[5] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[6] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[7] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[8] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; HSMC_TX_D_P[9] ; LVDS ; QSF Assignment ; -; I/O Standard ; ; ; I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; IRDA_RXD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; LEDG[8] ; 2.5 V ; QSF Assignment ; -; I/O Standard ; ; ; OTG_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_CS_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DACK_N[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DACK_N[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DATA[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DREQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_DREQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_FSPEED ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_INT[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_INT[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_LSPEED ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_RD_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_RST_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; OTG_WR_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_CLK2 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_DAT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; PS2_DAT2 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_CMD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_DAT[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SD_WP_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SMA_CLKIN ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SMA_CLKOUT ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_CE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_LB_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_OE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_UB_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; SRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_CLK27 ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_HS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_RESET_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; TD_VS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_CTS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_RTS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_RXD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; UART_TXD ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_BLANK_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_B[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_CLK ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_G[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_HS ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[0] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[1] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[2] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[3] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[4] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[5] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[6] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_R[7] ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_SYNC_N ; 3.3-V LVTTL ; QSF Assignment ; -; I/O Standard ; ; ; VGA_VS ; 3.3-V LVTTL ; QSF Assignment ; -+--------------+----------------+--------------+------------------+---------------+----------------+ - - -+----------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+---------------------+------------------------+ -; Type ; Value ; -+---------------------+------------------------+ -; Placement (by node) ; ; -; -- Requested ; 0 / 3866 ( 0.00 % ) ; -; -- Achieved ; 0 / 3866 ( 0.00 % ) ; -; ; ; -; Routing (by net) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+---------------------+------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -; sld_hub:auto_hub ; Auto-generated ; Post-Synthesis ; N/A ; Post-Synthesis ; N/A ; sld_hub:auto_hub ; -; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; -+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 3599 ; 0 ; N/A ; Source File ; -; sld_hub:auto_hub ; 257 ; 0 ; N/A ; Post-Synthesis ; -; hard_block:auto_generated_inst ; 10 ; 0 ; N/A ; Source File ; -+--------------------------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.pin. - - -+------------------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+--------------------------------+ -; Resource ; Usage ; -+---------------------------------------------+--------------------------------+ -; Total logic elements ; 2,232 / 114,480 ( 2 % ) ; -; -- Combinational with no register ; 1028 ; -; -- Register only ; 170 ; -; -- Combinational with a register ; 1034 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1077 ; -; -- 3 input functions ; 679 ; -; -- <=2 input functions ; 306 ; -; -- Register only ; 170 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 1915 ; -; -- arithmetic mode ; 147 ; -; ; ; -; Total registers* ; 1,204 / 117,053 ( 1 % ) ; -; -- Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; -; -- I/O registers ; 0 / 2,573 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 156 / 7,155 ( 2 % ) ; -; Virtual pins ; 0 ; -; I/O pins ; 118 / 529 ( 22 % ) ; -; -- Clock pins ; 1 / 7 ( 14 % ) ; -; -- Dedicated input pins ; 3 / 9 ( 33 % ) ; -; ; ; -; Global signals ; 4 ; -; M9Ks ; 205 / 432 ( 47 % ) ; -; Total block memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; -; Total block memory implementation bits ; 1,889,280 / 3,981,312 ( 47 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; -; PLLs ; 0 / 4 ( 0 % ) ; -; Global clocks ; 4 / 20 ( 20 % ) ; -; JTAGs ; 1 / 1 ( 100 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 2% / 1% / 2% ; -; Peak interconnect usage (total/H/V) ; 25% / 22% / 30% ; -; Maximum fan-out ; 1229 ; -; Highest non-global fan-out ; 204 ; -; Total fan-out ; 15201 ; -; Average fan-out ; 3.95 ; -+---------------------------------------------+--------------------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Partition Statistics ; -+---------------------------------------------+-------------------------+------------------------+--------------------------------+ -; Statistic ; Top ; sld_hub:auto_hub ; hard_block:auto_generated_inst ; -+---------------------------------------------+-------------------------+------------------------+--------------------------------+ -; Difficulty Clustering Region ; Low ; Low ; Low ; -; ; ; ; ; -; Total logic elements ; 2061 / 114480 ( 2 % ) ; 171 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; -; -- Combinational with no register ; 954 ; 74 ; 0 ; -; -- Register only ; 159 ; 11 ; 0 ; -; -- Combinational with a register ; 948 ; 86 ; 0 ; -; ; ; ; ; -; Logic element usage by number of LUT inputs ; ; ; ; -; -- 4 input functions ; 1007 ; 70 ; 0 ; -; -- 3 input functions ; 632 ; 47 ; 0 ; -; -- <=2 input functions ; 263 ; 43 ; 0 ; -; -- Register only ; 159 ; 11 ; 0 ; -; ; ; ; ; -; Logic elements by mode ; ; ; ; -; -- normal mode ; 1763 ; 152 ; 0 ; -; -- arithmetic mode ; 139 ; 8 ; 0 ; -; ; ; ; ; -; Total registers ; 1107 ; 97 ; 0 ; -; -- Dedicated logic registers ; 1107 / 114480 ( < 1 % ) ; 97 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; -; ; ; ; ; -; Total LABs: partially or completely used ; 142 / 7155 ( 2 % ) ; 15 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ; -; ; ; ; ; -; Virtual pins ; 0 ; 0 ; 0 ; -; I/O pins ; 118 ; 0 ; 0 ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ; -; Total memory bits ; 1649664 ; 0 ; 0 ; -; Total RAM block bits ; 1889280 ; 0 ; 0 ; -; JTAG ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; -; M9K ; 205 / 432 ( 47 % ) ; 0 / 432 ( 0 % ) ; 0 / 432 ( 0 % ) ; -; Clock control block ; 4 / 24 ( 16 % ) ; 0 / 24 ( 0 % ) ; 0 / 24 ( 0 % ) ; -; ; ; ; ; -; Connections ; ; ; ; -; -- Input Connections ; 268 ; 140 ; 0 ; -; -- Registered Input Connections ; 130 ; 107 ; 0 ; -; -- Output Connections ; 235 ; 173 ; 0 ; -; -- Registered Output Connections ; 4 ; 172 ; 0 ; -; ; ; ; ; -; Internal Connections ; ; ; ; -; -- Total Connections ; 14515 ; 1016 ; 5 ; -; -- Registered Connections ; 4720 ; 712 ; 0 ; -; ; ; ; ; -; External Connections ; ; ; ; -; -- Top ; 192 ; 311 ; 0 ; -; -- sld_hub:auto_hub ; 311 ; 2 ; 0 ; -; -- hard_block:auto_generated_inst ; 0 ; 0 ; 0 ; -; ; ; ; ; -; Partition Interface ; ; ; ; -; -- Input Ports ; 63 ; 23 ; 0 ; -; -- Output Ports ; 102 ; 40 ; 0 ; -; -- Bidir Ports ; 0 ; 0 ; 0 ; -; ; ; ; ; -; Registered Ports ; ; ; ; -; -- Registered Input Ports ; 0 ; 3 ; 0 ; -; -- Registered Output Ports ; 0 ; 29 ; 0 ; -; ; ; ; ; -; Port Connectivity ; ; ; ; -; -- Input Ports driven by GND ; 0 ; 9 ; 0 ; -; -- Output Ports driven by GND ; 0 ; 1 ; 0 ; -; -- Input Ports driven by VCC ; 0 ; 0 ; 0 ; -; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ; -; -- Input Ports with no Source ; 0 ; 1 ; 0 ; -; -- Output Ports with no Source ; 0 ; 0 ; 0 ; -; -- Input Ports with no Fanout ; 0 ; 2 ; 0 ; -; -- Output Ports with no Fanout ; 0 ; 26 ; 0 ; -+---------------------------------------------+-------------------------+------------------------+--------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; -+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; CLOCK_50 ; Y2 ; 2 ; 0 ; 36 ; 14 ; 1229 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; KEY[2] ; N21 ; 6 ; 115 ; 42 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; KEY[3] ; R24 ; 5 ; 115 ; 35 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; -+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ -; HEX0[0] ; G18 ; 7 ; 69 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[1] ; F22 ; 7 ; 107 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[2] ; E17 ; 7 ; 67 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[3] ; L26 ; 6 ; 115 ; 50 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[4] ; L25 ; 6 ; 115 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[5] ; J22 ; 6 ; 115 ; 67 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX0[6] ; H22 ; 6 ; 115 ; 69 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[0] ; M24 ; 6 ; 115 ; 41 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[1] ; Y22 ; 5 ; 115 ; 30 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[2] ; W21 ; 5 ; 115 ; 25 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[3] ; W22 ; 5 ; 115 ; 30 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[4] ; W25 ; 5 ; 115 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[5] ; U23 ; 5 ; 115 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX1[6] ; U24 ; 5 ; 115 ; 28 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[0] ; AA25 ; 5 ; 115 ; 17 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[1] ; AA26 ; 5 ; 115 ; 16 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[2] ; Y25 ; 5 ; 115 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[3] ; W26 ; 5 ; 115 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[4] ; Y26 ; 5 ; 115 ; 18 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[5] ; W27 ; 5 ; 115 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX2[6] ; W28 ; 5 ; 115 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX3[0] ; V21 ; 5 ; 115 ; 25 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX3[1] ; U21 ; 5 ; 115 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; HEX3[2] ; AB20 ; 4 ; 100 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[3] ; AA21 ; 4 ; 111 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[4] ; AD24 ; 4 ; 105 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[5] ; AF23 ; 4 ; 105 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX3[6] ; Y19 ; 4 ; 105 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[0] ; AB19 ; 4 ; 98 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[1] ; AA19 ; 4 ; 107 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[2] ; AG21 ; 4 ; 74 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[3] ; AH21 ; 4 ; 74 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[4] ; AE19 ; 4 ; 83 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[5] ; AF19 ; 4 ; 83 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX4[6] ; AE18 ; 4 ; 79 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[0] ; AD18 ; 4 ; 85 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[1] ; AC18 ; 4 ; 87 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[2] ; AB18 ; 4 ; 98 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[3] ; AH19 ; 4 ; 72 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[4] ; AG19 ; 4 ; 72 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[5] ; AF18 ; 4 ; 79 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX5[6] ; AH18 ; 4 ; 69 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[0] ; AA17 ; 4 ; 89 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[1] ; AB16 ; 4 ; 65 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[2] ; AA16 ; 4 ; 65 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[3] ; AB17 ; 4 ; 89 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[4] ; AB15 ; 4 ; 67 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[5] ; AA15 ; 4 ; 67 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX6[6] ; AC17 ; 4 ; 74 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[0] ; AD17 ; 4 ; 74 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[1] ; AE17 ; 4 ; 67 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[2] ; AG17 ; 4 ; 62 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[3] ; AH17 ; 4 ; 62 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[4] ; AF17 ; 4 ; 67 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[5] ; AG18 ; 4 ; 69 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; HEX7[6] ; AA14 ; 3 ; 54 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_BLON ; L6 ; 1 ; 0 ; 47 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_EN ; L4 ; 1 ; 0 ; 52 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_ON ; L5 ; 1 ; 0 ; 58 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_RS ; M2 ; 1 ; 0 ; 44 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_RW ; M1 ; 1 ; 0 ; 44 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[0] ; L3 ; 1 ; 0 ; 52 ; 14 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[1] ; L1 ; 1 ; 0 ; 44 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[2] ; L2 ; 1 ; 0 ; 44 ; 0 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[3] ; K7 ; 1 ; 0 ; 49 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[4] ; K1 ; 1 ; 0 ; 54 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[5] ; K2 ; 1 ; 0 ; 55 ; 21 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[6] ; M3 ; 1 ; 0 ; 51 ; 14 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LCD_data[7] ; M5 ; 1 ; 0 ; 47 ; 0 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; -; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[1] ; E22 ; 7 ; 111 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[2] ; E25 ; 7 ; 83 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[3] ; E24 ; 7 ; 85 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[4] ; H21 ; 7 ; 72 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[5] ; G20 ; 7 ; 74 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[6] ; G22 ; 7 ; 72 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDG[7] ; G21 ; 7 ; 74 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[10] ; J15 ; 7 ; 60 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[11] ; H16 ; 7 ; 65 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[12] ; J16 ; 7 ; 65 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[13] ; H17 ; 7 ; 67 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[14] ; F15 ; 7 ; 58 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[15] ; G15 ; 7 ; 65 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[16] ; G16 ; 7 ; 67 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[17] ; H15 ; 7 ; 60 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[7] ; H19 ; 7 ; 72 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[8] ; J17 ; 7 ; 69 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -; LEDR[9] ; G17 ; 7 ; 83 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------+ -; Dual Purpose and Dedicated Pins ; -+----------+-----------------------------+--------------------------+-------------------------+---------------------------+ -; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; -+----------+-----------------------------+--------------------------+-------------------------+---------------------------+ -; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; -; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; -; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; -; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; -; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; -; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; -; P7 ; TDI ; - ; altera_reserved_tdi ; JTAG Pin ; -; P5 ; TCK ; - ; altera_reserved_tck ; JTAG Pin ; -; P8 ; TMS ; - ; altera_reserved_tms ; JTAG Pin ; -; P6 ; TDO ; - ; altera_reserved_tdo ; JTAG Pin ; -; R8 ; nCE ; - ; - ; Dedicated Programming Pin ; -; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; -; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; -; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; -; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; -; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; -; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; -+----------+-----------------------------+--------------------------+-------------------------+---------------------------+ - - -+------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+------------------+---------------+--------------+ -; 1 ; 17 / 56 ( 30 % ) ; 3.3V ; -- ; -; 2 ; 1 / 63 ( 2 % ) ; 3.3V ; -- ; -; 3 ; 1 / 73 ( 1 % ) ; 3.3V ; -- ; -; 4 ; 32 / 71 ( 45 % ) ; 3.3V ; -- ; -; 5 ; 34 / 65 ( 52 % ) ; 2.5V ; -- ; -; 6 ; 9 / 58 ( 16 % ) ; 2.5V ; -- ; -; 7 ; 29 / 72 ( 40 % ) ; 2.5V ; -- ; -; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ; -+----------+------------------+---------------+--------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AA1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; -; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AA14 ; 191 ; 3 ; HEX7[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA15 ; 213 ; 4 ; HEX6[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA16 ; 211 ; 4 ; HEX6[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA17 ; 241 ; 4 ; HEX6[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AA19 ; 264 ; 4 ; HEX4[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; -; AA21 ; 269 ; 4 ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA25 ; 294 ; 5 ; HEX2[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA26 ; 293 ; 5 ; HEX2[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB15 ; 214 ; 4 ; HEX6[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB16 ; 212 ; 4 ; HEX6[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB17 ; 242 ; 4 ; HEX6[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB18 ; 254 ; 4 ; HEX5[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB19 ; 253 ; 4 ; HEX4[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB20 ; 257 ; 4 ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC17 ; 221 ; 4 ; HEX6[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AC18 ; 240 ; 4 ; HEX5[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD17 ; 222 ; 4 ; HEX7[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AD18 ; 237 ; 4 ; HEX5[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AD24 ; 260 ; 4 ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE17 ; 215 ; 4 ; HEX7[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AE18 ; 225 ; 4 ; HEX4[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AE19 ; 231 ; 4 ; HEX4[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF17 ; 216 ; 4 ; HEX7[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF18 ; 226 ; 4 ; HEX5[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF19 ; 232 ; 4 ; HEX4[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF23 ; 262 ; 4 ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG17 ; 207 ; 4 ; HEX7[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG18 ; 217 ; 4 ; HEX7[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG19 ; 219 ; 4 ; HEX5[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG21 ; 223 ; 4 ; HEX4[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AH2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AH16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH17 ; 208 ; 4 ; HEX7[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH18 ; 218 ; 4 ; HEX5[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH19 ; 220 ; 4 ; HEX5[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH21 ; 224 ; 4 ; HEX4[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH24 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; AH27 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; B1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E17 ; 456 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E22 ; 403 ; 7 ; LEDG[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; E24 ; 433 ; 7 ; LEDG[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E25 ; 434 ; 7 ; LEDG[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F15 ; 466 ; 7 ; LEDR[14] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F22 ; 409 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; G15 ; 457 ; 7 ; LEDR[15] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G16 ; 453 ; 7 ; LEDR[16] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G17 ; 437 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G18 ; 452 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G20 ; 444 ; 7 ; LEDG[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G21 ; 445 ; 7 ; LEDG[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G22 ; 449 ; 7 ; LEDG[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; -; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; H15 ; 464 ; 7 ; LEDR[17] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H16 ; 459 ; 7 ; LEDR[11] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H17 ; 454 ; 7 ; LEDR[13] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; H19 ; 446 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; -; H21 ; 448 ; 7 ; LEDG[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; H22 ; 399 ; 6 ; HEX0[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; J15 ; 465 ; 7 ; LEDR[10] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J16 ; 458 ; 7 ; LEDR[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J17 ; 450 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; J22 ; 394 ; 6 ; HEX0[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; K1 ; 28 ; 1 ; LCD_data[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K2 ; 27 ; 1 ; LCD_data[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K7 ; 38 ; 1 ; LCD_data[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L1 ; 49 ; 1 ; LCD_data[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L2 ; 48 ; 1 ; LCD_data[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L3 ; 32 ; 1 ; LCD_data[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L4 ; 31 ; 1 ; LCD_EN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L5 ; 21 ; 1 ; LCD_ON ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L6 ; 43 ; 1 ; LCD_BLON ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L25 ; 369 ; 6 ; HEX0[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; L26 ; 363 ; 6 ; HEX0[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M1 ; 51 ; 1 ; LCD_RW ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M2 ; 50 ; 1 ; LCD_RS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M3 ; 34 ; 1 ; LCD_data[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M5 ; 41 ; 1 ; LCD_data[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; -; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; M24 ; 347 ; 6 ; HEX1[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N21 ; 348 ; 6 ; KEY[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; -; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; P5 ; 59 ; 1 ; altera_reserved_tck ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P6 ; 61 ; 1 ; altera_reserved_tdo ; output ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P7 ; 58 ; 1 ; altera_reserved_tdi ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P8 ; 60 ; 1 ; altera_reserved_tms ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; -; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; -; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R24 ; 330 ; 5 ; KEY[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; -; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U21 ; 319 ; 5 ; HEX3[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U23 ; 305 ; 5 ; HEX1[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U24 ; 316 ; 5 ; HEX1[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V21 ; 311 ; 5 ; HEX3[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; W21 ; 310 ; 5 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W22 ; 321 ; 5 ; HEX1[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W25 ; 300 ; 5 ; HEX1[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W26 ; 299 ; 5 ; HEX2[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W27 ; 301 ; 5 ; HEX2[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W28 ; 302 ; 5 ; HEX2[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; Y2 ; 65 ; 2 ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; -; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y19 ; 263 ; 4 ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y22 ; 320 ; 5 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y25 ; 298 ; 5 ; HEX2[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y26 ; 297 ; 5 ; HEX2[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; |lights ; 2232 (1) ; 1204 (0) ; 0 (0) ; 1649664 ; 205 ; 0 ; 0 ; 0 ; 118 ; 0 ; 1028 (1) ; 170 (0) ; 1034 (0) ; |lights ; work ; -; |nios_system:NiosII| ; 2060 (0) ; 1107 (0) ; 0 (0) ; 1649664 ; 205 ; 0 ; 0 ; 0 ; 0 ; 0 ; 953 (0) ; 159 (0) ; 948 (0) ; |lights|nios_system:NiosII ; work ; -; |altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 10 (10) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 5 (5) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_data_master_translator| ; 9 (9) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_instruction_master_translator| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex0_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex1_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex2_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex3_s1_translator| ; 12 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex4_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex5_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex6_s1_translator| ; 12 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex7_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator| ; 23 (23) ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 23 (23) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_16207_0_control_slave_translator| ; 22 (22) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 15 (15) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_blon_s1_translator| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_on_s1_translator| ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:ledrs_s1_translator| ; 24 (24) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 21 (21) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:leds_s1_translator| ; 13 (13) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 11 (11) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator| ; 33 (33) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 33 (33) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:onchip_memory_s1_translator| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:push_switches_s1_translator| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:switches_s1_translator| ; 24 (24) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 21 (21) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_reset_controller:rst_controller| ; 10 (7) ; 9 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 7 (5) ; 3 (2) ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller ; altera_reserved_qsys_nios_system ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 1 (1) ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDRs:ledrs| ; 38 (38) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 18 (18) ; 18 (18) ; |lights|nios_system:NiosII|nios_system_LEDRs:ledrs ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDs:leds| ; 19 (19) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 8 (8) ; 8 (8) ; |lights|nios_system:NiosII|nios_system_LEDs:leds ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router:addr_router| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_addr_router:addr_router ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router_001:addr_router_001| ; 30 (30) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:cmd_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux_001| ; 60 (57) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (40) ; 0 (0) ; 19 (16) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux| ; 55 (52) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (3) ; 1 (0) ; 50 (47) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex0| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex0 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex1| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex1 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex2| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex2 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex3| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex3 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex4| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex4 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex5| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex5 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex6| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex6 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex7| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex7 ; altera_reserved_qsys_nios_system ; -; |nios_system_jtag_uart:jtag_uart| ; 157 (39) ; 104 (13) ; 0 (0) ; 1024 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (16) ; 17 (2) ; 97 (20) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart ; altera_reserved_qsys_nios_system ; -; |alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic| ; 68 (68) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 15 (15) ; 37 (37) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic ; work ; -; |nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r ; altera_reserved_qsys_nios_system ; -; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; work ; -; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 8 (2) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w ; altera_reserved_qsys_nios_system ; -; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; work ; -; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 8 (2) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_lcd_16207_0:lcd_16207_0| ; 12 (12) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 8 (8) ; |lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_blon| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_on| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_on ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor:nios2_processor| ; 1040 (658) ; 576 (306) ; 0 (0) ; 10240 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 440 (328) ; 51 (5) ; 549 (326) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci| ; 381 (81) ; 269 (80) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (1) ; 46 (1) ; 223 (79) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper| ; 139 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (0) ; 43 (0) ; 53 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk| ; 50 (46) ; 49 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 39 (37) ; 10 (8) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer4| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; work ; -; |nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck| ; 87 (83) ; 47 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 4 (0) ; 43 (43) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; work ; -; |sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; work ; -; |nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg| ; 9 (9) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug| ; 11 (9) ; 9 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 10 (9) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; work ; -; |nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem| ; 112 (112) ; 49 (49) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (62) ; 1 (1) ; 49 (49) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; work ; -; |altsyncram_4891:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; work ; -; |altsyncram_0rh1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; work ; -; |altsyncram_1rh1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; work ; -; |nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench ; altera_reserved_qsys_nios_system ; -; |nios_system_onchip_memory:onchip_memory| ; 171 (1) ; 3 (0) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 168 (1) ; 0 (0) ; 3 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 170 (0) ; 3 (0) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 167 (0) ; 0 (0) ; 3 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; work ; -; |altsyncram_4ed1:auto_generated| ; 170 (3) ; 3 (3) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 167 (0) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; work ; -; |decode_qsa:decode3| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 ; work ; -; |mux_nob:mux2| ; 160 (160) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 160 (160) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 ; work ; -; |nios_system_push_switches:push_switches| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_push_switches:push_switches ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux:rsp_xbar_mux| ; 11 (11) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 113 (113) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 89 (89) ; 0 (0) ; 24 (24) ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_switches:switches| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 18 (18) ; |lights|nios_system:NiosII|nios_system_switches:switches ; altera_reserved_qsys_nios_system ; -; |sld_hub:auto_hub| ; 171 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (1) ; 11 (0) ; 86 (0) ; |lights|sld_hub:auto_hub ; work ; -; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 170 (127) ; 97 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 (58) ; 11 (11) ; 86 (61) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; work ; -; |sld_rom_sr:hub_info_reg| ; 23 (23) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 9 (9) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; work ; -; |sld_shadow_jsm:shadow_jsm| ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 19 (19) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; work ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+---------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+-------------+----------+---------------+---------------+-----------------------+-----+------+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; -+-------------+----------+---------------+---------------+-----------------------+-----+------+ -; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDG[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[13] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[14] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[15] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[16] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LEDR[17] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX4[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX5[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX6[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; HEX7[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_RS ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_RW ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_data[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_EN ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_ON ; Output ; -- ; -- ; -- ; -- ; -- ; -; LCD_BLON ; Output ; -- ; -- ; -- ; -- ; -- ; -; CLOCK_50 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[7] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[8] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[9] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -; SW[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[13] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[15] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[16] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; SW[17] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; -; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; -+-------------+----------+---------------+---------------+-----------------------+-----+------+ - - -+-----------------------------------------------------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+-----------------------------------------------------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+-----------------------------------------------------------------------------------+-------------------+---------+ -; CLOCK_50 ; ; ; -; SW[0] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[0] ; 0 ; 6 ; -; KEY[1] ; ; ; -; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[0] ; 0 ; 6 ; -; SW[1] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[1] ; 0 ; 6 ; -; KEY[2] ; ; ; -; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[1] ; 1 ; 6 ; -; SW[2] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[2] ; 0 ; 6 ; -; KEY[3] ; ; ; -; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[2] ; 1 ; 6 ; -; SW[3] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[3] ; 0 ; 6 ; -; SW[4] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[4] ; 1 ; 6 ; -; SW[5] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[5] ; 0 ; 6 ; -; SW[6] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[6] ; 0 ; 6 ; -; SW[7] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[7] ; 1 ; 6 ; -; SW[8] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[8] ; 0 ; 6 ; -; SW[9] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[9] ; 1 ; 6 ; -; SW[10] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[10] ; 0 ; 6 ; -; SW[11] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[11] ; 0 ; 6 ; -; SW[12] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[12] ; 0 ; 6 ; -; SW[13] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[13] ; 0 ; 6 ; -; SW[14] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[14] ; 0 ; 6 ; -; SW[15] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[15] ; 0 ; 6 ; -; SW[16] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[16] ; 0 ; 6 ; -; SW[17] ; ; ; -; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[17] ; 0 ; 6 ; -; KEY[0] ; ; ; -; - nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; 1 ; 6 ; -+-----------------------------------------------------------------------------------+-------------------+---------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ -; CLOCK_50 ; PIN_Y2 ; 1227 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; -; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y37_N0 ; 183 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; -; altera_internal_jtag~TMSUTAP ; JTAG_X1_Y37_N0 ; 21 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; LCCOMB_X67_Y39_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; LCCOMB_X66_Y37_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~23 ; LCCOMB_X69_Y39_N6 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X62_Y40_N18 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK14 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; FF_X60_Y39_N11 ; 791 ; Async. clear ; yes ; Global Clock ; GCLK17 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; FF_X60_Y39_N15 ; 204 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~1 ; LCCOMB_X68_Y36_N10 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~2 ; LCCOMB_X68_Y38_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X67_Y37_N16 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~1 ; LCCOMB_X66_Y37_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~2 ; LCCOMB_X67_Y40_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|update_grant~1 ; LCCOMB_X67_Y40_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex0|always0~1 ; LCCOMB_X70_Y38_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex1|always0~1 ; LCCOMB_X70_Y32_N2 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex2|always0~1 ; LCCOMB_X70_Y36_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex3|always0~1 ; LCCOMB_X69_Y37_N28 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex4|always0~1 ; LCCOMB_X69_Y37_N26 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex5|always0~1 ; LCCOMB_X68_Y34_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex6|always0~1 ; LCCOMB_X70_Y35_N8 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_hex0:hex7|always0~1 ; LCCOMB_X68_Y35_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|r_ena~0 ; LCCOMB_X66_Y44_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0]~4 ; LCCOMB_X63_Y44_N18 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1]~0 ; LCCOMB_X65_Y45_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled~1 ; LCCOMB_X63_Y44_N30 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~2 ; LCCOMB_X66_Y43_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_wr ; FF_X65_Y42_N9 ; 15 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF~2 ; LCCOMB_X67_Y38_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; LCCOMB_X66_Y43_N28 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; LCCOMB_X67_Y42_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val~0 ; LCCOMB_X66_Y44_N14 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|read_0 ; FF_X66_Y43_N27 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|wr_rfifo ; LCCOMB_X66_Y43_N4 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[4] ; FF_X63_Y36_N25 ; 41 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_result~26 ; LCCOMB_X65_Y33_N16 ; 49 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_new_inst ; FF_X62_Y34_N23 ; 42 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_valid ; FF_X61_Y32_N9 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_sel_nxt.10~0 ; LCCOMB_X61_Y31_N2 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_valid~0 ; LCCOMB_X66_Y40_N14 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_hi_imm16 ; FF_X60_Y35_N9 ; 17 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot ; FF_X63_Y34_N9 ; 22 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~31 ; LCCOMB_X62_Y34_N26 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_hi~0 ; LCCOMB_X61_Y37_N4 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[2] ; FF_X66_Y31_N27 ; 131 ; Output enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren ; LCCOMB_X60_Y39_N16 ; 2 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie_inst_nxt~2 ; LCCOMB_X61_Y31_N0 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_valid ; FF_X61_Y32_N29 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4]~0 ; LCCOMB_X66_Y36_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data_en~0 ; LCCOMB_X66_Y33_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~1 ; LCCOMB_X66_Y36_N18 ; 30 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[8] ; FF_X62_Y38_N17 ; 36 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jxuir ; FF_X60_Y43_N13 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a ; LCCOMB_X60_Y41_N10 ; 15 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; LCCOMB_X60_Y40_N14 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_b ; LCCOMB_X60_Y41_N20 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_no_action_break_a~0 ; LCCOMB_X61_Y43_N28 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|update_jdo_strobe ; FF_X60_Y43_N27 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2]~13 ; LCCOMB_X63_Y44_N8 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34]~21 ; LCCOMB_X62_Y44_N28 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36]~29 ; LCCOMB_X62_Y44_N4 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_sdr~0 ; LCCOMB_X63_Y44_N2 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_uir~0 ; LCCOMB_X60_Y43_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; LCCOMB_X65_Y40_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0]~9 ; LCCOMB_X60_Y40_N26 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_wr_en ; LCCOMB_X65_Y40_N22 ; 2 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1849w[3] ; LCCOMB_X67_Y31_N20 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1866w[3] ; LCCOMB_X67_Y31_N30 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1876w[3] ; LCCOMB_X67_Y31_N18 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1886w[3] ; LCCOMB_X67_Y31_N22 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1896w[3] ; LCCOMB_X67_Y31_N12 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1906w[3] ; LCCOMB_X67_Y31_N8 ; 32 ; Write enable ; no ; -- ; -- ; -- ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1916w[3] ; LCCOMB_X67_Y31_N2 ; 8 ; Write enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X61_Y46_N19 ; 71 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; LCCOMB_X60_Y45_N0 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; LCCOMB_X60_Y45_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; LCCOMB_X60_Y45_N26 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; LCCOMB_X61_Y45_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; LCCOMB_X61_Y45_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~5 ; LCCOMB_X60_Y46_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~12 ; LCCOMB_X60_Y46_N0 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3 ; LCCOMB_X60_Y44_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~14 ; LCCOMB_X60_Y45_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; LCCOMB_X60_Y45_N28 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; LCCOMB_X60_Y46_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; LCCOMB_X59_Y44_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; LCCOMB_X59_Y46_N28 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; LCCOMB_X65_Y46_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; LCCOMB_X66_Y46_N12 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; LCCOMB_X65_Y46_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X63_Y46_N13 ; 15 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X61_Y46_N7 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X61_Y46_N23 ; 40 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; FF_X61_Y46_N11 ; 46 ; Sync. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; FF_X61_Y46_N13 ; 13 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; LCCOMB_X61_Y46_N2 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; FF_X62_Y46_N25 ; 31 ; Async. clear ; no ; -- ; -- ; -- ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+--------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+--------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; CLOCK_50 ; PIN_Y2 ; 1227 ; 0 ; Global Clock ; GCLK4 ; -- ; -; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y37_N0 ; 183 ; 0 ; Global Clock ; GCLK1 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X62_Y40_N18 ; 3 ; 0 ; Global Clock ; GCLK14 ; -- ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; FF_X60_Y39_N11 ; 791 ; 0 ; Global Clock ; GCLK17 ; -- ; -+--------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; Name ; Fan-Out ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; 204 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[48] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[47] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[46] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[45] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[44] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[43] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[42] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[41] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[40] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[39] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[38] ; 200 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[50] ; 192 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[49] ; 192 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[2] ; 131 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[1] ; 112 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[0] ; 112 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[3] ; 111 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; 71 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_no_action_break_a~0 ; 64 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; 58 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; 51 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[35] ; 50 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[34] ; 50 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[33] ; 50 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[32] ; 50 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_result~26 ; 49 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; 46 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_access ; 46 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; 42 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_new_inst ; 42 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[4] ; 41 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; 40 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|update_jdo_strobe ; 39 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_sdr~0 ; 39 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|read_latency_shift_reg[0] ; 38 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[8] ; 36 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; 35 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_ld ; 35 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_valid~0 ; 34 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_b ; 33 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_aligning_data ; 33 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001|src0_valid ; 33 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_logic_op[0] ; 33 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1896w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1906w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1886w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1849w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1876w[3] ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1866w[3] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0]~9 ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_rd_d1 ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[36] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[37] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15]~0 ; 32 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[2] ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot_right ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~31 ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_use_imm ; 32 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_logic_op[1] ; 32 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; 31 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|readdata~0 ; 31 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~1 ; 30 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux|src1_valid ; 30 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~24 ; 29 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|uav_write~0 ; 29 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[6] ; 29 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[5] ; 28 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001|src1_valid ; 27 ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|read_latency_shift_reg[0] ; 27 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; 26 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench|d_write ; 26 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; 25 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_valid ; 25 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[14] ; 24 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|write~0 ; 24 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|write_accepted ; 24 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; 23 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|read_latency_shift_reg[0] ; 23 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|read_latency_shift_reg[0] ; 23 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; 23 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[2] ; 22 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot ; 22 ; -; altera_internal_jtag~TMSUTAP ; 21 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0]~4 ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15] ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[12] ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[3] ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_logic ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_sub ; 21 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28]~19 ; 20 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_valid ; 20 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28]~20 ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[21] ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[16] ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[1] ; 19 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[4] ; 19 ; -; altera_internal_jtag~TDIUTAP ; 18 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34]~21 ; 18 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; 18 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[0] ; 18 ; -; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~1 ; 18 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[0] ; 18 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~30 ; 17 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_hi_imm16 ; 17 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_br_cmp ; 17 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_read ; 17 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_wr ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr~19 ; 16 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|read_0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_fill_bit~1 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_sel_nxt.10~0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_jmp_direct ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_lo~0 ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[5] ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_rdctl_inst ; 16 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[1] ; 16 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie_inst_nxt~2 ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_hi~0 ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[11] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[6] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[5] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[4] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[3] ; 15 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[2] ; 15 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; 14 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; 14 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|wr_rfifo ; 14 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[13] ; 14 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|read_accepted ; 14 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~2 ; 14 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; 13 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; 13 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2]~13 ; 13 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~5 ; 13 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|read_latency_shift_reg[0] ; 13 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|read_latency_shift_reg[0] ; 13 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; 12 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|read_latency_shift_reg[0] ; 12 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal8~0 ; 12 ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~1 ; 12 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; 11 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; 11 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val~0 ; 11 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; 11 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 11 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; 10 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; 10 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal133~0 ; 10 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|waitrequest ; 10 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; 9 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; 9 ; -; ~GND ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_fill_bit~0 ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_ld_signed ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; 9 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[6] ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[8] ; 9 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[7] ; 9 ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 9 ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 9 ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; 9 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal9~0 ; 9 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; 8 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1]~0 ; 8 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~2 ; 8 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 8 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1916w[3] ; 8 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[52] ; 8 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[53] ; 8 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[51] ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data_en~0 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4]~0 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~0 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_retaddr~0 ; 8 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal16~1 ; 8 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|read_latency_shift_reg[0] ; 8 ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~2 ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[8] ; 8 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[7] ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~31 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~30 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~29 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~28 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~27 ; 7 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~26 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~25 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~24 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~23 ; 7 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~22 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~21 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~20 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~19 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~18 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~17 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~16 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~15 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~14 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~13 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~12 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~11 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~10 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~9 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~8 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~7 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~6 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~5 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~4 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~3 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~2 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~1 ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~0 ; 7 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|wren~0 ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[35] ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_break ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_exception ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|write ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|i_read ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_cdr ; 7 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[0] ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex7|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex6|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex5|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~4 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex4|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex3|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex2|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex1|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_hex0:hex0|always0~1 ; 7 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[7] ; 7 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~1 ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|t_ena~reg0 ; 6 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[0] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|Equal0~0 ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[2] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[3] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[4] ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_b_is_dst~1 ; 6 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_valid ; 6 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_blon|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_on|always0~0 ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|read_latency_shift_reg[0] ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|read_latency_shift_reg[0] ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~23 ; 6 ; -; nios_system:NiosII|nios_system_hex0:hex6|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_hex0:hex5|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_hex0:hex3|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~0 ; 6 ; -; nios_system:NiosII|nios_system_LEDs:leds|always0~0 ; 6 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|uav_read~0 ; 6 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[4] ; 6 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~14 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]~0 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~12 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~5 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_proc~0 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal11~0 ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled~1 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~1 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~0 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_result[1]~5 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_result[0]~4 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3]~0 ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate~0 ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift~6 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[34] ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[17] ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~5 ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_req~0 ; 5 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|cp_valid ; 5 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator|read_accepted ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1]~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex7|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex4|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex2|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex1|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_hex0:hex0|always0~0 ; 5 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[0] ; 5 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~1 ; 5 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; 5 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[5] ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~0 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~3 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|m0_write~2 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~2 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[30] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[20] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[21] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[22] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[23] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[24] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[25] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[26] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[27] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[28] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[29] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[19] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_align_cycle[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_getting_data~13 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux|src0_valid ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; 4 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_uir~0 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|update_grant~1 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~1 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|local_read~1 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux|src0_valid~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|WideOr1 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001|src1_valid~0 ; 4 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux|src1_valid~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0]~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[17] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[18] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[19] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[20] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_shift_logical~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_br_nxt~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~4 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~3 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0]~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1]~0 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|Mux37~0 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal0~2 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|m0_write~0 ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[4] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_waitrequest_generated~2 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[2] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[3] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal4~2 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~3 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[10] ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal2~2 ; 4 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[0] ; 4 ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonARegAddrInc[8]~16 ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[1] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[2] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[3] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[4] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[5] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[6] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[7] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[0] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[6] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[7] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[8] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[9] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[10] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[11] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[12] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[13] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[14] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[15] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[16] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[17] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[18] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[4] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[2] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[3] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[13] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[14] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[9] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[10] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[11] ; 4 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[12] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~9 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg~8 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~11 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~4 ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_logic~9 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF~2 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[24] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[23] ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write1 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift~11 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_error ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest~1 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[18] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[19] ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst2 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|r_ena1 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[25] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_ocireg~0 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[26] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[27] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[28] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[29] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[30] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[31] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_wrctl_inst ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_single_step_mode ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[20] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[21] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_bstatus_reg ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_estatus_reg ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[31] ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid0 ; 3 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|t_dav ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|ir[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|ir[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|enable_action_strobe ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_align_cycle[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_implicit_dst_retaddr~0 ; 3 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|av_readdatavalid~0 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|read ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|WideOr1 ; 3 ; -; nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001|src0_valid~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|nios_system_addr_router:addr_router|Equal0~1 ; 3 ; -; nios_system:NiosII|nios_system_addr_router:addr_router|Equal0~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[3] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_force_src2_zero ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~2 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1]~0 ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|av_waitrequest~2 ; 3 ; -; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|write_accepted~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal7~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_getting_data~12 ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[6] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[8] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[15] ; 3 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal3~0 ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[17] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[8] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; 3 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_blon|data_out ; 3 ; -; nios_system:NiosII|nios_system_lcd_on:lcd_on|data_out ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[24] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[25] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[26] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[27] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[28] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[23] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[29] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[30] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[21] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[31] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[30] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[19] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[20] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[21] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[22] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[23] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[24] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[25] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[26] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[27] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[28] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[29] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[20] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|jtag_break ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[19] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[4] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[6] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[8] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[2] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[0] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[1] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[6] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[5] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[8] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[7] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[13] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[14] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[9] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[10] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[11] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[12] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[17] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[18] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[17] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[18] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[4] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[2] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[3] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[1] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[3] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[2] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[15] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[16] ; 3 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[17] ; 3 ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[5] ; 3 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg_proc~0 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~0 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~6 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg~1 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]~7 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~1 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~0 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~3 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~2 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~1 ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_wr_dst_reg~4 ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~2 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|read_latency_shift_reg~3 ; 2 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal4~3 ; 2 ; -; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|src_channel[1]~9 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[13] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[9] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[11] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[10] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[12] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[15] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[14] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[7] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[23] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[24] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[25] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[26] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[27] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[28] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[30] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|resetlatch ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[16] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[17] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[22] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[10] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[15] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[14] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[13] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[11] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|always2~0 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write2 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[19] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[20] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[30]~34 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[20]~33 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[21]~32 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[22]~31 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[23]~30 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[24]~29 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[25]~28 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[26]~27 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[27]~26 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[28]~25 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[29]~24 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[31]~23 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36]~29 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[16] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[19]~22 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_go ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[7] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|rvalid ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[6] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|woverflow ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[3] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ac ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|t_pause~reg0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[23] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid0~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|always1~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|avalon_ram_wr~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_rd ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_rd ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[7]~7 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[6]~6 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[5]~5 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[4]~4 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[3]~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[2]~2 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[1]~1 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[0]~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_wr_en ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|debugaccess ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_wr ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jxuir ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[32] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[33] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[18] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[19] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[20] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[22] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_fill_bit~0 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[31]~95 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[31] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[30]~92 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[30] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[29]~89 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[29] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[28]~86 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[28] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[27]~83 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[27] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[2] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_readdata[8]~0 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|pause_irq ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_readdata[9] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AE ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_crst ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg_nxt~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|break_on_reset ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_wrctl_status~0 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[26]~80 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[26] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[25]~77 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[25] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[24]~74 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[24] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[23]~71 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[23] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_wrctl_bstatus~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_src1[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_src2[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_invert_arith_src_msb ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[30]~32 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[1]~31 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[19]~30 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[20]~29 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[21]~28 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[22]~27 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[23]~26 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[24]~25 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[25]~24 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[26]~23 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[27]~22 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[28]~21 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[29]~20 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[31]~19 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[31] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[0]~18 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_compare_op[1] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_compare_op[0] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[2]~6 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[4]~5 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3]~4 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[1]~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[0]~1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state~1 ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[5] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[6] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[9] ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|grant[0]~1 ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|grant[0]~1 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[17]~68 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[17] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[18]~65 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[18] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[19]~62 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[19] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[20]~59 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[20] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[21]~56 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[21] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[18]~21 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[22]~53 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[22] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[10]~50 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[10] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[6]~47 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[6] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[8]~44 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[8] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~2 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_no_crst_nxt[16]~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_jmp_direct~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_stall~5 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_aligning_data_nxt~1 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_waiting_for_data_nxt~0 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[7]~41 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[7] ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_force_src2_zero~3 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_break~0 ; 2 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~4 ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[9]~38 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[9] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[15]~35 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[15] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[16]~32 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[16] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[14]~29 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[14] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[5]~26 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[5] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[12]~23 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[12] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[13]~20 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[13] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[11]~17 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[11] ; 2 ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[2]~14 ; 2 ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[2] ; 2 ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter RAM Summary ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ -; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; no ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X64_Y45_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X64_Y44_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 256 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 8192 ; 256 ; 32 ; -- ; -- ; 8192 ; 1 ; nios_system_nios2_processor_ociram_default_contents.mif ; M9K_X64_Y39_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; nios_system_nios2_processor_rf_ram_a.mif ; M9K_X64_Y32_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; nios_system_nios2_processor_rf_ram_b.mif ; M9K_X64_Y33_N0 ; Don't care ; Old data ; Old data ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 51200 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1638400 ; 51200 ; 32 ; -- ; -- ; 1638400 ; 200 ; nios_system_onchip_memory.hex ; M9K_X64_Y55_N0, M9K_X78_Y56_N0, M9K_X78_Y52_N0, M9K_X78_Y55_N0, M9K_X78_Y40_N0, M9K_X78_Y46_N0, M9K_X64_Y60_N0, M9K_X64_Y56_N0, M9K_X64_Y57_N0, M9K_X78_Y57_N0, M9K_X64_Y50_N0, M9K_X78_Y50_N0, M9K_X51_Y55_N0, M9K_X64_Y48_N0, M9K_X78_Y41_N0, M9K_X51_Y51_N0, M9K_X78_Y51_N0, M9K_X37_Y49_N0, M9K_X64_Y27_N0, M9K_X78_Y25_N0, M9K_X64_Y24_N0, M9K_X64_Y53_N0, M9K_X64_Y51_N0, M9K_X64_Y47_N0, M9K_X78_Y47_N0, M9K_X51_Y42_N0, M9K_X78_Y53_N0, M9K_X78_Y24_N0, M9K_X51_Y22_N0, M9K_X64_Y22_N0, M9K_X64_Y31_N0, M9K_X78_Y39_N0, M9K_X78_Y42_N0, M9K_X78_Y19_N0, M9K_X64_Y38_N0, M9K_X64_Y36_N0, M9K_X64_Y19_N0, M9K_X64_Y42_N0, M9K_X64_Y40_N0, M9K_X51_Y45_N0, M9K_X37_Y46_N0, M9K_X51_Y46_N0, M9K_X37_Y44_N0, M9K_X37_Y43_N0, M9K_X64_Y41_N0, M9K_X51_Y47_N0, M9K_X64_Y46_N0, M9K_X37_Y47_N0, M9K_X64_Y43_N0, M9K_X51_Y48_N0, M9K_X51_Y49_N0, M9K_X78_Y58_N0, M9K_X64_Y58_N0, M9K_X64_Y59_N0, M9K_X64_Y54_N0, M9K_X64_Y61_N0, M9K_X64_Y52_N0, M9K_X78_Y44_N0, M9K_X64_Y49_N0, M9K_X78_Y49_N0, M9K_X78_Y43_N0, M9K_X78_Y45_N0, M9K_X78_Y48_N0, M9K_X37_Y16_N0, M9K_X64_Y10_N0, M9K_X37_Y25_N0, M9K_X37_Y26_N0, M9K_X37_Y21_N0, M9K_X51_Y30_N0, M9K_X64_Y13_N0, M9K_X64_Y9_N0, M9K_X78_Y16_N0, M9K_X78_Y13_N0, M9K_X51_Y12_N0, M9K_X78_Y21_N0, M9K_X64_Y12_N0, M9K_X51_Y31_N0, M9K_X37_Y31_N0, M9K_X37_Y41_N0, M9K_X78_Y15_N0, M9K_X37_Y20_N0, M9K_X78_Y23_N0, M9K_X51_Y27_N0, M9K_X64_Y26_N0, M9K_X51_Y26_N0, M9K_X78_Y33_N0, M9K_X78_Y27_N0, M9K_X78_Y31_N0, M9K_X78_Y14_N0, M9K_X64_Y11_N0, M9K_X51_Y37_N0, M9K_X51_Y13_N0, M9K_X37_Y30_N0, M9K_X51_Y28_N0, M9K_X51_Y16_N0, M9K_X51_Y29_N0, M9K_X37_Y29_N0, M9K_X37_Y28_N0, M9K_X37_Y27_N0, M9K_X64_Y21_N0, M9K_X64_Y25_N0, M9K_X51_Y9_N0, M9K_X51_Y15_N0, M9K_X51_Y24_N0, M9K_X51_Y14_N0, M9K_X51_Y18_N0, M9K_X78_Y12_N0, M9K_X51_Y10_N0, M9K_X37_Y14_N0, M9K_X64_Y14_N0, M9K_X51_Y11_N0, M9K_X51_Y17_N0, M9K_X15_Y29_N0, M9K_X78_Y28_N0, M9K_X37_Y38_N0, M9K_X78_Y26_N0, M9K_X78_Y29_N0, M9K_X37_Y33_N0, M9K_X15_Y32_N0, M9K_X37_Y36_N0, M9K_X37_Y32_N0, M9K_X51_Y32_N0, M9K_X15_Y36_N0, M9K_X15_Y35_N0, M9K_X37_Y34_N0, M9K_X37_Y54_N0, M9K_X51_Y62_N0, M9K_X37_Y39_N0, M9K_X37_Y45_N0, M9K_X37_Y59_N0, M9K_X37_Y51_N0, M9K_X78_Y18_N0, M9K_X64_Y16_N0, M9K_X64_Y15_N0, M9K_X78_Y34_N0, M9K_X64_Y29_N0, M9K_X15_Y34_N0, M9K_X51_Y60_N0, M9K_X64_Y62_N0, M9K_X51_Y59_N0, M9K_X51_Y57_N0, M9K_X51_Y61_N0, M9K_X51_Y34_N0, M9K_X64_Y28_N0, M9K_X51_Y40_N0, M9K_X37_Y42_N0, M9K_X64_Y35_N0, M9K_X51_Y41_N0, M9K_X37_Y40_N0, M9K_X51_Y38_N0, M9K_X78_Y38_N0, M9K_X37_Y55_N0, M9K_X51_Y39_N0, M9K_X37_Y52_N0, M9K_X78_Y35_N0, M9K_X51_Y43_N0, M9K_X37_Y35_N0, M9K_X51_Y19_N0, M9K_X51_Y35_N0, M9K_X37_Y37_N0, M9K_X64_Y20_N0, M9K_X37_Y22_N0, M9K_X37_Y19_N0, M9K_X51_Y56_N0, M9K_X51_Y54_N0, M9K_X51_Y53_N0, M9K_X104_Y50_N0, M9K_X78_Y54_N0, M9K_X51_Y52_N0, M9K_X51_Y58_N0, M9K_X37_Y50_N0, M9K_X37_Y57_N0, M9K_X37_Y48_N0, M9K_X37_Y58_N0, M9K_X51_Y50_N0, M9K_X64_Y23_N0, M9K_X64_Y18_N0, M9K_X78_Y22_N0, M9K_X64_Y17_N0, M9K_X78_Y20_N0, M9K_X64_Y30_N0, M9K_X78_Y17_N0, M9K_X51_Y23_N0, M9K_X37_Y53_N0, M9K_X51_Y21_N0, M9K_X37_Y56_N0, M9K_X51_Y44_N0, M9K_X37_Y23_N0, M9K_X64_Y34_N0, M9K_X78_Y36_N0, M9K_X51_Y33_N0, M9K_X64_Y37_N0, M9K_X78_Y37_N0, M9K_X78_Y30_N0, M9K_X51_Y25_N0, M9K_X78_Y32_N0, M9K_X51_Y36_N0, M9K_X51_Y20_N0, M9K_X37_Y18_N0, M9K_X37_Y24_N0 ; Don't care ; Old data ; Old data ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ -Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. - - -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; -+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;8;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;16;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;24;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; - - -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; -+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;8;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;16;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; -;24;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; - - -RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; -+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; -;8;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; -;16;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; -;24;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; 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-;224;(10101100000011100100100111110101) (-226849365) (-1408349707) (-5-3-15-1-11-60-11) ;(11001001101001011110101001110110) (1963521980) (-911873418) (-3-6-5-10-1-5-8-10) ;(00000101101100000100110110000110) (554046606) (95440262) (5B04D86) ;(10110010100110101100011100010010) (616249292) (-1298479342) (-4-13-6-5-3-8-14-14) ;(01001110001101000100010010010011) (-532441425) (1312048275) (4E344493) ;(11010100010111101101111001001000) (-1055253374) (-731980216) (-2-11-10-1-2-1-11-8) ;(00111101101001111110010000100110) (-1038172546) (1034413094) (3DA7E426) ;(01001101011010101000100100110111) (-614979181) (1298827575) (4D6A8937) ; -;232;(10011001101101011001101111010100) (1819988890) (-1716151340) (-6-6-4-10-6-4-2-12) ;(00011111100010100101011101010001) (-552513775) (529160017) (1F8A5751) ;(10001011000001111110011001001110) (-33563718) (-1962416562) (-7-4-15-8-1-9-11-2) ;(10110100110111001101010010010110) (836858096) (-1260596074) (-4-11-2-3-2-11-6-10) ;(01000010111110000100111111100110) (-1871435902) (1123569638) (42F84FE6) ;(11110001110101011001010100101111) (-1612465321) (-237660881) (-14-2-10-6-10-13-1) ;(10100010111001011010010000101101) (-1358972075) (-1562008531) (-5-13-1-10-5-11-13-3) ;(00010101101100011010111100010110) (-1740639870) (363966230) (15B1AF16) ; -;240;(00010110100000000001001010111100) (-1654956022) (377492156) (168012BC) ;(00101110001001110110011000010010) (1316695726) (774333970) (2E276612) ;(10001001100100010011111010101010) (-191089582) (-1986969942) (-7-6-6-14-12-1-5-6) ;(11000110000001111010000110100010) (1413877456) (-972578398) (-3-9-15-8-5-14-5-14) ;(11111101100010110101010001001101) (-235125663) (-41200563) (-2-7-4-10-11-11-3) ;(10101110110000110001101001010011) (30320993) (-1362945453) (-5-1-3-12-14-5-10-13) ;(00100101111110010101100010101101) (281286959) (637098157) (25F958AD) ;(00110110010110010000001111101100) (-1963732838) (911803372) (365903EC) ; -;248;(00010100011101100001100001100101) (-1859553151) (343283813) (14761865) ;(01010110100011001100001000111011) (495657425) (1452065339) (568CC23B) ;(10110000001110000110001100000101) (385767275) (-1338481915) (-4-15-12-7-9-12-15-11) ;(11111011100111101011110110001010) (-430241166) (-73482870) (-4-6-1-4-2-7-6) ;(10100010010110010001000111010100) (-1404083406) (-1571221036) (-5-13-10-6-14-14-2-12) ;(10000000011011100011111110111011) (-1301889161) (-2140258373) (-7-15-9-1-120-4-5) ;(10011101111100110101001001100100) (-2055642986) (-1644998044) (-6-20-12-10-13-9-12) ;(11010110001010110011100000010100) (-870176458) (-701810668) (-2-9-13-4-12-7-14-12) ; - - -+---------------------------------------------------------+ -; Other Routing Usage Summary ; -+-----------------------------+---------------------------+ -; Other Routing Resource Type ; Usage ; -+-----------------------------+---------------------------+ -; Block interconnects ; 6,716 / 342,891 ( 2 % ) ; -; C16 interconnects ; 375 / 10,120 ( 4 % ) ; -; C4 interconnects ; 4,305 / 209,544 ( 2 % ) ; -; Direct links ; 341 / 342,891 ( < 1 % ) ; -; Global clocks ; 4 / 20 ( 20 % ) ; -; Local interconnects ; 1,184 / 119,088 ( < 1 % ) ; -; R24 interconnects ; 439 / 9,963 ( 4 % ) ; -; R4 interconnects ; 3,940 / 289,782 ( 1 % ) ; -+-----------------------------+---------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Logic Elements ; -+---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 14.31) ; Number of LABs (Total = 156) ; -+---------------------------------------------+-------------------------------+ -; 1 ; 1 ; -; 2 ; 2 ; -; 3 ; 1 ; -; 4 ; 1 ; -; 5 ; 1 ; -; 6 ; 1 ; -; 7 ; 1 ; -; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 4 ; -; 11 ; 5 ; -; 12 ; 7 ; -; 13 ; 1 ; -; 14 ; 18 ; -; 15 ; 28 ; -; 16 ; 82 ; -+---------------------------------------------+-------------------------------+ - - -+--------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 2.23) ; Number of LABs (Total = 156) ; -+------------------------------------+-------------------------------+ -; 1 Async. clear ; 109 ; -; 1 Clock ; 129 ; -; 1 Clock enable ; 52 ; -; 1 Sync. clear ; 6 ; -; 1 Sync. load ; 28 ; -; 2 Async. clears ; 3 ; -; 2 Clock enables ; 12 ; -; 2 Clocks ; 9 ; -+------------------------------------+-------------------------------+ - - -+------------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 21.70) ; Number of LABs (Total = 156) ; -+----------------------------------------------+-------------------------------+ -; 0 ; 1 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 1 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 1 ; -; 7 ; 1 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 2 ; -; 11 ; 0 ; -; 12 ; 3 ; -; 13 ; 2 ; -; 14 ; 4 ; -; 15 ; 2 ; -; 16 ; 17 ; -; 17 ; 3 ; -; 18 ; 5 ; -; 19 ; 4 ; -; 20 ; 9 ; -; 21 ; 6 ; -; 22 ; 7 ; -; 23 ; 18 ; -; 24 ; 14 ; -; 25 ; 17 ; -; 26 ; 9 ; -; 27 ; 11 ; -; 28 ; 3 ; -; 29 ; 5 ; -; 30 ; 2 ; -; 31 ; 3 ; -; 32 ; 5 ; -+----------------------------------------------+-------------------------------+ - - -+---------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 9.19) ; Number of LABs (Total = 156) ; -+-------------------------------------------------+-------------------------------+ -; 0 ; 1 ; -; 1 ; 0 ; -; 2 ; 8 ; -; 3 ; 4 ; -; 4 ; 15 ; -; 5 ; 7 ; -; 6 ; 10 ; -; 7 ; 12 ; -; 8 ; 15 ; -; 9 ; 12 ; -; 10 ; 16 ; -; 11 ; 9 ; -; 12 ; 8 ; -; 13 ; 12 ; -; 14 ; 5 ; -; 15 ; 6 ; -; 16 ; 11 ; -; 17 ; 3 ; -; 18 ; 0 ; -; 19 ; 0 ; -; 20 ; 2 ; -+-------------------------------------------------+-------------------------------+ - - -+------------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 19.24) ; Number of LABs (Total = 156) ; -+----------------------------------------------+-------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 3 ; -; 5 ; 4 ; -; 6 ; 1 ; -; 7 ; 3 ; -; 8 ; 4 ; -; 9 ; 1 ; -; 10 ; 2 ; -; 11 ; 2 ; -; 12 ; 9 ; -; 13 ; 4 ; -; 14 ; 7 ; -; 15 ; 4 ; -; 16 ; 9 ; -; 17 ; 4 ; -; 18 ; 11 ; -; 19 ; 7 ; -; 20 ; 7 ; -; 21 ; 10 ; -; 22 ; 8 ; -; 23 ; 5 ; -; 24 ; 5 ; -; 25 ; 5 ; -; 26 ; 12 ; -; 27 ; 4 ; -; 28 ; 3 ; -; 29 ; 2 ; -; 30 ; 2 ; -; 31 ; 3 ; -; 32 ; 6 ; -; 33 ; 5 ; -; 34 ; 1 ; -+----------------------------------------------+-------------------------------+ - - -+------------------------------------------+ -; I/O Rules Summary ; -+----------------------------------+-------+ -; I/O Rules Statistic ; Total ; -+----------------------------------+-------+ -; Total I/O Rules ; 30 ; -; Number of I/O Rules Passed ; 12 ; -; Number of I/O Rules Failed ; 0 ; -; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 18 ; -+----------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Details ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; -; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; -; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; -; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; -; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; -; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; -; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; -; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; -; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; -+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Total Pass ; 118 ; 0 ; 118 ; 0 ; 0 ; 122 ; 118 ; 0 ; 122 ; 122 ; 0 ; 49 ; 0 ; 0 ; 31 ; 0 ; 49 ; 31 ; 0 ; 0 ; 0 ; 49 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 ; 0 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 4 ; 122 ; 4 ; 122 ; 122 ; 0 ; 4 ; 122 ; 0 ; 0 ; 122 ; 73 ; 122 ; 122 ; 91 ; 122 ; 73 ; 91 ; 122 ; 122 ; 122 ; 73 ; 122 ; 122 ; 122 ; 122 ; 122 ; 0 ; 122 ; 122 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; LEDG[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDG[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LEDR[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX3[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX4[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX5[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX6[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HEX7[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_RS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_RW ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_data[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_EN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_ON ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LCD_BLON ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SW[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ - - -+---------------------------------------------------------------------------------------------+ -; Fitter Device Options ; -+------------------------------------------------------------------+--------------------------+ -; Option ; Setting ; -+------------------------------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Active Serial ; -; Error detection CRC ; Off ; -; Enable open drain on CRC_ERROR pin ; Off ; -; Enable input tri-state on active configuration pins in user mode ; Off ; -; Configuration Voltage Level ; Auto ; -; Force Configuration Voltage Level ; Off ; -; nCEO ; As output driving ground ; -; Data[0] ; As input tri-stated ; -; Data[1]/ASDO ; As input tri-stated ; -; Data[7..2] ; Unreserved ; -; FLASH_nCE/nCSO ; As input tri-stated ; -; Other Active Parallel pins ; Unreserved ; -; DCLK ; As output driving ground ; -; Base pin-out file on sameframe device ; Off ; -+------------------------------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 �C ; -; High Junction Temperature ; 85 �C ; -+---------------------------+--------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (119006): Selected device EP4CE115F29C7 for design "lights" -Info (21077): Core supply voltage is 1.2V -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. -Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info (176445): Device EP4CE40F29C7 is compatible - Info (176445): Device EP4CE40F29I7 is compatible - Info (176445): Device EP4CE30F29C7 is compatible - Info (176445): Device EP4CE30F29I7 is compatible - Info (176445): Device EP4CE55F29C7 is compatible - Info (176445): Device EP4CE55F29I7 is compatible - Info (176445): Device EP4CE75F29C7 is compatible - Info (176445): Device EP4CE75F29I7 is compatible - Info (176445): Device EP4CE115F29I7 is compatible -Info (169124): Fitter converted 5 user pins into dedicated programming pins - Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4 - Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 - Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3 - Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7 - Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28 -Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. -Info (332164): Evaluating HDL-embedded SDC commands - Info (332165): Entity alt_jtag_atlantic - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] - Info (332165): Entity altera_std_synchronizer - Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] - Info (332165): Entity sld_jtag_hub - Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz - Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} -Critical Warning (332012): Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements -Info (332111): Found 1 clocks - Info (332111): Period Clock Name - Info (332111): ======== ============ - Info (332111): 100.000 altera_reserved_tck -Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 -Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock -Info (176353): Automatically promoted node nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock - Info (176356): Following destination nodes may be non-global or may not use global or regional clocks - Info (176357): Destination node nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 - Info (176357): Destination node nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren - Info (176357): Destination node nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 -Info (176353): Automatically promoted node nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 - Info (176355): Automatically promoted destinations to use location or clock signal Global Clock -Info (176233): Starting register packing -Info (176235): Finished register packing - Extra Info (176218): Packed 8 registers into blocks of type EC -Warning (15709): Ignored I/O standard assignments to the following nodes - Warning (15710): Ignored I/O standard assignment to node "AUD_ADCDAT" - Warning (15710): Ignored I/O standard assignment to node "AUD_ADCLRCK" - Warning (15710): Ignored I/O standard assignment to node "AUD_BCLK" - Warning (15710): Ignored I/O standard assignment to node "AUD_DACDAT" - Warning (15710): Ignored I/O standard assignment to node "AUD_DACLRCK" - Warning (15710): Ignored I/O standard assignment to node "AUD_XCK" - Warning (15710): Ignored I/O standard assignment to node "CLOCK2_50" - Warning (15710): Ignored I/O standard assignment to node "CLOCK3_50" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_BA[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_BA[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CAS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CKE" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CLK" - Warning (15710): Ignored I/O standard assignment to node "DRAM_CS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[10]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[11]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[12]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[13]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[14]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[15]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[16]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[17]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[18]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[19]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[20]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[21]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[22]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[23]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[24]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[25]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[26]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[27]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[28]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[29]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[30]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[31]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[8]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[9]" - Warning (15710): Ignored I/O standard assignment to node "DRAM_RAS_N" - Warning (15710): Ignored I/O standard assignment to node "DRAM_WE_N" - Warning (15710): Ignored I/O standard assignment to node "EEP_I2C_SCLK" - Warning (15710): Ignored I/O standard assignment to node "EEP_I2C_SDAT" - Warning (15710): Ignored I/O standard assignment to node "ENET0_GTX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET0_INT_N" - Warning (15710): Ignored I/O standard assignment to node "ENET0_LINK100" - Warning (15710): Ignored I/O standard assignment to node "ENET0_MDC" - Warning (15710): Ignored I/O standard assignment to node "ENET0_MDIO" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RST_N" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_COL" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_CRS" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DV" - Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_EN" - Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENET1_GTX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET1_INT_N" - Warning (15710): Ignored I/O standard assignment to node "ENET1_LINK100" - Warning (15710): Ignored I/O standard assignment to node "ENET1_MDC" - Warning (15710): Ignored I/O standard assignment to node "ENET1_MDIO" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RST_N" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_COL" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_CRS" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DV" - Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_CLK" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_EN" - Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_ER" - Warning (15710): Ignored I/O standard assignment to node "ENETCLK_25" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[0]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[1]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[2]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[3]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[4]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[5]" - Warning (15710): Ignored I/O standard assignment to node "EX_IO[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[22]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "FL_CE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "FL_OE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_RST_N" - Warning (15710): Ignored I/O standard assignment to node "FL_RY" - Warning (15710): Ignored I/O standard assignment to node "FL_WE_N" - Warning (15710): Ignored I/O standard assignment to node "FL_WP_N" - Warning (15710): Ignored I/O standard assignment to node "GPIO[0]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[10]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[11]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[12]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[13]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[14]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[15]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[16]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[17]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[18]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[19]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[1]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[20]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[21]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[22]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[23]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[24]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[25]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[26]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[27]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[28]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[29]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[2]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[30]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[31]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[32]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[33]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[34]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[35]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[3]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[4]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[5]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[6]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[7]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[8]" - Warning (15710): Ignored I/O standard assignment to node "GPIO[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN0" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_N1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_N2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_P1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_P2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT0" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_N1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_N2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_P1" - Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_P2" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_D[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[9]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[0]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[10]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[11]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[12]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[13]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[14]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[15]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[16]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[1]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[2]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[3]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[4]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[5]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[6]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[7]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[8]" - Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[9]" - Warning (15710): Ignored I/O standard assignment to node "I2C_SCLK" - Warning (15710): Ignored I/O standard assignment to node "I2C_SDAT" - Warning (15710): Ignored I/O standard assignment to node "IRDA_RXD" - Warning (15710): Ignored I/O standard assignment to node "LEDG[8]" - Warning (15710): Ignored I/O standard assignment to node "OTG_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_CS_N" - Warning (15710): Ignored I/O standard assignment to node "OTG_DACK_N[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DACK_N[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[10]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[11]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[12]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[13]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[14]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[15]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[4]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[5]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[6]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[7]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[8]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[9]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DREQ[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_DREQ[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_FSPEED" - Warning (15710): Ignored I/O standard assignment to node "OTG_INT[0]" - Warning (15710): Ignored I/O standard assignment to node "OTG_INT[1]" - Warning (15710): Ignored I/O standard assignment to node "OTG_LSPEED" - Warning (15710): Ignored I/O standard assignment to node "OTG_RD_N" - Warning (15710): Ignored I/O standard assignment to node "OTG_RST_N" - Warning (15710): Ignored I/O standard assignment to node "OTG_WR_N" - Warning (15710): Ignored I/O standard assignment to node "PS2_CLK" - Warning (15710): Ignored I/O standard assignment to node "PS2_CLK2" - Warning (15710): Ignored I/O standard assignment to node "PS2_DAT" - Warning (15710): Ignored I/O standard assignment to node "PS2_DAT2" - Warning (15710): Ignored I/O standard assignment to node "SD_CLK" - Warning (15710): Ignored I/O standard assignment to node "SD_CMD" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[0]" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[1]" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[2]" - Warning (15710): Ignored I/O standard assignment to node "SD_DAT[3]" - Warning (15710): Ignored I/O standard assignment to node "SD_WP_N" - Warning (15710): Ignored I/O standard assignment to node "SMA_CLKIN" - Warning (15710): Ignored I/O standard assignment to node "SMA_CLKOUT" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[0]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[10]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[11]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[12]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[13]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[14]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[15]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[16]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[17]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[18]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[19]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[1]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[2]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[3]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[4]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[5]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[6]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[7]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[8]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[9]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_CE_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[0]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[10]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[11]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[12]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[13]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[14]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[15]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[1]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[2]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[3]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[4]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[5]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[6]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[7]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[8]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[9]" - Warning (15710): Ignored I/O standard assignment to node "SRAM_LB_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_OE_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_UB_N" - Warning (15710): Ignored I/O standard assignment to node "SRAM_WE_N" - Warning (15710): Ignored I/O standard assignment to node "TD_CLK27" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[0]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[1]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[2]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[3]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[4]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[5]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[6]" - Warning (15710): Ignored I/O standard assignment to node "TD_DATA[7]" - Warning (15710): Ignored I/O standard assignment to node "TD_HS" - Warning (15710): Ignored I/O standard assignment to node "TD_RESET_N" - Warning (15710): Ignored I/O standard assignment to node "TD_VS" - Warning (15710): Ignored I/O standard assignment to node "UART_CTS" - Warning (15710): Ignored I/O standard assignment to node "UART_RTS" - Warning (15710): Ignored I/O standard assignment to node "UART_RXD" - Warning (15710): Ignored I/O standard assignment to node "UART_TXD" - Warning (15710): Ignored I/O standard assignment to node "VGA_BLANK_N" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[0]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[1]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[2]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[3]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[4]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[5]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[6]" - Warning (15710): Ignored I/O standard assignment to node "VGA_B[7]" - Warning (15710): Ignored I/O standard assignment to node "VGA_CLK" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[0]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[1]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[2]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[3]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[4]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[5]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[6]" - Warning (15710): Ignored I/O standard assignment to node "VGA_G[7]" - Warning (15710): Ignored I/O standard assignment to node "VGA_HS" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[0]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[1]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[2]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[3]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[4]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[5]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[6]" - Warning (15710): Ignored I/O standard assignment to node "VGA_R[7]" - Warning (15710): Ignored I/O standard assignment to node "VGA_SYNC_N" - Warning (15710): Ignored I/O standard assignment to node "VGA_VS" -Warning (15705): Ignored locations or region assignments to the following nodes - Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design - Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design - Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design - Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design - Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design - Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DACK_N[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DACK_N[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_DREQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_FSPEED" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_INT[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_INT[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_LSPEED" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design - Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design - Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design - Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design - Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:05 -Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 -Info (170191): Fitter placement operations beginning -Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 -Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 2% of the available device resources - Info (170196): Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X58_Y24 to location X68_Y36 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:03 -Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info (170201): Optimizations that may affect the design's routability were skipped - Info (170200): Optimizations that may affect the design's timing were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 0.75 seconds. -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:04 -Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Warning (169177): 9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. - Info (169178): Pin LCD_data[0] uses I/O standard 3.3-V LVTTL at L3 - Info (169178): Pin LCD_data[1] uses I/O standard 3.3-V LVTTL at L1 - Info (169178): Pin LCD_data[2] uses I/O standard 3.3-V LVTTL at L2 - Info (169178): Pin LCD_data[3] uses I/O standard 3.3-V LVTTL at K7 - Info (169178): Pin LCD_data[4] uses I/O standard 3.3-V LVTTL at K1 - Info (169178): Pin LCD_data[5] uses I/O standard 3.3-V LVTTL at K2 - Info (169178): Pin LCD_data[6] uses I/O standard 3.3-V LVTTL at M3 - Info (169178): Pin LCD_data[7] uses I/O standard 3.3-V LVTTL at M5 - Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2 -Info (144001): Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg -Info: Quartus II 64-Bit Fitter was successful. 0 errors, 827 warnings - Info: Peak virtual memory: 1016 megabytes - Info: Processing ended: Fri Dec 02 01:33:13 2016 - Info: Elapsed time: 00:00:31 - Info: Total CPU time (on all processors): 00:00:31 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg. - - +Fitter report for lights +Thu Dec 22 10:08:30 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Fitter Netlist Optimizations + 7. Ignored Assignments + 8. Incremental Compilation Preservation Summary + 9. Incremental Compilation Partition Settings + 10. Incremental Compilation Placement Preservation + 11. Pin-Out File + 12. Fitter Resource Usage Summary + 13. Fitter Partition Statistics + 14. Input Pins + 15. Output Pins + 16. Dual Purpose and Dedicated Pins + 17. I/O Bank Usage + 18. All Package Pins + 19. Fitter Resource Utilization by Entity + 20. Delay Chain Summary + 21. Pad To Core Delay Chain Fanout + 22. Control Signals + 23. Global & Other Fast Signals + 24. Non-Global High Fan-Out Signals + 25. Fitter RAM Summary + 26. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM + 27. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM + 28. |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM + 29. |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM + 30. Other Routing Usage Summary + 31. LAB Logic Elements + 32. LAB-wide Signals + 33. LAB Signals Sourced + 34. LAB Signals Sourced Out + 35. LAB Distinct Inputs + 36. I/O Rules Summary + 37. I/O Rules Details + 38. I/O Rules Matrix + 39. Fitter Device Options + 40. Operating Settings and Conditions + 41. Fitter Messages + 42. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Thu Dec 22 10:08:30 2016 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; lights ; +; Top-level Entity Name ; lights ; +; Family ; Cyclone IV E ; +; Device ; EP4CE115F29C7 ; +; Timing Models ; Final ; +; Total logic elements ; 2,234 / 114,480 ( 2 % ) ; +; Total combinational functions ; 2,060 / 114,480 ( 2 % ) ; +; Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; +; Total registers ; 1204 ; +; Total pins ; 118 / 529 ( 22 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE115F29C7 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++----------------------------------------------------+ +; I/O Assignment Warnings ; ++-------------+--------------------------------------+ +; Pin Name ; Reason ; ++-------------+--------------------------------------+ +; LEDG[0] ; Missing drive strength and slew rate ; +; LEDG[1] ; Missing drive strength and slew rate ; +; LEDG[2] ; Missing drive strength and slew rate ; +; LEDG[3] ; Missing drive strength and slew rate ; +; LEDG[4] ; Missing drive strength and slew rate ; +; LEDG[5] ; Missing drive strength and slew rate ; +; LEDG[6] ; Missing drive strength and slew rate ; +; LEDG[7] ; Missing drive strength and slew rate ; +; LEDR[0] ; Missing drive strength and slew rate ; +; LEDR[1] ; Missing drive strength and slew rate ; +; LEDR[2] ; Missing drive strength and slew rate ; +; LEDR[3] ; Missing drive strength and slew rate ; +; LEDR[4] ; Missing drive strength and slew rate ; +; LEDR[5] ; Missing drive strength and slew rate ; +; LEDR[6] ; Missing drive strength and slew rate ; +; LEDR[7] ; Missing drive strength and slew rate ; +; LEDR[8] ; Missing drive strength and slew rate ; +; LEDR[9] ; Missing drive strength and slew rate ; +; LEDR[10] ; Missing drive strength and slew rate ; +; LEDR[11] ; Missing drive strength and slew rate ; +; LEDR[12] ; Missing drive strength and slew rate ; +; LEDR[13] ; Missing drive strength and slew rate ; +; LEDR[14] ; Missing drive strength and slew rate ; +; LEDR[15] ; Missing drive strength and slew rate ; +; LEDR[16] ; Missing drive strength and slew rate ; +; LEDR[17] ; Missing drive strength and slew rate ; +; HEX0[0] ; Missing drive strength and slew rate ; +; HEX0[1] ; Missing drive strength and slew rate ; +; HEX0[2] ; Missing drive strength and slew rate ; +; HEX0[3] ; Missing drive strength and slew rate ; +; HEX0[4] ; Missing drive strength and slew rate ; +; HEX0[5] ; Missing drive strength and slew rate ; +; HEX0[6] ; Missing drive strength and slew rate ; +; HEX1[0] ; Missing drive strength and slew rate ; +; HEX1[1] ; Missing drive strength and slew rate ; +; HEX1[2] ; Missing drive strength and slew rate ; +; HEX1[3] ; Missing drive strength and slew rate ; +; HEX1[4] ; Missing drive strength and slew rate ; +; HEX1[5] ; Missing drive strength and slew rate ; +; HEX1[6] ; Missing drive strength and slew rate ; +; HEX2[0] ; Missing drive strength and slew rate ; +; HEX2[1] ; Missing drive strength and slew rate ; +; HEX2[2] ; Missing drive strength and slew rate ; +; HEX2[3] ; Missing drive strength and slew rate ; +; HEX2[4] ; Missing drive strength and slew rate ; +; HEX2[5] ; Missing drive strength and slew rate ; +; HEX2[6] ; Missing drive strength and slew rate ; +; HEX3[0] ; Missing drive strength and slew rate ; +; HEX3[1] ; Missing drive strength and slew rate ; +; HEX3[2] ; Missing drive strength ; +; HEX3[3] ; Missing drive strength ; +; HEX3[4] ; Missing drive strength ; +; HEX3[5] ; Missing drive strength ; +; HEX3[6] ; Missing drive strength ; +; HEX4[0] ; Missing drive strength ; +; HEX4[1] ; Missing drive strength ; +; HEX4[2] ; Missing drive strength ; +; HEX4[3] ; Missing drive strength ; +; HEX4[4] ; Missing drive strength ; +; HEX4[5] ; Missing drive strength ; +; HEX4[6] ; Missing drive strength ; +; HEX5[0] ; Missing drive strength ; +; HEX5[1] ; Missing drive strength ; +; HEX5[2] ; Missing drive strength ; +; HEX5[3] ; Missing drive strength ; +; HEX5[4] ; Missing drive strength ; +; HEX5[5] ; Missing drive strength ; +; HEX5[6] ; Missing drive strength ; +; HEX6[0] ; Missing drive strength ; +; HEX6[1] ; Missing drive strength ; +; HEX6[2] ; Missing drive strength ; +; HEX6[3] ; Missing drive strength ; +; HEX6[4] ; Missing drive strength ; +; HEX6[5] ; Missing drive strength ; +; HEX6[6] ; Missing drive strength ; +; HEX7[0] ; Missing drive strength ; +; HEX7[1] ; Missing drive strength ; +; HEX7[2] ; Missing drive strength ; +; HEX7[3] ; Missing drive strength ; +; HEX7[4] ; Missing drive strength ; +; HEX7[5] ; Missing drive strength ; +; HEX7[6] ; Missing drive strength ; +; LCD_RS ; Missing drive strength ; +; LCD_RW ; Missing drive strength ; +; LCD_data[0] ; Missing drive strength ; +; LCD_data[1] ; Missing drive strength ; +; LCD_data[2] ; Missing drive strength ; +; LCD_data[3] ; Missing drive strength ; +; LCD_data[4] ; Missing drive strength ; +; LCD_data[5] ; Missing drive strength ; +; LCD_data[6] ; Missing drive strength ; +; LCD_data[7] ; Missing drive strength ; +; LCD_EN ; Missing drive strength ; +; LCD_ON ; Missing drive strength ; +; LCD_BLON ; Missing drive strength ; ++-------------+--------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[0] ; PORTBDATAOUT ; ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[1] ; PORTBDATAOUT ; ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[2] ; PORTBDATAOUT ; ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[3] ; PORTBDATAOUT ; ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[4] ; PORTBDATAOUT ; ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[5] ; PORTBDATAOUT ; ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[6] ; PORTBDATAOUT ; ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[7] ; PORTBDATAOUT ; ; ++-----------------------------------------------------------------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++--------------+----------------+--------------+------------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++--------------+----------------+--------------+------------------+---------------+----------------+ +; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ; +; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ; +; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ; +; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ; +; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ; +; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ; +; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ; +; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ; +; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ; +; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ; +; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ; +; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ; +; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ; +; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ; +; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ; +; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ; +; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ; +; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ; +; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ; +; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ; +; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ; +; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ; +; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ; +; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ; +; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ; +; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ; +; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ; +; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ; +; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ; +; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ; +; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ; +; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ; +; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ; +; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ; +; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ; +; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ; +; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ; +; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ; +; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ; +; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ; +; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ; +; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ; +; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ; +; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ; +; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ; +; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ; +; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ; +; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ; +; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ; +; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ; +; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ; +; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ; +; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ; +; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ; +; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ; +; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ; +; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ; +; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ; +; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ; +; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ; +; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ; +; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ; +; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ; +; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ; +; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ; +; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ; +; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ; +; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ; +; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ; +; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ; +; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ; +; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ; +; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ; +; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ; +; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ; +; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ; +; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ; +; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ; +; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ; +; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ; +; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ; +; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ; +; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ; +; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ; +; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ; +; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ; +; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ; +; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ; +; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ; +; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ; +; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ; +; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ; +; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ; +; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ; +; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ; +; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ; +; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ; +; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ; +; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ; +; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ; +; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ; +; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ; +; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ; +; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ; +; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ; +; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ; +; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ; +; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ; +; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ; +; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ; +; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ; +; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ; +; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ; +; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ; +; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ; +; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ; +; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ; +; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ; +; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ; +; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ; +; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ; +; Location ; ; ; OTG_DACK_N[0] ; PIN_C4 ; QSF Assignment ; +; Location ; ; ; OTG_DACK_N[1] ; PIN_D4 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ; +; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ; +; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ; +; Location ; ; ; OTG_DREQ[1] ; PIN_B4 ; QSF Assignment ; +; Location ; ; ; OTG_FSPEED ; PIN_C6 ; QSF Assignment ; +; Location ; ; ; OTG_INT[0] ; PIN_A6 ; QSF Assignment ; +; Location ; ; ; OTG_INT[1] ; PIN_D5 ; QSF Assignment ; +; Location ; ; ; OTG_LSPEED ; PIN_B6 ; QSF Assignment ; +; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ; +; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ; +; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ; +; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ; +; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ; +; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ; +; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ; +; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ; +; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ; +; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ; +; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ; +; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ; +; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ; +; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ; +; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ; +; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ; +; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ; +; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ; +; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ; +; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ; +; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ; +; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ; +; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ; +; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ; +; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ; +; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ; +; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ; +; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ; +; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ; +; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ; +; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ; +; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ; +; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ; +; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ; +; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ; +; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ; +; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ; +; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ; +; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ; +; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ; +; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ; +; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ; +; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ; +; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ; +; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ; +; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ; +; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ; +; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ; +; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ; +; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ; +; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ; +; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ; +; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ; +; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ; +; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ; +; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ; +; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ; +; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ; +; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ; +; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ; +; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ; +; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ; +; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ; +; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ; +; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ; +; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ; +; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ; +; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ; +; I/O Standard ; ; ; AUD_ADCDAT ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; AUD_ADCLRCK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; AUD_BCLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; AUD_DACDAT ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; AUD_DACLRCK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; AUD_XCK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; CLOCK2_50 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; CLOCK3_50 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_BA[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_BA[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_CAS_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_CKE ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_CS_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQM[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQM[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQM[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQM[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[16] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[17] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[18] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[19] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[20] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[21] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[22] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[23] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[24] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[25] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[26] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[27] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[28] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[29] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[30] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[31] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_RAS_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; DRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EEP_I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EEP_I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_GTX_CLK ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_INT_N ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_LINK100 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_MDC ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_MDIO ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RST_N ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_CLK ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_COL ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_CRS ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_DATA[0] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_DATA[1] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_DATA[2] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_DATA[3] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_DV ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_RX_ER ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_TX_CLK ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_TX_DATA[0] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_TX_DATA[1] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_TX_DATA[2] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_TX_DATA[3] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_TX_EN ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET0_TX_ER ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_GTX_CLK ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_INT_N ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_LINK100 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_MDC ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_MDIO ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RST_N ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_CLK ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_COL ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_CRS ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_DATA[0] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_DATA[1] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_DATA[2] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_DATA[3] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_DV ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_RX_ER ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_TX_CLK ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_TX_DATA[0] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_TX_DATA[1] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_TX_DATA[2] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_TX_DATA[3] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_TX_EN ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENET1_TX_ER ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; ENETCLK_25 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EX_IO[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EX_IO[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EX_IO[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EX_IO[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EX_IO[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EX_IO[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; EX_IO[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[20] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[21] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[22] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_CE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_OE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_RST_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_RY ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_WE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; FL_WP_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[15] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[16] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[17] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[18] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[19] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[20] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[21] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[22] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[23] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[24] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[25] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[26] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[27] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[28] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[29] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[30] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[31] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[32] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[33] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[34] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[35] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; GPIO[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKIN0 ; 3.0-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKIN_N1 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKIN_N2 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKIN_P1 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKIN_P2 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKOUT0 ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKOUT_N1 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKOUT_N2 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKOUT_P1 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_CLKOUT_P2 ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_D[0] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_D[1] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_D[2] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_D[3] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[0] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[10] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[11] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[12] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[13] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[14] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[15] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[16] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[1] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[2] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[3] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[4] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[5] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[6] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[7] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[8] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_N[9] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[0] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[10] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[11] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[12] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[13] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[14] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[15] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[16] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[1] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[2] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[3] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[4] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[5] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[6] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[7] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[8] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_RX_D_P[9] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[0] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[10] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[11] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[12] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[13] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[14] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[15] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[16] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[1] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[2] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[3] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[4] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[5] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[6] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[7] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[8] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_N[9] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[0] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[10] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[11] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[12] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[13] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[14] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[15] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[16] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[1] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[2] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[3] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[4] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[5] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[6] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[7] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[8] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; HSMC_TX_D_P[9] ; LVDS ; QSF Assignment ; +; I/O Standard ; ; ; I2C_SCLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; I2C_SDAT ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; IRDA_RXD ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; LEDG[8] ; 2.5 V ; QSF Assignment ; +; I/O Standard ; ; ; OTG_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_CS_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DACK_N[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DACK_N[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[15] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DATA[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DREQ[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_DREQ[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_FSPEED ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_INT[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_INT[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_LSPEED ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_RD_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_RST_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; OTG_WR_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; PS2_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; PS2_CLK2 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; PS2_DAT ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; PS2_DAT2 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SD_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SD_CMD ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SD_DAT[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SD_DAT[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SD_DAT[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SD_DAT[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SD_WP_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SMA_CLKIN ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SMA_CLKOUT ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[15] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[16] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[17] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[18] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[19] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_ADDR[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_CE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[10] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[11] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[12] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[13] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[14] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[15] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[8] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_DQ[9] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_LB_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_OE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_UB_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; SRAM_WE_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_CLK27 ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_DATA[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_HS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_RESET_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; TD_VS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; UART_CTS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; UART_RTS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; UART_RXD ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; UART_TXD ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_BLANK_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_B[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_CLK ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_G[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_HS ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[0] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[1] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[2] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[3] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[4] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[5] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[6] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_R[7] ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_SYNC_N ; 3.3-V LVTTL ; QSF Assignment ; +; I/O Standard ; ; ; VGA_VS ; 3.3-V LVTTL ; QSF Assignment ; ++--------------+----------------+--------------+------------------+---------------+----------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 3864 ( 0.00 % ) ; +; -- Achieved ; 0 / 3864 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; sld_hub:auto_hub ; Auto-generated ; Post-Synthesis ; N/A ; Post-Synthesis ; N/A ; sld_hub:auto_hub ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 3599 ; 0 ; N/A ; Source File ; +; sld_hub:auto_hub ; 255 ; 0 ; N/A ; Post-Synthesis ; +; hard_block:auto_generated_inst ; 10 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.pin. + + ++------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+--------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+--------------------------------+ +; Total logic elements ; 2,234 / 114,480 ( 2 % ) ; +; -- Combinational with no register ; 1030 ; +; -- Register only ; 174 ; +; -- Combinational with a register ; 1030 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 1077 ; +; -- 3 input functions ; 678 ; +; -- <=2 input functions ; 305 ; +; -- Register only ; 174 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 1913 ; +; -- arithmetic mode ; 147 ; +; ; ; +; Total registers* ; 1,204 / 117,053 ( 1 % ) ; +; -- Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; +; -- I/O registers ; 0 / 2,573 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 160 / 7,155 ( 2 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 118 / 529 ( 22 % ) ; +; -- Clock pins ; 1 / 7 ( 14 % ) ; +; -- Dedicated input pins ; 3 / 9 ( 33 % ) ; +; ; ; +; Global signals ; 4 ; +; M9Ks ; 205 / 432 ( 47 % ) ; +; Total block memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; +; Total block memory implementation bits ; 1,889,280 / 3,981,312 ( 47 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 4 / 20 ( 20 % ) ; +; JTAGs ; 1 / 1 ( 100 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ; +; Peak interconnect usage (total/H/V) ; 20% / 19% / 22% ; +; Maximum fan-out ; 1229 ; +; Highest non-global fan-out ; 204 ; +; Total fan-out ; 15183 ; +; Average fan-out ; 3.96 ; ++---------------------------------------------+--------------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+-------------------------+------------------------+--------------------------------+ +; Statistic ; Top ; sld_hub:auto_hub ; hard_block:auto_generated_inst ; ++---------------------------------------------+-------------------------+------------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; Low ; +; ; ; ; ; +; Total logic elements ; 2062 / 114480 ( 2 % ) ; 172 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; +; -- Combinational with no register ; 955 ; 75 ; 0 ; +; -- Register only ; 160 ; 14 ; 0 ; +; -- Combinational with a register ; 947 ; 83 ; 0 ; +; ; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; ; +; -- 4 input functions ; 1007 ; 70 ; 0 ; +; -- 3 input functions ; 632 ; 46 ; 0 ; +; -- <=2 input functions ; 263 ; 42 ; 0 ; +; -- Register only ; 160 ; 14 ; 0 ; +; ; ; ; ; +; Logic elements by mode ; ; ; ; +; -- normal mode ; 1763 ; 150 ; 0 ; +; -- arithmetic mode ; 139 ; 8 ; 0 ; +; ; ; ; ; +; Total registers ; 1107 ; 97 ; 0 ; +; -- Dedicated logic registers ; 1107 / 114480 ( < 1 % ) ; 97 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; +; ; ; ; ; +; Total LABs: partially or completely used ; 147 / 7155 ( 2 % ) ; 15 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ; +; ; ; ; ; +; Virtual pins ; 0 ; 0 ; 0 ; +; I/O pins ; 118 ; 0 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ; +; Total memory bits ; 1649664 ; 0 ; 0 ; +; Total RAM block bits ; 1889280 ; 0 ; 0 ; +; JTAG ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; +; M9K ; 205 / 432 ( 47 % ) ; 0 / 432 ( 0 % ) ; 0 / 432 ( 0 % ) ; +; Clock control block ; 4 / 24 ( 16 % ) ; 0 / 24 ( 0 % ) ; 0 / 24 ( 0 % ) ; +; ; ; ; ; +; Connections ; ; ; ; +; -- Input Connections ; 268 ; 141 ; 0 ; +; -- Registered Input Connections ; 131 ; 106 ; 0 ; +; -- Output Connections ; 236 ; 173 ; 0 ; +; -- Registered Output Connections ; 4 ; 172 ; 0 ; +; ; ; ; ; +; Internal Connections ; ; ; ; +; -- Total Connections ; 14498 ; 1016 ; 5 ; +; -- Registered Connections ; 4720 ; 708 ; 0 ; +; ; ; ; ; +; External Connections ; ; ; ; +; -- Top ; 192 ; 312 ; 0 ; +; -- sld_hub:auto_hub ; 312 ; 2 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; 0 ; +; ; ; ; ; +; Partition Interface ; ; ; ; +; -- Input Ports ; 63 ; 23 ; 0 ; +; -- Output Ports ; 102 ; 40 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; 0 ; +; ; ; ; ; +; Registered Ports ; ; ; ; +; -- Registered Input Ports ; 0 ; 3 ; 0 ; +; -- Registered Output Ports ; 0 ; 29 ; 0 ; +; ; ; ; ; +; Port Connectivity ; ; ; ; +; -- Input Ports driven by GND ; 0 ; 9 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 1 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 1 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 2 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 26 ; 0 ; ++---------------------------------------------+-------------------------+------------------------+--------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; CLOCK_50 ; Y2 ; 2 ; 0 ; 36 ; 14 ; 1229 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; KEY[1] ; M21 ; 6 ; 115 ; 53 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; KEY[2] ; N21 ; 6 ; 115 ; 42 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; KEY[3] ; R24 ; 5 ; 115 ; 35 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[10] ; AC24 ; 5 ; 115 ; 4 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[11] ; AB24 ; 5 ; 115 ; 5 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[12] ; AB23 ; 5 ; 115 ; 7 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[13] ; AA24 ; 5 ; 115 ; 9 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[14] ; AA23 ; 5 ; 115 ; 10 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[15] ; AA22 ; 5 ; 115 ; 6 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[16] ; Y24 ; 5 ; 115 ; 13 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[17] ; Y23 ; 5 ; 115 ; 14 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[9] ; AB25 ; 5 ; 115 ; 16 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; HEX0[0] ; G18 ; 7 ; 69 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[1] ; F22 ; 7 ; 107 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[2] ; E17 ; 7 ; 67 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[3] ; L26 ; 6 ; 115 ; 50 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[4] ; L25 ; 6 ; 115 ; 54 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[5] ; J22 ; 6 ; 115 ; 67 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX0[6] ; H22 ; 6 ; 115 ; 69 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[0] ; M24 ; 6 ; 115 ; 41 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[1] ; Y22 ; 5 ; 115 ; 30 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[2] ; W21 ; 5 ; 115 ; 25 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[3] ; W22 ; 5 ; 115 ; 30 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[4] ; W25 ; 5 ; 115 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[5] ; U23 ; 5 ; 115 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX1[6] ; U24 ; 5 ; 115 ; 28 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[0] ; AA25 ; 5 ; 115 ; 17 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[1] ; AA26 ; 5 ; 115 ; 16 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[2] ; Y25 ; 5 ; 115 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[3] ; W26 ; 5 ; 115 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[4] ; Y26 ; 5 ; 115 ; 18 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[5] ; W27 ; 5 ; 115 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX2[6] ; W28 ; 5 ; 115 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[0] ; V21 ; 5 ; 115 ; 25 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[1] ; U21 ; 5 ; 115 ; 29 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; HEX3[2] ; AB20 ; 4 ; 100 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[3] ; AA21 ; 4 ; 111 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[4] ; AD24 ; 4 ; 105 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[5] ; AF23 ; 4 ; 105 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX3[6] ; Y19 ; 4 ; 105 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX4[0] ; AB19 ; 4 ; 98 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX4[1] ; AA19 ; 4 ; 107 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX4[2] ; AG21 ; 4 ; 74 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX4[3] ; AH21 ; 4 ; 74 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX4[4] ; AE19 ; 4 ; 83 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX4[5] ; AF19 ; 4 ; 83 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX4[6] ; AE18 ; 4 ; 79 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX5[0] ; AD18 ; 4 ; 85 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX5[1] ; AC18 ; 4 ; 87 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX5[2] ; AB18 ; 4 ; 98 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX5[3] ; AH19 ; 4 ; 72 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX5[4] ; AG19 ; 4 ; 72 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX5[5] ; AF18 ; 4 ; 79 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX5[6] ; AH18 ; 4 ; 69 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX6[0] ; AA17 ; 4 ; 89 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX6[1] ; AB16 ; 4 ; 65 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX6[2] ; AA16 ; 4 ; 65 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX6[3] ; AB17 ; 4 ; 89 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX6[4] ; AB15 ; 4 ; 67 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX6[5] ; AA15 ; 4 ; 67 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX6[6] ; AC17 ; 4 ; 74 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX7[0] ; AD17 ; 4 ; 74 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX7[1] ; AE17 ; 4 ; 67 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX7[2] ; AG17 ; 4 ; 62 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX7[3] ; AH17 ; 4 ; 62 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX7[4] ; AF17 ; 4 ; 67 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX7[5] ; AG18 ; 4 ; 69 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; HEX7[6] ; AA14 ; 3 ; 54 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_BLON ; L6 ; 1 ; 0 ; 47 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_EN ; L4 ; 1 ; 0 ; 52 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_ON ; L5 ; 1 ; 0 ; 58 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_RS ; M2 ; 1 ; 0 ; 44 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_RW ; M1 ; 1 ; 0 ; 44 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[0] ; L3 ; 1 ; 0 ; 52 ; 14 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[1] ; L1 ; 1 ; 0 ; 44 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[2] ; L2 ; 1 ; 0 ; 44 ; 0 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[3] ; K7 ; 1 ; 0 ; 49 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[4] ; K1 ; 1 ; 0 ; 54 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[5] ; K2 ; 1 ; 0 ; 55 ; 21 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[6] ; M3 ; 1 ; 0 ; 51 ; 14 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LCD_data[7] ; M5 ; 1 ; 0 ; 47 ; 0 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ; +; LEDG[0] ; E21 ; 7 ; 107 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDG[1] ; E22 ; 7 ; 111 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDG[2] ; E25 ; 7 ; 83 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDG[3] ; E24 ; 7 ; 85 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDG[4] ; H21 ; 7 ; 72 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDG[5] ; G20 ; 7 ; 74 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDG[6] ; G22 ; 7 ; 72 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDG[7] ; G21 ; 7 ; 74 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[10] ; J15 ; 7 ; 60 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[11] ; H16 ; 7 ; 65 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[12] ; J16 ; 7 ; 65 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[13] ; H17 ; 7 ; 67 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[14] ; F15 ; 7 ; 58 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[15] ; G15 ; 7 ; 65 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[16] ; G16 ; 7 ; 67 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[17] ; H15 ; 7 ; 60 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[7] ; H19 ; 7 ; 72 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[8] ; J17 ; 7 ; 69 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LEDR[9] ; G17 ; 7 ; 83 ; 73 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; P7 ; TDI ; - ; altera_reserved_tdi ; JTAG Pin ; +; P5 ; TCK ; - ; altera_reserved_tck ; JTAG Pin ; +; P8 ; TMS ; - ; altera_reserved_tms ; JTAG Pin ; +; P6 ; TDO ; - ; altera_reserved_tdo ; JTAG Pin ; +; R8 ; nCE ; - ; - ; Dedicated Programming Pin ; +; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 17 / 56 ( 30 % ) ; 3.3V ; -- ; +; 2 ; 1 / 63 ( 2 % ) ; 3.3V ; -- ; +; 3 ; 1 / 73 ( 1 % ) ; 3.3V ; -- ; +; 4 ; 32 / 71 ( 45 % ) ; 3.3V ; -- ; +; 5 ; 34 / 65 ( 52 % ) ; 2.5V ; -- ; +; 6 ; 9 / 58 ( 16 % ) ; 2.5V ; -- ; +; 7 ; 29 / 72 ( 40 % ) ; 2.5V ; -- ; +; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AA1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AA14 ; 191 ; 3 ; HEX7[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA15 ; 213 ; 4 ; HEX6[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA16 ; 211 ; 4 ; HEX6[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA17 ; 241 ; 4 ; HEX6[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA19 ; 264 ; 4 ; HEX4[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; AA21 ; 269 ; 4 ; HEX3[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA22 ; 275 ; 5 ; SW[15] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA23 ; 280 ; 5 ; SW[14] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA24 ; 279 ; 5 ; SW[13] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA25 ; 294 ; 5 ; HEX2[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA26 ; 293 ; 5 ; HEX2[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB15 ; 214 ; 4 ; HEX6[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB16 ; 212 ; 4 ; HEX6[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB17 ; 242 ; 4 ; HEX6[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB18 ; 254 ; 4 ; HEX5[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB19 ; 253 ; 4 ; HEX4[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB20 ; 257 ; 4 ; HEX3[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AB23 ; 276 ; 5 ; SW[12] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AB24 ; 274 ; 5 ; SW[11] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AB25 ; 292 ; 5 ; SW[9] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC17 ; 221 ; 4 ; HEX6[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC18 ; 240 ; 4 ; HEX5[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AC24 ; 273 ; 5 ; SW[10] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD17 ; 222 ; 4 ; HEX7[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD18 ; 237 ; 4 ; HEX5[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AD24 ; 260 ; 4 ; HEX3[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE17 ; 215 ; 4 ; HEX7[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE18 ; 225 ; 4 ; HEX4[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE19 ; 231 ; 4 ; HEX4[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF17 ; 216 ; 4 ; HEX7[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF18 ; 226 ; 4 ; HEX5[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF19 ; 232 ; 4 ; HEX4[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF23 ; 262 ; 4 ; HEX3[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG17 ; 207 ; 4 ; HEX7[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG18 ; 217 ; 4 ; HEX7[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG19 ; 219 ; 4 ; HEX5[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG21 ; 223 ; 4 ; HEX4[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AH2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AH16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH17 ; 208 ; 4 ; HEX7[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AH18 ; 218 ; 4 ; HEX5[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AH19 ; 220 ; 4 ; HEX5[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AH20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH21 ; 224 ; 4 ; HEX4[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH24 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; AH27 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E17 ; 456 ; 7 ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E21 ; 407 ; 7 ; LEDG[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E22 ; 403 ; 7 ; LEDG[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E24 ; 433 ; 7 ; LEDG[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E25 ; 434 ; 7 ; LEDG[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F15 ; 466 ; 7 ; LEDR[14] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F22 ; 409 ; 7 ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; G15 ; 457 ; 7 ; LEDR[15] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G16 ; 453 ; 7 ; LEDR[16] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G17 ; 437 ; 7 ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G18 ; 452 ; 7 ; HEX0[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G20 ; 444 ; 7 ; LEDG[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G21 ; 445 ; 7 ; LEDG[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G22 ; 449 ; 7 ; LEDG[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; H15 ; 464 ; 7 ; LEDR[17] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; H16 ; 459 ; 7 ; LEDR[11] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; H17 ; 454 ; 7 ; LEDR[13] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H19 ; 446 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; 448 ; 7 ; LEDG[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; H22 ; 399 ; 6 ; HEX0[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; J15 ; 465 ; 7 ; LEDR[10] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; J16 ; 458 ; 7 ; LEDR[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; J17 ; 450 ; 7 ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; J22 ; 394 ; 6 ; HEX0[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; K1 ; 28 ; 1 ; LCD_data[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K2 ; 27 ; 1 ; LCD_data[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K7 ; 38 ; 1 ; LCD_data[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 49 ; 1 ; LCD_data[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L2 ; 48 ; 1 ; LCD_data[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L3 ; 32 ; 1 ; LCD_data[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L4 ; 31 ; 1 ; LCD_EN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L5 ; 21 ; 1 ; LCD_ON ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L6 ; 43 ; 1 ; LCD_BLON ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L25 ; 369 ; 6 ; HEX0[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L26 ; 363 ; 6 ; HEX0[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 51 ; 1 ; LCD_RW ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M2 ; 50 ; 1 ; LCD_RS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M3 ; 34 ; 1 ; LCD_data[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; 41 ; 1 ; LCD_data[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M21 ; 368 ; 6 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M24 ; 347 ; 6 ; HEX1[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N21 ; 348 ; 6 ; KEY[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 59 ; 1 ; altera_reserved_tck ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; +; P6 ; 61 ; 1 ; altera_reserved_tdo ; output ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; +; P7 ; 58 ; 1 ; altera_reserved_tdi ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; +; P8 ; 60 ; 1 ; altera_reserved_tms ; input ; 3.3-V LVTTL ; ; -- ; N ; no ; Off ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R24 ; 330 ; 5 ; KEY[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U21 ; 319 ; 5 ; HEX3[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U23 ; 305 ; 5 ; HEX1[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U24 ; 316 ; 5 ; HEX1[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 311 ; 5 ; HEX3[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; W21 ; 310 ; 5 ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W22 ; 321 ; 5 ; HEX1[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W25 ; 300 ; 5 ; HEX1[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W26 ; 299 ; 5 ; HEX2[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W27 ; 301 ; 5 ; HEX2[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W28 ; 302 ; 5 ; HEX2[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; Y2 ; 65 ; 2 ; CLOCK_50 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; 263 ; 4 ; HEX3[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y22 ; 320 ; 5 ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y23 ; 288 ; 5 ; SW[17] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y24 ; 287 ; 5 ; SW[16] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y25 ; 298 ; 5 ; HEX2[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y26 ; 297 ; 5 ; HEX2[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +; |lights ; 2234 (1) ; 1204 (0) ; 0 (0) ; 1649664 ; 205 ; 0 ; 0 ; 0 ; 118 ; 0 ; 1030 (1) ; 174 (0) ; 1030 (0) ; |lights ; work ; +; |nios_system:NiosII| ; 2061 (0) ; 1107 (0) ; 0 (0) ; 1649664 ; 205 ; 0 ; 0 ; 0 ; 0 ; 0 ; 954 (0) ; 160 (0) ; 947 (0) ; |lights|nios_system:NiosII ; work ; +; |altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 10 (10) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 5 (5) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_translator:nios2_processor_data_master_translator| ; 9 (9) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_translator:nios2_processor_instruction_master_translator| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex0_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex1_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex2_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex3_s1_translator| ; 12 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex4_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex5_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex6_s1_translator| ; 12 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex7_s1_translator| ; 13 (13) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 10 (10) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator| ; 23 (23) ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 23 (23) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:lcd_16207_0_control_slave_translator| ; 22 (22) ; 15 (15) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 15 (15) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:lcd_blon_s1_translator| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:lcd_on_s1_translator| ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:ledrs_s1_translator| ; 24 (24) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 21 (21) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:leds_s1_translator| ; 13 (13) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 11 (11) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator| ; 33 (33) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 33 (33) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:onchip_memory_s1_translator| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:push_switches_s1_translator| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:switches_s1_translator| ; 24 (24) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 21 (21) ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_reset_controller:rst_controller| ; 10 (7) ; 9 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 7 (5) ; 3 (2) ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller ; altera_reserved_qsys_nios_system ; +; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 1 (1) ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reserved_qsys_nios_system ; +; |nios_system_LEDRs:ledrs| ; 38 (38) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 18 (18) ; 18 (18) ; |lights|nios_system:NiosII|nios_system_LEDRs:ledrs ; altera_reserved_qsys_nios_system ; +; |nios_system_LEDs:leds| ; 19 (19) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 8 (8) ; 8 (8) ; |lights|nios_system:NiosII|nios_system_LEDs:leds ; altera_reserved_qsys_nios_system ; +; |nios_system_addr_router:addr_router| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_addr_router:addr_router ; altera_reserved_qsys_nios_system ; +; |nios_system_addr_router_001:addr_router_001| ; 30 (30) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux:cmd_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_mux:cmd_xbar_mux_001| ; 61 (58) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (41) ; 1 (0) ; 18 (15) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 ; altera_reserved_qsys_nios_system ; +; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_mux:cmd_xbar_mux| ; 55 (52) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (3) ; 1 (0) ; 50 (47) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux ; altera_reserved_qsys_nios_system ; +; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex0| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex0 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex1| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex1 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex2| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex2 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex3| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex3 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex4| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex4 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex5| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex5 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex6| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex6 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex7| ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 7 (7) ; 7 (7) ; |lights|nios_system:NiosII|nios_system_hex0:hex7 ; altera_reserved_qsys_nios_system ; +; |nios_system_jtag_uart:jtag_uart| ; 157 (39) ; 104 (13) ; 0 (0) ; 1024 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (16) ; 17 (2) ; 97 (20) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart ; altera_reserved_qsys_nios_system ; +; |alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic| ; 68 (68) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 15 (15) ; 37 (37) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic ; work ; +; |nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r ; altera_reserved_qsys_nios_system ; +; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; work ; +; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; work ; +; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; +; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 8 (2) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; +; |nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w ; altera_reserved_qsys_nios_system ; +; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; work ; +; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; work ; +; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; +; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 8 (2) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; +; |nios_system_lcd_16207_0:lcd_16207_0| ; 12 (12) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 8 (8) ; |lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 ; altera_reserved_qsys_nios_system ; +; |nios_system_lcd_on:lcd_blon| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon ; altera_reserved_qsys_nios_system ; +; |nios_system_lcd_on:lcd_on| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_on ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor:nios2_processor| ; 1040 (658) ; 576 (306) ; 0 (0) ; 10240 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 440 (328) ; 51 (5) ; 549 (326) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci| ; 381 (81) ; 269 (80) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (1) ; 46 (1) ; 223 (79) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper| ; 139 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 43 (0) ; 43 (0) ; 53 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk| ; 50 (46) ; 49 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 39 (37) ; 10 (8) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk ; altera_reserved_qsys_nios_system ; +; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer4| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; work ; +; |nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck| ; 87 (83) ; 47 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 4 (0) ; 43 (43) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck ; altera_reserved_qsys_nios_system ; +; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; work ; +; |sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; work ; +; |nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg| ; 9 (9) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug| ; 11 (9) ; 9 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 10 (9) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug ; altera_reserved_qsys_nios_system ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; work ; +; |nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem| ; 112 (112) ; 49 (49) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (62) ; 1 (1) ; 49 (49) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; work ; +; |altsyncram_4891:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; work ; +; |nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; work ; +; |altsyncram_0rh1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; work ; +; |nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; work ; +; |altsyncram_1rh1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; work ; +; |nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench ; altera_reserved_qsys_nios_system ; +; |nios_system_onchip_memory:onchip_memory| ; 171 (1) ; 3 (0) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 168 (1) ; 0 (0) ; 3 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 170 (0) ; 3 (0) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 167 (0) ; 0 (0) ; 3 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; work ; +; |altsyncram_4ed1:auto_generated| ; 170 (3) ; 3 (3) ; 0 (0) ; 1638400 ; 200 ; 0 ; 0 ; 0 ; 0 ; 0 ; 167 (0) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; work ; +; |decode_qsa:decode3| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 ; work ; +; |mux_nob:mux2| ; 160 (160) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 160 (160) ; 0 (0) ; 0 (0) ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 ; work ; +; |nios_system_push_switches:push_switches| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |lights|nios_system:NiosII|nios_system_push_switches:push_switches ; altera_reserved_qsys_nios_system ; +; |nios_system_rsp_xbar_mux:rsp_xbar_mux| ; 11 (11) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux ; altera_reserved_qsys_nios_system ; +; |nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 113 (113) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 89 (89) ; 0 (0) ; 24 (24) ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_switches:switches| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 18 (18) ; |lights|nios_system:NiosII|nios_system_switches:switches ; altera_reserved_qsys_nios_system ; +; |sld_hub:auto_hub| ; 172 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 75 (1) ; 14 (0) ; 83 (0) ; |lights|sld_hub:auto_hub ; work ; +; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 171 (126) ; 97 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (57) ; 14 (14) ; 83 (58) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; work ; +; |sld_rom_sr:hub_info_reg| ; 25 (25) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 9 (9) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; work ; +; |sld_shadow_jsm:shadow_jsm| ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 19 (19) ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; work ; ++--------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++-------------+----------+---------------+---------------+-----------------------+-----+------+ +; LEDG[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDG[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[10] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[11] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[12] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[13] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[14] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[15] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[16] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LEDR[17] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX4[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX4[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX4[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX4[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX4[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX4[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX4[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX5[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX5[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX5[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX5[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX5[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX5[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX5[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX6[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX6[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX6[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX6[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX6[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX6[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX6[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX7[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX7[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX7[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX7[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX7[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX7[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; HEX7[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_RS ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_RW ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_data[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_EN ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_ON ; Output ; -- ; -- ; -- ; -- ; -- ; +; LCD_BLON ; Output ; -- ; -- ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; KEY[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; KEY[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; KEY[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[8] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[9] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[13] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SW[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[15] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[16] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[17] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; KEY[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; ++-------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------------------------+-------------------+---------+ +; CLOCK_50 ; ; ; +; SW[0] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[0] ; 0 ; 6 ; +; KEY[1] ; ; ; +; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[0] ; 0 ; 6 ; +; SW[1] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[1] ; 0 ; 6 ; +; KEY[2] ; ; ; +; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[1] ; 0 ; 6 ; +; SW[2] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[2] ; 0 ; 6 ; +; KEY[3] ; ; ; +; - nios_system:NiosII|nios_system_push_switches:push_switches|read_mux_out[2] ; 0 ; 6 ; +; SW[3] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[3] ; 1 ; 6 ; +; SW[4] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[4] ; 1 ; 6 ; +; SW[5] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[5] ; 1 ; 6 ; +; SW[6] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[6] ; 0 ; 6 ; +; SW[7] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[7] ; 0 ; 6 ; +; SW[8] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[8] ; 0 ; 6 ; +; SW[9] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[9] ; 1 ; 6 ; +; SW[10] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[10] ; 0 ; 6 ; +; SW[11] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[11] ; 0 ; 6 ; +; SW[12] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[12] ; 0 ; 6 ; +; SW[13] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[13] ; 1 ; 6 ; +; SW[14] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[14] ; 0 ; 6 ; +; SW[15] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[15] ; 0 ; 6 ; +; SW[16] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[16] ; 0 ; 6 ; +; SW[17] ; ; ; +; - nios_system:NiosII|nios_system_switches:switches|read_mux_out[17] ; 0 ; 6 ; +; KEY[0] ; ; ; +; - nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; 1 ; 6 ; ++-----------------------------------------------------------------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_Y2 ; 1227 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; +; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y37_N0 ; 183 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; altera_internal_jtag~TMSUTAP ; JTAG_X1_Y37_N0 ; 21 ; Sync. clear ; no ; -- ; -- ; -- ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; LCCOMB_X58_Y39_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; LCCOMB_X59_Y35_N4 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~23 ; LCCOMB_X60_Y35_N6 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ; +; nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X55_Y38_N0 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK14 ; -- ; +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; FF_X57_Y48_N9 ; 791 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ; +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; FF_X57_Y48_N5 ; 204 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~1 ; LCCOMB_X59_Y28_N10 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_LEDs:leds|always0~2 ; LCCOMB_X62_Y33_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X59_Y39_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~1 ; LCCOMB_X59_Y39_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~2 ; LCCOMB_X58_Y36_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|update_grant~1 ; LCCOMB_X58_Y36_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex0|always0~1 ; LCCOMB_X63_Y33_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex1|always0~1 ; LCCOMB_X60_Y28_N8 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex2|always0~1 ; LCCOMB_X63_Y28_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex3|always0~1 ; LCCOMB_X63_Y29_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex4|always0~1 ; LCCOMB_X60_Y29_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex5|always0~1 ; LCCOMB_X61_Y29_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex6|always0~1 ; LCCOMB_X60_Y29_N12 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_hex0:hex7|always0~1 ; LCCOMB_X61_Y28_N0 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|r_ena~0 ; LCCOMB_X67_Y36_N28 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0]~4 ; LCCOMB_X63_Y36_N28 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1]~0 ; LCCOMB_X65_Y36_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled~1 ; LCCOMB_X63_Y36_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~2 ; LCCOMB_X61_Y34_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_wr ; FF_X65_Y34_N27 ; 15 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF~2 ; LCCOMB_X61_Y33_N2 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; LCCOMB_X61_Y34_N14 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; LCCOMB_X63_Y34_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val~0 ; LCCOMB_X67_Y36_N0 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|read_0 ; FF_X61_Y34_N31 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|wr_rfifo ; LCCOMB_X62_Y34_N28 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[4] ; FF_X57_Y35_N3 ; 41 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_result~26 ; LCCOMB_X55_Y29_N0 ; 49 ; Sync. clear ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_new_inst ; FF_X53_Y30_N15 ; 42 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_valid ; FF_X53_Y33_N13 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_sel_nxt.10~0 ; LCCOMB_X57_Y32_N2 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_valid~0 ; LCCOMB_X59_Y35_N26 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_hi_imm16 ; FF_X53_Y29_N11 ; 17 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot ; FF_X55_Y30_N11 ; 22 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~31 ; LCCOMB_X55_Y34_N18 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_hi~0 ; LCCOMB_X53_Y30_N20 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[2] ; FF_X57_Y33_N11 ; 131 ; Output enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren ; LCCOMB_X57_Y38_N20 ; 2 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie_inst_nxt~2 ; LCCOMB_X57_Y32_N16 ; 15 ; Sync. clear ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_valid ; FF_X53_Y33_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4]~0 ; LCCOMB_X57_Y30_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data_en~0 ; LCCOMB_X57_Y31_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~1 ; LCCOMB_X57_Y30_N26 ; 30 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[8] ; FF_X56_Y36_N9 ; 36 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jxuir ; FF_X65_Y37_N23 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a ; LCCOMB_X58_Y38_N18 ; 15 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; LCCOMB_X61_Y38_N8 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_b ; LCCOMB_X59_Y38_N18 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_no_action_break_a~0 ; LCCOMB_X61_Y38_N18 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|update_jdo_strobe ; FF_X58_Y38_N29 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2]~13 ; LCCOMB_X63_Y36_N8 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34]~21 ; LCCOMB_X62_Y36_N4 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36]~29 ; LCCOMB_X62_Y36_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_sdr~0 ; LCCOMB_X65_Y37_N18 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_uir~0 ; LCCOMB_X65_Y37_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; LCCOMB_X56_Y38_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0]~9 ; LCCOMB_X58_Y38_N8 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_wr_en ; LCCOMB_X57_Y38_N30 ; 2 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1849w[3] ; LCCOMB_X58_Y32_N28 ; 32 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1866w[3] ; LCCOMB_X58_Y32_N16 ; 32 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1876w[3] ; LCCOMB_X58_Y32_N10 ; 32 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1886w[3] ; LCCOMB_X58_Y32_N14 ; 32 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1896w[3] ; LCCOMB_X58_Y32_N20 ; 32 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1906w[3] ; LCCOMB_X58_Y32_N24 ; 32 ; Write enable ; no ; -- ; -- ; -- ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1916w[3] ; LCCOMB_X58_Y32_N26 ; 8 ; Write enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X68_Y37_N15 ; 71 ; Async. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; LCCOMB_X69_Y35_N0 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; LCCOMB_X69_Y35_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; LCCOMB_X70_Y34_N4 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; LCCOMB_X66_Y34_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; LCCOMB_X66_Y34_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~4 ; LCCOMB_X67_Y34_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~11 ; LCCOMB_X67_Y34_N16 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~4 ; LCCOMB_X66_Y34_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~10 ; LCCOMB_X69_Y35_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; LCCOMB_X69_Y35_N28 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; LCCOMB_X68_Y36_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; LCCOMB_X68_Y36_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; LCCOMB_X68_Y34_N28 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; LCCOMB_X65_Y37_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; LCCOMB_X66_Y37_N28 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; LCCOMB_X66_Y37_N30 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X68_Y37_N25 ; 15 ; Async. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X65_Y35_N9 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X68_Y37_N5 ; 40 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; FF_X68_Y37_N27 ; 46 ; Sync. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; FF_X68_Y37_N19 ; 14 ; Async. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; LCCOMB_X65_Y35_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; FF_X66_Y35_N1 ; 32 ; Async. clear ; no ; -- ; -- ; -- ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++--------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_Y2 ; 1227 ; 0 ; Global Clock ; GCLK4 ; -- ; +; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y37_N0 ; 183 ; 0 ; Global Clock ; GCLK2 ; -- ; +; nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X55_Y38_N0 ; 3 ; 0 ; Global Clock ; GCLK14 ; -- ; +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; FF_X57_Y48_N9 ; 791 ; 0 ; Global Clock ; GCLK11 ; -- ; ++--------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; 204 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[48] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[47] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[46] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[45] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[44] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[43] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[42] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[41] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[40] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[39] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[38] ; 200 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[50] ; 192 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[49] ; 192 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[2] ; 131 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[1] ; 112 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[0] ; 112 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[3] ; 111 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; 71 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_no_action_break_a~0 ; 64 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; 58 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; 51 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[35] ; 50 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[34] ; 50 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[33] ; 50 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[32] ; 50 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_result~26 ; 49 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; 46 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_access ; 46 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; 42 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_new_inst ; 42 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[4] ; 41 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; 40 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|update_jdo_strobe ; 39 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_sdr~0 ; 39 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|read_latency_shift_reg[0] ; 38 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[8] ; 36 ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; 35 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_ld ; 35 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_valid~0 ; 34 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_b ; 33 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_aligning_data ; 33 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001|src0_valid ; 33 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_logic_op[0] ; 33 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; 32 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1896w[3] ; 32 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1906w[3] ; 32 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1886w[3] ; 32 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1849w[3] ; 32 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1876w[3] ; 32 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1866w[3] ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0]~9 ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_rd_d1 ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[36] ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[37] ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15]~0 ; 32 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|address_reg_a[2] ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot_right ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~31 ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_use_imm ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_logic_op[1] ; 32 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|readdata~0 ; 31 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~1 ; 30 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux|src1_valid ; 30 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~24 ; 29 ; +; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|uav_write~0 ; 29 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[6] ; 29 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[5] ; 28 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001|src1_valid ; 27 ; +; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|read_latency_shift_reg[0] ; 27 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; 26 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench|d_write ; 26 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; 25 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_valid ; 25 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[14] ; 24 ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|write~0 ; 24 ; +; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|write_accepted ; 24 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; 23 ; +; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|read_latency_shift_reg[0] ; 23 ; +; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|read_latency_shift_reg[0] ; 23 ; +; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; 23 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[2] ; 22 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_shift_rot ; 22 ; +; altera_internal_jtag~TMSUTAP ; 21 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0]~4 ; 21 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15] ; 21 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[12] ; 21 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[3] ; 21 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_logic ; 21 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_alu_sub ; 21 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28]~19 ; 20 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_valid ; 20 ; +; altera_internal_jtag~TDIUTAP ; 19 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28]~20 ; 19 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[21] ; 19 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[16] ; 19 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[1] ; 19 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[4] ; 19 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34]~21 ; 18 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; 18 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[0] ; 18 ; +; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~1 ; 18 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[0] ; 18 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src1~30 ; 17 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_hi_imm16 ; 17 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_br_cmp ; 17 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_read ; 17 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_wr ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr~19 ; 16 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|read_0 ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_fill_bit~1 ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_sel_nxt.10~0 ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_jmp_direct ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_lo~0 ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[5] ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_rdctl_inst ; 16 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[1] ; 16 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|take_action_ocimem_a ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie_inst_nxt~2 ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_src2_hi~0 ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[11] ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[6] ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[5] ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[4] ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[3] ; 15 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[2] ; 15 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; 14 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; 14 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; 14 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|wr_rfifo ; 14 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[13] ; 14 ; +; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|read_accepted ; 14 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~2 ; 14 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; 13 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2]~13 ; 13 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~5 ; 13 ; +; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|read_latency_shift_reg[0] ; 13 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|read_latency_shift_reg[0] ; 13 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; 12 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|read_latency_shift_reg[0] ; 12 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal8~0 ; 12 ; +; nios_system:NiosII|nios_system_LEDs:leds|always0~1 ; 12 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val~0 ; 11 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; 11 ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 11 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; 10 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal133~0 ; 10 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|waitrequest ; 10 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; 9 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; 9 ; +; ~GND ; 9 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_fill_bit~0 ; 9 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_ld_signed ; 9 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; 9 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; 9 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[6] ; 9 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[8] ; 9 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[7] ; 9 ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 9 ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 9 ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; 9 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal9~0 ; 9 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; 8 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1]~0 ; 8 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~2 ; 8 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 8 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3|w_anode1916w[3] ; 8 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[52] ; 8 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[53] ; 8 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_data[51] ; 8 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data_en~0 ; 8 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4]~0 ; 8 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_rshift8~0 ; 8 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_retaddr~0 ; 8 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal16~1 ; 8 ; +; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|read_latency_shift_reg[0] ; 8 ; +; nios_system:NiosII|nios_system_LEDs:leds|always0~2 ; 8 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[8] ; 8 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[7] ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~31 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~30 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~29 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~28 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~27 ; 7 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~26 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~25 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~24 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~23 ; 7 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~22 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~21 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~20 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~19 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~18 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~17 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~16 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~15 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~14 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~13 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~12 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~11 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~10 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~9 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~8 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~7 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~6 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~5 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~4 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~3 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~2 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~1 ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|src_payload~0 ; 7 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|wren~0 ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[35] ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_break ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_exception ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|write ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|i_read ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_cdr ; 7 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[0] ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex7|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex6|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex5|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~4 ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex4|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex3|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex2|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex1|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_hex0:hex0|always0~1 ; 7 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[7] ; 7 ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~1 ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; 6 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; 6 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; 6 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|t_ena~reg0 ; 6 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 6 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[0] ; 6 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|Equal0~0 ; 6 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[2] ; 6 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[3] ; 6 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[4] ; 6 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_b_is_dst~1 ; 6 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_valid ; 6 ; +; nios_system:NiosII|nios_system_lcd_on:lcd_blon|always0~0 ; 6 ; +; nios_system:NiosII|nios_system_lcd_on:lcd_on|always0~0 ; 6 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|read_latency_shift_reg[0] ; 6 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|read_latency_shift_reg[0] ; 6 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0]~23 ; 6 ; +; nios_system:NiosII|nios_system_hex0:hex6|always0~0 ; 6 ; +; nios_system:NiosII|nios_system_hex0:hex5|always0~0 ; 6 ; +; nios_system:NiosII|nios_system_hex0:hex3|always0~0 ; 6 ; +; nios_system:NiosII|nios_system_LEDRs:ledrs|always0~0 ; 6 ; +; nios_system:NiosII|nios_system_LEDs:leds|always0~0 ; 6 ; +; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|uav_read~0 ; 6 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[4] ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~10 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~4 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]~1 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~11 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~4 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_proc~0 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal11~0 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled~1 ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~1 ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~0 ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_result[1]~5 ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_result[0]~4 ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3]~0 ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate~0 ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift~6 ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[34] ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[17] ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~5 ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_status_reg_pie ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_req~0 ; 5 ; +; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|cp_valid ; 5 ; +; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator|read_accepted ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0]~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1]~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1]~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1]~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|nios_system_hex0:hex7|always0~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|nios_system_hex0:hex4|always0~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|nios_system_hex0:hex2|always0~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|nios_system_hex0:hex1|always0~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|nios_system_hex0:hex0|always0~0 ; 5 ; +; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[0] ; 5 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~1 ; 5 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; 5 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[5] ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]~5 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; 4 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|fifo_rd~3 ; 4 ; +; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|m0_write~2 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|Equal0~2 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[30] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[20] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[21] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[22] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[23] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[24] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[25] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[26] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[27] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[28] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[29] ; 4 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; 4 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[19] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_align_cycle[0] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_getting_data~13 ; 4 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux|src0_valid ; 4 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; 4 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|virtual_state_uir~0 ; 4 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|update_grant~1 ; 4 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~1 ; 4 ; +; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|local_read~1 ; 4 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux|src0_valid~0 ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|WideOr1 ; 4 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001|src1_valid~0 ; 4 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux|src1_valid~0 ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0]~0 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[17] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[18] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[19] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[20] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_shift_logical~0 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_br_nxt~0 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~4 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~3 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~0 ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0]~0 ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1]~0 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|Mux37~0 ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal0~2 ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[0] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|m0_write~0 ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[4] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_waitrequest_generated~2 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[0] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[1] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[1] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[2] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[3] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal4~2 ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal1~3 ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[10] ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal2~2 ; 4 ; +; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[0] ; 4 ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonARegAddrInc[8]~16 ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[1] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[2] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[3] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[4] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[5] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[6] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[7] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|q_b[0] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[6] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[7] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[8] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[9] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[10] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[11] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[12] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[13] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[14] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[15] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[16] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[17] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[18] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[4] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[2] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[3] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[13] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[14] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[9] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[10] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[11] ; 4 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[12] ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~5 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~10 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~3 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~0 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_logic~9 ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF~2 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[24] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[22] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[23] ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write1 ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift~11 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_error ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest~1 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[18] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[19] ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst2 ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|r_ena1 ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|r_val ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[25] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_ocireg~0 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[26] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[27] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[28] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[29] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[30] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[31] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_wrctl_inst ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_single_step_mode ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[20] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[21] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[5] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_bstatus_reg ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_estatus_reg ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[31] ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid0 ; 3 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|t_dav ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|ir[0] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|ir[1] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|enable_action_strobe ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_align_cycle[1] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_implicit_dst_retaddr~0 ; 3 ; +; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|av_readdatavalid~0 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|read ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1]~0 ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1]~0 ; 3 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|WideOr1 ; 3 ; +; nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001|src0_valid~0 ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~0 ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|nios_system_addr_router:addr_router|Equal0~1 ; 3 ; +; nios_system:NiosII|nios_system_addr_router:addr_router|Equal0~0 ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[3] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[9] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[22] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[10] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_force_src2_zero ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[9] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal2~2 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~0 ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1]~0 ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0]~0 ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1]~0 ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1]~0 ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1]~0 ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 3 ; +; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|av_waitrequest~2 ; 3 ; +; nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator|write_accepted~0 ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[1] ; 3 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal7~0 ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_getting_data~12 ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[5] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[6] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[7] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[8] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[9] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[10] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[11] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[12] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[13] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[14] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[15] ; 3 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal3~0 ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[17] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[16] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[15] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[14] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[13] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[12] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[11] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[9] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[8] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1] ; 3 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; 3 ; +; nios_system:NiosII|nios_system_lcd_on:lcd_blon|data_out ; 3 ; +; nios_system:NiosII|nios_system_lcd_on:lcd_on|data_out ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[24] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[25] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[26] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[27] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[28] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[23] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[29] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[22] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[30] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[21] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[31] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[30] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[19] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[20] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[21] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[22] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[23] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[24] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[25] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[26] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[27] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[28] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[29] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[20] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[0] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte1_data[7] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|jtag_break ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[19] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[4] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[5] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[6] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[7] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[8] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[10] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[11] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[12] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[13] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[14] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[15] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[2] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[1] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[0] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[1] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[6] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[5] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[8] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[7] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[13] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[14] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[9] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[10] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[11] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[12] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[15] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[16] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[17] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[18] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[16] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[17] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[18] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[4] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[2] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[3] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[1] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[3] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[2] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[15] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[16] ; 3 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[17] ; 3 ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[5] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~10 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg_proc~0 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~0 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~1 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal0~0 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~2 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~1 ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_wr_dst_reg~4 ; 2 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~2 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|read_latency_shift_reg~3 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|read_latency_shift_reg~3 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|read_latency_shift_reg~3 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|read_latency_shift_reg~3 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|read_latency_shift_reg~3 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|read_latency_shift_reg~3 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|read_latency_shift_reg~3 ; 2 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|Equal4~3 ; 2 ; +; nios_system:NiosII|nios_system_addr_router_001:addr_router_001|src_channel[1]~9 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[13] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[9] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[11] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[10] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[12] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[8] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[15] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[14] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[7] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[23] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[24] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[6] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[25] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[26] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[27] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[28] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[30] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[31] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|resetlatch ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[16] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[17] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[21] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[22] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[10] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[6] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[7] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[15] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[14] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[13] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[11] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|always2~0 ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate1 ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write2 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[19] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[20] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[30]~34 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[20]~33 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[21]~32 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[22]~31 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[23]~30 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[24]~29 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[25]~28 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[26]~27 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[27]~26 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[28]~25 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[29]~24 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[31]~23 ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36]~29 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[1] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[5] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[3] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[16] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[19]~22 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_go ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[7] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|rvalid ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[6] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|woverflow ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[5] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[4] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[3] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ac ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[5] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|t_pause~reg0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[3] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[3] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[23] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read1 ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid0~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|always1~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|avalon_ram_wr~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_rd ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_rd ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[7]~7 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[7] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[6]~6 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[6] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[5]~5 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[5] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[4]~4 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[4] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[3]~3 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[3] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[2]~2 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[2] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[1]~1 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|address[1] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_addr[0]~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|writedata[0] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|ociram_wr_en ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|debugaccess ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|jtag_ram_wr ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[4] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[2] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jxuir ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[32] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[33] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[18] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[19] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[20] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[21] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[2] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[22] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_fill_bit~0 ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[31]~95 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[31] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[30]~92 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[30] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[29]~89 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[29] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[28]~86 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[28] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[27]~83 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[27] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[2] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[1] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[1] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte3_data[0] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[5] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_readdata[8]~0 ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|pause_irq ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AF ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_readdata[9] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|ien_AE ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_crst ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg_nxt~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|break_on_reset ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[0] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_wrctl_status~0 ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[26]~80 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[26] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[25]~77 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[25] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[24]~74 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[24] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[23]~71 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[23] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_wrctl_bstatus~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_src1[31] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_arith_src2[31] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_invert_arith_src_msb ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[30]~32 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[1]~31 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[19]~30 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[20]~29 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[21]~28 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[22]~27 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[23]~26 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[24]~25 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[25]~24 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[26]~23 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[27]~22 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[28]~21 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[29]~20 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[31]~19 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[31] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[0]~18 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_compare_op[1] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_compare_op[0] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[2]~6 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[4]~5 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3]~4 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[1]~3 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[0]~1 ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state~1 ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|jdo[3] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[5] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[6] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[7] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[8] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[9] ; 2 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; 2 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|grant[0]~1 ; 2 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|grant[0]~1 ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[17]~68 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[17] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[18]~65 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[18] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[19]~62 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[19] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[20]~59 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[20] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[21]~56 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[21] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[18]~21 ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[22]~53 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[22] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[10]~50 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[10] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[6]~47 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[6] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[8]~44 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[8] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~3 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~2 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc_no_crst_nxt[16]~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_jmp_direct~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_stall~5 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_aligning_data_nxt~1 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_waiting_for_data_nxt~0 ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[7]~41 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[7] ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_force_src2_zero~3 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_exception~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_ctrl_break~0 ; 2 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|Equal101~4 ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[9]~38 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[9] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[15]~35 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[15] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[16]~32 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[16] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[14]~29 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[14] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[5]~26 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[5] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[12]~23 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[12] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[13]~20 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[13] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[11]~17 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[11] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[2]~14 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[2] ; 2 ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2|result_node[0]~11 ; 2 ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|av_readdata_pre[0] ; 2 ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; no ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X64_Y32_N0 ; Don't care ; Old data ; Old data ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X64_Y34_N0 ; Don't care ; Old data ; Old data ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 256 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 8192 ; 256 ; 32 ; -- ; -- ; 8192 ; 1 ; nios_system_nios2_processor_ociram_default_contents.mif ; M9K_X51_Y37_N0 ; Don't care ; Old data ; Old data ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; nios_system_nios2_processor_rf_ram_a.mif ; M9K_X51_Y33_N0 ; Don't care ; Old data ; Old data ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; nios_system_nios2_processor_rf_ram_b.mif ; M9K_X51_Y34_N0 ; Don't care ; Old data ; Old data ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 51200 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1638400 ; 51200 ; 32 ; -- ; -- ; 1638400 ; 200 ; nios_system_onchip_memory.hex ; M9K_X37_Y40_N0, M9K_X37_Y37_N0, M9K_X37_Y33_N0, M9K_X15_Y40_N0, M9K_X51_Y41_N0, M9K_X37_Y41_N0, M9K_X37_Y48_N0, M9K_X37_Y52_N0, M9K_X37_Y36_N0, M9K_X37_Y44_N0, M9K_X37_Y42_N0, M9K_X37_Y45_N0, M9K_X51_Y16_N0, M9K_X51_Y15_N0, M9K_X51_Y31_N0, M9K_X37_Y23_N0, M9K_X51_Y28_N0, M9K_X51_Y35_N0, M9K_X15_Y28_N0, M9K_X78_Y25_N0, M9K_X51_Y22_N0, M9K_X37_Y28_N0, M9K_X78_Y21_N0, M9K_X51_Y32_N0, M9K_X64_Y20_N0, M9K_X15_Y30_N0, M9K_X37_Y20_N0, M9K_X37_Y22_N0, M9K_X15_Y24_N0, M9K_X37_Y21_N0, M9K_X51_Y36_N0, M9K_X37_Y25_N0, M9K_X51_Y18_N0, M9K_X37_Y18_N0, M9K_X78_Y24_N0, M9K_X37_Y24_N0, M9K_X78_Y18_N0, M9K_X51_Y27_N0, M9K_X37_Y19_N0, M9K_X51_Y12_N0, M9K_X51_Y14_N0, M9K_X78_Y23_N0, M9K_X78_Y26_N0, M9K_X78_Y16_N0, M9K_X78_Y19_N0, M9K_X64_Y14_N0, M9K_X64_Y19_N0, M9K_X64_Y25_N0, M9K_X51_Y29_N0, M9K_X37_Y31_N0, M9K_X64_Y21_N0, M9K_X78_Y15_N0, M9K_X64_Y15_N0, M9K_X78_Y22_N0, M9K_X51_Y24_N0, M9K_X78_Y17_N0, M9K_X64_Y16_N0, M9K_X64_Y52_N0, M9K_X51_Y21_N0, M9K_X37_Y29_N0, M9K_X51_Y52_N0, M9K_X51_Y17_N0, M9K_X64_Y17_N0, M9K_X51_Y26_N0, M9K_X51_Y30_N0, M9K_X37_Y27_N0, M9K_X37_Y30_N0, M9K_X51_Y25_N0, M9K_X51_Y40_N0, M9K_X51_Y23_N0, M9K_X51_Y20_N0, M9K_X51_Y13_N0, M9K_X64_Y24_N0, M9K_X37_Y26_N0, M9K_X64_Y28_N0, M9K_X51_Y19_N0, M9K_X37_Y58_N0, M9K_X51_Y59_N0, M9K_X51_Y46_N0, M9K_X37_Y59_N0, M9K_X37_Y46_N0, M9K_X78_Y50_N0, M9K_X78_Y20_N0, M9K_X64_Y18_N0, M9K_X51_Y42_N0, M9K_X51_Y43_N0, M9K_X51_Y38_N0, M9K_X64_Y22_N0, M9K_X51_Y63_N0, M9K_X51_Y61_N0, M9K_X51_Y57_N0, M9K_X51_Y60_N0, M9K_X51_Y45_N0, M9K_X51_Y39_N0, M9K_X78_Y63_N0, M9K_X15_Y49_N0, M9K_X51_Y48_N0, M9K_X37_Y47_N0, M9K_X37_Y51_N0, M9K_X37_Y50_N0, M9K_X51_Y50_N0, M9K_X64_Y47_N0, M9K_X78_Y45_N0, M9K_X78_Y52_N0, M9K_X37_Y53_N0, M9K_X78_Y48_N0, M9K_X51_Y54_N0, M9K_X64_Y51_N0, M9K_X64_Y55_N0, M9K_X64_Y56_N0, M9K_X64_Y49_N0, M9K_X64_Y50_N0, M9K_X64_Y54_N0, M9K_X51_Y47_N0, M9K_X78_Y31_N0, M9K_X51_Y53_N0, M9K_X78_Y54_N0, M9K_X64_Y44_N0, M9K_X78_Y32_N0, M9K_X37_Y49_N0, M9K_X51_Y64_N0, M9K_X37_Y56_N0, M9K_X37_Y60_N0, M9K_X37_Y38_N0, M9K_X37_Y61_N0, M9K_X64_Y43_N0, M9K_X78_Y61_N0, M9K_X78_Y41_N0, M9K_X78_Y59_N0, M9K_X78_Y44_N0, M9K_X78_Y39_N0, M9K_X64_Y42_N0, M9K_X78_Y42_N0, M9K_X64_Y36_N0, M9K_X64_Y53_N0, M9K_X78_Y43_N0, M9K_X64_Y57_N0, M9K_X64_Y64_N0, M9K_X64_Y62_N0, M9K_X37_Y57_N0, M9K_X51_Y44_N0, M9K_X37_Y43_N0, M9K_X64_Y39_N0, M9K_X51_Y58_N0, M9K_X37_Y39_N0, M9K_X64_Y26_N0, M9K_X37_Y32_N0, M9K_X37_Y34_N0, M9K_X37_Y35_N0, M9K_X64_Y23_N0, M9K_X51_Y55_N0, M9K_X51_Y56_N0, M9K_X78_Y49_N0, M9K_X37_Y55_N0, M9K_X104_Y38_N0, M9K_X64_Y38_N0, M9K_X78_Y46_N0, M9K_X64_Y48_N0, M9K_X64_Y37_N0, M9K_X64_Y33_N0, M9K_X78_Y29_N0, M9K_X78_Y28_N0, M9K_X64_Y41_N0, M9K_X64_Y60_N0, M9K_X64_Y63_N0, M9K_X78_Y56_N0, M9K_X78_Y37_N0, M9K_X78_Y40_N0, M9K_X64_Y61_N0, M9K_X78_Y38_N0, M9K_X64_Y35_N0, M9K_X64_Y30_N0, M9K_X78_Y33_N0, M9K_X64_Y31_N0, M9K_X78_Y34_N0, M9K_X78_Y36_N0, M9K_X104_Y41_N0, M9K_X78_Y53_N0, M9K_X78_Y55_N0, M9K_X78_Y35_N0, M9K_X64_Y40_N0, M9K_X78_Y57_N0, M9K_X104_Y39_N0, M9K_X64_Y29_N0, M9K_X64_Y27_N0, M9K_X78_Y30_N0, M9K_X78_Y27_N0, M9K_X104_Y32_N0, M9K_X64_Y58_N0, M9K_X64_Y59_N0, M9K_X64_Y45_N0, M9K_X64_Y46_N0, M9K_X51_Y49_N0, M9K_X37_Y54_N0, M9K_X51_Y65_N0, M9K_X51_Y62_N0, M9K_X78_Y51_N0, M9K_X78_Y47_N0, M9K_X51_Y51_N0, M9K_X78_Y62_N0 ; Don't care ; Old data ; Old data ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; +;8;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; +;16;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; +;24;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; + + +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; +;8;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; +;16;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; +;24;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ;(11011110101011011011111011101111) (170526875) (-559038737) (-2-1-5-2-4-1-1-1) ; + + +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; +;8;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; +;16;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; +;24;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; +;32;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; +;40;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; +;48;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ;(00000000000000000000000000000000) (0) (0) (00) ; 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+;224;(10101100000011100100100111110101) (-226849365) (-1408349707) (-5-3-15-1-11-60-11) ;(11001001101001011110101001110110) (1963521980) (-911873418) (-3-6-5-10-1-5-8-10) ;(00000101101100000100110110000110) (554046606) (95440262) (5B04D86) ;(10110010100110101100011100010010) (616249292) (-1298479342) (-4-13-6-5-3-8-14-14) ;(01001110001101000100010010010011) (-532441425) (1312048275) (4E344493) ;(11010100010111101101111001001000) (-1055253374) (-731980216) (-2-11-10-1-2-1-11-8) ;(00111101101001111110010000100110) (-1038172546) (1034413094) (3DA7E426) ;(01001101011010101000100100110111) (-614979181) (1298827575) (4D6A8937) ; +;232;(10011001101101011001101111010100) (1819988890) (-1716151340) (-6-6-4-10-6-4-2-12) ;(00011111100010100101011101010001) (-552513775) (529160017) (1F8A5751) ;(10001011000001111110011001001110) (-33563718) (-1962416562) (-7-4-15-8-1-9-11-2) ;(10110100110111001101010010010110) (836858096) (-1260596074) (-4-11-2-3-2-11-6-10) ;(01000010111110000100111111100110) (-1871435902) (1123569638) (42F84FE6) ;(11110001110101011001010100101111) (-1612465321) (-237660881) (-14-2-10-6-10-13-1) ;(10100010111001011010010000101101) (-1358972075) (-1562008531) (-5-13-1-10-5-11-13-3) ;(00010101101100011010111100010110) (-1740639870) (363966230) (15B1AF16) ; +;240;(00010110100000000001001010111100) (-1654956022) (377492156) (168012BC) ;(00101110001001110110011000010010) (1316695726) (774333970) (2E276612) ;(10001001100100010011111010101010) (-191089582) (-1986969942) (-7-6-6-14-12-1-5-6) ;(11000110000001111010000110100010) (1413877456) (-972578398) (-3-9-15-8-5-14-5-14) ;(11111101100010110101010001001101) (-235125663) (-41200563) (-2-7-4-10-11-11-3) ;(10101110110000110001101001010011) (30320993) (-1362945453) (-5-1-3-12-14-5-10-13) ;(00100101111110010101100010101101) (281286959) (637098157) (25F958AD) ;(00110110010110010000001111101100) (-1963732838) (911803372) (365903EC) ; +;248;(00010100011101100001100001100101) (-1859553151) (343283813) (14761865) ;(01010110100011001100001000111011) (495657425) (1452065339) (568CC23B) ;(10110000001110000110001100000101) (385767275) (-1338481915) (-4-15-12-7-9-12-15-11) ;(11111011100111101011110110001010) (-430241166) (-73482870) (-4-6-1-4-2-7-6) ;(10100010010110010001000111010100) (-1404083406) (-1571221036) (-5-13-10-6-14-14-2-12) ;(10000000011011100011111110111011) (-1301889161) (-2140258373) (-7-15-9-1-120-4-5) ;(10011101111100110101001001100100) (-2055642986) (-1644998044) (-6-20-12-10-13-9-12) ;(11010110001010110011100000010100) (-870176458) (-701810668) (-2-9-13-4-12-7-14-12) ; + + ++-------------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-------------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-------------------------+ +; Block interconnects ; 6,699 / 342,891 ( 2 % ) ; +; C16 interconnects ; 370 / 10,120 ( 4 % ) ; +; C4 interconnects ; 4,207 / 209,544 ( 2 % ) ; +; Direct links ; 319 / 342,891 ( < 1 % ) ; +; Global clocks ; 4 / 20 ( 20 % ) ; +; Local interconnects ; 1,216 / 119,088 ( 1 % ) ; +; R24 interconnects ; 466 / 9,963 ( 5 % ) ; +; R4 interconnects ; 4,336 / 289,782 ( 1 % ) ; ++-----------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-------------------------------+ +; Number of Logic Elements (Average = 13.96) ; Number of LABs (Total = 160) ; ++---------------------------------------------+-------------------------------+ +; 1 ; 1 ; +; 2 ; 4 ; +; 3 ; 1 ; +; 4 ; 1 ; +; 5 ; 1 ; +; 6 ; 4 ; +; 7 ; 1 ; +; 8 ; 2 ; +; 9 ; 3 ; +; 10 ; 2 ; +; 11 ; 4 ; +; 12 ; 7 ; +; 13 ; 4 ; +; 14 ; 16 ; +; 15 ; 29 ; +; 16 ; 80 ; ++---------------------------------------------+-------------------------------+ + + ++--------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-------------------------------+ +; LAB-wide Signals (Average = 2.25) ; Number of LABs (Total = 160) ; ++------------------------------------+-------------------------------+ +; 1 Async. clear ; 113 ; +; 1 Clock ; 136 ; +; 1 Clock enable ; 58 ; +; 1 Sync. clear ; 6 ; +; 1 Sync. load ; 28 ; +; 2 Async. clears ; 2 ; +; 2 Clock enables ; 10 ; +; 2 Clocks ; 7 ; ++------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-------------------------------+ +; Number of Signals Sourced (Average = 21.06) ; Number of LABs (Total = 160) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 1 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 2 ; +; 4 ; 2 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 1 ; +; 11 ; 3 ; +; 12 ; 3 ; +; 13 ; 1 ; +; 14 ; 2 ; +; 15 ; 4 ; +; 16 ; 16 ; +; 17 ; 6 ; +; 18 ; 6 ; +; 19 ; 5 ; +; 20 ; 12 ; +; 21 ; 7 ; +; 22 ; 8 ; +; 23 ; 10 ; +; 24 ; 12 ; +; 25 ; 18 ; +; 26 ; 8 ; +; 27 ; 11 ; +; 28 ; 9 ; +; 29 ; 3 ; +; 30 ; 1 ; +; 31 ; 1 ; +; 32 ; 5 ; ++----------------------------------------------+-------------------------------+ + + ++---------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-------------------------------+ +; Number of Signals Sourced Out (Average = 8.65) ; Number of LABs (Total = 160) ; ++-------------------------------------------------+-------------------------------+ +; 0 ; 1 ; +; 1 ; 1 ; +; 2 ; 7 ; +; 3 ; 5 ; +; 4 ; 24 ; +; 5 ; 6 ; +; 6 ; 16 ; +; 7 ; 10 ; +; 8 ; 15 ; +; 9 ; 10 ; +; 10 ; 14 ; +; 11 ; 7 ; +; 12 ; 11 ; +; 13 ; 7 ; +; 14 ; 10 ; +; 15 ; 2 ; +; 16 ; 10 ; +; 17 ; 1 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 2 ; +; 22 ; 0 ; +; 23 ; 1 ; ++-------------------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-------------------------------+ +; Number of Distinct Inputs (Average = 18.74) ; Number of LABs (Total = 160) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 3 ; +; 4 ; 2 ; +; 5 ; 5 ; +; 6 ; 2 ; +; 7 ; 4 ; +; 8 ; 0 ; +; 9 ; 3 ; +; 10 ; 2 ; +; 11 ; 4 ; +; 12 ; 5 ; +; 13 ; 5 ; +; 14 ; 6 ; +; 15 ; 7 ; +; 16 ; 6 ; +; 17 ; 6 ; +; 18 ; 14 ; +; 19 ; 9 ; +; 20 ; 7 ; +; 21 ; 10 ; +; 22 ; 5 ; +; 23 ; 5 ; +; 24 ; 6 ; +; 25 ; 7 ; +; 26 ; 12 ; +; 27 ; 7 ; +; 28 ; 3 ; +; 29 ; 3 ; +; 30 ; 2 ; +; 31 ; 2 ; +; 32 ; 0 ; +; 33 ; 4 ; +; 34 ; 2 ; ++----------------------------------------------+-------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 118 ; 0 ; 118 ; 0 ; 0 ; 122 ; 118 ; 0 ; 122 ; 122 ; 0 ; 49 ; 0 ; 0 ; 31 ; 0 ; 49 ; 31 ; 0 ; 0 ; 0 ; 49 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 4 ; 122 ; 4 ; 122 ; 122 ; 0 ; 4 ; 122 ; 0 ; 0 ; 122 ; 73 ; 122 ; 122 ; 91 ; 122 ; 73 ; 91 ; 122 ; 122 ; 122 ; 73 ; 122 ; 122 ; 122 ; 122 ; 122 ; 0 ; 122 ; 122 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; LEDG[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDG[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LEDR[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX2[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX3[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX4[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX4[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX4[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX4[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX4[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX4[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX4[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX5[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX5[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX5[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX5[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX5[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX5[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX5[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX6[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX6[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX6[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX6[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX6[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX6[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX6[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX7[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX7[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX7[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX7[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX7[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX7[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HEX7[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_RS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_RW ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_data[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_EN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_ON ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LCD_BLON ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 �C ; +; High Junction Temperature ; 85 �C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device EP4CE115F29C7 for design "lights" +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE40F29C7 is compatible + Info (176445): Device EP4CE40F29I7 is compatible + Info (176445): Device EP4CE30F29C7 is compatible + Info (176445): Device EP4CE30F29I7 is compatible + Info (176445): Device EP4CE55F29C7 is compatible + Info (176445): Device EP4CE55F29I7 is compatible + Info (176445): Device EP4CE75F29C7 is compatible + Info (176445): Device EP4CE75F29I7 is compatible + Info (176445): Device EP4CE115F29I7 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity alt_jtag_atlantic + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] + Info (332165): Entity sld_jtag_hub + Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz + Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} +Critical Warning (332012): Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 100.000 altera_reserved_tck +Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176353): Automatically promoted node nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node nios_system:NiosII|altera_reset_controller:rst_controller|WideOr0~0 + Info (176357): Destination node nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wren + Info (176357): Destination node nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 +Info (176353): Automatically promoted node nios_system:NiosII|altera_reset_controller:rst_controller|merged_reset~0 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176218): Packed 8 registers into blocks of type EC +Warning (15709): Ignored I/O standard assignments to the following nodes + Warning (15710): Ignored I/O standard assignment to node "AUD_ADCDAT" + Warning (15710): Ignored I/O standard assignment to node "AUD_ADCLRCK" + Warning (15710): Ignored I/O standard assignment to node "AUD_BCLK" + Warning (15710): Ignored I/O standard assignment to node "AUD_DACDAT" + Warning (15710): Ignored I/O standard assignment to node "AUD_DACLRCK" + Warning (15710): Ignored I/O standard assignment to node "AUD_XCK" + Warning (15710): Ignored I/O standard assignment to node "CLOCK2_50" + Warning (15710): Ignored I/O standard assignment to node "CLOCK3_50" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[0]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[10]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[11]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[1]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[2]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[3]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[4]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[5]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[6]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[7]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[8]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[9]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_BA[0]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_BA[1]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_CAS_N" + Warning (15710): Ignored I/O standard assignment to node "DRAM_CKE" + Warning (15710): Ignored I/O standard assignment to node "DRAM_CLK" + Warning (15710): Ignored I/O standard assignment to node "DRAM_CS_N" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[0]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[1]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[2]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQM[3]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[0]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[10]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[11]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[12]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[13]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[14]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[15]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[16]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[17]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[18]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[19]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[1]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[20]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[21]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[22]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[23]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[24]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[25]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[26]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[27]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[28]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[29]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[2]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[30]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[31]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[3]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[4]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[5]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[6]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[7]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[8]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[9]" + Warning (15710): Ignored I/O standard assignment to node "DRAM_RAS_N" + Warning (15710): Ignored I/O standard assignment to node "DRAM_WE_N" + Warning (15710): Ignored I/O standard assignment to node "EEP_I2C_SCLK" + Warning (15710): Ignored I/O standard assignment to node "EEP_I2C_SDAT" + Warning (15710): Ignored I/O standard assignment to node "ENET0_GTX_CLK" + Warning (15710): Ignored I/O standard assignment to node "ENET0_INT_N" + Warning (15710): Ignored I/O standard assignment to node "ENET0_LINK100" + Warning (15710): Ignored I/O standard assignment to node "ENET0_MDC" + Warning (15710): Ignored I/O standard assignment to node "ENET0_MDIO" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RST_N" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_CLK" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_COL" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_CRS" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[0]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[1]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[2]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DATA[3]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_DV" + Warning (15710): Ignored I/O standard assignment to node "ENET0_RX_ER" + Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_CLK" + Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[0]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[1]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[2]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_DATA[3]" + Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_EN" + Warning (15710): Ignored I/O standard assignment to node "ENET0_TX_ER" + Warning (15710): Ignored I/O standard assignment to node "ENET1_GTX_CLK" + Warning (15710): Ignored I/O standard assignment to node "ENET1_INT_N" + Warning (15710): Ignored I/O standard assignment to node "ENET1_LINK100" + Warning (15710): Ignored I/O standard assignment to node "ENET1_MDC" + Warning (15710): Ignored I/O standard assignment to node "ENET1_MDIO" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RST_N" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_CLK" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_COL" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_CRS" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[0]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[1]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[2]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DATA[3]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_DV" + Warning (15710): Ignored I/O standard assignment to node "ENET1_RX_ER" + Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_CLK" + Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[0]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[1]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[2]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_DATA[3]" + Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_EN" + Warning (15710): Ignored I/O standard assignment to node "ENET1_TX_ER" + Warning (15710): Ignored I/O standard assignment to node "ENETCLK_25" + Warning (15710): Ignored I/O standard assignment to node "EX_IO[0]" + Warning (15710): Ignored I/O standard assignment to node "EX_IO[1]" + Warning (15710): Ignored I/O standard assignment to node "EX_IO[2]" + Warning (15710): Ignored I/O standard assignment to node "EX_IO[3]" + Warning (15710): Ignored I/O standard assignment to node "EX_IO[4]" + Warning (15710): Ignored I/O standard assignment to node "EX_IO[5]" + Warning (15710): Ignored I/O standard assignment to node "EX_IO[6]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[22]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]" + Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]" + Warning (15710): Ignored I/O standard assignment to node "FL_CE_N" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]" + Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]" + Warning (15710): Ignored I/O standard assignment to node "FL_OE_N" + Warning (15710): Ignored I/O standard assignment to node "FL_RST_N" + Warning (15710): Ignored I/O standard assignment to node "FL_RY" + Warning (15710): Ignored I/O standard assignment to node "FL_WE_N" + Warning (15710): Ignored I/O standard assignment to node "FL_WP_N" + Warning (15710): Ignored I/O standard assignment to node "GPIO[0]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[10]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[11]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[12]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[13]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[14]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[15]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[16]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[17]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[18]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[19]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[1]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[20]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[21]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[22]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[23]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[24]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[25]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[26]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[27]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[28]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[29]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[2]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[30]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[31]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[32]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[33]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[34]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[35]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[3]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[4]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[5]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[6]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[7]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[8]" + Warning (15710): Ignored I/O standard assignment to node "GPIO[9]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN0" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_N1" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_N2" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_P1" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKIN_P2" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT0" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_N1" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_N2" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_P1" + Warning (15710): Ignored I/O standard assignment to node "HSMC_CLKOUT_P2" + Warning (15710): Ignored I/O standard assignment to node "HSMC_D[0]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_D[1]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_D[2]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_D[3]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[0]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[10]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[11]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[12]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[13]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[14]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[15]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[16]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[1]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[2]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[3]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[4]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[5]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[6]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[7]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[8]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_N[9]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[0]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[10]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[11]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[12]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[13]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[14]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[15]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[16]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[1]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[2]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[3]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[4]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[5]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[6]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[7]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[8]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_RX_D_P[9]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[0]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[10]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[11]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[12]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[13]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[14]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[15]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[16]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[1]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[2]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[3]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[4]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[5]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[6]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[7]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[8]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_N[9]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[0]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[10]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[11]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[12]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[13]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[14]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[15]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[16]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[1]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[2]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[3]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[4]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[5]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[6]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[7]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[8]" + Warning (15710): Ignored I/O standard assignment to node "HSMC_TX_D_P[9]" + Warning (15710): Ignored I/O standard assignment to node "I2C_SCLK" + Warning (15710): Ignored I/O standard assignment to node "I2C_SDAT" + Warning (15710): Ignored I/O standard assignment to node "IRDA_RXD" + Warning (15710): Ignored I/O standard assignment to node "LEDG[8]" + Warning (15710): Ignored I/O standard assignment to node "OTG_ADDR[0]" + Warning (15710): Ignored I/O standard assignment to node "OTG_ADDR[1]" + Warning (15710): Ignored I/O standard assignment to node "OTG_CS_N" + Warning (15710): Ignored I/O standard assignment to node "OTG_DACK_N[0]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DACK_N[1]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[0]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[10]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[11]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[12]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[13]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[14]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[15]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[1]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[2]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[3]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[4]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[5]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[6]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[7]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[8]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DATA[9]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DREQ[0]" + Warning (15710): Ignored I/O standard assignment to node "OTG_DREQ[1]" + Warning (15710): Ignored I/O standard assignment to node "OTG_FSPEED" + Warning (15710): Ignored I/O standard assignment to node "OTG_INT[0]" + Warning (15710): Ignored I/O standard assignment to node "OTG_INT[1]" + Warning (15710): Ignored I/O standard assignment to node "OTG_LSPEED" + Warning (15710): Ignored I/O standard assignment to node "OTG_RD_N" + Warning (15710): Ignored I/O standard assignment to node "OTG_RST_N" + Warning (15710): Ignored I/O standard assignment to node "OTG_WR_N" + Warning (15710): Ignored I/O standard assignment to node "PS2_CLK" + Warning (15710): Ignored I/O standard assignment to node "PS2_CLK2" + Warning (15710): Ignored I/O standard assignment to node "PS2_DAT" + Warning (15710): Ignored I/O standard assignment to node "PS2_DAT2" + Warning (15710): Ignored I/O standard assignment to node "SD_CLK" + Warning (15710): Ignored I/O standard assignment to node "SD_CMD" + Warning (15710): Ignored I/O standard assignment to node "SD_DAT[0]" + Warning (15710): Ignored I/O standard assignment to node "SD_DAT[1]" + Warning (15710): Ignored I/O standard assignment to node "SD_DAT[2]" + Warning (15710): Ignored I/O standard assignment to node "SD_DAT[3]" + Warning (15710): Ignored I/O standard assignment to node "SD_WP_N" + Warning (15710): Ignored I/O standard assignment to node "SMA_CLKIN" + Warning (15710): Ignored I/O standard assignment to node "SMA_CLKOUT" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[0]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[10]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[11]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[12]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[13]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[14]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[15]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[16]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[17]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[18]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[19]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[1]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[2]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[3]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[4]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[5]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[6]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[7]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[8]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_ADDR[9]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_CE_N" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[0]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[10]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[11]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[12]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[13]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[14]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[15]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[1]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[2]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[3]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[4]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[5]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[6]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[7]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[8]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_DQ[9]" + Warning (15710): Ignored I/O standard assignment to node "SRAM_LB_N" + Warning (15710): Ignored I/O standard assignment to node "SRAM_OE_N" + Warning (15710): Ignored I/O standard assignment to node "SRAM_UB_N" + Warning (15710): Ignored I/O standard assignment to node "SRAM_WE_N" + Warning (15710): Ignored I/O standard assignment to node "TD_CLK27" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[0]" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[1]" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[2]" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[3]" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[4]" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[5]" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[6]" + Warning (15710): Ignored I/O standard assignment to node "TD_DATA[7]" + Warning (15710): Ignored I/O standard assignment to node "TD_HS" + Warning (15710): Ignored I/O standard assignment to node "TD_RESET_N" + Warning (15710): Ignored I/O standard assignment to node "TD_VS" + Warning (15710): Ignored I/O standard assignment to node "UART_CTS" + Warning (15710): Ignored I/O standard assignment to node "UART_RTS" + Warning (15710): Ignored I/O standard assignment to node "UART_RXD" + Warning (15710): Ignored I/O standard assignment to node "UART_TXD" + Warning (15710): Ignored I/O standard assignment to node "VGA_BLANK_N" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[0]" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[1]" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[2]" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[3]" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[4]" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[5]" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[6]" + Warning (15710): Ignored I/O standard assignment to node "VGA_B[7]" + Warning (15710): Ignored I/O standard assignment to node "VGA_CLK" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[0]" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[1]" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[2]" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[3]" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[4]" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[5]" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[6]" + Warning (15710): Ignored I/O standard assignment to node "VGA_G[7]" + Warning (15710): Ignored I/O standard assignment to node "VGA_HS" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[0]" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[1]" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[2]" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[3]" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[4]" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[5]" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[6]" + Warning (15710): Ignored I/O standard assignment to node "VGA_R[7]" + Warning (15710): Ignored I/O standard assignment to node "VGA_SYNC_N" + Warning (15710): Ignored I/O standard assignment to node "VGA_VS" +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design + Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design + Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design + Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design + Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design + Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DACK_N[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DACK_N[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_DREQ[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_FSPEED" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_INT[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_INT[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_LSPEED" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design + Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design + Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design + Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design + Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design + Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design + Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design + Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:08 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 2% of the available device resources + Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X46_Y24 to location X57_Y36 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:04 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning (169177): 9 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. + Info (169178): Pin LCD_data[0] uses I/O standard 3.3-V LVTTL at L3 + Info (169178): Pin LCD_data[1] uses I/O standard 3.3-V LVTTL at L1 + Info (169178): Pin LCD_data[2] uses I/O standard 3.3-V LVTTL at L2 + Info (169178): Pin LCD_data[3] uses I/O standard 3.3-V LVTTL at K7 + Info (169178): Pin LCD_data[4] uses I/O standard 3.3-V LVTTL at K1 + Info (169178): Pin LCD_data[5] uses I/O standard 3.3-V LVTTL at K2 + Info (169178): Pin LCD_data[6] uses I/O standard 3.3-V LVTTL at M3 + Info (169178): Pin LCD_data[7] uses I/O standard 3.3-V LVTTL at M5 + Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at Y2 +Info (144001): Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 827 warnings + Info: Peak virtual memory: 1017 megabytes + Info: Processing ended: Thu Dec 22 10:08:33 2016 + Info: Elapsed time: 00:00:39 + Info: Total CPU time (on all processors): 00:00:38 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.fit.smsg. + + diff --git a/output_files/lights.fit.smsg b/output_files/lights.fit.smsg index 7121cbb..558ea95 100644 --- a/output_files/lights.fit.smsg +++ b/output_files/lights.fit.smsg @@ -1,8 +1,8 @@ -Extra Info (176273): Performing register packing on registers with non-logic cell location assignments -Extra Info (176274): Completed register packing on registers with non-logic cell location assignments -Extra Info (176236): Started Fast Input/Output/OE register processing -Extra Info (176237): Finished Fast Input/Output/OE register processing -Extra Info (176238): Start inferring scan chains for DSP blocks -Extra Info (176239): Inferring scan chains for DSP blocks is complete -Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/output_files/lights.fit.summary b/output_files/lights.fit.summary index f000b78..87d9510 100644 --- a/output_files/lights.fit.summary +++ b/output_files/lights.fit.summary @@ -1,16 +1,16 @@ -Fitter Status : Successful - Fri Dec 02 01:33:11 2016 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : lights -Top-level Entity Name : lights -Family : Cyclone IV E -Device : EP4CE115F29C7 -Timing Models : Final -Total logic elements : 2,232 / 114,480 ( 2 % ) - Total combinational functions : 2,062 / 114,480 ( 2 % ) - Dedicated logic registers : 1,204 / 114,480 ( 1 % ) -Total registers : 1204 -Total pins : 118 / 529 ( 22 % ) -Total virtual pins : 0 -Total memory bits : 1,649,664 / 3,981,312 ( 41 % ) -Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % ) -Total PLLs : 0 / 4 ( 0 % ) +Fitter Status : Successful - Thu Dec 22 10:08:30 2016 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : lights +Top-level Entity Name : lights +Family : Cyclone IV E +Device : EP4CE115F29C7 +Timing Models : Final +Total logic elements : 2,234 / 114,480 ( 2 % ) + Total combinational functions : 2,060 / 114,480 ( 2 % ) + Dedicated logic registers : 1,204 / 114,480 ( 1 % ) +Total registers : 1204 +Total pins : 118 / 529 ( 22 % ) +Total virtual pins : 0 +Total memory bits : 1,649,664 / 3,981,312 ( 41 % ) +Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/output_files/lights.flow.rpt b/output_files/lights.flow.rpt index 53da3cf..4a97568 100644 --- a/output_files/lights.flow.rpt +++ b/output_files/lights.flow.rpt @@ -1,123 +1,123 @@ -Flow report for lights -Fri Dec 02 01:33:28 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - 8. Flow Messages - 9. Flow Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Fri Dec 02 01:33:21 2016 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Device ; EP4CE115F29C7 ; -; Timing Models ; Final ; -; Total logic elements ; 2,232 / 114,480 ( 2 % ) ; -; Total combinational functions ; 2,062 / 114,480 ( 2 % ) ; -; Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; -; Total registers ; 1204 ; -; Total pins ; 118 / 529 ( 22 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; -; Total PLLs ; 0 / 4 ( 0 % ) ; -+------------------------------------+-------------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 12/02/2016 01:32:08 ; -; Main task ; Compilation ; -; Revision Name ; lights ; -+-------------------+---------------------+ - - -+------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+-------------------------------------+---------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+-------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 224508679122295.148060992813004 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -+-------------------------------------+---------------------------------+---------------+-------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:32 ; 1.0 ; 654 MB ; 00:00:31 ; -; Fitter ; 00:00:29 ; 1.0 ; 1016 MB ; 00:00:29 ; -; Assembler ; 00:00:07 ; 1.0 ; 477 MB ; 00:00:06 ; -; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 606 MB ; 00:00:05 ; -; Total ; 00:01:14 ; -- ; -- ; 00:01:11 ; -+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+----------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+---------------------------+------------------+-----------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+---------------------------+------------------+-----------+------------+----------------+ -; Analysis & Synthesis ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -; Fitter ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -; Assembler ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -; TimeQuest Timing Analyzer ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; -+---------------------------+------------------+-----------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off lights -c lights -quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights -quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights -quartus_sta lights -c lights - - - +Flow report for lights +Thu Dec 22 10:08:48 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Thu Dec 22 10:08:41 2016 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; lights ; +; Top-level Entity Name ; lights ; +; Family ; Cyclone IV E ; +; Device ; EP4CE115F29C7 ; +; Timing Models ; Final ; +; Total logic elements ; 2,234 / 114,480 ( 2 % ) ; +; Total combinational functions ; 2,060 / 114,480 ( 2 % ) ; +; Dedicated logic registers ; 1,204 / 114,480 ( 1 % ) ; +; Total registers ; 1204 ; +; Total pins ; 118 / 529 ( 22 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 1,649,664 / 3,981,312 ( 41 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/22/2016 10:07:13 ; +; Main task ; Compilation ; +; Revision Name ; lights ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+---------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+---------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 224508679122295.148236883301196 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+---------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:38 ; 1.0 ; 657 MB ; 00:00:35 ; +; Fitter ; 00:00:36 ; 1.0 ; 1017 MB ; 00:00:35 ; +; Assembler ; 00:00:07 ; 1.0 ; 481 MB ; 00:00:07 ; +; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 605 MB ; 00:00:06 ; +; Total ; 00:01:27 ; -- ; -- ; 00:01:23 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; LAPTOP-V9RF6EJU ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off lights -c lights +quartus_fit --read_settings_files=off --write_settings_files=off lights -c lights +quartus_asm --read_settings_files=off --write_settings_files=off lights -c lights +quartus_sta lights -c lights + + + diff --git a/output_files/lights.jdi b/output_files/lights.jdi index b0cfc33..ef8cbee 100644 --- a/output_files/lights.jdi +++ b/output_files/lights.jdi @@ -1,144 +1,144 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/output_files/lights.map.rpt b/output_files/lights.map.rpt index 77cca81..4e13598 100644 --- a/output_files/lights.map.rpt +++ b/output_files/lights.map.rpt @@ -1,7186 +1,7187 @@ -Analysis & Synthesis report for lights -Fri Dec 02 01:32:41 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. Analysis & Synthesis RAM Summary - 9. State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize - 10. Registers Protected by Synthesis - 11. Registers Removed During Synthesis - 12. Removed Registers Triggering Further Register Optimizations - 13. General Register Statistics - 14. Inverted Register Statistics - 15. Multiplexer Restructuring Statistics (Restructuring Performed) - 16. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated - 17. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated - 18. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer - 19. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated - 20. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 - 21. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 - 22. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 - 23. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 - 24. Source assignments for nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated - 25. Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 - 26. Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 - 27. Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller - 28. Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 - 29. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux - 30. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 - 31. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux - 32. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 - 33. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 - 34. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 - 35. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 - 36. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 - 37. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 - 38. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 - 39. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 - 40. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 - 41. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 - 42. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 - 43. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 - 44. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 - 45. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 - 46. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 - 47. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 - 48. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 - 49. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a - 50. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram - 51. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b - 52. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram - 53. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer - 54. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram - 55. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram - 56. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 - 57. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 - 58. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 - 59. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 - 60. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy - 61. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory - 62. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram - 63. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo - 64. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo - 65. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator - 66. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator - 67. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator - 68. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator - 69. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator - 70. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator - 71. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator - 72. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator - 73. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator - 74. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator - 75. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator - 76. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator - 77. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator - 78. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator - 79. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator - 80. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator - 81. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator - 82. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator - 83. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator - 84. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator - 85. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent - 86. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent - 87. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent - 88. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 89. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo - 90. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent - 91. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 92. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo - 93. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent - 94. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 95. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo - 96. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent - 97. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor - 98. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo - 99. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent -100. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -101. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -102. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent -103. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -104. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -105. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent -106. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -107. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -108. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent -109. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -110. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -111. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent -112. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -113. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -114. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent -115. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -116. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -117. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent -118. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -119. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -120. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent -121. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -122. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -123. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent -124. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -125. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -126. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent -127. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -128. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -129. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent -130. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -131. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -132. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent -133. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -134. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo -135. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent -136. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -137. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -138. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent -139. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor -140. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo -141. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode -142. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode -143. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode -144. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode -145. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode -146. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode -147. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode -148. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode -149. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode -150. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode -151. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode -152. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode -153. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode -154. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode -155. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode -156. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode -157. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode -158. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode -159. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode -160. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode -161. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller -162. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 -163. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb -164. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -165. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb -166. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -167. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb -168. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -169. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb -170. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder -171. altsyncram Parameter Settings by Entity Instance -172. scfifo Parameter Settings by Entity Instance -173. Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -174. Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -175. Port Connectivity Checks: "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -176. Port Connectivity Checks: "nios_system:NiosII|altera_reset_controller:rst_controller" -177. Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" -178. Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" -179. Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" -180. Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" -181. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -182. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent" -183. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -184. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent" -185. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" -186. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent" -187. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -188. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent" -189. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -190. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent" -191. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -192. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent" -193. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -194. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent" -195. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -196. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent" -197. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -198. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent" -199. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -200. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent" -201. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -202. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent" -203. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -204. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent" -205. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -206. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent" -207. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -208. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent" -209. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" -210. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent" -211. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -212. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent" -213. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" -214. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent" -215. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -216. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -217. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" -218. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -219. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator" -220. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator" -221. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" -222. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator" -223. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator" -224. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator" -225. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator" -226. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator" -227. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator" -228. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator" -229. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator" -230. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator" -231. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator" -232. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator" -233. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" -234. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" -235. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" -236. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" -237. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" -238. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" -239. Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" -240. Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" -241. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -242. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4" -243. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" -244. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" -245. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" -246. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" -247. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" -248. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" -249. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" -250. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" -251. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" -252. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" -253. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" -254. Port Connectivity Checks: "nios_system:NiosII" -255. Elapsed Time Per Partition -256. Analysis & Synthesis Messages -257. Analysis & Synthesis Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Fri Dec 02 01:32:41 2016 ; -; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; -; Revision Name ; lights ; -; Top-level Entity Name ; lights ; -; Family ; Cyclone IV E ; -; Total logic elements ; 2,333 ; -; Total combinational functions ; 2,058 ; -; Dedicated logic registers ; 1,212 ; -; Total registers ; 1212 ; -; Total pins ; 118 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 1,649,664 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Total PLLs ; 0 ; -+------------------------------------+-------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP4CE115F29C7 ; ; -; Top-level entity name ; lights ; lights ; -; Family name ; Cyclone IV E ; Cyclone IV GX ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; On ; On ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto DSP Block Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM Block Balancing ; On ; On ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; On ; On ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Pre-Mapping Resynthesis Optimization ; Off ; Off ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -; Resource Aware Inference For Block RAM ; On ; On ; -; Synthesis Seed ; 1 ; 1 ; -+----------------------------------------------------------------------------+--------------------+--------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; lights.vhd ; yes ; User VHDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd ; ; -; nios_system/synthesis/nios_system.v ; yes ; User Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v ; ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv ; altera_reserved_qsys_nios_system ; -; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v ; altera_reserved_qsys_nios_system ; -; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ; ; -; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; -; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc ; ; -; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; -; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ; -; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; -; altrom.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc ; ; -; altram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc ; ; -; altdpram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc ; ; -; db/altsyncram_0rh1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf ; ; -; db/altsyncram_1rh1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf ; ; -; altera_std_synchronizer.v ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; -; db/altsyncram_4891.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf ; ; -; sld_virtual_jtag_basic.v ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v ; ; -; db/altsyncram_4ed1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf ; ; -; db/decode_qsa.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf ; ; -; db/mux_nob.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf ; ; -; scfifo.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf ; ; -; a_regfifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_regfifo.inc ; ; -; a_dpfifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_dpfifo.inc ; ; -; a_i2fifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_i2fifo.inc ; ; -; a_fffifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_fffifo.inc ; ; -; a_f2fifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_f2fifo.inc ; ; -; db/scfifo_jr21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf ; ; -; db/a_dpfifo_q131.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf ; ; -; db/a_fefifo_7cf.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf ; ; -; db/cntr_do7.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf ; ; -; db/dpram_nl21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf ; ; -; db/altsyncram_r1m1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf ; ; -; db/cntr_1ob.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf ; ; -; alt_jtag_atlantic.v ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v ; ; -; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd ; ; -; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ; -; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ; -+---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ - - -+--------------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+----------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------+ -; Estimated Total logic elements ; 2,333 ; -; ; ; -; Total combinational functions ; 2058 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1077 ; -; -- 3 input functions ; 679 ; -; -- <=2 input functions ; 302 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 1911 ; -; -- arithmetic mode ; 147 ; -; ; ; -; Total registers ; 1212 ; -; -- Dedicated logic registers ; 1212 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 118 ; -; Total memory bits ; 1649664 ; -; Embedded Multiplier 9-bit elements ; 0 ; -; Maximum fan-out node ; CLOCK_50~input ; -; Maximum fan-out ; 1365 ; -; Total fan-out ; 16742 ; -; Average fan-out ; 4.35 ; -+---------------------------------------------+----------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -; |lights ; 2058 (1) ; 1212 (0) ; 1649664 ; 0 ; 0 ; 0 ; 118 ; 0 ; |lights ; work ; -; |nios_system:NiosII| ; 1897 (0) ; 1115 (0) ; 1649664 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII ; work ; -; |altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 8 (8) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_data_master_translator| ; 9 (9) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_master_translator:nios2_processor_instruction_master_translator| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex0_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex1_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex2_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex3_s1_translator| ; 5 (5) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex4_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex5_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex6_s1_translator| ; 5 (5) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:hex7_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator| ; 9 (9) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_16207_0_control_slave_translator| ; 14 (14) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_blon_s1_translator| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:lcd_on_s1_translator| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:ledrs_s1_translator| ; 6 (6) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:leds_s1_translator| ; 5 (5) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator| ; 1 (1) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:onchip_memory_s1_translator| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:push_switches_s1_translator| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_merlin_slave_translator:switches_s1_translator| ; 6 (6) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; altera_reserved_qsys_nios_system ; -; |altera_reset_controller:rst_controller| ; 2 (2) ; 9 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller ; altera_reserved_qsys_nios_system ; -; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDRs:ledrs| ; 20 (20) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_LEDRs:ledrs ; altera_reserved_qsys_nios_system ; -; |nios_system_LEDs:leds| ; 11 (11) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_LEDs:leds ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router:addr_router| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_addr_router:addr_router ; altera_reserved_qsys_nios_system ; -; |nios_system_addr_router_001:addr_router_001| ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:cmd_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux_001| ; 60 (56) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_cmd_xbar_mux:cmd_xbar_mux| ; 54 (50) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux ; altera_reserved_qsys_nios_system ; -; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex0| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex0 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex1| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex1 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex2| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex2 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex3| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex3 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex4| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex4 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex5| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex5 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex6| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex6 ; altera_reserved_qsys_nios_system ; -; |nios_system_hex0:hex7| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex7 ; altera_reserved_qsys_nios_system ; -; |nios_system_jtag_uart:jtag_uart| ; 140 (36) ; 112 (13) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart ; altera_reserved_qsys_nios_system ; -; |alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic| ; 53 (53) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic ; work ; -; |nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r ; altera_reserved_qsys_nios_system ; -; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; work ; -; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w ; altera_reserved_qsys_nios_system ; -; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; work ; -; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; work ; -; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; -; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; -; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; -; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; -; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; -; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; -; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; -; |nios_system_lcd_16207_0:lcd_16207_0| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_blon| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon ; altera_reserved_qsys_nios_system ; -; |nios_system_lcd_on:lcd_on| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_on ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor:nios2_processor| ; 929 (643) ; 576 (306) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci| ; 286 (34) ; 269 (80) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper| ; 92 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk| ; 6 (6) ; 49 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer4| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; work ; -; |nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck| ; 82 (82) ; 47 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; work ; -; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; work ; -; |sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; work ; -; |nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg| ; 8 (8) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug| ; 9 (8) ; 9 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug ; altera_reserved_qsys_nios_system ; -; |altera_std_synchronizer:the_altera_std_synchronizer| ; 1 (1) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; work ; -; |nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem| ; 111 (111) ; 49 (49) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem ; altera_reserved_qsys_nios_system ; -; |nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; work ; -; |altsyncram_4891:auto_generated| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; work ; -; |altsyncram_0rh1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; work ; -; |nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; work ; -; |altsyncram_1rh1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; work ; -; |nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench ; altera_reserved_qsys_nios_system ; -; |nios_system_onchip_memory:onchip_memory| ; 168 (1) ; 3 (0) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; altera_reserved_qsys_nios_system ; -; |altsyncram:the_altsyncram| ; 167 (0) ; 3 (0) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; work ; -; |altsyncram_4ed1:auto_generated| ; 167 (0) ; 3 (3) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; work ; -; |decode_qsa:decode3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 ; work ; -; |mux_nob:mux2| ; 160 (160) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 ; work ; -; |nios_system_push_switches:push_switches| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_push_switches:push_switches ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux:rsp_xbar_mux| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux ; altera_reserved_qsys_nios_system ; -; |nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; altera_reserved_qsys_nios_system ; -; |nios_system_switches:switches| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_switches:switches ; altera_reserved_qsys_nios_system ; -; |sld_hub:auto_hub| ; 160 (1) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub ; work ; -; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 159 (119) ; 97 (69) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; work ; -; |sld_rom_sr:hub_info_reg| ; 23 (23) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; work ; -; |sld_shadow_jsm:shadow_jsm| ; 17 (17) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; work ; -+--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis RAM Summary ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ -; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256 ; 32 ; -- ; -- ; 8192 ; nios_system_nios2_processor_ociram_default_contents.mif ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; nios_system_nios2_processor_rf_ram_a.mif ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; nios_system_nios2_processor_rf_ram_b.mif ; -; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 51200 ; 32 ; -- ; -- ; 1638400 ; nios_system_onchip_memory.hex ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ - - -Encoding Type: One-Hot -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize ; -+------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Name ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000 ; -+------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DRsize.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DRsize.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; DRsize.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; DRsize.011 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; DRsize.100 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; DRsize.101 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Registers Protected by Synthesis ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ -; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[7] ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[2] ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[3] ; yes ; yes ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[4] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[5] ; yes ; yes ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[6] ; yes ; yes ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Registers Removed During Synthesis ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Register name ; Reason for Removal ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|locked[0,1] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|locked[0,1] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|av_readdata_pre[18..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|av_readdata_pre[11,23..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|av_readdata_pre[8..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[3..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_switches:switches|readdata[18..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[0..4,6..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ipending_reg[0..4,6..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_custom ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im|trc_im_addr[0..6] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im|trc_wrap ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto0 ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk|xbrk_break ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[3..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[18..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[1..4,6..31] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst1 ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|waitrequest_reset_override ; -; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; Merged with nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[22] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[23] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[23] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[24] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[24] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[25] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[25] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[7] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[7] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[27] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[27] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[28] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[28] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[29] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[29] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[30] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[30] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[31] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[31] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[0] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[0] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[1] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[1] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[2] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[2] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[3] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[3] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[4] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[4] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[6] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[6] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[8] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[8] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[9] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[9] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[10] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[10] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[11] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[11] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[12] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[12] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[13] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[13] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[14] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[14] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[15] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[15] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[26] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[26] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[16] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[16] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[17] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[17] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[18] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[18] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[19] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[19] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[20] ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[20] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[21] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigger_state ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigbrktype ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_early_rst ; Merged with nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|share_count[0] ; Lost fanout ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|share_count[0] ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~3 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~4 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~5 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.101 ; Lost fanout ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.011 ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.001 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.001 ; Stuck at GND due to stuck port data_in ; -; Total Number of Removed Registers = 975 ; ; -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Removed Registers Triggering Further Register Optimizations ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Register name ; Reason for Removal ; Registers Removed due to This Register ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break, ; -; ; due to stuck port data_in ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigbrktype ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; -; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[12] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[12] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[11] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[11] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[10] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[10] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[9] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[9] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[8] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[8] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[7] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[7] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[6] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[6] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[5] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[5] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[4] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[4] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[3] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[3] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[31] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[31] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[30] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[30] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[29] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[29] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[28] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[28] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[27] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[27] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[26] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[26] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[25] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[25] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[24] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[24] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[23] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[23] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[22] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[22] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[21] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[21] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[20] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[20] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[19] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[19] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_switches:switches|readdata[18] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[18] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[31] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[31] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[30] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[30] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[29] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[29] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[28] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[28] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[27] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[27] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[26] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[26] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[25] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[25] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[24] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[24] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[23] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[23] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[22] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[22] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[21] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[21] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[20] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[20] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[19] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[19] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[18] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[18] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[17] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[17] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[16] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[16] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[15] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[15] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[14] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[14] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[13] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[13] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[12] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[12] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[11] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[11] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[10] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[10] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[9] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[9] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[8] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[8] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[7] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[7] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[6] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[6] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[4] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[4] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[3] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[3] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[2] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[2] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[1] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[1] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigger_state ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[31] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[31] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[30] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[30] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[29] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[29] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[28] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[28] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[27] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[27] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[26] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[26] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[25] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[25] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[24] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[24] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[23] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[23] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[22] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[22] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[21] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[21] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[20] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[20] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[19] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[19] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[18] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[18] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[17] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[17] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[16] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[16] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[15] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[15] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[14] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[14] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[13] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[13] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; -; ; due to stuck port data_in ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~3 ; Lost Fanouts ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.101 ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 1212 ; -; Number of registers using Synchronous Clear ; 69 ; -; Number of registers using Synchronous Load ; 166 ; -; Number of registers using Asynchronous Clear ; 885 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 476 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Inverted Register Statistics ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; Inverted Register ; Fan out ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; 801 ; -; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; 23 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest ; 7 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_chain[1] ; 2 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; 228 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|i_read ; 7 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; -; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; 11 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2] ; 1 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; 9 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|t_dav ; 3 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1] ; 1 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[5] ; 2 ; -; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst2 ; 3 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[0] ; 1 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 1 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ; -; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; 1 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; -; Total number of inverted registers = 22 ; ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0] ; -; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[12] ; -; 3:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[27] ; -; 3:1 ; 17 bits ; 34 LEs ; 34 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[12] ; -; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[12] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1] ; -; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; -; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4] ; -; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte2_data[2] ; -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|readdata[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[1] ; -; 4:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[10] ; -; 4:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[20] ; -; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; -; 4:1 ; 23 bits ; 46 LEs ; 46 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[15] ; -; 4:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[31] ; -; 6:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; -; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; -; 6:1 ; 13 bits ; 52 LEs ; 26 LEs ; 26 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 6:1 ; 16 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 5:1 ; 13 bits ; 39 LEs ; 39 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28] ; -; 4:1 ; 17 bits ; 34 LEs ; 34 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[10] ; -; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[2] ; -; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|break_readreg[15] ; -; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[3] ; -; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; -; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; -; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[18] ; -; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[19] ; -; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; -; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; -; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; -; 8:1 ; 5 bits ; 25 LEs ; 10 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; -; 34:1 ; 4 bits ; 88 LEs ; 60 LEs ; 28 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 28:1 ; 4 bits ; 72 LEs ; 48 LEs ; 24 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; -; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; -; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; -; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; -; PRESERVE_REGISTER ; ON ; - ; din_s1 ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller ; -+-------------------+-------+------+-----------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+-----------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[2] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+-----------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+-------------------+-------+------+------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-------------------+-------+------+------------------------------------------------------------------------------------------+ -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; -; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; -+-------------------+-------+------+------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; -+-----------------+-------+------+----------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+----------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+----------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; -+-----------------+-------+------+----------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+----------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+----------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; -+-----------------+-------+------+--------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+--------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+--------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------+ -; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 ; -+-----------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------+-------+------+------------------------------------------------------------+ -; MESSAGE_DISABLE ; 15610 ; - ; clk ; -; MESSAGE_DISABLE ; 15610 ; - ; reset ; -+-----------------+-------+------+------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; lpm_file ; nios_system_nios2_processor_rf_ram_a.mif ; String ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; DUAL_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 5 ; Signed Integer ; -; NUMWORDS_A ; 32 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 32 ; Signed Integer ; -; WIDTHAD_B ; 5 ; Signed Integer ; -; NUMWORDS_B ; 32 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK0 ; Untyped ; -; ADDRESS_REG_B ; CLOCK0 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Untyped ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_nios2_processor_rf_ram_a.mif ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_0rh1 ; Untyped ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -; lpm_file ; nios_system_nios2_processor_rf_ram_b.mif ; String ; -+----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; DUAL_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 5 ; Signed Integer ; -; NUMWORDS_A ; 32 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 32 ; Signed Integer ; -; WIDTHAD_B ; 5 ; Signed Integer ; -; NUMWORDS_B ; 32 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK0 ; Untyped ; -; ADDRESS_REG_B ; CLOCK0 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Untyped ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_nios2_processor_rf_ram_b.mif ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_1rh1 ; Untyped ; -+------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; -+----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; lpm_file ; nios_system_nios2_processor_ociram_default_contents.mif ; String ; -+----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; -+------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; SINGLE_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 1 ; Untyped ; -; WIDTHAD_B ; 1 ; Untyped ; -; NUMWORDS_B ; 1 ; Untyped ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_nios2_processor_ociram_default_contents.mif ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_4891 ; Untyped ; -+------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; depth ; 2 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; sld_mfg_id ; 70 ; Signed Integer ; -; sld_type_id ; 34 ; Signed Integer ; -; sld_version ; 3 ; Signed Integer ; -; sld_instance_index ; 0 ; Signed Integer ; -; sld_auto_instance_index ; YES ; String ; -; sld_ir_width ; 2 ; Signed Integer ; -; sld_sim_n_scan ; 0 ; Signed Integer ; -; sld_sim_action ; ; String ; -; sld_sim_total_length ; 0 ; Signed Integer ; -; lpm_type ; sld_virtual_jtag_basic ; String ; -; lpm_hint ; UNUSED ; String ; -+-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; -+----------------+-------------------------------+--------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------------------------+--------------------------------------------------------+ -; INIT_FILE ; nios_system_onchip_memory.hex ; String ; -+----------------+-------------------------------+--------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; -+------------------------------------+-------------------------------+--------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-------------------------------+--------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; SINGLE_PORT ; Untyped ; -; WIDTH_A ; 32 ; Signed Integer ; -; WIDTHAD_A ; 16 ; Signed Integer ; -; NUMWORDS_A ; 51200 ; Signed Integer ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 1 ; Untyped ; -; WIDTHAD_B ; 1 ; Untyped ; -; NUMWORDS_B ; 1 ; Untyped ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Signed Integer ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; nios_system_onchip_memory.hex ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 51200 ; Signed Integer ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; -; WIDTH_ECCSTATUS ; 3 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; CBXI_PARAMETER ; altsyncram_4ed1 ; Untyped ; -+------------------------------------+-------------------------------+--------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; lpm_width ; 8 ; Signed Integer ; -; LPM_NUMWORDS ; 64 ; Signed Integer ; -; LPM_WIDTHU ; 6 ; Signed Integer ; -; LPM_SHOWAHEAD ; OFF ; Untyped ; -; UNDERFLOW_CHECKING ; OFF ; Untyped ; -; OVERFLOW_CHECKING ; OFF ; Untyped ; -; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; ALMOST_FULL_VALUE ; 0 ; Untyped ; -; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; lpm_width ; 8 ; Signed Integer ; -; LPM_NUMWORDS ; 64 ; Signed Integer ; -; LPM_WIDTHU ; 6 ; Signed Integer ; -; LPM_SHOWAHEAD ; OFF ; Untyped ; -; UNDERFLOW_CHECKING ; OFF ; Untyped ; -; OVERFLOW_CHECKING ; OFF ; Untyped ; -; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; ALMOST_FULL_VALUE ; 0 ; Untyped ; -; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; -; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; -+-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 19 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; USE_BURSTCOUNT ; 0 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WRITE ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 1 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -+-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 19 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; USE_BURSTCOUNT ; 0 ; Signed Integer ; -; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; -; USE_BEGINTRANSFER ; 0 ; Signed Integer ; -; USE_CHIPSELECT ; 0 ; Signed Integer ; -; USE_READ ; 1 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WRITE ; 1 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; AV_REGISTERINCOMINGSIGNALS ; 1 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -+-----------------------------+-------+--------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 9 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 16 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 4 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 1 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 1 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; -+--------------------------------+-------+---------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+---------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+---------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+-----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 8 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 13 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 13 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 13 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 13 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+--------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; -+--------------------------------+-------+----------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+----------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+----------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -; AV_ADDRESS_W ; 2 ; Signed Integer ; -; AV_DATA_W ; 32 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; -; AV_BYTEENABLE_W ; 1 ; Signed Integer ; -; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; -; AV_READLATENCY ; 0 ; Signed Integer ; -; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; -; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; -; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; -; USE_READDATAVALID ; 0 ; Signed Integer ; -; USE_WAITREQUEST ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; -; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; -; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; -; BITS_PER_WORD ; 2 ; Signed Integer ; -; UAV_ADDRESS_W ; 19 ; Signed Integer ; -; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; UAV_DATA_W ; 32 ; Signed Integer ; -; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; -; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; -; USE_UAV_CLKEN ; 0 ; Signed Integer ; -; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; -+--------------------------------+-------+------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 75 ; Signed Integer ; -; PKT_QOS_L ; 75 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 73 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 73 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 72 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 72 ; Signed Integer ; -; PKT_CACHE_H ; 93 ; Signed Integer ; -; PKT_CACHE_L ; 90 ; Signed Integer ; -; PKT_THREAD_ID_H ; 86 ; Signed Integer ; -; PKT_THREAD_ID_L ; 86 ; Signed Integer ; -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 71 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 70 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 60 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; -; BURSTWRAP_VALUE ; 3 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 19 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 5 ; Signed Integer ; -; PKT_DEST_ID_W ; 5 ; Signed Integer ; -+---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -; PKT_QOS_H ; 75 ; Signed Integer ; -; PKT_QOS_L ; 75 ; Signed Integer ; -; PKT_DATA_SIDEBAND_H ; 73 ; Signed Integer ; -; PKT_DATA_SIDEBAND_L ; 73 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_H ; 72 ; Signed Integer ; -; PKT_ADDR_SIDEBAND_L ; 72 ; Signed Integer ; -; PKT_CACHE_H ; 93 ; Signed Integer ; -; PKT_CACHE_L ; 90 ; Signed Integer ; -; PKT_THREAD_ID_H ; 86 ; Signed Integer ; -; PKT_THREAD_ID_L ; 86 ; Signed Integer ; -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; PKT_BURST_TYPE_H ; 71 ; Signed Integer ; -; PKT_BURST_TYPE_L ; 70 ; Signed Integer ; -; PKT_TRANS_EXCLUSIVE ; 60 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; -; ID ; 0 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; -; BURSTWRAP_VALUE ; 7 ; Signed Integer ; -; CACHE_VALUE ; 0 ; Signed Integer ; -; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; -; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_PROTECTION_W ; 3 ; Signed Integer ; -; PKT_ADDR_W ; 19 ; Signed Integer ; -; PKT_DATA_W ; 32 ; Signed Integer ; -; PKT_BYTEEN_W ; 4 ; Signed Integer ; -; PKT_SRC_ID_W ; 5 ; Signed Integer ; -; PKT_DEST_ID_W ; 5 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+----------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -; PKT_BEGIN_BURST ; 74 ; Signed Integer ; -; PKT_DATA_H ; 31 ; Signed Integer ; -; PKT_DATA_L ; 0 ; Signed Integer ; -; PKT_SYMBOL_W ; 8 ; Signed Integer ; -; PKT_BYTEEN_H ; 35 ; Signed Integer ; -; PKT_BYTEEN_L ; 32 ; Signed Integer ; -; PKT_ADDR_H ; 54 ; Signed Integer ; -; PKT_ADDR_L ; 36 ; Signed Integer ; -; PKT_TRANS_LOCK ; 59 ; Signed Integer ; -; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; -; PKT_TRANS_POSTED ; 56 ; Signed Integer ; -; PKT_TRANS_WRITE ; 57 ; Signed Integer ; -; PKT_TRANS_READ ; 58 ; Signed Integer ; -; PKT_SRC_ID_H ; 80 ; Signed Integer ; -; PKT_SRC_ID_L ; 76 ; Signed Integer ; -; PKT_DEST_ID_H ; 85 ; Signed Integer ; -; PKT_DEST_ID_L ; 81 ; Signed Integer ; -; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; -; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; -; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; -; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; -; PKT_PROTECTION_H ; 89 ; Signed Integer ; -; PKT_PROTECTION_L ; 87 ; Signed Integer ; -; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; -; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; -; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; -; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; -; ST_DATA_W ; 96 ; Signed Integer ; -; ST_CHANNEL_W ; 18 ; Signed Integer ; -; ADDR_W ; 19 ; Signed Integer ; -; AVS_DATA_W ; 32 ; Signed Integer ; -; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; -; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; -; USE_READRESPONSE ; 0 ; Signed Integer ; -; USE_WRITERESPONSE ; 0 ; Signed Integer ; -; AVS_BE_W ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -; FIFO_DATA_W ; 97 ; Signed Integer ; -+---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; ADDR_W ; 19 ; Signed Integer ; -; BURSTWRAP_W ; 3 ; Signed Integer ; -; BYTE_CNT_W ; 3 ; Signed Integer ; -; PKT_SYMBOLS ; 4 ; Signed Integer ; -; BURST_SIZE_W ; 3 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; -; BITS_PER_SYMBOL ; 97 ; Signed Integer ; -; FIFO_DEPTH ; 2 ; Signed Integer ; -; CHANNEL_WIDTH ; 0 ; Signed Integer ; -; ERROR_WIDTH ; 0 ; Signed Integer ; -; USE_PACKETS ; 1 ; Signed Integer ; -; USE_FILL_LEVEL ; 0 ; Signed Integer ; -; USE_STORE_FORWARD ; 0 ; Signed Integer ; -; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; -; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; -; EMPTY_LATENCY ; 1 ; Signed Integer ; -; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; -; DATA_WIDTH ; 97 ; Signed Integer ; -; EMPTY_WIDTH ; 0 ; Signed Integer ; -+---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 15 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 1 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 15 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 1 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 1 ; Signed Integer ; -+--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -; DEFAULT_CHANNEL ; 0 ; Signed Integer ; -; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; -; DEFAULT_DESTID ; 0 ; Signed Integer ; -+--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller ; -+-------------------------+----------+-------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+----------+-------------------------------------------------------------------+ -; NUM_RESET_INPUTS ; 2 ; Signed Integer ; -; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; -; SYNC_DEPTH ; 2 ; Signed Integer ; -; RESET_REQUEST_PRESENT ; 1 ; Signed Integer ; -+-------------------------+----------+-------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ -; ASYNC_RESET ; 1 ; Unsigned Binary ; -; DEPTH ; 2 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; -+----------------+-------------+-----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------+-----------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; round-robin ; String ; -; PIPELINE ; 1 ; Signed Integer ; -+----------------+-------------+-----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; -+----------------+-------------+---------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------------+---------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; round-robin ; String ; -; PIPELINE ; 1 ; Signed Integer ; -+----------------+-------------+---------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb ; -+----------------+--------+----------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+----------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 2 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+----------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 4 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb ; -+----------------+--------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+------------------------------------------------------------------------------------------------------------------+ -; NUM_REQUESTERS ; 18 ; Signed Integer ; -; SCHEME ; no-arb ; String ; -; PIPELINE ; 0 ; Signed Integer ; -+----------------+--------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; WIDTH ; 36 ; Signed Integer ; -+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; altsyncram Parameter Settings by Entity Instance ; -+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Name ; Value ; -+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Number of entity instances ; 4 ; -; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; DUAL_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 32 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 32 ; -; -- NUMWORDS_B ; 32 ; -; -- ADDRESS_REG_B ; CLOCK0 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; DUAL_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 32 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 32 ; -; -- NUMWORDS_B ; 32 ; -; -- ADDRESS_REG_B ; CLOCK0 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; SINGLE_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 1 ; -; -- NUMWORDS_B ; 1 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; -; -- OPERATION_MODE ; SINGLE_PORT ; -; -- WIDTH_A ; 32 ; -; -- NUMWORDS_A ; 51200 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 1 ; -; -- NUMWORDS_B ; 1 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -+-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; scfifo Parameter Settings by Entity Instance ; -+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Name ; Value ; -+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Number of entity instances ; 2 ; -; Entity Instance ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; -; -- FIFO Type ; Single Clock ; -; -- lpm_width ; 8 ; -; -- LPM_NUMWORDS ; 64 ; -; -- LPM_SHOWAHEAD ; OFF ; -; -- USE_EAB ; ON ; -; Entity Instance ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; -; -- FIFO Type ; Single Clock ; -; -- lpm_width ; 8 ; -; -- LPM_NUMWORDS ; 64 ; -; -- LPM_SHOWAHEAD ; OFF ; -; -- USE_EAB ; ON ; -+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ -; b[35..1] ; Input ; Info ; Stuck at GND ; -; b[0] ; Input ; Info ; Stuck at VCC ; -; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; b[3..1] ; Input ; Info ; Stuck at GND ; -; b[0] ; Input ; Info ; Stuck at VCC ; -; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; -+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ -; b[3..2] ; Input ; Info ; Stuck at GND ; -+---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_reset_controller:rst_controller" ; -+------------+-------+----------+-------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+-------+----------+-------------------------------------------------------+ -; reset_in2 ; Input ; Info ; Stuck at GND ; -; reset_in3 ; Input ; Info ; Stuck at GND ; -; reset_in4 ; Input ; Info ; Stuck at GND ; -; reset_in5 ; Input ; Info ; Stuck at GND ; -; reset_in6 ; Input ; Info ; Stuck at GND ; -; reset_in7 ; Input ; Info ; Stuck at GND ; -; reset_in8 ; Input ; Info ; Stuck at GND ; -; reset_in9 ; Input ; Info ; Stuck at GND ; -; reset_in10 ; Input ; Info ; Stuck at GND ; -; reset_in11 ; Input ; Info ; Stuck at GND ; -; reset_in12 ; Input ; Info ; Stuck at GND ; -; reset_in13 ; Input ; Info ; Stuck at GND ; -; reset_in14 ; Input ; Info ; Stuck at GND ; -; reset_in15 ; Input ; Info ; Stuck at GND ; -+------------+-------+----------+-------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+------------------------+--------+----------+-------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ -; default_wr_channel ; Output ; Info ; Explicitly unconnected ; -; default_rd_channel ; Output ; Info ; Explicitly unconnected ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+---------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+-------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+-------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+-------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-----------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+---------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ -; csr_address ; Input ; Info ; Stuck at GND ; -; csr_read ; Input ; Info ; Stuck at GND ; -; csr_write ; Input ; Info ; Stuck at GND ; -; csr_readdata ; Output ; Info ; Explicitly unconnected ; -; csr_writedata ; Input ; Info ; Stuck at GND ; -; almost_full_data ; Output ; Info ; Explicitly unconnected ; -; almost_empty_data ; Output ; Info ; Explicitly unconnected ; -; in_empty ; Input ; Info ; Stuck at GND ; -; out_empty ; Output ; Info ; Explicitly unconnected ; -; in_error ; Input ; Info ; Stuck at GND ; -; out_error ; Output ; Info ; Explicitly unconnected ; -; in_channel ; Input ; Info ; Stuck at GND ; -; out_channel ; Output ; Info ; Explicitly unconnected ; -+-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ -; m0_response ; Input ; Info ; Stuck at GND ; -; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" ; -+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ -; av_response ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator" ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator" ; -+--------------------------+--------+----------+-----------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-----------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-----------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" ; -+--------------------------+--------+----------+---------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------------------------+ -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator" ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; av_write ; Output ; Info ; Explicitly unconnected ; -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_writedata ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator" ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-------------------------------------------------------+ -; av_write ; Output ; Info ; Explicitly unconnected ; -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_writedata ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator" ; -+--------------------------+--------+----------+----------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+----------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+----------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" ; -+--------------------------+--------+----------+-----------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-----------------------------------------------------------------------+ -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-----------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" ; -+--------------------------+--------+----------+---------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+---------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_byteenable ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+---------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+------------------------------------------------------------+ -; av_read ; Output ; Info ; Explicitly unconnected ; -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_waitrequest ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Output ; Info ; Explicitly unconnected ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" ; -+--------------------------+--------+----------+-----------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-----------------------------------------------------------------------------+ -; av_begintransfer ; Output ; Info ; Explicitly unconnected ; -; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; -; av_burstcount ; Output ; Info ; Explicitly unconnected ; -; av_readdatavalid ; Input ; Info ; Stuck at GND ; -; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Output ; Info ; Explicitly unconnected ; -; av_chipselect ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Output ; Info ; Explicitly unconnected ; -; uav_clken ; Input ; Info ; Stuck at GND ; -; av_outputenable ; Output ; Info ; Explicitly unconnected ; -; uav_response ; Output ; Info ; Explicitly unconnected ; -; av_response ; Input ; Info ; Stuck at GND ; -; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; -; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; -+--------------------------+--------+----------+-----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" ; -+--------------------------+--------+----------+------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+------------------------------------------------------------------------+ -; av_burstcount ; Input ; Info ; Stuck at VCC ; -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_readdatavalid ; Output ; Info ; Explicitly unconnected ; -; av_lock ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+--------------------------+--------+----------+------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" ; -+--------------------------+--------+----------+-------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------------+--------+----------+-------------------------------------------------------------------------------+ -; av_burstcount ; Input ; Info ; Stuck at VCC ; -; av_byteenable ; Input ; Info ; Stuck at VCC ; -; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; -; av_begintransfer ; Input ; Info ; Stuck at GND ; -; av_chipselect ; Input ; Info ; Stuck at GND ; -; av_readdatavalid ; Output ; Info ; Explicitly unconnected ; -; av_write ; Input ; Info ; Stuck at GND ; -; av_writedata ; Input ; Info ; Stuck at GND ; -; av_lock ; Input ; Info ; Stuck at GND ; -; av_debugaccess ; Input ; Info ; Stuck at GND ; -; uav_clken ; Output ; Info ; Explicitly unconnected ; -; av_clken ; Input ; Info ; Stuck at VCC ; -; uav_response ; Input ; Info ; Stuck at GND ; -; av_response ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponserequest ; Output ; Info ; Explicitly unconnected ; -; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; -; av_writeresponserequest ; Input ; Info ; Stuck at GND ; -; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; -+--------------------------+--------+----------+-------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" ; -+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ -; raw_tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; tdi ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; rti ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; shift ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; update ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; usr1 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; clr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; ir_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; tdo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; irq ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; ir_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_sdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -; jtag_state_udr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; -+----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" ; -+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ -; dataavailable ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; readyfordata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; virtual_state_e1dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; virtual_state_pdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; virtual_state_e2dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; virtual_state_cir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; tms ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_tlr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sdrs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e1dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_pdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e2dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_udr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sirs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_cir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_sir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e1ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_pir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_e2ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -; jtag_state_uir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; -+--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4" ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_n ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; reset_n ; Input ; Info ; Stuck at VCC ; -+---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" ; -+---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; clkx2 ; Input ; Info ; Stuck at GND ; -; tr_clk ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; tr_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; fifowp_inc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; td_mode ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; jdo ; Input ; Warning ; Input port expression (38 bits) is wider than the input port (16 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; -+------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; dbrk_trigout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; xbrk_trigout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; debugreq ; Input ; Info ; Stuck at GND ; -+----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ -; oci_ienable[31..6] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; oci_ienable[4..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" ; -+-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ -; F_pcb[1..0] ; Input ; Info ; Stuck at GND ; -; i_address[1..0] ; Input ; Info ; Stuck at GND ; -+-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" ; -+--------------+--------+----------+---------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------------+--------+----------+---------------------------------------------------------+ -; no_ci_readra ; Output ; Info ; Explicitly unconnected ; -+--------------+--------+----------+---------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "nios_system:NiosII" ; -+------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ -; lcd_16207_0_data ; Bidir ; Critical Warning ; Port on prototype, e.g. VHDL component, declared as "Output" but port on entity declared as "Bidir" ; -+------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ - - -+---------------------------------+ -; Elapsed Time Per Partition ; -+------------------+--------------+ -; Partition Name ; Elapsed Time ; -+------------------+--------------+ -; Top ; 00:00:07 ; -; sld_hub:auto_hub ; 00:00:00 ; -+------------------+--------------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit Analysis & Synthesis - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Dec 02 01:32:07 2016 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (12248): Elaborating Qsys system entity "nios_system.qsys" -Info (12250): 2016.12.02.01:32:09 Progress: Loading qsys_tutorial/nios_system.qsys -Info (12250): 2016.12.02.01:32:09 Progress: Reading input file -Info (12250): 2016.12.02.01:32:09 Progress: Adding clk_0 [clock_source 13.0] -Info (12250): 2016.12.02.01:32:09 Progress: Parameterizing module clk_0 -Info (12250): 2016.12.02.01:32:09 Progress: Adding nios2_processor [altera_nios2_qsys 13.0] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module nios2_processor -Info (12250): 2016.12.02.01:32:10 Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module onchip_memory -Info (12250): 2016.12.02.01:32:10 Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module jtag_uart -Info (12250): 2016.12.02.01:32:10 Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module LEDs -Info (12250): 2016.12.02.01:32:10 Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module LEDRs -Info (12250): 2016.12.02.01:32:10 Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module switches -Info (12250): 2016.12.02.01:32:10 Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module push_switches -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex0 -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex1 -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex2 -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex3 -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex4 -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex5 -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex6 -Info (12250): 2016.12.02.01:32:10 Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module hex7 -Info (12250): 2016.12.02.01:32:10 Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module lcd_16207_0 -Info (12250): 2016.12.02.01:32:10 Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module lcd_on -Info (12250): 2016.12.02.01:32:10 Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing module lcd_blon -Info (12250): 2016.12.02.01:32:10 Progress: Building connections -Info (12250): 2016.12.02.01:32:10 Progress: Parameterizing connections -Info (12250): 2016.12.02.01:32:10 Progress: Validating -Info (12250): 2016.12.02.01:32:11 Progress: Done reading input file -Info (12250): Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info (12250): Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. -Info (12250): Nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH -Info (12250): Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections -Info (12250): No custom instruction connections, skipping transform -Info (12250): Merlin_translator_transform: After transform: 39 modules, 155 connections -Info (12250): Merlin_domain_transform: After transform: 78 modules, 423 connections -Info (12250): Merlin_router_transform: After transform: 98 modules, 503 connections -Info (12250): Reset_adaptation_transform: After transform: 99 modules, 390 connections -Info (12250): Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections -Info (12250): Merlin_mm_transform: After transform: 138 modules, 470 connections -Info (12250): Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" -Info (12250): Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' -Info (12250): Nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) Starting Nios II generation -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) Checking for plaintext license. -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) Defaulting to contents of LM_LICENSE_FILE environment variable -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) LM_LICENSE_FILE environment variable is empty -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) Plaintext license not found. -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) No license required to generate encrypted Nios II/e. -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) Elaborating CPU configuration settings -Info (12250): Nios2_processor: # 2016.12.02 01:32:17 (*) Creating all objects for CPU -Info (12250): Nios2_processor: # 2016.12.02 01:32:18 (*) Generating RTL from CPU objects -Info (12250): Nios2_processor: # 2016.12.02 01:32:18 (*) Creating plain-text RTL -Info (12250): Nios2_processor: # 2016.12.02 01:32:20 (*) Done Nios II generation -Info (12250): Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' -Info (12250): Nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" -Info (12250): Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' -Info (12250): Onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] -Info (12250): Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' -Info (12250): Onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" -Info (12250): Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' -Info (12250): Jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] -Info (12250): Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' -Info (12250): Jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" -Info (12250): LEDs: Starting RTL generation for module 'nios_system_LEDs' -Info (12250): LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] -Info (12250): LEDs: Done RTL generation for module 'nios_system_LEDs' -Info (12250): LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" -Info (12250): LEDRs: Starting RTL generation for module 'nios_system_LEDRs' -Info (12250): LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] -Info (12250): LEDRs: Done RTL generation for module 'nios_system_LEDRs' -Info (12250): LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" -Info (12250): Switches: Starting RTL generation for module 'nios_system_switches' -Info (12250): Switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] -Info (12250): Switches: Done RTL generation for module 'nios_system_switches' -Info (12250): Switches: "nios_system" instantiated altera_avalon_pio "switches" -Info (12250): Push_switches: Starting RTL generation for module 'nios_system_push_switches' -Info (12250): Push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] -Info (12250): Push_switches: Done RTL generation for module 'nios_system_push_switches' -Info (12250): Push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" -Info (12250): Hex0: Starting RTL generation for module 'nios_system_hex0' -Info (12250): Hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] -Info (12250): Hex0: Done RTL generation for module 'nios_system_hex0' -Info (12250): Hex0: "nios_system" instantiated altera_avalon_pio "hex0" -Info (12250): Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' -Info (12250): Lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] -Info (12250): Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' -Info (12250): Lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" -Info (12250): Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' -Info (12250): Lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7136_6175737974426620063.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] -Info (12250): Lcd_on: Done RTL generation for module 'nios_system_lcd_on' -Info (12250): Lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" -Info (12250): Nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" -Info (12250): Nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" -Info (12250): Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info (12250): Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info (12250): Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info (12250): Addr_router: "nios_system" instantiated altera_merlin_router "addr_router" -Info (12250): Addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" -Info (12250): Id_router: "nios_system" instantiated altera_merlin_router "id_router" -Info (12250): Id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" -Info (12250): Rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" -Info (12250): Cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" -Info (12250): Cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" -Info (12250): Cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" -Info (12250): Rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" -Info (12250): Rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" -Info (12250): Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv -Info (12250): Rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" -Info (12250): Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv -Info (12250): Irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" -Info (12250): Nios_system: Done nios_system" with 28 modules, 155 files, 4086283 bytes -Info (12249): Finished elaborating Qsys system entity "nios_system.qsys" -Info (12021): Found 2 design units, including 1 entities, in source file lights.vhd - Info (12022): Found design unit 1: lights-lights_rtl - Info (12023): Found entity 1: lights -Info (12021): Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v - Info (12023): Found entity 1: nios_system -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v - Info (12023): Found entity 1: nios_system -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v - Info (12023): Found entity 1: altera_avalon_sc_fifo -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv - Info (12023): Found entity 1: altera_merlin_arbitrator - Info (12023): Found entity 2: altera_merlin_arb_adder -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv - Info (12023): Found entity 1: altera_merlin_burst_uncompressor -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv - Info (12023): Found entity 1: altera_merlin_master_agent -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv - Info (12023): Found entity 1: altera_merlin_master_translator -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv - Info (12023): Found entity 1: altera_merlin_slave_agent -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv - Info (12023): Found entity 1: altera_merlin_slave_translator -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v - Info (12023): Found entity 1: altera_reset_controller -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v - Info (12023): Found entity 1: altera_reset_synchronizer -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v - Info (12023): Found entity 1: nios_system_LEDRs -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v - Info (12023): Found entity 1: nios_system_LEDs -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv - Info (12023): Found entity 1: nios_system_addr_router_default_decode - Info (12023): Found entity 2: nios_system_addr_router -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv - Info (12023): Found entity 1: nios_system_addr_router_001_default_decode - Info (12023): Found entity 2: nios_system_addr_router_001 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv - Info (12023): Found entity 1: nios_system_cmd_xbar_demux -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv - Info (12023): Found entity 1: nios_system_cmd_xbar_demux_001 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv - Info (12023): Found entity 1: nios_system_cmd_xbar_mux -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v - Info (12023): Found entity 1: nios_system_hex0 -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv - Info (12023): Found entity 1: nios_system_id_router_default_decode - Info (12023): Found entity 2: nios_system_id_router -Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv - Info (12023): Found entity 1: nios_system_id_router_002_default_decode - Info (12023): Found entity 2: nios_system_id_router_002 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv - Info (12023): Found entity 1: nios_system_irq_mapper -Info (12021): Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v - Info (12023): Found entity 1: nios_system_jtag_uart_sim_scfifo_w - Info (12023): Found entity 2: nios_system_jtag_uart_scfifo_w - Info (12023): Found entity 3: nios_system_jtag_uart_sim_scfifo_r - Info (12023): Found entity 4: nios_system_jtag_uart_scfifo_r - Info (12023): Found entity 5: nios_system_jtag_uart -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v - Info (12023): Found entity 1: nios_system_lcd_16207_0 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v - Info (12023): Found entity 1: nios_system_lcd_on -Info (12021): Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v - Info (12023): Found entity 1: nios_system_nios2_processor_register_bank_a_module - Info (12023): Found entity 2: nios_system_nios2_processor_register_bank_b_module - Info (12023): Found entity 3: nios_system_nios2_processor_nios2_oci_debug - Info (12023): Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module - Info (12023): Found entity 5: nios_system_nios2_processor_nios2_ocimem - Info (12023): Found entity 6: nios_system_nios2_processor_nios2_avalon_reg - Info (12023): Found entity 7: nios_system_nios2_processor_nios2_oci_break - Info (12023): Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk - Info (12023): Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk - Info (12023): Found entity 10: nios_system_nios2_processor_nios2_oci_itrace - Info (12023): Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode - Info (12023): Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace - Info (12023): Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count - Info (12023): Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc - Info (12023): Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc - Info (12023): Found entity 16: nios_system_nios2_processor_nios2_oci_fifo - Info (12023): Found entity 17: nios_system_nios2_processor_nios2_oci_pib - Info (12023): Found entity 18: nios_system_nios2_processor_nios2_oci_im - Info (12023): Found entity 19: nios_system_nios2_processor_nios2_performance_monitors - Info (12023): Found entity 20: nios_system_nios2_processor_nios2_oci - Info (12023): Found entity 21: nios_system_nios2_processor -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v - Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v - Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v - Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v - Info (12023): Found entity 1: nios_system_nios2_processor_oci_test_bench -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v - Info (12023): Found entity 1: nios_system_nios2_processor_test_bench -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v - Info (12023): Found entity 1: nios_system_onchip_memory -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v - Info (12023): Found entity 1: nios_system_push_switches -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv - Info (12023): Found entity 1: nios_system_rsp_xbar_demux_002 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv - Info (12023): Found entity 1: nios_system_rsp_xbar_mux -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv - Info (12023): Found entity 1: nios_system_rsp_xbar_mux_001 -Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v - Info (12023): Found entity 1: nios_system_switches -Info (12127): Elaborating entity "lights" for the top level hierarchy -Info (12128): Elaborating entity "nios_system" for hierarchy "nios_system:NiosII" -Info (12128): Elaborating entity "nios_system_nios2_processor" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" -Info (12128): Elaborating entity "nios_system_nios2_processor_test_bench" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" -Info (12128): Elaborating entity "nios_system_nios2_processor_register_bank_a_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "address_reg_b" = "CLOCK0" - Info (12134): Parameter "init_file" = "nios_system_nios2_processor_rf_ram_a.mif" - Info (12134): Parameter "maximum_depth" = "0" - Info (12134): Parameter "numwords_a" = "32" - Info (12134): Parameter "numwords_b" = "32" - Info (12134): Parameter "operation_mode" = "DUAL_PORT" - Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" - Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_b" = "32" - Info (12134): Parameter "widthad_a" = "5" - Info (12134): Parameter "widthad_b" = "5" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf - Info (12023): Found entity 1: altsyncram_0rh1 -Info (12128): Elaborating entity "altsyncram_0rh1" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated" -Info (12128): Elaborating entity "nios_system_nios2_processor_register_bank_b_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "address_reg_b" = "CLOCK0" - Info (12134): Parameter "init_file" = "nios_system_nios2_processor_rf_ram_b.mif" - Info (12134): Parameter "maximum_depth" = "0" - Info (12134): Parameter "numwords_a" = "32" - Info (12134): Parameter "numwords_b" = "32" - Info (12134): Parameter "operation_mode" = "DUAL_PORT" - Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" - Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_b" = "32" - Info (12134): Parameter "widthad_a" = "5" - Info (12134): Parameter "widthad_b" = "5" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf - Info (12023): Found entity 1: altsyncram_1rh1 -Info (12128): Elaborating entity "altsyncram_1rh1" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_debug" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" -Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: - Info (12134): Parameter "depth" = "2" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_ocimem" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem" -Info (12128): Elaborating entity "nios_system_nios2_processor_ociram_sp_ram_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "init_file" = "nios_system_nios2_processor_ociram_default_contents.mif" - Info (12134): Parameter "maximum_depth" = "0" - Info (12134): Parameter "numwords_a" = "256" - Info (12134): Parameter "operation_mode" = "SINGLE_PORT" - Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_byteena_a" = "4" - Info (12134): Parameter "widthad_a" = "8" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf - Info (12023): Found entity 1: altsyncram_4891 -Info (12128): Elaborating entity "altsyncram_4891" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_avalon_reg" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_break" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_xbrk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_dbrk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_itrace" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_dtrace" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_td_mode" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifo" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_compute_tm_count" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifowp_inc" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifocount_inc" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" -Info (12128): Elaborating entity "nios_system_nios2_processor_oci_test_bench" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_pib" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" -Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_im" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im" -Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_wrapper" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper" -Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_tck" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck" -Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_sysclk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk" -Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" with the following parameter: - Info (12134): Parameter "sld_auto_instance_index" = "YES" - Info (12134): Parameter "sld_instance_index" = "0" - Info (12134): Parameter "sld_ir_width" = "2" - Info (12134): Parameter "sld_mfg_id" = "70" - Info (12134): Parameter "sld_sim_action" = "" - Info (12134): Parameter "sld_sim_n_scan" = "0" - Info (12134): Parameter "sld_sim_total_length" = "0" - Info (12134): Parameter "sld_type_id" = "34" - Info (12134): Parameter "sld_version" = "3" -Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" -Info (12131): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" -Info (12128): Elaborating entity "nios_system_onchip_memory" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory" -Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" with the following parameter: - Info (12134): Parameter "byte_size" = "8" - Info (12134): Parameter "init_file" = "nios_system_onchip_memory.hex" - Info (12134): Parameter "lpm_type" = "altsyncram" - Info (12134): Parameter "maximum_depth" = "51200" - Info (12134): Parameter "numwords_a" = "51200" - Info (12134): Parameter "operation_mode" = "SINGLE_PORT" - Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" - Info (12134): Parameter "ram_block_type" = "AUTO" - Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" - Info (12134): Parameter "width_a" = "32" - Info (12134): Parameter "width_byteena_a" = "4" - Info (12134): Parameter "widthad_a" = "16" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf - Info (12023): Found entity 1: altsyncram_4ed1 -Info (12128): Elaborating entity "altsyncram_4ed1" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated" -Info (12021): Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf - Info (12023): Found entity 1: decode_qsa -Info (12128): Elaborating entity "decode_qsa" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3" -Info (12021): Found 1 design units, including 1 entities, in source file db/mux_nob.tdf - Info (12023): Found entity 1: mux_nob -Info (12128): Elaborating entity "mux_nob" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2" -Info (12128): Elaborating entity "nios_system_jtag_uart" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" -Info (12128): Elaborating entity "nios_system_jtag_uart_scfifo_w" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w" -Info (12128): Elaborating entity "scfifo" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" with the following parameter: - Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO" - Info (12134): Parameter "lpm_numwords" = "64" - Info (12134): Parameter "lpm_showahead" = "OFF" - Info (12134): Parameter "lpm_type" = "scfifo" - Info (12134): Parameter "lpm_width" = "8" - Info (12134): Parameter "lpm_widthu" = "6" - Info (12134): Parameter "overflow_checking" = "OFF" - Info (12134): Parameter "underflow_checking" = "OFF" - Info (12134): Parameter "use_eab" = "ON" -Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf - Info (12023): Found entity 1: scfifo_jr21 -Info (12128): Elaborating entity "scfifo_jr21" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated" -Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf - Info (12023): Found entity 1: a_dpfifo_q131 -Info (12128): Elaborating entity "a_dpfifo_q131" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo" -Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf - Info (12023): Found entity 1: a_fefifo_7cf -Info (12128): Elaborating entity "a_fefifo_7cf" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state" -Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf - Info (12023): Found entity 1: cntr_do7 -Info (12128): Elaborating entity "cntr_do7" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw" -Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf - Info (12023): Found entity 1: dpram_nl21 -Info (12128): Elaborating entity "dpram_nl21" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf - Info (12023): Found entity 1: altsyncram_r1m1 -Info (12128): Elaborating entity "altsyncram_r1m1" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1" -Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf - Info (12023): Found entity 1: cntr_1ob -Info (12128): Elaborating entity "cntr_1ob" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count" -Info (12128): Elaborating entity "nios_system_jtag_uart_scfifo_r" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r" -Info (12128): Elaborating entity "alt_jtag_atlantic" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" -Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" -Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" with the following parameter: - Info (12134): Parameter "INSTANCE_ID" = "0" - Info (12134): Parameter "LOG2_RXFIFO_DEPTH" = "6" - Info (12134): Parameter "LOG2_TXFIFO_DEPTH" = "6" - Info (12134): Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES" -Info (12128): Elaborating entity "nios_system_LEDs" for hierarchy "nios_system:NiosII|nios_system_LEDs:leds" -Info (12128): Elaborating entity "nios_system_LEDRs" for hierarchy "nios_system:NiosII|nios_system_LEDRs:ledrs" -Info (12128): Elaborating entity "nios_system_switches" for hierarchy "nios_system:NiosII|nios_system_switches:switches" -Info (12128): Elaborating entity "nios_system_push_switches" for hierarchy "nios_system:NiosII|nios_system_push_switches:push_switches" -Info (12128): Elaborating entity "nios_system_hex0" for hierarchy "nios_system:NiosII|nios_system_hex0:hex0" -Info (12128): Elaborating entity "nios_system_lcd_16207_0" for hierarchy "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0" -Info (12128): Elaborating entity "nios_system_lcd_on" for hierarchy "nios_system:NiosII|nios_system_lcd_on:lcd_on" -Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" -Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" -Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" -Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" -Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" -Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" -Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" -Info (12128): Elaborating entity "nios_system_addr_router" for hierarchy "nios_system:NiosII|nios_system_addr_router:addr_router" -Info (12128): Elaborating entity "nios_system_addr_router_default_decode" for hierarchy "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" -Info (12128): Elaborating entity "nios_system_addr_router_001" for hierarchy "nios_system:NiosII|nios_system_addr_router_001:addr_router_001" -Info (12128): Elaborating entity "nios_system_addr_router_001_default_decode" for hierarchy "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" -Info (12128): Elaborating entity "nios_system_id_router" for hierarchy "nios_system:NiosII|nios_system_id_router:id_router" -Info (12128): Elaborating entity "nios_system_id_router_default_decode" for hierarchy "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" -Info (12128): Elaborating entity "nios_system_id_router_002" for hierarchy "nios_system:NiosII|nios_system_id_router_002:id_router_002" -Info (12128): Elaborating entity "nios_system_id_router_002_default_decode" for hierarchy "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" -Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "nios_system:NiosII|altera_reset_controller:rst_controller" -Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" -Info (12128): Elaborating entity "nios_system_cmd_xbar_demux" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux" -Info (12128): Elaborating entity "nios_system_cmd_xbar_demux_001" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001" -Info (12128): Elaborating entity "nios_system_cmd_xbar_mux" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux" -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb" -Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -Info (12128): Elaborating entity "nios_system_rsp_xbar_demux_002" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002" -Info (12128): Elaborating entity "nios_system_rsp_xbar_mux" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux" -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb" -Info (12128): Elaborating entity "nios_system_rsp_xbar_mux_001" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001" -Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb" -Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -Info (12128): Elaborating entity "nios_system_irq_mapper" for hierarchy "nios_system:NiosII|nios_system_irq_mapper:irq_mapper" -Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder -Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[0]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[0]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[1]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[1]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[2]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[2]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[3]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[3]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[4]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[4]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[5]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[5]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[6]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[6]" into an OR gate - Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[7]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[7]" into an OR gate -Info (13000): Registers with preset signals will power-up high -Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back -Info (286031): Timing-Driven Synthesis is running on partition "Top" -Info (17049): 166 registers lost all their fanouts during netlist optimizations. -Info (13000): Registers with preset signals will power-up high -Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back -Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "sld_hub:auto_hub|receive[0][0]" is stuck at GND -Info (286031): Timing-Driven Synthesis is running on partition "sld_hub:auto_hub" -Info (144001): Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg -Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" - Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 2881 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 26 input pins - Info (21059): Implemented 96 output pins - Info (21061): Implemented 2422 logic cells - Info (21064): Implemented 336 RAM segments -Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 149 warnings - Info: Peak virtual memory: 654 megabytes - Info: Processing ended: Fri Dec 02 01:32:41 2016 - Info: Elapsed time: 00:00:34 - Info: Total CPU time (on all processors): 00:00:33 - - -+------------------------------------------+ -; Analysis & Synthesis Suppressed Messages ; -+------------------------------------------+ -The suppressed messages can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg. - - +Analysis & Synthesis report for lights +Thu Dec 22 10:07:53 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize + 10. Registers Protected by Synthesis + 11. Registers Removed During Synthesis + 12. Removed Registers Triggering Further Register Optimizations + 13. General Register Statistics + 14. Inverted Register Statistics + 15. Multiplexer Restructuring Statistics (Restructuring Performed) + 16. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated + 17. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated + 18. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer + 19. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated + 20. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 + 21. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 + 22. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 + 23. Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 + 24. Source assignments for nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated + 25. Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 + 26. Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 + 27. Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller + 28. Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 + 29. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux + 30. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 + 31. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux + 32. Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 + 33. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 + 34. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 + 35. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 + 36. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 + 37. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 + 38. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 + 39. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 + 40. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 + 41. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 + 42. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 + 43. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 + 44. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 + 45. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 + 46. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 + 47. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 + 48. Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 + 49. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a + 50. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram + 51. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b + 52. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram + 53. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer + 54. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram + 55. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram + 56. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 + 57. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 + 58. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 + 59. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 + 60. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy + 61. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory + 62. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram + 63. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo + 64. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo + 65. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator + 66. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator + 67. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator + 68. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator + 69. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator + 70. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator + 71. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator + 72. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator + 73. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator + 74. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator + 75. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator + 76. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator + 77. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator + 78. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator + 79. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator + 80. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator + 81. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator + 82. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator + 83. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator + 84. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator + 85. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent + 86. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent + 87. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent + 88. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 89. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo + 90. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent + 91. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 92. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 93. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent + 94. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 95. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 96. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent + 97. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 98. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo + 99. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent +100. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +101. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +102. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent +103. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +104. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +105. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent +106. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +107. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +108. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent +109. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +110. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +111. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent +112. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +113. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +114. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent +115. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +116. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +117. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent +118. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +119. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +120. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent +121. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +122. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +123. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent +124. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +125. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +126. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent +127. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +128. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +129. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent +130. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +131. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +132. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent +133. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +134. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo +135. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent +136. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +137. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +138. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent +139. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +140. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +141. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode +142. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode +143. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode +144. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode +145. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode +146. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode +147. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode +148. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode +149. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode +150. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode +151. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode +152. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode +153. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode +154. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode +155. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode +156. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode +157. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode +158. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode +159. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode +160. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode +161. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller +162. Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 +163. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb +164. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +165. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb +166. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +167. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb +168. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +169. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb +170. Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +171. altsyncram Parameter Settings by Entity Instance +172. scfifo Parameter Settings by Entity Instance +173. Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +174. Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +175. Port Connectivity Checks: "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +176. Port Connectivity Checks: "nios_system:NiosII|altera_reset_controller:rst_controller" +177. Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" +178. Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" +179. Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" +180. Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" +181. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +182. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent" +183. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +184. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent" +185. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" +186. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent" +187. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +188. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent" +189. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +190. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent" +191. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +192. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent" +193. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +194. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent" +195. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +196. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent" +197. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +198. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent" +199. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +200. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent" +201. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +202. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent" +203. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +204. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent" +205. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +206. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent" +207. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +208. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent" +209. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" +210. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent" +211. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +212. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent" +213. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +214. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent" +215. Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +216. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" +217. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" +218. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" +219. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator" +220. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator" +221. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" +222. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator" +223. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator" +224. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator" +225. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator" +226. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator" +227. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator" +228. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator" +229. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator" +230. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator" +231. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator" +232. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator" +233. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" +234. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" +235. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" +236. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" +237. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" +238. Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" +239. Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" +240. Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" +241. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" +242. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4" +243. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" +244. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" +245. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" +246. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" +247. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" +248. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" +249. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" +250. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" +251. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" +252. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" +253. Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" +254. Port Connectivity Checks: "nios_system:NiosII" +255. Elapsed Time Per Partition +256. Analysis & Synthesis Messages +257. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Dec 22 10:07:53 2016 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; lights ; +; Top-level Entity Name ; lights ; +; Family ; Cyclone IV E ; +; Total logic elements ; 2,331 ; +; Total combinational functions ; 2,056 ; +; Dedicated logic registers ; 1,212 ; +; Total registers ; 1212 ; +; Total pins ; 118 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 1,649,664 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE115F29C7 ; ; +; Top-level entity name ; lights ; lights ; +; Family name ; Cyclone IV E ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +; lights.vhd ; yes ; User VHDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/lights.vhd ; ; +; nios_system/synthesis/nios_system.v ; yes ; User Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system/synthesis/nios_system.v ; ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_avalon_sc_fifo.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_agent.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_master_translator.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_agent.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_slave_translator.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_controller.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_reset_synchronizer.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDRs.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_LEDs.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_addr_router_001.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_hex0.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_id_router_002.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_irq_mapper.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_jtag_uart.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_16207_0.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_lcd_on.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_onchip_memory.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_push_switches.v ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv ; altera_reserved_qsys_nios_system ; +; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v ; yes ; Auto-Found Verilog HDL File ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/nios_system_switches.v ; altera_reserved_qsys_nios_system ; +; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_0rh1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_0rh1.tdf ; ; +; db/altsyncram_1rh1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_1rh1.tdf ; ; +; altera_std_synchronizer.v ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; +; db/altsyncram_4891.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4891.tdf ; ; +; sld_virtual_jtag_basic.v ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v ; ; +; db/altsyncram_4ed1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_4ed1.tdf ; ; +; db/decode_qsa.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/decode_qsa.tdf ; ; +; db/mux_nob.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/mux_nob.tdf ; ; +; scfifo.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf ; ; +; a_regfifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_regfifo.inc ; ; +; a_dpfifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_dpfifo.inc ; ; +; a_i2fifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_i2fifo.inc ; ; +; a_fffifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_fffifo.inc ; ; +; a_f2fifo.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_f2fifo.inc ; ; +; db/scfifo_jr21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/scfifo_jr21.tdf ; ; +; db/a_dpfifo_q131.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_dpfifo_q131.tdf ; ; +; db/a_fefifo_7cf.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/a_fefifo_7cf.tdf ; ; +; db/cntr_do7.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_do7.tdf ; ; +; db/dpram_nl21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/dpram_nl21.tdf ; ; +; db/altsyncram_r1m1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/altsyncram_r1m1.tdf ; ; +; db/cntr_1ob.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/cntr_1ob.tdf ; ; +; alt_jtag_atlantic.v ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v ; ; +; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_hub.vhd ; ; +; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ; +; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ; ++---------------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimated Total logic elements ; 2,331 ; +; ; ; +; Total combinational functions ; 2056 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 1077 ; +; -- 3 input functions ; 678 ; +; -- <=2 input functions ; 301 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 1909 ; +; -- arithmetic mode ; 147 ; +; ; ; +; Total registers ; 1212 ; +; -- Dedicated logic registers ; 1212 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 118 ; +; Total memory bits ; 1649664 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; CLOCK_50~input ; +; Maximum fan-out ; 1365 ; +; Total fan-out ; 16737 ; +; Average fan-out ; 4.35 ; ++---------------------------------------------+----------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +; |lights ; 2056 (1) ; 1212 (0) ; 1649664 ; 0 ; 0 ; 0 ; 118 ; 0 ; |lights ; work ; +; |nios_system:NiosII| ; 1897 (0) ; 1115 (0) ; 1649664 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII ; work ; +; |altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 8 (8) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_translator:nios2_processor_data_master_translator| ; 9 (9) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_master_translator:nios2_processor_instruction_master_translator| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex0_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex1_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex2_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex3_s1_translator| ; 5 (5) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex4_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex5_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex6_s1_translator| ; 5 (5) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:hex7_s1_translator| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator| ; 9 (9) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:lcd_16207_0_control_slave_translator| ; 14 (14) ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:lcd_blon_s1_translator| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:lcd_on_s1_translator| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:ledrs_s1_translator| ; 6 (6) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:leds_s1_translator| ; 5 (5) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator| ; 1 (1) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:onchip_memory_s1_translator| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:push_switches_s1_translator| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_merlin_slave_translator:switches_s1_translator| ; 6 (6) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; altera_reserved_qsys_nios_system ; +; |altera_reset_controller:rst_controller| ; 2 (2) ; 9 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller ; altera_reserved_qsys_nios_system ; +; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reserved_qsys_nios_system ; +; |nios_system_LEDRs:ledrs| ; 20 (20) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_LEDRs:ledrs ; altera_reserved_qsys_nios_system ; +; |nios_system_LEDs:leds| ; 11 (11) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_LEDs:leds ; altera_reserved_qsys_nios_system ; +; |nios_system_addr_router:addr_router| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_addr_router:addr_router ; altera_reserved_qsys_nios_system ; +; |nios_system_addr_router_001:addr_router_001| ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_addr_router_001:addr_router_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux:cmd_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_mux:cmd_xbar_mux_001| ; 60 (56) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001 ; altera_reserved_qsys_nios_system ; +; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; +; |nios_system_cmd_xbar_mux:cmd_xbar_mux| ; 54 (50) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux ; altera_reserved_qsys_nios_system ; +; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex0| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex0 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex1| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex1 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex2| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex2 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex3| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex3 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex4| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex4 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex5| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex5 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex6| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex6 ; altera_reserved_qsys_nios_system ; +; |nios_system_hex0:hex7| ; 9 (9) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_hex0:hex7 ; altera_reserved_qsys_nios_system ; +; |nios_system_jtag_uart:jtag_uart| ; 140 (36) ; 112 (13) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart ; altera_reserved_qsys_nios_system ; +; |alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic| ; 53 (53) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic ; work ; +; |nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r ; altera_reserved_qsys_nios_system ; +; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; work ; +; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; work ; +; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; +; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; +; |nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w ; altera_reserved_qsys_nios_system ; +; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; work ; +; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; work ; +; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; work ; +; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; work ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; work ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; work ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; work ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; work ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; work ; +; |nios_system_lcd_16207_0:lcd_16207_0| ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0 ; altera_reserved_qsys_nios_system ; +; |nios_system_lcd_on:lcd_blon| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_blon ; altera_reserved_qsys_nios_system ; +; |nios_system_lcd_on:lcd_on| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_lcd_on:lcd_on ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor:nios2_processor| ; 929 (643) ; 576 (306) ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci| ; 286 (34) ; 269 (80) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper| ; 92 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk| ; 6 (6) ; 49 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk ; altera_reserved_qsys_nios_system ; +; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer4| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; work ; +; |nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck| ; 82 (82) ; 47 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck ; altera_reserved_qsys_nios_system ; +; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; work ; +; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; work ; +; |sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; work ; +; |nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg| ; 8 (8) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug| ; 9 (8) ; 9 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug ; altera_reserved_qsys_nios_system ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 1 (1) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; work ; +; |nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem| ; 111 (111) ; 49 (49) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem ; altera_reserved_qsys_nios_system ; +; |nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; work ; +; |altsyncram_4891:auto_generated| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; work ; +; |nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; work ; +; |altsyncram_0rh1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; work ; +; |nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; work ; +; |altsyncram_1rh1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; work ; +; |nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench ; altera_reserved_qsys_nios_system ; +; |nios_system_onchip_memory:onchip_memory| ; 168 (1) ; 3 (0) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; altera_reserved_qsys_nios_system ; +; |altsyncram:the_altsyncram| ; 167 (0) ; 3 (0) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; work ; +; |altsyncram_4ed1:auto_generated| ; 167 (0) ; 3 (3) ; 1638400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; work ; +; |decode_qsa:decode3| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3 ; work ; +; |mux_nob:mux2| ; 160 (160) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2 ; work ; +; |nios_system_push_switches:push_switches| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_push_switches:push_switches ; altera_reserved_qsys_nios_system ; +; |nios_system_rsp_xbar_mux:rsp_xbar_mux| ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux ; altera_reserved_qsys_nios_system ; +; |nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; altera_reserved_qsys_nios_system ; +; |nios_system_switches:switches| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|nios_system:NiosII|nios_system_switches:switches ; altera_reserved_qsys_nios_system ; +; |sld_hub:auto_hub| ; 158 (1) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub ; work ; +; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 157 (115) ; 97 (69) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; work ; +; |sld_rom_sr:hub_info_reg| ; 25 (25) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; work ; +; |sld_shadow_jsm:shadow_jsm| ; 17 (17) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; work ; ++--------------------------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256 ; 32 ; -- ; -- ; 8192 ; nios_system_nios2_processor_ociram_default_contents.mif ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; nios_system_nios2_processor_rf_ram_a.mif ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; nios_system_nios2_processor_rf_ram_b.mif ; +; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 51200 ; 32 ; -- ; -- ; 1638400 ; nios_system_onchip_memory.hex ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+---------------------------------------------------------+ + + +Encoding Type: One-Hot ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize ; ++------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Name ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000 ; ++------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DRsize.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DRsize.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; DRsize.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; DRsize.011 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; DRsize.100 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; DRsize.101 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++------------+------------+------------+------------+------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Protected by Synthesis ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rvalid ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; yes ; yes ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[7] ; yes ; yes ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; yes ; yes ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|dreg[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[1] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4|din_s1 ; yes ; yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[2] ; yes ; yes ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[3] ; yes ; yes ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[4] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[5] ; yes ; yes ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rdata[6] ; yes ; yes ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|locked[0,1] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|locked[0,1] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|av_readdata_pre[18..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|av_readdata_pre[11,23..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|av_readdata_pre[8..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[3..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_switches:switches|readdata[18..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[0..4,6..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ipending_reg[0..4,6..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|R_ctrl_custom ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im|trc_im_addr[0..6] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im|trc_wrap ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto0 ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk|xbrk_break ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[3..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[18..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[1..4,6..31] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][76] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Lost fanout ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][76] ; Lost fanout ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst1 ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|waitrequest_reset_override ; +; nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|waitrequest_reset_override ; Merged with nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; +; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; Merged with nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[22] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[23] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[23] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[24] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[24] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[25] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[25] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[7] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[7] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[27] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[27] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[28] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[28] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[29] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[29] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[30] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[30] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[31] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[31] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[0] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[0] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[1] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[1] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[2] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[2] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[3] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[3] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[4] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[4] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[6] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[6] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[8] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[8] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[9] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[9] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[10] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[10] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[11] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[11] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[12] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[12] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[13] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[13] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[14] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[14] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[15] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[15] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[26] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[26] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[16] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[16] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[17] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[17] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[18] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[18] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[19] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[19] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[20] ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[20] ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[21] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][77] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][78] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][79] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][80] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][61] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Merged with nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigger_state ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigbrktype ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_reset_controller:rst_controller|r_early_rst ; Merged with nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; Stuck at GND due to stuck port data_in ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|share_count[0] ; Lost fanout ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|share_count[0] ; Lost fanout ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~3 ; Lost fanout ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~4 ; Lost fanout ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~5 ; Lost fanout ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.101 ; Lost fanout ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.011 ; Merged with nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.001 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.001 ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 975 ; ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_break, ; +; ; due to stuck port data_in ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigbrktype ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][80] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55], ; +; ; due to stuck port data_in ; nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[12] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[12] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[11] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[11] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[10] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[10] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[9] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[9] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[8] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[8] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[7] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[7] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[6] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[6] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[5] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[5] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[4] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[4] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[3] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[3] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[31] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[31] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[30] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[30] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[29] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[29] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[28] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[28] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[27] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[27] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[26] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[26] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[25] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[25] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[24] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[24] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[23] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[23] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[22] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[22] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[21] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[21] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[20] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[20] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[19] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[19] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_switches:switches|readdata[18] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|av_readdata_pre[18] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[31] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[31] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[30] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[30] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[29] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[29] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[28] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[28] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[27] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[27] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[26] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[26] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[25] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[25] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[24] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[24] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[23] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[23] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[22] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[22] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[21] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[21] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[20] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[20] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[19] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[19] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[18] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[18] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[17] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[17] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[16] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[16] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[15] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[15] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[14] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[14] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[13] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[13] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[12] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[12] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[11] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[11] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[10] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[10] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[9] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[9] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[8] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[8] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[7] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[7] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[6] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[6] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[4] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[4] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[3] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[3] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[2] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[2] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_ienable_reg[1] ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_control_rd_data[1] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|trigger_state ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[31] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[31] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[30] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[30] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[29] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[29] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[28] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[28] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[27] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[27] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[26] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[26] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[25] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[25] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[24] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[24] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[23] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[23] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[22] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[22] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[21] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[21] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[20] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[20] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[19] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[19] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[18] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[18] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[17] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[17] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[16] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[16] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[15] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[15] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[14] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[14] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_push_switches:push_switches|readdata[13] ; Stuck at GND ; nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|av_readdata_pre[13] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][96] ; Stuck at GND ; nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][96] ; +; ; due to stuck port data_in ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize~3 ; Lost Fanouts ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.101 ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 1212 ; +; Number of registers using Synchronous Clear ; 69 ; +; Number of registers using Synchronous Load ; 166 ; +; Number of registers using Asynchronous Clear ; 885 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 476 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Inverted Register Statistics ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Inverted Register ; Fan out ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst ; 801 ; +; nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent|hold_waitrequest ; 23 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|av_waitrequest ; 7 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_chain[1] ; 2 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|r_sync_rst_dly ; 228 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|i_read ; 7 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; +; nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; 11 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[2] ; 1 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; 9 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|t_dav ; 3 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[1] ; 1 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg|oci_ienable[5] ; 2 ; +; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|rst2 ; 3 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer_int_chain[0] ; 1 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 1 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ; +; nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; 1 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; +; Total number of inverted registers = 22 ; ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator|wait_latency_counter[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator|wait_latency_counter[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|wait_latency_counter[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator|wait_latency_counter[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator|wait_latency_counter[0] ; +; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[12] ; +; 3:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[27] ; +; 3:1 ; 17 bits ; 34 LEs ; 34 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src1[12] ; +; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_shift_rot_result[12] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lights|nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; +; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_iw[15] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte0_data[4] ; +; 3:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|av_ld_byte2_data[2] ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|readdata[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[1] ; +; 4:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[10] ; +; 4:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_src2[20] ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; +; 4:1 ; 23 bits ; 46 LEs ; 46 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[15] ; +; 4:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonDReg[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_writedata[31] ; +; 6:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; +; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; +; 6:1 ; 13 bits ; 52 LEs ; 26 LEs ; 26 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; +; 6:1 ; 16 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; +; 5:1 ; 13 bits ; 39 LEs ; 39 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_alu_result[28] ; +; 4:1 ; 17 bits ; 34 LEs ; 34 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|F_pc[10] ; +; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|MonAReg[2] ; +; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break|break_readreg[15] ; +; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|d_byteenable[3] ; +; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; +; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |lights|nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; +; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|E_logic_result[18] ; +; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|W_rf_wr_data[19] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |lights|nios_system:NiosII|nios_system_nios2_processor:nios2_processor|D_dst_regnum[3] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; +; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; +; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; +; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; +; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; +; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; +; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; +; 8:1 ; 5 bits ; 25 LEs ; 10 LEs ; 15 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; +; 34:1 ; 4 bits ; 88 LEs ; 60 LEs ; 28 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; +; 28:1 ; 4 bits ; 72 LEs ; 48 LEs ; 24 LEs ; Yes ; |lights|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller ; ++-------------------+-------+------+-----------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-------------------+-------+------+-----------------------------------------------+ +; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[2] ; +; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; +; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; ++-------------------+-------+------+-----------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; ++-------------------+-------+------+------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-------------------+-------+------+------------------------------------------------------------------------------------------+ +; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; +; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; ++-------------------+-------+------+------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_cmd_xbar_demux:rsp_xbar_demux_001 ; ++-----------------+-------+------+--------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+--------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+--------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_003 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_004 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_005 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_006 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_007 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_008 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_009 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_010 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_011 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_012 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_013 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_014 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_015 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_016 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------+ +; Source assignments for nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_017 ; ++-----------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a ; ++----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ +; lpm_file ; nios_system_nios2_processor_rf_ram_a.mif ; String ; ++----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; ++------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 32 ; Signed Integer ; +; WIDTHAD_A ; 5 ; Signed Integer ; +; NUMWORDS_A ; 32 ; Signed Integer ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 32 ; Signed Integer ; +; WIDTHAD_B ; 5 ; Signed Integer ; +; NUMWORDS_B ; 32 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK0 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; nios_system_nios2_processor_rf_ram_a.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Signed Integer ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; CBXI_PARAMETER ; altsyncram_0rh1 ; Untyped ; ++------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b ; ++----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ +; lpm_file ; nios_system_nios2_processor_rf_ram_b.mif ; String ; ++----------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; ++------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; DUAL_PORT ; Untyped ; +; WIDTH_A ; 32 ; Signed Integer ; +; WIDTHAD_A ; 5 ; Signed Integer ; +; NUMWORDS_A ; 32 ; Signed Integer ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 32 ; Signed Integer ; +; WIDTHAD_B ; 5 ; Signed Integer ; +; NUMWORDS_B ; 32 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK0 ; Untyped ; +; ADDRESS_REG_B ; CLOCK0 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; nios_system_nios2_processor_rf_ram_b.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Signed Integer ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; CBXI_PARAMETER ; altsyncram_1rh1 ; Untyped ; ++------------------------------------+------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram ; ++----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; lpm_file ; nios_system_nios2_processor_ociram_default_contents.mif ; String ; ++----------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; ++------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; SINGLE_PORT ; Untyped ; +; WIDTH_A ; 32 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 1 ; Untyped ; +; WIDTHAD_B ; 1 ; Untyped ; +; NUMWORDS_B ; 1 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; nios_system_nios2_processor_ociram_default_contents.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Signed Integer ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; CBXI_PARAMETER ; altsyncram_4891 ; Untyped ; ++------------------------------------+---------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2 ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4 ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy ; ++-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; sld_mfg_id ; 70 ; Signed Integer ; +; sld_type_id ; 34 ; Signed Integer ; +; sld_version ; 3 ; Signed Integer ; +; sld_instance_index ; 0 ; Signed Integer ; +; sld_auto_instance_index ; YES ; String ; +; sld_ir_width ; 2 ; Signed Integer ; +; sld_sim_n_scan ; 0 ; Signed Integer ; +; sld_sim_action ; ; String ; +; sld_sim_total_length ; 0 ; Signed Integer ; +; lpm_type ; sld_virtual_jtag_basic ; String ; +; lpm_hint ; UNUSED ; String ; ++-------------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory ; ++----------------+-------------------------------+--------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------------------------------+--------------------------------------------------------+ +; INIT_FILE ; nios_system_onchip_memory.hex ; String ; ++----------------+-------------------------------+--------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; ++------------------------------------+-------------------------------+--------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-------------------------------+--------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; SINGLE_PORT ; Untyped ; +; WIDTH_A ; 32 ; Signed Integer ; +; WIDTHAD_A ; 16 ; Signed Integer ; +; NUMWORDS_A ; 51200 ; Signed Integer ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 1 ; Untyped ; +; WIDTHAD_B ; 1 ; Untyped ; +; NUMWORDS_B ; 1 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 4 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Signed Integer ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; nios_system_onchip_memory.hex ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 51200 ; Signed Integer ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; CBXI_PARAMETER ; altsyncram_4ed1 ; Untyped ; ++------------------------------------+-------------------------------+--------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; ++-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 8 ; Signed Integer ; +; LPM_NUMWORDS ; 64 ; Signed Integer ; +; LPM_WIDTHU ; 6 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; ++-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; ++-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 8 ; Signed Integer ; +; LPM_NUMWORDS ; 64 ; Signed Integer ; +; LPM_WIDTHU ; 6 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; ++-------------------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator ; ++-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 19 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; USE_BURSTCOUNT ; 0 ; Signed Integer ; +; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; +; USE_BEGINTRANSFER ; 0 ; Signed Integer ; +; USE_CHIPSELECT ; 0 ; Signed Integer ; +; USE_READ ; 1 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WRITE ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; AV_LINEWRAPBURSTS ; 1 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; ++-----------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator ; ++-----------------------------+-------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------------------+-------+--------------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 19 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; USE_BURSTCOUNT ; 0 ; Signed Integer ; +; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; +; USE_BEGINTRANSFER ; 0 ; Signed Integer ; +; USE_CHIPSELECT ; 0 ; Signed Integer ; +; USE_READ ; 1 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WRITE ; 1 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; AV_REGISTERINCOMINGSIGNALS ; 1 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; ++-----------------------------+-------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 9 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 16 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 1 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 1 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator ; ++--------------------------------+-------+---------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+---------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+---------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator ; ++--------------------------------+-------+------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 8 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 13 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 13 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 13 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 13 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator ; ++--------------------------------+-------+----------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+----------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+----------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator ; ++--------------------------------+-------+------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 19 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ +; PKT_QOS_H ; 75 ; Signed Integer ; +; PKT_QOS_L ; 75 ; Signed Integer ; +; PKT_DATA_SIDEBAND_H ; 73 ; Signed Integer ; +; PKT_DATA_SIDEBAND_L ; 73 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_H ; 72 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_L ; 72 ; Signed Integer ; +; PKT_CACHE_H ; 93 ; Signed Integer ; +; PKT_CACHE_L ; 90 ; Signed Integer ; +; PKT_THREAD_ID_H ; 86 ; Signed Integer ; +; PKT_THREAD_ID_L ; 86 ; Signed Integer ; +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; PKT_BURST_TYPE_H ; 71 ; Signed Integer ; +; PKT_BURST_TYPE_L ; 70 ; Signed Integer ; +; PKT_TRANS_EXCLUSIVE ; 60 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; ID ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; +; BURSTWRAP_VALUE ; 3 ; Signed Integer ; +; CACHE_VALUE ; 0 ; Signed Integer ; +; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; +; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_PROTECTION_W ; 3 ; Signed Integer ; +; PKT_ADDR_W ; 19 ; Signed Integer ; +; PKT_DATA_W ; 32 ; Signed Integer ; +; PKT_BYTEEN_W ; 4 ; Signed Integer ; +; PKT_SRC_ID_W ; 5 ; Signed Integer ; +; PKT_DEST_ID_W ; 5 ; Signed Integer ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ +; PKT_QOS_H ; 75 ; Signed Integer ; +; PKT_QOS_L ; 75 ; Signed Integer ; +; PKT_DATA_SIDEBAND_H ; 73 ; Signed Integer ; +; PKT_DATA_SIDEBAND_L ; 73 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_H ; 72 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_L ; 72 ; Signed Integer ; +; PKT_CACHE_H ; 93 ; Signed Integer ; +; PKT_CACHE_L ; 90 ; Signed Integer ; +; PKT_THREAD_ID_H ; 86 ; Signed Integer ; +; PKT_THREAD_ID_L ; 86 ; Signed Integer ; +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; PKT_BURST_TYPE_H ; 71 ; Signed Integer ; +; PKT_BURST_TYPE_L ; 70 ; Signed Integer ; +; PKT_TRANS_EXCLUSIVE ; 60 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; ID ; 0 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; +; BURSTWRAP_VALUE ; 7 ; Signed Integer ; +; CACHE_VALUE ; 0 ; Signed Integer ; +; SECURE_ACCESS_BIT ; 1 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; +; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_PROTECTION_W ; 3 ; Signed Integer ; +; PKT_ADDR_W ; 19 ; Signed Integer ; +; PKT_DATA_W ; 32 ; Signed Integer ; +; PKT_BYTEEN_W ; 4 ; Signed Integer ; +; PKT_SRC_ID_W ; 5 ; Signed Integer ; +; PKT_DEST_ID_W ; 5 ; Signed Integer ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 74 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 54 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 59 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 55 ; Signed Integer ; +; PKT_TRANS_POSTED ; 56 ; Signed Integer ; +; PKT_TRANS_WRITE ; 57 ; Signed Integer ; +; PKT_TRANS_READ ; 58 ; Signed Integer ; +; PKT_SRC_ID_H ; 80 ; Signed Integer ; +; PKT_SRC_ID_L ; 76 ; Signed Integer ; +; PKT_DEST_ID_H ; 85 ; Signed Integer ; +; PKT_DEST_ID_L ; 81 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 66 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 64 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 63 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 61 ; Signed Integer ; +; PKT_PROTECTION_H ; 89 ; Signed Integer ; +; PKT_PROTECTION_L ; 87 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 95 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 94 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 69 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 67 ; Signed Integer ; +; ST_DATA_W ; 96 ; Signed Integer ; +; ST_CHANNEL_W ; 18 ; Signed Integer ; +; ADDR_W ; 19 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; USE_READRESPONSE ; 0 ; Signed Integer ; +; USE_WRITERESPONSE ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 97 ; Signed Integer ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 19 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 97 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 97 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 1 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 15 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 1 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 15 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router:id_router_001|nios_system_id_router_default_decode:the_default_decode ; ++--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++--------------------+-------+--------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_003|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_004|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_005|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_006|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_007|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_008|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_009|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_010|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_011|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_012|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_013|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_014|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_015|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_016|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_id_router_002:id_router_017|nios_system_id_router_002_default_decode:the_default_decode ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_WR_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_RD_CHANNEL ; -1 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++--------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller ; ++-------------------------+----------+-------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+----------+-------------------------------------------------------------------+ +; NUM_RESET_INPUTS ; 2 ; Signed Integer ; +; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; +; SYNC_DEPTH ; 2 ; Signed Integer ; +; RESET_REQUEST_PRESENT ; 1 ; Signed Integer ; ++-------------------------+----------+-------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +; ASYNC_RESET ; 1 ; Unsigned Binary ; +; DEPTH ; 2 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; ++----------------+-------------+-----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------------+-----------------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 2 ; Signed Integer ; +; SCHEME ; round-robin ; String ; +; PIPELINE ; 1 ; Signed Integer ; ++----------------+-------------+-----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 4 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; ++----------------+-------------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------------+---------------------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 2 ; Signed Integer ; +; SCHEME ; round-robin ; String ; +; PIPELINE ; 1 ; Signed Integer ; ++----------------+-------------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 4 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb ; ++----------------+--------+----------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+--------+----------------------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 2 ; Signed Integer ; +; SCHEME ; no-arb ; String ; +; PIPELINE ; 0 ; Signed Integer ; ++----------------+--------+----------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 4 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb ; ++----------------+--------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+--------+------------------------------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 18 ; Signed Integer ; +; SCHEME ; no-arb ; String ; +; PIPELINE ; 0 ; Signed Integer ; ++----------------+--------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 36 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Name ; Value ; ++-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Number of entity instances ; 4 ; +; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 32 ; +; -- NUMWORDS_A ; 32 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 32 ; +; -- NUMWORDS_B ; 32 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram ; +; -- OPERATION_MODE ; DUAL_PORT ; +; -- WIDTH_A ; 32 ; +; -- NUMWORDS_A ; 32 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 32 ; +; -- NUMWORDS_B ; 32 ; +; -- ADDRESS_REG_B ; CLOCK0 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram ; +; -- OPERATION_MODE ; SINGLE_PORT ; +; -- WIDTH_A ; 32 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram ; +; -- OPERATION_MODE ; SINGLE_PORT ; +; -- WIDTH_A ; 32 ; +; -- NUMWORDS_A ; 51200 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; scfifo Parameter Settings by Entity Instance ; ++----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ +; Number of entity instances ; 2 ; +; Entity Instance ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 8 ; +; -- LPM_NUMWORDS ; 64 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; +; Entity Instance ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r|scfifo:rfifo ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 8 ; +; -- LPM_NUMWORDS ; 64 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; ++----------------------------+-----------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; ++----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ +; b[35..1] ; Input ; Info ; Stuck at GND ; +; b[0] ; Input ; Info ; Stuck at VCC ; +; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+--------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; ++---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ +; b[3..1] ; Input ; Info ; Stuck at GND ; +; b[0] ; Input ; Info ; Stuck at VCC ; +; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; ++---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ +; b[3..2] ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+--------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_reset_controller:rst_controller" ; ++------------+-------+----------+-------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+-------+----------+-------------------------------------------------------+ +; reset_in2 ; Input ; Info ; Stuck at GND ; +; reset_in3 ; Input ; Info ; Stuck at GND ; +; reset_in4 ; Input ; Info ; Stuck at GND ; +; reset_in5 ; Input ; Info ; Stuck at GND ; +; reset_in6 ; Input ; Info ; Stuck at GND ; +; reset_in7 ; Input ; Info ; Stuck at GND ; +; reset_in8 ; Input ; Info ; Stuck at GND ; +; reset_in9 ; Input ; Info ; Stuck at GND ; +; reset_in10 ; Input ; Info ; Stuck at GND ; +; reset_in11 ; Input ; Info ; Stuck at GND ; +; reset_in12 ; Input ; Info ; Stuck at GND ; +; reset_in13 ; Input ; Info ; Stuck at GND ; +; reset_in14 ; Input ; Info ; Stuck at GND ; +; reset_in15 ; Input ; Info ; Stuck at GND ; ++------------+-------+----------+-------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ +; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; default_wr_channel ; Output ; Info ; Explicitly unconnected ; +; default_rd_channel ; Output ; Info ; Explicitly unconnected ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------------+ +; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; default_wr_channel ; Output ; Info ; Explicitly unconnected ; +; default_rd_channel ; Output ; Info ; Explicitly unconnected ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ +; default_wr_channel ; Output ; Info ; Explicitly unconnected ; +; default_rd_channel ; Output ; Info ; Explicitly unconnected ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ +; default_wr_channel ; Output ; Info ; Explicitly unconnected ; +; default_rd_channel ; Output ; Info ; Explicitly unconnected ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_blon_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_blon_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_on_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_on_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:lcd_16207_0_control_slave_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex7_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex7_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex6_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex6_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex5_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex5_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex4_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex4_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex3_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex3_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex2_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex1_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:hex0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:hex0_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:push_switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:push_switches_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+---------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+---------------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+---------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:switches_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:ledrs_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:ledrs_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+-------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+-------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+-------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:leds_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:onchip_memory_s1_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+---------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+---------------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+---------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ +; m0_response ; Input ; Info ; Stuck at GND ; +; m0_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; m0_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++-------------------------+--------+----------+--------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ +; av_response ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Input ; Info ; Stuck at GND ; +; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; ++-------------------------+--------+----------+----------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" ; ++-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ +; av_response ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Input ; Info ; Stuck at GND ; +; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; ++-------------------------+--------+----------+-----------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_blon_s1_translator" ; ++--------------------------+--------+----------+-------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+-------------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+-------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_on_s1_translator" ; ++--------------------------+--------+----------+-----------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+-----------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" ; ++--------------------------+--------+----------+---------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------------------------+ +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_chipselect ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex7_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex6_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex5_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex4_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex3_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex2_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex1_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:hex0_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:push_switches_s1_translator" ; ++--------------------------+--------+----------+------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+------------------------------------------------------------+ +; av_write ; Output ; Info ; Explicitly unconnected ; +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_writedata ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_chipselect ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:switches_s1_translator" ; ++--------------------------+--------+----------+-------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+-------------------------------------------------------+ +; av_write ; Output ; Info ; Explicitly unconnected ; +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_writedata ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_chipselect ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+-------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:ledrs_s1_translator" ; ++--------------------------+--------+----------+----------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+----------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+----------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" ; ++--------------------------+--------+----------+-----------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+-----------------------------------------------------------------------+ +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+-----------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" ; ++--------------------------+--------+----------+---------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+---------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+---------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" ; ++--------------------------+--------+----------+------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+------------------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" ; ++--------------------------+--------+----------+-----------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+-----------------------------------------------------------------------------+ +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_chipselect ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; +; uav_response ; Output ; Info ; Explicitly unconnected ; +; av_response ; Input ; Info ; Stuck at GND ; +; uav_writeresponserequest ; Input ; Info ; Stuck at GND ; +; uav_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; +; av_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; av_writeresponsevalid ; Input ; Info ; Stuck at GND ; ++--------------------------+--------+----------+-----------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" ; ++--------------------------+--------+----------+------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+------------------------------------------------------------------------+ +; av_burstcount ; Input ; Info ; Stuck at VCC ; +; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; +; av_begintransfer ; Input ; Info ; Stuck at GND ; +; av_chipselect ; Input ; Info ; Stuck at GND ; +; av_readdatavalid ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Input ; Info ; Stuck at GND ; +; uav_clken ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Input ; Info ; Stuck at VCC ; +; uav_response ; Input ; Info ; Stuck at GND ; +; av_response ; Output ; Info ; Explicitly unconnected ; +; uav_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; +; av_writeresponserequest ; Input ; Info ; Stuck at GND ; +; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; ++--------------------------+--------+----------+------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" ; ++--------------------------+--------+----------+-------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------------+--------+----------+-------------------------------------------------------------------------------+ +; av_burstcount ; Input ; Info ; Stuck at VCC ; +; av_byteenable ; Input ; Info ; Stuck at VCC ; +; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; +; av_begintransfer ; Input ; Info ; Stuck at GND ; +; av_chipselect ; Input ; Info ; Stuck at GND ; +; av_readdatavalid ; Output ; Info ; Explicitly unconnected ; +; av_write ; Input ; Info ; Stuck at GND ; +; av_writedata ; Input ; Info ; Stuck at GND ; +; av_lock ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Input ; Info ; Stuck at GND ; +; uav_clken ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Input ; Info ; Stuck at VCC ; +; uav_response ; Input ; Info ; Stuck at GND ; +; av_response ; Output ; Info ; Explicitly unconnected ; +; uav_writeresponserequest ; Output ; Info ; Explicitly unconnected ; +; uav_writeresponsevalid ; Input ; Info ; Stuck at GND ; +; av_writeresponserequest ; Input ; Info ; Stuck at GND ; +; av_writeresponsevalid ; Output ; Info ; Explicitly unconnected ; ++--------------------------+--------+----------+-------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" ; ++----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; raw_tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; tdi ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; rti ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; shift ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; update ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; usr1 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; clr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; ir_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; tdo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; irq ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; ir_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_cdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; jtag_state_sdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; jtag_state_udr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ++----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" ; ++---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; dataavailable ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; readyfordata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" ; ++--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; virtual_state_e1dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; virtual_state_pdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; virtual_state_e2dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; virtual_state_cir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; tms ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_tlr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_sdrs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_cdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_sdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_e1dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_pdr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_e2dr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_udr ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_sirs ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_cir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_sir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_e1ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_pir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_e2ir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_uir ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++--------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer4" ; ++---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; reset_n ; Input ; Info ; Stuck at VCC ; ++---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3" ; ++---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; reset_n ; Input ; Info ; Stuck at VCC ; ++---------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" ; ++---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; clkx2 ; Input ; Info ; Stuck at GND ; +; tr_clk ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; tr_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" ; ++------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; fifowp_inc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" ; ++---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; td_mode ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" ; ++------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; jdo ; Input ; Warning ; Input port expression (38 bits) is wider than the input port (16 bits) it drives. The 22 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; ++------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" ; ++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; dbrk_trigout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" ; ++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; xbrk_trigout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" ; ++----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; debugreq ; Input ; Info ; Stuck at GND ; ++----------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ +; oci_ienable[31..6] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; oci_ienable[4..0] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" ; ++-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; F_pcb[1..0] ; Input ; Info ; Stuck at GND ; +; i_address[1..0] ; Input ; Info ; Stuck at GND ; ++-----------------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" ; ++--------------+--------+----------+---------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+---------------------------------------------------------+ +; no_ci_readra ; Output ; Info ; Explicitly unconnected ; ++--------------+--------+----------+---------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "nios_system:NiosII" ; ++------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ +; lcd_16207_0_data ; Bidir ; Critical Warning ; Port on prototype, e.g. VHDL component, declared as "Output" but port on entity declared as "Bidir" ; ++------------------+-------+------------------+-----------------------------------------------------------------------------------------------------+ + + ++---------------------------------+ +; Elapsed Time Per Partition ; ++------------------+--------------+ +; Partition Name ; Elapsed Time ; ++------------------+--------------+ +; Top ; 00:00:07 ; +; sld_hub:auto_hub ; 00:00:00 ; ++------------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Thu Dec 22 10:07:13 2016 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lights -c lights +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12248): Elaborating Qsys system entity "nios_system.qsys" +Info (12250): 2016.12.22.10:07:14 Progress: Loading qsys_tutorial/nios_system.qsys +Info (12250): 2016.12.22.10:07:14 Progress: Reading input file +Info (12250): 2016.12.22.10:07:14 Progress: Adding clk_0 [clock_source 13.0] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module clk_0 +Info (12250): 2016.12.22.10:07:15 Progress: Adding nios2_processor [altera_nios2_qsys 13.0] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module nios2_processor +Info (12250): 2016.12.22.10:07:15 Progress: Adding onchip_memory [altera_avalon_onchip_memory2 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module onchip_memory +Info (12250): 2016.12.22.10:07:15 Progress: Adding jtag_uart [altera_avalon_jtag_uart 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module jtag_uart +Info (12250): 2016.12.22.10:07:15 Progress: Adding LEDs [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module LEDs +Info (12250): 2016.12.22.10:07:15 Progress: Adding LEDRs [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module LEDRs +Info (12250): 2016.12.22.10:07:15 Progress: Adding switches [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module switches +Info (12250): 2016.12.22.10:07:15 Progress: Adding push_switches [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module push_switches +Info (12250): 2016.12.22.10:07:15 Progress: Adding hex0 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex0 +Info (12250): 2016.12.22.10:07:15 Progress: Adding hex1 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex1 +Info (12250): 2016.12.22.10:07:15 Progress: Adding hex2 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex2 +Info (12250): 2016.12.22.10:07:15 Progress: Adding hex3 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex3 +Info (12250): 2016.12.22.10:07:15 Progress: Adding hex4 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex4 +Info (12250): 2016.12.22.10:07:15 Progress: Adding hex5 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:15 Progress: Parameterizing module hex5 +Info (12250): 2016.12.22.10:07:15 Progress: Adding hex6 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module hex6 +Info (12250): 2016.12.22.10:07:16 Progress: Adding hex7 [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module hex7 +Info (12250): 2016.12.22.10:07:16 Progress: Adding lcd_16207_0 [altera_avalon_lcd_16207 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module lcd_16207_0 +Info (12250): 2016.12.22.10:07:16 Progress: Adding lcd_on [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module lcd_on +Info (12250): 2016.12.22.10:07:16 Progress: Adding lcd_blon [altera_avalon_pio 13.0.1.99.2] +Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing module lcd_blon +Info (12250): 2016.12.22.10:07:16 Progress: Building connections +Info (12250): 2016.12.22.10:07:16 Progress: Parameterizing connections +Info (12250): 2016.12.22.10:07:16 Progress: Validating +Info (12250): 2016.12.22.10:07:16 Progress: Done reading input file +Info (12250): Nios_system.switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info (12250): Nios_system.push_switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info (12250): Nios_system: Generating nios_system "nios_system" for QUARTUS_SYNTH +Info (12250): Pipeline_bridge_swap_transform: After transform: 19 modules, 75 connections +Info (12250): No custom instruction connections, skipping transform +Info (12250): Merlin_translator_transform: After transform: 39 modules, 155 connections +Info (12250): Merlin_domain_transform: After transform: 78 modules, 423 connections +Info (12250): Merlin_router_transform: After transform: 98 modules, 503 connections +Info (12250): Reset_adaptation_transform: After transform: 99 modules, 390 connections +Info (12250): Merlin_network_to_switch_transform: After transform: 138 modules, 470 connections +Info (12250): Merlin_mm_transform: After transform: 138 modules, 470 connections +Info (12250): Merlin_interrupt_mapper_transform: After transform: 139 modules, 473 connections +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Warning (12251): Nios_system: "No matching role found for rst_controller:reset_out:reset_req (reset_req)" +Info (12250): Nios2_processor: Starting RTL generation for module 'nios_system_nios2_processor' +Info (12250): Nios2_processor: Generation command is [exec C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/13.0sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=nios_system_nios2_processor --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0001_nios2_processor_gen//nios_system_nios2_processor_processor_configuration.pl --do_build_sim=0 --bogus ] +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Starting Nios II generation +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Checking for plaintext license. +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Couldn't query license setup in Quartus directory C:/altera/13.0sp1/quartus +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) LM_LICENSE_FILE environment variable is empty +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Plaintext license not found. +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) No license required to generate encrypted Nios II/e. +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Elaborating CPU configuration settings +Info (12250): Nios2_processor: # 2016.12.22 10:07:23 (*) Creating all objects for CPU +Info (12250): Nios2_processor: # 2016.12.22 10:07:24 (*) Generating RTL from CPU objects +Info (12250): Nios2_processor: # 2016.12.22 10:07:24 (*) Creating plain-text RTL +Info (12250): Nios2_processor: # 2016.12.22 10:07:26 (*) Done Nios II generation +Info (12250): Nios2_processor: Done RTL generation for module 'nios_system_nios2_processor' +Info (12250): Nios2_processor: "nios_system" instantiated altera_nios2_qsys "nios2_processor" +Info (12250): Onchip_memory: Starting RTL generation for module 'nios_system_onchip_memory' +Info (12250): Onchip_memory: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=nios_system_onchip_memory --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0002_onchip_memory_gen//nios_system_onchip_memory_component_configuration.pl --do_build_sim=0 ] +Info (12250): Onchip_memory: Done RTL generation for module 'nios_system_onchip_memory' +Info (12250): Onchip_memory: "nios_system" instantiated altera_avalon_onchip_memory2 "onchip_memory" +Info (12250): Jtag_uart: Starting RTL generation for module 'nios_system_jtag_uart' +Info (12250): Jtag_uart: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=nios_system_jtag_uart --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0003_jtag_uart_gen//nios_system_jtag_uart_component_configuration.pl --do_build_sim=0 ] +Info (12250): Jtag_uart: Done RTL generation for module 'nios_system_jtag_uart' +Info (12250): Jtag_uart: "nios_system" instantiated altera_avalon_jtag_uart "jtag_uart" +Info (12250): LEDs: Starting RTL generation for module 'nios_system_LEDs' +Info (12250): LEDs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0004_LEDs_gen//nios_system_LEDs_component_configuration.pl --do_build_sim=0 ] +Info (12250): LEDs: Done RTL generation for module 'nios_system_LEDs' +Info (12250): LEDs: "nios_system" instantiated altera_avalon_pio "LEDs" +Info (12250): LEDRs: Starting RTL generation for module 'nios_system_LEDRs' +Info (12250): LEDRs: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_LEDRs --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0005_LEDRs_gen//nios_system_LEDRs_component_configuration.pl --do_build_sim=0 ] +Info (12250): LEDRs: Done RTL generation for module 'nios_system_LEDRs' +Info (12250): LEDRs: "nios_system" instantiated altera_avalon_pio "LEDRs" +Info (12250): Switches: Starting RTL generation for module 'nios_system_switches' +Info (12250): Switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0006_switches_gen//nios_system_switches_component_configuration.pl --do_build_sim=0 ] +Info (12250): Switches: Done RTL generation for module 'nios_system_switches' +Info (12250): Switches: "nios_system" instantiated altera_avalon_pio "switches" +Info (12250): Push_switches: Starting RTL generation for module 'nios_system_push_switches' +Info (12250): Push_switches: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_push_switches --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0007_push_switches_gen//nios_system_push_switches_component_configuration.pl --do_build_sim=0 ] +Info (12250): Push_switches: Done RTL generation for module 'nios_system_push_switches' +Info (12250): Push_switches: "nios_system" instantiated altera_avalon_pio "push_switches" +Info (12250): Hex0: Starting RTL generation for module 'nios_system_hex0' +Info (12250): Hex0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_hex0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0008_hex0_gen//nios_system_hex0_component_configuration.pl --do_build_sim=0 ] +Info (12250): Hex0: Done RTL generation for module 'nios_system_hex0' +Info (12250): Hex0: "nios_system" instantiated altera_avalon_pio "hex0" +Info (12250): Lcd_16207_0: Starting RTL generation for module 'nios_system_lcd_16207_0' +Info (12250): Lcd_16207_0: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207 -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_lcd_16207/generate_rtl.pl --name=nios_system_lcd_16207_0 --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0009_lcd_16207_0_gen//nios_system_lcd_16207_0_component_configuration.pl --do_build_sim=0 ] +Info (12250): Lcd_16207_0: Done RTL generation for module 'nios_system_lcd_16207_0' +Info (12250): Lcd_16207_0: "nios_system" instantiated altera_avalon_lcd_16207 "lcd_16207_0" +Info (12250): Lcd_on: Starting RTL generation for module 'nios_system_lcd_on' +Info (12250): Lcd_on: Generation command is [exec C:/altera/13.0sp1/quartus/bin/perl/bin/perl.exe -I C:/altera/13.0sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/13.0sp1/quartus/sopc_builder/bin/europa -I C:/altera/13.0sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/13.0sp1/quartus/sopc_builder/bin -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/altera/13.0sp1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=nios_system_lcd_on --dir=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen/ --quartus_dir=C:/altera/13.0sp1/quartus --verilog --config=C:/Users/takayun/AppData/Local/Temp/alt7157_6744727567867726945.dir/0010_lcd_on_gen//nios_system_lcd_on_component_configuration.pl --do_build_sim=0 ] +Info (12250): Lcd_on: Done RTL generation for module 'nios_system_lcd_on' +Info (12250): Lcd_on: "nios_system" instantiated altera_avalon_pio "lcd_on" +Info (12250): Nios2_processor_instruction_master_translator: "nios_system" instantiated altera_merlin_master_translator "nios2_processor_instruction_master_translator" +Info (12250): Nios2_processor_jtag_debug_module_translator: "nios_system" instantiated altera_merlin_slave_translator "nios2_processor_jtag_debug_module_translator" +Info (12250): Nios2_processor_instruction_master_translator_avalon_universal_master_0_agent: "nios_system" instantiated altera_merlin_master_agent "nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" +Info (12250): Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent: "nios_system" instantiated altera_merlin_slave_agent "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info (12250): Nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "nios_system" instantiated altera_avalon_sc_fifo "nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info (12250): Addr_router: "nios_system" instantiated altera_merlin_router "addr_router" +Info (12250): Addr_router_001: "nios_system" instantiated altera_merlin_router "addr_router_001" +Info (12250): Id_router: "nios_system" instantiated altera_merlin_router "id_router" +Info (12250): Id_router_002: "nios_system" instantiated altera_merlin_router "id_router_002" +Info (12250): Rst_controller: "nios_system" instantiated altera_reset_controller "rst_controller" +Info (12250): Cmd_xbar_demux: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info (12250): Cmd_xbar_demux_001: "nios_system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info (12250): Cmd_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info (12250): Rsp_xbar_demux_002: "nios_system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info (12250): Rsp_xbar_mux: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info (12250): Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv +Info (12250): Rsp_xbar_mux_001: "nios_system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info (12250): Reusing file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/db/ip/nios_system/submodules/altera_merlin_arbitrator.sv +Info (12250): Irq_mapper: "nios_system" instantiated altera_irq_mapper "irq_mapper" +Info (12250): Nios_system: Done nios_system" with 28 modules, 155 files, 4086283 bytes +Info (12249): Finished elaborating Qsys system entity "nios_system.qsys" +Info (12021): Found 2 design units, including 1 entities, in source file lights.vhd + Info (12022): Found design unit 1: lights-lights_rtl + Info (12023): Found entity 1: lights +Info (12021): Found 1 design units, including 1 entities, in source file nios_system/synthesis/nios_system.v + Info (12023): Found entity 1: nios_system +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/nios_system.v + Info (12023): Found entity 1: nios_system +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_avalon_sc_fifo.v + Info (12023): Found entity 1: altera_avalon_sc_fifo +Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/altera_merlin_arbitrator.sv + Info (12023): Found entity 1: altera_merlin_arbitrator + Info (12023): Found entity 2: altera_merlin_arb_adder +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_burst_uncompressor.sv + Info (12023): Found entity 1: altera_merlin_burst_uncompressor +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_agent.sv + Info (12023): Found entity 1: altera_merlin_master_agent +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_master_translator.sv + Info (12023): Found entity 1: altera_merlin_master_translator +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_agent.sv + Info (12023): Found entity 1: altera_merlin_slave_agent +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_merlin_slave_translator.sv + Info (12023): Found entity 1: altera_merlin_slave_translator +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_controller.v + Info (12023): Found entity 1: altera_reset_controller +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/altera_reset_synchronizer.v + Info (12023): Found entity 1: altera_reset_synchronizer +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_ledrs.v + Info (12023): Found entity 1: nios_system_LEDRs +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_leds.v + Info (12023): Found entity 1: nios_system_LEDs +Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router.sv + Info (12023): Found entity 1: nios_system_addr_router_default_decode + Info (12023): Found entity 2: nios_system_addr_router +Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_addr_router_001.sv + Info (12023): Found entity 1: nios_system_addr_router_001_default_decode + Info (12023): Found entity 2: nios_system_addr_router_001 +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux.sv + Info (12023): Found entity 1: nios_system_cmd_xbar_demux +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_demux_001.sv + Info (12023): Found entity 1: nios_system_cmd_xbar_demux_001 +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_cmd_xbar_mux.sv + Info (12023): Found entity 1: nios_system_cmd_xbar_mux +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_hex0.v + Info (12023): Found entity 1: nios_system_hex0 +Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router.sv + Info (12023): Found entity 1: nios_system_id_router_default_decode + Info (12023): Found entity 2: nios_system_id_router +Info (12021): Found 2 design units, including 2 entities, in source file db/ip/nios_system/submodules/nios_system_id_router_002.sv + Info (12023): Found entity 1: nios_system_id_router_002_default_decode + Info (12023): Found entity 2: nios_system_id_router_002 +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_irq_mapper.sv + Info (12023): Found entity 1: nios_system_irq_mapper +Info (12021): Found 5 design units, including 5 entities, in source file db/ip/nios_system/submodules/nios_system_jtag_uart.v + Info (12023): Found entity 1: nios_system_jtag_uart_sim_scfifo_w + Info (12023): Found entity 2: nios_system_jtag_uart_scfifo_w + Info (12023): Found entity 3: nios_system_jtag_uart_sim_scfifo_r + Info (12023): Found entity 4: nios_system_jtag_uart_scfifo_r + Info (12023): Found entity 5: nios_system_jtag_uart +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_16207_0.v + Info (12023): Found entity 1: nios_system_lcd_16207_0 +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_lcd_on.v + Info (12023): Found entity 1: nios_system_lcd_on +Info (12021): Found 21 design units, including 21 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor.v + Info (12023): Found entity 1: nios_system_nios2_processor_register_bank_a_module + Info (12023): Found entity 2: nios_system_nios2_processor_register_bank_b_module + Info (12023): Found entity 3: nios_system_nios2_processor_nios2_oci_debug + Info (12023): Found entity 4: nios_system_nios2_processor_ociram_sp_ram_module + Info (12023): Found entity 5: nios_system_nios2_processor_nios2_ocimem + Info (12023): Found entity 6: nios_system_nios2_processor_nios2_avalon_reg + Info (12023): Found entity 7: nios_system_nios2_processor_nios2_oci_break + Info (12023): Found entity 8: nios_system_nios2_processor_nios2_oci_xbrk + Info (12023): Found entity 9: nios_system_nios2_processor_nios2_oci_dbrk + Info (12023): Found entity 10: nios_system_nios2_processor_nios2_oci_itrace + Info (12023): Found entity 11: nios_system_nios2_processor_nios2_oci_td_mode + Info (12023): Found entity 12: nios_system_nios2_processor_nios2_oci_dtrace + Info (12023): Found entity 13: nios_system_nios2_processor_nios2_oci_compute_tm_count + Info (12023): Found entity 14: nios_system_nios2_processor_nios2_oci_fifowp_inc + Info (12023): Found entity 15: nios_system_nios2_processor_nios2_oci_fifocount_inc + Info (12023): Found entity 16: nios_system_nios2_processor_nios2_oci_fifo + Info (12023): Found entity 17: nios_system_nios2_processor_nios2_oci_pib + Info (12023): Found entity 18: nios_system_nios2_processor_nios2_oci_im + Info (12023): Found entity 19: nios_system_nios2_processor_nios2_performance_monitors + Info (12023): Found entity 20: nios_system_nios2_processor_nios2_oci + Info (12023): Found entity 21: nios_system_nios2_processor +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_sysclk.v + Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_sysclk +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_tck.v + Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_tck +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_jtag_debug_module_wrapper.v + Info (12023): Found entity 1: nios_system_nios2_processor_jtag_debug_module_wrapper +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_oci_test_bench.v + Info (12023): Found entity 1: nios_system_nios2_processor_oci_test_bench +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_nios2_processor_test_bench.v + Info (12023): Found entity 1: nios_system_nios2_processor_test_bench +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_onchip_memory.v + Info (12023): Found entity 1: nios_system_onchip_memory +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_push_switches.v + Info (12023): Found entity 1: nios_system_push_switches +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_demux_002.sv + Info (12023): Found entity 1: nios_system_rsp_xbar_demux_002 +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux.sv + Info (12023): Found entity 1: nios_system_rsp_xbar_mux +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_rsp_xbar_mux_001.sv + Info (12023): Found entity 1: nios_system_rsp_xbar_mux_001 +Info (12021): Found 1 design units, including 1 entities, in source file db/ip/nios_system/submodules/nios_system_switches.v + Info (12023): Found entity 1: nios_system_switches +Info (12127): Elaborating entity "lights" for the top level hierarchy +Info (12128): Elaborating entity "nios_system" for hierarchy "nios_system:NiosII" +Info (12128): Elaborating entity "nios_system_nios2_processor" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor" +Info (12128): Elaborating entity "nios_system_nios2_processor_test_bench" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_test_bench:the_nios_system_nios2_processor_test_bench" +Info (12128): Elaborating entity "nios_system_nios2_processor_register_bank_a_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a" +Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "nios_system_nios2_processor_rf_ram_a.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "32" + Info (12134): Parameter "numwords_b" = "32" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "widthad_a" = "5" + Info (12134): Parameter "widthad_b" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0rh1.tdf + Info (12023): Found entity 1: altsyncram_0rh1 +Info (12128): Elaborating entity "altsyncram_0rh1" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_a_module:nios_system_nios2_processor_register_bank_a|altsyncram:the_altsyncram|altsyncram_0rh1:auto_generated" +Info (12128): Elaborating entity "nios_system_nios2_processor_register_bank_b_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b" +Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "nios_system_nios2_processor_rf_ram_b.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "32" + Info (12134): Parameter "numwords_b" = "32" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "widthad_a" = "5" + Info (12134): Parameter "widthad_b" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1rh1.tdf + Info (12023): Found entity 1: altsyncram_1rh1 +Info (12128): Elaborating entity "altsyncram_1rh1" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_register_bank_b_module:nios_system_nios2_processor_register_bank_b|altsyncram:the_altsyncram|altsyncram_1rh1:auto_generated" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_debug" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug" +Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: + Info (12134): Parameter "depth" = "2" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_ocimem" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem" +Info (12128): Elaborating entity "nios_system_nios2_processor_ociram_sp_ram_module" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram" +Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "init_file" = "nios_system_nios2_processor_ociram_default_contents.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "256" + Info (12134): Parameter "operation_mode" = "SINGLE_PORT" + Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_byteena_a" = "4" + Info (12134): Parameter "widthad_a" = "8" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4891.tdf + Info (12023): Found entity 1: altsyncram_4891 +Info (12128): Elaborating entity "altsyncram_4891" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_ocimem:the_nios_system_nios2_processor_nios2_ocimem|nios_system_nios2_processor_ociram_sp_ram_module:nios_system_nios2_processor_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_4891:auto_generated" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_avalon_reg" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_avalon_reg:the_nios_system_nios2_processor_nios2_avalon_reg" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_break" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_break:the_nios_system_nios2_processor_nios2_oci_break" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_xbrk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_xbrk:the_nios_system_nios2_processor_nios2_oci_xbrk" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_dbrk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dbrk:the_nios_system_nios2_processor_nios2_oci_dbrk" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_itrace" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_itrace:the_nios_system_nios2_processor_nios2_oci_itrace" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_dtrace" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_td_mode" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_dtrace:the_nios_system_nios2_processor_nios2_oci_dtrace|nios_system_nios2_processor_nios2_oci_td_mode:nios_system_nios2_processor_nios2_oci_trc_ctrl_td_mode" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifo" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_compute_tm_count" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_compute_tm_count:nios_system_nios2_processor_nios2_oci_compute_tm_count_tm_count" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifowp_inc" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifowp_inc:nios_system_nios2_processor_nios2_oci_fifowp_inc_fifowp" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_fifocount_inc" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_nios2_oci_fifocount_inc:nios_system_nios2_processor_nios2_oci_fifocount_inc_fifocount" +Info (12128): Elaborating entity "nios_system_nios2_processor_oci_test_bench" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_fifo:the_nios_system_nios2_processor_nios2_oci_fifo|nios_system_nios2_processor_oci_test_bench:the_nios_system_nios2_processor_oci_test_bench" +Warning (12158): Entity "nios_system_nios2_processor_oci_test_bench" contains only dangling pins +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_pib" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_pib:the_nios_system_nios2_processor_nios2_oci_pib" +Info (12128): Elaborating entity "nios_system_nios2_processor_nios2_oci_im" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_im:the_nios_system_nios2_processor_nios2_oci_im" +Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_wrapper" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper" +Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_tck" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck" +Info (12128): Elaborating entity "nios_system_nios2_processor_jtag_debug_module_sysclk" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_sysclk:the_nios_system_nios2_processor_jtag_debug_module_sysclk" +Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" with the following parameter: + Info (12134): Parameter "sld_auto_instance_index" = "YES" + Info (12134): Parameter "sld_instance_index" = "0" + Info (12134): Parameter "sld_ir_width" = "2" + Info (12134): Parameter "sld_mfg_id" = "70" + Info (12134): Parameter "sld_sim_action" = "" + Info (12134): Parameter "sld_sim_n_scan" = "0" + Info (12134): Parameter "sld_sim_total_length" = "0" + Info (12134): Parameter "sld_type_id" = "34" + Info (12134): Parameter "sld_version" = "3" +Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" +Info (12131): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|sld_virtual_jtag_basic:nios_system_nios2_processor_jtag_debug_module_phy" +Info (12128): Elaborating entity "nios_system_onchip_memory" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory" +Info (12128): Elaborating entity "altsyncram" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "byte_size" = "8" + Info (12134): Parameter "init_file" = "nios_system_onchip_memory.hex" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "maximum_depth" = "51200" + Info (12134): Parameter "numwords_a" = "51200" + Info (12134): Parameter "operation_mode" = "SINGLE_PORT" + Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_byteena_a" = "4" + Info (12134): Parameter "widthad_a" = "16" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4ed1.tdf + Info (12023): Found entity 1: altsyncram_4ed1 +Info (12128): Elaborating entity "altsyncram_4ed1" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/decode_qsa.tdf + Info (12023): Found entity 1: decode_qsa +Info (12128): Elaborating entity "decode_qsa" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|decode_qsa:decode3" +Info (12021): Found 1 design units, including 1 entities, in source file db/mux_nob.tdf + Info (12023): Found entity 1: mux_nob +Info (12128): Elaborating entity "mux_nob" for hierarchy "nios_system:NiosII|nios_system_onchip_memory:onchip_memory|altsyncram:the_altsyncram|altsyncram_4ed1:auto_generated|mux_nob:mux2" +Info (12128): Elaborating entity "nios_system_jtag_uart" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart" +Info (12128): Elaborating entity "nios_system_jtag_uart_scfifo_w" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w" +Info (12128): Elaborating entity "scfifo" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo" with the following parameter: + Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO" + Info (12134): Parameter "lpm_numwords" = "64" + Info (12134): Parameter "lpm_showahead" = "OFF" + Info (12134): Parameter "lpm_type" = "scfifo" + Info (12134): Parameter "lpm_width" = "8" + Info (12134): Parameter "lpm_widthu" = "6" + Info (12134): Parameter "overflow_checking" = "OFF" + Info (12134): Parameter "underflow_checking" = "OFF" + Info (12134): Parameter "use_eab" = "ON" +Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf + Info (12023): Found entity 1: scfifo_jr21 +Info (12128): Elaborating entity "scfifo_jr21" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf + Info (12023): Found entity 1: a_dpfifo_q131 +Info (12128): Elaborating entity "a_dpfifo_q131" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf + Info (12023): Found entity 1: a_fefifo_7cf +Info (12128): Elaborating entity "a_fefifo_7cf" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf + Info (12023): Found entity 1: cntr_do7 +Info (12128): Elaborating entity "cntr_do7" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw" +Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf + Info (12023): Found entity 1: dpram_nl21 +Info (12128): Elaborating entity "dpram_nl21" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf + Info (12023): Found entity 1: altsyncram_r1m1 +Info (12128): Elaborating entity "altsyncram_r1m1" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf + Info (12023): Found entity 1: cntr_1ob +Info (12128): Elaborating entity "cntr_1ob" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_w:the_nios_system_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count" +Info (12128): Elaborating entity "nios_system_jtag_uart_scfifo_r" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|nios_system_jtag_uart_scfifo_r:the_nios_system_jtag_uart_scfifo_r" +Info (12128): Elaborating entity "alt_jtag_atlantic" for hierarchy "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" +Info (12130): Elaborated megafunction instantiation "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" +Info (12133): Instantiated megafunction "nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic" with the following parameter: + Info (12134): Parameter "INSTANCE_ID" = "0" + Info (12134): Parameter "LOG2_RXFIFO_DEPTH" = "6" + Info (12134): Parameter "LOG2_TXFIFO_DEPTH" = "6" + Info (12134): Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES" +Info (12128): Elaborating entity "nios_system_LEDs" for hierarchy "nios_system:NiosII|nios_system_LEDs:leds" +Info (12128): Elaborating entity "nios_system_LEDRs" for hierarchy "nios_system:NiosII|nios_system_LEDRs:ledrs" +Info (12128): Elaborating entity "nios_system_switches" for hierarchy "nios_system:NiosII|nios_system_switches:switches" +Info (12128): Elaborating entity "nios_system_push_switches" for hierarchy "nios_system:NiosII|nios_system_push_switches:push_switches" +Info (12128): Elaborating entity "nios_system_hex0" for hierarchy "nios_system:NiosII|nios_system_hex0:hex0" +Info (12128): Elaborating entity "nios_system_lcd_16207_0" for hierarchy "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0" +Info (12128): Elaborating entity "nios_system_lcd_on" for hierarchy "nios_system:NiosII|nios_system_lcd_on:lcd_on" +Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_instruction_master_translator" +Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "nios_system:NiosII|altera_merlin_master_translator:nios2_processor_data_master_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:nios2_processor_jtag_debug_module_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:onchip_memory_s1_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:leds_s1_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:jtag_uart_avalon_jtag_slave_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator" +Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_instruction_master_translator_avalon_universal_master_0_agent" +Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "nios_system:NiosII|altera_merlin_master_agent:nios2_processor_data_master_translator_avalon_universal_master_0_agent" +Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "nios_system:NiosII|altera_merlin_slave_agent:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" +Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "nios_system:NiosII|altera_avalon_sc_fifo:nios2_processor_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info (12128): Elaborating entity "nios_system_addr_router" for hierarchy "nios_system:NiosII|nios_system_addr_router:addr_router" +Info (12128): Elaborating entity "nios_system_addr_router_default_decode" for hierarchy "nios_system:NiosII|nios_system_addr_router:addr_router|nios_system_addr_router_default_decode:the_default_decode" +Info (12128): Elaborating entity "nios_system_addr_router_001" for hierarchy "nios_system:NiosII|nios_system_addr_router_001:addr_router_001" +Info (12128): Elaborating entity "nios_system_addr_router_001_default_decode" for hierarchy "nios_system:NiosII|nios_system_addr_router_001:addr_router_001|nios_system_addr_router_001_default_decode:the_default_decode" +Info (12128): Elaborating entity "nios_system_id_router" for hierarchy "nios_system:NiosII|nios_system_id_router:id_router" +Info (12128): Elaborating entity "nios_system_id_router_default_decode" for hierarchy "nios_system:NiosII|nios_system_id_router:id_router|nios_system_id_router_default_decode:the_default_decode" +Info (12128): Elaborating entity "nios_system_id_router_002" for hierarchy "nios_system:NiosII|nios_system_id_router_002:id_router_002" +Info (12128): Elaborating entity "nios_system_id_router_002_default_decode" for hierarchy "nios_system:NiosII|nios_system_id_router_002:id_router_002|nios_system_id_router_002_default_decode:the_default_decode" +Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "nios_system:NiosII|altera_reset_controller:rst_controller" +Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "nios_system:NiosII|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" +Info (12128): Elaborating entity "nios_system_cmd_xbar_demux" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_demux:cmd_xbar_demux" +Info (12128): Elaborating entity "nios_system_cmd_xbar_demux_001" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_demux_001:cmd_xbar_demux_001" +Info (12128): Elaborating entity "nios_system_cmd_xbar_mux" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux" +Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb" +Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "nios_system:NiosII|nios_system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +Info (12128): Elaborating entity "nios_system_rsp_xbar_demux_002" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_demux_002:rsp_xbar_demux_002" +Info (12128): Elaborating entity "nios_system_rsp_xbar_mux" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux" +Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb" +Info (12128): Elaborating entity "nios_system_rsp_xbar_mux_001" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001" +Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb" +Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "nios_system:NiosII|nios_system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +Info (12128): Elaborating entity "nios_system_irq_mapper" for hierarchy "nios_system:NiosII|nios_system_irq_mapper:irq_mapper" +Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[0]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[0]" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[1]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[1]" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[2]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[2]" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[3]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[3]" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[4]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[4]" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[5]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[5]" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[6]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[6]" into an OR gate + Warning (13047): Converted the fan-out from the tri-state buffer "nios_system:NiosII|nios_system_lcd_16207_0:lcd_16207_0|LCD_data[7]" to the node "nios_system:NiosII|altera_merlin_slave_translator:lcd_16207_0_control_slave_translator|av_readdata_pre[7]" into an OR gate +Info (13000): Registers with preset signals will power-up high +Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Info (286031): Timing-Driven Synthesis is running on partition "Top" +Info (17049): 166 registers lost all their fanouts during netlist optimizations. +Info (13000): Registers with preset signals will power-up high +Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "sld_hub:auto_hub|receive[0][0]" is stuck at GND +Info (286031): Timing-Driven Synthesis is running on partition "sld_hub:auto_hub" +Info (144001): Generated suppressed messages file C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 2878 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 26 input pins + Info (21059): Implemented 96 output pins + Info (21061): Implemented 2419 logic cells + Info (21064): Implemented 336 RAM segments +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 150 warnings + Info: Peak virtual memory: 657 megabytes + Info: Processing ended: Thu Dec 22 10:07:53 2016 + Info: Elapsed time: 00:00:40 + Info: Total CPU time (on all processors): 00:00:36 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in C:/Users/takayun/Documents/DE2-115/qsys_tutorial/output_files/lights.map.smsg. + + diff --git a/output_files/lights.map.smsg b/output_files/lights.map.smsg index e539087..9cb4eec 100644 --- a/output_files/lights.map.smsg +++ b/output_files/lights.map.smsg @@ -1,12 +1,12 @@ -Info (10281): Verilog HDL Declaration information at nios_system_addr_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_addr_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope -Info (10281): Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant -Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant +Info (10281): Verilog HDL Declaration information at nios_system_addr_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope +Info (10281): Verilog HDL Declaration information at nios_system_addr_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope +Info (10281): Verilog HDL Declaration information at nios_system_addr_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope +Info (10281): Verilog HDL Declaration information at nios_system_addr_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope +Info (10281): Verilog HDL Declaration information at nios_system_id_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope +Info (10281): Verilog HDL Declaration information at nios_system_id_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope +Info (10281): Verilog HDL Declaration information at nios_system_id_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope +Info (10281): Verilog HDL Declaration information at nios_system_id_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope +Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1567): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1569): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(1725): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at nios_system_nios2_processor.v(2553): conditional expression evaluates to a constant diff --git a/output_files/lights.map.summary b/output_files/lights.map.summary index 590a392..cc7c897 100644 --- a/output_files/lights.map.summary +++ b/output_files/lights.map.summary @@ -1,14 +1,14 @@ -Analysis & Synthesis Status : Successful - Fri Dec 02 01:32:41 2016 -Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -Revision Name : lights -Top-level Entity Name : lights -Family : Cyclone IV E -Total logic elements : 2,333 - Total combinational functions : 2,058 - Dedicated logic registers : 1,212 -Total registers : 1212 -Total pins : 118 -Total virtual pins : 0 -Total memory bits : 1,649,664 -Embedded Multiplier 9-bit elements : 0 -Total PLLs : 0 +Analysis & Synthesis Status : Successful - Thu Dec 22 10:07:53 2016 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : lights +Top-level Entity Name : lights +Family : Cyclone IV E +Total logic elements : 2,331 + Total combinational functions : 2,056 + Dedicated logic registers : 1,212 +Total registers : 1212 +Total pins : 118 +Total virtual pins : 0 +Total memory bits : 1,649,664 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/output_files/lights.pin b/output_files/lights.pin index 3b89a2b..d64e56b 100644 --- a/output_files/lights.pin +++ b/output_files/lights.pin @@ -1,850 +1,850 @@ - -- Copyright (C) 1991-2013 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 3.3V - -- Bank 5: 2.5V - -- Bank 6: 2.5V - -- Bank 7: 2.5V - -- Bank 8: 2.5V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -CHIP "lights" ASSIGNED TO AN: EP4CE115F29C7 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -VCCIO8 : A2 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : -VCCIO8 : A5 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : -VCCIO8 : A9 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 : -VCCIO8 : A13 : power : : 2.5V : 8 : -GND+ : A14 : : : : 8 : -GND+ : A15 : : : : 7 : -VCCIO7 : A16 : power : : 2.5V : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : -VCCIO7 : A20 : power : : 2.5V : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 : -VCCIO7 : A24 : power : : 2.5V : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 : -VCCIO7 : A27 : power : : 2.5V : 7 : -VCCIO2 : AA1 : power : : 3.3V : 2 : -GND : AA2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : -GNDA1 : AA9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : -VCCIO3 : AA11 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 : -HEX7[6] : AA14 : output : 3.3-V LVTTL : : 3 : Y -HEX6[5] : AA15 : output : 3.3-V LVTTL : : 4 : Y -HEX6[2] : AA16 : output : 3.3-V LVTTL : : 4 : Y -HEX6[0] : AA17 : output : 3.3-V LVTTL : : 4 : Y -VCCIO4 : AA18 : power : : 3.3V : 4 : -HEX4[1] : AA19 : output : 3.3-V LVTTL : : 4 : Y -GNDA4 : AA20 : gnd : : : : -HEX3[3] : AA21 : output : 3.3-V LVTTL : : 4 : Y -SW[15] : AA22 : input : 2.5 V : : 5 : Y -SW[14] : AA23 : input : 2.5 V : : 5 : Y -SW[13] : AA24 : input : 2.5 V : : 5 : Y -HEX2[0] : AA25 : output : 2.5 V : : 5 : Y -HEX2[1] : AA26 : output : 2.5 V : : 5 : Y -GND : AA27 : gnd : : : : -VCCIO5 : AA28 : power : : 2.5V : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 : -HEX6[4] : AB15 : output : 3.3-V LVTTL : : 4 : Y -HEX6[1] : AB16 : output : 3.3-V LVTTL : : 4 : Y -HEX6[3] : AB17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[2] : AB18 : output : 3.3-V LVTTL : : 4 : Y -HEX4[0] : AB19 : output : 3.3-V LVTTL : : 4 : Y -HEX3[2] : AB20 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 : -SW[12] : AB23 : input : 2.5 V : : 5 : Y -SW[11] : AB24 : input : 2.5 V : : 5 : Y -SW[9] : AB25 : input : 2.5 V : : 5 : Y -SW[7] : AB26 : input : 2.5 V : : 5 : Y -SW[4] : AB27 : input : 2.5 V : : 5 : Y -SW[0] : AB28 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 : -GND : AC6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 : -GND : AC9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 : -GND : AC13 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 : -GND : AC16 : gnd : : : : -HEX6[6] : AC17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[1] : AC18 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 : -GND : AC20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 : -GND : AC23 : gnd : : : : -SW[10] : AC24 : input : 2.5 V : : 5 : Y -SW[8] : AC25 : input : 2.5 V : : 5 : Y -SW[5] : AC26 : input : 2.5 V : : 5 : Y -SW[2] : AC27 : input : 2.5 V : : 5 : Y -SW[1] : AC28 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 : -VCCIO3 : AD6 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 : -VCCIO3 : AD9 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 : -VCCIO3 : AD13 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 : -VCCIO4 : AD16 : power : : 3.3V : 4 : -HEX7[0] : AD17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[0] : AD18 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 : -VCCIO4 : AD20 : power : : 3.3V : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 : -VCCIO4 : AD23 : power : : 3.3V : 4 : -HEX3[4] : AD24 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 : -SW[6] : AD26 : input : 2.5 V : : 5 : Y -SW[3] : AD27 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 : -HEX7[1] : AE17 : output : 3.3-V LVTTL : : 4 : Y -HEX4[6] : AE18 : output : 3.3-V LVTTL : : 4 : Y -HEX4[4] : AE19 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 : -GND : AF1 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 : -HEX7[4] : AF17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[5] : AF18 : output : 3.3-V LVTTL : : 4 : Y -HEX4[5] : AF19 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 : -HEX3[5] : AF23 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 : -GND : AF28 : gnd : : : : -VCCIO2 : AG1 : power : : 3.3V : 2 : -GND : AG2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 : -GND : AG5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 : -GND : AG9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 : -GND : AG13 : gnd : : : : -GND+ : AG14 : : : : 3 : -GND+ : AG15 : : : : 4 : -GND : AG16 : gnd : : : : -HEX7[2] : AG17 : output : 3.3-V LVTTL : : 4 : Y -HEX7[5] : AG18 : output : 3.3-V LVTTL : : 4 : Y -HEX5[4] : AG19 : output : 3.3-V LVTTL : : 4 : Y -GND : AG20 : gnd : : : : -HEX4[2] : AG21 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 : -GND : AG24 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 : -GND : AG27 : gnd : : : : -VCCIO5 : AG28 : power : : 2.5V : 5 : -VCCIO3 : AH2 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 : -VCCIO3 : AH5 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 : -VCCIO3 : AH9 : power : : 3.3V : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 : -VCCIO3 : AH13 : power : : 3.3V : 3 : -GND+ : AH14 : : : : 3 : -GND+ : AH15 : : : : 4 : -VCCIO4 : AH16 : power : : 3.3V : 4 : -HEX7[3] : AH17 : output : 3.3-V LVTTL : : 4 : Y -HEX5[6] : AH18 : output : 3.3-V LVTTL : : 4 : Y -HEX5[3] : AH19 : output : 3.3-V LVTTL : : 4 : Y -VCCIO4 : AH20 : power : : 3.3V : 4 : -HEX4[3] : AH21 : output : 3.3-V LVTTL : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 : -VCCIO4 : AH24 : power : : 3.3V : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 : -VCCIO4 : AH27 : power : : 3.3V : 4 : -VCCIO1 : B1 : power : : 3.3V : 1 : -GND : B2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : -GND : B5 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : -GND : B9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 : -GND : B12 : gnd : : : : -GND : B13 : gnd : : : : -GND+ : B14 : : : : 8 : -GND+ : B15 : : : : 7 : -GND : B16 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : -GND : B20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 : -GND : B24 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 : -GND : B27 : gnd : : : : -VCCIO6 : B28 : power : : 2.5V : 6 : -GND : C1 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 : -GND : C28 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 : -GND : D3 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 : -~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : -VCCIO8 : E6 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : -VCCIO8 : E9 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 : -VCCIO8 : E13 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : -VCCIO7 : E16 : power : : 2.5V : 7 : -HEX0[2] : E17 : output : 2.5 V : : 7 : Y -LEDR[5] : E18 : output : 2.5 V : : 7 : Y -LEDR[2] : E19 : output : 2.5 V : : 7 : Y -VCCIO7 : E20 : power : : 2.5V : 7 : -LEDG[0] : E21 : output : 2.5 V : : 7 : Y -LEDG[1] : E22 : output : 2.5 V : : 7 : Y -VCCIO7 : E23 : power : : 2.5V : 7 : -LEDG[3] : E24 : output : 2.5 V : : 7 : Y -LEDG[2] : E25 : output : 2.5 V : : 7 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 : -~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : -GND : F6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : -GND : F9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 : -GND : F13 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 : -LEDR[14] : F15 : output : 2.5 V : : 7 : Y -GND : F16 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 : -LEDR[4] : F18 : output : 2.5 V : : 7 : Y -LEDR[1] : F19 : output : 2.5 V : : 7 : Y -GND : F20 : gnd : : : : -LEDR[3] : F21 : output : 2.5 V : : 7 : Y -HEX0[1] : F22 : output : 2.5 V : : 7 : Y -GND : F23 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 : -LEDR[15] : G15 : output : 2.5 V : : 7 : Y -LEDR[16] : G16 : output : 2.5 V : : 7 : Y -LEDR[9] : G17 : output : 2.5 V : : 7 : Y -HEX0[0] : G18 : output : 2.5 V : : 7 : Y -LEDR[0] : G19 : output : 2.5 V : : 7 : Y -LEDG[5] : G20 : output : 2.5 V : : 7 : Y -LEDG[7] : G21 : output : 2.5 V : : 7 : Y -LEDG[6] : G22 : output : 2.5 V : : 7 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 : -VCCIO1 : H1 : power : : 3.3V : 1 : -GND : H2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 : -GNDA3 : H9 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 : -VCCIO8 : H11 : power : : 2.5V : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 : -LEDR[17] : H15 : output : 2.5 V : : 7 : Y -LEDR[11] : H16 : output : 2.5 V : : 7 : Y -LEDR[13] : H17 : output : 2.5 V : : 7 : Y -VCCIO7 : H18 : power : : 2.5V : 7 : -LEDR[7] : H19 : output : 2.5 V : : 7 : Y -GNDA2 : H20 : gnd : : : : -LEDG[4] : H21 : output : 2.5 V : : 7 : Y -HEX0[6] : H22 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 : -GND : H27 : gnd : : : : -VCCIO6 : H28 : power : : 2.5V : 6 : -GND+ : J1 : : : : 1 : -GND : J2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 : -VCCA3 : J8 : power : : 2.5V : : -VCCD_PLL3 : J9 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : -GND : J11 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 : -LEDR[10] : J15 : output : 2.5 V : : 7 : Y -LEDR[12] : J16 : output : 2.5 V : : 7 : Y -LEDR[8] : J17 : output : 2.5 V : : 7 : Y -GND : J18 : gnd : : : : -LEDR[6] : J19 : output : 2.5 V : : 7 : Y -VCCD_PLL2 : J20 : power : : 1.2V : : -VCCA2 : J21 : power : : 2.5V : : -HEX0[5] : J22 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 : -GND+ : J27 : : : : 6 : -GND+ : J28 : : : : 6 : -LCD_data[4] : K1 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[5] : K2 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 : -VCCIO1 : K5 : power : : 3.3V : 1 : -GND : K6 : gnd : : : : -LCD_data[3] : K7 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 : -VCCINT : K9 : power : : 1.2V : : -GND : K10 : gnd : : : : -VCCINT : K11 : power : : 1.2V : : -GND : K12 : gnd : : : : -VCCINT : K13 : power : : 1.2V : : -GND : K14 : gnd : : : : -VCCINT : K15 : power : : 1.2V : : -GND : K16 : gnd : : : : -VCCINT : K17 : power : : 1.2V : : -GND : K18 : gnd : : : : -VCCINT : K19 : power : : 1.2V : : -GND : K20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : -GND : K23 : gnd : : : : -VCCIO6 : K24 : power : : 2.5V : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 : -LCD_data[1] : L1 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[2] : L2 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[0] : L3 : output : 3.3-V LVTTL : : 1 : Y -LCD_EN : L4 : output : 3.3-V LVTTL : : 1 : Y -LCD_ON : L5 : output : 3.3-V LVTTL : : 1 : Y -LCD_BLON : L6 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 : -GND : L9 : gnd : : : : -VCCINT : L10 : power : : 1.2V : : -GND : L11 : gnd : : : : -VCCINT : L12 : power : : 1.2V : : -GND : L13 : gnd : : : : -VCCINT : L14 : power : : 1.2V : : -GND : L15 : gnd : : : : -VCCINT : L16 : power : : 1.2V : : -GND : L17 : gnd : : : : -VCCINT : L18 : power : : 1.2V : : -GND : L19 : gnd : : : : -VCCINT : L20 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 : -HEX0[4] : L25 : output : 2.5 V : : 6 : Y -HEX0[3] : L26 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 : -LCD_RW : M1 : output : 3.3-V LVTTL : : 1 : Y -LCD_RS : M2 : output : 3.3-V LVTTL : : 1 : Y -LCD_data[6] : M3 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 : -LCD_data[7] : M5 : output : 3.3-V LVTTL : : 1 : Y -nSTATUS : M6 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 : -VCCINT : M9 : power : : 1.2V : : -GND : M10 : gnd : : : : -VCCINT : M11 : power : : 1.2V : : -GND : M12 : gnd : : : : -VCCINT : M13 : power : : 1.2V : : -GND : M14 : gnd : : : : -VCCINT : M15 : power : : 1.2V : : -GND : M16 : gnd : : : : -VCCINT : M17 : power : : 1.2V : : -GND : M18 : gnd : : : : -VCCINT : M19 : power : : 1.2V : : -GND : M20 : gnd : : : : -KEY[1] : M21 : input : 2.5 V : : 6 : Y -MSEL2 : M22 : : : : 6 : -KEY[0] : M23 : input : 2.5 V : : 6 : Y -HEX1[0] : M24 : output : 2.5 V : : 6 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 : -VCCIO1 : N1 : power : : 3.3V : 1 : -GND : N2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 : -VCCIO1 : N5 : power : : 3.3V : 1 : -GND : N6 : gnd : : : : -~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 3.3-V LVTTL : : 1 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 : -GND : N9 : gnd : : : : -VCCINT : N10 : power : : 1.2V : : -GND : N11 : gnd : : : : -VCCINT : N12 : power : : 1.2V : : -GND : N13 : gnd : : : : -VCCINT : N14 : power : : 1.2V : : -GND : N15 : gnd : : : : -VCCINT : N16 : power : : 1.2V : : -GND : N17 : gnd : : : : -VCCINT : N18 : power : : 1.2V : : -GND : N19 : gnd : : : : -VCCINT : N20 : power : : 1.2V : : -KEY[2] : N21 : input : 2.5 V : : 6 : Y -MSEL0 : N22 : : : : 6 : -GND : N23 : gnd : : : : -VCCIO6 : N24 : power : : 2.5V : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 : -GND : N27 : gnd : : : : -VCCIO6 : N28 : power : : 2.5V : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 : -~ALTERA_DCLK~ : P3 : output : 3.3-V LVTTL : : 1 : N -nCONFIG : P4 : : : : 1 : -altera_reserved_tck : P5 : input : 3.3-V LVTTL : : 1 : N -altera_reserved_tdo : P6 : output : 3.3-V LVTTL : : 1 : N -altera_reserved_tdi : P7 : input : 3.3-V LVTTL : : 1 : N -altera_reserved_tms : P8 : input : 3.3-V LVTTL : : 1 : N -VCCINT : P9 : power : : 1.2V : : -GND : P10 : gnd : : : : -VCCINT : P11 : power : : 1.2V : : -GND : P12 : gnd : : : : -VCCINT : P13 : power : : 1.2V : : -GND : P14 : gnd : : : : -VCCINT : P15 : power : : 1.2V : : -GND : P16 : gnd : : : : -VCCINT : P17 : power : : 1.2V : : -GND : P18 : gnd : : : : -VCCINT : P19 : power : : 1.2V : : -GND : P20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : -MSEL3 : P22 : : : : 6 : -MSEL1 : P23 : : : : 6 : -CONF_DONE : P24 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 : -~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N -RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : -nCE : R8 : : : : 1 : -GND : R9 : gnd : : : : -VCCINT : R10 : power : : 1.2V : : -GND : R11 : gnd : : : : -VCCINT : R12 : power : : 1.2V : : -GND : R13 : gnd : : : : -VCCINT : R14 : power : : 1.2V : : -GND : R15 : gnd : : : : -VCCINT : R16 : power : : 1.2V : : -GND : R17 : gnd : : : : -VCCINT : R18 : power : : 1.2V : : -GND : R19 : gnd : : : : -VCCINT : R20 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 : -KEY[3] : R24 : input : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 : -VCCIO2 : T1 : power : : 3.3V : 2 : -GND : T2 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 : -VCCIO2 : T5 : power : : 3.3V : 2 : -GND : T6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 : -VCCINT : T9 : power : : 1.2V : : -GND : T10 : gnd : : : : -VCCINT : T11 : power : : 1.2V : : -GND : T12 : gnd : : : : -VCCINT : T13 : power : : 1.2V : : -GND : T14 : gnd : : : : -VCCINT : T15 : power : : 1.2V : : -GND : T16 : gnd : : : : -VCCINT : T17 : power : : 1.2V : : -GND : T18 : gnd : : : : -VCCINT : T19 : power : : 1.2V : : -GND : T20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : -GND : T23 : gnd : : : : -VCCIO5 : T24 : power : : 2.5V : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 : -GND : T27 : gnd : : : : -VCCIO5 : T28 : power : : 2.5V : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 : -GND : U9 : gnd : : : : -VCCINT : U10 : power : : 1.2V : : -GND : U11 : gnd : : : : -VCCINT : U12 : power : : 1.2V : : -GND : U13 : gnd : : : : -VCCINT : U14 : power : : 1.2V : : -GND : U15 : gnd : : : : -VCCINT : U16 : power : : 1.2V : : -GND : U17 : gnd : : : : -VCCINT : U18 : power : : 1.2V : : -GND : U19 : gnd : : : : -VCCINT : U20 : power : : 1.2V : : -HEX3[1] : U21 : output : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : -HEX1[5] : U23 : output : 2.5 V : : 5 : Y -HEX1[6] : U24 : output : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 : -VCCINT : V9 : power : : 1.2V : : -GND : V10 : gnd : : : : -VCCINT : V11 : power : : 1.2V : : -GND : V12 : gnd : : : : -VCCINT : V13 : power : : 1.2V : : -GND : V14 : gnd : : : : -VCCINT : V15 : power : : 1.2V : : -GND : V16 : gnd : : : : -VCCINT : V17 : power : : 1.2V : : -GND : V18 : gnd : : : : -VCCINT : V19 : power : : 1.2V : : -GND : V20 : gnd : : : : -HEX3[0] : V21 : output : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 : -VCCIO2 : W5 : power : : 3.3V : 2 : -GND : W6 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 : -GND : W9 : gnd : : : : -VCCINT : W10 : power : : 1.2V : : -GND : W11 : gnd : : : : -VCCINT : W12 : power : : 1.2V : : -GND : W13 : gnd : : : : -VCCINT : W14 : power : : 1.2V : : -GND : W15 : gnd : : : : -VCCINT : W16 : power : : 1.2V : : -GND : W17 : gnd : : : : -VCCINT : W18 : power : : 1.2V : : -GND : W19 : gnd : : : : -VCCINT : W20 : power : : 1.2V : : -HEX1[2] : W21 : output : 2.5 V : : 5 : Y -HEX1[3] : W22 : output : 2.5 V : : 5 : Y -GND : W23 : gnd : : : : -VCCIO5 : W24 : power : : 2.5V : 5 : -HEX1[4] : W25 : output : 2.5 V : : 5 : Y -HEX2[3] : W26 : output : 2.5 V : : 5 : Y -HEX2[5] : W27 : output : 2.5 V : : 5 : Y -HEX2[6] : W28 : output : 2.5 V : : 5 : Y -GND+ : Y1 : : : : 2 : -CLOCK_50 : Y2 : input : 3.3-V LVTTL : : 2 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 : -VCCA1 : Y8 : power : : 2.5V : : -VCCD_PLL1 : Y9 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : -GND : Y11 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : -GND : Y18 : gnd : : : : -HEX3[6] : Y19 : output : 3.3-V LVTTL : : 4 : Y -VCCD_PLL4 : Y20 : power : : 1.2V : : -VCCA4 : Y21 : power : : 2.5V : : -HEX1[1] : Y22 : output : 2.5 V : : 5 : Y -SW[17] : Y23 : input : 2.5 V : : 5 : Y -SW[16] : Y24 : input : 2.5 V : : 5 : Y -HEX2[2] : Y25 : output : 2.5 V : : 5 : Y -HEX2[4] : Y26 : output : 2.5 V : : 5 : Y -GND+ : Y27 : : : : 5 : -GND+ : Y28 : : : : 5 : + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "lights" ASSIGNED TO AN: EP4CE115F29C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A2 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +VCCIO8 : A5 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : +VCCIO8 : A9 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 : +VCCIO8 : A13 : power : : 2.5V : 8 : +GND+ : A14 : : : : 8 : +GND+ : A15 : : : : 7 : +VCCIO7 : A16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 : +VCCIO7 : A20 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 : +VCCIO7 : A24 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 : +VCCIO7 : A27 : power : : 2.5V : 7 : +VCCIO2 : AA1 : power : : 3.3V : 2 : +GND : AA2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 : +GNDA1 : AA9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 : +VCCIO3 : AA11 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 : +HEX7[6] : AA14 : output : 3.3-V LVTTL : : 3 : Y +HEX6[5] : AA15 : output : 3.3-V LVTTL : : 4 : Y +HEX6[2] : AA16 : output : 3.3-V LVTTL : : 4 : Y +HEX6[0] : AA17 : output : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AA18 : power : : 3.3V : 4 : +HEX4[1] : AA19 : output : 3.3-V LVTTL : : 4 : Y +GNDA4 : AA20 : gnd : : : : +HEX3[3] : AA21 : output : 3.3-V LVTTL : : 4 : Y +SW[15] : AA22 : input : 2.5 V : : 5 : Y +SW[14] : AA23 : input : 2.5 V : : 5 : Y +SW[13] : AA24 : input : 2.5 V : : 5 : Y +HEX2[0] : AA25 : output : 2.5 V : : 5 : Y +HEX2[1] : AA26 : output : 2.5 V : : 5 : Y +GND : AA27 : gnd : : : : +VCCIO5 : AA28 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 : +HEX6[4] : AB15 : output : 3.3-V LVTTL : : 4 : Y +HEX6[1] : AB16 : output : 3.3-V LVTTL : : 4 : Y +HEX6[3] : AB17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[2] : AB18 : output : 3.3-V LVTTL : : 4 : Y +HEX4[0] : AB19 : output : 3.3-V LVTTL : : 4 : Y +HEX3[2] : AB20 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 : +SW[12] : AB23 : input : 2.5 V : : 5 : Y +SW[11] : AB24 : input : 2.5 V : : 5 : Y +SW[9] : AB25 : input : 2.5 V : : 5 : Y +SW[7] : AB26 : input : 2.5 V : : 5 : Y +SW[4] : AB27 : input : 2.5 V : : 5 : Y +SW[0] : AB28 : input : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 : +GND : AC6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 : +GND : AC9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 : +GND : AC13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 : +GND : AC16 : gnd : : : : +HEX6[6] : AC17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[1] : AC18 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 : +GND : AC20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 : +GND : AC23 : gnd : : : : +SW[10] : AC24 : input : 2.5 V : : 5 : Y +SW[8] : AC25 : input : 2.5 V : : 5 : Y +SW[5] : AC26 : input : 2.5 V : : 5 : Y +SW[2] : AC27 : input : 2.5 V : : 5 : Y +SW[1] : AC28 : input : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 : +VCCIO3 : AD6 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 : +VCCIO3 : AD9 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 : +VCCIO3 : AD13 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 : +VCCIO4 : AD16 : power : : 3.3V : 4 : +HEX7[0] : AD17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[0] : AD18 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 : +VCCIO4 : AD20 : power : : 3.3V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 : +VCCIO4 : AD23 : power : : 3.3V : 4 : +HEX3[4] : AD24 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 : +SW[6] : AD26 : input : 2.5 V : : 5 : Y +SW[3] : AD27 : input : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 : +HEX7[1] : AE17 : output : 3.3-V LVTTL : : 4 : Y +HEX4[6] : AE18 : output : 3.3-V LVTTL : : 4 : Y +HEX4[4] : AE19 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 : +GND : AF1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 : +HEX7[4] : AF17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[5] : AF18 : output : 3.3-V LVTTL : : 4 : Y +HEX4[5] : AF19 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 : +HEX3[5] : AF23 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 : +GND : AF28 : gnd : : : : +VCCIO2 : AG1 : power : : 3.3V : 2 : +GND : AG2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 : +GND : AG5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 : +GND : AG9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 : +GND : AG13 : gnd : : : : +GND+ : AG14 : : : : 3 : +GND+ : AG15 : : : : 4 : +GND : AG16 : gnd : : : : +HEX7[2] : AG17 : output : 3.3-V LVTTL : : 4 : Y +HEX7[5] : AG18 : output : 3.3-V LVTTL : : 4 : Y +HEX5[4] : AG19 : output : 3.3-V LVTTL : : 4 : Y +GND : AG20 : gnd : : : : +HEX4[2] : AG21 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 : +GND : AG24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 : +GND : AG27 : gnd : : : : +VCCIO5 : AG28 : power : : 2.5V : 5 : +VCCIO3 : AH2 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 : +VCCIO3 : AH5 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 : +VCCIO3 : AH9 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 : +VCCIO3 : AH13 : power : : 3.3V : 3 : +GND+ : AH14 : : : : 3 : +GND+ : AH15 : : : : 4 : +VCCIO4 : AH16 : power : : 3.3V : 4 : +HEX7[3] : AH17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[6] : AH18 : output : 3.3-V LVTTL : : 4 : Y +HEX5[3] : AH19 : output : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AH20 : power : : 3.3V : 4 : +HEX4[3] : AH21 : output : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 : +VCCIO4 : AH24 : power : : 3.3V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 : +VCCIO4 : AH27 : power : : 3.3V : 4 : +VCCIO1 : B1 : power : : 3.3V : 1 : +GND : B2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +GND : B5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +GND : B9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 : +GND : B12 : gnd : : : : +GND : B13 : gnd : : : : +GND+ : B14 : : : : 8 : +GND+ : B15 : : : : 7 : +GND : B16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 : +GND : B20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 : +GND : B24 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 : +GND : B27 : gnd : : : : +VCCIO6 : B28 : power : : 2.5V : 6 : +GND : C1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 : +GND : C28 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 : +GND : D3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 : +VCCIO8 : E6 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +VCCIO8 : E9 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 : +VCCIO8 : E13 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 : +VCCIO7 : E16 : power : : 2.5V : 7 : +HEX0[2] : E17 : output : 2.5 V : : 7 : Y +LEDR[5] : E18 : output : 2.5 V : : 7 : Y +LEDR[2] : E19 : output : 2.5 V : : 7 : Y +VCCIO7 : E20 : power : : 2.5V : 7 : +LEDG[0] : E21 : output : 2.5 V : : 7 : Y +LEDG[1] : E22 : output : 2.5 V : : 7 : Y +VCCIO7 : E23 : power : : 2.5V : 7 : +LEDG[3] : E24 : output : 2.5 V : : 7 : Y +LEDG[2] : E25 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : +GND : F6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : +GND : F9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 : +GND : F13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 : +LEDR[14] : F15 : output : 2.5 V : : 7 : Y +GND : F16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 : +LEDR[4] : F18 : output : 2.5 V : : 7 : Y +LEDR[1] : F19 : output : 2.5 V : : 7 : Y +GND : F20 : gnd : : : : +LEDR[3] : F21 : output : 2.5 V : : 7 : Y +HEX0[1] : F22 : output : 2.5 V : : 7 : Y +GND : F23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 : +LEDR[15] : G15 : output : 2.5 V : : 7 : Y +LEDR[16] : G16 : output : 2.5 V : : 7 : Y +LEDR[9] : G17 : output : 2.5 V : : 7 : Y +HEX0[0] : G18 : output : 2.5 V : : 7 : Y +LEDR[0] : G19 : output : 2.5 V : : 7 : Y +LEDG[5] : G20 : output : 2.5 V : : 7 : Y +LEDG[7] : G21 : output : 2.5 V : : 7 : Y +LEDG[6] : G22 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 : +VCCIO1 : H1 : power : : 3.3V : 1 : +GND : H2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 : +GNDA3 : H9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 : +VCCIO8 : H11 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 : +LEDR[17] : H15 : output : 2.5 V : : 7 : Y +LEDR[11] : H16 : output : 2.5 V : : 7 : Y +LEDR[13] : H17 : output : 2.5 V : : 7 : Y +VCCIO7 : H18 : power : : 2.5V : 7 : +LEDR[7] : H19 : output : 2.5 V : : 7 : Y +GNDA2 : H20 : gnd : : : : +LEDG[4] : H21 : output : 2.5 V : : 7 : Y +HEX0[6] : H22 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 : +GND : H27 : gnd : : : : +VCCIO6 : H28 : power : : 2.5V : 6 : +GND+ : J1 : : : : 1 : +GND : J2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 : +VCCA3 : J8 : power : : 2.5V : : +VCCD_PLL3 : J9 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 : +GND : J11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 : +LEDR[10] : J15 : output : 2.5 V : : 7 : Y +LEDR[12] : J16 : output : 2.5 V : : 7 : Y +LEDR[8] : J17 : output : 2.5 V : : 7 : Y +GND : J18 : gnd : : : : +LEDR[6] : J19 : output : 2.5 V : : 7 : Y +VCCD_PLL2 : J20 : power : : 1.2V : : +VCCA2 : J21 : power : : 2.5V : : +HEX0[5] : J22 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 : +GND+ : J27 : : : : 6 : +GND+ : J28 : : : : 6 : +LCD_data[4] : K1 : output : 3.3-V LVTTL : : 1 : Y +LCD_data[5] : K2 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 : +VCCIO1 : K5 : power : : 3.3V : 1 : +GND : K6 : gnd : : : : +LCD_data[3] : K7 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +VCCINT : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCCINT : K13 : power : : 1.2V : : +GND : K14 : gnd : : : : +VCCINT : K15 : power : : 1.2V : : +GND : K16 : gnd : : : : +VCCINT : K17 : power : : 1.2V : : +GND : K18 : gnd : : : : +VCCINT : K19 : power : : 1.2V : : +GND : K20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +GND : K23 : gnd : : : : +VCCIO6 : K24 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 : +LCD_data[1] : L1 : output : 3.3-V LVTTL : : 1 : Y +LCD_data[2] : L2 : output : 3.3-V LVTTL : : 1 : Y +LCD_data[0] : L3 : output : 3.3-V LVTTL : : 1 : Y +LCD_EN : L4 : output : 3.3-V LVTTL : : 1 : Y +LCD_ON : L5 : output : 3.3-V LVTTL : : 1 : Y +LCD_BLON : L6 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 : +GND : L9 : gnd : : : : +VCCINT : L10 : power : : 1.2V : : +GND : L11 : gnd : : : : +VCCINT : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +GND : L15 : gnd : : : : +VCCINT : L16 : power : : 1.2V : : +GND : L17 : gnd : : : : +VCCINT : L18 : power : : 1.2V : : +GND : L19 : gnd : : : : +VCCINT : L20 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 : +HEX0[4] : L25 : output : 2.5 V : : 6 : Y +HEX0[3] : L26 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 : +LCD_RW : M1 : output : 3.3-V LVTTL : : 1 : Y +LCD_RS : M2 : output : 3.3-V LVTTL : : 1 : Y +LCD_data[6] : M3 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 : +LCD_data[7] : M5 : output : 3.3-V LVTTL : : 1 : Y +nSTATUS : M6 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +VCCINT : M11 : power : : 1.2V : : +GND : M12 : gnd : : : : +VCCINT : M13 : power : : 1.2V : : +GND : M14 : gnd : : : : +VCCINT : M15 : power : : 1.2V : : +GND : M16 : gnd : : : : +VCCINT : M17 : power : : 1.2V : : +GND : M18 : gnd : : : : +VCCINT : M19 : power : : 1.2V : : +GND : M20 : gnd : : : : +KEY[1] : M21 : input : 2.5 V : : 6 : Y +MSEL2 : M22 : : : : 6 : +KEY[0] : M23 : input : 2.5 V : : 6 : Y +HEX1[0] : M24 : output : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 : +VCCIO1 : N1 : power : : 3.3V : 1 : +GND : N2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 : +VCCIO1 : N5 : power : : 3.3V : 1 : +GND : N6 : gnd : : : : +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 3.3-V LVTTL : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 : +GND : N9 : gnd : : : : +VCCINT : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCCINT : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND : N15 : gnd : : : : +VCCINT : N16 : power : : 1.2V : : +GND : N17 : gnd : : : : +VCCINT : N18 : power : : 1.2V : : +GND : N19 : gnd : : : : +VCCINT : N20 : power : : 1.2V : : +KEY[2] : N21 : input : 2.5 V : : 6 : Y +MSEL0 : N22 : : : : 6 : +GND : N23 : gnd : : : : +VCCIO6 : N24 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 : +GND : N27 : gnd : : : : +VCCIO6 : N28 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 : +~ALTERA_DCLK~ : P3 : output : 3.3-V LVTTL : : 1 : N +nCONFIG : P4 : : : : 1 : +altera_reserved_tck : P5 : input : 3.3-V LVTTL : : 1 : N +altera_reserved_tdo : P6 : output : 3.3-V LVTTL : : 1 : N +altera_reserved_tdi : P7 : input : 3.3-V LVTTL : : 1 : N +altera_reserved_tms : P8 : input : 3.3-V LVTTL : : 1 : N +VCCINT : P9 : power : : 1.2V : : +GND : P10 : gnd : : : : +VCCINT : P11 : power : : 1.2V : : +GND : P12 : gnd : : : : +VCCINT : P13 : power : : 1.2V : : +GND : P14 : gnd : : : : +VCCINT : P15 : power : : 1.2V : : +GND : P16 : gnd : : : : +VCCINT : P17 : power : : 1.2V : : +GND : P18 : gnd : : : : +VCCINT : P19 : power : : 1.2V : : +GND : P20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +MSEL3 : P22 : : : : 6 : +MSEL1 : P23 : : : : 6 : +CONF_DONE : P24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 : +nCE : R8 : : : : 1 : +GND : R9 : gnd : : : : +VCCINT : R10 : power : : 1.2V : : +GND : R11 : gnd : : : : +VCCINT : R12 : power : : 1.2V : : +GND : R13 : gnd : : : : +VCCINT : R14 : power : : 1.2V : : +GND : R15 : gnd : : : : +VCCINT : R16 : power : : 1.2V : : +GND : R17 : gnd : : : : +VCCINT : R18 : power : : 1.2V : : +GND : R19 : gnd : : : : +VCCINT : R20 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 : +KEY[3] : R24 : input : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 : +VCCIO2 : T1 : power : : 3.3V : 2 : +GND : T2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 : +VCCIO2 : T5 : power : : 3.3V : 2 : +GND : T6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 : +VCCINT : T9 : power : : 1.2V : : +GND : T10 : gnd : : : : +VCCINT : T11 : power : : 1.2V : : +GND : T12 : gnd : : : : +VCCINT : T13 : power : : 1.2V : : +GND : T14 : gnd : : : : +VCCINT : T15 : power : : 1.2V : : +GND : T16 : gnd : : : : +VCCINT : T17 : power : : 1.2V : : +GND : T18 : gnd : : : : +VCCINT : T19 : power : : 1.2V : : +GND : T20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +GND : T23 : gnd : : : : +VCCIO5 : T24 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 : +GND : T27 : gnd : : : : +VCCIO5 : T28 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 : +GND : U9 : gnd : : : : +VCCINT : U10 : power : : 1.2V : : +GND : U11 : gnd : : : : +VCCINT : U12 : power : : 1.2V : : +GND : U13 : gnd : : : : +VCCINT : U14 : power : : 1.2V : : +GND : U15 : gnd : : : : +VCCINT : U16 : power : : 1.2V : : +GND : U17 : gnd : : : : +VCCINT : U18 : power : : 1.2V : : +GND : U19 : gnd : : : : +VCCINT : U20 : power : : 1.2V : : +HEX3[1] : U21 : output : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +HEX1[5] : U23 : output : 2.5 V : : 5 : Y +HEX1[6] : U24 : output : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 : +VCCINT : V9 : power : : 1.2V : : +GND : V10 : gnd : : : : +VCCINT : V11 : power : : 1.2V : : +GND : V12 : gnd : : : : +VCCINT : V13 : power : : 1.2V : : +GND : V14 : gnd : : : : +VCCINT : V15 : power : : 1.2V : : +GND : V16 : gnd : : : : +VCCINT : V17 : power : : 1.2V : : +GND : V18 : gnd : : : : +VCCINT : V19 : power : : 1.2V : : +GND : V20 : gnd : : : : +HEX3[0] : V21 : output : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 : +VCCIO2 : W5 : power : : 3.3V : 2 : +GND : W6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 : +GND : W9 : gnd : : : : +VCCINT : W10 : power : : 1.2V : : +GND : W11 : gnd : : : : +VCCINT : W12 : power : : 1.2V : : +GND : W13 : gnd : : : : +VCCINT : W14 : power : : 1.2V : : +GND : W15 : gnd : : : : +VCCINT : W16 : power : : 1.2V : : +GND : W17 : gnd : : : : +VCCINT : W18 : power : : 1.2V : : +GND : W19 : gnd : : : : +VCCINT : W20 : power : : 1.2V : : +HEX1[2] : W21 : output : 2.5 V : : 5 : Y +HEX1[3] : W22 : output : 2.5 V : : 5 : Y +GND : W23 : gnd : : : : +VCCIO5 : W24 : power : : 2.5V : 5 : +HEX1[4] : W25 : output : 2.5 V : : 5 : Y +HEX2[3] : W26 : output : 2.5 V : : 5 : Y +HEX2[5] : W27 : output : 2.5 V : : 5 : Y +HEX2[6] : W28 : output : 2.5 V : : 5 : Y +GND+ : Y1 : : : : 2 : +CLOCK_50 : Y2 : input : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 : +VCCA1 : Y8 : power : : 2.5V : : +VCCD_PLL1 : Y9 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 : +GND : Y11 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 : +GND : Y18 : gnd : : : : +HEX3[6] : Y19 : output : 3.3-V LVTTL : : 4 : Y +VCCD_PLL4 : Y20 : power : : 1.2V : : +VCCA4 : Y21 : power : : 2.5V : : +HEX1[1] : Y22 : output : 2.5 V : : 5 : Y +SW[17] : Y23 : input : 2.5 V : : 5 : Y +SW[16] : Y24 : input : 2.5 V : : 5 : Y +HEX2[2] : Y25 : output : 2.5 V : : 5 : Y +HEX2[4] : Y26 : output : 2.5 V : : 5 : Y +GND+ : Y27 : : : : 5 : +GND+ : Y28 : : : : 5 : diff --git a/output_files/lights.sof b/output_files/lights.sof index 64b093e..0e0d4db 100644 --- a/output_files/lights.sof +++ b/output_files/lights.sof Binary files differ diff --git a/output_files/lights.sta.rpt b/output_files/lights.sta.rpt index 11c1619..4872c07 100644 --- a/output_files/lights.sta.rpt +++ b/output_files/lights.sta.rpt @@ -1,2976 +1,2976 @@ -TimeQuest Timing Analyzer report for lights -Fri Dec 02 01:33:28 2016 -Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. TimeQuest Timing Analyzer Summary - 3. Parallel Compilation - 4. Clocks - 5. Slow 1200mV 85C Model Fmax Summary - 6. Timing Closure Recommendations - 7. Slow 1200mV 85C Model Setup Summary - 8. Slow 1200mV 85C Model Hold Summary - 9. Slow 1200mV 85C Model Recovery Summary - 10. Slow 1200mV 85C Model Removal Summary - 11. Slow 1200mV 85C Model Minimum Pulse Width Summary - 12. Slow 1200mV 85C Model Setup: 'altera_reserved_tck' - 13. Slow 1200mV 85C Model Hold: 'altera_reserved_tck' - 14. Slow 1200mV 85C Model Recovery: 'altera_reserved_tck' - 15. Slow 1200mV 85C Model Removal: 'altera_reserved_tck' - 16. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' - 17. Setup Times - 18. Hold Times - 19. Clock to Output Times - 20. Minimum Clock to Output Times - 21. MTBF Summary - 22. Synchronizer Summary - 23. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years - 24. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years - 25. Slow 1200mV 0C Model Fmax Summary - 26. Slow 1200mV 0C Model Setup Summary - 27. Slow 1200mV 0C Model Hold Summary - 28. Slow 1200mV 0C Model Recovery Summary - 29. Slow 1200mV 0C Model Removal Summary - 30. Slow 1200mV 0C Model Minimum Pulse Width Summary - 31. Slow 1200mV 0C Model Setup: 'altera_reserved_tck' - 32. Slow 1200mV 0C Model Hold: 'altera_reserved_tck' - 33. Slow 1200mV 0C Model Recovery: 'altera_reserved_tck' - 34. Slow 1200mV 0C Model Removal: 'altera_reserved_tck' - 35. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' - 36. Setup Times - 37. Hold Times - 38. Clock to Output Times - 39. Minimum Clock to Output Times - 40. MTBF Summary - 41. Synchronizer Summary - 42. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years - 43. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years - 44. Fast 1200mV 0C Model Setup Summary - 45. Fast 1200mV 0C Model Hold Summary - 46. Fast 1200mV 0C Model Recovery Summary - 47. Fast 1200mV 0C Model Removal Summary - 48. Fast 1200mV 0C Model Minimum Pulse Width Summary - 49. Fast 1200mV 0C Model Setup: 'altera_reserved_tck' - 50. Fast 1200mV 0C Model Hold: 'altera_reserved_tck' - 51. Fast 1200mV 0C Model Recovery: 'altera_reserved_tck' - 52. Fast 1200mV 0C Model Removal: 'altera_reserved_tck' - 53. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' - 54. Setup Times - 55. Hold Times - 56. Clock to Output Times - 57. Minimum Clock to Output Times - 58. MTBF Summary - 59. Synchronizer Summary - 60. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years - 61. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years - 62. Multicorner Timing Analysis Summary - 63. Setup Times - 64. Hold Times - 65. Clock to Output Times - 66. Minimum Clock to Output Times - 67. Board Trace Model Assignments - 68. Input Transition Times - 69. Signal Integrity Metrics (Slow 1200mv 0c Model) - 70. Signal Integrity Metrics (Slow 1200mv 85c Model) - 71. Signal Integrity Metrics (Fast 1200mv 0c Model) - 72. Setup Transfers - 73. Hold Transfers - 74. Recovery Transfers - 75. Removal Transfers - 76. Report TCCS - 77. Report RSKM - 78. Unconstrained Paths - 79. TimeQuest Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+----------------------------------------------------------------------------------------+ -; TimeQuest Timing Analyzer Summary ; -+--------------------+-------------------------------------------------------------------+ -; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; -; Revision Name ; lights ; -; Device Family ; Cyclone IV E ; -; Device Name ; EP4CE115F29C7 ; -; Timing Models ; Final ; -; Delay Model ; Combined ; -; Rise/Fall Delays ; Enabled ; -+--------------------+-------------------------------------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ -; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { altera_reserved_tck } ; -+---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ - - -+----------------------------------------------------------+ -; Slow 1200mV 85C Model Fmax Summary ; -+-----------+-----------------+---------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+---------------------+------+ -; 118.4 MHz ; 118.4 MHz ; altera_reserved_tck ; ; -+-----------+-----------------+---------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - ----------------------------------- -; Timing Closure Recommendations ; ----------------------------------- -HTML report is unavailable in plain text report export. - - -+----------------------------------------------+ -; Slow 1200mV 85C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 45.777 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 85C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.403 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Slow 1200mV 85C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 47.734 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 85C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 1.385 ; 0.000 ; -+---------------------+-------+---------------+ - - -+---------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width Summary ; -+---------------------+--------+--------------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+--------------------+ -; altera_reserved_tck ; 49.549 ; 0.000 ; -+---------------------+--------+--------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Setup: 'altera_reserved_tck' ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 45.777 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.163 ; 4.404 ; -; 45.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.163 ; 4.264 ; -; 46.569 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.173 ; 3.622 ; -; 46.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.160 ; 3.225 ; -; 46.971 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.160 ; 3.207 ; -; 47.096 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.160 ; 3.082 ; -; 47.127 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.167 ; 3.058 ; -; 47.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.166 ; 3.042 ; -; 47.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.166 ; 2.827 ; -; 47.380 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.160 ; 2.798 ; -; 47.492 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.159 ; 2.685 ; -; 47.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.161 ; 2.670 ; -; 47.707 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.159 ; 2.470 ; -; 47.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.161 ; 2.414 ; -; 47.907 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.162 ; 2.273 ; -; 47.987 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.161 ; 2.192 ; -; 48.269 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.160 ; 1.909 ; -; 48.929 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.167 ; 1.256 ; -; 95.214 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.731 ; -; 95.214 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.731 ; -; 95.214 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.731 ; -; 95.214 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.731 ; -; 95.214 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.731 ; -; 95.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 4.694 ; -; 95.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 4.694 ; -; 95.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 4.694 ; -; 95.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 4.694 ; -; 95.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 4.694 ; -; 95.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.572 ; -; 95.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.514 ; -; 95.495 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 4.445 ; -; 95.495 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 4.445 ; -; 95.495 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 4.445 ; -; 95.495 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 4.445 ; -; 95.495 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 4.445 ; -; 95.519 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 4.422 ; -; 95.519 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 4.422 ; -; 95.519 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 4.422 ; -; 95.519 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 4.422 ; -; 95.519 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 4.422 ; -; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.417 ; -; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.417 ; -; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.417 ; -; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.417 ; -; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.417 ; -; 95.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.417 ; -; 95.576 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.373 ; -; 95.576 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 4.373 ; -; 95.626 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.324 ; -; 95.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.266 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.693 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 4.241 ; -; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.223 ; -; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.223 ; -; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.223 ; -; 95.719 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.223 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.067 ; 4.186 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.765 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.185 ; -; 95.787 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.155 ; -; 95.787 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.155 ; -; 95.787 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.155 ; -; 95.787 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.155 ; -; 95.787 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.155 ; -; 95.809 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.141 ; -; 95.809 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 4.141 ; -; 95.819 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.123 ; -; 95.823 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.067 ; 4.128 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.117 ; -; 95.840 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.102 ; -; 95.840 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.102 ; -; 95.840 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.102 ; -; 95.840 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.102 ; -; 95.842 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 4.098 ; -; 95.854 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.088 ; -; 95.854 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.088 ; -; 95.854 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.088 ; -; 95.854 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.088 ; -; 95.854 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 4.088 ; -; 95.864 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.071 ; -; 95.864 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.071 ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Hold: 'altera_reserved_tck' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.403 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.669 ; -; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.669 ; -; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; -; 0.405 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.078 ; 0.669 ; -; 0.408 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.674 ; -; 0.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.674 ; -; 0.409 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.674 ; -; 0.409 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.674 ; -; 0.422 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.687 ; -; 0.424 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.689 ; -; 0.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.692 ; -; 0.429 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.694 ; -; 0.429 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.694 ; -; 0.430 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.696 ; -; 0.430 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.695 ; -; 0.431 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.696 ; -; 0.431 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.696 ; -; 0.431 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.696 ; -; 0.431 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.696 ; -; 0.432 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.697 ; -; 0.432 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.698 ; -; 0.433 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.698 ; -; 0.433 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.698 ; -; 0.436 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.702 ; -; 0.436 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.702 ; -; 0.436 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.701 ; -; 0.437 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.702 ; -; 0.437 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.702 ; -; 0.438 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.703 ; -; 0.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.704 ; -; 0.439 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.704 ; -; 0.439 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.704 ; -; 0.439 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.705 ; -; 0.440 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.705 ; -; 0.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.706 ; -; 0.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.707 ; -; 0.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.708 ; -; 0.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.708 ; -; 0.445 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.710 ; -; 0.452 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.718 ; -; 0.453 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.718 ; -; 0.453 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.718 ; -; 0.454 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.719 ; -; 0.462 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.727 ; -; 0.475 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.740 ; -; 0.555 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.820 ; -; 0.555 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.820 ; -; 0.555 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.820 ; -; 0.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.821 ; -; 0.557 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.822 ; -; 0.561 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.826 ; -; 0.576 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.842 ; -; 0.577 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.843 ; -; 0.577 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.842 ; -; 0.578 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.844 ; -; 0.584 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.849 ; -; 0.585 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.850 ; -; 0.591 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.857 ; -; 0.593 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.859 ; -; 0.597 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.863 ; -; 0.598 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.864 ; -; 0.600 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.865 ; -; 0.600 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.865 ; -; 0.600 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.866 ; -; 0.600 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.866 ; -; 0.601 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.866 ; -; 0.601 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.867 ; -; 0.602 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.868 ; -; 0.602 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.868 ; -; 0.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.869 ; -; 0.605 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.872 ; -; 0.608 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.873 ; -; 0.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.875 ; -; 0.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.875 ; -; 0.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.876 ; -; 0.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.876 ; -; 0.616 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.881 ; -; 0.624 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.889 ; -; 0.637 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.902 ; -; 0.637 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.903 ; -; 0.638 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.904 ; -; 0.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 0.905 ; -; 0.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.904 ; -; 0.639 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.904 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Recovery: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 47.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.160 ; 2.444 ; -; 47.994 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.165 ; 2.189 ; -; 48.268 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.166 ; 1.916 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.411 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.084 ; 2.523 ; -; 97.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.495 ; -; 97.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.495 ; -; 97.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.495 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.446 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.489 ; -; 97.459 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 2.483 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.395 ; -; 97.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.389 ; -; 97.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.389 ; -; 97.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.389 ; -; 97.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.389 ; -; 97.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.389 ; -; 97.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.389 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.743 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 2.193 ; -; 97.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.189 ; -; 97.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.189 ; -; 98.034 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.906 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.095 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.845 ; -; 98.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 1.826 ; -; 98.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 1.826 ; -; 98.116 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.076 ; 1.826 ; -; 98.145 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 1.794 ; -; 98.145 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 1.794 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -; 98.168 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 1.772 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Removal: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.651 ; -; 1.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.679 ; -; 1.413 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.679 ; -; 1.437 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 1.705 ; -; 1.437 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 1.705 ; -; 1.437 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 1.705 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.455 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.721 ; -; 1.480 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 1.746 ; -; 1.783 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.050 ; -; 1.783 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.050 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.798 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.077 ; 2.061 ; -; 1.982 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.085 ; 2.253 ; -; 1.982 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.085 ; 2.253 ; -; 1.982 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.085 ; 2.253 ; -; 1.982 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.085 ; 2.253 ; -; 1.982 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.085 ; 2.253 ; -; 1.982 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.085 ; 2.253 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 1.996 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.086 ; 2.268 ; -; 2.078 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.083 ; 2.347 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 2.362 ; -; 2.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.078 ; 2.373 ; -; 2.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.078 ; 2.373 ; -; 2.109 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.078 ; 2.373 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 2.125 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.385 ; -; 51.250 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.327 ; 1.763 ; -; 51.537 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.327 ; 2.050 ; -; 51.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.322 ; 2.314 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.549 ; 49.769 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; -; 49.549 ; 49.769 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; -; 49.549 ; 49.769 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; -; 49.600 ; 49.788 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.100 ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; -; 49.601 ; 49.789 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 5.966 ; 6.153 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 8.682 ; 8.853 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -1.018 ; -1.163 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -2.179 ; -2.292 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 16.072 ; 16.482 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 13.593 ; 14.008 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - ----------------- -; MTBF Summary ; ----------------- -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 2 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 -Worst Case Available Settling Time: 197.101 ns - -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 - - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Synchronizer Summary ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ - - -Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.101 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.150 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 97.951 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.313 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.148 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 98.165 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -+-----------------------------------------------------------+ -; Slow 1200mV 0C Model Fmax Summary ; -+------------+-----------------+---------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+------------+-----------------+---------------------+------+ -; 134.52 MHz ; 134.52 MHz ; altera_reserved_tck ; ; -+------------+-----------------+---------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+----------------------------------------------+ -; Slow 1200mV 0C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 46.283 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 0C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.353 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Slow 1200mV 0C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 48.047 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Slow 1200mV 0C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 1.278 ; 0.000 ; -+---------------------+-------+---------------+ - - -+--------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width Summary ; -+---------------------+--------+-------------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+-------------------+ -; altera_reserved_tck ; 49.476 ; 0.000 ; -+---------------------+--------+-------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Setup: 'altera_reserved_tck' ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 46.283 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.243 ; 3.979 ; -; 46.391 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.243 ; 3.871 ; -; 46.925 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.253 ; 3.347 ; -; 47.311 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.239 ; 2.947 ; -; 47.335 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.239 ; 2.923 ; -; 47.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.246 ; 2.830 ; -; 47.444 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.239 ; 2.814 ; -; 47.487 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.247 ; 2.779 ; -; 47.701 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.239 ; 2.557 ; -; 47.713 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.246 ; 2.552 ; -; 47.813 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.240 ; 2.446 ; -; 47.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.241 ; 2.395 ; -; 47.959 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.240 ; 2.300 ; -; 48.054 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.242 ; 2.207 ; -; 48.216 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.242 ; 2.045 ; -; 48.232 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.240 ; 2.027 ; -; 48.514 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.241 ; 1.746 ; -; 49.121 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.246 ; 1.144 ; -; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.351 ; -; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.351 ; -; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.351 ; -; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.351 ; -; 95.603 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.351 ; -; 95.636 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 4.319 ; -; 95.636 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 4.319 ; -; 95.636 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 4.319 ; -; 95.636 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 4.319 ; -; 95.636 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 4.319 ; -; 95.777 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.180 ; -; 95.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.127 ; -; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.083 ; -; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.083 ; -; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.083 ; -; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.083 ; -; 95.865 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.083 ; -; 95.872 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.085 ; -; 95.872 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.085 ; -; 95.872 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.085 ; -; 95.872 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.085 ; -; 95.872 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.085 ; -; 95.872 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.085 ; -; 95.898 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 4.051 ; -; 95.898 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 4.051 ; -; 95.898 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 4.051 ; -; 95.898 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 4.051 ; -; 95.898 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 4.051 ; -; 95.918 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.039 ; -; 95.918 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.039 ; -; 96.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.946 ; -; 96.031 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.919 ; -; 96.031 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.919 ; -; 96.031 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.919 ; -; 96.031 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.919 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.057 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.884 ; -; 96.065 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.893 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.101 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.857 ; -; 96.138 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.812 ; -; 96.138 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.812 ; -; 96.138 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.812 ; -; 96.138 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.812 ; -; 96.147 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.811 ; -; 96.147 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 3.811 ; -; 96.159 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 3.800 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.166 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 3.789 ; -; 96.182 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 3.765 ; -; 96.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 3.764 ; -; 96.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 3.764 ; -; 96.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 3.764 ; -; 96.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 3.764 ; -; 96.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 3.764 ; -; 96.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.069 ; 3.749 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -; 96.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 3.738 ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Hold: 'altera_reserved_tck' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; -; 0.355 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.071 ; 0.597 ; -; 0.364 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; -; 0.364 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; -; 0.364 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; -; 0.365 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.608 ; -; 0.381 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.624 ; -; 0.382 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.625 ; -; 0.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.628 ; -; 0.386 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.630 ; -; 0.393 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.637 ; -; 0.395 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.639 ; -; 0.395 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; -; 0.395 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; -; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.639 ; -; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.639 ; -; 0.396 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; -; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.640 ; -; 0.397 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.640 ; -; 0.397 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.641 ; -; 0.397 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.641 ; -; 0.398 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.641 ; -; 0.400 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.644 ; -; 0.400 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.644 ; -; 0.401 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.645 ; -; 0.401 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.645 ; -; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.646 ; -; 0.402 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.646 ; -; 0.403 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.647 ; -; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.647 ; -; 0.404 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.648 ; -; 0.404 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.647 ; -; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.649 ; -; 0.405 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.648 ; -; 0.406 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.650 ; -; 0.406 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.650 ; -; 0.408 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.652 ; -; 0.415 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.659 ; -; 0.415 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.659 ; -; 0.416 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.660 ; -; 0.417 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.660 ; -; 0.424 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.668 ; -; 0.434 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.678 ; -; 0.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.744 ; -; 0.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.744 ; -; 0.507 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.750 ; -; 0.507 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.751 ; -; 0.508 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.752 ; -; 0.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.756 ; -; 0.527 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.771 ; -; 0.528 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.772 ; -; 0.528 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.771 ; -; 0.529 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.773 ; -; 0.533 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.777 ; -; 0.534 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.778 ; -; 0.539 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.783 ; -; 0.540 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.784 ; -; 0.544 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.788 ; -; 0.547 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.791 ; -; 0.547 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 0.792 ; -; 0.547 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.791 ; -; 0.548 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.792 ; -; 0.548 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.791 ; -; 0.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.793 ; -; 0.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.793 ; -; 0.553 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.797 ; -; 0.554 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.798 ; -; 0.555 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.799 ; -; 0.555 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.798 ; -; 0.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.800 ; -; 0.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.799 ; -; 0.557 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.801 ; -; 0.559 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 0.804 ; -; 0.560 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 0.805 ; -; 0.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.811 ; -; 0.568 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.812 ; -; 0.579 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.823 ; -; 0.582 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.826 ; -; 0.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.826 ; -; 0.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.826 ; -; 0.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.826 ; -; 0.584 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.828 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Recovery: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 48.047 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.241 ; 2.213 ; -; 48.303 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.245 ; 1.961 ; -; 48.540 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.246 ; 1.725 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.663 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.279 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 2.262 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 2.262 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 2.262 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.685 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.077 ; 2.257 ; -; 97.707 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 2.244 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.778 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 2.176 ; -; 97.792 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 2.161 ; -; 97.792 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 2.161 ; -; 97.792 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 2.161 ; -; 97.792 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 2.161 ; -; 97.792 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 2.161 ; -; 97.792 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 2.161 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.968 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 1.977 ; -; 97.987 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.961 ; -; 97.987 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.961 ; -; 98.222 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.725 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.247 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.700 ; -; 98.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 1.643 ; -; 98.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 1.643 ; -; 98.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 1.643 ; -; 98.335 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.612 ; -; 98.335 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.072 ; 1.612 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -; 98.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.591 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Removal: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.523 ; -; 1.298 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.543 ; -; 1.298 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.543 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.306 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.550 ; -; 1.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.076 ; 1.560 ; -; 1.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.076 ; 1.560 ; -; 1.313 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.076 ; 1.560 ; -; 1.357 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 1.602 ; -; 1.633 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 1.879 ; -; 1.633 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.075 ; 1.879 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.650 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 1.893 ; -; 1.802 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 2.053 ; -; 1.802 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 2.053 ; -; 1.802 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 2.053 ; -; 1.802 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 2.053 ; -; 1.802 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 2.053 ; -; 1.802 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.080 ; 2.053 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.806 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 2.058 ; -; 1.882 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.078 ; 2.131 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.069 ; 2.141 ; -; 1.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.148 ; -; 1.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.148 ; -; 1.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.074 ; 2.148 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 1.929 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 2.168 ; -; 51.048 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.399 ; 1.618 ; -; 51.310 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.398 ; 1.879 ; -; 51.542 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.393 ; 2.106 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.476 ; 49.694 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; -; 49.476 ; 49.694 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.477 ; 49.695 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; -; 49.520 ; 49.706 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; -; 49.521 ; 49.707 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 5.681 ; 5.963 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 8.434 ; 8.616 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -1.039 ; -1.299 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -2.262 ; -2.479 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 15.072 ; 15.134 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 12.632 ; 12.709 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - ----------------- -; MTBF Summary ; ----------------- -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 2 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 -Worst Case Available Settling Time: 197.386 ns - -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 - - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Synchronizer Summary ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ - - -Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.386 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.236 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 98.150 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 197.573 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.233 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 98.340 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -+----------------------------------------------+ -; Fast 1200mV 0C Model Setup Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 48.270 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 1200mV 0C Model Hold Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.180 ; 0.000 ; -+---------------------+-------+---------------+ - - -+----------------------------------------------+ -; Fast 1200mV 0C Model Recovery Summary ; -+---------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+---------------+ -; altera_reserved_tck ; 49.194 ; 0.000 ; -+---------------------+--------+---------------+ - - -+---------------------------------------------+ -; Fast 1200mV 0C Model Removal Summary ; -+---------------------+-------+---------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+-------+---------------+ -; altera_reserved_tck ; 0.657 ; 0.000 ; -+---------------------+-------+---------------+ - - -+--------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width Summary ; -+---------------------+--------+-------------------+ -; Clock ; Slack ; End Point TNS ; -+---------------------+--------+-------------------+ -; altera_reserved_tck ; 49.301 ; 0.000 ; -+---------------------+--------+-------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Setup: 'altera_reserved_tck' ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 48.270 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.445 ; 2.182 ; -; 48.336 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.445 ; 2.116 ; -; 48.626 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.451 ; 1.832 ; -; 48.878 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 1.570 ; -; 48.895 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 1.553 ; -; 48.924 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 1.524 ; -; 48.928 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.448 ; 1.527 ; -; 48.959 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.448 ; 1.496 ; -; 49.044 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.448 ; 1.411 ; -; 49.077 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 1.371 ; -; 49.123 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.445 ; 1.329 ; -; 49.152 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.444 ; 1.299 ; -; 49.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.445 ; 1.279 ; -; 49.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.446 ; 1.186 ; -; 49.362 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.444 ; 1.089 ; -; 49.389 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.442 ; 1.060 ; -; 49.467 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.446 ; 0.986 ; -; 49.815 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.445 ; 0.637 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.378 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.378 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.378 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.378 ; -; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.378 ; -; 97.676 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.297 ; -; 97.676 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.297 ; -; 97.676 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.297 ; -; 97.676 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.297 ; -; 97.676 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.297 ; -; 97.681 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.296 ; -; 97.713 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.264 ; -; 97.745 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.222 ; -; 97.745 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.222 ; -; 97.745 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.222 ; -; 97.745 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.222 ; -; 97.745 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.222 ; -; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.178 ; -; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.178 ; -; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.178 ; -; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.178 ; -; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.178 ; -; 97.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.178 ; -; 97.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.163 ; -; 97.821 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.156 ; -; 97.821 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.030 ; 2.156 ; -; 97.826 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.141 ; -; 97.826 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.141 ; -; 97.826 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.141 ; -; 97.826 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.141 ; -; 97.826 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 2.141 ; -; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.134 ; -; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.134 ; -; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.134 ; -; 97.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.134 ; -; 97.847 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.131 ; -; 97.861 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.117 ; -; 97.877 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.092 ; -; 97.891 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.087 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.073 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.073 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.073 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.073 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.073 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.081 ; -; 97.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.068 ; -; 97.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.068 ; -; 97.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.068 ; -; 97.901 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.068 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.915 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.050 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.917 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.042 ; 2.048 ; -; 97.919 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.059 ; -; 97.919 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.059 ; -; 97.942 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.036 ; -; 97.942 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.036 ; -; 97.942 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.036 ; -; 97.942 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.036 ; -; 97.942 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.036 ; -; 97.942 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.029 ; 2.036 ; -; 97.943 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 2.026 ; -; 97.955 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 2.018 ; -+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Hold: 'altera_reserved_tck' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.180 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.043 ; 0.307 ; -; 0.181 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; -; 0.188 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.313 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.313 ; -; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; -; 0.189 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.314 ; -; 0.189 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.314 ; -; 0.189 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.314 ; -; 0.190 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.315 ; -; 0.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.315 ; -; 0.191 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.316 ; -; 0.191 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; -; 0.191 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; -; 0.191 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.316 ; -; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.316 ; -; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.316 ; -; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.316 ; -; 0.192 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.317 ; -; 0.192 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; -; 0.192 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.317 ; -; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.318 ; -; 0.193 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; -; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; -; 0.194 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.319 ; -; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.320 ; -; 0.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.319 ; -; 0.195 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.320 ; -; 0.195 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.320 ; -; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.321 ; -; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.322 ; -; 0.197 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.322 ; -; 0.198 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.323 ; -; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; -; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; -; 0.200 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.325 ; -; 0.201 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.326 ; -; 0.203 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.328 ; -; 0.207 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.332 ; -; 0.212 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.337 ; -; 0.248 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.373 ; -; 0.249 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.374 ; -; 0.250 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.375 ; -; 0.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.377 ; -; 0.252 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.377 ; -; 0.253 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.378 ; -; 0.256 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.382 ; -; 0.257 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.382 ; -; 0.260 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.385 ; -; 0.261 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.386 ; -; 0.261 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.386 ; -; 0.261 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.386 ; -; 0.261 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.386 ; -; 0.261 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.387 ; -; 0.262 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.387 ; -; 0.262 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.388 ; -; 0.262 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.388 ; -; 0.262 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.387 ; -; 0.263 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.389 ; -; 0.263 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.388 ; -; 0.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.389 ; -; 0.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.389 ; -; 0.265 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.390 ; -; 0.265 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.390 ; -; 0.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.391 ; -; 0.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.392 ; -; 0.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.393 ; -; 0.268 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.393 ; -; 0.269 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.394 ; -; 0.273 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.399 ; -; 0.276 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.401 ; -; 0.278 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.404 ; -; 0.278 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.403 ; -; 0.279 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.405 ; -; 0.279 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.405 ; -; 0.279 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.404 ; -; 0.280 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.406 ; -; 0.280 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.406 ; -; 0.280 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.406 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Recovery: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 49.194 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.446 ; 1.259 ; -; 49.350 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.448 ; 1.105 ; -; 49.484 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.448 ; 0.971 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.666 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.300 ; -; 98.680 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 1.291 ; -; 98.680 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 1.291 ; -; 98.680 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 1.291 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.684 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 1.282 ; -; 98.705 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 1.266 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.747 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.034 ; 1.226 ; -; 98.751 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.035 ; 1.221 ; -; 98.751 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.035 ; 1.221 ; -; 98.751 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.035 ; 1.221 ; -; 98.751 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.035 ; 1.221 ; -; 98.751 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.035 ; 1.221 ; -; 98.751 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.035 ; 1.221 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.831 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.138 ; -; 98.864 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.105 ; -; 98.864 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 1.105 ; -; 99.001 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.965 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.039 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.927 ; -; 99.050 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 0.919 ; -; 99.050 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 0.919 ; -; 99.050 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.038 ; 0.919 ; -; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.896 ; -; 99.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.896 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -; 99.081 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.040 ; 0.886 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Removal: 'altera_reserved_tck' ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.657 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.783 ; -; 0.664 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.790 ; -; 0.664 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.790 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.670 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.795 ; -; 0.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.811 ; -; 0.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.811 ; -; 0.683 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.811 ; -; 0.687 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.812 ; -; 0.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.963 ; -; 0.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.963 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.869 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.044 ; 0.997 ; -; 0.933 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.065 ; -; 0.933 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.065 ; -; 0.933 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.065 ; -; 0.933 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.065 ; -; 0.933 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.065 ; -; 0.933 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.065 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.941 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.048 ; 1.073 ; -; 0.969 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.047 ; 1.100 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.997 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.122 ; -; 0.999 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.047 ; 1.130 ; -; 0.999 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.047 ; 1.130 ; -; 0.999 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.047 ; 1.130 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 1.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 1.129 ; -; 50.227 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.535 ; 0.846 ; -; 50.344 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.535 ; 0.963 ; -; 50.490 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.533 ; 1.107 ; -+--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.301 ; 49.517 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; -; 49.301 ; 49.517 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.303 ; 49.519 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; -; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; -; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; -+--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 2.759 ; 3.054 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 3.650 ; 4.067 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -0.365 ; -0.660 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -0.709 ; -1.040 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 8.450 ; 9.059 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 7.186 ; 7.788 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - ----------------- -; MTBF Summary ; ----------------- -Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - -Number of Synchronizer Chains Found: 2 -Shortest Synchronizer Chain: 2 Registers -Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 -Worst Case Available Settling Time: 198.621 ns - -Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 - - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Synchronizer Summary ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ - - -Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 198.621 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.593 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 99.028 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years -=============================================================================== -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Chain Summary ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Property ; Value ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; -; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; -; Typical MTBF (years) ; Greater than 1 Billion ; -; Included in Design MTBF ; Yes ; -+-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ -; Method of Synchronizer Identification ; User Specified ; ; ; ; -; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; -; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 198.717 ; ; ; ; -; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; -; Source Clock ; ; ; ; ; -; Unknown ; ; ; ; ; -; Synchronization Clock ; ; ; ; ; -; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; -; Asynchronous Source ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; -; Synchronization Registers ; ; ; ; ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.591 ; -; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 99.126 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ - - - -+----------------------------------------------------------------------------------+ -; Multicorner Timing Analysis Summary ; -+----------------------+--------+-------+----------+---------+---------------------+ -; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; -+----------------------+--------+-------+----------+---------+---------------------+ -; Worst-case Slack ; 45.777 ; 0.180 ; 47.734 ; 0.657 ; 49.301 ; -; altera_reserved_tck ; 45.777 ; 0.180 ; 47.734 ; 0.657 ; 49.301 ; -; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -; altera_reserved_tck ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; -+----------------------+--------+-------+----------+---------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Setup Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 5.966 ; 6.153 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 8.682 ; 8.853 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Hold Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; -0.365 ; -0.660 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -0.709 ; -1.040 ; Rise ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------+ -; Clock to Output Times ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+--------+--------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 16.072 ; 16.482 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+--------+--------+------------+---------------------+ - - -+----------------------------------------------------------------------------------------------+ -; Minimum Clock to Output Times ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; -+---------------------+---------------------+-------+-------+------------+---------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 7.186 ; 7.788 ; Fall ; altera_reserved_tck ; -+---------------------+---------------------+-------+-------+------------+---------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Board Trace Model Assignments ; -+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; -+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ -; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDG[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LEDR[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX5[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX6[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; HEX7[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_RS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_RW ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_EN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_ON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; LCD_BLON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; -+---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ - - -+----------------------------------------------------------------------------+ -; Input Transition Times ; -+-------------------------+--------------+-----------------+-----------------+ -; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; -+-------------------------+--------------+-----------------+-----------------+ -; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ; -; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ; -; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; altera_reserved_tms ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; altera_reserved_tck ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; altera_reserved_tdi ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -+-------------------------+--------------+-----------------+-----------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1200mv 0c Model) ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; -; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; -; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; -; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; -; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; -; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; -; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; -; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; -; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; -; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; -; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; -; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; -; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; -; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; -; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; -; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 4.33e-08 V ; 3.11 V ; -0.0128 V ; 0.235 V ; 0.229 V ; 6.79e-10 s ; 1.6e-09 s ; Yes ; Yes ; 3.08 V ; 4.33e-08 V ; 3.11 V ; -0.0128 V ; 0.235 V ; 0.229 V ; 6.79e-10 s ; 1.6e-09 s ; Yes ; Yes ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.149 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.149 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Slow 1200mv 85c Model) ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; -; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; -; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; -; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; -; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; -; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; -; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; -; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; -; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; -; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; -; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; -; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; -; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; -; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; -; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; -; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.02e-06 V ; 3.09 V ; -0.00287 V ; 0.055 V ; 0.123 V ; 8.59e-10 s ; 2.03e-09 s ; Yes ; Yes ; 3.08 V ; 5.02e-06 V ; 3.09 V ; -0.00287 V ; 0.055 V ; 0.123 V ; 8.59e-10 s ; 2.03e-09 s ; Yes ; Yes ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Signal Integrity Metrics (Fast 1200mv 0c Model) ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; -; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; -; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; -; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; -; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; -; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; -; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; -; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; -; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; -; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; -; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; -; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; -; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; -; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; -; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; -; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; -; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 4.9e-07 V ; 3.52 V ; -0.0234 V ; 0.372 V ; 0.263 V ; 5.16e-10 s ; 1.44e-09 s ; No ; No ; 3.46 V ; 4.9e-07 V ; 3.52 V ; -0.0234 V ; 0.372 V ; 0.263 V ; 5.16e-10 s ; 1.44e-09 s ; No ; No ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; -; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; -+---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+---------------------------------------------------------------------------------------+ -; Setup Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 1728 ; 0 ; 32 ; 2 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------+ -; Hold Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 1728 ; 0 ; 32 ; 2 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------+ -; Recovery Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 81 ; 0 ; 3 ; 0 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------+ -; Removal Transfers ; -+---------------------+---------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+---------------------+---------------------+----------+----------+----------+----------+ -; altera_reserved_tck ; altera_reserved_tck ; 81 ; 0 ; 3 ; 0 ; -+---------------------+---------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 1 ; 1 ; -; Unconstrained Input Ports ; 24 ; 24 ; -; Unconstrained Input Port Paths ; 90 ; 90 ; -; Unconstrained Output Ports ; 96 ; 96 ; -; Unconstrained Output Port Paths ; 129 ; 129 ; -+---------------------------------+-------+------+ - - -+------------------------------------+ -; TimeQuest Timing Analyzer Messages ; -+------------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer - Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Fri Dec 02 01:33:22 2016 -Info: Command: quartus_sta lights -c lights -Info: qsta_default_script.tcl version: #1 -Warning (20028): Parallel compilation is not licensed and has been disabled -Info (21077): Core supply voltage is 1.2V -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (332164): Evaluating HDL-embedded SDC commands - Info (332165): Entity alt_jtag_atlantic - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] - Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] - Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] - Info (332165): Entity altera_std_synchronizer - Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] - Info (332165): Entity sld_jtag_hub - Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz - Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} -Critical Warning (332012): Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info: Analyzing Slow 1200mV 85C Model -Info (332146): Worst-case setup slack is 45.777 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 45.777 0.000 altera_reserved_tck -Info (332146): Worst-case hold slack is 0.403 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.403 0.000 altera_reserved_tck -Info (332146): Worst-case recovery slack is 47.734 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 47.734 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 1.385 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 1.385 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 49.549 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.549 0.000 altera_reserved_tck -Info (332114): Report Metastability: Found 2 synchronizer chains. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 2 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 - Info (332114): Worst Case Available Settling Time: 197.101 ns - Info (332114): - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 -Info: Analyzing Slow 1200mV 0C Model -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info (332146): Worst-case setup slack is 46.283 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 46.283 0.000 altera_reserved_tck -Info (332146): Worst-case hold slack is 0.353 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.353 0.000 altera_reserved_tck -Info (332146): Worst-case recovery slack is 48.047 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 48.047 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 1.278 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 1.278 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 49.476 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.476 0.000 altera_reserved_tck -Info (332114): Report Metastability: Found 2 synchronizer chains. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 2 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 - Info (332114): Worst Case Available Settling Time: 197.386 ns - Info (332114): - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 -Info: Analyzing Fast 1200mV 0C Model -Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. -Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) - Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) -Info (332146): Worst-case setup slack is 48.270 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 48.270 0.000 altera_reserved_tck -Info (332146): Worst-case hold slack is 0.180 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.180 0.000 altera_reserved_tck -Info (332146): Worst-case recovery slack is 49.194 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.194 0.000 altera_reserved_tck -Info (332146): Worst-case removal slack is 0.657 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 0.657 0.000 altera_reserved_tck -Info (332146): Worst-case minimum pulse width slack is 49.301 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= ============= ===================== - Info (332119): 49.301 0.000 altera_reserved_tck -Info (332114): Report Metastability: Found 2 synchronizer chains. - Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. - - Info (332114): Number of Synchronizer Chains Found: 2 - Info (332114): Shortest Synchronizer Chain: 2 Registers - Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 - Info (332114): Worst Case Available Settling Time: 198.621 ns - Info (332114): - Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings - Info: Peak virtual memory: 606 megabytes - Info: Processing ended: Fri Dec 02 01:33:28 2016 - Info: Elapsed time: 00:00:06 - Info: Total CPU time (on all processors): 00:00:05 - - +TimeQuest Timing Analyzer report for lights +Thu Dec 22 10:08:48 2016 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Setup: 'altera_reserved_tck' + 13. Slow 1200mV 85C Model Hold: 'altera_reserved_tck' + 14. Slow 1200mV 85C Model Recovery: 'altera_reserved_tck' + 15. Slow 1200mV 85C Model Removal: 'altera_reserved_tck' + 16. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' + 17. Setup Times + 18. Hold Times + 19. Clock to Output Times + 20. Minimum Clock to Output Times + 21. MTBF Summary + 22. Synchronizer Summary + 23. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years + 24. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years + 25. Slow 1200mV 0C Model Fmax Summary + 26. Slow 1200mV 0C Model Setup Summary + 27. Slow 1200mV 0C Model Hold Summary + 28. Slow 1200mV 0C Model Recovery Summary + 29. Slow 1200mV 0C Model Removal Summary + 30. Slow 1200mV 0C Model Minimum Pulse Width Summary + 31. Slow 1200mV 0C Model Setup: 'altera_reserved_tck' + 32. Slow 1200mV 0C Model Hold: 'altera_reserved_tck' + 33. Slow 1200mV 0C Model Recovery: 'altera_reserved_tck' + 34. Slow 1200mV 0C Model Removal: 'altera_reserved_tck' + 35. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' + 36. Setup Times + 37. Hold Times + 38. Clock to Output Times + 39. Minimum Clock to Output Times + 40. MTBF Summary + 41. Synchronizer Summary + 42. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years + 43. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years + 44. Fast 1200mV 0C Model Setup Summary + 45. Fast 1200mV 0C Model Hold Summary + 46. Fast 1200mV 0C Model Recovery Summary + 47. Fast 1200mV 0C Model Removal Summary + 48. Fast 1200mV 0C Model Minimum Pulse Width Summary + 49. Fast 1200mV 0C Model Setup: 'altera_reserved_tck' + 50. Fast 1200mV 0C Model Hold: 'altera_reserved_tck' + 51. Fast 1200mV 0C Model Recovery: 'altera_reserved_tck' + 52. Fast 1200mV 0C Model Removal: 'altera_reserved_tck' + 53. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' + 54. Setup Times + 55. Hold Times + 56. Clock to Output Times + 57. Minimum Clock to Output Times + 58. MTBF Summary + 59. Synchronizer Summary + 60. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years + 61. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years + 62. Multicorner Timing Analysis Summary + 63. Setup Times + 64. Hold Times + 65. Clock to Output Times + 66. Minimum Clock to Output Times + 67. Board Trace Model Assignments + 68. Input Transition Times + 69. Signal Integrity Metrics (Slow 1200mv 0c Model) + 70. Signal Integrity Metrics (Slow 1200mv 85c Model) + 71. Signal Integrity Metrics (Fast 1200mv 0c Model) + 72. Setup Transfers + 73. Hold Transfers + 74. Recovery Transfers + 75. Removal Transfers + 76. Report TCCS + 77. Report RSKM + 78. Unconstrained Paths + 79. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; lights ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE115F29C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+-------------------------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ +; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { altera_reserved_tck } ; ++---------------------+------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------------------+ + + ++-----------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+---------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+---------------------+------+ +; 149.52 MHz ; 149.52 MHz ; altera_reserved_tck ; ; ++------------+-----------------+---------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++----------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++---------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+---------------+ +; altera_reserved_tck ; 46.656 ; 0.000 ; ++---------------------+--------+---------------+ + + ++---------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++---------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+-------+---------------+ +; altera_reserved_tck ; 0.401 ; 0.000 ; ++---------------------+-------+---------------+ + + ++----------------------------------------------+ +; Slow 1200mV 85C Model Recovery Summary ; ++---------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+---------------+ +; altera_reserved_tck ; 47.591 ; 0.000 ; ++---------------------+--------+---------------+ + + ++---------------------------------------------+ +; Slow 1200mV 85C Model Removal Summary ; ++---------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+-------+---------------+ +; altera_reserved_tck ; 1.180 ; 0.000 ; ++---------------------+-------+---------------+ + + ++---------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++---------------------+--------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+--------------------+ +; altera_reserved_tck ; 49.555 ; 0.000 ; ++---------------------+--------+--------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'altera_reserved_tck' ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 46.656 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.150 ; 3.512 ; +; 46.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.152 ; 3.380 ; +; 46.911 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.150 ; 3.257 ; +; 47.218 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.940 ; +; 47.221 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.150 ; 2.947 ; +; 47.294 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.138 ; 2.862 ; +; 47.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.781 ; +; 47.378 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.154 ; 2.794 ; +; 47.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.640 ; +; 47.549 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.141 ; 2.610 ; +; 47.560 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.609 ; +; 47.658 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.511 ; +; 47.742 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.151 ; 2.427 ; +; 47.866 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.154 ; 2.306 ; +; 47.965 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.153 ; 2.206 ; +; 48.251 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.153 ; 1.920 ; +; 48.617 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 1.541 ; +; 48.849 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.116 ; 1.285 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 93.991 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.918 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.070 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.839 ; +; 94.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.611 ; +; 94.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.611 ; +; 94.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.533 ; +; 94.377 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.108 ; 5.533 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.500 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.473 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.109 ; 5.436 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.527 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.420 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.545 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.402 ; +; 94.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.113 ; +; 94.835 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.113 ; +; 94.853 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.095 ; +; 94.853 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.070 ; 5.095 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.945 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 5.002 ; +; 94.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.992 ; +; 94.953 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.992 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 94.963 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 4.984 ; +; 95.052 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.893 ; +; 95.052 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.893 ; +; 95.111 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.834 ; +; 95.213 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 4.732 ; +; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; +; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; +; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; +; 95.234 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 4.701 ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'altera_reserved_tck' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 0.401 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.669 ; +; 0.404 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 0.669 ; +; 0.407 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; +; 0.407 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; +; 0.407 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; +; 0.407 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.674 ; +; 0.419 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.686 ; +; 0.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.694 ; +; 0.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.694 ; +; 0.427 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.694 ; +; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; +; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; +; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; +; 0.428 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; +; 0.428 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 0.696 ; +; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; +; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; +; 0.428 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.695 ; +; 0.429 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; +; 0.429 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; +; 0.429 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; +; 0.429 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.696 ; +; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; +; 0.430 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; +; 0.430 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; +; 0.430 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; +; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; +; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; +; 0.430 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.697 ; +; 0.434 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.701 ; +; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; +; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; +; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; +; 0.435 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.702 ; +; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; +; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; +; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; +; 0.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; +; 0.436 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; +; 0.436 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.703 ; +; 0.437 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.704 ; +; 0.437 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.704 ; +; 0.437 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.704 ; +; 0.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.710 ; +; 0.443 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.710 ; +; 0.444 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.711 ; +; 0.450 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.717 ; +; 0.450 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.717 ; +; 0.451 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; +; 0.451 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; +; 0.451 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; +; 0.451 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.718 ; +; 0.452 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.719 ; +; 0.453 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.720 ; +; 0.488 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.755 ; +; 0.552 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.819 ; +; 0.553 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.820 ; +; 0.560 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.827 ; +; 0.561 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.828 ; +; 0.561 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.828 ; +; 0.564 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.831 ; +; 0.573 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.840 ; +; 0.574 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.841 ; +; 0.574 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.841 ; +; 0.574 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.841 ; +; 0.576 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.843 ; +; 0.577 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.844 ; +; 0.577 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.844 ; +; 0.592 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.859 ; +; 0.599 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.866 ; +; 0.599 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 0.867 ; +; 0.599 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.866 ; +; 0.599 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.866 ; +; 0.601 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.868 ; +; 0.601 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.868 ; +; 0.602 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.869 ; +; 0.605 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.872 ; +; 0.607 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.874 ; +; 0.612 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.879 ; +; 0.616 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.883 ; +; 0.622 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.889 ; +; 0.622 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.889 ; +; 0.628 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.081 ; 0.895 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'altera_reserved_tck' ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 47.591 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.567 ; +; 47.694 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.140 ; 2.464 ; +; 48.594 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.156 ; 1.580 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.178 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 2.750 ; +; 97.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.745 ; +; 97.182 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.745 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.359 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.567 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.651 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.089 ; 2.278 ; +; 97.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.274 ; +; 97.661 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.083 ; 2.274 ; +; 97.690 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.237 ; +; 97.690 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.091 ; 2.237 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.709 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.217 ; +; 97.711 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.119 ; 2.188 ; +; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; +; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; +; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; +; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; +; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; +; 97.712 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 2.214 ; +; 97.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.094 ; 2.134 ; +; 97.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.094 ; 2.134 ; +; 97.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.094 ; 2.134 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.927 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.092 ; 1.999 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 97.964 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.093 ; 1.961 ; +; 98.045 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 1.883 ; +; 98.045 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.090 ; 1.883 ; +; 98.358 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.580 ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'altera_reserved_tck' ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 1.180 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.082 ; 1.448 ; +; 1.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.120 ; 1.746 ; +; 1.440 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.120 ; 1.746 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.117 ; 1.815 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.536 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 1.840 ; +; 1.705 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.116 ; 2.007 ; +; 1.705 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.116 ; 2.007 ; +; 1.705 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.116 ; 2.007 ; +; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; +; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; +; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; +; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; +; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; +; 1.752 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.056 ; +; 1.759 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.091 ; 2.036 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.076 ; +; 1.794 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.127 ; 2.107 ; +; 1.794 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.127 ; 2.107 ; +; 1.795 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.100 ; +; 1.795 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.100 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 1.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.112 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.108 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.118 ; 2.412 ; +; 2.296 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.601 ; +; 2.296 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.119 ; 2.601 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 2.299 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.121 ; 2.606 ; +; 50.944 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.318 ; 1.448 ; +; 51.799 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.350 ; 2.335 ; +; 51.875 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.351 ; 2.412 ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.555 ; 49.775 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; +; 49.557 ; 49.777 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.559 ; 49.779 ; 0.220 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; 49.609 ; 49.797 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; +; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; +; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; +; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; +; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; +; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; +; 49.610 ; 49.798 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; +; 49.611 ; 49.799 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; +; 49.612 ; 49.800 ; 0.188 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 4.797 ; 5.038 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 9.083 ; 9.211 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+-------+-------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; -1.132 ; -1.407 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -2.605 ; -2.801 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 13.944 ; 14.539 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 11.553 ; 12.146 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 2 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 197.069 ns + +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; +; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 197.069 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.147 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 97.922 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; +; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 197.289 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.147 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 98.142 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++-----------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+---------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+---------------------+------+ +; 169.03 MHz ; 169.03 MHz ; altera_reserved_tck ; ; ++------------+-----------------+---------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++----------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++---------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+---------------+ +; altera_reserved_tck ; 47.042 ; 0.000 ; ++---------------------+--------+---------------+ + + ++---------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++---------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+-------+---------------+ +; altera_reserved_tck ; 0.353 ; 0.000 ; ++---------------------+-------+---------------+ + + ++----------------------------------------------+ +; Slow 1200mV 0C Model Recovery Summary ; ++---------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+---------------+ +; altera_reserved_tck ; 47.930 ; 0.000 ; ++---------------------+--------+---------------+ + + ++---------------------------------------------+ +; Slow 1200mV 0C Model Removal Summary ; ++---------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+-------+---------------+ +; altera_reserved_tck ; 1.082 ; 0.000 ; ++---------------------+-------+---------------+ + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++---------------------+--------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+-------------------+ +; altera_reserved_tck ; 49.489 ; 0.000 ; ++---------------------+--------+-------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'altera_reserved_tck' ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 47.042 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 3.205 ; +; 47.180 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.231 ; 3.070 ; +; 47.288 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.229 ; 2.960 ; +; 47.505 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.230 ; 2.744 ; +; 47.543 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.221 ; 2.697 ; +; 47.662 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.221 ; 2.578 ; +; 47.667 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.219 ; 2.571 ; +; 47.720 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.232 ; 2.531 ; +; 47.826 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.220 ; 2.413 ; +; 47.838 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 2.409 ; +; 47.904 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.229 ; 2.344 ; +; 47.976 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 2.271 ; +; 48.062 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.228 ; 2.185 ; +; 48.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.232 ; 2.072 ; +; 48.246 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.231 ; 2.004 ; +; 48.501 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.231 ; 1.749 ; +; 48.833 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.222 ; 1.408 ; +; 49.052 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.198 ; 1.165 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.529 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.394 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.615 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.307 ; +; 94.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.118 ; +; 94.805 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.118 ; +; 94.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.023 ; +; 94.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 5.023 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.903 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.096 ; 5.020 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 94.993 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.097 ; 4.929 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.012 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.945 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.038 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.919 ; +; 95.285 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.672 ; +; 95.285 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.672 ; +; 95.322 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.635 ; +; 95.322 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.635 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.383 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.574 ; +; 95.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.559 ; +; 95.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.065 ; 4.559 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.416 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 4.541 ; +; 95.492 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 4.461 ; +; 95.492 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.066 ; 4.461 ; +; 95.541 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.064 ; 4.414 ; +; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; +; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; +; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; +; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; +; 95.583 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.074 ; 4.362 ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'altera_reserved_tck' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.353 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.353 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.353 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.354 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.597 ; +; 0.355 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.071 ; 0.597 ; +; 0.364 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; +; 0.364 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; +; 0.364 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.608 ; +; 0.365 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.608 ; +; 0.379 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.622 ; +; 0.386 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.630 ; +; 0.386 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.629 ; +; 0.387 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.630 ; +; 0.387 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.631 ; +; 0.394 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.638 ; +; 0.394 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.638 ; +; 0.395 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; +; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; +; 0.395 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.638 ; +; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.640 ; +; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; +; 0.396 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; +; 0.396 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; +; 0.396 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.640 ; +; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.640 ; +; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; +; 0.396 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.639 ; +; 0.397 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.640 ; +; 0.397 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.640 ; +; 0.398 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.641 ; +; 0.398 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.641 ; +; 0.398 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.641 ; +; 0.401 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.645 ; +; 0.401 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.644 ; +; 0.401 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.644 ; +; 0.401 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.645 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.646 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.646 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.645 ; +; 0.402 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.645 ; +; 0.403 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; +; 0.403 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; +; 0.403 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; +; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; +; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; +; 0.403 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; +; 0.403 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.646 ; +; 0.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.652 ; +; 0.409 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.652 ; +; 0.416 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; +; 0.416 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; +; 0.416 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; +; 0.416 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.659 ; +; 0.417 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.660 ; +; 0.417 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.660 ; +; 0.418 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.661 ; +; 0.418 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.661 ; +; 0.450 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.693 ; +; 0.507 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.750 ; +; 0.507 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.751 ; +; 0.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.755 ; +; 0.513 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.757 ; +; 0.514 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.758 ; +; 0.514 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.758 ; +; 0.526 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.769 ; +; 0.526 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.769 ; +; 0.526 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.770 ; +; 0.527 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.770 ; +; 0.528 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.772 ; +; 0.530 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.773 ; +; 0.534 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.777 ; +; 0.547 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.790 ; +; 0.547 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.791 ; +; 0.548 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.791 ; +; 0.548 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.792 ; +; 0.549 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.793 ; +; 0.550 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.794 ; +; 0.553 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.796 ; +; 0.554 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.797 ; +; 0.556 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.799 ; +; 0.557 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.801 ; +; 0.561 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.804 ; +; 0.562 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.805 ; +; 0.569 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.812 ; +; 0.569 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.072 ; 0.812 ; +; 0.574 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 0.818 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'altera_reserved_tck' ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 47.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.222 ; 2.311 ; +; 48.002 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.221 ; 2.238 ; +; 48.832 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.233 ; 1.420 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.438 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.502 ; +; 97.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.497 ; +; 97.441 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.497 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.627 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 2.311 ; +; 97.873 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.067 ; +; 97.873 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.079 ; 2.067 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.896 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 2.043 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.897 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.078 ; 2.044 ; +; 97.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.047 ; +; 97.899 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.073 ; 2.047 ; +; 97.912 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.107 ; 2.000 ; +; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; +; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; +; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; +; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; +; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; +; 97.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.987 ; +; 98.018 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 1.919 ; +; 98.018 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 1.919 ; +; 98.018 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.082 ; 1.919 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.796 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.172 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.081 ; 1.766 ; +; 98.244 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.695 ; +; 98.244 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.080 ; 1.695 ; +; 98.528 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.071 ; 1.420 ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'altera_reserved_tck' ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 1.082 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.073 ; 1.326 ; +; 1.321 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.599 ; +; 1.321 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.599 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.385 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 1.661 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.410 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.687 ; +; 1.565 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.104 ; 1.840 ; +; 1.565 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.104 ; 1.840 ; +; 1.565 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.104 ; 1.840 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.597 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 1.874 ; +; 1.598 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.079 ; 1.848 ; +; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; +; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; +; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; +; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; +; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; +; 1.611 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.889 ; +; 1.617 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.895 ; +; 1.617 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 1.895 ; +; 1.653 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.114 ; 1.938 ; +; 1.653 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.114 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.659 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.108 ; 1.938 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 1.938 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.105 ; 2.214 ; +; 2.088 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 2.365 ; +; 2.088 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.106 ; 2.365 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 2.092 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.107 ; 2.370 ; +; 50.772 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.383 ; 1.326 ; +; 51.532 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.413 ; 2.116 ; +; 51.629 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.414 ; 2.214 ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.489 ; 49.707 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; +; 49.490 ; 49.708 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; +; 49.490 ; 49.708 ; 0.218 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; +; 49.532 ; 49.718 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.100 ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; 49.533 ; 49.719 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; +; 49.534 ; 49.720 ; 0.186 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 4.588 ; 4.953 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 8.807 ; 8.972 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+-------+-------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; -1.136 ; -1.533 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -2.650 ; -2.955 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 12.999 ; 13.411 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 10.643 ; 11.056 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 2 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 197.362 ns + +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; +; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 197.362 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.235 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 98.127 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; +; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 197.556 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.237 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 98.319 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++----------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++---------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+---------------+ +; altera_reserved_tck ; 48.710 ; 0.000 ; ++---------------------+--------+---------------+ + + ++---------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++---------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+-------+---------------+ +; altera_reserved_tck ; 0.178 ; 0.000 ; ++---------------------+-------+---------------+ + + ++----------------------------------------------+ +; Fast 1200mV 0C Model Recovery Summary ; ++---------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+---------------+ +; altera_reserved_tck ; 49.091 ; 0.000 ; ++---------------------+--------+---------------+ + + ++---------------------------------------------+ +; Fast 1200mV 0C Model Removal Summary ; ++---------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+-------+---------------+ +; altera_reserved_tck ; 0.560 ; 0.000 ; ++---------------------+-------+---------------+ + + ++--------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++---------------------+--------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++---------------------+--------+-------------------+ +; altera_reserved_tck ; 49.301 ; 0.000 ; ++---------------------+--------+-------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'altera_reserved_tck' ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 48.710 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.437 ; 1.734 ; +; 48.770 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.440 ; 1.677 ; +; 48.832 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.437 ; 1.612 ; +; 48.931 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.439 ; 1.515 ; +; 48.952 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.488 ; +; 49.013 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.431 ; 1.425 ; +; 49.048 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.392 ; +; 49.082 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.442 ; 1.367 ; +; 49.116 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.434 ; 1.325 ; +; 49.160 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.438 ; 1.285 ; +; 49.174 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.439 ; 1.272 ; +; 49.212 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.438 ; 1.233 ; +; 49.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.438 ; 1.178 ; +; 49.342 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.442 ; 1.107 ; +; 49.412 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 1.036 ; +; 49.561 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.441 ; 0.887 ; +; 49.660 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 0.780 ; +; 49.775 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.417 ; 0.649 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.973 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.974 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 96.995 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.950 ; +; 97.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.803 ; +; 97.142 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.062 ; 2.803 ; +; 97.143 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.804 ; +; 97.143 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.060 ; 2.804 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.179 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.063 ; 2.765 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.061 ; 2.745 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.266 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.705 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.272 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.699 ; +; 97.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.535 ; +; 97.436 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.535 ; +; 97.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.529 ; +; 97.442 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.036 ; 2.529 ; +; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.039 ; 2.499 ; +; 97.469 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.039 ; 2.499 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.494 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.476 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.500 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.470 ; +; 97.518 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.452 ; +; 97.518 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.452 ; +; 97.567 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.039 ; 2.401 ; +; 97.590 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.037 ; 2.380 ; +; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; +; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; +; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; +; 97.595 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.045 ; 2.367 ; ++--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'altera_reserved_tck' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 0.178 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.045 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.181 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.307 ; +; 0.182 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.307 ; +; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; +; 0.187 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; +; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; +; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; +; 0.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.313 ; +; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.188 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.314 ; +; 0.189 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; +; 0.189 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; +; 0.189 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; +; 0.189 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.315 ; +; 0.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; +; 0.190 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; +; 0.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; +; 0.190 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; +; 0.190 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.316 ; +; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; +; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; +; 0.191 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; +; 0.191 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.317 ; +; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.192 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.192 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.192 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.192 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.318 ; +; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; +; 0.193 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; +; 0.193 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.319 ; +; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; +; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; +; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; +; 0.196 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.322 ; +; 0.199 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; +; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; +; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; +; 0.199 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.325 ; +; 0.200 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.326 ; +; 0.200 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.326 ; +; 0.201 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.327 ; +; 0.203 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.328 ; +; 0.206 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.332 ; +; 0.219 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.345 ; +; 0.247 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.373 ; +; 0.248 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.374 ; +; 0.252 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.378 ; +; 0.252 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.378 ; +; 0.252 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.378 ; +; 0.253 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.379 ; +; 0.257 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.383 ; +; 0.257 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.382 ; +; 0.258 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.384 ; +; 0.258 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.383 ; +; 0.258 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.384 ; +; 0.259 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.384 ; +; 0.260 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.386 ; +; 0.260 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.386 ; +; 0.260 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.386 ; +; 0.261 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[37] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.387 ; +; 0.261 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.387 ; +; 0.262 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.388 ; +; 0.262 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.387 ; +; 0.263 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.389 ; +; 0.263 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.388 ; +; 0.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.390 ; +; 0.264 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.390 ; +; 0.267 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.393 ; +; 0.268 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.041 ; 0.393 ; +; 0.271 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.397 ; +; 0.272 ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.398 ; +; 0.273 ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[36] ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.042 ; 0.399 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'altera_reserved_tck' ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 49.091 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.349 ; +; 49.173 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.433 ; 1.267 ; +; 49.671 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 50.000 ; 0.443 ; 0.779 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.509 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.452 ; +; 98.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.447 ; +; 98.512 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.447 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.609 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.349 ; +; 98.783 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.043 ; 1.181 ; +; 98.783 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.043 ; 1.181 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.790 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.171 ; +; 98.808 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.153 ; +; 98.808 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.046 ; 1.153 ; +; 98.812 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.068 ; 1.127 ; +; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; +; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; +; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; +; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; +; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; +; 98.815 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.145 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 1.144 ; +; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.050 ; 1.105 ; +; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.050 ; 1.105 ; +; 98.852 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.050 ; 1.105 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.930 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.048 ; 1.029 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 98.948 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.049 ; 1.010 ; +; 99.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 0.956 ; +; 99.004 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.047 ; 0.956 ; +; 99.187 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 100.000 ; -0.041 ; 0.779 ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'altera_reserved_tck' ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ +; 0.560 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.043 ; 0.687 ; +; 0.686 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.837 ; +; 0.686 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.837 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.726 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 0.875 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.734 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 0.884 ; +; 0.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.064 ; 0.964 ; +; 0.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.064 ; 0.964 ; +; 0.816 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.064 ; 0.964 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.822 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.973 ; +; 0.828 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.980 ; +; 0.828 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.980 ; +; 0.830 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.046 ; 0.960 ; +; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; +; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; +; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; +; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; +; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; +; 0.836 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.067 ; 0.987 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.846 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 0.998 ; +; 0.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|state ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.071 ; 1.012 ; +; 0.857 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|user_saw_rvalid ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.071 ; 1.012 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[3] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[4] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[7] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.010 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.065 ; 1.159 ; +; 1.098 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 1.248 ; +; 1.098 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.066 ; 1.248 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|count[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[10] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_stalled ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read_req ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[8] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[6] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[5] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[2] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[1] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[9] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 1.100 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[0] ; altera_reserved_tck ; altera_reserved_tck ; 0.000 ; 0.068 ; 1.252 ; +; 50.069 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.534 ; 0.687 ; +; 50.466 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.554 ; 1.104 ; +; 50.520 ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; altera_reserved_tck ; altera_reserved_tck ; -50.000 ; 0.555 ; 1.159 ; ++--------+--------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.301 ; 49.517 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tdo~reg0 ; +; 49.302 ; 49.518 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.303 ; 49.519 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|jupdate ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[16] ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[17] ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[18] ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[19] ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[20] ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[21] ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[22] ; +; 49.344 ; 49.528 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[23] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|tck_t_dav ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[10] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[11] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[12] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[13] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[14] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[1] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[24] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[25] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[26] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[27] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[28] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[29] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[2] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[30] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[31] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[32] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[33] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[34] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[3] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[4] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[5] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[6] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[8] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[9] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; 49.345 ; 49.529 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|read ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[3] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[4] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|td_shift[7] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[1] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[2] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[3] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[4] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[5] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[6] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|wdata[7] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_jtag_uart:jtag_uart|alt_jtag_atlantic:nios_system_jtag_uart_alt_jtag_atlantic|write_valid ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.000 ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.010 ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|DRsize.100 ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|ir_out[0] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[0] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[15] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|sr[35] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; +; 49.346 ; 49.530 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; ++--------+--------------+----------------+------------------+---------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 2.198 ; 2.498 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 3.853 ; 4.252 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+-------+-------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; -0.427 ; -0.731 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -0.933 ; -1.275 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 7.464 ; 8.013 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+-------+-------+------------+---------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 6.241 ; 6.786 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+-------+-------+------------+---------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 2 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 +Worst Case Available Settling Time: 198.608 ns + +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; Greater than 1 Billion ; Yes ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; +; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 198.608 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|hbreak_enabled ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; 99.592 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; 99.016 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; +; Synchronization Node ; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 198.706 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_nios2_oci_debug:the_nios_system_nios2_processor_nios2_oci_debug|monitor_ready ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 99.593 ; +; nios_system:NiosII|nios_system_nios2_processor:nios2_processor|nios_system_nios2_processor_nios2_oci:the_nios_system_nios2_processor_nios2_oci|nios_system_nios2_processor_jtag_debug_module_wrapper:the_nios_system_nios2_processor_jtag_debug_module_wrapper|nios_system_nios2_processor_jtag_debug_module_tck:the_nios_system_nios2_processor_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 99.113 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + ++----------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++----------------------+--------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++----------------------+--------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 46.656 ; 0.178 ; 47.591 ; 0.560 ; 49.301 ; +; altera_reserved_tck ; 46.656 ; 0.178 ; 47.591 ; 0.560 ; 49.301 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; altera_reserved_tck ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ++----------------------+--------+-------+----------+---------+---------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 4.797 ; 5.038 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 9.083 ; 9.211 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+-------+-------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; -0.427 ; -0.731 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -0.933 ; -1.275 ; Rise ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 13.944 ; 14.539 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+--------+--------+------------+---------------------+ + + ++----------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+---------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 6.241 ; 6.786 ; Fall ; altera_reserved_tck ; ++---------------------+---------------------+-------+-------+------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDG[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LEDR[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX3[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX4[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX4[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX4[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX4[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX4[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX4[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX4[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX5[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX5[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX5[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX5[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX5[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX5[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX5[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX6[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX6[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX6[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX6[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX6[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX6[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX6[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX7[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX7[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX7[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX7[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX7[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX7[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; HEX7[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_RS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_RW ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_data[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_EN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_ON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LCD_BLON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; altera_reserved_tdo ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; CLOCK_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; altera_reserved_tms ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; altera_reserved_tck ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; altera_reserved_tdi ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; +; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; +; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; 2.32 V ; 4.49e-09 V ; 2.33 V ; -0.00467 V ; 0.226 V ; 0.087 V ; 2.91e-09 s ; 2.74e-09 s ; Yes ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.33 V ; -0.00496 V ; 0.223 V ; 0.086 V ; 2.9e-09 s ; 2.73e-09 s ; Yes ; Yes ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.37 V ; -0.00994 V ; 0.186 V ; 0.028 V ; 4.98e-10 s ; 4.96e-10 s ; Yes ; Yes ; +; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; 2.32 V ; 3.07e-09 V ; 2.38 V ; -0.0144 V ; 0.227 V ; 0.024 V ; 3.14e-10 s ; 3.39e-10 s ; Yes ; Yes ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; +; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; 3.08 V ; 1.58e-08 V ; 3.09 V ; -0.012 V ; 0.232 V ; 0.268 V ; 4.75e-09 s ; 3.5e-09 s ; Yes ; No ; +; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 1.58e-08 V ; 3.13 V ; -0.117 V ; 0.143 V ; 0.259 V ; 6.22e-10 s ; 4.46e-10 s ; No ; No ; +; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; +; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.09 V ; -0.0117 V ; 0.268 V ; 0.262 V ; 4.74e-09 s ; 3.5e-09 s ; No ; No ; +; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; 3.08 V ; 1.11e-08 V ; 3.13 V ; -0.0798 V ; 0.192 V ; 0.22 V ; 8.68e-10 s ; 6.46e-10 s ; No ; No ; +; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 4.33e-08 V ; 3.11 V ; -0.0128 V ; 0.235 V ; 0.229 V ; 6.79e-10 s ; 1.6e-09 s ; Yes ; Yes ; 3.08 V ; 4.33e-08 V ; 3.11 V ; -0.0128 V ; 0.235 V ; 0.229 V ; 6.79e-10 s ; 1.6e-09 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.149 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.149 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; +; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; +; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.33 V ; -0.00265 V ; 0.133 V ; 0.056 V ; 3.55e-09 s ; 3.31e-09 s ; Yes ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.33 V ; -0.00269 V ; 0.13 V ; 0.055 V ; 3.54e-09 s ; 3.29e-09 s ; Yes ; Yes ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.35 V ; -0.00942 V ; 0.116 V ; 0.033 V ; 6.66e-10 s ; 6.27e-10 s ; Yes ; Yes ; +; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; 2.32 V ; 4.67e-07 V ; 2.36 V ; -0.00552 V ; 0.11 V ; 0.007 V ; 4.54e-10 s ; 4.35e-10 s ; Yes ; Yes ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; +; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; 3.08 V ; 1.9e-06 V ; 3.08 V ; -0.00581 V ; 0.138 V ; 0.22 V ; 5.55e-09 s ; 4.38e-09 s ; Yes ; Yes ; +; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; 3.08 V ; 1.9e-06 V ; 3.11 V ; -0.0625 V ; 0.224 V ; 0.17 V ; 6.86e-10 s ; 6.31e-10 s ; Yes ; No ; +; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; +; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; 3.08 V ; 1.28e-06 V ; 3.08 V ; -0.00641 V ; 0.261 V ; 0.26 V ; 5.52e-09 s ; 4.36e-09 s ; Yes ; Yes ; +; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; 3.08 V ; 1.28e-06 V ; 3.11 V ; -0.0528 V ; 0.302 V ; 0.199 V ; 9.51e-10 s ; 8.47e-10 s ; Yes ; No ; +; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.02e-06 V ; 3.09 V ; -0.00287 V ; 0.055 V ; 0.123 V ; 8.59e-10 s ; 2.03e-09 s ; Yes ; Yes ; 3.08 V ; 5.02e-06 V ; 3.09 V ; -0.00287 V ; 0.055 V ; 0.123 V ; 8.59e-10 s ; 2.03e-09 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDG[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDG[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDG[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDG[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDG[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDG[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDG[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; LEDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; LEDR[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LEDR[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; +; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; +; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; +; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; HEX3[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; +; HEX3[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX3[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX3[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX3[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX4[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX4[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX4[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX4[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX4[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX4[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX4[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX5[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX5[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; +; HEX5[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX5[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX5[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX5[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX5[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX6[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX6[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX6[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX6[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX6[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX6[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; +; HEX6[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX7[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX7[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX7[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX7[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX7[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX7[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; HEX7[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; +; LCD_RS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_RW ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_data[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; +; LCD_EN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; LCD_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.48 V ; -0.0162 V ; 0.354 V ; 0.317 V ; 3.88e-09 s ; 3.06e-09 s ; No ; No ; +; LCD_BLON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +; altera_reserved_tdo ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 4.9e-07 V ; 3.52 V ; -0.0234 V ; 0.372 V ; 0.263 V ; 5.16e-10 s ; 1.44e-09 s ; No ; No ; 3.46 V ; 4.9e-07 V ; 3.52 V ; -0.0234 V ; 0.372 V ; 0.263 V ; 5.16e-10 s ; 1.44e-09 s ; No ; No ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Setup Transfers ; ++---------------------+---------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++---------------------+---------------------+----------+----------+----------+----------+ +; altera_reserved_tck ; altera_reserved_tck ; 1728 ; 0 ; 32 ; 2 ; ++---------------------+---------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++---------------------------------------------------------------------------------------+ +; Hold Transfers ; ++---------------------+---------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++---------------------+---------------------+----------+----------+----------+----------+ +; altera_reserved_tck ; altera_reserved_tck ; 1728 ; 0 ; 32 ; 2 ; ++---------------------+---------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++---------------------------------------------------------------------------------------+ +; Recovery Transfers ; ++---------------------+---------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++---------------------+---------------------+----------+----------+----------+----------+ +; altera_reserved_tck ; altera_reserved_tck ; 81 ; 0 ; 3 ; 0 ; ++---------------------+---------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++---------------------------------------------------------------------------------------+ +; Removal Transfers ; ++---------------------+---------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++---------------------+---------------------+----------+----------+----------+----------+ +; altera_reserved_tck ; altera_reserved_tck ; 81 ; 0 ; 3 ; 0 ; ++---------------------+---------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 1 ; 1 ; +; Unconstrained Input Ports ; 24 ; 24 ; +; Unconstrained Input Port Paths ; 90 ; 90 ; +; Unconstrained Output Ports ; 96 ; 96 ; +; Unconstrained Output Port Paths ; 129 ; 129 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Thu Dec 22 10:08:42 2016 +Info: Command: quartus_sta lights -c lights +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity alt_jtag_atlantic + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] + Info (332165): Entity sld_jtag_hub + Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz + Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} +Critical Warning (332012): Synopsys Design Constraints File file not found: 'lights.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Info (332146): Worst-case setup slack is 46.656 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 46.656 0.000 altera_reserved_tck +Info (332146): Worst-case hold slack is 0.401 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.401 0.000 altera_reserved_tck +Info (332146): Worst-case recovery slack is 47.591 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 47.591 0.000 altera_reserved_tck +Info (332146): Worst-case removal slack is 1.180 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.180 0.000 altera_reserved_tck +Info (332146): Worst-case minimum pulse width slack is 49.555 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 49.555 0.000 altera_reserved_tck +Info (332114): Report Metastability: Found 2 synchronizer chains. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 2 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 197.069 ns + Info (332114): + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) +Info (332146): Worst-case setup slack is 47.042 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 47.042 0.000 altera_reserved_tck +Info (332146): Worst-case hold slack is 0.353 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.353 0.000 altera_reserved_tck +Info (332146): Worst-case recovery slack is 47.930 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 47.930 0.000 altera_reserved_tck +Info (332146): Worst-case removal slack is 1.082 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.082 0.000 altera_reserved_tck +Info (332146): Worst-case minimum pulse width slack is 49.489 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 49.489 0.000 altera_reserved_tck +Info (332114): Report Metastability: Found 2 synchronizer chains. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 2 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 197.362 ns + Info (332114): + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 +Info: Analyzing Fast 1200mV 0C Model +Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) + Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) +Info (332146): Worst-case setup slack is 48.710 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 48.710 0.000 altera_reserved_tck +Info (332146): Worst-case hold slack is 0.178 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.178 0.000 altera_reserved_tck +Info (332146): Worst-case recovery slack is 49.091 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 49.091 0.000 altera_reserved_tck +Info (332146): Worst-case removal slack is 0.560 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.560 0.000 altera_reserved_tck +Info (332146): Worst-case minimum pulse width slack is 49.301 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 49.301 0.000 altera_reserved_tck +Info (332114): Report Metastability: Found 2 synchronizer chains. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 2 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 + Info (332114): Worst Case Available Settling Time: 198.608 ns + Info (332114): + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings + Info: Peak virtual memory: 605 megabytes + Info: Processing ended: Thu Dec 22 10:08:48 2016 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 + + diff --git a/output_files/lights.sta.summary b/output_files/lights.sta.summary index 630b706..0146831 100644 --- a/output_files/lights.sta.summary +++ b/output_files/lights.sta.summary @@ -1,65 +1,65 @@ ------------------------------------------------------------- -TimeQuest Timing Analyzer Summary ------------------------------------------------------------- - -Type : Slow 1200mV 85C Model Setup 'altera_reserved_tck' -Slack : 45.777 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'altera_reserved_tck' -Slack : 0.403 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Recovery 'altera_reserved_tck' -Slack : 47.734 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Removal 'altera_reserved_tck' -Slack : 1.385 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.549 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'altera_reserved_tck' -Slack : 46.283 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'altera_reserved_tck' -Slack : 0.353 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Recovery 'altera_reserved_tck' -Slack : 48.047 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'altera_reserved_tck' -Slack : 1.278 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.476 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'altera_reserved_tck' -Slack : 48.270 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'altera_reserved_tck' -Slack : 0.180 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Recovery 'altera_reserved_tck' -Slack : 49.194 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'altera_reserved_tck' -Slack : 0.657 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.301 -TNS : 0.000 - ------------------------------------------------------------- +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'altera_reserved_tck' +Slack : 46.656 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'altera_reserved_tck' +Slack : 0.401 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Recovery 'altera_reserved_tck' +Slack : 47.591 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Removal 'altera_reserved_tck' +Slack : 1.180 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck' +Slack : 49.555 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'altera_reserved_tck' +Slack : 47.042 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'altera_reserved_tck' +Slack : 0.353 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Recovery 'altera_reserved_tck' +Slack : 47.930 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Removal 'altera_reserved_tck' +Slack : 1.082 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' +Slack : 49.489 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'altera_reserved_tck' +Slack : 48.710 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'altera_reserved_tck' +Slack : 0.178 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Recovery 'altera_reserved_tck' +Slack : 49.091 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Removal 'altera_reserved_tck' +Slack : 0.560 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' +Slack : 49.301 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/software/DE2_115_ASM/.cproject b/software/DE2_115_ASM/.cproject new file mode 100644 index 0000000..7c21de5 --- /dev/null +++ b/software/DE2_115_ASM/.cproject @@ -0,0 +1,508 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + mem_init_install + true + false + false + + + make + + mem_init_generate + true + false + false + + + make + + help + true + false + false + + + + diff --git a/software/DE2_115_ASM/.force_relink b/software/DE2_115_ASM/.force_relink new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/software/DE2_115_ASM/.force_relink diff --git a/software/DE2_115_ASM/.project b/software/DE2_115_ASM/.project new file mode 100644 index 0000000..ed311e5 --- /dev/null +++ b/software/DE2_115_ASM/.project @@ -0,0 +1,96 @@ + + + DE2_115_ASM + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/software/DE2_115_ASM/DE2_115_ASM.elf b/software/DE2_115_ASM/DE2_115_ASM.elf new file mode 100644 index 0000000..aaefd07 --- /dev/null +++ b/software/DE2_115_ASM/DE2_115_ASM.elf Binary files differ diff --git a/software/DE2_115_ASM/DE2_115_ASM.map b/software/DE2_115_ASM/DE2_115_ASM.map new file mode 100644 index 0000000..a258896 --- /dev/null +++ b/software/DE2_115_ASM/DE2_115_ASM.map @@ -0,0 +1,2510 @@ +Archive member included because of file (symbol) + +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-divmod.o) + obj/default/hex_out.o (__divsi3) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-mul.o) + obj/default/inst_decoder.o (__mulsi3) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-ctype_.o) + obj/default/hex_encoder.o (__ctype_ptr) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sprintf.o) + obj/default/hello_world_small.o (sprintf) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strlen.o) + obj/default/LCD.o (strlen) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sprintf.o) (___vfprintf_internal_r) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (__swsetup_r) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (_dtoa_r) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (_fflush_r) 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+c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__floatunsidf) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) (__muldi3) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clz.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) (__clz_tab) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_si_to_df.o) (__clzsi2) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__pack_d) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_unpack_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__unpack_d) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_fpcmp_parts_df.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_eq_df.o) (__fpcmp_parts_d) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_close.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-closer.o) (close) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dev.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_close.o) (alt_fd_list) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_errno.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_close.o) (alt_errno) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_fstat.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) (fstat) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_isatty.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) (isatty) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_load.o) + ../DE2_115_ASM_bsp//obj/HAL/src/crt0.o (alt_load) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_lseek.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) (lseek) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) + ../DE2_115_ASM_bsp//obj/HAL/src/crt0.o (alt_main) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_malloc_lock.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o) (__malloc_lock) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_read.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) (read) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_release_fd.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_close.o) (alt_release_fd) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sbrk.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) (sbrk) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_usleep.o) + obj/default/LCD.o (usleep) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_write.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o) (write) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) (alt_irq_init) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_lcd_16207.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_lcd_16207_init) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_lcd_16207_write_fd) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_alarm_start.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_busy_sleep.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_usleep.o) (alt_busy_sleep) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_load.o) (alt_dcache_flush_all) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) (alt_dev_llist_insert) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_do_ctors.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) (_do_ctors) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_do_dtors.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) (_do_dtors) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_load.o) (alt_icache_flush_all) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_ic_isr_register) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic.o) (alt_iic_isr_register) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_io_redirect.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) (alt_io_redirect) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_entry) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_handler.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_handler) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_vars.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic.o) (alt_irq_active) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_open.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_io_redirect.o) (open) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_tick.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate) +../DE2_115_ASM_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_nios2_qsys_irq_init) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) (alt_exception) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_find_dev.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_open.o) (alt_find_dev) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_find_file.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_open.o) (alt_find_file) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_get_fd.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_open.o) (alt_get_fd) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) (atexit) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) (exit) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_find_dev.o) (memcmp) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) (__register_exitproc) +c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (__call_exitprocs) +../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exit.o) + c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (_exit) + +Allocating common symbols +Common symbol size file + +alt_irq 0x100 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_handler.o) +errno 0x4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o) +stack 0x5 obj/default/hello_world_small.o +global_registers 0xf obj/default/sys_register.o +_atexit0 0x190 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + +Memory Configuration + +Name Origin Length Attributes +reset 0x00000000 0x00000020 +onchip_memory 0x00000020 0x00031fe0 +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD ../DE2_115_ASM_bsp//obj/HAL/src/crt0.o +LOAD obj/default/LCD.o +LOAD obj/default/hello_world_small.o +LOAD obj/default/hex_encoder.o +LOAD obj/default/hex_out.o +LOAD obj/default/input_int.o +LOAD obj/default/inst_decoder.o +LOAD obj/default/lcd_out.o +LOAD obj/default/sys_debug.o +LOAD obj/default/sys_except.o +LOAD obj/default/sys_memory.o +LOAD obj/default/sys_prog.o +LOAD obj/default/sys_register.o +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libstdc++.a +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libm.a +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a +START GROUP +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a +LOAD ../DE2_115_ASM_bsp/\libhal_bsp.a +END GROUP +LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a + 0x00000000 __alt_mem_onchip_memory = 0x0 + +.entry 0x00000000 0x20 + *(.entry) + .entry 0x00000000 0x20 ../DE2_115_ASM_bsp//obj/HAL/src/crt0.o + 0x00000000 __reset + +.exceptions 0x00000020 0x194 + 0x00000020 PROVIDE (__ram_exceptions_start, ABSOLUTE (.)) + 0x00000020 . = ALIGN (0x20) + *(.irq) + *(.exceptions.entry.label) + .exceptions.entry.label + 0x00000020 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + 0x00000020 alt_irq_entry + .exceptions.entry.label + 0x00000020 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + 0x00000020 alt_exception + *(.exceptions.entry.user) + *(.exceptions.entry) + .exceptions.entry + 0x00000020 0x54 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.irqtest.user) + *(.exceptions.irqtest) + .exceptions.irqtest + 0x00000074 0x10 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.irqhandler.user) + *(.exceptions.irqhandler) + .exceptions.irqhandler + 0x00000084 0x4 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.irqreturn.user) + *(.exceptions.irqreturn) + .exceptions.irqreturn + 0x00000088 0x4 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.label) + .exceptions.notirq.label + 0x0000008c 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.user) + *(.exceptions.notirq) + .exceptions.notirq + 0x0000008c 0x8 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.soft.user) + *(.exceptions.soft) + *(.exceptions.unknown.user) + *(.exceptions.unknown) + .exceptions.unknown + 0x00000094 0x4 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.label) + .exceptions.exit.label + 0x00000098 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + .exceptions.exit.label + 0x00000098 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.user) + *(.exceptions.exit) + .exceptions.exit + 0x00000098 0x54 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + *(.exceptions) + .exceptions 0x000000ec 0xc8 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_handler.o) + 0x000000ec alt_irq_handler + 0x000001b4 PROVIDE (__ram_exceptions_end, ABSOLUTE (.)) + 0x00000020 PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions)) + +.text 0x000001b4 0xfddc + 0x000001b4 PROVIDE (stext, ABSOLUTE (.)) + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* 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altera_avalon_jtag_uart_read_fd + 0x0000d14c altera_avalon_jtag_uart_write_fd + 0x0000d1a4 altera_avalon_jtag_uart_close_fd + 0x0000d1ec altera_avalon_jtag_uart_ioctl_fd + .text 0x0000d23c 0x40c ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + 0x0000d23c altera_avalon_jtag_uart_init + 0x0000d5d4 altera_avalon_jtag_uart_close + .text 0x0000d648 0xf4 ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) + 0x0000d648 altera_avalon_jtag_uart_ioctl + .text 0x0000d73c 0x224 ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + 0x0000d73c altera_avalon_jtag_uart_read + .text 0x0000d960 0x240 ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + 0x0000d960 altera_avalon_jtag_uart_write + .text 0x0000dba0 0xf80 ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_lcd_16207.o) + 0x0000e3dc altera_avalon_lcd_16207_write + 0x0000e9e4 altera_avalon_lcd_16207_init + .text 0x0000eb20 0x58 ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) + 0x0000eb20 altera_avalon_lcd_16207_write_fd + .text 0x0000eb78 0x154 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_alarm_start.o) + 0x0000eb78 alt_alarm_start + .text 0x0000eccc 0x15c ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_busy_sleep.o) + 0x0000eccc alt_busy_sleep + .text 0x0000ee28 0x1c ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + 0x0000ee28 alt_dcache_flush_all + .text 0x0000ee44 0x114 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + 0x0000ee44 alt_dev_llist_insert + .text 0x0000ef58 0x64 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_do_ctors.o) + 0x0000ef58 _do_ctors + .text 0x0000efbc 0x64 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_do_dtors.o) + 0x0000efbc _do_dtors + .text 0x0000f020 0x1c ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + 0x0000f020 alt_icache_flush_all + .text 0x0000f03c 0x1d4 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic.o) + 0x0000f03c alt_ic_isr_register + 0x0000f08c alt_ic_irq_enable + 0x0000f128 alt_ic_irq_disable + 0x0000f1c8 alt_ic_irq_enabled + .text 0x0000f210 0xf8 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + 0x0000f210 alt_iic_isr_register + .text 0x0000f308 0x150 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_io_redirect.o) + 0x0000f3e0 alt_io_redirect + .text 0x0000f458 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + .text 0x0000f458 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_handler.o) + .text 0x0000f458 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_vars.o) + .text 0x0000f458 0x2e4 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_open.o) + 0x0000f550 open + .text 0x0000f73c 0x1a4 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_tick.o) + 0x0000f73c alt_alarm_stop + 0x0000f7d4 alt_tick + .text 0x0000f8e0 0x20 ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) + 0x0000f8e0 altera_nios2_qsys_irq_init + .text 0x0000f900 0x0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + .text 0x0000f900 0x94 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_find_dev.o) + 0x0000f900 alt_find_dev + .text 0x0000f994 0x120 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_find_file.o) + 0x0000f994 alt_find_file + .text 0x0000fab4 0xd0 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_get_fd.o) + 0x0000fab4 alt_get_fd + .text 0x0000fb84 0x14 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + 0x0000fb84 atexit + .text 0x0000fb98 0x38 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + 0x0000fb98 exit + .text 0x0000fbd0 0x74 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + 0x0000fbd0 memcmp + .text 0x0000fc44 0x134 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + 0x0000fc44 __register_exitproc + .text 0x0000fd78 0x1b4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + 0x0000fd7c __call_exitprocs + .text 0x0000ff2c 0x60 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exit.o) + 0x0000ff6c _exit + *(.gnu.warning.*) + *(.fini) + 0x0000ff8c PROVIDE (__etext, ABSOLUTE (.)) + 0x0000ff8c PROVIDE (_etext, ABSOLUTE (.)) + 0x0000ff8c PROVIDE (etext, ABSOLUTE (.)) + *(.eh_frame_hdr) + 0x0000ff8c . = ALIGN (0x4) + 0x0000ff8c PROVIDE (__preinit_array_start, ABSOLUTE (.)) + *(.preinit_array) + 0x0000ff8c PROVIDE (__preinit_array_end, ABSOLUTE (.)) + 0x0000ff8c PROVIDE (__init_array_start, ABSOLUTE (.)) + *(.init_array) + 0x0000ff8c PROVIDE (__init_array_end, ABSOLUTE (.)) + 0x0000ff8c PROVIDE (__fini_array_start, ABSOLUTE (.)) + *(.fini_array) + 0x0000ff8c PROVIDE (__fini_array_end, ABSOLUTE (.)) + *(.eh_frame) + *(.gcc_except_table) + *(.dynamic) + 0x0000ff8c PROVIDE (__CTOR_LIST__, ABSOLUTE (.)) + *(.ctors) + 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0x00014344 0x100 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_handler.o) + 0x00014344 alt_irq + COMMON 0x00014444 0x190 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + 0x00014444 _atexit0 + 0x000145d4 . = ALIGN (0x4) + 0x000145d4 __bss_end = ABSOLUTE (.) + +.onchip_memory 0x000145d4 0x0 + 0x000145d4 PROVIDE (_alt_partition_onchip_memory_start, ABSOLUTE (.)) + *(.onchip_memory. onchip_memory.*) + 0x000145d4 . = ALIGN (0x4) + 0x000145d4 PROVIDE (_alt_partition_onchip_memory_end, ABSOLUTE (.)) + 0x000145d4 _end = ABSOLUTE (.) + 0x000145d4 end = ABSOLUTE (.) + 0x000145d4 __alt_stack_base = ABSOLUTE (.) + 0x000145d4 PROVIDE (_alt_partition_onchip_memory_load_addr, LOADADDR (.onchip_memory)) + +.stab + *(.stab) + +.stabstr + *(.stabstr) + +.stab.excl + *(.stab.excl) + +.stab.exclstr + *(.stab.exclstr) + +.stab.index + *(.stab.index) + +.stab.indexstr + *(.stab.indexstr) + +.comment 0x00000000 0x26 + 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0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strcmp.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-callocr.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-closer.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fclose.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_umoddi3.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_div_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_eq_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_ne_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_gt_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_ge_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_lt_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_si_to_df.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_df_to_si.o) + .comment 0x00000000 0x27 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_thenan_df.o) + .comment 0x00000000 0x27 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../DE2_115_ASM_bsp/\libhal_bsp.a(alt_close.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dev.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_errno.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_fstat.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_isatty.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_load.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_lseek.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_malloc_lock.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_read.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_release_fd.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sbrk.o) + .comment 0x00000000 0x27 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_usleep.o) + .comment 0x00000000 0x27 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c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_lt_df.o) + .debug_loc 0x0000b25d 0x9a c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_si_to_df.o) + .debug_loc 0x0000b2f7 0x8b c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_df_to_si.o) + .debug_loc 0x0000b382 0x5b c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) + .debug_loc 0x0000b3dd 0x103 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) + .debug_loc 0x0000b4e0 0x1e c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) + .debug_loc 0x0000b4fe 0x184 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) + .debug_loc 0x0000b682 0xe5 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_unpack_df.o) + .debug_loc 0x0000b767 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_close.o) + .debug_loc 0x0000b7bd 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dev.o) + .debug_loc 0x0000b7e8 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_fstat.o) + .debug_loc 0x0000b83e 0x57 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_isatty.o) + .debug_loc 0x0000b895 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_load.o) + .debug_loc 0x0000b8eb 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_lseek.o) + .debug_loc 0x0000b941 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_main.o) + .debug_loc 0x0000b96c 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_malloc_lock.o) + .debug_loc 0x0000b9c2 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_read.o) + .debug_loc 0x0000ba18 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_release_fd.o) + .debug_loc 0x0000ba43 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sbrk.o) + .debug_loc 0x0000ba6e 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_usleep.o) + .debug_loc 0x0000ba99 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_write.o) + .debug_loc 0x0000baef 0x81 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_sys_init.o) + .debug_loc 0x0000bb70 0xac ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) + .debug_loc 0x0000bc1c 0xac ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) + .debug_loc 0x0000bcc8 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) + .debug_loc 0x0000bcf3 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) + .debug_loc 0x0000bd1e 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) + .debug_loc 0x0000bd49 0x184 ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_lcd_16207.o) + .debug_loc 0x0000becd 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) + .debug_loc 0x0000bef8 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_alarm_start.o) + .debug_loc 0x0000bf23 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_busy_sleep.o) + .debug_loc 0x0000bf4e 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) + .debug_loc 0x0000bf79 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) + .debug_loc 0x0000bfcf 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_do_ctors.o) + .debug_loc 0x0000bffa 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_do_dtors.o) + .debug_loc 0x0000c025 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_icache_flush_all.o) + .debug_loc 0x0000c050 0xac ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic.o) + .debug_loc 0x0000c0fc 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_iic_isr_register.o) + .debug_loc 0x0000c127 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_io_redirect.o) + .debug_loc 0x0000c17d 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_handler.o) + .debug_loc 0x0000c1a8 0x81 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_open.o) + .debug_loc 0x0000c229 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_tick.o) + .debug_loc 0x0000c27f 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) + .debug_loc 0x0000c2aa 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_find_dev.o) + .debug_loc 0x0000c2d5 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_find_file.o) + .debug_loc 0x0000c300 0x2b ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_get_fd.o) + .debug_loc 0x0000c32b 0x1e c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) + .debug_loc 0x0000c349 0x3d c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) + .debug_loc 0x0000c386 0x114 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) + .debug_loc 0x0000c49a 0x120 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) + .debug_loc 0x0000c5ba 0x1cb c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) + .debug_loc 0x0000c785 0x56 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exit.o) + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) + +.debug_alt_sim_info + 0x00000000 0x40 + *(.debug_alt_sim_info) + .debug_alt_sim_info + 0x00000000 0x10 ../DE2_115_ASM_bsp//obj/HAL/src/crt0.o + .debug_alt_sim_info + 0x00000010 0x30 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_busy_sleep.o) + 0x00032000 __alt_data_end = 0x32000 + 0x00032000 PROVIDE (__alt_stack_pointer, __alt_data_end) + 0x000145d4 PROVIDE (__alt_stack_limit, __alt_stack_base) + 0x000145d4 PROVIDE (__alt_heap_start, end) + 0x00032000 PROVIDE (__alt_heap_limit, 0x32000) +OUTPUT(DE2_115_ASM.elf elf32-littlenios2) + +.debug_ranges 0x00000000 0x9e0 + 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c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-reallocr.o) + .debug_ranges 0x000003f0 0x38 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-callocr.o) + .debug_ranges 0x00000428 0x190 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) + .debug_ranges 0x000005b8 0x1c0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_umoddi3.o) + .debug_ranges 0x00000778 0x30 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) + .debug_ranges 0x000007a8 0x88 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) + .debug_ranges 0x00000830 0x50 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_div_df.o) + .debug_ranges 0x00000880 0x18 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) + .debug_ranges 0x00000898 0x88 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) + .debug_ranges 0x00000920 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) + .debug_ranges 0x00000948 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) + .debug_ranges 0x00000970 0x28 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_irq_entry.o) + .debug_ranges 0x00000998 0x30 ../DE2_115_ASM_bsp/\libhal_bsp.a(alt_exception_entry.o) + .debug_ranges 0x000009c8 0x18 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) diff --git a/software/DE2_115_ASM/DE2_115_ASM.objdump b/software/DE2_115_ASM/DE2_115_ASM.objdump new file mode 100644 index 0000000..6936a86 --- /dev/null +++ b/software/DE2_115_ASM/DE2_115_ASM.objdump @@ -0,0 +1,20932 @@ + +DE2_115_ASM.elf: file format elf32-littlenios2 +DE2_115_ASM.elf +architecture: nios2, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x000001b4 + +Program Header: + LOAD off 0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12 + filesz 0x00000020 memsz 0x00000020 flags r-x + LOAD off 0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12 + filesz 0x00010694 memsz 0x00010694 flags r-x + LOAD off 0x000116b4 vaddr 0x000106b4 paddr 0x0001223c align 2**12 + filesz 0x00001b88 memsz 0x00001b88 flags rw- + LOAD off 0x00013dc4 vaddr 0x00013dc4 paddr 0x00013dc4 align 2**12 + filesz 0x00000000 memsz 0x00000810 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .entry 00000020 00000000 00000000 00001000 2**5 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .exceptions 00000194 00000020 00000020 00001020 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 0000fddc 000001b4 000001b4 000011b4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .rodata 00000724 0000ff90 0000ff90 00010f90 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .rwdata 00001b88 000106b4 0001223c 000116b4 2**2 + CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA + 5 .bss 00000810 00013dc4 00013dc4 00013dc4 2**2 + ALLOC, SMALL_DATA + 6 .comment 00000026 00000000 00000000 0001323c 2**0 + CONTENTS, READONLY + 7 .debug_aranges 00000e18 00000000 00000000 00013268 2**3 + CONTENTS, READONLY, DEBUGGING + 8 .debug_pubnames 000017d8 00000000 00000000 00014080 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 000251cd 00000000 00000000 00015858 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00008258 00000000 00000000 0003aa25 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_line 00015d82 00000000 00000000 00042c7d 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_frame 0000202c 00000000 00000000 00058a00 2**2 + CONTENTS, READONLY, DEBUGGING + 13 .debug_str 000023b5 00000000 00000000 0005aa2c 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_loc 0000c7db 00000000 00000000 0005cde1 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_alt_sim_info 00000040 00000000 00000000 000695bc 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_ranges 000009e0 00000000 00000000 00069600 2**3 + CONTENTS, READONLY, DEBUGGING + 17 .thread_model 00000003 00000000 00000000 0006d7ff 2**0 + CONTENTS, READONLY + 18 .cpu 0000000f 00000000 00000000 0006d802 2**0 + CONTENTS, READONLY + 19 .qsys 00000001 00000000 00000000 0006d811 2**0 + CONTENTS, READONLY + 20 .simulation_enabled 00000001 00000000 00000000 0006d812 2**0 + CONTENTS, READONLY + 21 .stderr_dev 00000009 00000000 00000000 0006d813 2**0 + CONTENTS, READONLY + 22 .stdin_dev 00000009 00000000 00000000 0006d81c 2**0 + CONTENTS, READONLY + 23 .stdout_dev 00000009 00000000 00000000 0006d825 2**0 + CONTENTS, READONLY + 24 .sopc_system_name 0000000b 00000000 00000000 0006d82e 2**0 + CONTENTS, READONLY + 25 .quartus_project_dir 00000030 00000000 00000000 0006d839 2**0 + CONTENTS, READONLY + 26 .sopcinfo 0007d2ad 00000000 00000000 0006d869 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +00000000 l d .entry 00000000 .entry +00000020 l d .exceptions 00000000 .exceptions +000001b4 l d .text 00000000 .text +0000ff90 l d .rodata 00000000 .rodata +000106b4 l d .rwdata 00000000 .rwdata +00013dc4 l d .bss 00000000 .bss +00000000 l d .comment 00000000 .comment +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_pubnames 00000000 .debug_pubnames +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_alt_sim_info 00000000 .debug_alt_sim_info +00000000 l d .debug_ranges 00000000 .debug_ranges +000001ec l .text 00000000 alt_after_alt_main +00000000 l df *ABS* 00000000 alt_irq_handler.c +00000000 l df *ABS* 00000000 LCD.c +00000000 l df *ABS* 00000000 hello_world_small.c +000003dc l F .text 000000c0 init +00000734 l F .text 00000044 reset_mem_cancel +00000778 l F .text 000000b4 reset_mem +0000082c l F .text 00000044 reset_pc_cancel +00000870 l F .text 00000090 reset_pc +00000000 l df *ABS* 00000000 hex_encoder.c +00000000 l df *ABS* 00000000 hex_out.c +00000000 l df *ABS* 00000000 input_int.c +000014f8 l F .text 000000e8 update_sw_reg +00013dcc l O .bss 00000004 event_code.1400 +00013dd0 l O .bss 00000001 status.1399 +00000000 l df *ABS* 00000000 inst_decoder.c +00000000 l df *ABS* 00000000 lcd_out.c +00000000 l df *ABS* 00000000 sys_debug.c +00000000 l df *ABS* 00000000 sys_except.c +00000000 l df *ABS* 00000000 sys_memory.c +00013e0c l O .bss 00000100 memory +00013f0c l O .bss 00000400 inst_memory +00000000 l df *ABS* 00000000 sys_prog.c +00000000 l df *ABS* 00000000 sys_register.c +00000000 l df *ABS* 00000000 lib2-divmod.c +00002ad8 l F .text 0000007c udivmodsi4 +00000000 l df *ABS* 00000000 lib2-mul.c +00000000 l df *ABS* 00000000 ctype_.c +000101e5 l O .rodata 00000180 _ctype_b +00000000 l df *ABS* 00000000 sprintf.c +00000000 l df *ABS* 00000000 strlen.c +00000000 l df *ABS* 00000000 vfprintf.c +00002da4 l F .text 00000058 __sprint_r +000103d6 l O .rodata 00000010 blanks.3452 +000103c6 l O .rodata 00000010 zeroes.3453 +00000000 l df *ABS* 00000000 wsetup.c +00000000 l df *ABS* 00000000 dtoa.c +00004e20 l F .text 00000244 quorem +00000000 l df *ABS* 00000000 fflush.c +00000000 l df *ABS* 00000000 findfp.c +00006848 l F .text 00000058 std +00006954 l F .text 00000008 __fp_lock +0000695c l F .text 00000008 __fp_unlock +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 fvwrite.c +00000000 l df *ABS* 00000000 fwalk.c +00000000 l df *ABS* 00000000 impure.c +000106b4 l O .rwdata 00000400 impure_data +00000000 l df *ABS* 00000000 locale.c +00012204 l O .rwdata 00000004 charset +0001040c l O .rodata 00000030 lconv +00000000 l df *ABS* 00000000 makebuf.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 memchr.c +00000000 l df *ABS* 00000000 memcpy.c +00000000 l df *ABS* 00000000 memmove.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 mprec.c +00010554 l O .rodata 0000000c p05.2458 +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 s_isinfd.c +00000000 l df *ABS* 00000000 s_isnand.c +00000000 l df *ABS* 00000000 sbrkr.c +00000000 l df *ABS* 00000000 stdio.c +00000000 l df *ABS* 00000000 strcmp.c +00000000 l df *ABS* 00000000 writer.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 closer.c +00000000 l df *ABS* 00000000 fclose.c +00000000 l df *ABS* 00000000 fstatr.c +00000000 l df *ABS* 00000000 int_errno.c +00000000 l df *ABS* 00000000 isattyr.c +00000000 l df *ABS* 00000000 lseekr.c +00000000 l df *ABS* 00000000 readr.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 dp-bit.c +0000ad08 l F .text 00000410 _fpadd_parts +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 alt_close.c +0000c5ec l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_dev.c +0000c64c l F .text 0000002c alt_dev_null_write +00000000 l df *ABS* 00000000 alt_errno.c +00000000 l df *ABS* 00000000 alt_fstat.c +0000c750 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_isatty.c +0000c874 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_load.c +0000c954 l F .text 0000006c alt_load_section +00000000 l df *ABS* 00000000 alt_lseek.c +0000cab4 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_main.c +00000000 l df *ABS* 00000000 alt_malloc_lock.c +00000000 l df *ABS* 00000000 alt_read.c +0000cce4 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_release_fd.c +00000000 l df *ABS* 00000000 alt_sbrk.c +00012228 l O .rwdata 00000004 heap_end +00000000 l df *ABS* 00000000 alt_usleep.c +00000000 l df *ABS* 00000000 alt_write.c +0000cfcc l F .text 00000060 alt_get_errno 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alt_lcd_16207_timeout +00000000 l df *ABS* 00000000 altera_avalon_lcd_16207_fd.c +00000000 l df *ABS* 00000000 alt_alarm_start.c +00000000 l df *ABS* 00000000 alt_busy_sleep.c +00000000 l df *ABS* 00000000 alt_dcache_flush_all.c +00000000 l df *ABS* 00000000 alt_dev_llist_insert.c +0000eef8 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_do_ctors.c +00000000 l df *ABS* 00000000 alt_do_dtors.c +00000000 l df *ABS* 00000000 alt_icache_flush_all.c +00000000 l df *ABS* 00000000 alt_iic.c +00000000 l df *ABS* 00000000 alt_iic_isr_register.c +00000000 l df *ABS* 00000000 alt_io_redirect.c +0000f308 l F .text 000000d8 alt_open_fd +00000000 l df *ABS* 00000000 alt_irq_vars.c +00000000 l df *ABS* 00000000 alt_open.c +0000f458 l F .text 000000f8 alt_file_locked +0000f6dc l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_tick.c +00000000 l df *ABS* 00000000 altera_nios2_qsys_irq.c +00000000 l df *ABS* 00000000 alt_find_dev.c +00000000 l df *ABS* 00000000 alt_find_file.c +00000000 l df *ABS* 00000000 alt_get_fd.c +00000000 l df *ABS* 00000000 atexit.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 memcmp.c +00000000 l df *ABS* 00000000 __atexit.c +00000000 l df *ABS* 00000000 __call_atexit.c +0000fd78 l F .text 00000004 register_fini +00000000 l df *ABS* 00000000 alt_exit.c +0000ff2c l F .text 00000040 alt_sim_halt +00008638 g F .text 00000094 _mprec_log10 +00008724 g F .text 00000088 __any_on +00009edc g F .text 00000070 _isatty_r +0001052c g O .rodata 00000028 __mprec_tinytens +00001b20 g F .text 00000038 inst_load +0000cb14 g F .text 0000006c alt_main +00014344 g O .bss 00000100 alt_irq +00009f4c g F .text 00000078 _lseek_r +0001223c g *ABS* 00000000 __flash_rwdata_start +0000b828 g F .text 00000088 __eqdf2 +000145d4 g *ABS* 00000000 __alt_heap_start +000028c8 g F .text 00000070 get_pc +00009994 g F .text 00000068 __sseek +000068b0 g F .text 000000a4 __sinit +000027bc g F .text 00000084 inc_pc +00001348 g F .text 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inst_sub +0000f73c g F .text 00000098 alt_alarm_stop +00013e00 g O .bss 00000004 alt_irq_active +00001790 g F .text 0000004c inst_fetch +000000ec g F .exceptions 000000c8 alt_irq_handler +00010ec8 g O .rwdata 00000028 alt_dev_null +0000ee28 g F .text 0000001c alt_dcache_flush_all +00008254 g F .text 00000070 __hi0bits +00014334 g O .bss 0000000f global_registers +0000bbc8 g F .text 000000d8 __fixdfsi +00001d74 g F .text 0000006c inst_jeq +0001223c g *ABS* 00000000 __ram_rwdata_end +00000000 g *ABS* 00000000 __alt_mem_onchip_memory +00012218 g O .rwdata 00000008 alt_dev_list +0000cea8 g F .text 00000124 write +000106b4 g *ABS* 00000000 __ram_rodata_end +0000c678 g F .text 000000d8 fstat +00009078 g F .text 00000120 __pow5mult +00013dd8 g O .bss 00000004 __nlocale_changed +00002c1c g F .text 00000008 __umodsi3 +000145d4 g *ABS* 00000000 end +0000e3dc g F .text 0000053c altera_avalon_lcd_16207_write +00002840 g F .text 00000050 add_pc +0000d23c g F .text 000000c0 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+000086cc g F .text 00000058 __copybits +00010ac0 g O .rwdata 00000408 __malloc_av_ +000068ac g F .text 00000004 __sinit_lock_release +0000b20c g F .text 000003c4 __muldf3 +00009a78 g F .text 00000060 __sread +0000f994 g F .text 00000120 alt_find_file +0000ee44 g F .text 000000b4 alt_dev_llist_insert +0000cb80 g F .text 00000020 __malloc_lock +0000cdbc g F .text 000000bc sbrk +00006618 g F .text 000001fc _fflush_r +00009c0c g F .text 000000c8 _calloc_r +00013dc4 g *ABS* 00000000 __bss_start +000001f0 g F .text 0000009c LCD_Init +00008194 g F .text 00000098 memset +00001eec g F .text 00000048 lcd_init +00000900 g F .text 00000288 main +00013dfc g O .bss 00000004 alt_envp +00013dec g O .bss 00000004 __malloc_max_total_mem +0000d14c g F .text 00000058 altera_avalon_jtag_uart_write_fd +0000e9e4 g F .text 0000013c altera_avalon_lcd_16207_init +00000314 g F .text 0000003c LCD_Line2 +00000b88 g F .text 000001dc encodeNumHex +0000998c g F .text 00000008 __sclose +00032000 g *ABS* 00000000 __alt_heap_limit +00009e54 g F .text 00000014 fclose +00014444 g O .bss 00000190 _atexit0 +00005064 g F .text 000015b4 _dtoa_r +000077f0 g F .text 00000740 _malloc_r +00012224 g O .rwdata 00000004 alt_errno +000074e0 g F .text 000000b8 _fwalk +000014d0 g F .text 00000028 in_int +00002b54 g F .text 00000060 __divsi3 +00010560 g O .rodata 00000014 __thenan_df +00006b3c g F .text 0000012c _malloc_trim_r +0000ff90 g *ABS* 00000000 __CTOR_END__ +00009ad8 g F .text 000000bc strcmp +0000ff90 g *ABS* 00000000 __flash_rodata_start +0000ff90 g *ABS* 00000000 __DTOR_LIST__ +0000b8b0 g F .text 00000088 __nedf2 +0000d02c g F .text 00000034 alt_irq_init +0000028c g F .text 00000088 LCD_Show_Text +0000cd44 g F .text 00000078 alt_release_fd +00002c5c g F .text 00000074 sprintf +00010574 g O .rodata 00000100 __clz_tab +00013de0 g O .bss 00000004 _PathLocale +0000fb84 g F .text 00000014 atexit +00002890 g F .text 00000038 set_pc +00009b94 g F .text 00000078 _write_r +00007640 g F .text 0000001c setlocale +000006c4 g F .text 00000070 print_change_memory +0000168c g F .text 00000104 push_int +00002060 g F .text 0000006c display_mem +000121f8 g O .rwdata 00000004 _impure_ptr +00013df4 g O .bss 00000004 alt_argc +00013dd4 g O .bss 00000004 global_current_memory +0000efbc g F .text 00000064 _do_dtors +00000020 g .exceptions 00000000 alt_irq_entry +000083e8 g F .text 00000080 __ulp +000098ac g F .text 00000040 __isinfd +00006964 g F .text 00000018 __fp_unlock_all +0000eb20 g F .text 00000058 altera_avalon_lcd_16207_write_fd +00012210 g O .rwdata 00000008 alt_fs_list +00000020 g *ABS* 00000000 __ram_exceptions_start +000075ac g F .text 00000010 localeconv +00000d64 g F .text 00000454 encodeLatHex +0000223c g F .text 000002c4 convertInstName +0000f03c g F .text 00000050 alt_ic_isr_register +0001223c g *ABS* 00000000 _edata +000145d4 g *ABS* 00000000 _end +000001b4 g *ABS* 00000000 __ram_exceptions_end +0000d648 g F .text 000000f4 altera_avalon_jtag_uart_ioctl +00001f5c g F .text 00000028 lcd_caret_reset2 +0000f128 g F .text 000000a0 alt_ic_irq_disable +0000257c g F .text 0000007c memory_init +000099fc g F .text 0000007c __swrite +00012208 g O .rwdata 00000004 __malloc_trim_threshold +0000f8e0 g F .text 00000020 altera_nios2_qsys_irq_init +0000fb98 g F .text 00000038 exit +0000272c g F .text 00000090 memory_load +00007418 g F .text 000000c8 _fwalk_reent +000089e4 g F .text 0000018c __mdiff +00002bb4 g F .text 00000060 __modsi3 +00032000 g *ABS* 00000000 __alt_data_end +00000020 g F .exceptions 00000000 alt_exception +000068a4 g F .text 00000004 __sfp_lock_release +000017dc g F .text 00000278 inst_decode +000100e4 g O .rodata 00000101 _ctype_ +00001ca4 g F .text 000000d0 inst_comp +0000ff6c g F .text 00000020 _exit +000098ec g F .text 00000030 __isnand +00002a88 g F .text 00000050 registers_init +0000eb78 g F .text 00000154 alt_alarm_start +0000be34 g F .text 00000124 __muldi3 +0000765c g F .text 00000194 __smakebuf_r +00001de0 g F .text 0000006c inst_jne +00002d30 g F .text 00000074 strlen +0000f550 g F .text 0000018c open +0000b9c0 g F .text 00000088 __gedf2 +00000580 g F .text 00000144 store_inst +0000f020 g F .text 0000001c alt_icache_flush_all +00012230 g O .rwdata 00000004 alt_priority_mask +0000f08c g F .text 0000009c alt_ic_irq_enable +00004cc0 g F .text 00000024 __vfprintf_internal +0000b118 g F .text 00000080 __subdf3 +000082c4 g F .text 000000c4 __lo0bits +00012234 g O .rwdata 00000008 alt_alarm_list +0000ef58 g F .text 00000064 _do_ctors +000025f8 g F .text 00000050 inst_memory_store +0000c4ec g F .text 00000100 close +000015e0 g F .text 000000ac push_decode +0000c8d4 g F .text 00000080 alt_load +0000bfd8 g F .text 00000314 __pack_d +000121f0 g O .rwdata 00000001 PUSH_EVENT +00002648 g F .text 00000048 inst_memory_load +00000000 w *UND* 00000000 free +000068a8 g F .text 00000004 __sinit_lock_acquire +00008f4c g F .text 0000012c __multadd +0000822c g F .text 00000028 _Bfree + + + +Disassembly of section .entry: + +00000000 <__reset>: + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + 0: 00400034 movhi at,0 + ori r1, r1, %lo(_start) + 4: 08406d14 ori at,at,436 + jmp r1 + 8: 0800683a jmp at + ... + +Disassembly of section .exceptions: + +00000020 : + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + 20: deffed04 addi sp,sp,-76 + +#endif + +#endif + + stw ra, 0(sp) + 24: dfc00015 stw ra,0(sp) + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + 28: d8400215 stw at,8(sp) + stw r2, 12(sp) + 2c: d8800315 stw r2,12(sp) + stw r3, 16(sp) + 30: d8c00415 stw r3,16(sp) + stw r4, 20(sp) + 34: d9000515 stw r4,20(sp) + stw r5, 24(sp) + 38: d9400615 stw r5,24(sp) + stw r6, 28(sp) + 3c: d9800715 stw r6,28(sp) + stw r7, 32(sp) + 40: d9c00815 stw r7,32(sp) + + rdctl r5, estatus + 44: 000b307a rdctl r5,estatus + + stw r8, 36(sp) + 48: da000915 stw r8,36(sp) + stw r9, 40(sp) + 4c: da400a15 stw r9,40(sp) + stw r10, 44(sp) + 50: da800b15 stw r10,44(sp) + stw r11, 48(sp) + 54: dac00c15 stw r11,48(sp) + stw r12, 52(sp) + 58: db000d15 stw r12,52(sp) + stw r13, 56(sp) + 5c: db400e15 stw r13,56(sp) + stw r14, 60(sp) + 60: db800f15 stw r14,60(sp) + stw r15, 64(sp) + 64: dbc01015 stw r15,64(sp) + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + 68: d9401115 stw r5,68(sp) + addi r15, ea, -4 /* instruction that caused exception */ + 6c: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + 70: dbc01215 stw r15,72(sp) +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + 74: 0009313a rdctl r4,ipending + andi r2, r5, 1 + 78: 2880004c andi r2,r5,1 + beq r2, zero, .Lnot_irq + 7c: 10000326 beq r2,zero,8c + beq r4, zero, .Lnot_irq + 80: 20000226 beq r4,zero,8c + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + 84: 00000ec0 call ec + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + 88: 00000306 br 98 + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + 8c: df401215 stw ea,72(sp) + ldw r2, -4(ea) /* Instruction that caused exception */ + 90: e8bfff17 ldw r2,-4(ea) +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break + 94: 003da03a break 0 + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + 98: d9401117 ldw r5,68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + 9c: df401217 ldw ea,72(sp) + ldw ra, 0(sp) + a0: dfc00017 ldw ra,0(sp) + + wrctl estatus, r5 + a4: 2801707a wrctl estatus,r5 + + ldw r1, 8(sp) + a8: d8400217 ldw at,8(sp) + ldw r2, 12(sp) + ac: d8800317 ldw r2,12(sp) + ldw r3, 16(sp) + b0: d8c00417 ldw r3,16(sp) + ldw r4, 20(sp) + b4: d9000517 ldw r4,20(sp) + ldw r5, 24(sp) + b8: d9400617 ldw r5,24(sp) + ldw r6, 28(sp) + bc: d9800717 ldw r6,28(sp) + ldw r7, 32(sp) + c0: d9c00817 ldw r7,32(sp) +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + c4: da000917 ldw r8,36(sp) + ldw r9, 40(sp) + c8: da400a17 ldw r9,40(sp) + ldw r10, 44(sp) + cc: da800b17 ldw r10,44(sp) + ldw r11, 48(sp) + d0: dac00c17 ldw r11,48(sp) + ldw r12, 52(sp) + d4: db000d17 ldw r12,52(sp) + ldw r13, 56(sp) + d8: db400e17 ldw r13,56(sp) + ldw r14, 60(sp) + dc: db800f17 ldw r14,60(sp) + ldw r15, 64(sp) + e0: dbc01017 ldw r15,64(sp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + e4: dec01304 addi sp,sp,76 + + /* + * Return to the interrupted instruction. + */ + + eret + e8: ef80083a eret + +000000ec : + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ + ec: defff904 addi sp,sp,-28 + f0: dfc00615 stw ra,24(sp) + f4: df000515 stw fp,20(sp) + f8: df000504 addi fp,sp,20 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + fc: 0005313a rdctl r2,ipending + 100: e0bffc15 stw r2,-16(fp) + + return active; + 104: e0bffc17 ldw r2,-16(fp) + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + 108: e0bfff15 stw r2,-4(fp) + + do + { + i = 0; + 10c: e03ffd15 stw zero,-12(fp) + mask = 1; + 110: 00800044 movi r2,1 + 114: e0bffe15 stw r2,-8(fp) + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + 118: e0ffff17 ldw r3,-4(fp) + 11c: e0bffe17 ldw r2,-8(fp) + 120: 1884703a and r2,r3,r2 + 124: 1005003a cmpeq r2,r2,zero + 128: 1000161e bne r2,zero,184 + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); + 12c: e0bffd17 ldw r2,-12(fp) + 130: 00c00074 movhi r3,1 + 134: 18d0d104 addi r3,r3,17220 + 138: 100490fa slli r2,r2,3 + 13c: 10c5883a add r2,r2,r3 + 140: 11400017 ldw r5,0(r2) + 144: e0bffd17 ldw r2,-12(fp) + 148: 00c00074 movhi r3,1 + 14c: 18d0d104 addi r3,r3,17220 + 150: 100490fa slli r2,r2,3 + 154: 10c5883a add r2,r2,r3 + 158: 10800104 addi r2,r2,4 + 15c: 11000017 ldw r4,0(r2) + 160: 283ee83a callr r5 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 164: 0005313a rdctl r2,ipending + 168: e0bffb15 stw r2,-20(fp) + + return active; + 16c: e0bffb17 ldw r2,-20(fp) + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + 170: e0bfff15 stw r2,-4(fp) + + } while (active); + 174: e0bfff17 ldw r2,-4(fp) + 178: 1004c03a cmpne r2,r2,zero + 17c: 103fe31e bne r2,zero,10c + 180: 00000706 br 1a0 +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + 184: e0bffe17 ldw r2,-8(fp) + 188: 1085883a add r2,r2,r2 + 18c: e0bffe15 stw r2,-8(fp) + i++; + 190: e0bffd17 ldw r2,-12(fp) + 194: 10800044 addi r2,r2,1 + 198: e0bffd15 stw r2,-12(fp) + + } while (1); + 19c: 003fde06 br 118 + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); +} + 1a0: e037883a mov sp,fp + 1a4: dfc00117 ldw ra,4(sp) + 1a8: df000017 ldw fp,0(sp) + 1ac: dec00204 addi sp,sp,8 + 1b0: f800283a ret + +Disassembly of section .text: + +000001b4 <_start>: +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + 1b4: 06c000f4 movhi sp,3 + ori sp, sp, %lo(__alt_stack_pointer) + 1b8: dec80014 ori sp,sp,8192 + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + 1bc: 06800074 movhi gp,1 + ori gp, gp, %lo(_gp) + 1c0: d6a87c14 ori gp,gp,41456 + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + 1c4: 00800074 movhi r2,1 + ori r2, r2, %lo(__bss_start) + 1c8: 108f7114 ori r2,r2,15812 + + movhi r3, %hi(__bss_end) + 1cc: 00c00074 movhi r3,1 + ori r3, r3, %lo(__bss_end) + 1d0: 18d17514 ori r3,r3,17876 + + beq r2, r3, 1f + 1d4: 10c00326 beq r2,r3,1e4 <_start+0x30> + +0: + stw zero, (r2) + 1d8: 10000015 stw zero,0(r2) + addi r2, r2, 4 + 1dc: 10800104 addi r2,r2,4 + bltu r2, r3, 0b + 1e0: 10fffd36 bltu r2,r3,1d8 <_start+0x24> + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + 1e4: 000c8d40 call c8d4 + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + 1e8: 000cb140 call cb14 + +000001ec : + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + 1ec: 003fff06 br 1ec + +000001f0 : +#include +#include "system.h" +#include "LCD.h" +//------------------------------------------------------------------------- +void LCD_Init() +{ + 1f0: defffe04 addi sp,sp,-8 + 1f4: dfc00115 stw ra,4(sp) + 1f8: df000015 stw fp,0(sp) + 1fc: d839883a mov fp,sp + lcd_write_cmd(LCD_16207_0_BASE,0x38); + 200: 00c00134 movhi r3,4 + 204: 18c40c04 addi r3,r3,4144 + 208: 00800e04 movi r2,56 + 20c: 18800035 stwio r2,0(r3) + usleep(2000); + 210: 0101f404 movi r4,2000 + 214: 000ce780 call ce78 + lcd_write_cmd(LCD_16207_0_BASE,0x0C); + 218: 00c00134 movhi r3,4 + 21c: 18c40c04 addi r3,r3,4144 + 220: 00800304 movi r2,12 + 224: 18800035 stwio r2,0(r3) + usleep(2000); + 228: 0101f404 movi r4,2000 + 22c: 000ce780 call ce78 + lcd_write_cmd(LCD_16207_0_BASE,0x01); + 230: 00c00134 movhi r3,4 + 234: 18c40c04 addi r3,r3,4144 + 238: 00800044 movi r2,1 + 23c: 18800035 stwio r2,0(r3) + usleep(2000); + 240: 0101f404 movi r4,2000 + 244: 000ce780 call ce78 + lcd_write_cmd(LCD_16207_0_BASE,0x06); + 248: 00c00134 movhi r3,4 + 24c: 18c40c04 addi r3,r3,4144 + 250: 00800184 movi r2,6 + 254: 18800035 stwio r2,0(r3) + usleep(2000); + 258: 0101f404 movi r4,2000 + 25c: 000ce780 call ce78 + lcd_write_cmd(LCD_16207_0_BASE,0x80); + 260: 00c00134 movhi r3,4 + 264: 18c40c04 addi r3,r3,4144 + 268: 00802004 movi r2,128 + 26c: 18800035 stwio r2,0(r3) + usleep(2000); + 270: 0101f404 movi r4,2000 + 274: 000ce780 call ce78 +} + 278: e037883a mov sp,fp + 27c: dfc00117 ldw ra,4(sp) + 280: df000017 ldw fp,0(sp) + 284: dec00204 addi sp,sp,8 + 288: f800283a ret + +0000028c : +//------------------------------------------------------------------------- +void LCD_Show_Text(const char* Text) +{ + 28c: defffb04 addi sp,sp,-20 + 290: dfc00415 stw ra,16(sp) + 294: df000315 stw fp,12(sp) + 298: dc000215 stw r16,8(sp) + 29c: df000204 addi fp,sp,8 + 2a0: e13fff15 stw r4,-4(fp) + int i; + for(i=0;i + { + lcd_write_data(LCD_16207_0_BASE,Text[i]); + 2ac: e0bffe17 ldw r2,-8(fp) + 2b0: 1007883a mov r3,r2 + 2b4: e0bfff17 ldw r2,-4(fp) + 2b8: 1885883a add r2,r3,r2 + 2bc: 10800003 ldbu r2,0(r2) + 2c0: 10c03fcc andi r3,r2,255 + 2c4: 18c0201c xori r3,r3,128 + 2c8: 18ffe004 addi r3,r3,-128 + 2cc: 00800134 movhi r2,4 + 2d0: 10840e04 addi r2,r2,4152 + 2d4: 10c00035 stwio r3,0(r2) + usleep(2000); + 2d8: 0101f404 movi r4,2000 + 2dc: 000ce780 call ce78 +} +//------------------------------------------------------------------------- +void LCD_Show_Text(const char* Text) +{ + int i; + for(i=0;i + 2f8: 80bfec36 bltu r16,r2,2ac + { + lcd_write_data(LCD_16207_0_BASE,Text[i]); + usleep(2000); + } +} + 2fc: e037883a mov sp,fp + 300: dfc00217 ldw ra,8(sp) + 304: df000117 ldw fp,4(sp) + 308: dc000017 ldw r16,0(sp) + 30c: dec00304 addi sp,sp,12 + 310: f800283a ret + +00000314 : +//------------------------------------------------------------------------- +void LCD_Line2() +{ + 314: defffe04 addi sp,sp,-8 + 318: dfc00115 stw ra,4(sp) + 31c: df000015 stw fp,0(sp) + 320: d839883a mov fp,sp + lcd_write_cmd(LCD_16207_0_BASE,0xC0); + 324: 00c00134 movhi r3,4 + 328: 18c40c04 addi r3,r3,4144 + 32c: 00803004 movi r2,192 + 330: 18800035 stwio r2,0(r3) + usleep(2000); + 334: 0101f404 movi r4,2000 + 338: 000ce780 call ce78 +} + 33c: e037883a mov sp,fp + 340: dfc00117 ldw ra,4(sp) + 344: df000017 ldw fp,0(sp) + 348: dec00204 addi sp,sp,8 + 34c: f800283a ret + +00000350 : +//------------------------------------------------------------------------- +void LCD_Test() +{ + 350: defff604 addi sp,sp,-40 + 354: dfc00915 stw ra,36(sp) + 358: df000815 stw fp,32(sp) + 35c: df000804 addi fp,sp,32 + char Text1[16] = ""; + 360: 00c00074 movhi r3,1 + 364: 18ffe404 addi r3,r3,-112 + 368: 18800017 ldw r2,0(r3) + 36c: e0bff815 stw r2,-32(fp) + 370: 18800117 ldw r2,4(r3) + 374: e0bff915 stw r2,-28(fp) + 378: 18800217 ldw r2,8(r3) + 37c: e0bffa15 stw r2,-24(fp) + 380: 18800317 ldw r2,12(r3) + 384: e0bffb15 stw r2,-20(fp) + char Text2[16] = "Nice to See You!"; + 388: 00c00074 movhi r3,1 + 38c: 18ffe904 addi r3,r3,-92 + 390: 18800017 ldw r2,0(r3) + 394: e0bffc15 stw r2,-16(fp) + 398: 18800117 ldw r2,4(r3) + 39c: e0bffd15 stw r2,-12(fp) + 3a0: 18800217 ldw r2,8(r3) + 3a4: e0bffe15 stw r2,-8(fp) + 3a8: 18800317 ldw r2,12(r3) + 3ac: e0bfff15 stw r2,-4(fp) + // Initial LCD + LCD_Init(); + 3b0: 00001f00 call 1f0 + // Show Text to LCD + LCD_Show_Text(Text1); + 3b4: e13ff804 addi r4,fp,-32 + 3b8: 000028c0 call 28c + // Change Line2 + LCD_Line2(); + 3bc: 00003140 call 314 + // Show Text to LCD + LCD_Show_Text(Text2); + 3c0: e13ffc04 addi r4,fp,-16 + 3c4: 000028c0 call 28c +} + 3c8: e037883a mov sp,fp + 3cc: dfc00117 ldw ra,4(sp) + 3d0: df000017 ldw fp,0(sp) + 3d4: dec00204 addi sp,sp,8 + 3d8: f800283a ret + +000003dc : +#include "sys_debug.h" +#include "sys_prog.h" + +#define ledrs (volatile int *) LEDRS_BASE + +static void init() { + 3dc: defffe04 addi sp,sp,-8 + 3e0: dfc00115 stw ra,4(sp) + 3e4: df000015 stw fp,0(sp) + 3e8: d839883a mov fp,sp + // lcd + lcd_init(); + 3ec: 0001eec0 call 1eec + lcd_print("Starting now..."); + 3f0: 01000074 movhi r4,1 + 3f4: 213fee04 addi r4,r4,-72 + 3f8: 0001f840 call 1f84 + + registers_init(); + 3fc: 0002a880 call 2a88 + memory_init(); + 400: 000257c0 call 257c + // hex + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + 404: 0009883a mov r4,zero + 408: 00013480 call 1348 + 40c: 01000044 movi r4,1 + 410: 00013480 call 1348 + 414: 01000084 movi r4,2 + 418: 00013480 call 1348 + print_block("he", 2, HEX6_7); + 41c: 01000074 movhi r4,1 + 420: 213ff204 addi r4,r4,-56 + 424: 01400084 movi r5,2 + 428: 01800084 movi r6,2 + 42c: 00011b80 call 11b8 + print_block("lo", 2, HEX4_5); + 430: 01000074 movhi r4,1 + 434: 213ff304 addi r4,r4,-52 + 438: 01400084 movi r5,2 + 43c: 01800044 movi r6,1 + 440: 00011b80 call 11b8 + print_block("you1", 4, HEX0_3); + 444: 01000074 movhi r4,1 + 448: 213ff404 addi r4,r4,-48 + 44c: 01400104 movi r5,4 + 450: 000d883a mov r6,zero + 454: 00011b80 call 11b8 + delay10ms(200); + 458: 01003204 movi r4,200 + 45c: 00025000 call 2500 + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + 460: 0009883a mov r4,zero + 464: 00013480 call 1348 + 468: 01000044 movi r4,1 + 46c: 00013480 call 1348 + 470: 01000084 movi r4,2 + 474: 00013480 call 1348 + + lcd_caret_reset2(); + 478: 0001f5c0 call 1f5c + lcd_print("Ok!"); + 47c: 01000074 movhi r4,1 + 480: 213ff604 addi r4,r4,-40 + 484: 0001f840 call 1f84 +} + 488: e037883a mov sp,fp + 48c: dfc00117 ldw ra,4(sp) + 490: df000017 ldw fp,0(sp) + 494: dec00204 addi sp,sp,8 + 498: f800283a ret + +0000049c : + +char stack[5]; + +void store_value(){ + 49c: defffb04 addi sp,sp,-20 + 4a0: dfc00415 stw ra,16(sp) + 4a4: df000315 stw fp,12(sp) + 4a8: df000304 addi fp,sp,12 + unsigned int memi = global_registers[Ssw_memi]; + 4ac: 00800074 movhi r2,1 + 4b0: 1090cd04 addi r2,r2,17204 + 4b4: 10800283 ldbu r2,10(r2) + 4b8: 10803fcc andi r2,r2,255 + 4bc: 1080201c xori r2,r2,128 + 4c0: 10bfe004 addi r2,r2,-128 + 4c4: e0bffd15 stw r2,-12(fp) + memory_store(memi, Ssw_data); + 4c8: e13ffd17 ldw r4,-12(fp) + 4cc: 014001c4 movi r5,7 + 4d0: 00026900 call 2690 + + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "%02x", (unsigned char)memi); + 4d4: e0bffd17 ldw r2,-12(fp) + 4d8: 11803fcc andi r6,r2,255 + 4dc: e13ffe04 addi r4,fp,-8 + 4e0: 01400074 movhi r5,1 + 4e4: 297ff704 addi r5,r5,-36 + 4e8: 0002c5c0 call 2c5c + print_block(buf, 2, HEX6_7); + 4ec: e13ffe04 addi r4,fp,-8 + 4f0: 01400084 movi r5,2 + 4f4: 01800084 movi r6,2 + 4f8: 00011b80 call 11b8 + print_block("--", 2, HEX4_5); + 4fc: 01000074 movhi r4,1 + 500: 213ff904 addi r4,r4,-28 + 504: 01400084 movi r5,2 + 508: 01800044 movi r6,1 + 50c: 00011b80 call 11b8 + sprintf(buf, "%04d", global_registers[Ssw_data]); + 510: 00800074 movhi r2,1 + 514: 1090cd04 addi r2,r2,17204 + 518: 108001c3 ldbu r2,7(r2) + 51c: 11803fcc andi r6,r2,255 + 520: 3180201c xori r6,r6,128 + 524: 31bfe004 addi r6,r6,-128 + 528: e13ffe04 addi r4,fp,-8 + 52c: 01400074 movhi r5,1 + 530: 297ffa04 addi r5,r5,-24 + 534: 0002c5c0 call 2c5c + print_block(buf, 4, HEX0_3); + 538: e13ffe04 addi r4,fp,-8 + 53c: 01400104 movi r5,4 + 540: 000d883a mov r6,zero + 544: 00011b80 call 11b8 + + display_mem((unsigned char)memi, global_registers[Ssw_data]); + 548: e0bffd17 ldw r2,-12(fp) + 54c: 11003fcc andi r4,r2,255 + 550: 00800074 movhi r2,1 + 554: 1090cd04 addi r2,r2,17204 + 558: 108001c3 ldbu r2,7(r2) + 55c: 11403fcc andi r5,r2,255 + 560: 2940201c xori r5,r5,128 + 564: 297fe004 addi r5,r5,-128 + 568: 00020600 call 2060 + } +} + 56c: e037883a mov sp,fp + 570: dfc00117 ldw ra,4(sp) + 574: df000017 ldw fp,0(sp) + 578: dec00204 addi sp,sp,8 + 57c: f800283a ret + +00000580 : +void store_inst(){ + 580: defff904 addi sp,sp,-28 + 584: dfc00615 stw ra,24(sp) + 588: df000515 stw fp,20(sp) + 58c: df000504 addi fp,sp,20 + char reg_index; + unsigned int stored_pc; + struct InstRec inst_rec; + + // �K�v�ȏ��̎擾 + inst = global_registers[Ssw_inst]; + 590: 00800074 movhi r2,1 + 594: 1090cd04 addi r2,r2,17204 + 598: 10800203 ldbu r2,8(r2) + 59c: e0bffc85 stb r2,-14(fp) + mem_index = global_registers[Ssw_memi]; + 5a0: 00800074 movhi r2,1 + 5a4: 1090cd04 addi r2,r2,17204 + 5a8: 10800283 ldbu r2,10(r2) + 5ac: e0bffc45 stb r2,-15(fp) + reg_index = global_registers[Ssw_regi]; + 5b0: 00800074 movhi r2,1 + 5b4: 1090cd04 addi r2,r2,17204 + 5b8: 10800243 ldbu r2,9(r2) + 5bc: e0bffc05 stb r2,-16(fp) + inst_rec.inst = (unsigned int)inst; + 5c0: e0bffc83 ldbu r2,-14(fp) + 5c4: 108003cc andi r2,r2,15 + 5c8: 10803fcc andi r2,r2,255 + 5cc: 110003cc andi r4,r2,15 + 5d0: e0fffd17 ldw r3,-12(fp) + 5d4: 00bffc04 movi r2,-16 + 5d8: 1884703a and r2,r3,r2 + 5dc: 1104b03a or r2,r2,r4 + 5e0: e0bffd15 stw r2,-12(fp) + inst_rec.memi = (unsigned int)mem_index; + 5e4: e0bffc43 ldbu r2,-15(fp) + 5e8: 108003cc andi r2,r2,15 + 5ec: 10803fcc andi r2,r2,255 + 5f0: 108003cc andi r2,r2,15 + 5f4: 1008913a slli r4,r2,4 + 5f8: e0fffd17 ldw r3,-12(fp) + 5fc: 00bfc3c4 movi r2,-241 + 600: 1884703a and r2,r3,r2 + 604: 1104b03a or r2,r2,r4 + 608: e0bffd15 stw r2,-12(fp) + inst_rec.regi = (unsigned int)reg_index; + 60c: e0bffc03 ldbu r2,-16(fp) + 610: 108003cc andi r2,r2,15 + 614: 10803fcc andi r2,r2,255 + 618: 108003cc andi r2,r2,15 + 61c: 1008923a slli r4,r2,8 + 620: e0fffd17 ldw r3,-12(fp) + 624: 00bc3fc4 movi r2,-3841 + 628: 1884703a and r2,r3,r2 + 62c: 1104b03a or r2,r2,r4 + 630: e0bffd15 stw r2,-12(fp) + + // �X�g�A���� + stored_pc = get_pc(); + 634: 00028c80 call 28c8 + 638: e0bffb15 stw r2,-20(fp) + inst_memory_store(get_pc(), inst_rec); + 63c: 00028c80 call 28c8 + 640: 1009883a mov r4,r2 + 644: e17ffd17 ldw r5,-12(fp) + 648: 00025f80 call 25f8 + inc_pc(); + 64c: 00027bc0 call 27bc + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "%04d", inst_rec.inst); + 650: e0bffd17 ldw r2,-12(fp) + 654: 108003cc andi r2,r2,15 + 658: 11803fcc andi r6,r2,255 + 65c: e13ffe04 addi r4,fp,-8 + 660: 01400074 movhi r5,1 + 664: 297ffa04 addi r5,r5,-24 + 668: 0002c5c0 call 2c5c + print_block(buf, 4, HEX0_3); + 66c: e13ffe04 addi r4,fp,-8 + 670: 01400104 movi r5,4 + 674: 000d883a mov r6,zero + 678: 00011b80 call 11b8 + sprintf(buf, "%02x", get_pc()); + 67c: 00028c80 call 28c8 + 680: 100d883a mov r6,r2 + 684: e13ffe04 addi r4,fp,-8 + 688: 01400074 movhi r5,1 + 68c: 297ff704 addi r5,r5,-36 + 690: 0002c5c0 call 2c5c + print_block(buf, 2, HEX4_5); + 694: e13ffe04 addi r4,fp,-8 + 698: 01400084 movi r5,2 + 69c: 01800044 movi r6,1 + 6a0: 00011b80 call 11b8 + + display_inst(inst_rec, stored_pc); + 6a4: e13ffd17 ldw r4,-12(fp) + 6a8: e17ffb17 ldw r5,-20(fp) + 6ac: 0001fb40 call 1fb4 + } +} + 6b0: e037883a mov sp,fp + 6b4: dfc00117 ldw ra,4(sp) + 6b8: df000017 ldw fp,0(sp) + 6bc: dec00204 addi sp,sp,8 + 6c0: f800283a ret + +000006c4 : + +void print_change_memory(unsigned int current_memory) { + 6c4: defff804 addi sp,sp,-32 + 6c8: dfc00715 stw ra,28(sp) + 6cc: df000615 stw fp,24(sp) + 6d0: df000604 addi fp,sp,24 + 6d4: e13fff15 stw r4,-4(fp) + char buf[17]; + sprintf(buf, "Current page:%2d", current_memory); + 6d8: e13ffa04 addi r4,fp,-24 + 6dc: 01400074 movhi r5,1 + 6e0: 297ffc04 addi r5,r5,-16 + 6e4: e1bfff17 ldw r6,-4(fp) + 6e8: 0002c5c0 call 2c5c + lcd_caret_reset(); + 6ec: 0001f340 call 1f34 + lcd_print("Change program"); + 6f0: 01000074 movhi r4,1 + 6f4: 21000104 addi r4,r4,4 + 6f8: 0001f840 call 1f84 + lcd_caret_reset2(); + 6fc: 0001f5c0 call 1f5c + lcd_print(buf); + 700: e13ffa04 addi r4,fp,-24 + 704: 0001f840 call 1f84 + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + 708: 0009883a mov r4,zero + 70c: 00013480 call 1348 + 710: 01000044 movi r4,1 + 714: 00013480 call 1348 + 718: 01000084 movi r4,2 + 71c: 00013480 call 1348 +} + 720: e037883a mov sp,fp + 724: dfc00117 ldw ra,4(sp) + 728: df000017 ldw fp,0(sp) + 72c: dec00204 addi sp,sp,8 + 730: f800283a ret + +00000734 : + +static void reset_mem_cancel() { + 734: defffe04 addi sp,sp,-8 + 738: dfc00115 stw ra,4(sp) + 73c: df000015 stw fp,0(sp) + 740: d839883a mov fp,sp + lcd_caret_reset(); + 744: 0001f340 call 1f34 + lcd_print("rewrite all 0?"); + 748: 01000074 movhi r4,1 + 74c: 21000504 addi r4,r4,20 + 750: 0001f840 call 1f84 + lcd_caret_reset2(); + 754: 0001f5c0 call 1f5c + lcd_print("push again -> NG"); + 758: 01000074 movhi r4,1 + 75c: 21000904 addi r4,r4,36 + 760: 0001f840 call 1f84 +} + 764: e037883a mov sp,fp + 768: dfc00117 ldw ra,4(sp) + 76c: df000017 ldw fp,0(sp) + 770: dec00204 addi sp,sp,8 + 774: f800283a ret + +00000778 : +static char reset_mem(char confirmed) { + 778: defffb04 addi sp,sp,-20 + 77c: dfc00415 stw ra,16(sp) + 780: df000315 stw fp,12(sp) + 784: df000304 addi fp,sp,12 + 788: e13ffe05 stb r4,-8(fp) + if (confirmed == 0) { + 78c: e0bffe07 ldb r2,-8(fp) + 790: 1004c03a cmpne r2,r2,zero + 794: 10000b1e bne r2,zero,7c4 + lcd_caret_reset(); + 798: 0001f340 call 1f34 + lcd_print("rewrite all 0?"); + 79c: 01000074 movhi r4,1 + 7a0: 21000504 addi r4,r4,20 + 7a4: 0001f840 call 1f84 + lcd_caret_reset2(); + 7a8: 0001f5c0 call 1f5c + lcd_print("push again"); + 7ac: 01000074 movhi r4,1 + 7b0: 21000e04 addi r4,r4,56 + 7b4: 0001f840 call 1f84 + // �m�F�v�� + return 1; + 7b8: 00800044 movi r2,1 + 7bc: e0bfff15 stw r2,-4(fp) + 7c0: 00001406 br 814 + } else { + int i; + for (i = 0; i < MEM_SIZE; i++){ + 7c4: e03ffd15 stw zero,-12(fp) + 7c8: 00000606 br 7e4 + memory_store(i,Szero); + 7cc: e13ffd17 ldw r4,-12(fp) + 7d0: 000b883a mov r5,zero + 7d4: 00026900 call 2690 + lcd_print("push again"); + // �m�F�v�� + return 1; + } else { + int i; + for (i = 0; i < MEM_SIZE; i++){ + 7d8: e0bffd17 ldw r2,-12(fp) + 7dc: 10800044 addi r2,r2,1 + 7e0: e0bffd15 stw r2,-12(fp) + 7e4: e0bffd17 ldw r2,-12(fp) + 7e8: 10800410 cmplti r2,r2,16 + 7ec: 103ff71e bne r2,zero,7cc + memory_store(i,Szero); + } + lcd_caret_reset(); + 7f0: 0001f340 call 1f34 + lcd_print("rewrite all 0?"); + 7f4: 01000074 movhi r4,1 + 7f8: 21000504 addi r4,r4,20 + 7fc: 0001f840 call 1f84 + lcd_caret_reset2(); + 800: 0001f5c0 call 1f5c + lcd_print("push again -> OK"); + 804: 01000074 movhi r4,1 + 808: 21001104 addi r4,r4,68 + 80c: 0001f840 call 1f84 + + // PC���Z�b�g���� + return 0; + 810: e03fff15 stw zero,-4(fp) + 814: e0bfff17 ldw r2,-4(fp) + } +} + 818: e037883a mov sp,fp + 81c: dfc00117 ldw ra,4(sp) + 820: df000017 ldw fp,0(sp) + 824: dec00204 addi sp,sp,8 + 828: f800283a ret + +0000082c : +static void reset_pc_cancel() { + 82c: defffe04 addi sp,sp,-8 + 830: dfc00115 stw ra,4(sp) + 834: df000015 stw fp,0(sp) + 838: d839883a mov fp,sp + lcd_caret_reset(); + 83c: 0001f340 call 1f34 + lcd_print("reset pc?"); + 840: 01000074 movhi r4,1 + 844: 21001604 addi r4,r4,88 + 848: 0001f840 call 1f84 + lcd_caret_reset2(); + 84c: 0001f5c0 call 1f5c + lcd_print("push again -> NG"); + 850: 01000074 movhi r4,1 + 854: 21000904 addi r4,r4,36 + 858: 0001f840 call 1f84 +} + 85c: e037883a mov sp,fp + 860: dfc00117 ldw ra,4(sp) + 864: df000017 ldw fp,0(sp) + 868: dec00204 addi sp,sp,8 + 86c: f800283a ret + +00000870 : +static char reset_pc(char confirmed) { + 870: defffc04 addi sp,sp,-16 + 874: dfc00315 stw ra,12(sp) + 878: df000215 stw fp,8(sp) + 87c: df000204 addi fp,sp,8 + 880: e13ffe05 stb r4,-8(fp) + if (confirmed == 0) { + 884: e0bffe07 ldb r2,-8(fp) + 888: 1004c03a cmpne r2,r2,zero + 88c: 10000b1e bne r2,zero,8bc + lcd_caret_reset(); + 890: 0001f340 call 1f34 + lcd_print("reset pc?"); + 894: 01000074 movhi r4,1 + 898: 21001604 addi r4,r4,88 + 89c: 0001f840 call 1f84 + lcd_caret_reset2(); + 8a0: 0001f5c0 call 1f5c + lcd_print("push again"); + 8a4: 01000074 movhi r4,1 + 8a8: 21000e04 addi r4,r4,56 + 8ac: 0001f840 call 1f84 + // �m�F�v�� + return 1; + 8b0: 00800044 movi r2,1 + 8b4: e0bfff15 stw r2,-4(fp) + 8b8: 00000b06 br 8e8 + } else { + set_pc(0); + 8bc: 0009883a mov r4,zero + 8c0: 00028900 call 2890 + + lcd_caret_reset(); + 8c4: 0001f340 call 1f34 + lcd_print("reset pc?"); + 8c8: 01000074 movhi r4,1 + 8cc: 21001604 addi r4,r4,88 + 8d0: 0001f840 call 1f84 + lcd_caret_reset2(); + 8d4: 0001f5c0 call 1f5c + lcd_print("push again -> OK"); + 8d8: 01000074 movhi r4,1 + 8dc: 21001104 addi r4,r4,68 + 8e0: 0001f840 call 1f84 + + // PC���Z�b�g���� + return 0; + 8e4: e03fff15 stw zero,-4(fp) + 8e8: e0bfff17 ldw r2,-4(fp) + } +} + 8ec: e037883a mov sp,fp + 8f0: dfc00117 ldw ra,4(sp) + 8f4: df000017 ldw fp,0(sp) + 8f8: dec00204 addi sp,sp,8 + 8fc: f800283a ret + +00000900
: + + +int main() +{ + 900: defffc04 addi sp,sp,-16 + 904: dfc00315 stw ra,12(sp) + 908: df000215 stw fp,8(sp) + 90c: df000204 addi fp,sp,8 + init(); + 910: 00003dc0 call 3dc + + enum RunMode fRun = RUN_STOP; + 914: e03fff15 stw zero,-4(fp) + char reset_pc_confirmed = 0; + 918: e03ffec5 stb zero,-5(fp) + char reset_mem_confirmed = 0; + 91c: e03ffe85 stb zero,-6(fp) + 920: 00000006 br 924 + + while(1) { + // interrupt + in_int(); + 924: 00014d00 call 14d0 + + // event + // CANCEL + if (global_registers[Ssw_rw] == 0 + 928: 00800074 movhi r2,1 + 92c: 1090cd04 addi r2,r2,17204 + 930: 10800303 ldbu r2,12(r2) + 934: 10803fcc andi r2,r2,255 + 938: 1080201c xori r2,r2,128 + 93c: 10bfe004 addi r2,r2,-128 + 940: 1005003a cmpeq r2,r2,zero + 944: 10000e1e bne r2,zero,980 + 948: 00800074 movhi r2,1 + 94c: 10887c04 addi r2,r2,8688 + 950: 10800003 ldbu r2,0(r2) + 954: 10803fcc andi r2,r2,255 + 958: 1080008c andi r2,r2,2 + 95c: 1005003a cmpeq r2,r2,zero + 960: 10000c1e bne r2,zero,994 + 964: 00800074 movhi r2,1 + 968: 10887c04 addi r2,r2,8688 + 96c: 10800003 ldbu r2,0(r2) + 970: 10803fcc andi r2,r2,255 + 974: 1080010c andi r2,r2,4 + 978: 1004c03a cmpne r2,r2,zero + 97c: 1000051e bne r2,zero,994 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_VALSTR))) { + if (reset_mem_confirmed == 1) { + 980: e0bffe87 ldb r2,-6(fp) + 984: 10800058 cmpnei r2,r2,1 + 988: 1000021e bne r2,zero,994 + reset_mem_confirmed = 0; //�m�F�L�����Z�� + 98c: e03ffe85 stb zero,-6(fp) + reset_mem_cancel(); + 990: 00007340 call 734 + } + } + if (global_registers[Ssw_rw] == 0 + 994: 00800074 movhi r2,1 + 998: 1090cd04 addi r2,r2,17204 + 99c: 10800303 ldbu r2,12(r2) + 9a0: 10803fcc andi r2,r2,255 + 9a4: 1080201c xori r2,r2,128 + 9a8: 10bfe004 addi r2,r2,-128 + 9ac: 1005003a cmpeq r2,r2,zero + 9b0: 10000e1e bne r2,zero,9ec + 9b4: 00800074 movhi r2,1 + 9b8: 10887c04 addi r2,r2,8688 + 9bc: 10800003 ldbu r2,0(r2) + 9c0: 10803fcc andi r2,r2,255 + 9c4: 1080008c andi r2,r2,2 + 9c8: 1005003a cmpeq r2,r2,zero + 9cc: 10000c1e bne r2,zero,a00 + 9d0: 00800074 movhi r2,1 + 9d4: 10887c04 addi r2,r2,8688 + 9d8: 10800003 ldbu r2,0(r2) + 9dc: 10803fcc andi r2,r2,255 + 9e0: 1080020c andi r2,r2,8 + 9e4: 1004c03a cmpne r2,r2,zero + 9e8: 1000051e bne r2,zero,a00 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_INSSTR))) { + if (reset_pc_confirmed == 1) { + 9ec: e0bffec7 ldb r2,-5(fp) + 9f0: 10800058 cmpnei r2,r2,1 + 9f4: 1000021e bne r2,zero,a00 + reset_pc_confirmed = 0; //�m�F�L�����Z�� + 9f8: e03ffec5 stb zero,-5(fp) + reset_pc_cancel(); + 9fc: 000082c0 call 82c + } + } + // CONFIRM + if (PUSH_EVENT & PUSH_VALSTR) { + a00: 00800074 movhi r2,1 + a04: 10887c04 addi r2,r2,8688 + a08: 10800003 ldbu r2,0(r2) + a0c: 10803fcc andi r2,r2,255 + a10: 1080010c andi r2,r2,4 + a14: 1005003a cmpeq r2,r2,zero + a18: 1000161e bne r2,zero,a74 + // �l�̃X�g�A + if (global_registers[Ssw_rw] == 1) { + a1c: 00800074 movhi r2,1 + a20: 1090cd04 addi r2,r2,17204 + a24: 10800303 ldbu r2,12(r2) + a28: 10803fcc andi r2,r2,255 + a2c: 1080201c xori r2,r2,128 + a30: 10bfe004 addi r2,r2,-128 + a34: 10800058 cmpnei r2,r2,1 + a38: 10000d1e bne r2,zero,a70 + //�폜 + char res = reset_mem(reset_mem_confirmed);//���m�F�̏��F + a3c: e13ffe87 ldb r4,-6(fp) + a40: 00007780 call 778 + a44: e0bffe45 stb r2,-7(fp) + if (1 == res) reset_mem_confirmed = 1; //���m�F + a48: e0bffe47 ldb r2,-7(fp) + a4c: 10800058 cmpnei r2,r2,1 + a50: 1000021e bne r2,zero,a5c + a54: 00800044 movi r2,1 + a58: e0bffe85 stb r2,-6(fp) + if (0 == res) reset_mem_confirmed = 0; //���Z�b�g�̊m�F + a5c: e0bffe47 ldb r2,-7(fp) + a60: 1004c03a cmpne r2,r2,zero + a64: 1000031e bne r2,zero,a74 + a68: e03ffe85 stb zero,-6(fp) + a6c: 00000106 br a74 + } else { + store_value(); + a70: 000049c0 call 49c + } + } + if (PUSH_EVENT & PUSH_INSSTR) { + a74: 00800074 movhi r2,1 + a78: 10887c04 addi r2,r2,8688 + a7c: 10800003 ldbu r2,0(r2) + a80: 10803fcc andi r2,r2,255 + a84: 1080020c andi r2,r2,8 + a88: 1005003a cmpeq r2,r2,zero + a8c: 1000161e bne r2,zero,ae8 + // ���߂̃X�g�A + if (global_registers[Ssw_rw] == 1) { + a90: 00800074 movhi r2,1 + a94: 1090cd04 addi r2,r2,17204 + a98: 10800303 ldbu r2,12(r2) + a9c: 10803fcc andi r2,r2,255 + aa0: 1080201c xori r2,r2,128 + aa4: 10bfe004 addi r2,r2,-128 + aa8: 10800058 cmpnei r2,r2,1 + aac: 10000d1e bne r2,zero,ae4 + //PC�̃��Z�b�g + char res = reset_pc(reset_pc_confirmed);//���m�F�̏��F + ab0: e13ffec7 ldb r4,-5(fp) + ab4: 00008700 call 870 + ab8: e0bffe05 stb r2,-8(fp) + if (1 == res) reset_pc_confirmed = 1; //���m�F + abc: e0bffe07 ldb r2,-8(fp) + ac0: 10800058 cmpnei r2,r2,1 + ac4: 1000021e bne r2,zero,ad0 + ac8: 00800044 movi r2,1 + acc: e0bffec5 stb r2,-5(fp) + if (0 == res) reset_pc_confirmed = 0; //���Z�b�g�̊m�F + ad0: e0bffe07 ldb r2,-8(fp) + ad4: 1004c03a cmpne r2,r2,zero + ad8: 1000031e bne r2,zero,ae8 + adc: e03ffec5 stb zero,-5(fp) + ae0: 00000106 br ae8 + } else { + store_inst(); + ae4: 00005800 call 580 + } + } + // RUN + if (PUSH_EVENT & PUSH_RUN) { + ae8: 00800074 movhi r2,1 + aec: 10887c04 addi r2,r2,8688 + af0: 10800003 ldbu r2,0(r2) + af4: 10803fcc andi r2,r2,255 + af8: 1080040c andi r2,r2,16 + afc: 1005003a cmpeq r2,r2,zero + b00: 10001a1e bne r2,zero,b6c + if (global_current_memory != (unsigned int)global_registers[Ssw_psel]) { + b04: 00800074 movhi r2,1 + b08: 1090cd04 addi r2,r2,17204 + b0c: 108002c3 ldbu r2,11(r2) + b10: 10c03fcc andi r3,r2,255 + b14: 18c0201c xori r3,r3,128 + b18: 18ffe004 addi r3,r3,-128 + b1c: 00800074 movhi r2,1 + b20: 108f7504 addi r2,r2,15828 + b24: 10800017 ldw r2,0(r2) + b28: 18800e26 beq r3,r2,b64 + global_current_memory = (unsigned int)global_registers[Ssw_psel]; + b2c: 00800074 movhi r2,1 + b30: 1090cd04 addi r2,r2,17204 + b34: 108002c3 ldbu r2,11(r2) + b38: 10c03fcc andi r3,r2,255 + b3c: 18c0201c xori r3,r3,128 + b40: 18ffe004 addi r3,r3,-128 + b44: 00800074 movhi r2,1 + b48: 108f7504 addi r2,r2,15828 + b4c: 10c00015 stw r3,0(r2) + print_change_memory(global_current_memory); + b50: 00800074 movhi r2,1 + b54: 108f7504 addi r2,r2,15828 + b58: 11000017 ldw r4,0(r2) + b5c: 00006c40 call 6c4 + b60: 00000206 br b6c + } + else { + // �v���O�����������ݒ� + fRun = RUN_INIT; + b64: 00800044 movi r2,1 + b68: e0bfff15 stw r2,-4(fp) + } + } + if (fRun != RUN_STOP) { + b6c: e0bfff17 ldw r2,-4(fp) + b70: 1005003a cmpeq r2,r2,zero + b74: 103f6b1e bne r2,zero,924 + // �v���O�������s���荞�� & ���s���[�h�X�V + fRun = run_proc(fRun); + b78: e13fff17 ldw r4,-4(fp) + b7c: 00029380 call 2938 + b80: e0bfff15 stw r2,-4(fp) + } + } + b84: 003f6706 br 924 + +00000b88 : + */ + +#include "hex_encoder.h" +#include + +void encodeNumHex(int hex_i, int num) { + b88: defffc04 addi sp,sp,-16 + b8c: df000315 stw fp,12(sp) + b90: df000304 addi fp,sp,12 + b94: e13ffe15 stw r4,-8(fp) + b98: e17fff15 stw r5,-4(fp) + char encoded = 0; + b9c: e03ffd05 stb zero,-12(fp) + switch (num) { + ba0: e0bfff17 ldw r2,-4(fp) + ba4: 108002a8 cmpgeui r2,r2,10 + ba8: 10002f1e bne r2,zero,c68 + bac: e0bfff17 ldw r2,-4(fp) + bb0: 1085883a add r2,r2,r2 + bb4: 1087883a add r3,r2,r2 + bb8: 00800034 movhi r2,0 + bbc: 1082f304 addi r2,r2,3020 + bc0: 1885883a add r2,r3,r2 + bc4: 10800017 ldw r2,0(r2) + bc8: 1000683a jmp r2 + bcc: 00000bf4 movhi zero,47 + bd0: 00000c00 call c0 <__flash_exceptions_start+0xa0> + bd4: 00000c0c andi zero,zero,48 + bd8: 00000c18 cmpnei zero,zero,48 + bdc: 00000c24 muli zero,zero,48 + be0: 00000c30 cmpltui zero,zero,48 + be4: 00000c3c xorhi zero,zero,48 + be8: 00000c48 cmpgei zero,zero,49 + bec: 00000c54 movui zero,49 + bf0: 00000c5c xori zero,zero,49 + case 0: + encoded = (char)0x40; // 100 0000 + bf4: 00801004 movi r2,64 + bf8: e0bffd05 stb r2,-12(fp) + break; + bfc: 00001b06 br c6c + case 1: + encoded = (char)0xF9; // 111 1001 + c00: 00bffe44 movi r2,-7 + c04: e0bffd05 stb r2,-12(fp) + break; + c08: 00001806 br c6c + case 2: + encoded = (char)0x24; // 010 0100 + c0c: 00800904 movi r2,36 + c10: e0bffd05 stb r2,-12(fp) + break; + c14: 00001506 br c6c + case 3: + encoded = (char)0x30; // 011 0000 + c18: 00800c04 movi r2,48 + c1c: e0bffd05 stb r2,-12(fp) + break; + c20: 00001206 br c6c + case 4: + encoded = (char)0x19; // 001 1001 + c24: 00800644 movi r2,25 + c28: e0bffd05 stb r2,-12(fp) + break; + c2c: 00000f06 br c6c + case 5: + encoded = (char)0x12; // 001 0010 + c30: 00800484 movi r2,18 + c34: e0bffd05 stb r2,-12(fp) + break; + c38: 00000c06 br c6c + case 6: + encoded = (char)0x02; // 000 0010 + c3c: 00800084 movi r2,2 + c40: e0bffd05 stb r2,-12(fp) + break; + c44: 00000906 br c6c + case 7: + encoded = (char)0x58; // 101 1000 + c48: 00801604 movi r2,88 + c4c: e0bffd05 stb r2,-12(fp) + break; + c50: 00000606 br c6c + case 8: + encoded = (char)0x00; // 000 0000 + c54: e03ffd05 stb zero,-12(fp) + break; + c58: 00000406 br c6c + case 9: + encoded = (char)0x10; // 001 0000 + c5c: 00800404 movi r2,16 + c60: e0bffd05 stb r2,-12(fp) + break; + c64: 00000106 br c6c + default: + encoded = 0; + c68: e03ffd05 stb zero,-12(fp) + break; + } + + switch (hex_i) { + c6c: e0bffe17 ldw r2,-8(fp) + c70: 10800228 cmpgeui r2,r2,8 + c74: 1000371e bne r2,zero,d54 + c78: e0bffe17 ldw r2,-8(fp) + c7c: 1085883a add r2,r2,r2 + c80: 1087883a add r3,r2,r2 + c84: 00800034 movhi r2,0 + c88: 10832604 addi r2,r2,3224 + c8c: 1885883a add r2,r3,r2 + c90: 10800017 ldw r2,0(r2) + c94: 1000683a jmp r2 + c98: 00000cb8 rdprs zero,zero,50 + c9c: 00000ccc andi zero,zero,51 + ca0: 00000ce0 cmpeqi zero,zero,51 + ca4: 00000cf4 movhi zero,51 + ca8: 00000d08 cmpgei zero,zero,52 + cac: 00000d1c xori zero,zero,52 + cb0: 00000d30 cmpltui zero,zero,52 + cb4: 00000d44 movi zero,53 + case 0: + *hex0 = encoded; + cb8: 00c00134 movhi r3,4 + cbc: 18c42c04 addi r3,r3,4272 + cc0: e0bffd03 ldbu r2,-12(fp) + cc4: 18800005 stb r2,0(r3) + break; + cc8: 00002206 br d54 + case 1: + *hex1 = encoded; + ccc: 00c00134 movhi r3,4 + cd0: 18c42804 addi r3,r3,4256 + cd4: e0bffd03 ldbu r2,-12(fp) + cd8: 18800005 stb r2,0(r3) + break; + cdc: 00001d06 br d54 + case 2: + *hex2 = encoded; + ce0: 00c00134 movhi r3,4 + ce4: 18c42404 addi r3,r3,4240 + ce8: e0bffd03 ldbu r2,-12(fp) + cec: 18800005 stb r2,0(r3) + break; + cf0: 00001806 br d54 + case 3: + *hex3 = encoded; + cf4: 00c00134 movhi r3,4 + cf8: 18c42004 addi r3,r3,4224 + cfc: e0bffd03 ldbu r2,-12(fp) + d00: 18800005 stb r2,0(r3) + break; + d04: 00001306 br d54 + case 4: + *hex4 = encoded; + d08: 00c00134 movhi r3,4 + d0c: 18c41c04 addi r3,r3,4208 + d10: e0bffd03 ldbu r2,-12(fp) + d14: 18800005 stb r2,0(r3) + break; + d18: 00000e06 br d54 + case 5: + *hex5 = encoded; + d1c: 00c00134 movhi r3,4 + d20: 18c41804 addi r3,r3,4192 + d24: e0bffd03 ldbu r2,-12(fp) + d28: 18800005 stb r2,0(r3) + break; + d2c: 00000906 br d54 + case 6: + *hex6 = encoded; + d30: 00c00134 movhi r3,4 + d34: 18c41404 addi r3,r3,4176 + d38: e0bffd03 ldbu r2,-12(fp) + d3c: 18800005 stb r2,0(r3) + break; + d40: 00000406 br d54 + case 7: + *hex7 = encoded; + d44: 00c00134 movhi r3,4 + d48: 18c41004 addi r3,r3,4160 + d4c: e0bffd03 ldbu r2,-12(fp) + d50: 18800005 stb r2,0(r3) + break; + default: + break; + } +} + d54: e037883a mov sp,fp + d58: df000017 ldw fp,0(sp) + d5c: dec00104 addi sp,sp,4 + d60: f800283a ret + +00000d64 : + +void encodeLatHex(int hex_i, char c) { + d64: defffa04 addi sp,sp,-24 + d68: dfc00515 stw ra,20(sp) + d6c: df000415 stw fp,16(sp) + d70: df000404 addi fp,sp,16 + d74: e13ffd15 stw r4,-12(fp) + d78: e17ffe05 stb r5,-8(fp) + char encoded = 0; + d7c: e03ffc05 stb zero,-16(fp) + + if (isdigit(c)) { + d80: e0bffe07 ldb r2,-8(fp) + d84: 1007883a mov r3,r2 + d88: 00800074 movhi r2,1 + d8c: 10887d04 addi r2,r2,8692 + d90: 10800017 ldw r2,0(r2) + d94: 1885883a add r2,r3,r2 + d98: 10800003 ldbu r2,0(r2) + d9c: 10803fcc andi r2,r2,255 + da0: 1080010c andi r2,r2,4 + da4: 1005003a cmpeq r2,r2,zero + da8: 1000051e bne r2,zero,dc0 + encodeNumHex(hex_i, c-'0'); + dac: e0bffe07 ldb r2,-8(fp) + db0: 117ff404 addi r5,r2,-48 + db4: e13ffd17 ldw r4,-12(fp) + db8: 0000b880 call b88 + return; + dbc: 0000f906 br 11a4 + } + + switch (c) { + dc0: e0bffe07 ldb r2,-8(fp) + dc4: 10bff804 addi r2,r2,-32 + dc8: e0bfff15 stw r2,-4(fp) + dcc: e0ffff17 ldw r3,-4(fp) + dd0: 188016e8 cmpgeui r2,r3,91 + dd4: 1000b81e bne r2,zero,10b8 + dd8: e13fff17 ldw r4,-4(fp) + ddc: e13fff17 ldw r4,-4(fp) + de0: 2105883a add r2,r4,r4 + de4: 1087883a add r3,r2,r2 + de8: 00800034 movhi r2,0 + dec: 10837f04 addi r2,r2,3580 + df0: 1885883a add r2,r3,r2 + df4: 10800017 ldw r2,0(r2) + df8: 1000683a jmp r2 + dfc: 00000f68 cmpgeui zero,zero,61 + e00: 000010b8 rdprs zero,zero,66 + e04: 000010b8 rdprs zero,zero,66 + e08: 000010b8 rdprs zero,zero,66 + e0c: 000010b8 rdprs zero,zero,66 + e10: 000010b8 rdprs zero,zero,66 + e14: 000010b8 rdprs zero,zero,66 + e18: 000010b8 rdprs zero,zero,66 + e1c: 000010b8 rdprs zero,zero,66 + e20: 000010b8 rdprs zero,zero,66 + e24: 000010b8 rdprs zero,zero,66 + e28: 000010b8 rdprs zero,zero,66 + e2c: 000010b8 rdprs zero,zero,66 + e30: 00000f74 movhi zero,61 + e34: 000010b8 rdprs zero,zero,66 + e38: 000010b8 rdprs zero,zero,66 + e3c: 000010b8 rdprs zero,zero,66 + e40: 000010b8 rdprs zero,zero,66 + e44: 000010b8 rdprs zero,zero,66 + e48: 000010b8 rdprs zero,zero,66 + e4c: 000010b8 rdprs zero,zero,66 + e50: 000010b8 rdprs zero,zero,66 + e54: 000010b8 rdprs zero,zero,66 + e58: 000010b8 rdprs zero,zero,66 + e5c: 000010b8 rdprs zero,zero,66 + e60: 000010b8 rdprs zero,zero,66 + e64: 000010b8 rdprs zero,zero,66 + e68: 000010b8 rdprs zero,zero,66 + e6c: 000010b8 rdprs zero,zero,66 + e70: 000010b8 rdprs zero,zero,66 + e74: 000010b8 rdprs zero,zero,66 + e78: 000010b8 rdprs zero,zero,66 + e7c: 000010b8 rdprs zero,zero,66 + e80: 000010b8 rdprs zero,zero,66 + e84: 000010b8 rdprs zero,zero,66 + e88: 000010b8 rdprs zero,zero,66 + e8c: 000010b8 rdprs zero,zero,66 + e90: 000010b8 rdprs zero,zero,66 + e94: 000010b8 rdprs zero,zero,66 + e98: 000010b8 rdprs zero,zero,66 + e9c: 000010b8 rdprs zero,zero,66 + ea0: 000010b8 rdprs zero,zero,66 + ea4: 000010b8 rdprs zero,zero,66 + ea8: 000010b8 rdprs zero,zero,66 + eac: 000010b8 rdprs zero,zero,66 + eb0: 000010b8 rdprs zero,zero,66 + eb4: 000010b8 rdprs zero,zero,66 + eb8: 000010b8 rdprs zero,zero,66 + ebc: 000010b8 rdprs zero,zero,66 + ec0: 000010b8 rdprs zero,zero,66 + ec4: 000010b8 rdprs zero,zero,66 + ec8: 000010b8 rdprs zero,zero,66 + ecc: 000010b8 rdprs zero,zero,66 + ed0: 000010b8 rdprs zero,zero,66 + ed4: 000010b8 rdprs zero,zero,66 + ed8: 000010b8 rdprs zero,zero,66 + edc: 000010b8 rdprs zero,zero,66 + ee0: 000010b8 rdprs zero,zero,66 + ee4: 000010b8 rdprs zero,zero,66 + ee8: 000010b8 rdprs zero,zero,66 + eec: 000010b8 rdprs zero,zero,66 + ef0: 000010b8 rdprs zero,zero,66 + ef4: 000010b8 rdprs zero,zero,66 + ef8: 000010b8 rdprs zero,zero,66 + efc: 000010b8 rdprs zero,zero,66 + f00: 00000f80 call f8 + f04: 00000f8c andi zero,zero,62 + f08: 00000f98 cmpnei zero,zero,62 + f0c: 00000fa4 muli zero,zero,62 + f10: 00000fb0 cmpltui zero,zero,62 + f14: 00000fbc xorhi zero,zero,62 + f18: 00000fc8 cmpgei zero,zero,63 + f1c: 00000fd4 movui zero,63 + f20: 00000fe0 cmpeqi zero,zero,63 + f24: 00000fec andhi zero,zero,63 + f28: 00000ff8 rdprs zero,zero,63 + f2c: 00001004 movi zero,64 + f30: 00001010 cmplti zero,zero,64 + f34: 0000101c xori zero,zero,64 + f38: 00001028 cmpgeui zero,zero,64 + f3c: 00001034 movhi zero,64 + f40: 00001040 call 104 + f44: 0000104c andi zero,zero,65 + f48: 00001058 cmpnei zero,zero,65 + f4c: 00001064 muli zero,zero,65 + f50: 00001070 cmpltui zero,zero,65 + f54: 0000107c xorhi zero,zero,65 + f58: 00001088 cmpgei zero,zero,66 + f5c: 00001094 movui zero,66 + f60: 000010a0 cmpeqi zero,zero,66 + f64: 000010ac andhi zero,zero,66 + case ' ': + encoded = (char)0xFF; // 111 1111 + f68: 00bfffc4 movi r2,-1 + f6c: e0bffc05 stb r2,-16(fp) + break; + f70: 00005206 br 10bc + case '-': + encoded = (char)0x3F; // 011 1111 + f74: 00800fc4 movi r2,63 + f78: e0bffc05 stb r2,-16(fp) + break; + f7c: 00004f06 br 10bc + case 'a': + encoded = (char)0x08; // 000 1000 + f80: 00800204 movi r2,8 + f84: e0bffc05 stb r2,-16(fp) + break; + f88: 00004c06 br 10bc + case 'b': + encoded = (char)0x03; // 000 0011 + f8c: 008000c4 movi r2,3 + f90: e0bffc05 stb r2,-16(fp) + break; + f94: 00004906 br 10bc + case 'c': + encoded = (char)0x27; // 010 0111 + f98: 008009c4 movi r2,39 + f9c: e0bffc05 stb r2,-16(fp) + break; + fa0: 00004606 br 10bc + case 'd': + encoded = (char)0x21; // 010 0001 + fa4: 00800844 movi r2,33 + fa8: e0bffc05 stb r2,-16(fp) + break; + fac: 00004306 br 10bc + case 'e': + encoded = (char)0x06; // 000 0110 + fb0: 00800184 movi r2,6 + fb4: e0bffc05 stb r2,-16(fp) + break; + fb8: 00004006 br 10bc + case 'f': + encoded = (char)0x0E; // 000 1110 + fbc: 00800384 movi r2,14 + fc0: e0bffc05 stb r2,-16(fp) + break; + fc4: 00003d06 br 10bc + case 'g': + encoded = (char)0x42; // 100 0010 + fc8: 00801084 movi r2,66 + fcc: e0bffc05 stb r2,-16(fp) + break; + fd0: 00003a06 br 10bc + case 'h': + encoded = (char)0x0B; // 000 1011 + fd4: 008002c4 movi r2,11 + fd8: e0bffc05 stb r2,-16(fp) + break; + fdc: 00003706 br 10bc + case 'i': + encoded = (char)0xFB; // 111 1011 + fe0: 00bffec4 movi r2,-5 + fe4: e0bffc05 stb r2,-16(fp) + break; + fe8: 00003406 br 10bc + case 'j': + encoded = (char)0x61; // 110 0001 + fec: 00801844 movi r2,97 + ff0: e0bffc05 stb r2,-16(fp) + break; + ff4: 00003106 br 10bc + case 'k': + encoded = (char)0x0A; // 000 1010 + ff8: 00800284 movi r2,10 + ffc: e0bffc05 stb r2,-16(fp) + break; + 1000: 00002e06 br 10bc + case 'l': + encoded = (char)0x47; // 100 0111 + 1004: 008011c4 movi r2,71 + 1008: e0bffc05 stb r2,-16(fp) + break; + 100c: 00002b06 br 10bc + case 'm': + encoded = (char)0x48; // 100 1000 + 1010: 00801204 movi r2,72 + 1014: e0bffc05 stb r2,-16(fp) + break; + 1018: 00002806 br 10bc + case 'n': + encoded = (char)0x2B; // 010 1011 + 101c: 00800ac4 movi r2,43 + 1020: e0bffc05 stb r2,-16(fp) + break; + 1024: 00002506 br 10bc + case 'o': + encoded = (char)0x23; // 010 0011 + 1028: 008008c4 movi r2,35 + 102c: e0bffc05 stb r2,-16(fp) + break; + 1030: 00002206 br 10bc + case 'p': + encoded = (char)0x0C; // 000 1100 + 1034: 00800304 movi r2,12 + 1038: e0bffc05 stb r2,-16(fp) + break; + 103c: 00001f06 br 10bc + case 'q': + encoded = (char)0x04; // 000 0100 + 1040: 00800104 movi r2,4 + 1044: e0bffc05 stb r2,-16(fp) + break; + 1048: 00001c06 br 10bc + case 'r': + encoded = (char)0x2F; // 010 1111 + 104c: 00800bc4 movi r2,47 + 1050: e0bffc05 stb r2,-16(fp) + break; + 1054: 00001906 br 10bc + case 's': + encoded = (char)0x13; // 001 0011 + 1058: 008004c4 movi r2,19 + 105c: e0bffc05 stb r2,-16(fp) + break; + 1060: 00001606 br 10bc + case 't': + encoded = (char)0x07; // 000 0111 + 1064: 008001c4 movi r2,7 + 1068: e0bffc05 stb r2,-16(fp) + break; + 106c: 00001306 br 10bc + case 'u': + encoded = (char)0x63; // 110 0011 + 1070: 008018c4 movi r2,99 + 1074: e0bffc05 stb r2,-16(fp) + break; + 1078: 00001006 br 10bc + case 'v': + encoded = (char)0x41; // 100 0001 + 107c: 00801044 movi r2,65 + 1080: e0bffc05 stb r2,-16(fp) + break; + 1084: 00000d06 br 10bc + case 'w': + encoded = (char)0x01; // 000 0001 + 1088: 00800044 movi r2,1 + 108c: e0bffc05 stb r2,-16(fp) + break; + 1090: 00000a06 br 10bc + case 'x': + encoded = (char)0x09; // 000 1001 + 1094: 00800244 movi r2,9 + 1098: e0bffc05 stb r2,-16(fp) + break; + 109c: 00000706 br 10bc + case 'y': + encoded = (char)0x11; // 001 0001 + 10a0: 00800444 movi r2,17 + 10a4: e0bffc05 stb r2,-16(fp) + break; + 10a8: 00000406 br 10bc + case 'z': + encoded = (char)0x64; // 110 0100 + 10ac: 00801904 movi r2,100 + 10b0: e0bffc05 stb r2,-16(fp) + break; + 10b4: 00000106 br 10bc + default: + encoded = 0; + 10b8: e03ffc05 stb zero,-16(fp) + break; + } + + switch (hex_i) { + 10bc: e0bffd17 ldw r2,-12(fp) + 10c0: 10800228 cmpgeui r2,r2,8 + 10c4: 1000371e bne r2,zero,11a4 + 10c8: e0bffd17 ldw r2,-12(fp) + 10cc: 1085883a add r2,r2,r2 + 10d0: 1087883a add r3,r2,r2 + 10d4: 00800034 movhi r2,0 + 10d8: 10843a04 addi r2,r2,4328 + 10dc: 1885883a add r2,r3,r2 + 10e0: 10800017 ldw r2,0(r2) + 10e4: 1000683a jmp r2 + 10e8: 00001108 cmpgei zero,zero,68 + 10ec: 0000111c xori zero,zero,68 + 10f0: 00001130 cmpltui zero,zero,68 + 10f4: 00001144 movi zero,69 + 10f8: 00001158 cmpnei zero,zero,69 + 10fc: 0000116c andhi zero,zero,69 + 1100: 00001180 call 118 + 1104: 00001194 movui zero,70 + case 0: + *hex0 = encoded; + 1108: 00c00134 movhi r3,4 + 110c: 18c42c04 addi r3,r3,4272 + 1110: e0bffc03 ldbu r2,-16(fp) + 1114: 18800005 stb r2,0(r3) + break; + 1118: 00002206 br 11a4 + case 1: + *hex1 = encoded; + 111c: 00c00134 movhi r3,4 + 1120: 18c42804 addi r3,r3,4256 + 1124: e0bffc03 ldbu r2,-16(fp) + 1128: 18800005 stb r2,0(r3) + break; + 112c: 00001d06 br 11a4 + case 2: + *hex2 = encoded; + 1130: 00c00134 movhi r3,4 + 1134: 18c42404 addi r3,r3,4240 + 1138: e0bffc03 ldbu r2,-16(fp) + 113c: 18800005 stb r2,0(r3) + break; + 1140: 00001806 br 11a4 + case 3: + *hex3 = encoded; + 1144: 00c00134 movhi r3,4 + 1148: 18c42004 addi r3,r3,4224 + 114c: e0bffc03 ldbu r2,-16(fp) + 1150: 18800005 stb r2,0(r3) + break; + 1154: 00001306 br 11a4 + case 4: + *hex4 = encoded; + 1158: 00c00134 movhi r3,4 + 115c: 18c41c04 addi r3,r3,4208 + 1160: e0bffc03 ldbu r2,-16(fp) + 1164: 18800005 stb r2,0(r3) + break; + 1168: 00000e06 br 11a4 + case 5: + *hex5 = encoded; + 116c: 00c00134 movhi r3,4 + 1170: 18c41804 addi r3,r3,4192 + 1174: e0bffc03 ldbu r2,-16(fp) + 1178: 18800005 stb r2,0(r3) + break; + 117c: 00000906 br 11a4 + case 6: + *hex6 = encoded; + 1180: 00c00134 movhi r3,4 + 1184: 18c41404 addi r3,r3,4176 + 1188: e0bffc03 ldbu r2,-16(fp) + 118c: 18800005 stb r2,0(r3) + break; + 1190: 00000406 br 11a4 + case 7: + *hex7 = encoded; + 1194: 00c00134 movhi r3,4 + 1198: 18c41004 addi r3,r3,4160 + 119c: e0bffc03 ldbu r2,-16(fp) + 11a0: 18800005 stb r2,0(r3) + break; + default: + break; + } +} + 11a4: e037883a mov sp,fp + 11a8: dfc00117 ldw ra,4(sp) + 11ac: df000017 ldw fp,0(sp) + 11b0: dec00204 addi sp,sp,8 + 11b4: f800283a ret + +000011b8 : + */ +#include "hex_out.h" +#include "hex_encoder.h" +#include "sys_except.h" + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { + 11b8: defffa04 addi sp,sp,-24 + 11bc: dfc00515 stw ra,20(sp) + 11c0: df000415 stw fp,16(sp) + 11c4: df000404 addi fp,sp,16 + 11c8: e13ffd15 stw r4,-12(fp) + 11cc: e17ffe15 stw r5,-8(fp) + 11d0: e1bfff15 stw r6,-4(fp) + int i; + if (block_i == HEX0_3) { + 11d4: e0bfff17 ldw r2,-4(fp) + 11d8: 1004c03a cmpne r2,r2,zero + 11dc: 10001a1e bne r2,zero,1248 + if (size > 4) panic(); + 11e0: e0bffe17 ldw r2,-8(fp) + 11e4: 10800170 cmpltui r2,r2,5 + 11e8: 1000011e bne r2,zero,11f0 + 11ec: 000253c0 call 253c + for (i = 0; i < size; i++) { + 11f0: e03ffc15 stw zero,-16(fp) + 11f4: 00001006 br 1238 + encodeLatHex(i,str[size-1-i]); + 11f8: e0fffc17 ldw r3,-16(fp) + 11fc: e0bffe17 ldw r2,-8(fp) + 1200: 10c5c83a sub r2,r2,r3 + 1204: 1007883a mov r3,r2 + 1208: e0bffd17 ldw r2,-12(fp) + 120c: 1885883a add r2,r3,r2 + 1210: 10bfffc4 addi r2,r2,-1 + 1214: 10800003 ldbu r2,0(r2) + 1218: 11403fcc andi r5,r2,255 + 121c: 2940201c xori r5,r5,128 + 1220: 297fe004 addi r5,r5,-128 + 1224: e13ffc17 ldw r4,-16(fp) + 1228: 0000d640 call d64 + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { + int i; + if (block_i == HEX0_3) { + if (size > 4) panic(); + for (i = 0; i < size; i++) { + 122c: e0bffc17 ldw r2,-16(fp) + 1230: 10800044 addi r2,r2,1 + 1234: e0bffc15 stw r2,-16(fp) + 1238: e0fffc17 ldw r3,-16(fp) + 123c: e0bffe17 ldw r2,-8(fp) + 1240: 18bfed36 bltu r3,r2,11f8 + 1244: 00003b06 br 1334 + encodeLatHex(i,str[size-1-i]); + } + } + else if (block_i == HEX4_5) { + 1248: e0bfff17 ldw r2,-4(fp) + 124c: 10800058 cmpnei r2,r2,1 + 1250: 10001b1e bne r2,zero,12c0 + if (size > 2) panic(); + 1254: e0bffe17 ldw r2,-8(fp) + 1258: 108000f0 cmpltui r2,r2,3 + 125c: 1000011e bne r2,zero,1264 + 1260: 000253c0 call 253c + for (i = 0; i < size; i++) { + 1264: e03ffc15 stw zero,-16(fp) + 1268: 00001106 br 12b0 + encodeLatHex(i+4,str[size-1-i]); + 126c: e0bffc17 ldw r2,-16(fp) + 1270: 11000104 addi r4,r2,4 + 1274: e0fffc17 ldw r3,-16(fp) + 1278: e0bffe17 ldw r2,-8(fp) + 127c: 10c5c83a sub r2,r2,r3 + 1280: 1007883a mov r3,r2 + 1284: e0bffd17 ldw r2,-12(fp) + 1288: 1885883a add r2,r3,r2 + 128c: 10bfffc4 addi r2,r2,-1 + 1290: 10800003 ldbu r2,0(r2) + 1294: 11403fcc andi r5,r2,255 + 1298: 2940201c xori r5,r5,128 + 129c: 297fe004 addi r5,r5,-128 + 12a0: 0000d640 call d64 + encodeLatHex(i,str[size-1-i]); + } + } + else if (block_i == HEX4_5) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + 12a4: e0bffc17 ldw r2,-16(fp) + 12a8: 10800044 addi r2,r2,1 + 12ac: e0bffc15 stw r2,-16(fp) + 12b0: e0fffc17 ldw r3,-16(fp) + 12b4: e0bffe17 ldw r2,-8(fp) + 12b8: 18bfec36 bltu r3,r2,126c + 12bc: 00001d06 br 1334 + encodeLatHex(i+4,str[size-1-i]); + } + } + else if (block_i == HEX6_7) { + 12c0: e0bfff17 ldw r2,-4(fp) + 12c4: 10800098 cmpnei r2,r2,2 + 12c8: 10001a1e bne r2,zero,1334 + if (size > 2) panic(); + 12cc: e0bffe17 ldw r2,-8(fp) + 12d0: 108000f0 cmpltui r2,r2,3 + 12d4: 1000011e bne r2,zero,12dc + 12d8: 000253c0 call 253c + for (i = 0; i < size; i++) { + 12dc: e03ffc15 stw zero,-16(fp) + 12e0: 00001106 br 1328 + encodeLatHex(i+6,str[size-1-i]); + 12e4: e0bffc17 ldw r2,-16(fp) + 12e8: 11000184 addi r4,r2,6 + 12ec: e0fffc17 ldw r3,-16(fp) + 12f0: e0bffe17 ldw r2,-8(fp) + 12f4: 10c5c83a sub r2,r2,r3 + 12f8: 1007883a mov r3,r2 + 12fc: e0bffd17 ldw r2,-12(fp) + 1300: 1885883a add r2,r3,r2 + 1304: 10bfffc4 addi r2,r2,-1 + 1308: 10800003 ldbu r2,0(r2) + 130c: 11403fcc andi r5,r2,255 + 1310: 2940201c xori r5,r5,128 + 1314: 297fe004 addi r5,r5,-128 + 1318: 0000d640 call d64 + encodeLatHex(i+4,str[size-1-i]); + } + } + else if (block_i == HEX6_7) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + 131c: e0bffc17 ldw r2,-16(fp) + 1320: 10800044 addi r2,r2,1 + 1324: e0bffc15 stw r2,-16(fp) + 1328: e0fffc17 ldw r3,-16(fp) + 132c: e0bffe17 ldw r2,-8(fp) + 1330: 18bfec36 bltu r3,r2,12e4 + encodeLatHex(i+6,str[size-1-i]); + } + } +} + 1334: e037883a mov sp,fp + 1338: dfc00117 ldw ra,4(sp) + 133c: df000017 ldw fp,0(sp) + 1340: dec00204 addi sp,sp,8 + 1344: f800283a ret + +00001348 : + +void clear_block(enum BLOCK_N block_i) { + 1348: defffd04 addi sp,sp,-12 + 134c: dfc00215 stw ra,8(sp) + 1350: df000115 stw fp,4(sp) + 1354: df000104 addi fp,sp,4 + 1358: e13fff15 stw r4,-4(fp) + if (block_i == HEX0_3) { + 135c: e0bfff17 ldw r2,-4(fp) + 1360: 1004c03a cmpne r2,r2,zero + 1364: 1000061e bne r2,zero,1380 + print_block(" ", 4, HEX0_3); + 1368: 01000074 movhi r4,1 + 136c: 21001904 addi r4,r4,100 + 1370: 01400104 movi r5,4 + 1374: 000d883a mov r6,zero + 1378: 00011b80 call 11b8 + 137c: 00001106 br 13c4 + } + else if (block_i == HEX4_5) { + 1380: e0bfff17 ldw r2,-4(fp) + 1384: 10800058 cmpnei r2,r2,1 + 1388: 1000061e bne r2,zero,13a4 + print_block(" ", 2, HEX4_5); + 138c: 01000074 movhi r4,1 + 1390: 21001b04 addi r4,r4,108 + 1394: 01400084 movi r5,2 + 1398: 01800044 movi r6,1 + 139c: 00011b80 call 11b8 + 13a0: 00000806 br 13c4 + } + else if (block_i == HEX6_7) { + 13a4: e0bfff17 ldw r2,-4(fp) + 13a8: 10800098 cmpnei r2,r2,2 + 13ac: 1000051e bne r2,zero,13c4 + print_block(" ", 2, HEX6_7); + 13b0: 01000074 movhi r4,1 + 13b4: 21001b04 addi r4,r4,108 + 13b8: 01400084 movi r5,2 + 13bc: 01800084 movi r6,2 + 13c0: 00011b80 call 11b8 + } +} + 13c4: e037883a mov sp,fp + 13c8: dfc00117 ldw ra,4(sp) + 13cc: df000017 ldw fp,0(sp) + 13d0: dec00204 addi sp,sp,8 + 13d4: f800283a ret + +000013d8 : + +void print_number(char num) { + 13d8: defff904 addi sp,sp,-28 + 13dc: dfc00615 stw ra,24(sp) + 13e0: df000515 stw fp,20(sp) + 13e4: df000504 addi fp,sp,20 + 13e8: e13fff05 stb r4,-4(fp) + int i; + char buf[5]; + char val; + for (i = 0; i < 4; i++) { + 13ec: e03ffc15 stw zero,-16(fp) + 13f0: 00002906 br 1498 + if (num < 0) { + 13f4: e0bfff07 ldb r2,-4(fp) + 13f8: 1004403a cmpge r2,r2,zero + 13fc: 1000061e bne r2,zero,1418 + buf[0] = '-'; + 1400: 00800b44 movi r2,45 + 1404: e0bffd05 stb r2,-12(fp) + val = -num; + 1408: e0bfff03 ldbu r2,-4(fp) + 140c: 0085c83a sub r2,zero,r2 + 1410: e0bffb05 stb r2,-20(fp) + 1414: 00000406 br 1428 + } else { + buf[0] = ' '; + 1418: 00800804 movi r2,32 + 141c: e0bffd05 stb r2,-12(fp) + val = num; + 1420: e0bfff03 ldbu r2,-4(fp) + 1424: e0bffb05 stb r2,-20(fp) + } + buf[1] = val/100%10 + '0'; + 1428: e13ffb07 ldb r4,-20(fp) + 142c: 01401904 movi r5,100 + 1430: 0002b540 call 2b54 <__divsi3> + 1434: 11003fcc andi r4,r2,255 + 1438: 2100201c xori r4,r4,128 + 143c: 213fe004 addi r4,r4,-128 + 1440: 01400284 movi r5,10 + 1444: 0002bb40 call 2bb4 <__modsi3> + 1448: 10800c04 addi r2,r2,48 + 144c: e0bffd45 stb r2,-11(fp) + buf[2] = val/10%10 + '0'; + 1450: e13ffb07 ldb r4,-20(fp) + 1454: 01400284 movi r5,10 + 1458: 0002b540 call 2b54 <__divsi3> + 145c: 11003fcc andi r4,r2,255 + 1460: 2100201c xori r4,r4,128 + 1464: 213fe004 addi r4,r4,-128 + 1468: 01400284 movi r5,10 + 146c: 0002bb40 call 2bb4 <__modsi3> + 1470: 10800c04 addi r2,r2,48 + 1474: e0bffd85 stb r2,-10(fp) + buf[3] = val%10 + '0'; + 1478: e13ffb07 ldb r4,-20(fp) + 147c: 01400284 movi r5,10 + 1480: 0002bb40 call 2bb4 <__modsi3> + 1484: 10800c04 addi r2,r2,48 + 1488: e0bffdc5 stb r2,-9(fp) + +void print_number(char num) { + int i; + char buf[5]; + char val; + for (i = 0; i < 4; i++) { + 148c: e0bffc17 ldw r2,-16(fp) + 1490: 10800044 addi r2,r2,1 + 1494: e0bffc15 stw r2,-16(fp) + 1498: e0bffc17 ldw r2,-16(fp) + 149c: 10800110 cmplti r2,r2,4 + 14a0: 103fd41e bne r2,zero,13f4 + } + buf[1] = val/100%10 + '0'; + buf[2] = val/10%10 + '0'; + buf[3] = val%10 + '0'; + } + clear_block(HEX0_3); + 14a4: 0009883a mov r4,zero + 14a8: 00013480 call 1348 + print_block(buf, 4, HEX0_3); + 14ac: e13ffd04 addi r4,fp,-12 + 14b0: 01400104 movi r5,4 + 14b4: 000d883a mov r6,zero + 14b8: 00011b80 call 11b8 +} + 14bc: e037883a mov sp,fp + 14c0: dfc00117 ldw ra,4(sp) + 14c4: df000017 ldw fp,0(sp) + 14c8: dec00204 addi sp,sp,8 + 14cc: f800283a ret + +000014d0 : +#include "input_int.h" +#include "sys_register.h" + +unsigned char PUSH_EVENT = PUSH_NONE; + +void in_int() { + 14d0: defffe04 addi sp,sp,-8 + 14d4: dfc00115 stw ra,4(sp) + 14d8: df000015 stw fp,0(sp) + 14dc: d839883a mov fp,sp + push_int(); + 14e0: 000168c0 call 168c +} + 14e4: e037883a mov sp,fp + 14e8: dfc00117 ldw ra,4(sp) + 14ec: df000017 ldw fp,0(sp) + 14f0: dec00204 addi sp,sp,8 + 14f4: f800283a ret + +000014f8 : + +static void update_sw_reg(sw_t s) { + 14f8: defffe04 addi sp,sp,-8 + 14fc: df000115 stw fp,4(sp) + 1500: df000104 addi fp,sp,4 + 1504: e13fff15 stw r4,-4(fp) + global_registers[Ssw_data] = (char)s.data.value; + 1508: e0bfff17 ldw r2,-4(fp) + 150c: 1004d2ba srli r2,r2,10 + 1510: 1007883a mov r3,r2 + 1514: 00bfffc4 movi r2,-1 + 1518: 1884703a and r2,r3,r2 + 151c: 1007883a mov r3,r2 + 1520: 00800074 movhi r2,1 + 1524: 1090cd04 addi r2,r2,17204 + 1528: 10c001c5 stb r3,7(r2) + global_registers[Ssw_inst] = (char)s.splited.instruction_code; + 152c: e0bfff17 ldw r2,-4(fp) + 1530: 1004d3ba srli r2,r2,14 + 1534: 108003cc andi r2,r2,15 + 1538: 1007883a mov r3,r2 + 153c: 00800074 movhi r2,1 + 1540: 1090cd04 addi r2,r2,17204 + 1544: 10c00205 stb r3,8(r2) + global_registers[Ssw_memi] = (char)s.splited.memory_index; + 1548: e0bfff17 ldw r2,-4(fp) + 154c: 1004d1ba srli r2,r2,6 + 1550: 108003cc andi r2,r2,15 + 1554: 1007883a mov r3,r2 + 1558: 00800074 movhi r2,1 + 155c: 1090cd04 addi r2,r2,17204 + 1560: 10c00285 stb r3,10(r2) + global_registers[Ssw_regi] = (char)s.splited.register_index; + 1564: e0bfff17 ldw r2,-4(fp) + 1568: 1004d2ba srli r2,r2,10 + 156c: 108003cc andi r2,r2,15 + 1570: 1007883a mov r3,r2 + 1574: 00800074 movhi r2,1 + 1578: 1090cd04 addi r2,r2,17204 + 157c: 10c00245 stb r3,9(r2) + global_registers[Ssw_psel] = (char)s.splited.program_selecter; + 1580: e0bfff17 ldw r2,-4(fp) + 1584: 1004d0ba srli r2,r2,2 + 1588: 108003cc andi r2,r2,15 + 158c: 1007883a mov r3,r2 + 1590: 00800074 movhi r2,1 + 1594: 1090cd04 addi r2,r2,17204 + 1598: 10c002c5 stb r3,11(r2) + global_registers[Ssw_rw] = (char)s.splited.rw_mode; + 159c: e0bfff17 ldw r2,-4(fp) + 15a0: 1004d07a srli r2,r2,1 + 15a4: 1080004c andi r2,r2,1 + 15a8: 1007883a mov r3,r2 + 15ac: 00800074 movhi r2,1 + 15b0: 1090cd04 addi r2,r2,17204 + 15b4: 10c00305 stb r3,12(r2) + global_registers[Ssw_run] = (char)s.splited.run_mode; + 15b8: e0bfff17 ldw r2,-4(fp) + 15bc: 1080004c andi r2,r2,1 + 15c0: 1007883a mov r3,r2 + 15c4: 00800074 movhi r2,1 + 15c8: 1090cd04 addi r2,r2,17204 + 15cc: 10c00345 stb r3,13(r2) +} + 15d0: e037883a mov sp,fp + 15d4: df000017 ldw fp,0(sp) + 15d8: dec00104 addi sp,sp,4 + 15dc: f800283a ret + +000015e0 : + +enum PushEvent push_decode(char psw) { + 15e0: defffc04 addi sp,sp,-16 + 15e4: df000315 stw fp,12(sp) + 15e8: df000304 addi fp,sp,12 + 15ec: e13ffe05 stb r4,-8(fp) + int result = PUSH_NONE; + 15f0: 00800044 movi r2,1 + 15f4: e0bffd15 stw r2,-12(fp) + switch(psw) { + 15f8: e0bffe07 ldb r2,-8(fp) + 15fc: e0bfff15 stw r2,-4(fp) + 1600: e0ffff17 ldw r3,-4(fp) + 1604: 18800160 cmpeqi r2,r3,5 + 1608: 10000e1e bne r2,zero,1644 + 160c: e0ffff17 ldw r3,-4(fp) + 1610: 188001a0 cmpeqi r2,r3,6 + 1614: 1000121e bne r2,zero,1660 + 1618: e0ffff17 ldw r3,-4(fp) + 161c: 188000e0 cmpeqi r2,r3,3 + 1620: 1000011e bne r2,zero,1628 + 1624: 00001406 br 1678 + case 0x3: + result += PUSH_ANY; + 1628: e0bffd17 ldw r2,-12(fp) + 162c: 10800084 addi r2,r2,2 + 1630: e0bffd15 stw r2,-12(fp) + result += PUSH_VALSTR; + 1634: e0bffd17 ldw r2,-12(fp) + 1638: 10800104 addi r2,r2,4 + 163c: e0bffd15 stw r2,-12(fp) + break; + 1640: 00000d06 br 1678 + case 0x5: + result += PUSH_ANY; + 1644: e0bffd17 ldw r2,-12(fp) + 1648: 10800084 addi r2,r2,2 + 164c: e0bffd15 stw r2,-12(fp) + result += PUSH_INSSTR; + 1650: e0bffd17 ldw r2,-12(fp) + 1654: 10800204 addi r2,r2,8 + 1658: e0bffd15 stw r2,-12(fp) + break; + 165c: 00000606 br 1678 + case 0x6: + result += PUSH_ANY; + 1660: e0bffd17 ldw r2,-12(fp) + 1664: 10800084 addi r2,r2,2 + 1668: e0bffd15 stw r2,-12(fp) + result += PUSH_RUN; + 166c: e0bffd17 ldw r2,-12(fp) + 1670: 10800404 addi r2,r2,16 + 1674: e0bffd15 stw r2,-12(fp) + break; + } + return result; + 1678: e0bffd17 ldw r2,-12(fp) +} + 167c: e037883a mov sp,fp + 1680: df000017 ldw fp,0(sp) + 1684: dec00104 addi sp,sp,4 + 1688: f800283a ret + +0000168c : + +void push_int() { + 168c: defffc04 addi sp,sp,-16 + 1690: dfc00315 stw ra,12(sp) + 1694: df000215 stw fp,8(sp) + 1698: df000204 addi fp,sp,8 + static unsigned char status = 0; + static enum PushEvent event_code; + volatile sw_t s; + s.sw = *switches; + 169c: 00800134 movhi r2,4 + 16a0: 10843404 addi r2,r2,4304 + 16a4: 10800017 ldw r2,0(r2) + 16a8: e0bffe15 stw r2,-8(fp) + + switch (status) { + 16ac: d0a6f803 ldbu r2,-25632(gp) + 16b0: 10803fcc andi r2,r2,255 + 16b4: e0bfff15 stw r2,-4(fp) + 16b8: e0ffff17 ldw r3,-4(fp) + 16bc: 18800060 cmpeqi r2,r3,1 + 16c0: 10001e1e bne r2,zero,173c + 16c4: e0ffff17 ldw r3,-4(fp) + 16c8: 188000a0 cmpeqi r2,r3,2 + 16cc: 1000261e bne r2,zero,1768 + 16d0: e0ffff17 ldw r3,-4(fp) + 16d4: 1805003a cmpeq r2,r3,zero + 16d8: 1000011e bne r2,zero,16e0 + 16dc: 00002606 br 1778 + case 0: + PUSH_EVENT = PUSH_NONE; + 16e0: 00800044 movi r2,1 + 16e4: d0a00005 stb r2,-32768(gp) + if (*push_switches != 7) { + 16e8: 00800134 movhi r2,4 + 16ec: 10843004 addi r2,r2,4288 + 16f0: 10800003 ldbu r2,0(r2) + 16f4: 10803fcc andi r2,r2,255 + 16f8: 1080201c xori r2,r2,128 + 16fc: 10bfe004 addi r2,r2,-128 + 1700: 108001e0 cmpeqi r2,r2,7 + 1704: 10000a1e bne r2,zero,1730 + event_code = push_decode(*push_switches); + 1708: 00800134 movhi r2,4 + 170c: 10843004 addi r2,r2,4288 + 1710: 10800003 ldbu r2,0(r2) + 1714: 11003fcc andi r4,r2,255 + 1718: 2100201c xori r4,r4,128 + 171c: 213fe004 addi r4,r4,-128 + 1720: 00015e00 call 15e0 + 1724: d0a6f715 stw r2,-25636(gp) + status = 1; + 1728: 00800044 movi r2,1 + 172c: d0a6f805 stb r2,-25632(gp) + } + update_sw_reg(s); // �X�C�b�`���W�X�^�X�V + 1730: e13ffe17 ldw r4,-8(fp) + 1734: 00014f80 call 14f8 + break; + 1738: 00001006 br 177c + case 1: + if (*push_switches == 7) status = 2; + 173c: 00800134 movhi r2,4 + 1740: 10843004 addi r2,r2,4288 + 1744: 10800003 ldbu r2,0(r2) + 1748: 10803fcc andi r2,r2,255 + 174c: 1080201c xori r2,r2,128 + 1750: 10bfe004 addi r2,r2,-128 + 1754: 108001d8 cmpnei r2,r2,7 + 1758: 1000081e bne r2,zero,177c + 175c: 00800084 movi r2,2 + 1760: d0a6f805 stb r2,-25632(gp) + break; + 1764: 00000506 br 177c + case 2: + PUSH_EVENT = event_code; + 1768: d0a6f717 ldw r2,-25636(gp) + 176c: d0a00005 stb r2,-32768(gp) + status = 0; + 1770: d026f805 stb zero,-25632(gp) + break; + 1774: 00000106 br 177c + default: + status = 0; + 1778: d026f805 stb zero,-25632(gp) + break; + } +} + 177c: e037883a mov sp,fp + 1780: dfc00117 ldw ra,4(sp) + 1784: df000017 ldw fp,0(sp) + 1788: dec00204 addi sp,sp,8 + 178c: f800283a ret + +00001790 : +#include "hex_out.h" +#include "sys_prog.h" +#include +#include + +struct InstRec inst_fetch(){ + 1790: defffd04 addi sp,sp,-12 + 1794: dfc00215 stw ra,8(sp) + 1798: df000115 stw fp,4(sp) + 179c: df000104 addi fp,sp,4 + struct InstRec rec = inst_memory_load((unsigned int)global_registers[Spc]); + 17a0: 00800074 movhi r2,1 + 17a4: 1090cd04 addi r2,r2,17204 + 17a8: 10800043 ldbu r2,1(r2) + 17ac: 11003fcc andi r4,r2,255 + 17b0: 2100201c xori r4,r4,128 + 17b4: 213fe004 addi r4,r4,-128 + 17b8: 00026480 call 2648 + 17bc: e0bfff15 stw r2,-4(fp) + inc_pc(); + 17c0: 00027bc0 call 27bc + return rec; + 17c4: e0bfff17 ldw r2,-4(fp) +} + 17c8: e037883a mov sp,fp + 17cc: dfc00117 ldw ra,4(sp) + 17d0: df000017 ldw fp,0(sp) + 17d4: dec00204 addi sp,sp,8 + 17d8: f800283a ret + +000017dc : + +void inst_decode(struct InstRec inst_rec){ + 17dc: defffc04 addi sp,sp,-16 + 17e0: dfc00315 stw ra,12(sp) + 17e4: df000215 stw fp,8(sp) + 17e8: df000204 addi fp,sp,8 + 17ec: e13ffe15 stw r4,-8(fp) + switch(inst_rec.inst) { + 17f0: e0bffe17 ldw r2,-8(fp) + 17f4: 108003cc andi r2,r2,15 + 17f8: 10803fcc andi r2,r2,255 + 17fc: e0bfff15 stw r2,-4(fp) + 1800: e0ffff17 ldw r3,-4(fp) + 1804: 18800368 cmpgeui r2,r3,13 + 1808: 10008d1e bne r2,zero,1a40 + 180c: e13fff17 ldw r4,-4(fp) + 1810: e13fff17 ldw r4,-4(fp) + 1814: 2105883a add r2,r4,r4 + 1818: 1087883a add r3,r2,r2 + 181c: 00800034 movhi r2,0 + 1820: 10860c04 addi r2,r2,6192 + 1824: 1885883a add r2,r3,r2 + 1828: 10800017 ldw r2,0(r2) + 182c: 1000683a jmp r2 + 1830: 00001a40 call 1a4 + 1834: 00001864 muli zero,zero,97 + 1838: 0000188c andi zero,zero,98 + 183c: 000018b4 movhi zero,98 + 1840: 000018dc xori zero,zero,99 + 1844: 00001904 movi zero,100 + 1848: 0000192c andhi zero,zero,100 + 184c: 0000197c xorhi zero,zero,101 + 1850: 000019a4 muli zero,zero,102 + 1854: 000019cc andi zero,zero,103 + 1858: 000019f4 movhi zero,103 + 185c: 00001a1c xori zero,zero,104 + 1860: 00001954 movui zero,101 + case INST_END: + break; + case INST_JUMP: + inst_jump(inst_rec.regi, inst_rec.memi); + 1864: e0bffe17 ldw r2,-8(fp) + 1868: 1004d23a srli r2,r2,8 + 186c: 108003cc andi r2,r2,15 + 1870: 11003fcc andi r4,r2,255 + 1874: e0bffe17 ldw r2,-8(fp) + 1878: 1004d13a srli r2,r2,4 + 187c: 108003cc andi r2,r2,15 + 1880: 11403fcc andi r5,r2,255 + 1884: 0001a540 call 1a54 + break; + 1888: 00006d06 br 1a40 + case INST_OUTPUT: + inst_output(inst_rec.regi, inst_rec.memi); + 188c: e0bffe17 ldw r2,-8(fp) + 1890: 1004d23a srli r2,r2,8 + 1894: 108003cc andi r2,r2,15 + 1898: 11003fcc andi r4,r2,255 + 189c: e0bffe17 ldw r2,-8(fp) + 18a0: 1004d13a srli r2,r2,4 + 18a4: 108003cc andi r2,r2,15 + 18a8: 11403fcc andi r5,r2,255 + 18ac: 0001ab00 call 1ab0 + break; + 18b0: 00006306 br 1a40 + case INST_LOAD: + inst_load(inst_rec.regi, inst_rec.memi); + 18b4: e0bffe17 ldw r2,-8(fp) + 18b8: 1004d23a srli r2,r2,8 + 18bc: 108003cc andi r2,r2,15 + 18c0: 11003fcc andi r4,r2,255 + 18c4: e0bffe17 ldw r2,-8(fp) + 18c8: 1004d13a srli r2,r2,4 + 18cc: 108003cc andi r2,r2,15 + 18d0: 11403fcc andi r5,r2,255 + 18d4: 0001b200 call 1b20 + break; + 18d8: 00005906 br 1a40 + case INST_STORE: + inst_store(inst_rec.regi, inst_rec.memi); + 18dc: e0bffe17 ldw r2,-8(fp) + 18e0: 1004d23a srli r2,r2,8 + 18e4: 108003cc andi r2,r2,15 + 18e8: 11003fcc andi r4,r2,255 + 18ec: e0bffe17 ldw r2,-8(fp) + 18f0: 1004d13a srli r2,r2,4 + 18f4: 108003cc andi r2,r2,15 + 18f8: 11403fcc andi r5,r2,255 + 18fc: 0001b580 call 1b58 + break; + 1900: 00004f06 br 1a40 + case INST_DELAY: + inst_delay(inst_rec.regi, inst_rec.memi); + 1904: e0bffe17 ldw r2,-8(fp) + 1908: 1004d23a srli r2,r2,8 + 190c: 108003cc andi r2,r2,15 + 1910: 11003fcc andi r4,r2,255 + 1914: e0bffe17 ldw r2,-8(fp) + 1918: 1004d13a srli r2,r2,4 + 191c: 108003cc andi r2,r2,15 + 1920: 11403fcc andi r5,r2,255 + 1924: 0001b900 call 1b90 + break; + 1928: 00004506 br 1a40 + case INST_ADD: + inst_add(inst_rec.regi, inst_rec.memi); + 192c: e0bffe17 ldw r2,-8(fp) + 1930: 1004d23a srli r2,r2,8 + 1934: 108003cc andi r2,r2,15 + 1938: 11003fcc andi r4,r2,255 + 193c: e0bffe17 ldw r2,-8(fp) + 1940: 1004d13a srli r2,r2,4 + 1944: 108003cc andi r2,r2,15 + 1948: 11403fcc andi r5,r2,255 + 194c: 0001bec0 call 1bec + break; + 1950: 00003b06 br 1a40 + case INST_SUB: + inst_sub(inst_rec.regi, inst_rec.memi); + 1954: e0bffe17 ldw r2,-8(fp) + 1958: 1004d23a srli r2,r2,8 + 195c: 108003cc andi r2,r2,15 + 1960: 11003fcc andi r4,r2,255 + 1964: e0bffe17 ldw r2,-8(fp) + 1968: 1004d13a srli r2,r2,4 + 196c: 108003cc andi r2,r2,15 + 1970: 11403fcc andi r5,r2,255 + 1974: 0001c480 call 1c48 + break; + 1978: 00003106 br 1a40 + case INST_COMP: + inst_comp(inst_rec.regi, inst_rec.memi); + 197c: e0bffe17 ldw r2,-8(fp) + 1980: 1004d23a srli r2,r2,8 + 1984: 108003cc andi r2,r2,15 + 1988: 11003fcc andi r4,r2,255 + 198c: e0bffe17 ldw r2,-8(fp) + 1990: 1004d13a srli r2,r2,4 + 1994: 108003cc andi r2,r2,15 + 1998: 11403fcc andi r5,r2,255 + 199c: 0001ca40 call 1ca4 + break; + 19a0: 00002706 br 1a40 + case INST_JEQ: + inst_jeq(inst_rec.regi, inst_rec.memi); + 19a4: e0bffe17 ldw r2,-8(fp) + 19a8: 1004d23a srli r2,r2,8 + 19ac: 108003cc andi r2,r2,15 + 19b0: 11003fcc andi r4,r2,255 + 19b4: e0bffe17 ldw r2,-8(fp) + 19b8: 1004d13a srli r2,r2,4 + 19bc: 108003cc andi r2,r2,15 + 19c0: 11403fcc andi r5,r2,255 + 19c4: 0001d740 call 1d74 + break; + 19c8: 00001d06 br 1a40 + case INST_JNE: + inst_jne(inst_rec.regi, inst_rec.memi); + 19cc: e0bffe17 ldw r2,-8(fp) + 19d0: 1004d23a srli r2,r2,8 + 19d4: 108003cc andi r2,r2,15 + 19d8: 11003fcc andi r4,r2,255 + 19dc: e0bffe17 ldw r2,-8(fp) + 19e0: 1004d13a srli r2,r2,4 + 19e4: 108003cc andi r2,r2,15 + 19e8: 11403fcc andi r5,r2,255 + 19ec: 0001de00 call 1de0 + break; + 19f0: 00001306 br 1a40 + case INST_JIEQ: + inst_jieq(inst_rec.regi, inst_rec.memi); + 19f4: e0bffe17 ldw r2,-8(fp) + 19f8: 1004d23a srli r2,r2,8 + 19fc: 108003cc andi r2,r2,15 + 1a00: 11003fcc andi r4,r2,255 + 1a04: e0bffe17 ldw r2,-8(fp) + 1a08: 1004d13a srli r2,r2,4 + 1a0c: 108003cc andi r2,r2,15 + 1a10: 11403fcc andi r5,r2,255 + 1a14: 0001e4c0 call 1e4c + break; + 1a18: 00000906 br 1a40 + case INST_JINE: + inst_jine(inst_rec.regi, inst_rec.memi); + 1a1c: e0bffe17 ldw r2,-8(fp) + 1a20: 1004d23a srli r2,r2,8 + 1a24: 108003cc andi r2,r2,15 + 1a28: 11003fcc andi r4,r2,255 + 1a2c: e0bffe17 ldw r2,-8(fp) + 1a30: 1004d13a srli r2,r2,4 + 1a34: 108003cc andi r2,r2,15 + 1a38: 11403fcc andi r5,r2,255 + 1a3c: 0001e9c0 call 1e9c + break; + } +} + 1a40: e037883a mov sp,fp + 1a44: dfc00117 ldw ra,4(sp) + 1a48: df000017 ldw fp,0(sp) + 1a4c: dec00204 addi sp,sp,8 + 1a50: f800283a ret + +00001a54 : + +void inst_jump(enum Register reg, unsigned char memory_index){ + 1a54: defffc04 addi sp,sp,-16 + 1a58: dfc00315 stw ra,12(sp) + 1a5c: df000215 stw fp,8(sp) + 1a60: df000204 addi fp,sp,8 + 1a64: e13ffe15 stw r4,-8(fp) + 1a68: e17fff05 stb r5,-4(fp) + set_pc(global_registers[reg]+memory_index); + 1a6c: e0fffe17 ldw r3,-8(fp) + 1a70: 00800074 movhi r2,1 + 1a74: 1090cd04 addi r2,r2,17204 + 1a78: 10c5883a add r2,r2,r3 + 1a7c: 10800003 ldbu r2,0(r2) + 1a80: 10c03fcc andi r3,r2,255 + 1a84: 18c0201c xori r3,r3,128 + 1a88: 18ffe004 addi r3,r3,-128 + 1a8c: e0bfff03 ldbu r2,-4(fp) + 1a90: 1885883a add r2,r3,r2 + 1a94: 1009883a mov r4,r2 + 1a98: 00028900 call 2890 +} + 1a9c: e037883a mov sp,fp + 1aa0: dfc00117 ldw ra,4(sp) + 1aa4: df000017 ldw fp,0(sp) + 1aa8: dec00204 addi sp,sp,8 + 1aac: f800283a ret + +00001ab0 : +void inst_output(enum Register reg, unsigned char memory_index){ + 1ab0: defffa04 addi sp,sp,-24 + 1ab4: dfc00515 stw ra,20(sp) + 1ab8: df000415 stw fp,16(sp) + 1abc: df000404 addi fp,sp,16 + 1ac0: e13ffe15 stw r4,-8(fp) + 1ac4: e17fff05 stb r5,-4(fp) + //�������̒l��7�Z�O�ɕ\�� + char buf[5]; + memory_load(memory_index, Sseg); + 1ac8: e13fff03 ldbu r4,-4(fp) + 1acc: 01400384 movi r5,14 + 1ad0: 000272c0 call 272c + sprintf(buf, "%04d", global_registers[Sseg]); + 1ad4: 00800074 movhi r2,1 + 1ad8: 1090cd04 addi r2,r2,17204 + 1adc: 10800383 ldbu r2,14(r2) + 1ae0: 11803fcc andi r6,r2,255 + 1ae4: 3180201c xori r6,r6,128 + 1ae8: 31bfe004 addi r6,r6,-128 + 1aec: e13ffc04 addi r4,fp,-16 + 1af0: 01400074 movhi r5,1 + 1af4: 29401c04 addi r5,r5,112 + 1af8: 0002c5c0 call 2c5c + print_block(buf, 4, HEX0_3); + 1afc: e13ffc04 addi r4,fp,-16 + 1b00: 01400104 movi r5,4 + 1b04: 000d883a mov r6,zero + 1b08: 00011b80 call 11b8 +} + 1b0c: e037883a mov sp,fp + 1b10: dfc00117 ldw ra,4(sp) + 1b14: df000017 ldw fp,0(sp) + 1b18: dec00204 addi sp,sp,8 + 1b1c: f800283a ret + +00001b20 : +void inst_load(enum Register reg, unsigned char memory_index){ + 1b20: defffc04 addi sp,sp,-16 + 1b24: dfc00315 stw ra,12(sp) + 1b28: df000215 stw fp,8(sp) + 1b2c: df000204 addi fp,sp,8 + 1b30: e13ffe15 stw r4,-8(fp) + 1b34: e17fff05 stb r5,-4(fp) + memory_load(memory_index, reg); + 1b38: e13fff03 ldbu r4,-4(fp) + 1b3c: e17ffe17 ldw r5,-8(fp) + 1b40: 000272c0 call 272c +} + 1b44: e037883a mov sp,fp + 1b48: dfc00117 ldw ra,4(sp) + 1b4c: df000017 ldw fp,0(sp) + 1b50: dec00204 addi sp,sp,8 + 1b54: f800283a ret + +00001b58 : +void inst_store(enum Register reg, unsigned char memory_index){ + 1b58: defffc04 addi sp,sp,-16 + 1b5c: dfc00315 stw ra,12(sp) + 1b60: df000215 stw fp,8(sp) + 1b64: df000204 addi fp,sp,8 + 1b68: e13ffe15 stw r4,-8(fp) + 1b6c: e17fff05 stb r5,-4(fp) + memory_store(memory_index, reg); + 1b70: e13fff03 ldbu r4,-4(fp) + 1b74: e17ffe17 ldw r5,-8(fp) + 1b78: 00026900 call 2690 +} + 1b7c: e037883a mov sp,fp + 1b80: dfc00117 ldw ra,4(sp) + 1b84: df000017 ldw fp,0(sp) + 1b88: dec00204 addi sp,sp,8 + 1b8c: f800283a ret + +00001b90 : +void inst_delay(enum Register reg, unsigned char memory_index){ + 1b90: defffc04 addi sp,sp,-16 + 1b94: dfc00315 stw ra,12(sp) + 1b98: df000215 stw fp,8(sp) + 1b9c: df000204 addi fp,sp,8 + 1ba0: e13ffe15 stw r4,-8(fp) + 1ba4: e17fff05 stb r5,-4(fp) + //���W�X�^�̒l*10ms�҂� + usleep((int)global_registers[reg]*10000); + 1ba8: e0fffe17 ldw r3,-8(fp) + 1bac: 00800074 movhi r2,1 + 1bb0: 1090cd04 addi r2,r2,17204 + 1bb4: 10c5883a add r2,r2,r3 + 1bb8: 10800003 ldbu r2,0(r2) + 1bbc: 11003fcc andi r4,r2,255 + 1bc0: 2100201c xori r4,r4,128 + 1bc4: 213fe004 addi r4,r4,-128 + 1bc8: 0149c404 movi r5,10000 + 1bcc: 0002c240 call 2c24 <__mulsi3> + 1bd0: 1009883a mov r4,r2 + 1bd4: 000ce780 call ce78 +} + 1bd8: e037883a mov sp,fp + 1bdc: dfc00117 ldw ra,4(sp) + 1be0: df000017 ldw fp,0(sp) + 1be4: dec00204 addi sp,sp,8 + 1be8: f800283a ret + +00001bec : +void inst_add(enum Register reg, unsigned char memory_index){ + 1bec: defffd04 addi sp,sp,-12 + 1bf0: df000215 stw fp,8(sp) + 1bf4: df000204 addi fp,sp,8 + 1bf8: e13ffe15 stw r4,-8(fp) + 1bfc: e17fff05 stb r5,-4(fp) + global_registers[Sacc]+=global_registers[reg]; + 1c00: 00800074 movhi r2,1 + 1c04: 1090cd04 addi r2,r2,17204 + 1c08: 10800143 ldbu r2,5(r2) + 1c0c: 1009883a mov r4,r2 + 1c10: e0fffe17 ldw r3,-8(fp) + 1c14: 00800074 movhi r2,1 + 1c18: 1090cd04 addi r2,r2,17204 + 1c1c: 10c5883a add r2,r2,r3 + 1c20: 10800003 ldbu r2,0(r2) + 1c24: 2085883a add r2,r4,r2 + 1c28: 1007883a mov r3,r2 + 1c2c: 00800074 movhi r2,1 + 1c30: 1090cd04 addi r2,r2,17204 + 1c34: 10c00145 stb r3,5(r2) +} + 1c38: e037883a mov sp,fp + 1c3c: df000017 ldw fp,0(sp) + 1c40: dec00104 addi sp,sp,4 + 1c44: f800283a ret + +00001c48 : +void inst_sub(enum Register reg, unsigned char memory_index){ + 1c48: defffd04 addi sp,sp,-12 + 1c4c: df000215 stw fp,8(sp) + 1c50: df000204 addi fp,sp,8 + 1c54: e13ffe15 stw r4,-8(fp) + 1c58: e17fff05 stb r5,-4(fp) + global_registers[Sacc]-=global_registers[reg]; + 1c5c: 00800074 movhi r2,1 + 1c60: 1090cd04 addi r2,r2,17204 + 1c64: 10800143 ldbu r2,5(r2) + 1c68: 1009883a mov r4,r2 + 1c6c: e0fffe17 ldw r3,-8(fp) + 1c70: 00800074 movhi r2,1 + 1c74: 1090cd04 addi r2,r2,17204 + 1c78: 10c5883a add r2,r2,r3 + 1c7c: 10800003 ldbu r2,0(r2) + 1c80: 2085c83a sub r2,r4,r2 + 1c84: 1007883a mov r3,r2 + 1c88: 00800074 movhi r2,1 + 1c8c: 1090cd04 addi r2,r2,17204 + 1c90: 10c00145 stb r3,5(r2) +} + 1c94: e037883a mov sp,fp + 1c98: df000017 ldw fp,0(sp) + 1c9c: dec00104 addi sp,sp,4 + 1ca0: f800283a ret + +00001ca4 : +void inst_comp(enum Register reg, unsigned char memory_index){ + 1ca4: defffd04 addi sp,sp,-12 + 1ca8: df000215 stw fp,8(sp) + 1cac: df000204 addi fp,sp,8 + 1cb0: e13ffe15 stw r4,-8(fp) + 1cb4: e17fff05 stb r5,-4(fp) + if(global_registers[Sacc]==global_registers[reg]){ + 1cb8: 00800074 movhi r2,1 + 1cbc: 1090cd04 addi r2,r2,17204 + 1cc0: 11000143 ldbu r4,5(r2) + 1cc4: e0fffe17 ldw r3,-8(fp) + 1cc8: 00800074 movhi r2,1 + 1ccc: 1090cd04 addi r2,r2,17204 + 1cd0: 10c5883a add r2,r2,r3 + 1cd4: 10800003 ldbu r2,0(r2) + 1cd8: 20c03fcc andi r3,r4,255 + 1cdc: 18c0201c xori r3,r3,128 + 1ce0: 18ffe004 addi r3,r3,-128 + 1ce4: 10803fcc andi r2,r2,255 + 1ce8: 1080201c xori r2,r2,128 + 1cec: 10bfe004 addi r2,r2,-128 + 1cf0: 1880041e bne r3,r2,1d04 + global_registers[Sflg]=0; + 1cf4: 00800074 movhi r2,1 + 1cf8: 1090cd04 addi r2,r2,17204 + 1cfc: 10000185 stb zero,6(r2) + 1d00: 00001806 br 1d64 + } else if(global_registers[Sacc] > global_registers[reg]){ + 1d04: 00800074 movhi r2,1 + 1d08: 1090cd04 addi r2,r2,17204 + 1d0c: 11000143 ldbu r4,5(r2) + 1d10: e0fffe17 ldw r3,-8(fp) + 1d14: 00800074 movhi r2,1 + 1d18: 1090cd04 addi r2,r2,17204 + 1d1c: 10c5883a add r2,r2,r3 + 1d20: 10800003 ldbu r2,0(r2) + 1d24: 20c03fcc andi r3,r4,255 + 1d28: 18c0201c xori r3,r3,128 + 1d2c: 18ffe004 addi r3,r3,-128 + 1d30: 10803fcc andi r2,r2,255 + 1d34: 1080201c xori r2,r2,128 + 1d38: 10bfe004 addi r2,r2,-128 + 1d3c: 10c0050e bge r2,r3,1d54 + global_registers[Sflg]=-1; + 1d40: 00c00074 movhi r3,1 + 1d44: 18d0cd04 addi r3,r3,17204 + 1d48: 00bfffc4 movi r2,-1 + 1d4c: 18800185 stb r2,6(r3) + 1d50: 00000406 br 1d64 + }else{ + global_registers[Sflg]=1; + 1d54: 00c00074 movhi r3,1 + 1d58: 18d0cd04 addi r3,r3,17204 + 1d5c: 00800044 movi r2,1 + 1d60: 18800185 stb r2,6(r3) + } +} + 1d64: e037883a mov sp,fp + 1d68: df000017 ldw fp,0(sp) + 1d6c: dec00104 addi sp,sp,4 + 1d70: f800283a ret + +00001d74 : +void inst_jeq(enum Register reg, unsigned char memory_index){ + 1d74: defffc04 addi sp,sp,-16 + 1d78: dfc00315 stw ra,12(sp) + 1d7c: df000215 stw fp,8(sp) + 1d80: df000204 addi fp,sp,8 + 1d84: e13ffe15 stw r4,-8(fp) + 1d88: e17fff05 stb r5,-4(fp) + if(global_registers[Sflg]==global_registers[reg]){ + 1d8c: 00800074 movhi r2,1 + 1d90: 1090cd04 addi r2,r2,17204 + 1d94: 11000183 ldbu r4,6(r2) + 1d98: e0fffe17 ldw r3,-8(fp) + 1d9c: 00800074 movhi r2,1 + 1da0: 1090cd04 addi r2,r2,17204 + 1da4: 10c5883a add r2,r2,r3 + 1da8: 10800003 ldbu r2,0(r2) + 1dac: 20c03fcc andi r3,r4,255 + 1db0: 18c0201c xori r3,r3,128 + 1db4: 18ffe004 addi r3,r3,-128 + 1db8: 10803fcc andi r2,r2,255 + 1dbc: 1080201c xori r2,r2,128 + 1dc0: 10bfe004 addi r2,r2,-128 + 1dc4: 1880011e bne r3,r2,1dcc + inc_pc(); + 1dc8: 00027bc0 call 27bc + } +} + 1dcc: e037883a mov sp,fp + 1dd0: dfc00117 ldw ra,4(sp) + 1dd4: df000017 ldw fp,0(sp) + 1dd8: dec00204 addi sp,sp,8 + 1ddc: f800283a ret + +00001de0 : +void inst_jne(enum Register reg, unsigned char memory_index){ + 1de0: defffc04 addi sp,sp,-16 + 1de4: dfc00315 stw ra,12(sp) + 1de8: df000215 stw fp,8(sp) + 1dec: df000204 addi fp,sp,8 + 1df0: e13ffe15 stw r4,-8(fp) + 1df4: e17fff05 stb r5,-4(fp) + if(global_registers[Sflg]!=global_registers[reg]){ + 1df8: 00800074 movhi r2,1 + 1dfc: 1090cd04 addi r2,r2,17204 + 1e00: 11000183 ldbu r4,6(r2) + 1e04: e0fffe17 ldw r3,-8(fp) + 1e08: 00800074 movhi r2,1 + 1e0c: 1090cd04 addi r2,r2,17204 + 1e10: 10c5883a add r2,r2,r3 + 1e14: 10800003 ldbu r2,0(r2) + 1e18: 20c03fcc andi r3,r4,255 + 1e1c: 18c0201c xori r3,r3,128 + 1e20: 18ffe004 addi r3,r3,-128 + 1e24: 10803fcc andi r2,r2,255 + 1e28: 1080201c xori r2,r2,128 + 1e2c: 10bfe004 addi r2,r2,-128 + 1e30: 18800126 beq r3,r2,1e38 + inc_pc(); + 1e34: 00027bc0 call 27bc + } +} + 1e38: e037883a mov sp,fp + 1e3c: dfc00117 ldw ra,4(sp) + 1e40: df000017 ldw fp,0(sp) + 1e44: dec00204 addi sp,sp,8 + 1e48: f800283a ret + +00001e4c : +void inst_jieq(char im, unsigned char memory_index){ + 1e4c: defffc04 addi sp,sp,-16 + 1e50: dfc00315 stw ra,12(sp) + 1e54: df000215 stw fp,8(sp) + 1e58: df000204 addi fp,sp,8 + 1e5c: e13ffe05 stb r4,-8(fp) + 1e60: e17fff05 stb r5,-4(fp) + if(global_registers[Sflg]==im){ + 1e64: 00800074 movhi r2,1 + 1e68: 1090cd04 addi r2,r2,17204 + 1e6c: 10800183 ldbu r2,6(r2) + 1e70: 10c03fcc andi r3,r2,255 + 1e74: 18c0201c xori r3,r3,128 + 1e78: 18ffe004 addi r3,r3,-128 + 1e7c: e0bffe07 ldb r2,-8(fp) + 1e80: 1880011e bne r3,r2,1e88 + inc_pc(); + 1e84: 00027bc0 call 27bc + } +} + 1e88: e037883a mov sp,fp + 1e8c: dfc00117 ldw ra,4(sp) + 1e90: df000017 ldw fp,0(sp) + 1e94: dec00204 addi sp,sp,8 + 1e98: f800283a ret + +00001e9c : +void inst_jine(char im, unsigned char memory_index){ + 1e9c: defffc04 addi sp,sp,-16 + 1ea0: dfc00315 stw ra,12(sp) + 1ea4: df000215 stw fp,8(sp) + 1ea8: df000204 addi fp,sp,8 + 1eac: e13ffe05 stb r4,-8(fp) + 1eb0: e17fff05 stb r5,-4(fp) + if(global_registers[Sflg]!=im){ + 1eb4: 00800074 movhi r2,1 + 1eb8: 1090cd04 addi r2,r2,17204 + 1ebc: 10800183 ldbu r2,6(r2) + 1ec0: 10c03fcc andi r3,r2,255 + 1ec4: 18c0201c xori r3,r3,128 + 1ec8: 18ffe004 addi r3,r3,-128 + 1ecc: e0bffe07 ldb r2,-8(fp) + 1ed0: 18800126 beq r3,r2,1ed8 + inc_pc(); + 1ed4: 00027bc0 call 27bc + } +} + 1ed8: e037883a mov sp,fp + 1edc: dfc00117 ldw ra,4(sp) + 1ee0: df000017 ldw fp,0(sp) + 1ee4: dec00204 addi sp,sp,8 + 1ee8: f800283a ret + +00001eec : +#include +#include "system.h" +#include "LCD.h" + +// LCD�̏����� +void lcd_init() { + 1eec: defffe04 addi sp,sp,-8 + 1ef0: dfc00115 stw ra,4(sp) + 1ef4: df000015 stw fp,0(sp) + 1ef8: d839883a mov fp,sp + *lcd_on = 1; + 1efc: 00c00134 movhi r3,4 + 1f00: 18c40404 addi r3,r3,4112 + 1f04: 00800044 movi r2,1 + 1f08: 18800005 stb r2,0(r3) + *lcd_blon = 1; + 1f0c: 00c00134 movhi r3,4 + 1f10: 18c40804 addi r3,r3,4128 + 1f14: 00800044 movi r2,1 + 1f18: 18800005 stb r2,0(r3) + LCD_Init(); + 1f1c: 00001f00 call 1f0 +} + 1f20: e037883a mov sp,fp + 1f24: dfc00117 ldw ra,4(sp) + 1f28: df000017 ldw fp,0(sp) + 1f2c: dec00204 addi sp,sp,8 + 1f30: f800283a ret + +00001f34 : + +// LCD�̃L�����b�g���P�s�ڂ̂͂��߂Ɉړ����� +void lcd_caret_reset() { + 1f34: defffe04 addi sp,sp,-8 + 1f38: dfc00115 stw ra,4(sp) + 1f3c: df000015 stw fp,0(sp) + 1f40: d839883a mov fp,sp + LCD_Init(); + 1f44: 00001f00 call 1f0 +} + 1f48: e037883a mov sp,fp + 1f4c: dfc00117 ldw ra,4(sp) + 1f50: df000017 ldw fp,0(sp) + 1f54: dec00204 addi sp,sp,8 + 1f58: f800283a ret + +00001f5c : + +// LCD�̃L�����b�g���Q�s�ڂ̂͂��߂Ɉړ����� +void lcd_caret_reset2() { + 1f5c: defffe04 addi sp,sp,-8 + 1f60: dfc00115 stw ra,4(sp) + 1f64: df000015 stw fp,0(sp) + 1f68: d839883a mov fp,sp + LCD_Line2(); + 1f6c: 00003140 call 314 +} + 1f70: e037883a mov sp,fp + 1f74: dfc00117 ldw ra,4(sp) + 1f78: df000017 ldw fp,0(sp) + 1f7c: dec00204 addi sp,sp,8 + 1f80: f800283a ret + +00001f84 : + +// LCD�ɕ�����\������ +void lcd_print(const char *str) { + 1f84: defffd04 addi sp,sp,-12 + 1f88: dfc00215 stw ra,8(sp) + 1f8c: df000115 stw fp,4(sp) + 1f90: df000104 addi fp,sp,4 + 1f94: e13fff15 stw r4,-4(fp) + LCD_Show_Text(str); + 1f98: e13fff17 ldw r4,-4(fp) + 1f9c: 000028c0 call 28c +} + 1fa0: e037883a mov sp,fp + 1fa4: dfc00117 ldw ra,4(sp) + 1fa8: df000017 ldw fp,0(sp) + 1fac: dec00204 addi sp,sp,8 + 1fb0: f800283a ret + +00001fb4 : +#include "sys_debug.h" +#include +#include "lcd_out.h" +#include + +void display_inst(struct InstRec inst, unsigned int pc) { + 1fb4: defff504 addi sp,sp,-44 + 1fb8: dfc00a15 stw ra,40(sp) + 1fbc: df000915 stw fp,36(sp) + 1fc0: df000904 addi fp,sp,36 + 1fc4: e13ffe15 stw r4,-8(fp) + 1fc8: e17fff15 stw r5,-4(fp) + char inst_name[INST_NAME_ARRAY_LEN]; // ���ߖ� + char reg_name[REG_NAME_ARRAY_LEN]; // ���W�X�^�� + char buf[17]; + + // ���߂̖��O�̎擾 + convertInstName(inst_name, inst.inst); + 1fcc: e0bffe17 ldw r2,-8(fp) + 1fd0: 108003cc andi r2,r2,15 + 1fd4: 11403fcc andi r5,r2,255 + 1fd8: e13ff704 addi r4,fp,-36 + 1fdc: 000223c0 call 223c + // ���W�X�^�̖��O�̎擾 + convertRegName(reg_name, inst.regi); + 1fe0: e0bffe17 ldw r2,-8(fp) + 1fe4: 1004d23a srli r2,r2,8 + 1fe8: 108003cc andi r2,r2,15 + 1fec: 11403fcc andi r5,r2,255 + 1ff0: e13ff844 addi r4,fp,-31 + 1ff4: 00020cc0 call 20cc + + lcd_caret_reset(); + 1ff8: 0001f340 call 1f34 + sprintf(buf, "PC:0x%02x -> %4s",pc,inst_name); + 1ffc: e13ff944 addi r4,fp,-27 + 2000: 01400074 movhi r5,1 + 2004: 29401e04 addi r5,r5,120 + 2008: e1bfff17 ldw r6,-4(fp) + 200c: e1fff704 addi r7,fp,-36 + 2010: 0002c5c0 call 2c5c + lcd_print(buf); + 2014: e13ff944 addi r4,fp,-27 + 2018: 0001f840 call 1f84 + lcd_caret_reset2(); + 201c: 0001f5c0 call 1f5c + sprintf(buf, "REG:%3s,MEM:0x%1x",reg_name,inst.memi); + 2020: e0bffe17 ldw r2,-8(fp) + 2024: 1004d13a srli r2,r2,4 + 2028: 108003cc andi r2,r2,15 + 202c: 11c03fcc andi r7,r2,255 + 2030: e13ff944 addi r4,fp,-27 + 2034: e1bff844 addi r6,fp,-31 + 2038: 01400074 movhi r5,1 + 203c: 29402304 addi r5,r5,140 + 2040: 0002c5c0 call 2c5c + lcd_print(buf); + 2044: e13ff944 addi r4,fp,-27 + 2048: 0001f840 call 1f84 +} + 204c: e037883a mov sp,fp + 2050: dfc00117 ldw ra,4(sp) + 2054: df000017 ldw fp,0(sp) + 2058: dec00204 addi sp,sp,8 + 205c: f800283a ret + +00002060 : + +void display_mem(unsigned char memi, char memv) { + 2060: defff704 addi sp,sp,-36 + 2064: dfc00815 stw ra,32(sp) + 2068: df000715 stw fp,28(sp) + 206c: df000704 addi fp,sp,28 + 2070: e13ffe05 stb r4,-8(fp) + 2074: e17fff05 stb r5,-4(fp) + char buf[17]; + + lcd_caret_reset(); + 2078: 0001f340 call 1f34 + sprintf(buf, "MEM:0x%1x",memi); + 207c: e1bffe03 ldbu r6,-8(fp) + 2080: e13ff904 addi r4,fp,-28 + 2084: 01400074 movhi r5,1 + 2088: 29402804 addi r5,r5,160 + 208c: 0002c5c0 call 2c5c + lcd_print(buf); + 2090: e13ff904 addi r4,fp,-28 + 2094: 0001f840 call 1f84 + lcd_caret_reset2(); + 2098: 0001f5c0 call 1f5c + sprintf(buf, "value:%d",memv); + 209c: e1bfff07 ldb r6,-4(fp) + 20a0: e13ff904 addi r4,fp,-28 + 20a4: 01400074 movhi r5,1 + 20a8: 29402b04 addi r5,r5,172 + 20ac: 0002c5c0 call 2c5c + lcd_print(buf); + 20b0: e13ff904 addi r4,fp,-28 + 20b4: 0001f840 call 1f84 +} + 20b8: e037883a mov sp,fp + 20bc: dfc00117 ldw ra,4(sp) + 20c0: df000017 ldw fp,0(sp) + 20c4: dec00204 addi sp,sp,8 + 20c8: f800283a ret + +000020cc : + +void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code) { + 20cc: defffd04 addi sp,sp,-12 + 20d0: df000215 stw fp,8(sp) + 20d4: df000204 addi fp,sp,8 + 20d8: e13ffe15 stw r4,-8(fp) + 20dc: e17fff15 stw r5,-4(fp) + switch(reg_code) { + 20e0: e0bfff17 ldw r2,-4(fp) + 20e4: 108001e8 cmpgeui r2,r2,7 + 20e8: 1000481e bne r2,zero,220c + 20ec: e0bfff17 ldw r2,-4(fp) + 20f0: 1085883a add r2,r2,r2 + 20f4: 1087883a add r3,r2,r2 + 20f8: 00800034 movhi r2,0 + 20fc: 10884304 addi r2,r2,8460 + 2100: 1885883a add r2,r3,r2 + 2104: 10800017 ldw r2,0(r2) + 2108: 1000683a jmp r2 + 210c: 00002128 cmpgeui zero,zero,132 + 2110: 00002144 movi zero,133 + 2114: 00002160 cmpeqi zero,zero,133 + 2118: 0000217c xorhi zero,zero,133 + 211c: 000021a0 cmpeqi zero,zero,134 + 2120: 000021c4 movi zero,135 + 2124: 000021e8 cmpgeui zero,zero,135 + case Szero: + sprintf(reg_name, STRING_REG_ZERO); + 2128: e0bffe17 ldw r2,-8(fp) + 212c: 00c01684 movi r3,90 + 2130: 10c00005 stb r3,0(r2) + 2134: 00c01144 movi r3,69 + 2138: 10c00045 stb r3,1(r2) + 213c: 10000085 stb zero,2(r2) + break; + 2140: 00003a06 br 222c + case Spc: + sprintf(reg_name, STRING_REG_PC); + 2144: e0bffe17 ldw r2,-8(fp) + 2148: 00c01404 movi r3,80 + 214c: 10c00005 stb r3,0(r2) + 2150: 00c010c4 movi r3,67 + 2154: 10c00045 stb r3,1(r2) + 2158: 10000085 stb zero,2(r2) + break; + 215c: 00003306 br 222c + case Ssp: + sprintf(reg_name, STRING_REG_SP); + 2160: e0bffe17 ldw r2,-8(fp) + 2164: 00c014c4 movi r3,83 + 2168: 10c00005 stb r3,0(r2) + 216c: 00c01404 movi r3,80 + 2170: 10c00045 stb r3,1(r2) + 2174: 10000085 stb zero,2(r2) + break; + 2178: 00002c06 br 222c + case Sgp0: + sprintf(reg_name, STRING_REG_GP0); + 217c: e0fffe17 ldw r3,-8(fp) + 2180: 008011c4 movi r2,71 + 2184: 18800005 stb r2,0(r3) + 2188: 00801404 movi r2,80 + 218c: 18800045 stb r2,1(r3) + 2190: 00800c04 movi r2,48 + 2194: 18800085 stb r2,2(r3) + 2198: 180000c5 stb zero,3(r3) + break; + 219c: 00002306 br 222c + case Sgp1: + sprintf(reg_name, STRING_REG_GP1); + 21a0: e0fffe17 ldw r3,-8(fp) + 21a4: 008011c4 movi r2,71 + 21a8: 18800005 stb r2,0(r3) + 21ac: 00801404 movi r2,80 + 21b0: 18800045 stb r2,1(r3) + 21b4: 00800c44 movi r2,49 + 21b8: 18800085 stb r2,2(r3) + 21bc: 180000c5 stb zero,3(r3) + break; + 21c0: 00001a06 br 222c + case Sacc: + sprintf(reg_name, STRING_REG_ACC); + 21c4: e0fffe17 ldw r3,-8(fp) + 21c8: 00801044 movi r2,65 + 21cc: 18800005 stb r2,0(r3) + 21d0: 008010c4 movi r2,67 + 21d4: 18800045 stb r2,1(r3) + 21d8: 008010c4 movi r2,67 + 21dc: 18800085 stb r2,2(r3) + 21e0: 180000c5 stb zero,3(r3) + break; + 21e4: 00001106 br 222c + case Sflg: + sprintf(reg_name, STRING_REG_FLG); + 21e8: e0fffe17 ldw r3,-8(fp) + 21ec: 00801184 movi r2,70 + 21f0: 18800005 stb r2,0(r3) + 21f4: 00801304 movi r2,76 + 21f8: 18800045 stb r2,1(r3) + 21fc: 008011c4 movi r2,71 + 2200: 18800085 stb r2,2(r3) + 2204: 180000c5 stb zero,3(r3) + break; + 2208: 00000806 br 222c + default: + sprintf(reg_name, "non"); + 220c: e0fffe17 ldw r3,-8(fp) + 2210: 00801b84 movi r2,110 + 2214: 18800005 stb r2,0(r3) + 2218: 00801bc4 movi r2,111 + 221c: 18800045 stb r2,1(r3) + 2220: 00801b84 movi r2,110 + 2224: 18800085 stb r2,2(r3) + 2228: 180000c5 stb zero,3(r3) + break; + } +} + 222c: e037883a mov sp,fp + 2230: df000017 ldw fp,0(sp) + 2234: dec00104 addi sp,sp,4 + 2238: f800283a ret + +0000223c : + + +void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code) { + 223c: defffc04 addi sp,sp,-16 + 2240: df000315 stw fp,12(sp) + 2244: df000304 addi fp,sp,12 + 2248: e13ffd15 stw r4,-12(fp) + 224c: e17ffe05 stb r5,-8(fp) + switch(inst_code) { + 2250: e0bffe03 ldbu r2,-8(fp) + 2254: e0bfff15 stw r2,-4(fp) + 2258: e0ffff17 ldw r3,-4(fp) + 225c: 18800368 cmpgeui r2,r3,13 + 2260: 1000991e bne r2,zero,24c8 + 2264: e13fff17 ldw r4,-4(fp) + 2268: e13fff17 ldw r4,-4(fp) + 226c: 2105883a add r2,r4,r4 + 2270: 1087883a add r3,r2,r2 + 2274: 00800034 movhi r2,0 + 2278: 1088a204 addi r2,r2,8840 + 227c: 1885883a add r2,r3,r2 + 2280: 10800017 ldw r2,0(r2) + 2284: 1000683a jmp r2 + 2288: 000022bc xorhi zero,zero,138 + 228c: 000022e0 cmpeqi zero,zero,139 + 2290: 0000230c andi zero,zero,140 + 2294: 00002330 cmpltui zero,zero,140 + 2298: 0000235c xori zero,zero,141 + 229c: 00002388 cmpgei zero,zero,142 + 22a0: 000023b4 movhi zero,142 + 22a4: 000023fc xorhi zero,zero,143 + 22a8: 00002428 cmpgeui zero,zero,144 + 22ac: 0000244c andi zero,zero,145 + 22b0: 00002470 cmpltui zero,zero,145 + 22b4: 0000249c xori zero,zero,146 + 22b8: 000023d8 cmpnei zero,zero,143 + case INST_END: + sprintf(inst_name, STRING_INST_END); + 22bc: e0fffd17 ldw r3,-12(fp) + 22c0: 00801144 movi r2,69 + 22c4: 18800005 stb r2,0(r3) + 22c8: 00801384 movi r2,78 + 22cc: 18800045 stb r2,1(r3) + 22d0: 00801104 movi r2,68 + 22d4: 18800085 stb r2,2(r3) + 22d8: 180000c5 stb zero,3(r3) + break; + 22dc: 00008406 br 24f0 + case INST_JUMP: + sprintf(inst_name, STRING_INST_JUMP); + 22e0: e0fffd17 ldw r3,-12(fp) + 22e4: 00801284 movi r2,74 + 22e8: 18800005 stb r2,0(r3) + 22ec: 00801544 movi r2,85 + 22f0: 18800045 stb r2,1(r3) + 22f4: 00801344 movi r2,77 + 22f8: 18800085 stb r2,2(r3) + 22fc: 00801404 movi r2,80 + 2300: 188000c5 stb r2,3(r3) + 2304: 18000105 stb zero,4(r3) + break; + 2308: 00007906 br 24f0 + case INST_OUTPUT: + sprintf(inst_name, STRING_INST_OUTPUT); + 230c: e0fffd17 ldw r3,-12(fp) + 2310: 008013c4 movi r2,79 + 2314: 18800005 stb r2,0(r3) + 2318: 00801544 movi r2,85 + 231c: 18800045 stb r2,1(r3) + 2320: 00801504 movi r2,84 + 2324: 18800085 stb r2,2(r3) + 2328: 180000c5 stb zero,3(r3) + break; + 232c: 00007006 br 24f0 + case INST_LOAD: + sprintf(inst_name, STRING_INST_LOAD); + 2330: e0fffd17 ldw r3,-12(fp) + 2334: 00801304 movi r2,76 + 2338: 18800005 stb r2,0(r3) + 233c: 008013c4 movi r2,79 + 2340: 18800045 stb r2,1(r3) + 2344: 00801044 movi r2,65 + 2348: 18800085 stb r2,2(r3) + 234c: 00801104 movi r2,68 + 2350: 188000c5 stb r2,3(r3) + 2354: 18000105 stb zero,4(r3) + break; + 2358: 00006506 br 24f0 + case INST_STORE: + sprintf(inst_name, STRING_INST_STORE); + 235c: e0fffd17 ldw r3,-12(fp) + 2360: 008014c4 movi r2,83 + 2364: 18800005 stb r2,0(r3) + 2368: 00801504 movi r2,84 + 236c: 18800045 stb r2,1(r3) + 2370: 008013c4 movi r2,79 + 2374: 18800085 stb r2,2(r3) + 2378: 00801484 movi r2,82 + 237c: 188000c5 stb r2,3(r3) + 2380: 18000105 stb zero,4(r3) + break; + 2384: 00005a06 br 24f0 + case INST_DELAY: + sprintf(inst_name, STRING_INST_DELAY); + 2388: e0fffd17 ldw r3,-12(fp) + 238c: 00801104 movi r2,68 + 2390: 18800005 stb r2,0(r3) + 2394: 00801144 movi r2,69 + 2398: 18800045 stb r2,1(r3) + 239c: 00801304 movi r2,76 + 23a0: 18800085 stb r2,2(r3) + 23a4: 00801644 movi r2,89 + 23a8: 188000c5 stb r2,3(r3) + 23ac: 18000105 stb zero,4(r3) + break; + 23b0: 00004f06 br 24f0 + case INST_ADD: + sprintf(inst_name, STRING_INST_ADD); + 23b4: e0fffd17 ldw r3,-12(fp) + 23b8: 00801044 movi r2,65 + 23bc: 18800005 stb r2,0(r3) + 23c0: 00801104 movi r2,68 + 23c4: 18800045 stb r2,1(r3) + 23c8: 00801104 movi r2,68 + 23cc: 18800085 stb r2,2(r3) + 23d0: 180000c5 stb zero,3(r3) + break; + 23d4: 00004606 br 24f0 + case INST_SUB: + sprintf(inst_name, STRING_INST_SUB); + 23d8: e0fffd17 ldw r3,-12(fp) + 23dc: 008014c4 movi r2,83 + 23e0: 18800005 stb r2,0(r3) + 23e4: 00801544 movi r2,85 + 23e8: 18800045 stb r2,1(r3) + 23ec: 00801084 movi r2,66 + 23f0: 18800085 stb r2,2(r3) + 23f4: 180000c5 stb zero,3(r3) + break; + 23f8: 00003d06 br 24f0 + case INST_COMP: + sprintf(inst_name, STRING_INST_COMP); + 23fc: e0fffd17 ldw r3,-12(fp) + 2400: 008010c4 movi r2,67 + 2404: 18800005 stb r2,0(r3) + 2408: 008013c4 movi r2,79 + 240c: 18800045 stb r2,1(r3) + 2410: 00801344 movi r2,77 + 2414: 18800085 stb r2,2(r3) + 2418: 00801404 movi r2,80 + 241c: 188000c5 stb r2,3(r3) + 2420: 18000105 stb zero,4(r3) + break; + 2424: 00003206 br 24f0 + case INST_JEQ: + sprintf(inst_name, STRING_INST_JEQ); + 2428: e0fffd17 ldw r3,-12(fp) + 242c: 00801284 movi r2,74 + 2430: 18800005 stb r2,0(r3) + 2434: 00801144 movi r2,69 + 2438: 18800045 stb r2,1(r3) + 243c: 00801444 movi r2,81 + 2440: 18800085 stb r2,2(r3) + 2444: 180000c5 stb zero,3(r3) + break; + 2448: 00002906 br 24f0 + case INST_JNE: + sprintf(inst_name, STRING_INST_JNE); + 244c: e0fffd17 ldw r3,-12(fp) + 2450: 00801284 movi r2,74 + 2454: 18800005 stb r2,0(r3) + 2458: 00801384 movi r2,78 + 245c: 18800045 stb r2,1(r3) + 2460: 00801144 movi r2,69 + 2464: 18800085 stb r2,2(r3) + 2468: 180000c5 stb zero,3(r3) + break; + 246c: 00002006 br 24f0 + case INST_JIEQ: + sprintf(inst_name, STRING_INST_JIEQ); + 2470: e0fffd17 ldw r3,-12(fp) + 2474: 00801284 movi r2,74 + 2478: 18800005 stb r2,0(r3) + 247c: 00801244 movi r2,73 + 2480: 18800045 stb r2,1(r3) + 2484: 00801144 movi r2,69 + 2488: 18800085 stb r2,2(r3) + 248c: 00801444 movi r2,81 + 2490: 188000c5 stb r2,3(r3) + 2494: 18000105 stb zero,4(r3) + break; + 2498: 00001506 br 24f0 + case INST_JINE: + sprintf(inst_name, STRING_INST_JINE); + 249c: e0fffd17 ldw r3,-12(fp) + 24a0: 00801284 movi r2,74 + 24a4: 18800005 stb r2,0(r3) + 24a8: 00801244 movi r2,73 + 24ac: 18800045 stb r2,1(r3) + 24b0: 00801384 movi r2,78 + 24b4: 18800085 stb r2,2(r3) + 24b8: 00801144 movi r2,69 + 24bc: 188000c5 stb r2,3(r3) + 24c0: 18000105 stb zero,4(r3) + break; + 24c4: 00000a06 br 24f0 + default: + sprintf(inst_name, "NoOp"); + 24c8: e0fffd17 ldw r3,-12(fp) + 24cc: 00801384 movi r2,78 + 24d0: 18800005 stb r2,0(r3) + 24d4: 00801bc4 movi r2,111 + 24d8: 18800045 stb r2,1(r3) + 24dc: 008013c4 movi r2,79 + 24e0: 18800085 stb r2,2(r3) + 24e4: 00801c04 movi r2,112 + 24e8: 188000c5 stb r2,3(r3) + 24ec: 18000105 stb zero,4(r3) + break; + } +} + 24f0: e037883a mov sp,fp + 24f4: df000017 ldw fp,0(sp) + 24f8: dec00104 addi sp,sp,4 + 24fc: f800283a ret + +00002500 : + +void delay10ms(unsigned int s) { + 2500: defffd04 addi sp,sp,-12 + 2504: dfc00215 stw ra,8(sp) + 2508: df000115 stw fp,4(sp) + 250c: df000104 addi fp,sp,4 + 2510: e13fff15 stw r4,-4(fp) + usleep(s*10000); + 2514: e13fff17 ldw r4,-4(fp) + 2518: 0149c404 movi r5,10000 + 251c: 0002c240 call 2c24 <__mulsi3> + 2520: 1009883a mov r4,r2 + 2524: 000ce780 call ce78 +} + 2528: e037883a mov sp,fp + 252c: dfc00117 ldw ra,4(sp) + 2530: df000017 ldw fp,0(sp) + 2534: dec00204 addi sp,sp,8 + 2538: f800283a ret + +0000253c : + * Author: takayun + */ +#include "system.h" +#include "hex_out.h" + +void panic() { + 253c: defffe04 addi sp,sp,-8 + 2540: dfc00115 stw ra,4(sp) + 2544: df000015 stw fp,0(sp) + 2548: d839883a mov fp,sp + clear_block(HEX0_3); + 254c: 0009883a mov r4,zero + 2550: 00013480 call 1348 + print_block("err ", 4, HEX0_3); + 2554: 01000074 movhi r4,1 + 2558: 21002e04 addi r4,r4,184 + 255c: 01400104 movi r5,4 + 2560: 000d883a mov r6,zero + 2564: 00011b80 call 11b8 +} + 2568: e037883a mov sp,fp + 256c: dfc00117 ldw ra,4(sp) + 2570: df000017 ldw fp,0(sp) + 2574: dec00204 addi sp,sp,8 + 2578: f800283a ret + +0000257c : + +/************************************************** + * Impl + **************************************************/ + +void memory_init() { + 257c: defffd04 addi sp,sp,-12 + 2580: df000215 stw fp,8(sp) + 2584: df000204 addi fp,sp,8 + int i, j; + for (i = 0; i < MEMS_COUNT; i++) + 2588: e03fff15 stw zero,-4(fp) + 258c: 00001306 br 25dc + for (j = 0; j < MEM_SIZE; j++) { + 2590: e03ffe15 stw zero,-8(fp) + 2594: 00000b06 br 25c4 + memory[i][j] = 0; + 2598: e0bfff17 ldw r2,-4(fp) + 259c: e13ffe17 ldw r4,-8(fp) + 25a0: 00c00074 movhi r3,1 + 25a4: 18cf8304 addi r3,r3,15884 + 25a8: 1004913a slli r2,r2,4 + 25ac: 10c5883a add r2,r2,r3 + 25b0: 1105883a add r2,r2,r4 + 25b4: 10000005 stb zero,0(r2) + **************************************************/ + +void memory_init() { + int i, j; + for (i = 0; i < MEMS_COUNT; i++) + for (j = 0; j < MEM_SIZE; j++) { + 25b8: e0bffe17 ldw r2,-8(fp) + 25bc: 10800044 addi r2,r2,1 + 25c0: e0bffe15 stw r2,-8(fp) + 25c4: e0bffe17 ldw r2,-8(fp) + 25c8: 10800410 cmplti r2,r2,16 + 25cc: 103ff21e bne r2,zero,2598 + * Impl + **************************************************/ + +void memory_init() { + int i, j; + for (i = 0; i < MEMS_COUNT; i++) + 25d0: e0bfff17 ldw r2,-4(fp) + 25d4: 10800044 addi r2,r2,1 + 25d8: e0bfff15 stw r2,-4(fp) + 25dc: e0bfff17 ldw r2,-4(fp) + 25e0: 10800410 cmplti r2,r2,16 + 25e4: 103fea1e bne r2,zero,2590 + for (j = 0; j < MEM_SIZE; j++) { + memory[i][j] = 0; + } +} + 25e8: e037883a mov sp,fp + 25ec: df000017 ldw fp,0(sp) + 25f0: dec00104 addi sp,sp,4 + 25f4: f800283a ret + +000025f8 : + +void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec){ + 25f8: defffd04 addi sp,sp,-12 + 25fc: df000215 stw fp,8(sp) + 2600: df000204 addi fp,sp,8 + 2604: e13ffe15 stw r4,-8(fp) + 2608: e17fff15 stw r5,-4(fp) + inst_memory[global_current_memory][mem_addr] = inst_rec; + 260c: d0a6f917 ldw r2,-25628(gp) + 2610: e0fffe17 ldw r3,-8(fp) + 2614: 01000074 movhi r4,1 + 2618: 210fc304 addi r4,r4,16140 + 261c: 1004913a slli r2,r2,4 + 2620: 10c5883a add r2,r2,r3 + 2624: 1085883a add r2,r2,r2 + 2628: 1085883a add r2,r2,r2 + 262c: 1107883a add r3,r2,r4 + 2630: e0bfff17 ldw r2,-4(fp) + 2634: 18800015 stw r2,0(r3) +} + 2638: e037883a mov sp,fp + 263c: df000017 ldw fp,0(sp) + 2640: dec00104 addi sp,sp,4 + 2644: f800283a ret + +00002648 : +struct InstRec inst_memory_load(unsigned int mem_addr){ + 2648: defffe04 addi sp,sp,-8 + 264c: df000115 stw fp,4(sp) + 2650: df000104 addi fp,sp,4 + 2654: e13fff15 stw r4,-4(fp) + return inst_memory[global_current_memory][mem_addr]; + 2658: d0a6f917 ldw r2,-25628(gp) + 265c: e0ffff17 ldw r3,-4(fp) + 2660: 01000074 movhi r4,1 + 2664: 210fc304 addi r4,r4,16140 + 2668: 1004913a slli r2,r2,4 + 266c: 10c5883a add r2,r2,r3 + 2670: 1085883a add r2,r2,r2 + 2674: 1085883a add r2,r2,r2 + 2678: 1105883a add r2,r2,r4 + 267c: 10800017 ldw r2,0(r2) +} + 2680: e037883a mov sp,fp + 2684: df000017 ldw fp,0(sp) + 2688: dec00104 addi sp,sp,4 + 268c: f800283a ret + +00002690 : + +char memory_store(unsigned int mem_addr, enum Register reg) { + 2690: defffc04 addi sp,sp,-16 + 2694: dfc00315 stw ra,12(sp) + 2698: df000215 stw fp,8(sp) + 269c: df000204 addi fp,sp,8 + 26a0: e13ffe15 stw r4,-8(fp) + 26a4: e17fff15 stw r5,-4(fp) + if (!(mem_addr < MEM_SIZE)) panic(); + 26a8: e0bffe17 ldw r2,-8(fp) + 26ac: 10800430 cmpltui r2,r2,16 + 26b0: 1000011e bne r2,zero,26b8 + 26b4: 000253c0 call 253c + memory[global_current_memory][mem_addr] = global_registers[reg]; + 26b8: d166f917 ldw r5,-25628(gp) + 26bc: e1bffe17 ldw r6,-8(fp) + 26c0: e0ffff17 ldw r3,-4(fp) + 26c4: 00800074 movhi r2,1 + 26c8: 1090cd04 addi r2,r2,17204 + 26cc: 10c5883a add r2,r2,r3 + 26d0: 11000003 ldbu r4,0(r2) + 26d4: 00c00074 movhi r3,1 + 26d8: 18cf8304 addi r3,r3,15884 + 26dc: 2804913a slli r2,r5,4 + 26e0: 10c5883a add r2,r2,r3 + 26e4: 1185883a add r2,r2,r6 + 26e8: 11000005 stb r4,0(r2) + return memory[global_current_memory][mem_addr]; + 26ec: d0a6f917 ldw r2,-25628(gp) + 26f0: e13ffe17 ldw r4,-8(fp) + 26f4: 00c00074 movhi r3,1 + 26f8: 18cf8304 addi r3,r3,15884 + 26fc: 1004913a slli r2,r2,4 + 2700: 10c5883a add r2,r2,r3 + 2704: 1105883a add r2,r2,r4 + 2708: 10800003 ldbu r2,0(r2) + 270c: 10803fcc andi r2,r2,255 + 2710: 1080201c xori r2,r2,128 + 2714: 10bfe004 addi r2,r2,-128 +} + 2718: e037883a mov sp,fp + 271c: dfc00117 ldw ra,4(sp) + 2720: df000017 ldw fp,0(sp) + 2724: dec00204 addi sp,sp,8 + 2728: f800283a ret + +0000272c : + +char memory_load(unsigned int mem_addr, enum Register reg) { + 272c: defffc04 addi sp,sp,-16 + 2730: dfc00315 stw ra,12(sp) + 2734: df000215 stw fp,8(sp) + 2738: df000204 addi fp,sp,8 + 273c: e13ffe15 stw r4,-8(fp) + 2740: e17fff15 stw r5,-4(fp) + if (!(mem_addr < MEM_SIZE)) panic(); + 2744: e0bffe17 ldw r2,-8(fp) + 2748: 10800430 cmpltui r2,r2,16 + 274c: 1000011e bne r2,zero,2754 + 2750: 000253c0 call 253c + global_registers[reg] = memory[global_current_memory][mem_addr]; + 2754: e17fff17 ldw r5,-4(fp) + 2758: d0a6f917 ldw r2,-25628(gp) + 275c: e13ffe17 ldw r4,-8(fp) + 2760: 00c00074 movhi r3,1 + 2764: 18cf8304 addi r3,r3,15884 + 2768: 1004913a slli r2,r2,4 + 276c: 10c5883a add r2,r2,r3 + 2770: 1105883a add r2,r2,r4 + 2774: 10c00003 ldbu r3,0(r2) + 2778: 00800074 movhi r2,1 + 277c: 1090cd04 addi r2,r2,17204 + 2780: 1145883a add r2,r2,r5 + 2784: 10c00005 stb r3,0(r2) + return global_registers[reg]; + 2788: e0ffff17 ldw r3,-4(fp) + 278c: 00800074 movhi r2,1 + 2790: 1090cd04 addi r2,r2,17204 + 2794: 10c5883a add r2,r2,r3 + 2798: 10800003 ldbu r2,0(r2) + 279c: 10803fcc andi r2,r2,255 + 27a0: 1080201c xori r2,r2,128 + 27a4: 10bfe004 addi r2,r2,-128 +} + 27a8: e037883a mov sp,fp + 27ac: dfc00117 ldw ra,4(sp) + 27b0: df000017 ldw fp,0(sp) + 27b4: dec00204 addi sp,sp,8 + 27b8: f800283a ret + +000027bc : +#include "sys_register.h" +#include "sys_memory.h" +#include "hex_out.h" +#include "lcd_out.h" + +unsigned int inc_pc() { + 27bc: deffff04 addi sp,sp,-4 + 27c0: df000015 stw fp,0(sp) + 27c4: d839883a mov fp,sp + if ((unsigned char)global_registers[Spc]+1 < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + 27c8: 00800074 movhi r2,1 + 27cc: 1090cd04 addi r2,r2,17204 + 27d0: 10800043 ldbu r2,1(r2) + 27d4: 10803fcc andi r2,r2,255 + 27d8: 10800044 addi r2,r2,1 + 27dc: 1009883a mov r4,r2 + 27e0: 00800074 movhi r2,1 + 27e4: 108f7504 addi r2,r2,15828 + 27e8: 10800017 ldw r2,0(r2) + 27ec: 1006913a slli r3,r2,4 + 27f0: 00804004 movi r2,256 + 27f4: 10c5c83a sub r2,r2,r3 + 27f8: 2080092e bgeu r4,r2,2820 + global_registers[Spc] = (unsigned char)global_registers[Spc] + 1; + 27fc: 00800074 movhi r2,1 + 2800: 1090cd04 addi r2,r2,17204 + 2804: 10800043 ldbu r2,1(r2) + 2808: 10800044 addi r2,r2,1 + 280c: 1007883a mov r3,r2 + 2810: 00800074 movhi r2,1 + 2814: 1090cd04 addi r2,r2,17204 + 2818: 10c00045 stb r3,1(r2) + 281c: 00000306 br 282c + } else { + global_registers[Spc] = 0; + 2820: 00800074 movhi r2,1 + 2824: 1090cd04 addi r2,r2,17204 + 2828: 10000045 stb zero,1(r2) + } + return 0; + 282c: 0005883a mov r2,zero +} + 2830: e037883a mov sp,fp + 2834: df000017 ldw fp,0(sp) + 2838: dec00104 addi sp,sp,4 + 283c: f800283a ret + +00002840 : +unsigned int add_pc(unsigned int cnt) { + 2840: defffc04 addi sp,sp,-16 + 2844: dfc00315 stw ra,12(sp) + 2848: df000215 stw fp,8(sp) + 284c: df000204 addi fp,sp,8 + 2850: e13fff15 stw r4,-4(fp) + int i; + for (i = 0; i < cnt; i++) inc_pc(); + 2854: e03ffe15 stw zero,-8(fp) + 2858: 00000406 br 286c + 285c: 00027bc0 call 27bc + 2860: e0bffe17 ldw r2,-8(fp) + 2864: 10800044 addi r2,r2,1 + 2868: e0bffe15 stw r2,-8(fp) + 286c: e0fffe17 ldw r3,-8(fp) + 2870: e0bfff17 ldw r2,-4(fp) + 2874: 18bff936 bltu r3,r2,285c + return 0; + 2878: 0005883a mov r2,zero +} + 287c: e037883a mov sp,fp + 2880: dfc00117 ldw ra,4(sp) + 2884: df000017 ldw fp,0(sp) + 2888: dec00204 addi sp,sp,8 + 288c: f800283a ret + +00002890 : +unsigned int set_pc(unsigned int cnt) { + 2890: defffe04 addi sp,sp,-8 + 2894: df000115 stw fp,4(sp) + 2898: df000104 addi fp,sp,4 + 289c: e13fff15 stw r4,-4(fp) + global_registers[Spc]=cnt; + 28a0: e0bfff17 ldw r2,-4(fp) + 28a4: 1007883a mov r3,r2 + 28a8: 00800074 movhi r2,1 + 28ac: 1090cd04 addi r2,r2,17204 + 28b0: 10c00045 stb r3,1(r2) + return 0; + 28b4: 0005883a mov r2,zero +} + 28b8: e037883a mov sp,fp + 28bc: df000017 ldw fp,0(sp) + 28c0: dec00104 addi sp,sp,4 + 28c4: f800283a ret + +000028c8 : +unsigned int get_pc() { + 28c8: defffe04 addi sp,sp,-8 + 28cc: df000115 stw fp,4(sp) + 28d0: df000104 addi fp,sp,4 + if ((unsigned char)global_registers[Spc] < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + 28d4: 00800074 movhi r2,1 + 28d8: 1090cd04 addi r2,r2,17204 + 28dc: 10800043 ldbu r2,1(r2) + 28e0: 11003fcc andi r4,r2,255 + 28e4: 00800074 movhi r2,1 + 28e8: 108f7504 addi r2,r2,15828 + 28ec: 10800017 ldw r2,0(r2) + 28f0: 1006913a slli r3,r2,4 + 28f4: 00804004 movi r2,256 + 28f8: 10c5c83a sub r2,r2,r3 + 28fc: 2080082e bgeu r4,r2,2920 + return (unsigned int)global_registers[Spc]; + 2900: 00800074 movhi r2,1 + 2904: 1090cd04 addi r2,r2,17204 + 2908: 10800043 ldbu r2,1(r2) + 290c: 10803fcc andi r2,r2,255 + 2910: 1080201c xori r2,r2,128 + 2914: 10bfe004 addi r2,r2,-128 + 2918: e0bfff15 stw r2,-4(fp) + 291c: 00000106 br 2924 + } else { + return 0; + 2920: e03fff15 stw zero,-4(fp) + 2924: e0bfff17 ldw r2,-4(fp) + } +} + 2928: e037883a mov sp,fp + 292c: df000017 ldw fp,0(sp) + 2930: dec00104 addi sp,sp,4 + 2934: f800283a ret + +00002938 : + +enum RunMode run_proc(enum RunMode mode) { + 2938: defff904 addi sp,sp,-28 + 293c: dfc00615 stw ra,24(sp) + 2940: df000515 stw fp,20(sp) + 2944: df000504 addi fp,sp,20 + 2948: e13ffe15 stw r4,-8(fp) + volatile struct InstRec inst_rec; + + if (RUN_INIT == mode) { + 294c: e0bffe17 ldw r2,-8(fp) + 2950: 10800058 cmpnei r2,r2,1 + 2954: 1000101e bne r2,zero,2998 + lcd_caret_reset(); + 2958: 0001f340 call 1f34 + lcd_print("Run...now"); + 295c: 01000074 movhi r4,1 + 2960: 21003004 addi r4,r4,192 + 2964: 0001f840 call 1f84 + + global_registers[Spc] = 0; + 2968: 00800074 movhi r2,1 + 296c: 1090cd04 addi r2,r2,17204 + 2970: 10000045 stb zero,1(r2) + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + 2974: 0009883a mov r4,zero + 2978: 00013480 call 1348 + 297c: 01000044 movi r4,1 + 2980: 00013480 call 1348 + 2984: 01000084 movi r4,2 + 2988: 00013480 call 1348 + + // �v���O�������s���֑J�� + return RUN_PROC; + 298c: 00800084 movi r2,2 + 2990: e0bfff15 stw r2,-4(fp) + 2994: 00003606 br 2a70 + } + + if (RUN_PROC == mode) { + 2998: e0bffe17 ldw r2,-8(fp) + 299c: 10800098 cmpnei r2,r2,2 + 29a0: 1000291e bne r2,zero,2a48 + // ���߃t�F�b�` + inst_rec = inst_fetch(); + 29a4: 00017900 call 1790 + 29a8: e0bffb15 stw r2,-20(fp) + // ���߃f�R�[�h���s + inst_decode(inst_rec); + 29ac: e13ffb17 ldw r4,-20(fp) + 29b0: 00017dc0 call 17dc + // pc�\�� + { + char buf[5]; + sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); + 29b4: 00800074 movhi r2,1 + 29b8: 1090cd04 addi r2,r2,17204 + 29bc: 10800043 ldbu r2,1(r2) + 29c0: 11803fcc andi r6,r2,255 + 29c4: e13ffc04 addi r4,fp,-16 + 29c8: 01400074 movhi r5,1 + 29cc: 29403304 addi r5,r5,204 + 29d0: 0002c5c0 call 2c5c + print_block("pc", 2, HEX6_7); + 29d4: 01000074 movhi r4,1 + 29d8: 21003504 addi r4,r4,212 + 29dc: 01400084 movi r5,2 + 29e0: 01800084 movi r6,2 + 29e4: 00011b80 call 11b8 + print_block(buf, 2, HEX4_5); + 29e8: e13ffc04 addi r4,fp,-16 + 29ec: 01400084 movi r5,2 + 29f0: 01800044 movi r6,1 + 29f4: 00011b80 call 11b8 + } + + // �f�o�b�N�p + if ( global_registers[Ssw_run] ) delay10ms(100U); + 29f8: 00800074 movhi r2,1 + 29fc: 1090cd04 addi r2,r2,17204 + 2a00: 10800343 ldbu r2,13(r2) + 2a04: 10803fcc andi r2,r2,255 + 2a08: 1080201c xori r2,r2,128 + 2a0c: 10bfe004 addi r2,r2,-128 + 2a10: 1005003a cmpeq r2,r2,zero + 2a14: 1000021e bne r2,zero,2a20 + 2a18: 01001904 movi r4,100 + 2a1c: 00025000 call 2500 + + // �v���O�����I������ + if (inst_rec.inst != INST_END) return RUN_PROC; + 2a20: e0bffb17 ldw r2,-20(fp) + 2a24: 108003cc andi r2,r2,15 + 2a28: 1005003a cmpeq r2,r2,zero + 2a2c: 1000031e bne r2,zero,2a3c + 2a30: 00800084 movi r2,2 + 2a34: e0bfff15 stw r2,-4(fp) + 2a38: 00000d06 br 2a70 + return RUN_TERM; + 2a3c: 008000c4 movi r2,3 + 2a40: e0bfff15 stw r2,-4(fp) + 2a44: 00000a06 br 2a70 + } + + if (RUN_TERM == mode) { + 2a48: e0bffe17 ldw r2,-8(fp) + 2a4c: 108000d8 cmpnei r2,r2,3 + 2a50: 1000061e bne r2,zero,2a6c + lcd_caret_reset(); + 2a54: 0001f340 call 1f34 + lcd_print("Run...Exit"); + 2a58: 01000074 movhi r4,1 + 2a5c: 21003604 addi r4,r4,216 + 2a60: 0001f840 call 1f84 + return RUN_STOP; + 2a64: e03fff15 stw zero,-4(fp) + 2a68: 00000106 br 2a70 + } + + // Default + return RUN_STOP; + 2a6c: e03fff15 stw zero,-4(fp) + 2a70: e0bfff17 ldw r2,-4(fp) +} + 2a74: e037883a mov sp,fp + 2a78: dfc00117 ldw ra,4(sp) + 2a7c: df000017 ldw fp,0(sp) + 2a80: dec00204 addi sp,sp,8 + 2a84: f800283a ret + +00002a88 : + */ +#include "sys_register.h" + +char global_registers[REG_MAX_COUNT]; + +void registers_init() { + 2a88: defffe04 addi sp,sp,-8 + 2a8c: df000115 stw fp,4(sp) + 2a90: df000104 addi fp,sp,4 + int i; + for (i = 0; i < REG_MAX_COUNT; i++) global_registers[i] = 0; + 2a94: e03fff15 stw zero,-4(fp) + 2a98: 00000806 br 2abc + 2a9c: e0ffff17 ldw r3,-4(fp) + 2aa0: 00800074 movhi r2,1 + 2aa4: 1090cd04 addi r2,r2,17204 + 2aa8: 10c5883a add r2,r2,r3 + 2aac: 10000005 stb zero,0(r2) + 2ab0: e0bfff17 ldw r2,-4(fp) + 2ab4: 10800044 addi r2,r2,1 + 2ab8: e0bfff15 stw r2,-4(fp) + 2abc: e0bfff17 ldw r2,-4(fp) + 2ac0: 108003d0 cmplti r2,r2,15 + 2ac4: 103ff51e bne r2,zero,2a9c +} + 2ac8: e037883a mov sp,fp + 2acc: df000017 ldw fp,0(sp) + 2ad0: dec00104 addi sp,sp,4 + 2ad4: f800283a ret + +00002ad8 : + 2ad8: 29001b2e bgeu r5,r4,2b48 + 2adc: 28001a16 blt r5,zero,2b48 + 2ae0: 00800044 movi r2,1 + 2ae4: 0007883a mov r3,zero + 2ae8: 01c007c4 movi r7,31 + 2aec: 00000306 br 2afc + 2af0: 19c01326 beq r3,r7,2b40 + 2af4: 18c00044 addi r3,r3,1 + 2af8: 28000416 blt r5,zero,2b0c + 2afc: 294b883a add r5,r5,r5 + 2b00: 1085883a add r2,r2,r2 + 2b04: 293ffa36 bltu r5,r4,2af0 + 2b08: 10000d26 beq r2,zero,2b40 + 2b0c: 0007883a mov r3,zero + 2b10: 21400236 bltu r4,r5,2b1c + 2b14: 2149c83a sub r4,r4,r5 + 2b18: 1886b03a or r3,r3,r2 + 2b1c: 1004d07a srli r2,r2,1 + 2b20: 280ad07a srli r5,r5,1 + 2b24: 103ffa1e bne r2,zero,2b10 + 2b28: 30000226 beq r6,zero,2b34 + 2b2c: 2005883a mov r2,r4 + 2b30: f800283a ret + 2b34: 1809883a mov r4,r3 + 2b38: 2005883a mov r2,r4 + 2b3c: f800283a ret + 2b40: 0007883a mov r3,zero + 2b44: 003ff806 br 2b28 + 2b48: 00800044 movi r2,1 + 2b4c: 0007883a mov r3,zero + 2b50: 003fef06 br 2b10 + +00002b54 <__divsi3>: + 2b54: defffe04 addi sp,sp,-8 + 2b58: dc000015 stw r16,0(sp) + 2b5c: dfc00115 stw ra,4(sp) + 2b60: 0021883a mov r16,zero + 2b64: 20000c16 blt r4,zero,2b98 <__divsi3+0x44> + 2b68: 000d883a mov r6,zero + 2b6c: 28000e16 blt r5,zero,2ba8 <__divsi3+0x54> + 2b70: 0002ad80 call 2ad8 + 2b74: 1007883a mov r3,r2 + 2b78: 8005003a cmpeq r2,r16,zero + 2b7c: 1000011e bne r2,zero,2b84 <__divsi3+0x30> + 2b80: 00c7c83a sub r3,zero,r3 + 2b84: 1805883a mov r2,r3 + 2b88: dfc00117 ldw ra,4(sp) + 2b8c: dc000017 ldw r16,0(sp) + 2b90: dec00204 addi sp,sp,8 + 2b94: f800283a ret + 2b98: 0109c83a sub r4,zero,r4 + 2b9c: 04000044 movi r16,1 + 2ba0: 000d883a mov r6,zero + 2ba4: 283ff20e bge r5,zero,2b70 <__divsi3+0x1c> + 2ba8: 014bc83a sub r5,zero,r5 + 2bac: 8021003a cmpeq r16,r16,zero + 2bb0: 003fef06 br 2b70 <__divsi3+0x1c> + +00002bb4 <__modsi3>: + 2bb4: deffff04 addi sp,sp,-4 + 2bb8: dfc00015 stw ra,0(sp) + 2bbc: 01800044 movi r6,1 + 2bc0: 2807883a mov r3,r5 + 2bc4: 20000416 blt r4,zero,2bd8 <__modsi3+0x24> + 2bc8: 28000c16 blt r5,zero,2bfc <__modsi3+0x48> + 2bcc: dfc00017 ldw ra,0(sp) + 2bd0: dec00104 addi sp,sp,4 + 2bd4: 0002ad81 jmpi 2ad8 + 2bd8: 0109c83a sub r4,zero,r4 + 2bdc: 28000b16 blt r5,zero,2c0c <__modsi3+0x58> + 2be0: 180b883a mov r5,r3 + 2be4: 01800044 movi r6,1 + 2be8: 0002ad80 call 2ad8 + 2bec: 0085c83a sub r2,zero,r2 + 2bf0: dfc00017 ldw ra,0(sp) + 2bf4: dec00104 addi sp,sp,4 + 2bf8: f800283a ret + 2bfc: 014bc83a sub r5,zero,r5 + 2c00: dfc00017 ldw ra,0(sp) + 2c04: dec00104 addi sp,sp,4 + 2c08: 0002ad81 jmpi 2ad8 + 2c0c: 0147c83a sub r3,zero,r5 + 2c10: 003ff306 br 2be0 <__modsi3+0x2c> + +00002c14 <__udivsi3>: + 2c14: 000d883a mov r6,zero + 2c18: 0002ad81 jmpi 2ad8 + +00002c1c <__umodsi3>: + 2c1c: 01800044 movi r6,1 + 2c20: 0002ad81 jmpi 2ad8 + +00002c24 <__mulsi3>: + 2c24: 20000a26 beq r4,zero,2c50 <__mulsi3+0x2c> + 2c28: 0007883a mov r3,zero + 2c2c: 2080004c andi r2,r4,1 + 2c30: 1005003a cmpeq r2,r2,zero + 2c34: 2008d07a srli r4,r4,1 + 2c38: 1000011e bne r2,zero,2c40 <__mulsi3+0x1c> + 2c3c: 1947883a add r3,r3,r5 + 2c40: 294b883a add r5,r5,r5 + 2c44: 203ff91e bne r4,zero,2c2c <__mulsi3+0x8> + 2c48: 1805883a mov r2,r3 + 2c4c: f800283a ret + 2c50: 0007883a mov r3,zero + 2c54: 1805883a mov r2,r3 + 2c58: f800283a ret + +00002c5c : + 2c5c: deffe504 addi sp,sp,-108 + 2c60: 2013883a mov r9,r4 + 2c64: dfc01815 stw ra,96(sp) + 2c68: d9801915 stw r6,100(sp) + 2c6c: d9c01a15 stw r7,104(sp) + 2c70: d8801904 addi r2,sp,100 + 2c74: d8800015 stw r2,0(sp) + 2c78: 00800074 movhi r2,1 + 2c7c: 10887e04 addi r2,r2,8696 + 2c80: 11000017 ldw r4,0(r2) + 2c84: d9c00017 ldw r7,0(sp) + 2c88: 00808204 movi r2,520 + 2c8c: 00e00034 movhi r3,32768 + 2c90: 18ffffc4 addi r3,r3,-1 + 2c94: 280d883a mov r6,r5 + 2c98: d880040d sth r2,16(sp) + 2c9c: d9400104 addi r5,sp,4 + 2ca0: 00bfffc4 movi r2,-1 + 2ca4: d8c00615 stw r3,24(sp) + 2ca8: d8c00315 stw r3,12(sp) + 2cac: da400515 stw r9,20(sp) + 2cb0: d880048d sth r2,18(sp) + 2cb4: da400115 stw r9,4(sp) + 2cb8: 0002dfc0 call 2dfc <___vfprintf_internal_r> + 2cbc: d8c00117 ldw r3,4(sp) + 2cc0: 18000005 stb zero,0(r3) + 2cc4: dfc01817 ldw ra,96(sp) + 2cc8: dec01b04 addi sp,sp,108 + 2ccc: f800283a ret + +00002cd0 <_sprintf_r>: + 2cd0: deffe604 addi sp,sp,-104 + 2cd4: 2813883a mov r9,r5 + 2cd8: dfc01815 stw ra,96(sp) + 2cdc: d9c01915 stw r7,100(sp) + 2ce0: d8801904 addi r2,sp,100 + 2ce4: d8800015 stw r2,0(sp) + 2ce8: 100f883a mov r7,r2 + 2cec: 00808204 movi r2,520 + 2cf0: 00e00034 movhi r3,32768 + 2cf4: 18ffffc4 addi r3,r3,-1 + 2cf8: d880040d sth r2,16(sp) + 2cfc: d9400104 addi r5,sp,4 + 2d00: 00bfffc4 movi r2,-1 + 2d04: d8c00615 stw r3,24(sp) + 2d08: d8c00315 stw r3,12(sp) + 2d0c: da400515 stw r9,20(sp) + 2d10: d880048d sth r2,18(sp) + 2d14: da400115 stw r9,4(sp) + 2d18: 0002dfc0 call 2dfc <___vfprintf_internal_r> + 2d1c: d8c00117 ldw r3,4(sp) + 2d20: 18000005 stb zero,0(r3) + 2d24: dfc01817 ldw ra,96(sp) + 2d28: dec01a04 addi sp,sp,104 + 2d2c: f800283a ret + +00002d30 : + 2d30: 208000cc andi r2,r4,3 + 2d34: 2011883a mov r8,r4 + 2d38: 1000161e bne r2,zero,2d94 + 2d3c: 20c00017 ldw r3,0(r4) + 2d40: 017fbff4 movhi r5,65279 + 2d44: 297fbfc4 addi r5,r5,-257 + 2d48: 01e02074 movhi r7,32897 + 2d4c: 39e02004 addi r7,r7,-32640 + 2d50: 1945883a add r2,r3,r5 + 2d54: 11c4703a and r2,r2,r7 + 2d58: 00c6303a nor r3,zero,r3 + 2d5c: 1886703a and r3,r3,r2 + 2d60: 18000c1e bne r3,zero,2d94 + 2d64: 280d883a mov r6,r5 + 2d68: 380b883a mov r5,r7 + 2d6c: 21000104 addi r4,r4,4 + 2d70: 20800017 ldw r2,0(r4) + 2d74: 1187883a add r3,r2,r6 + 2d78: 1946703a and r3,r3,r5 + 2d7c: 0084303a nor r2,zero,r2 + 2d80: 10c4703a and r2,r2,r3 + 2d84: 103ff926 beq r2,zero,2d6c + 2d88: 20800007 ldb r2,0(r4) + 2d8c: 10000326 beq r2,zero,2d9c + 2d90: 21000044 addi r4,r4,1 + 2d94: 20800007 ldb r2,0(r4) + 2d98: 103ffd1e bne r2,zero,2d90 + 2d9c: 2205c83a sub r2,r4,r8 + 2da0: f800283a ret + +00002da4 <__sprint_r>: + 2da4: 30800217 ldw r2,8(r6) + 2da8: defffe04 addi sp,sp,-8 + 2dac: dc000015 stw r16,0(sp) + 2db0: dfc00115 stw ra,4(sp) + 2db4: 3021883a mov r16,r6 + 2db8: 0007883a mov r3,zero + 2dbc: 1000061e bne r2,zero,2dd8 <__sprint_r+0x34> + 2dc0: 1805883a mov r2,r3 + 2dc4: 30000115 stw zero,4(r6) + 2dc8: dfc00117 ldw ra,4(sp) + 2dcc: dc000017 ldw r16,0(sp) + 2dd0: dec00204 addi sp,sp,8 + 2dd4: f800283a ret + 2dd8: 0006f7c0 call 6f7c <__sfvwrite_r> + 2ddc: 1007883a mov r3,r2 + 2de0: 1805883a mov r2,r3 + 2de4: 80000115 stw zero,4(r16) + 2de8: 80000215 stw zero,8(r16) + 2dec: dfc00117 ldw ra,4(sp) + 2df0: dc000017 ldw r16,0(sp) + 2df4: dec00204 addi sp,sp,8 + 2df8: f800283a ret + +00002dfc <___vfprintf_internal_r>: + 2dfc: defea404 addi sp,sp,-1392 + 2e00: dd815815 stw r22,1376(sp) + 2e04: dc015215 stw r16,1352(sp) + 2e08: d9c15115 stw r7,1348(sp) + 2e0c: dfc15b15 stw ra,1388(sp) + 2e10: df015a15 stw fp,1384(sp) + 2e14: ddc15915 stw r23,1380(sp) + 2e18: dd415715 stw r21,1372(sp) + 2e1c: dd015615 stw r20,1368(sp) + 2e20: dcc15515 stw r19,1364(sp) + 2e24: dc815415 stw r18,1360(sp) + 2e28: dc415315 stw r17,1356(sp) + 2e2c: 282d883a mov r22,r5 + 2e30: 3021883a mov r16,r6 + 2e34: d9014f15 stw r4,1340(sp) + 2e38: 00075a00 call 75a0 <_localeconv_r> + 2e3c: 10800017 ldw r2,0(r2) + 2e40: d9c15117 ldw r7,1348(sp) + 2e44: d8814915 stw r2,1316(sp) + 2e48: d8814f17 ldw r2,1340(sp) + 2e4c: 10000226 beq r2,zero,2e58 <___vfprintf_internal_r+0x5c> + 2e50: 10800e17 ldw r2,56(r2) + 2e54: 10020d26 beq r2,zero,368c <___vfprintf_internal_r+0x890> + 2e58: b080030b ldhu r2,12(r22) + 2e5c: 1080020c andi r2,r2,8 + 2e60: 10020e26 beq r2,zero,369c <___vfprintf_internal_r+0x8a0> + 2e64: b0800417 ldw r2,16(r22) + 2e68: 10020c26 beq r2,zero,369c <___vfprintf_internal_r+0x8a0> + 2e6c: b200030b ldhu r8,12(r22) + 2e70: 00800284 movi r2,10 + 2e74: 40c0068c andi r3,r8,26 + 2e78: 18802f1e bne r3,r2,2f38 <___vfprintf_internal_r+0x13c> + 2e7c: b080038f ldh r2,14(r22) + 2e80: 10002d16 blt r2,zero,2f38 <___vfprintf_internal_r+0x13c> + 2e84: b240038b ldhu r9,14(r22) + 2e88: b2800717 ldw r10,28(r22) + 2e8c: b2c00917 ldw r11,36(r22) + 2e90: d9014f17 ldw r4,1340(sp) + 2e94: dc402904 addi r17,sp,164 + 2e98: d8804004 addi r2,sp,256 + 2e9c: 00c10004 movi r3,1024 + 2ea0: 423fff4c andi r8,r8,65533 + 2ea4: 800d883a mov r6,r16 + 2ea8: 880b883a mov r5,r17 + 2eac: da002c0d sth r8,176(sp) + 2eb0: da402c8d sth r9,178(sp) + 2eb4: da803015 stw r10,192(sp) + 2eb8: dac03215 stw r11,200(sp) + 2ebc: d8802d15 stw r2,180(sp) + 2ec0: d8c02e15 stw r3,184(sp) + 2ec4: d8802915 stw r2,164(sp) + 2ec8: d8c02b15 stw r3,172(sp) + 2ecc: d8002f15 stw zero,188(sp) + 2ed0: 0002dfc0 call 2dfc <___vfprintf_internal_r> + 2ed4: d8814b15 stw r2,1324(sp) + 2ed8: 10000416 blt r2,zero,2eec <___vfprintf_internal_r+0xf0> + 2edc: d9014f17 ldw r4,1340(sp) + 2ee0: 880b883a mov r5,r17 + 2ee4: 00066180 call 6618 <_fflush_r> + 2ee8: 1002321e bne r2,zero,37b4 <___vfprintf_internal_r+0x9b8> + 2eec: d8802c0b ldhu r2,176(sp) + 2ef0: 1080100c andi r2,r2,64 + 2ef4: 10000326 beq r2,zero,2f04 <___vfprintf_internal_r+0x108> + 2ef8: b080030b ldhu r2,12(r22) + 2efc: 10801014 ori r2,r2,64 + 2f00: b080030d sth r2,12(r22) + 2f04: d8814b17 ldw r2,1324(sp) + 2f08: dfc15b17 ldw ra,1388(sp) + 2f0c: df015a17 ldw fp,1384(sp) + 2f10: ddc15917 ldw r23,1380(sp) + 2f14: dd815817 ldw r22,1376(sp) + 2f18: dd415717 ldw r21,1372(sp) + 2f1c: dd015617 ldw r20,1368(sp) + 2f20: dcc15517 ldw r19,1364(sp) + 2f24: dc815417 ldw r18,1360(sp) + 2f28: dc415317 ldw r17,1356(sp) + 2f2c: dc015217 ldw r16,1352(sp) + 2f30: dec15c04 addi sp,sp,1392 + 2f34: f800283a ret + 2f38: 0005883a mov r2,zero + 2f3c: 0007883a mov r3,zero + 2f40: dd401904 addi r21,sp,100 + 2f44: d8814215 stw r2,1288(sp) + 2f48: 802f883a mov r23,r16 + 2f4c: d8c14315 stw r3,1292(sp) + 2f50: d8014b15 stw zero,1324(sp) + 2f54: d8014815 stw zero,1312(sp) + 2f58: d8014415 stw zero,1296(sp) + 2f5c: d8014715 stw zero,1308(sp) + 2f60: dd400c15 stw r21,48(sp) + 2f64: d8000e15 stw zero,56(sp) + 2f68: d8000d15 stw zero,52(sp) + 2f6c: b8800007 ldb r2,0(r23) + 2f70: 10001926 beq r2,zero,2fd8 <___vfprintf_internal_r+0x1dc> + 2f74: 00c00944 movi r3,37 + 2f78: 10c01726 beq r2,r3,2fd8 <___vfprintf_internal_r+0x1dc> + 2f7c: b821883a mov r16,r23 + 2f80: 00000106 br 2f88 <___vfprintf_internal_r+0x18c> + 2f84: 10c00326 beq r2,r3,2f94 <___vfprintf_internal_r+0x198> + 2f88: 84000044 addi r16,r16,1 + 2f8c: 80800007 ldb r2,0(r16) + 2f90: 103ffc1e bne r2,zero,2f84 <___vfprintf_internal_r+0x188> + 2f94: 85e7c83a sub r19,r16,r23 + 2f98: 98000e26 beq r19,zero,2fd4 <___vfprintf_internal_r+0x1d8> + 2f9c: dc800e17 ldw r18,56(sp) + 2fa0: dc400d17 ldw r17,52(sp) + 2fa4: 008001c4 movi r2,7 + 2fa8: 94e5883a add r18,r18,r19 + 2fac: 8c400044 addi r17,r17,1 + 2fb0: adc00015 stw r23,0(r21) + 2fb4: dc800e15 stw r18,56(sp) + 2fb8: acc00115 stw r19,4(r21) + 2fbc: dc400d15 stw r17,52(sp) + 2fc0: 14428b16 blt r2,r17,39f0 <___vfprintf_internal_r+0xbf4> + 2fc4: ad400204 addi r21,r21,8 + 2fc8: d9014b17 ldw r4,1324(sp) + 2fcc: 24c9883a add r4,r4,r19 + 2fd0: d9014b15 stw r4,1324(sp) + 2fd4: 802f883a mov r23,r16 + 2fd8: b8800007 ldb r2,0(r23) + 2fdc: 10013c26 beq r2,zero,34d0 <___vfprintf_internal_r+0x6d4> + 2fe0: bdc00044 addi r23,r23,1 + 2fe4: d8000405 stb zero,16(sp) + 2fe8: b8c00007 ldb r3,0(r23) + 2fec: 04ffffc4 movi r19,-1 + 2ff0: d8014c15 stw zero,1328(sp) + 2ff4: d8014a15 stw zero,1320(sp) + 2ff8: d8c14d15 stw r3,1332(sp) + 2ffc: bdc00044 addi r23,r23,1 + 3000: d9414d17 ldw r5,1332(sp) + 3004: 00801604 movi r2,88 + 3008: 28fff804 addi r3,r5,-32 + 300c: 10c06036 bltu r2,r3,3190 <___vfprintf_internal_r+0x394> + 3010: 18c5883a add r2,r3,r3 + 3014: 1085883a add r2,r2,r2 + 3018: 00c00034 movhi r3,0 + 301c: 18cc0b04 addi r3,r3,12332 + 3020: 10c5883a add r2,r2,r3 + 3024: 11000017 ldw r4,0(r2) + 3028: 2000683a jmp r4 + 302c: 00003fa0 cmpeqi zero,zero,254 + 3030: 00003190 cmplti zero,zero,198 + 3034: 00003190 cmplti zero,zero,198 + 3038: 00003f8c andi zero,zero,254 + 303c: 00003190 cmplti zero,zero,198 + 3040: 00003190 cmplti zero,zero,198 + 3044: 00003190 cmplti zero,zero,198 + 3048: 00003190 cmplti zero,zero,198 + 304c: 00003190 cmplti zero,zero,198 + 3050: 00003190 cmplti zero,zero,198 + 3054: 00003d6c andhi zero,zero,245 + 3058: 00003f7c xorhi zero,zero,253 + 305c: 00003190 cmplti zero,zero,198 + 3060: 00003d84 movi zero,246 + 3064: 00004024 muli zero,zero,256 + 3068: 00003190 cmplti zero,zero,198 + 306c: 00004010 cmplti zero,zero,256 + 3070: 00003fcc andi zero,zero,255 + 3074: 00003fcc andi zero,zero,255 + 3078: 00003fcc andi zero,zero,255 + 307c: 00003fcc andi zero,zero,255 + 3080: 00003fcc andi zero,zero,255 + 3084: 00003fcc andi zero,zero,255 + 3088: 00003fcc andi zero,zero,255 + 308c: 00003fcc andi zero,zero,255 + 3090: 00003fcc andi zero,zero,255 + 3094: 00003190 cmplti zero,zero,198 + 3098: 00003190 cmplti zero,zero,198 + 309c: 00003190 cmplti zero,zero,198 + 30a0: 00003190 cmplti zero,zero,198 + 30a4: 00003190 cmplti zero,zero,198 + 30a8: 00003190 cmplti zero,zero,198 + 30ac: 00003190 cmplti zero,zero,198 + 30b0: 00003190 cmplti zero,zero,198 + 30b4: 00003190 cmplti zero,zero,198 + 30b8: 00003190 cmplti zero,zero,198 + 30bc: 000037e8 cmpgeui zero,zero,223 + 30c0: 00003e54 movui zero,249 + 30c4: 00003190 cmplti zero,zero,198 + 30c8: 00003e54 movui zero,249 + 30cc: 00003190 cmplti zero,zero,198 + 30d0: 00003190 cmplti zero,zero,198 + 30d4: 00003190 cmplti zero,zero,198 + 30d8: 00003190 cmplti zero,zero,198 + 30dc: 00003fb8 rdprs zero,zero,254 + 30e0: 00003190 cmplti zero,zero,198 + 30e4: 00003190 cmplti zero,zero,198 + 30e8: 0000389c xori zero,zero,226 + 30ec: 00003190 cmplti zero,zero,198 + 30f0: 00003190 cmplti zero,zero,198 + 30f4: 00003190 cmplti zero,zero,198 + 30f8: 00003190 cmplti zero,zero,198 + 30fc: 00003190 cmplti zero,zero,198 + 3100: 000038e8 cmpgeui zero,zero,227 + 3104: 00003190 cmplti zero,zero,198 + 3108: 00003190 cmplti zero,zero,198 + 310c: 00003f08 cmpgei zero,zero,252 + 3110: 00003190 cmplti zero,zero,198 + 3114: 00003190 cmplti zero,zero,198 + 3118: 00003190 cmplti zero,zero,198 + 311c: 00003190 cmplti zero,zero,198 + 3120: 00003190 cmplti zero,zero,198 + 3124: 00003190 cmplti zero,zero,198 + 3128: 00003190 cmplti zero,zero,198 + 312c: 00003190 cmplti zero,zero,198 + 3130: 00003190 cmplti zero,zero,198 + 3134: 00003190 cmplti zero,zero,198 + 3138: 00003edc xori zero,zero,251 + 313c: 000037f4 movhi zero,223 + 3140: 00003e54 movui zero,249 + 3144: 00003e54 movui zero,249 + 3148: 00003e54 movui zero,249 + 314c: 00003e40 call 3e4 + 3150: 000037f4 movhi zero,223 + 3154: 00003190 cmplti zero,zero,198 + 3158: 00003190 cmplti zero,zero,198 + 315c: 00003dc8 cmpgei zero,zero,247 + 3160: 00003190 cmplti zero,zero,198 + 3164: 00003d98 cmpnei zero,zero,246 + 3168: 000038a8 cmpgeui zero,zero,226 + 316c: 00003df8 rdprs zero,zero,247 + 3170: 00003de4 muli zero,zero,247 + 3174: 00003190 cmplti zero,zero,198 + 3178: 0000408c andi zero,zero,258 + 317c: 00003190 cmplti zero,zero,198 + 3180: 000038f4 movhi zero,227 + 3184: 00003190 cmplti zero,zero,198 + 3188: 00003190 cmplti zero,zero,198 + 318c: 00003f6c andhi zero,zero,253 + 3190: d9014d17 ldw r4,1332(sp) + 3194: 2000ce26 beq r4,zero,34d0 <___vfprintf_internal_r+0x6d4> + 3198: 01400044 movi r5,1 + 319c: d9800f04 addi r6,sp,60 + 31a0: d9c14015 stw r7,1280(sp) + 31a4: d9414515 stw r5,1300(sp) + 31a8: d9814115 stw r6,1284(sp) + 31ac: 280f883a mov r7,r5 + 31b0: d9000f05 stb r4,60(sp) + 31b4: d8000405 stb zero,16(sp) + 31b8: d8014615 stw zero,1304(sp) + 31bc: d8c14c17 ldw r3,1328(sp) + 31c0: 1880008c andi r2,r3,2 + 31c4: 1005003a cmpeq r2,r2,zero + 31c8: d8815015 stw r2,1344(sp) + 31cc: 1000031e bne r2,zero,31dc <___vfprintf_internal_r+0x3e0> + 31d0: d9014517 ldw r4,1300(sp) + 31d4: 21000084 addi r4,r4,2 + 31d8: d9014515 stw r4,1300(sp) + 31dc: d9414c17 ldw r5,1328(sp) + 31e0: 2940210c andi r5,r5,132 + 31e4: d9414e15 stw r5,1336(sp) + 31e8: 28002d1e bne r5,zero,32a0 <___vfprintf_internal_r+0x4a4> + 31ec: d9814a17 ldw r6,1320(sp) + 31f0: d8814517 ldw r2,1300(sp) + 31f4: 30a1c83a sub r16,r6,r2 + 31f8: 0400290e bge zero,r16,32a0 <___vfprintf_internal_r+0x4a4> + 31fc: 00800404 movi r2,16 + 3200: 14045e0e bge r2,r16,437c <___vfprintf_internal_r+0x1580> + 3204: dc800e17 ldw r18,56(sp) + 3208: dc400d17 ldw r17,52(sp) + 320c: 1027883a mov r19,r2 + 3210: 07000074 movhi fp,1 + 3214: e700f584 addi fp,fp,982 + 3218: 050001c4 movi r20,7 + 321c: 00000306 br 322c <___vfprintf_internal_r+0x430> + 3220: 843ffc04 addi r16,r16,-16 + 3224: ad400204 addi r21,r21,8 + 3228: 9c00130e bge r19,r16,3278 <___vfprintf_internal_r+0x47c> + 322c: 94800404 addi r18,r18,16 + 3230: 8c400044 addi r17,r17,1 + 3234: af000015 stw fp,0(r21) + 3238: acc00115 stw r19,4(r21) + 323c: dc800e15 stw r18,56(sp) + 3240: dc400d15 stw r17,52(sp) + 3244: a47ff60e bge r20,r17,3220 <___vfprintf_internal_r+0x424> + 3248: d9014f17 ldw r4,1340(sp) + 324c: b00b883a mov r5,r22 + 3250: d9800c04 addi r6,sp,48 + 3254: d9c15115 stw r7,1348(sp) + 3258: 0002da40 call 2da4 <__sprint_r> + 325c: d9c15117 ldw r7,1348(sp) + 3260: 10009e1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3264: 843ffc04 addi r16,r16,-16 + 3268: dc800e17 ldw r18,56(sp) + 326c: dc400d17 ldw r17,52(sp) + 3270: dd401904 addi r21,sp,100 + 3274: 9c3fed16 blt r19,r16,322c <___vfprintf_internal_r+0x430> + 3278: 9425883a add r18,r18,r16 + 327c: 8c400044 addi r17,r17,1 + 3280: 008001c4 movi r2,7 + 3284: af000015 stw fp,0(r21) + 3288: ac000115 stw r16,4(r21) + 328c: dc800e15 stw r18,56(sp) + 3290: dc400d15 stw r17,52(sp) + 3294: 1441f516 blt r2,r17,3a6c <___vfprintf_internal_r+0xc70> + 3298: ad400204 addi r21,r21,8 + 329c: 00000206 br 32a8 <___vfprintf_internal_r+0x4ac> + 32a0: dc800e17 ldw r18,56(sp) + 32a4: dc400d17 ldw r17,52(sp) + 32a8: d8800407 ldb r2,16(sp) + 32ac: 10000b26 beq r2,zero,32dc <___vfprintf_internal_r+0x4e0> + 32b0: 00800044 movi r2,1 + 32b4: 94800044 addi r18,r18,1 + 32b8: 8c400044 addi r17,r17,1 + 32bc: a8800115 stw r2,4(r21) + 32c0: d8c00404 addi r3,sp,16 + 32c4: 008001c4 movi r2,7 + 32c8: a8c00015 stw r3,0(r21) + 32cc: dc800e15 stw r18,56(sp) + 32d0: dc400d15 stw r17,52(sp) + 32d4: 1441da16 blt r2,r17,3a40 <___vfprintf_internal_r+0xc44> + 32d8: ad400204 addi r21,r21,8 + 32dc: d9015017 ldw r4,1344(sp) + 32e0: 20000b1e bne r4,zero,3310 <___vfprintf_internal_r+0x514> + 32e4: d8800444 addi r2,sp,17 + 32e8: 94800084 addi r18,r18,2 + 32ec: 8c400044 addi r17,r17,1 + 32f0: a8800015 stw r2,0(r21) + 32f4: 00c00084 movi r3,2 + 32f8: 008001c4 movi r2,7 + 32fc: a8c00115 stw r3,4(r21) + 3300: dc800e15 stw r18,56(sp) + 3304: dc400d15 stw r17,52(sp) + 3308: 1441c216 blt r2,r17,3a14 <___vfprintf_internal_r+0xc18> + 330c: ad400204 addi r21,r21,8 + 3310: d9414e17 ldw r5,1336(sp) + 3314: 00802004 movi r2,128 + 3318: 2880b126 beq r5,r2,35e0 <___vfprintf_internal_r+0x7e4> + 331c: d8c14617 ldw r3,1304(sp) + 3320: 19e1c83a sub r16,r3,r7 + 3324: 0400260e bge zero,r16,33c0 <___vfprintf_internal_r+0x5c4> + 3328: 00800404 movi r2,16 + 332c: 1403cf0e bge r2,r16,426c <___vfprintf_internal_r+0x1470> + 3330: 1027883a mov r19,r2 + 3334: 07000074 movhi fp,1 + 3338: e700f184 addi fp,fp,966 + 333c: 050001c4 movi r20,7 + 3340: 00000306 br 3350 <___vfprintf_internal_r+0x554> + 3344: 843ffc04 addi r16,r16,-16 + 3348: ad400204 addi r21,r21,8 + 334c: 9c00130e bge r19,r16,339c <___vfprintf_internal_r+0x5a0> + 3350: 94800404 addi r18,r18,16 + 3354: 8c400044 addi r17,r17,1 + 3358: af000015 stw fp,0(r21) + 335c: acc00115 stw r19,4(r21) + 3360: dc800e15 stw r18,56(sp) + 3364: dc400d15 stw r17,52(sp) + 3368: a47ff60e bge r20,r17,3344 <___vfprintf_internal_r+0x548> + 336c: d9014f17 ldw r4,1340(sp) + 3370: b00b883a mov r5,r22 + 3374: d9800c04 addi r6,sp,48 + 3378: d9c15115 stw r7,1348(sp) + 337c: 0002da40 call 2da4 <__sprint_r> + 3380: d9c15117 ldw r7,1348(sp) + 3384: 1000551e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3388: 843ffc04 addi r16,r16,-16 + 338c: dc800e17 ldw r18,56(sp) + 3390: dc400d17 ldw r17,52(sp) + 3394: dd401904 addi r21,sp,100 + 3398: 9c3fed16 blt r19,r16,3350 <___vfprintf_internal_r+0x554> + 339c: 9425883a add r18,r18,r16 + 33a0: 8c400044 addi r17,r17,1 + 33a4: 008001c4 movi r2,7 + 33a8: af000015 stw fp,0(r21) + 33ac: ac000115 stw r16,4(r21) + 33b0: dc800e15 stw r18,56(sp) + 33b4: dc400d15 stw r17,52(sp) + 33b8: 14418216 blt r2,r17,39c4 <___vfprintf_internal_r+0xbc8> + 33bc: ad400204 addi r21,r21,8 + 33c0: d9014c17 ldw r4,1328(sp) + 33c4: 2080400c andi r2,r4,256 + 33c8: 10004a1e bne r2,zero,34f4 <___vfprintf_internal_r+0x6f8> + 33cc: d9414117 ldw r5,1284(sp) + 33d0: 91e5883a add r18,r18,r7 + 33d4: 8c400044 addi r17,r17,1 + 33d8: 008001c4 movi r2,7 + 33dc: a9400015 stw r5,0(r21) + 33e0: a9c00115 stw r7,4(r21) + 33e4: dc800e15 stw r18,56(sp) + 33e8: dc400d15 stw r17,52(sp) + 33ec: 14416716 blt r2,r17,398c <___vfprintf_internal_r+0xb90> + 33f0: a8c00204 addi r3,r21,8 + 33f4: d9814c17 ldw r6,1328(sp) + 33f8: 3080010c andi r2,r6,4 + 33fc: 10002826 beq r2,zero,34a0 <___vfprintf_internal_r+0x6a4> + 3400: d8814a17 ldw r2,1320(sp) + 3404: d9014517 ldw r4,1300(sp) + 3408: 1121c83a sub r16,r2,r4 + 340c: 0400240e bge zero,r16,34a0 <___vfprintf_internal_r+0x6a4> + 3410: 00800404 movi r2,16 + 3414: 1404550e bge r2,r16,456c <___vfprintf_internal_r+0x1770> + 3418: dc400d17 ldw r17,52(sp) + 341c: 1027883a mov r19,r2 + 3420: 07000074 movhi fp,1 + 3424: e700f584 addi fp,fp,982 + 3428: 050001c4 movi r20,7 + 342c: 00000306 br 343c <___vfprintf_internal_r+0x640> + 3430: 843ffc04 addi r16,r16,-16 + 3434: 18c00204 addi r3,r3,8 + 3438: 9c00110e bge r19,r16,3480 <___vfprintf_internal_r+0x684> + 343c: 94800404 addi r18,r18,16 + 3440: 8c400044 addi r17,r17,1 + 3444: 1f000015 stw fp,0(r3) + 3448: 1cc00115 stw r19,4(r3) + 344c: dc800e15 stw r18,56(sp) + 3450: dc400d15 stw r17,52(sp) + 3454: a47ff60e bge r20,r17,3430 <___vfprintf_internal_r+0x634> + 3458: d9014f17 ldw r4,1340(sp) + 345c: b00b883a mov r5,r22 + 3460: d9800c04 addi r6,sp,48 + 3464: 0002da40 call 2da4 <__sprint_r> + 3468: 10001c1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 346c: 843ffc04 addi r16,r16,-16 + 3470: dc800e17 ldw r18,56(sp) + 3474: dc400d17 ldw r17,52(sp) + 3478: d8c01904 addi r3,sp,100 + 347c: 9c3fef16 blt r19,r16,343c <___vfprintf_internal_r+0x640> + 3480: 9425883a add r18,r18,r16 + 3484: 8c400044 addi r17,r17,1 + 3488: 008001c4 movi r2,7 + 348c: 1f000015 stw fp,0(r3) + 3490: 1c000115 stw r16,4(r3) + 3494: dc800e15 stw r18,56(sp) + 3498: dc400d15 stw r17,52(sp) + 349c: 1440cb16 blt r2,r17,37cc <___vfprintf_internal_r+0x9d0> + 34a0: d8814a17 ldw r2,1320(sp) + 34a4: d9414517 ldw r5,1300(sp) + 34a8: 1140010e bge r2,r5,34b0 <___vfprintf_internal_r+0x6b4> + 34ac: 2805883a mov r2,r5 + 34b0: d9814b17 ldw r6,1324(sp) + 34b4: 308d883a add r6,r6,r2 + 34b8: d9814b15 stw r6,1324(sp) + 34bc: 90013b1e bne r18,zero,39ac <___vfprintf_internal_r+0xbb0> + 34c0: d9c14017 ldw r7,1280(sp) + 34c4: dd401904 addi r21,sp,100 + 34c8: d8000d15 stw zero,52(sp) + 34cc: 003ea706 br 2f6c <___vfprintf_internal_r+0x170> + 34d0: d8800e17 ldw r2,56(sp) + 34d4: 1005451e bne r2,zero,49ec <___vfprintf_internal_r+0x1bf0> + 34d8: d8000d15 stw zero,52(sp) + 34dc: b080030b ldhu r2,12(r22) + 34e0: 1080100c andi r2,r2,64 + 34e4: 103e8726 beq r2,zero,2f04 <___vfprintf_internal_r+0x108> + 34e8: 00bfffc4 movi r2,-1 + 34ec: d8814b15 stw r2,1324(sp) + 34f0: 003e8406 br 2f04 <___vfprintf_internal_r+0x108> + 34f4: d9814d17 ldw r6,1332(sp) + 34f8: 00801944 movi r2,101 + 34fc: 11806e16 blt r2,r6,36b8 <___vfprintf_internal_r+0x8bc> + 3500: d9414717 ldw r5,1308(sp) + 3504: 00c00044 movi r3,1 + 3508: 1943490e bge r3,r5,4230 <___vfprintf_internal_r+0x1434> + 350c: d8814117 ldw r2,1284(sp) + 3510: 94800044 addi r18,r18,1 + 3514: 8c400044 addi r17,r17,1 + 3518: a8800015 stw r2,0(r21) + 351c: 008001c4 movi r2,7 + 3520: a8c00115 stw r3,4(r21) + 3524: dc800e15 stw r18,56(sp) + 3528: dc400d15 stw r17,52(sp) + 352c: 1441ca16 blt r2,r17,3c58 <___vfprintf_internal_r+0xe5c> + 3530: a8c00204 addi r3,r21,8 + 3534: d9014917 ldw r4,1316(sp) + 3538: 00800044 movi r2,1 + 353c: 94800044 addi r18,r18,1 + 3540: 8c400044 addi r17,r17,1 + 3544: 18800115 stw r2,4(r3) + 3548: 008001c4 movi r2,7 + 354c: 19000015 stw r4,0(r3) + 3550: dc800e15 stw r18,56(sp) + 3554: dc400d15 stw r17,52(sp) + 3558: 1441b616 blt r2,r17,3c34 <___vfprintf_internal_r+0xe38> + 355c: 1cc00204 addi r19,r3,8 + 3560: d9014217 ldw r4,1288(sp) + 3564: d9414317 ldw r5,1292(sp) + 3568: 000d883a mov r6,zero + 356c: 000f883a mov r7,zero + 3570: 000b8b00 call b8b0 <__nedf2> + 3574: 10017426 beq r2,zero,3b48 <___vfprintf_internal_r+0xd4c> + 3578: d9414717 ldw r5,1308(sp) + 357c: d9814117 ldw r6,1284(sp) + 3580: 8c400044 addi r17,r17,1 + 3584: 2c85883a add r2,r5,r18 + 3588: 14bfffc4 addi r18,r2,-1 + 358c: 28bfffc4 addi r2,r5,-1 + 3590: 30c00044 addi r3,r6,1 + 3594: 98800115 stw r2,4(r19) + 3598: 008001c4 movi r2,7 + 359c: 98c00015 stw r3,0(r19) + 35a0: dc800e15 stw r18,56(sp) + 35a4: dc400d15 stw r17,52(sp) + 35a8: 14418e16 blt r2,r17,3be4 <___vfprintf_internal_r+0xde8> + 35ac: 9cc00204 addi r19,r19,8 + 35b0: d9414817 ldw r5,1312(sp) + 35b4: d8800804 addi r2,sp,32 + 35b8: 8c400044 addi r17,r17,1 + 35bc: 9165883a add r18,r18,r5 + 35c0: 98800015 stw r2,0(r19) + 35c4: 008001c4 movi r2,7 + 35c8: 99400115 stw r5,4(r19) + 35cc: dc800e15 stw r18,56(sp) + 35d0: dc400d15 stw r17,52(sp) + 35d4: 1440ed16 blt r2,r17,398c <___vfprintf_internal_r+0xb90> + 35d8: 98c00204 addi r3,r19,8 + 35dc: 003f8506 br 33f4 <___vfprintf_internal_r+0x5f8> + 35e0: d9814a17 ldw r6,1320(sp) + 35e4: d8814517 ldw r2,1300(sp) + 35e8: 30a1c83a sub r16,r6,r2 + 35ec: 043f4b0e bge zero,r16,331c <___vfprintf_internal_r+0x520> + 35f0: 00800404 movi r2,16 + 35f4: 14043a0e bge r2,r16,46e0 <___vfprintf_internal_r+0x18e4> + 35f8: 1027883a mov r19,r2 + 35fc: 07000074 movhi fp,1 + 3600: e700f184 addi fp,fp,966 + 3604: 050001c4 movi r20,7 + 3608: 00000306 br 3618 <___vfprintf_internal_r+0x81c> + 360c: 843ffc04 addi r16,r16,-16 + 3610: ad400204 addi r21,r21,8 + 3614: 9c00130e bge r19,r16,3664 <___vfprintf_internal_r+0x868> + 3618: 94800404 addi r18,r18,16 + 361c: 8c400044 addi r17,r17,1 + 3620: af000015 stw fp,0(r21) + 3624: acc00115 stw r19,4(r21) + 3628: dc800e15 stw r18,56(sp) + 362c: dc400d15 stw r17,52(sp) + 3630: a47ff60e bge r20,r17,360c <___vfprintf_internal_r+0x810> + 3634: d9014f17 ldw r4,1340(sp) + 3638: b00b883a mov r5,r22 + 363c: d9800c04 addi r6,sp,48 + 3640: d9c15115 stw r7,1348(sp) + 3644: 0002da40 call 2da4 <__sprint_r> + 3648: d9c15117 ldw r7,1348(sp) + 364c: 103fa31e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3650: 843ffc04 addi r16,r16,-16 + 3654: dc800e17 ldw r18,56(sp) + 3658: dc400d17 ldw r17,52(sp) + 365c: dd401904 addi r21,sp,100 + 3660: 9c3fed16 blt r19,r16,3618 <___vfprintf_internal_r+0x81c> + 3664: 9425883a add r18,r18,r16 + 3668: 8c400044 addi r17,r17,1 + 366c: 008001c4 movi r2,7 + 3670: af000015 stw fp,0(r21) + 3674: ac000115 stw r16,4(r21) + 3678: dc800e15 stw r18,56(sp) + 367c: dc400d15 stw r17,52(sp) + 3680: 14416116 blt r2,r17,3c08 <___vfprintf_internal_r+0xe0c> + 3684: ad400204 addi r21,r21,8 + 3688: 003f2406 br 331c <___vfprintf_internal_r+0x520> + 368c: d9014f17 ldw r4,1340(sp) + 3690: 00068b00 call 68b0 <__sinit> + 3694: d9c15117 ldw r7,1348(sp) + 3698: 003def06 br 2e58 <___vfprintf_internal_r+0x5c> + 369c: d9014f17 ldw r4,1340(sp) + 36a0: b00b883a mov r5,r22 + 36a4: d9c15115 stw r7,1348(sp) + 36a8: 0004ce40 call 4ce4 <__swsetup_r> + 36ac: d9c15117 ldw r7,1348(sp) + 36b0: 103dee26 beq r2,zero,2e6c <___vfprintf_internal_r+0x70> + 36b4: 003f8c06 br 34e8 <___vfprintf_internal_r+0x6ec> + 36b8: d9014217 ldw r4,1288(sp) + 36bc: d9414317 ldw r5,1292(sp) + 36c0: 000d883a mov r6,zero + 36c4: 000f883a mov r7,zero + 36c8: 000b8280 call b828 <__eqdf2> + 36cc: 1000f21e bne r2,zero,3a98 <___vfprintf_internal_r+0xc9c> + 36d0: 00800074 movhi r2,1 + 36d4: 1080f104 addi r2,r2,964 + 36d8: 94800044 addi r18,r18,1 + 36dc: 8c400044 addi r17,r17,1 + 36e0: a8800015 stw r2,0(r21) + 36e4: 00c00044 movi r3,1 + 36e8: 008001c4 movi r2,7 + 36ec: a8c00115 stw r3,4(r21) + 36f0: dc800e15 stw r18,56(sp) + 36f4: dc400d15 stw r17,52(sp) + 36f8: 14430016 blt r2,r17,42fc <___vfprintf_internal_r+0x1500> + 36fc: a8c00204 addi r3,r21,8 + 3700: d8800517 ldw r2,20(sp) + 3704: d9014717 ldw r4,1308(sp) + 3708: 11015c0e bge r2,r4,3c7c <___vfprintf_internal_r+0xe80> + 370c: dc400d17 ldw r17,52(sp) + 3710: d9814917 ldw r6,1316(sp) + 3714: 00800044 movi r2,1 + 3718: 94800044 addi r18,r18,1 + 371c: 8c400044 addi r17,r17,1 + 3720: 18800115 stw r2,4(r3) + 3724: 008001c4 movi r2,7 + 3728: 19800015 stw r6,0(r3) + 372c: dc800e15 stw r18,56(sp) + 3730: dc400d15 stw r17,52(sp) + 3734: 14431616 blt r2,r17,4390 <___vfprintf_internal_r+0x1594> + 3738: 18c00204 addi r3,r3,8 + 373c: d8814717 ldw r2,1308(sp) + 3740: 143fffc4 addi r16,r2,-1 + 3744: 043f2b0e bge zero,r16,33f4 <___vfprintf_internal_r+0x5f8> + 3748: 00800404 movi r2,16 + 374c: 1402a80e bge r2,r16,41f0 <___vfprintf_internal_r+0x13f4> + 3750: dc400d17 ldw r17,52(sp) + 3754: 1027883a mov r19,r2 + 3758: 07000074 movhi fp,1 + 375c: e700f184 addi fp,fp,966 + 3760: 050001c4 movi r20,7 + 3764: 00000306 br 3774 <___vfprintf_internal_r+0x978> + 3768: 18c00204 addi r3,r3,8 + 376c: 843ffc04 addi r16,r16,-16 + 3770: 9c02a20e bge r19,r16,41fc <___vfprintf_internal_r+0x1400> + 3774: 94800404 addi r18,r18,16 + 3778: 8c400044 addi r17,r17,1 + 377c: 1f000015 stw fp,0(r3) + 3780: 1cc00115 stw r19,4(r3) + 3784: dc800e15 stw r18,56(sp) + 3788: dc400d15 stw r17,52(sp) + 378c: a47ff60e bge r20,r17,3768 <___vfprintf_internal_r+0x96c> + 3790: d9014f17 ldw r4,1340(sp) + 3794: b00b883a mov r5,r22 + 3798: d9800c04 addi r6,sp,48 + 379c: 0002da40 call 2da4 <__sprint_r> + 37a0: 103f4e1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 37a4: dc800e17 ldw r18,56(sp) + 37a8: dc400d17 ldw r17,52(sp) + 37ac: d8c01904 addi r3,sp,100 + 37b0: 003fee06 br 376c <___vfprintf_internal_r+0x970> + 37b4: d8802c0b ldhu r2,176(sp) + 37b8: 00ffffc4 movi r3,-1 + 37bc: d8c14b15 stw r3,1324(sp) + 37c0: 1080100c andi r2,r2,64 + 37c4: 103dcc1e bne r2,zero,2ef8 <___vfprintf_internal_r+0xfc> + 37c8: 003dce06 br 2f04 <___vfprintf_internal_r+0x108> + 37cc: d9014f17 ldw r4,1340(sp) + 37d0: b00b883a mov r5,r22 + 37d4: d9800c04 addi r6,sp,48 + 37d8: 0002da40 call 2da4 <__sprint_r> + 37dc: 103f3f1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 37e0: dc800e17 ldw r18,56(sp) + 37e4: 003f2e06 br 34a0 <___vfprintf_internal_r+0x6a4> + 37e8: d9414c17 ldw r5,1328(sp) + 37ec: 29400414 ori r5,r5,16 + 37f0: d9414c15 stw r5,1328(sp) + 37f4: d9814c17 ldw r6,1328(sp) + 37f8: 3080080c andi r2,r6,32 + 37fc: 10014f1e bne r2,zero,3d3c <___vfprintf_internal_r+0xf40> + 3800: d8c14c17 ldw r3,1328(sp) + 3804: 1880040c andi r2,r3,16 + 3808: 1002f01e bne r2,zero,43cc <___vfprintf_internal_r+0x15d0> + 380c: d9014c17 ldw r4,1328(sp) + 3810: 2080100c andi r2,r4,64 + 3814: 1002ed26 beq r2,zero,43cc <___vfprintf_internal_r+0x15d0> + 3818: 3880000f ldh r2,0(r7) + 381c: 39c00104 addi r7,r7,4 + 3820: d9c14015 stw r7,1280(sp) + 3824: 1023d7fa srai r17,r2,31 + 3828: 1021883a mov r16,r2 + 382c: 88037816 blt r17,zero,4610 <___vfprintf_internal_r+0x1814> + 3830: 01000044 movi r4,1 + 3834: 98000416 blt r19,zero,3848 <___vfprintf_internal_r+0xa4c> + 3838: d8c14c17 ldw r3,1328(sp) + 383c: 00bfdfc4 movi r2,-129 + 3840: 1886703a and r3,r3,r2 + 3844: d8c14c15 stw r3,1328(sp) + 3848: 8444b03a or r2,r16,r17 + 384c: 10022c1e bne r2,zero,4100 <___vfprintf_internal_r+0x1304> + 3850: 98022b1e bne r19,zero,4100 <___vfprintf_internal_r+0x1304> + 3854: 20803fcc andi r2,r4,255 + 3858: 1002a126 beq r2,zero,42e0 <___vfprintf_internal_r+0x14e4> + 385c: d8c01904 addi r3,sp,100 + 3860: dd000f04 addi r20,sp,60 + 3864: d8c14115 stw r3,1284(sp) + 3868: d8c14117 ldw r3,1284(sp) + 386c: dcc14515 stw r19,1300(sp) + 3870: a0c5c83a sub r2,r20,r3 + 3874: 11c00a04 addi r7,r2,40 + 3878: 99c0010e bge r19,r7,3880 <___vfprintf_internal_r+0xa84> + 387c: d9c14515 stw r7,1300(sp) + 3880: dcc14615 stw r19,1304(sp) + 3884: d8800407 ldb r2,16(sp) + 3888: 103e4c26 beq r2,zero,31bc <___vfprintf_internal_r+0x3c0> + 388c: d8814517 ldw r2,1300(sp) + 3890: 10800044 addi r2,r2,1 + 3894: d8814515 stw r2,1300(sp) + 3898: 003e4806 br 31bc <___vfprintf_internal_r+0x3c0> + 389c: d9814c17 ldw r6,1328(sp) + 38a0: 31800414 ori r6,r6,16 + 38a4: d9814c15 stw r6,1328(sp) + 38a8: d8c14c17 ldw r3,1328(sp) + 38ac: 1880080c andi r2,r3,32 + 38b0: 1001271e bne r2,zero,3d50 <___vfprintf_internal_r+0xf54> + 38b4: d9414c17 ldw r5,1328(sp) + 38b8: 2880040c andi r2,r5,16 + 38bc: 1002bc1e bne r2,zero,43b0 <___vfprintf_internal_r+0x15b4> + 38c0: d9814c17 ldw r6,1328(sp) + 38c4: 3080100c andi r2,r6,64 + 38c8: 1002b926 beq r2,zero,43b0 <___vfprintf_internal_r+0x15b4> + 38cc: 3c00000b ldhu r16,0(r7) + 38d0: 0009883a mov r4,zero + 38d4: 39c00104 addi r7,r7,4 + 38d8: 0023883a mov r17,zero + 38dc: d9c14015 stw r7,1280(sp) + 38e0: d8000405 stb zero,16(sp) + 38e4: 003fd306 br 3834 <___vfprintf_internal_r+0xa38> + 38e8: d9014c17 ldw r4,1328(sp) + 38ec: 21000414 ori r4,r4,16 + 38f0: d9014c15 stw r4,1328(sp) + 38f4: d9414c17 ldw r5,1328(sp) + 38f8: 2880080c andi r2,r5,32 + 38fc: 1001081e bne r2,zero,3d20 <___vfprintf_internal_r+0xf24> + 3900: d8c14c17 ldw r3,1328(sp) + 3904: 1880040c andi r2,r3,16 + 3908: 1002b61e bne r2,zero,43e4 <___vfprintf_internal_r+0x15e8> + 390c: d9014c17 ldw r4,1328(sp) + 3910: 2080100c andi r2,r4,64 + 3914: 1002b326 beq r2,zero,43e4 <___vfprintf_internal_r+0x15e8> + 3918: 3c00000b ldhu r16,0(r7) + 391c: 01000044 movi r4,1 + 3920: 39c00104 addi r7,r7,4 + 3924: 0023883a mov r17,zero + 3928: d9c14015 stw r7,1280(sp) + 392c: d8000405 stb zero,16(sp) + 3930: 003fc006 br 3834 <___vfprintf_internal_r+0xa38> + 3934: d9014f17 ldw r4,1340(sp) + 3938: b00b883a mov r5,r22 + 393c: d9800c04 addi r6,sp,48 + 3940: 0002da40 call 2da4 <__sprint_r> + 3944: 103ee51e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3948: dc800e17 ldw r18,56(sp) + 394c: d8c01904 addi r3,sp,100 + 3950: d9814c17 ldw r6,1328(sp) + 3954: 3080004c andi r2,r6,1 + 3958: 1005003a cmpeq r2,r2,zero + 395c: 103ea51e bne r2,zero,33f4 <___vfprintf_internal_r+0x5f8> + 3960: 00800044 movi r2,1 + 3964: dc400d17 ldw r17,52(sp) + 3968: 18800115 stw r2,4(r3) + 396c: d8814917 ldw r2,1316(sp) + 3970: 94800044 addi r18,r18,1 + 3974: 8c400044 addi r17,r17,1 + 3978: 18800015 stw r2,0(r3) + 397c: 008001c4 movi r2,7 + 3980: dc800e15 stw r18,56(sp) + 3984: dc400d15 stw r17,52(sp) + 3988: 1442240e bge r2,r17,421c <___vfprintf_internal_r+0x1420> + 398c: d9014f17 ldw r4,1340(sp) + 3990: b00b883a mov r5,r22 + 3994: d9800c04 addi r6,sp,48 + 3998: 0002da40 call 2da4 <__sprint_r> + 399c: 103ecf1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 39a0: dc800e17 ldw r18,56(sp) + 39a4: d8c01904 addi r3,sp,100 + 39a8: 003e9206 br 33f4 <___vfprintf_internal_r+0x5f8> + 39ac: d9014f17 ldw r4,1340(sp) + 39b0: b00b883a mov r5,r22 + 39b4: d9800c04 addi r6,sp,48 + 39b8: 0002da40 call 2da4 <__sprint_r> + 39bc: 103ec026 beq r2,zero,34c0 <___vfprintf_internal_r+0x6c4> + 39c0: 003ec606 br 34dc <___vfprintf_internal_r+0x6e0> + 39c4: d9014f17 ldw r4,1340(sp) + 39c8: b00b883a mov r5,r22 + 39cc: d9800c04 addi r6,sp,48 + 39d0: d9c15115 stw r7,1348(sp) + 39d4: 0002da40 call 2da4 <__sprint_r> + 39d8: d9c15117 ldw r7,1348(sp) + 39dc: 103ebf1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 39e0: dc800e17 ldw r18,56(sp) + 39e4: dc400d17 ldw r17,52(sp) + 39e8: dd401904 addi r21,sp,100 + 39ec: 003e7406 br 33c0 <___vfprintf_internal_r+0x5c4> + 39f0: d9014f17 ldw r4,1340(sp) + 39f4: b00b883a mov r5,r22 + 39f8: d9800c04 addi r6,sp,48 + 39fc: d9c15115 stw r7,1348(sp) + 3a00: 0002da40 call 2da4 <__sprint_r> + 3a04: d9c15117 ldw r7,1348(sp) + 3a08: 103eb41e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3a0c: dd401904 addi r21,sp,100 + 3a10: 003d6d06 br 2fc8 <___vfprintf_internal_r+0x1cc> + 3a14: d9014f17 ldw r4,1340(sp) + 3a18: b00b883a mov r5,r22 + 3a1c: d9800c04 addi r6,sp,48 + 3a20: d9c15115 stw r7,1348(sp) + 3a24: 0002da40 call 2da4 <__sprint_r> + 3a28: d9c15117 ldw r7,1348(sp) + 3a2c: 103eab1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3a30: dc800e17 ldw r18,56(sp) + 3a34: dc400d17 ldw r17,52(sp) + 3a38: dd401904 addi r21,sp,100 + 3a3c: 003e3406 br 3310 <___vfprintf_internal_r+0x514> + 3a40: d9014f17 ldw r4,1340(sp) + 3a44: b00b883a mov r5,r22 + 3a48: d9800c04 addi r6,sp,48 + 3a4c: d9c15115 stw r7,1348(sp) + 3a50: 0002da40 call 2da4 <__sprint_r> + 3a54: d9c15117 ldw r7,1348(sp) + 3a58: 103ea01e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3a5c: dc800e17 ldw r18,56(sp) + 3a60: dc400d17 ldw r17,52(sp) + 3a64: dd401904 addi r21,sp,100 + 3a68: 003e1c06 br 32dc <___vfprintf_internal_r+0x4e0> + 3a6c: d9014f17 ldw r4,1340(sp) + 3a70: b00b883a mov r5,r22 + 3a74: d9800c04 addi r6,sp,48 + 3a78: d9c15115 stw r7,1348(sp) + 3a7c: 0002da40 call 2da4 <__sprint_r> + 3a80: d9c15117 ldw r7,1348(sp) + 3a84: 103e951e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3a88: dc800e17 ldw r18,56(sp) + 3a8c: dc400d17 ldw r17,52(sp) + 3a90: dd401904 addi r21,sp,100 + 3a94: 003e0406 br 32a8 <___vfprintf_internal_r+0x4ac> + 3a98: d9000517 ldw r4,20(sp) + 3a9c: 0102580e bge zero,r4,4400 <___vfprintf_internal_r+0x1604> + 3aa0: d9814717 ldw r6,1308(sp) + 3aa4: 21807a16 blt r4,r6,3c90 <___vfprintf_internal_r+0xe94> + 3aa8: d8814117 ldw r2,1284(sp) + 3aac: 91a5883a add r18,r18,r6 + 3ab0: 8c400044 addi r17,r17,1 + 3ab4: a8800015 stw r2,0(r21) + 3ab8: 008001c4 movi r2,7 + 3abc: a9800115 stw r6,4(r21) + 3ac0: dc800e15 stw r18,56(sp) + 3ac4: dc400d15 stw r17,52(sp) + 3ac8: 1442fc16 blt r2,r17,46bc <___vfprintf_internal_r+0x18c0> + 3acc: a8c00204 addi r3,r21,8 + 3ad0: d9414717 ldw r5,1308(sp) + 3ad4: 2161c83a sub r16,r4,r5 + 3ad8: 043f9d0e bge zero,r16,3950 <___vfprintf_internal_r+0xb54> + 3adc: 00800404 movi r2,16 + 3ae0: 1402190e bge r2,r16,4348 <___vfprintf_internal_r+0x154c> + 3ae4: dc400d17 ldw r17,52(sp) + 3ae8: 1027883a mov r19,r2 + 3aec: 07000074 movhi fp,1 + 3af0: e700f184 addi fp,fp,966 + 3af4: 050001c4 movi r20,7 + 3af8: 00000306 br 3b08 <___vfprintf_internal_r+0xd0c> + 3afc: 18c00204 addi r3,r3,8 + 3b00: 843ffc04 addi r16,r16,-16 + 3b04: 9c02130e bge r19,r16,4354 <___vfprintf_internal_r+0x1558> + 3b08: 94800404 addi r18,r18,16 + 3b0c: 8c400044 addi r17,r17,1 + 3b10: 1f000015 stw fp,0(r3) + 3b14: 1cc00115 stw r19,4(r3) + 3b18: dc800e15 stw r18,56(sp) + 3b1c: dc400d15 stw r17,52(sp) + 3b20: a47ff60e bge r20,r17,3afc <___vfprintf_internal_r+0xd00> + 3b24: d9014f17 ldw r4,1340(sp) + 3b28: b00b883a mov r5,r22 + 3b2c: d9800c04 addi r6,sp,48 + 3b30: 0002da40 call 2da4 <__sprint_r> + 3b34: 103e691e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3b38: dc800e17 ldw r18,56(sp) + 3b3c: dc400d17 ldw r17,52(sp) + 3b40: d8c01904 addi r3,sp,100 + 3b44: 003fee06 br 3b00 <___vfprintf_internal_r+0xd04> + 3b48: d8814717 ldw r2,1308(sp) + 3b4c: 143fffc4 addi r16,r2,-1 + 3b50: 043e970e bge zero,r16,35b0 <___vfprintf_internal_r+0x7b4> + 3b54: 00800404 movi r2,16 + 3b58: 1400180e bge r2,r16,3bbc <___vfprintf_internal_r+0xdc0> + 3b5c: 1029883a mov r20,r2 + 3b60: 07000074 movhi fp,1 + 3b64: e700f184 addi fp,fp,966 + 3b68: 054001c4 movi r21,7 + 3b6c: 00000306 br 3b7c <___vfprintf_internal_r+0xd80> + 3b70: 9cc00204 addi r19,r19,8 + 3b74: 843ffc04 addi r16,r16,-16 + 3b78: a400120e bge r20,r16,3bc4 <___vfprintf_internal_r+0xdc8> + 3b7c: 94800404 addi r18,r18,16 + 3b80: 8c400044 addi r17,r17,1 + 3b84: 9f000015 stw fp,0(r19) + 3b88: 9d000115 stw r20,4(r19) + 3b8c: dc800e15 stw r18,56(sp) + 3b90: dc400d15 stw r17,52(sp) + 3b94: ac7ff60e bge r21,r17,3b70 <___vfprintf_internal_r+0xd74> + 3b98: d9014f17 ldw r4,1340(sp) + 3b9c: b00b883a mov r5,r22 + 3ba0: d9800c04 addi r6,sp,48 + 3ba4: 0002da40 call 2da4 <__sprint_r> + 3ba8: 103e4c1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3bac: dc800e17 ldw r18,56(sp) + 3bb0: dc400d17 ldw r17,52(sp) + 3bb4: dcc01904 addi r19,sp,100 + 3bb8: 003fee06 br 3b74 <___vfprintf_internal_r+0xd78> + 3bbc: 07000074 movhi fp,1 + 3bc0: e700f184 addi fp,fp,966 + 3bc4: 9425883a add r18,r18,r16 + 3bc8: 8c400044 addi r17,r17,1 + 3bcc: 008001c4 movi r2,7 + 3bd0: 9f000015 stw fp,0(r19) + 3bd4: 9c000115 stw r16,4(r19) + 3bd8: dc800e15 stw r18,56(sp) + 3bdc: dc400d15 stw r17,52(sp) + 3be0: 147e720e bge r2,r17,35ac <___vfprintf_internal_r+0x7b0> + 3be4: d9014f17 ldw r4,1340(sp) + 3be8: b00b883a mov r5,r22 + 3bec: d9800c04 addi r6,sp,48 + 3bf0: 0002da40 call 2da4 <__sprint_r> + 3bf4: 103e391e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3bf8: dc800e17 ldw r18,56(sp) + 3bfc: dc400d17 ldw r17,52(sp) + 3c00: dcc01904 addi r19,sp,100 + 3c04: 003e6a06 br 35b0 <___vfprintf_internal_r+0x7b4> + 3c08: d9014f17 ldw r4,1340(sp) + 3c0c: b00b883a mov r5,r22 + 3c10: d9800c04 addi r6,sp,48 + 3c14: d9c15115 stw r7,1348(sp) + 3c18: 0002da40 call 2da4 <__sprint_r> + 3c1c: d9c15117 ldw r7,1348(sp) + 3c20: 103e2e1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3c24: dc800e17 ldw r18,56(sp) + 3c28: dc400d17 ldw r17,52(sp) + 3c2c: dd401904 addi r21,sp,100 + 3c30: 003dba06 br 331c <___vfprintf_internal_r+0x520> + 3c34: d9014f17 ldw r4,1340(sp) + 3c38: b00b883a mov r5,r22 + 3c3c: d9800c04 addi r6,sp,48 + 3c40: 0002da40 call 2da4 <__sprint_r> + 3c44: 103e251e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3c48: dc800e17 ldw r18,56(sp) + 3c4c: dc400d17 ldw r17,52(sp) + 3c50: dcc01904 addi r19,sp,100 + 3c54: 003e4206 br 3560 <___vfprintf_internal_r+0x764> + 3c58: d9014f17 ldw r4,1340(sp) + 3c5c: b00b883a mov r5,r22 + 3c60: d9800c04 addi r6,sp,48 + 3c64: 0002da40 call 2da4 <__sprint_r> + 3c68: 103e1c1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 3c6c: dc800e17 ldw r18,56(sp) + 3c70: dc400d17 ldw r17,52(sp) + 3c74: d8c01904 addi r3,sp,100 + 3c78: 003e2e06 br 3534 <___vfprintf_internal_r+0x738> + 3c7c: d9414c17 ldw r5,1328(sp) + 3c80: 2880004c andi r2,r5,1 + 3c84: 1005003a cmpeq r2,r2,zero + 3c88: 103dda1e bne r2,zero,33f4 <___vfprintf_internal_r+0x5f8> + 3c8c: 003e9f06 br 370c <___vfprintf_internal_r+0x910> + 3c90: d8c14117 ldw r3,1284(sp) + 3c94: 9125883a add r18,r18,r4 + 3c98: 8c400044 addi r17,r17,1 + 3c9c: 008001c4 movi r2,7 + 3ca0: a8c00015 stw r3,0(r21) + 3ca4: a9000115 stw r4,4(r21) + 3ca8: dc800e15 stw r18,56(sp) + 3cac: dc400d15 stw r17,52(sp) + 3cb0: 14426c16 blt r2,r17,4664 <___vfprintf_internal_r+0x1868> + 3cb4: a8c00204 addi r3,r21,8 + 3cb8: d9414917 ldw r5,1316(sp) + 3cbc: 00800044 movi r2,1 + 3cc0: 94800044 addi r18,r18,1 + 3cc4: 8c400044 addi r17,r17,1 + 3cc8: 18800115 stw r2,4(r3) + 3ccc: 008001c4 movi r2,7 + 3cd0: 19400015 stw r5,0(r3) + 3cd4: dc800e15 stw r18,56(sp) + 3cd8: dc400d15 stw r17,52(sp) + 3cdc: 2021883a mov r16,r4 + 3ce0: 14425616 blt r2,r17,463c <___vfprintf_internal_r+0x1840> + 3ce4: 19400204 addi r5,r3,8 + 3ce8: d9814717 ldw r6,1308(sp) + 3cec: 8c400044 addi r17,r17,1 + 3cf0: dc400d15 stw r17,52(sp) + 3cf4: 3107c83a sub r3,r6,r4 + 3cf8: d9014117 ldw r4,1284(sp) + 3cfc: 90e5883a add r18,r18,r3 + 3d00: 28c00115 stw r3,4(r5) + 3d04: 8105883a add r2,r16,r4 + 3d08: 28800015 stw r2,0(r5) + 3d0c: 008001c4 movi r2,7 + 3d10: dc800e15 stw r18,56(sp) + 3d14: 147f1d16 blt r2,r17,398c <___vfprintf_internal_r+0xb90> + 3d18: 28c00204 addi r3,r5,8 + 3d1c: 003db506 br 33f4 <___vfprintf_internal_r+0x5f8> + 3d20: 3c000017 ldw r16,0(r7) + 3d24: 3c400117 ldw r17,4(r7) + 3d28: 39800204 addi r6,r7,8 + 3d2c: 01000044 movi r4,1 + 3d30: d9814015 stw r6,1280(sp) + 3d34: d8000405 stb zero,16(sp) + 3d38: 003ebe06 br 3834 <___vfprintf_internal_r+0xa38> + 3d3c: 3c000017 ldw r16,0(r7) + 3d40: 3c400117 ldw r17,4(r7) + 3d44: 38800204 addi r2,r7,8 + 3d48: d8814015 stw r2,1280(sp) + 3d4c: 003eb706 br 382c <___vfprintf_internal_r+0xa30> + 3d50: 3c000017 ldw r16,0(r7) + 3d54: 3c400117 ldw r17,4(r7) + 3d58: 39000204 addi r4,r7,8 + 3d5c: d9014015 stw r4,1280(sp) + 3d60: 0009883a mov r4,zero + 3d64: d8000405 stb zero,16(sp) + 3d68: 003eb206 br 3834 <___vfprintf_internal_r+0xa38> + 3d6c: 38c00017 ldw r3,0(r7) + 3d70: 39c00104 addi r7,r7,4 + 3d74: d8c14a15 stw r3,1320(sp) + 3d78: 1800d70e bge r3,zero,40d8 <___vfprintf_internal_r+0x12dc> + 3d7c: 00c7c83a sub r3,zero,r3 + 3d80: d8c14a15 stw r3,1320(sp) + 3d84: d9014c17 ldw r4,1328(sp) + 3d88: b8c00007 ldb r3,0(r23) + 3d8c: 21000114 ori r4,r4,4 + 3d90: d9014c15 stw r4,1328(sp) + 3d94: 003c9806 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3d98: d9814c17 ldw r6,1328(sp) + 3d9c: 3080080c andi r2,r6,32 + 3da0: 1001f626 beq r2,zero,457c <___vfprintf_internal_r+0x1780> + 3da4: d9014b17 ldw r4,1324(sp) + 3da8: 38800017 ldw r2,0(r7) + 3dac: 39c00104 addi r7,r7,4 + 3db0: d9c14015 stw r7,1280(sp) + 3db4: 2007d7fa srai r3,r4,31 + 3db8: d9c14017 ldw r7,1280(sp) + 3dbc: 11000015 stw r4,0(r2) + 3dc0: 10c00115 stw r3,4(r2) + 3dc4: 003c6906 br 2f6c <___vfprintf_internal_r+0x170> + 3dc8: b8c00007 ldb r3,0(r23) + 3dcc: 00801b04 movi r2,108 + 3dd0: 18825526 beq r3,r2,4728 <___vfprintf_internal_r+0x192c> + 3dd4: d9414c17 ldw r5,1328(sp) + 3dd8: 29400414 ori r5,r5,16 + 3ddc: d9414c15 stw r5,1328(sp) + 3de0: 003c8506 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3de4: d9814c17 ldw r6,1328(sp) + 3de8: b8c00007 ldb r3,0(r23) + 3dec: 31800814 ori r6,r6,32 + 3df0: d9814c15 stw r6,1328(sp) + 3df4: 003c8006 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3df8: d8814c17 ldw r2,1328(sp) + 3dfc: 3c000017 ldw r16,0(r7) + 3e00: 00c01e04 movi r3,120 + 3e04: 10800094 ori r2,r2,2 + 3e08: d8814c15 stw r2,1328(sp) + 3e0c: 39c00104 addi r7,r7,4 + 3e10: 01400074 movhi r5,1 + 3e14: 2940da04 addi r5,r5,872 + 3e18: 00800c04 movi r2,48 + 3e1c: 0023883a mov r17,zero + 3e20: 01000084 movi r4,2 + 3e24: d9c14015 stw r7,1280(sp) + 3e28: d8c14d15 stw r3,1332(sp) + 3e2c: d9414415 stw r5,1296(sp) + 3e30: d8800445 stb r2,17(sp) + 3e34: d8c00485 stb r3,18(sp) + 3e38: d8000405 stb zero,16(sp) + 3e3c: 003e7d06 br 3834 <___vfprintf_internal_r+0xa38> + 3e40: d8814c17 ldw r2,1328(sp) + 3e44: b8c00007 ldb r3,0(r23) + 3e48: 10801014 ori r2,r2,64 + 3e4c: d8814c15 stw r2,1328(sp) + 3e50: 003c6906 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3e54: d9414c17 ldw r5,1328(sp) + 3e58: 2880020c andi r2,r5,8 + 3e5c: 1001e526 beq r2,zero,45f4 <___vfprintf_internal_r+0x17f8> + 3e60: 39800017 ldw r6,0(r7) + 3e64: 38800204 addi r2,r7,8 + 3e68: d8814015 stw r2,1280(sp) + 3e6c: d9814215 stw r6,1288(sp) + 3e70: 39c00117 ldw r7,4(r7) + 3e74: d9c14315 stw r7,1292(sp) + 3e78: d9014217 ldw r4,1288(sp) + 3e7c: d9414317 ldw r5,1292(sp) + 3e80: 00098ac0 call 98ac <__isinfd> + 3e84: 10021d26 beq r2,zero,46fc <___vfprintf_internal_r+0x1900> + 3e88: d9014217 ldw r4,1288(sp) + 3e8c: d9414317 ldw r5,1292(sp) + 3e90: 000d883a mov r6,zero + 3e94: 000f883a mov r7,zero + 3e98: 000ba480 call ba48 <__ltdf2> + 3e9c: 1002d016 blt r2,zero,49e0 <___vfprintf_internal_r+0x1be4> + 3ea0: d9414d17 ldw r5,1332(sp) + 3ea4: 008011c4 movi r2,71 + 3ea8: 11421016 blt r2,r5,46ec <___vfprintf_internal_r+0x18f0> + 3eac: 01800074 movhi r6,1 + 3eb0: 3180df04 addi r6,r6,892 + 3eb4: d9814115 stw r6,1284(sp) + 3eb8: d9014c17 ldw r4,1328(sp) + 3ebc: 00c000c4 movi r3,3 + 3ec0: 00bfdfc4 movi r2,-129 + 3ec4: 2088703a and r4,r4,r2 + 3ec8: 180f883a mov r7,r3 + 3ecc: d8c14515 stw r3,1300(sp) + 3ed0: d9014c15 stw r4,1328(sp) + 3ed4: d8014615 stw zero,1304(sp) + 3ed8: 003e6a06 br 3884 <___vfprintf_internal_r+0xa88> + 3edc: 38800017 ldw r2,0(r7) + 3ee0: 00c00044 movi r3,1 + 3ee4: 39c00104 addi r7,r7,4 + 3ee8: d9c14015 stw r7,1280(sp) + 3eec: d9000f04 addi r4,sp,60 + 3ef0: 180f883a mov r7,r3 + 3ef4: d8c14515 stw r3,1300(sp) + 3ef8: d9014115 stw r4,1284(sp) + 3efc: d8800f05 stb r2,60(sp) + 3f00: d8000405 stb zero,16(sp) + 3f04: 003cac06 br 31b8 <___vfprintf_internal_r+0x3bc> + 3f08: 01400074 movhi r5,1 + 3f0c: 2940e504 addi r5,r5,916 + 3f10: d9414415 stw r5,1296(sp) + 3f14: d9814c17 ldw r6,1328(sp) + 3f18: 3080080c andi r2,r6,32 + 3f1c: 1000ff26 beq r2,zero,431c <___vfprintf_internal_r+0x1520> + 3f20: 3c000017 ldw r16,0(r7) + 3f24: 3c400117 ldw r17,4(r7) + 3f28: 38800204 addi r2,r7,8 + 3f2c: d8814015 stw r2,1280(sp) + 3f30: d9414c17 ldw r5,1328(sp) + 3f34: 2880004c andi r2,r5,1 + 3f38: 1005003a cmpeq r2,r2,zero + 3f3c: 1000b91e bne r2,zero,4224 <___vfprintf_internal_r+0x1428> + 3f40: 8444b03a or r2,r16,r17 + 3f44: 1000b726 beq r2,zero,4224 <___vfprintf_internal_r+0x1428> + 3f48: d9814d17 ldw r6,1332(sp) + 3f4c: 29400094 ori r5,r5,2 + 3f50: 00800c04 movi r2,48 + 3f54: 01000084 movi r4,2 + 3f58: d9414c15 stw r5,1328(sp) + 3f5c: d8800445 stb r2,17(sp) + 3f60: d9800485 stb r6,18(sp) + 3f64: d8000405 stb zero,16(sp) + 3f68: 003e3206 br 3834 <___vfprintf_internal_r+0xa38> + 3f6c: 01800074 movhi r6,1 + 3f70: 3180da04 addi r6,r6,872 + 3f74: d9814415 stw r6,1296(sp) + 3f78: 003fe606 br 3f14 <___vfprintf_internal_r+0x1118> + 3f7c: 00800ac4 movi r2,43 + 3f80: d8800405 stb r2,16(sp) + 3f84: b8c00007 ldb r3,0(r23) + 3f88: 003c1b06 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3f8c: d8814c17 ldw r2,1328(sp) + 3f90: b8c00007 ldb r3,0(r23) + 3f94: 10800054 ori r2,r2,1 + 3f98: d8814c15 stw r2,1328(sp) + 3f9c: 003c1606 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3fa0: d8800407 ldb r2,16(sp) + 3fa4: 10004c1e bne r2,zero,40d8 <___vfprintf_internal_r+0x12dc> + 3fa8: 00800804 movi r2,32 + 3fac: d8800405 stb r2,16(sp) + 3fb0: b8c00007 ldb r3,0(r23) + 3fb4: 003c1006 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3fb8: d9814c17 ldw r6,1328(sp) + 3fbc: b8c00007 ldb r3,0(r23) + 3fc0: 31800214 ori r6,r6,8 + 3fc4: d9814c15 stw r6,1328(sp) + 3fc8: 003c0b06 br 2ff8 <___vfprintf_internal_r+0x1fc> + 3fcc: 0009883a mov r4,zero + 3fd0: 04000244 movi r16,9 + 3fd4: 01400284 movi r5,10 + 3fd8: d9c15115 stw r7,1348(sp) + 3fdc: 0002c240 call 2c24 <__mulsi3> + 3fe0: b9000007 ldb r4,0(r23) + 3fe4: d8c14d17 ldw r3,1332(sp) + 3fe8: bdc00044 addi r23,r23,1 + 3fec: d9014d15 stw r4,1332(sp) + 3ff0: d9414d17 ldw r5,1332(sp) + 3ff4: 1885883a add r2,r3,r2 + 3ff8: 113ff404 addi r4,r2,-48 + 3ffc: 28bff404 addi r2,r5,-48 + 4000: d9c15117 ldw r7,1348(sp) + 4004: 80bff32e bgeu r16,r2,3fd4 <___vfprintf_internal_r+0x11d8> + 4008: d9014a15 stw r4,1320(sp) + 400c: 003bfc06 br 3000 <___vfprintf_internal_r+0x204> + 4010: d8814c17 ldw r2,1328(sp) + 4014: b8c00007 ldb r3,0(r23) + 4018: 10802014 ori r2,r2,128 + 401c: d8814c15 stw r2,1328(sp) + 4020: 003bf506 br 2ff8 <___vfprintf_internal_r+0x1fc> + 4024: b8c00007 ldb r3,0(r23) + 4028: 00800a84 movi r2,42 + 402c: bdc00044 addi r23,r23,1 + 4030: 18831826 beq r3,r2,4c94 <___vfprintf_internal_r+0x1e98> + 4034: d8c14d15 stw r3,1332(sp) + 4038: 18bff404 addi r2,r3,-48 + 403c: 00c00244 movi r3,9 + 4040: 18827b36 bltu r3,r2,4a30 <___vfprintf_internal_r+0x1c34> + 4044: 1821883a mov r16,r3 + 4048: 0009883a mov r4,zero + 404c: 01400284 movi r5,10 + 4050: d9c15115 stw r7,1348(sp) + 4054: 0002c240 call 2c24 <__mulsi3> + 4058: d9414d17 ldw r5,1332(sp) + 405c: b9800007 ldb r6,0(r23) + 4060: d9c15117 ldw r7,1348(sp) + 4064: 1145883a add r2,r2,r5 + 4068: 113ff404 addi r4,r2,-48 + 406c: 30bff404 addi r2,r6,-48 + 4070: d9814d15 stw r6,1332(sp) + 4074: bdc00044 addi r23,r23,1 + 4078: 80bff42e bgeu r16,r2,404c <___vfprintf_internal_r+0x1250> + 407c: 2027883a mov r19,r4 + 4080: 203bdf0e bge r4,zero,3000 <___vfprintf_internal_r+0x204> + 4084: 04ffffc4 movi r19,-1 + 4088: 003bdd06 br 3000 <___vfprintf_internal_r+0x204> + 408c: d8000405 stb zero,16(sp) + 4090: 39800017 ldw r6,0(r7) + 4094: 39c00104 addi r7,r7,4 + 4098: d9c14015 stw r7,1280(sp) + 409c: d9814115 stw r6,1284(sp) + 40a0: 3001c926 beq r6,zero,47c8 <___vfprintf_internal_r+0x19cc> + 40a4: 98000e16 blt r19,zero,40e0 <___vfprintf_internal_r+0x12e4> + 40a8: d9014117 ldw r4,1284(sp) + 40ac: 000b883a mov r5,zero + 40b0: 980d883a mov r6,r19 + 40b4: 0007f300 call 7f30 + 40b8: 10025926 beq r2,zero,4a20 <___vfprintf_internal_r+0x1c24> + 40bc: d8c14117 ldw r3,1284(sp) + 40c0: 10cfc83a sub r7,r2,r3 + 40c4: 99c19e16 blt r19,r7,4740 <___vfprintf_internal_r+0x1944> + 40c8: d9c14515 stw r7,1300(sp) + 40cc: 38000916 blt r7,zero,40f4 <___vfprintf_internal_r+0x12f8> + 40d0: d8014615 stw zero,1304(sp) + 40d4: 003deb06 br 3884 <___vfprintf_internal_r+0xa88> + 40d8: b8c00007 ldb r3,0(r23) + 40dc: 003bc606 br 2ff8 <___vfprintf_internal_r+0x1fc> + 40e0: d9014117 ldw r4,1284(sp) + 40e4: 0002d300 call 2d30 + 40e8: d8814515 stw r2,1300(sp) + 40ec: 100f883a mov r7,r2 + 40f0: 103ff70e bge r2,zero,40d0 <___vfprintf_internal_r+0x12d4> + 40f4: d8014515 stw zero,1300(sp) + 40f8: d8014615 stw zero,1304(sp) + 40fc: 003de106 br 3884 <___vfprintf_internal_r+0xa88> + 4100: 20c03fcc andi r3,r4,255 + 4104: 00800044 movi r2,1 + 4108: 18802d26 beq r3,r2,41c0 <___vfprintf_internal_r+0x13c4> + 410c: 18800e36 bltu r3,r2,4148 <___vfprintf_internal_r+0x134c> + 4110: 00800084 movi r2,2 + 4114: 1880fa26 beq r3,r2,4500 <___vfprintf_internal_r+0x1704> + 4118: 01000074 movhi r4,1 + 411c: 2100ea04 addi r4,r4,936 + 4120: 0002d300 call 2d30 + 4124: 100f883a mov r7,r2 + 4128: dcc14515 stw r19,1300(sp) + 412c: 9880010e bge r19,r2,4134 <___vfprintf_internal_r+0x1338> + 4130: d8814515 stw r2,1300(sp) + 4134: 00800074 movhi r2,1 + 4138: 1080ea04 addi r2,r2,936 + 413c: dcc14615 stw r19,1304(sp) + 4140: d8814115 stw r2,1284(sp) + 4144: 003dcf06 br 3884 <___vfprintf_internal_r+0xa88> + 4148: d9401904 addi r5,sp,100 + 414c: dd000f04 addi r20,sp,60 + 4150: d9414115 stw r5,1284(sp) + 4154: 880a977a slli r5,r17,29 + 4158: d9814117 ldw r6,1284(sp) + 415c: 8004d0fa srli r2,r16,3 + 4160: 8806d0fa srli r3,r17,3 + 4164: 810001cc andi r4,r16,7 + 4168: 2884b03a or r2,r5,r2 + 416c: 31bfffc4 addi r6,r6,-1 + 4170: 21000c04 addi r4,r4,48 + 4174: d9814115 stw r6,1284(sp) + 4178: 10cab03a or r5,r2,r3 + 417c: 31000005 stb r4,0(r6) + 4180: 1021883a mov r16,r2 + 4184: 1823883a mov r17,r3 + 4188: 283ff21e bne r5,zero,4154 <___vfprintf_internal_r+0x1358> + 418c: d8c14c17 ldw r3,1328(sp) + 4190: 1880004c andi r2,r3,1 + 4194: 1005003a cmpeq r2,r2,zero + 4198: 103db31e bne r2,zero,3868 <___vfprintf_internal_r+0xa6c> + 419c: 20803fcc andi r2,r4,255 + 41a0: 1080201c xori r2,r2,128 + 41a4: 10bfe004 addi r2,r2,-128 + 41a8: 00c00c04 movi r3,48 + 41ac: 10fdae26 beq r2,r3,3868 <___vfprintf_internal_r+0xa6c> + 41b0: 31bfffc4 addi r6,r6,-1 + 41b4: d9814115 stw r6,1284(sp) + 41b8: 30c00005 stb r3,0(r6) + 41bc: 003daa06 br 3868 <___vfprintf_internal_r+0xa6c> + 41c0: 88800068 cmpgeui r2,r17,1 + 41c4: 10002c1e bne r2,zero,4278 <___vfprintf_internal_r+0x147c> + 41c8: 8800021e bne r17,zero,41d4 <___vfprintf_internal_r+0x13d8> + 41cc: 00800244 movi r2,9 + 41d0: 14002936 bltu r2,r16,4278 <___vfprintf_internal_r+0x147c> + 41d4: d90018c4 addi r4,sp,99 + 41d8: dd000f04 addi r20,sp,60 + 41dc: d9014115 stw r4,1284(sp) + 41e0: d9014117 ldw r4,1284(sp) + 41e4: 80800c04 addi r2,r16,48 + 41e8: 20800005 stb r2,0(r4) + 41ec: 003d9e06 br 3868 <___vfprintf_internal_r+0xa6c> + 41f0: dc400d17 ldw r17,52(sp) + 41f4: 07000074 movhi fp,1 + 41f8: e700f184 addi fp,fp,966 + 41fc: 9425883a add r18,r18,r16 + 4200: 8c400044 addi r17,r17,1 + 4204: 008001c4 movi r2,7 + 4208: 1f000015 stw fp,0(r3) + 420c: 1c000115 stw r16,4(r3) + 4210: dc800e15 stw r18,56(sp) + 4214: dc400d15 stw r17,52(sp) + 4218: 147ddc16 blt r2,r17,398c <___vfprintf_internal_r+0xb90> + 421c: 18c00204 addi r3,r3,8 + 4220: 003c7406 br 33f4 <___vfprintf_internal_r+0x5f8> + 4224: 01000084 movi r4,2 + 4228: d8000405 stb zero,16(sp) + 422c: 003d8106 br 3834 <___vfprintf_internal_r+0xa38> + 4230: d9814c17 ldw r6,1328(sp) + 4234: 30c4703a and r2,r6,r3 + 4238: 1005003a cmpeq r2,r2,zero + 423c: 103cb326 beq r2,zero,350c <___vfprintf_internal_r+0x710> + 4240: d9014117 ldw r4,1284(sp) + 4244: 94800044 addi r18,r18,1 + 4248: 8c400044 addi r17,r17,1 + 424c: 008001c4 movi r2,7 + 4250: a9000015 stw r4,0(r21) + 4254: a8c00115 stw r3,4(r21) + 4258: dc800e15 stw r18,56(sp) + 425c: dc400d15 stw r17,52(sp) + 4260: 147e6016 blt r2,r17,3be4 <___vfprintf_internal_r+0xde8> + 4264: acc00204 addi r19,r21,8 + 4268: 003cd106 br 35b0 <___vfprintf_internal_r+0x7b4> + 426c: 07000074 movhi fp,1 + 4270: e700f184 addi fp,fp,966 + 4274: 003c4906 br 339c <___vfprintf_internal_r+0x5a0> + 4278: dd000f04 addi r20,sp,60 + 427c: dc801904 addi r18,sp,100 + 4280: 8009883a mov r4,r16 + 4284: 880b883a mov r5,r17 + 4288: 01800284 movi r6,10 + 428c: 000f883a mov r7,zero + 4290: 000a6a80 call a6a8 <__umoddi3> + 4294: 12000c04 addi r8,r2,48 + 4298: 94bfffc4 addi r18,r18,-1 + 429c: 8009883a mov r4,r16 + 42a0: 880b883a mov r5,r17 + 42a4: 01800284 movi r6,10 + 42a8: 000f883a mov r7,zero + 42ac: 92000005 stb r8,0(r18) + 42b0: 000a03c0 call a03c <__udivdi3> + 42b4: 1009883a mov r4,r2 + 42b8: 1021883a mov r16,r2 + 42bc: 18800068 cmpgeui r2,r3,1 + 42c0: 1823883a mov r17,r3 + 42c4: 103fee1e bne r2,zero,4280 <___vfprintf_internal_r+0x1484> + 42c8: 1800021e bne r3,zero,42d4 <___vfprintf_internal_r+0x14d8> + 42cc: 00800244 movi r2,9 + 42d0: 113feb36 bltu r2,r4,4280 <___vfprintf_internal_r+0x1484> + 42d4: 94bfffc4 addi r18,r18,-1 + 42d8: dc814115 stw r18,1284(sp) + 42dc: 003fc006 br 41e0 <___vfprintf_internal_r+0x13e4> + 42e0: d9014c17 ldw r4,1328(sp) + 42e4: 2080004c andi r2,r4,1 + 42e8: 10009a1e bne r2,zero,4554 <___vfprintf_internal_r+0x1758> + 42ec: d9401904 addi r5,sp,100 + 42f0: dd000f04 addi r20,sp,60 + 42f4: d9414115 stw r5,1284(sp) + 42f8: 003d5b06 br 3868 <___vfprintf_internal_r+0xa6c> + 42fc: d9014f17 ldw r4,1340(sp) + 4300: b00b883a mov r5,r22 + 4304: d9800c04 addi r6,sp,48 + 4308: 0002da40 call 2da4 <__sprint_r> + 430c: 103c731e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 4310: dc800e17 ldw r18,56(sp) + 4314: d8c01904 addi r3,sp,100 + 4318: 003cf906 br 3700 <___vfprintf_internal_r+0x904> + 431c: d8c14c17 ldw r3,1328(sp) + 4320: 1880040c andi r2,r3,16 + 4324: 1000711e bne r2,zero,44ec <___vfprintf_internal_r+0x16f0> + 4328: d9014c17 ldw r4,1328(sp) + 432c: 2080100c andi r2,r4,64 + 4330: 10006e26 beq r2,zero,44ec <___vfprintf_internal_r+0x16f0> + 4334: 3c00000b ldhu r16,0(r7) + 4338: 0023883a mov r17,zero + 433c: 39c00104 addi r7,r7,4 + 4340: d9c14015 stw r7,1280(sp) + 4344: 003efa06 br 3f30 <___vfprintf_internal_r+0x1134> + 4348: dc400d17 ldw r17,52(sp) + 434c: 07000074 movhi fp,1 + 4350: e700f184 addi fp,fp,966 + 4354: 9425883a add r18,r18,r16 + 4358: 8c400044 addi r17,r17,1 + 435c: 008001c4 movi r2,7 + 4360: 1f000015 stw fp,0(r3) + 4364: 1c000115 stw r16,4(r3) + 4368: dc800e15 stw r18,56(sp) + 436c: dc400d15 stw r17,52(sp) + 4370: 147d7016 blt r2,r17,3934 <___vfprintf_internal_r+0xb38> + 4374: 18c00204 addi r3,r3,8 + 4378: 003d7506 br 3950 <___vfprintf_internal_r+0xb54> + 437c: dc800e17 ldw r18,56(sp) + 4380: dc400d17 ldw r17,52(sp) + 4384: 07000074 movhi fp,1 + 4388: e700f584 addi fp,fp,982 + 438c: 003bba06 br 3278 <___vfprintf_internal_r+0x47c> + 4390: d9014f17 ldw r4,1340(sp) + 4394: b00b883a mov r5,r22 + 4398: d9800c04 addi r6,sp,48 + 439c: 0002da40 call 2da4 <__sprint_r> + 43a0: 103c4e1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 43a4: dc800e17 ldw r18,56(sp) + 43a8: d8c01904 addi r3,sp,100 + 43ac: 003ce306 br 373c <___vfprintf_internal_r+0x940> + 43b0: 3c000017 ldw r16,0(r7) + 43b4: 0009883a mov r4,zero + 43b8: 39c00104 addi r7,r7,4 + 43bc: 0023883a mov r17,zero + 43c0: d9c14015 stw r7,1280(sp) + 43c4: d8000405 stb zero,16(sp) + 43c8: 003d1a06 br 3834 <___vfprintf_internal_r+0xa38> + 43cc: 38800017 ldw r2,0(r7) + 43d0: 39c00104 addi r7,r7,4 + 43d4: d9c14015 stw r7,1280(sp) + 43d8: 1023d7fa srai r17,r2,31 + 43dc: 1021883a mov r16,r2 + 43e0: 003d1206 br 382c <___vfprintf_internal_r+0xa30> + 43e4: 3c000017 ldw r16,0(r7) + 43e8: 01000044 movi r4,1 + 43ec: 39c00104 addi r7,r7,4 + 43f0: 0023883a mov r17,zero + 43f4: d9c14015 stw r7,1280(sp) + 43f8: d8000405 stb zero,16(sp) + 43fc: 003d0d06 br 3834 <___vfprintf_internal_r+0xa38> + 4400: 00800074 movhi r2,1 + 4404: 1080f104 addi r2,r2,964 + 4408: 94800044 addi r18,r18,1 + 440c: 8c400044 addi r17,r17,1 + 4410: a8800015 stw r2,0(r21) + 4414: 00c00044 movi r3,1 + 4418: 008001c4 movi r2,7 + 441c: a8c00115 stw r3,4(r21) + 4420: dc800e15 stw r18,56(sp) + 4424: dc400d15 stw r17,52(sp) + 4428: 1440ca16 blt r2,r17,4754 <___vfprintf_internal_r+0x1958> + 442c: a8c00204 addi r3,r21,8 + 4430: 2000061e bne r4,zero,444c <___vfprintf_internal_r+0x1650> + 4434: d9414717 ldw r5,1308(sp) + 4438: 2800041e bne r5,zero,444c <___vfprintf_internal_r+0x1650> + 443c: d9814c17 ldw r6,1328(sp) + 4440: 3080004c andi r2,r6,1 + 4444: 1005003a cmpeq r2,r2,zero + 4448: 103bea1e bne r2,zero,33f4 <___vfprintf_internal_r+0x5f8> + 444c: 00800044 movi r2,1 + 4450: dc400d17 ldw r17,52(sp) + 4454: 18800115 stw r2,4(r3) + 4458: d8814917 ldw r2,1316(sp) + 445c: 94800044 addi r18,r18,1 + 4460: 8c400044 addi r17,r17,1 + 4464: 18800015 stw r2,0(r3) + 4468: 008001c4 movi r2,7 + 446c: dc800e15 stw r18,56(sp) + 4470: dc400d15 stw r17,52(sp) + 4474: 1440ca16 blt r2,r17,47a0 <___vfprintf_internal_r+0x19a4> + 4478: 18c00204 addi r3,r3,8 + 447c: 0121c83a sub r16,zero,r4 + 4480: 0400500e bge zero,r16,45c4 <___vfprintf_internal_r+0x17c8> + 4484: 00800404 movi r2,16 + 4488: 1400800e bge r2,r16,468c <___vfprintf_internal_r+0x1890> + 448c: 1027883a mov r19,r2 + 4490: 07000074 movhi fp,1 + 4494: e700f184 addi fp,fp,966 + 4498: 050001c4 movi r20,7 + 449c: 00000306 br 44ac <___vfprintf_internal_r+0x16b0> + 44a0: 18c00204 addi r3,r3,8 + 44a4: 843ffc04 addi r16,r16,-16 + 44a8: 9c007a0e bge r19,r16,4694 <___vfprintf_internal_r+0x1898> + 44ac: 94800404 addi r18,r18,16 + 44b0: 8c400044 addi r17,r17,1 + 44b4: 1f000015 stw fp,0(r3) + 44b8: 1cc00115 stw r19,4(r3) + 44bc: dc800e15 stw r18,56(sp) + 44c0: dc400d15 stw r17,52(sp) + 44c4: a47ff60e bge r20,r17,44a0 <___vfprintf_internal_r+0x16a4> + 44c8: d9014f17 ldw r4,1340(sp) + 44cc: b00b883a mov r5,r22 + 44d0: d9800c04 addi r6,sp,48 + 44d4: 0002da40 call 2da4 <__sprint_r> + 44d8: 103c001e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 44dc: dc800e17 ldw r18,56(sp) + 44e0: dc400d17 ldw r17,52(sp) + 44e4: d8c01904 addi r3,sp,100 + 44e8: 003fee06 br 44a4 <___vfprintf_internal_r+0x16a8> + 44ec: 3c000017 ldw r16,0(r7) + 44f0: 0023883a mov r17,zero + 44f4: 39c00104 addi r7,r7,4 + 44f8: d9c14015 stw r7,1280(sp) + 44fc: 003e8c06 br 3f30 <___vfprintf_internal_r+0x1134> + 4500: d9401904 addi r5,sp,100 + 4504: dd000f04 addi r20,sp,60 + 4508: d9414115 stw r5,1284(sp) + 450c: d9814417 ldw r6,1296(sp) + 4510: 880a973a slli r5,r17,28 + 4514: 8004d13a srli r2,r16,4 + 4518: 810003cc andi r4,r16,15 + 451c: 3109883a add r4,r6,r4 + 4520: 2884b03a or r2,r5,r2 + 4524: 21400003 ldbu r5,0(r4) + 4528: d9014117 ldw r4,1284(sp) + 452c: 8806d13a srli r3,r17,4 + 4530: 1021883a mov r16,r2 + 4534: 213fffc4 addi r4,r4,-1 + 4538: d9014115 stw r4,1284(sp) + 453c: d9814117 ldw r6,1284(sp) + 4540: 10c8b03a or r4,r2,r3 + 4544: 1823883a mov r17,r3 + 4548: 31400005 stb r5,0(r6) + 454c: 203fef1e bne r4,zero,450c <___vfprintf_internal_r+0x1710> + 4550: 003cc506 br 3868 <___vfprintf_internal_r+0xa6c> + 4554: 00800c04 movi r2,48 + 4558: d98018c4 addi r6,sp,99 + 455c: dd000f04 addi r20,sp,60 + 4560: d88018c5 stb r2,99(sp) + 4564: d9814115 stw r6,1284(sp) + 4568: 003cbf06 br 3868 <___vfprintf_internal_r+0xa6c> + 456c: dc400d17 ldw r17,52(sp) + 4570: 07000074 movhi fp,1 + 4574: e700f584 addi fp,fp,982 + 4578: 003bc106 br 3480 <___vfprintf_internal_r+0x684> + 457c: d9414c17 ldw r5,1328(sp) + 4580: 2880040c andi r2,r5,16 + 4584: 10007c26 beq r2,zero,4778 <___vfprintf_internal_r+0x197c> + 4588: 38800017 ldw r2,0(r7) + 458c: 39c00104 addi r7,r7,4 + 4590: d9c14015 stw r7,1280(sp) + 4594: d9814b17 ldw r6,1324(sp) + 4598: d9c14017 ldw r7,1280(sp) + 459c: 11800015 stw r6,0(r2) + 45a0: 003a7206 br 2f6c <___vfprintf_internal_r+0x170> + 45a4: d9014f17 ldw r4,1340(sp) + 45a8: b00b883a mov r5,r22 + 45ac: d9800c04 addi r6,sp,48 + 45b0: 0002da40 call 2da4 <__sprint_r> + 45b4: 103bc91e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 45b8: dc800e17 ldw r18,56(sp) + 45bc: dc400d17 ldw r17,52(sp) + 45c0: d8c01904 addi r3,sp,100 + 45c4: d9014717 ldw r4,1308(sp) + 45c8: d9414117 ldw r5,1284(sp) + 45cc: 8c400044 addi r17,r17,1 + 45d0: 9125883a add r18,r18,r4 + 45d4: 008001c4 movi r2,7 + 45d8: 19400015 stw r5,0(r3) + 45dc: 19000115 stw r4,4(r3) + 45e0: dc800e15 stw r18,56(sp) + 45e4: dc400d15 stw r17,52(sp) + 45e8: 147ce816 blt r2,r17,398c <___vfprintf_internal_r+0xb90> + 45ec: 18c00204 addi r3,r3,8 + 45f0: 003b8006 br 33f4 <___vfprintf_internal_r+0x5f8> + 45f4: 38c00017 ldw r3,0(r7) + 45f8: 39000204 addi r4,r7,8 + 45fc: d9014015 stw r4,1280(sp) + 4600: d8c14215 stw r3,1288(sp) + 4604: 39c00117 ldw r7,4(r7) + 4608: d9c14315 stw r7,1292(sp) + 460c: 003e1a06 br 3e78 <___vfprintf_internal_r+0x107c> + 4610: 0005883a mov r2,zero + 4614: 1409c83a sub r4,r2,r16 + 4618: 1105803a cmpltu r2,r2,r4 + 461c: 044bc83a sub r5,zero,r17 + 4620: 2885c83a sub r2,r5,r2 + 4624: 2021883a mov r16,r4 + 4628: 1023883a mov r17,r2 + 462c: 01000044 movi r4,1 + 4630: 00800b44 movi r2,45 + 4634: d8800405 stb r2,16(sp) + 4638: 003c7e06 br 3834 <___vfprintf_internal_r+0xa38> + 463c: d9014f17 ldw r4,1340(sp) + 4640: b00b883a mov r5,r22 + 4644: d9800c04 addi r6,sp,48 + 4648: 0002da40 call 2da4 <__sprint_r> + 464c: 103ba31e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 4650: dc800e17 ldw r18,56(sp) + 4654: dc400d17 ldw r17,52(sp) + 4658: d9000517 ldw r4,20(sp) + 465c: d9401904 addi r5,sp,100 + 4660: 003da106 br 3ce8 <___vfprintf_internal_r+0xeec> + 4664: d9014f17 ldw r4,1340(sp) + 4668: b00b883a mov r5,r22 + 466c: d9800c04 addi r6,sp,48 + 4670: 0002da40 call 2da4 <__sprint_r> + 4674: 103b991e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 4678: dc800e17 ldw r18,56(sp) + 467c: dc400d17 ldw r17,52(sp) + 4680: d9000517 ldw r4,20(sp) + 4684: d8c01904 addi r3,sp,100 + 4688: 003d8b06 br 3cb8 <___vfprintf_internal_r+0xebc> + 468c: 07000074 movhi fp,1 + 4690: e700f184 addi fp,fp,966 + 4694: 9425883a add r18,r18,r16 + 4698: 8c400044 addi r17,r17,1 + 469c: 008001c4 movi r2,7 + 46a0: 1f000015 stw fp,0(r3) + 46a4: 1c000115 stw r16,4(r3) + 46a8: dc800e15 stw r18,56(sp) + 46ac: dc400d15 stw r17,52(sp) + 46b0: 147fbc16 blt r2,r17,45a4 <___vfprintf_internal_r+0x17a8> + 46b4: 18c00204 addi r3,r3,8 + 46b8: 003fc206 br 45c4 <___vfprintf_internal_r+0x17c8> + 46bc: d9014f17 ldw r4,1340(sp) + 46c0: b00b883a mov r5,r22 + 46c4: d9800c04 addi r6,sp,48 + 46c8: 0002da40 call 2da4 <__sprint_r> + 46cc: 103b831e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 46d0: dc800e17 ldw r18,56(sp) + 46d4: d9000517 ldw r4,20(sp) + 46d8: d8c01904 addi r3,sp,100 + 46dc: 003cfc06 br 3ad0 <___vfprintf_internal_r+0xcd4> + 46e0: 07000074 movhi fp,1 + 46e4: e700f184 addi fp,fp,966 + 46e8: 003bde06 br 3664 <___vfprintf_internal_r+0x868> + 46ec: 00800074 movhi r2,1 + 46f0: 1080e004 addi r2,r2,896 + 46f4: d8814115 stw r2,1284(sp) + 46f8: 003def06 br 3eb8 <___vfprintf_internal_r+0x10bc> + 46fc: d9014217 ldw r4,1288(sp) + 4700: d9414317 ldw r5,1292(sp) + 4704: 00098ec0 call 98ec <__isnand> + 4708: 10003926 beq r2,zero,47f0 <___vfprintf_internal_r+0x19f4> + 470c: d9414d17 ldw r5,1332(sp) + 4710: 008011c4 movi r2,71 + 4714: 1140ce16 blt r2,r5,4a50 <___vfprintf_internal_r+0x1c54> + 4718: 01800074 movhi r6,1 + 471c: 3180e104 addi r6,r6,900 + 4720: d9814115 stw r6,1284(sp) + 4724: 003de406 br 3eb8 <___vfprintf_internal_r+0x10bc> + 4728: d9014c17 ldw r4,1328(sp) + 472c: bdc00044 addi r23,r23,1 + 4730: b8c00007 ldb r3,0(r23) + 4734: 21000814 ori r4,r4,32 + 4738: d9014c15 stw r4,1328(sp) + 473c: 003a2e06 br 2ff8 <___vfprintf_internal_r+0x1fc> + 4740: dcc14515 stw r19,1300(sp) + 4744: 98011016 blt r19,zero,4b88 <___vfprintf_internal_r+0x1d8c> + 4748: 980f883a mov r7,r19 + 474c: d8014615 stw zero,1304(sp) + 4750: 003c4c06 br 3884 <___vfprintf_internal_r+0xa88> + 4754: d9014f17 ldw r4,1340(sp) + 4758: b00b883a mov r5,r22 + 475c: d9800c04 addi r6,sp,48 + 4760: 0002da40 call 2da4 <__sprint_r> + 4764: 103b5d1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 4768: dc800e17 ldw r18,56(sp) + 476c: d9000517 ldw r4,20(sp) + 4770: d8c01904 addi r3,sp,100 + 4774: 003f2e06 br 4430 <___vfprintf_internal_r+0x1634> + 4778: d8c14c17 ldw r3,1328(sp) + 477c: 1880100c andi r2,r3,64 + 4780: 1000a026 beq r2,zero,4a04 <___vfprintf_internal_r+0x1c08> + 4784: 38800017 ldw r2,0(r7) + 4788: 39c00104 addi r7,r7,4 + 478c: d9c14015 stw r7,1280(sp) + 4790: d9014b17 ldw r4,1324(sp) + 4794: d9c14017 ldw r7,1280(sp) + 4798: 1100000d sth r4,0(r2) + 479c: 0039f306 br 2f6c <___vfprintf_internal_r+0x170> + 47a0: d9014f17 ldw r4,1340(sp) + 47a4: b00b883a mov r5,r22 + 47a8: d9800c04 addi r6,sp,48 + 47ac: 0002da40 call 2da4 <__sprint_r> + 47b0: 103b4a1e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 47b4: dc800e17 ldw r18,56(sp) + 47b8: dc400d17 ldw r17,52(sp) + 47bc: d9000517 ldw r4,20(sp) + 47c0: d8c01904 addi r3,sp,100 + 47c4: 003f2d06 br 447c <___vfprintf_internal_r+0x1680> + 47c8: 00800184 movi r2,6 + 47cc: 14c09a36 bltu r2,r19,4a38 <___vfprintf_internal_r+0x1c3c> + 47d0: dcc14515 stw r19,1300(sp) + 47d4: 9800010e bge r19,zero,47dc <___vfprintf_internal_r+0x19e0> + 47d8: d8014515 stw zero,1300(sp) + 47dc: 00800074 movhi r2,1 + 47e0: 1080e304 addi r2,r2,908 + 47e4: 980f883a mov r7,r19 + 47e8: d8814115 stw r2,1284(sp) + 47ec: 003a7206 br 31b8 <___vfprintf_internal_r+0x3bc> + 47f0: 00bfffc4 movi r2,-1 + 47f4: 9880e226 beq r19,r2,4b80 <___vfprintf_internal_r+0x1d84> + 47f8: d9414d17 ldw r5,1332(sp) + 47fc: 008019c4 movi r2,103 + 4800: 2880dc26 beq r5,r2,4b74 <___vfprintf_internal_r+0x1d78> + 4804: 008011c4 movi r2,71 + 4808: 2880da26 beq r5,r2,4b74 <___vfprintf_internal_r+0x1d78> + 480c: d9414c17 ldw r5,1328(sp) + 4810: d9014317 ldw r4,1292(sp) + 4814: d9814217 ldw r6,1288(sp) + 4818: 29404014 ori r5,r5,256 + 481c: d9414c15 stw r5,1328(sp) + 4820: 2000cc16 blt r4,zero,4b54 <___vfprintf_internal_r+0x1d58> + 4824: 3021883a mov r16,r6 + 4828: 2023883a mov r17,r4 + 482c: 0039883a mov fp,zero + 4830: d9414d17 ldw r5,1332(sp) + 4834: 00801984 movi r2,102 + 4838: 2880b726 beq r5,r2,4b18 <___vfprintf_internal_r+0x1d1c> + 483c: 00801184 movi r2,70 + 4840: 2880b526 beq r5,r2,4b18 <___vfprintf_internal_r+0x1d1c> + 4844: 00801944 movi r2,101 + 4848: 2880c826 beq r5,r2,4b6c <___vfprintf_internal_r+0x1d70> + 484c: 00801144 movi r2,69 + 4850: 2880c626 beq r5,r2,4b6c <___vfprintf_internal_r+0x1d70> + 4854: 9829883a mov r20,r19 + 4858: d9014f17 ldw r4,1340(sp) + 485c: d8800504 addi r2,sp,20 + 4860: 880d883a mov r6,r17 + 4864: d8800115 stw r2,4(sp) + 4868: d8c00604 addi r3,sp,24 + 486c: d8800704 addi r2,sp,28 + 4870: 800b883a mov r5,r16 + 4874: 01c00084 movi r7,2 + 4878: d8c00215 stw r3,8(sp) + 487c: d8800315 stw r2,12(sp) + 4880: dd000015 stw r20,0(sp) + 4884: 00050640 call 5064 <_dtoa_r> + 4888: d9814d17 ldw r6,1332(sp) + 488c: d8814115 stw r2,1284(sp) + 4890: 008019c4 movi r2,103 + 4894: 30809526 beq r6,r2,4aec <___vfprintf_internal_r+0x1cf0> + 4898: d8c14d17 ldw r3,1332(sp) + 489c: 008011c4 movi r2,71 + 48a0: 18809226 beq r3,r2,4aec <___vfprintf_internal_r+0x1cf0> + 48a4: d9414117 ldw r5,1284(sp) + 48a8: d9814d17 ldw r6,1332(sp) + 48ac: 00801984 movi r2,102 + 48b0: 2d25883a add r18,r5,r20 + 48b4: 30808626 beq r6,r2,4ad0 <___vfprintf_internal_r+0x1cd4> + 48b8: 00801184 movi r2,70 + 48bc: 30808426 beq r6,r2,4ad0 <___vfprintf_internal_r+0x1cd4> + 48c0: 000d883a mov r6,zero + 48c4: 000f883a mov r7,zero + 48c8: 880b883a mov r5,r17 + 48cc: 8009883a mov r4,r16 + 48d0: 000b8280 call b828 <__eqdf2> + 48d4: 1000751e bne r2,zero,4aac <___vfprintf_internal_r+0x1cb0> + 48d8: 9005883a mov r2,r18 + 48dc: dc800715 stw r18,28(sp) + 48e0: d9014117 ldw r4,1284(sp) + 48e4: d9414d17 ldw r5,1332(sp) + 48e8: 00c019c4 movi r3,103 + 48ec: 1125c83a sub r18,r2,r4 + 48f0: 28c06826 beq r5,r3,4a94 <___vfprintf_internal_r+0x1c98> + 48f4: 008011c4 movi r2,71 + 48f8: 28806626 beq r5,r2,4a94 <___vfprintf_internal_r+0x1c98> + 48fc: d9000517 ldw r4,20(sp) + 4900: d8c14d17 ldw r3,1332(sp) + 4904: 00801944 movi r2,101 + 4908: 10c05516 blt r2,r3,4a60 <___vfprintf_internal_r+0x1c64> + 490c: 213fffc4 addi r4,r4,-1 + 4910: d9000515 stw r4,20(sp) + 4914: d8c00805 stb r3,32(sp) + 4918: 2021883a mov r16,r4 + 491c: 2000c116 blt r4,zero,4c24 <___vfprintf_internal_r+0x1e28> + 4920: 00800ac4 movi r2,43 + 4924: d8800845 stb r2,33(sp) + 4928: 00800244 movi r2,9 + 492c: 1400af0e bge r2,r16,4bec <___vfprintf_internal_r+0x1df0> + 4930: 1027883a mov r19,r2 + 4934: dc400b84 addi r17,sp,46 + 4938: 8009883a mov r4,r16 + 493c: 01400284 movi r5,10 + 4940: 0002bb40 call 2bb4 <__modsi3> + 4944: 10800c04 addi r2,r2,48 + 4948: 8c7fffc4 addi r17,r17,-1 + 494c: 8009883a mov r4,r16 + 4950: 01400284 movi r5,10 + 4954: 88800005 stb r2,0(r17) + 4958: 0002b540 call 2b54 <__divsi3> + 495c: 1021883a mov r16,r2 + 4960: 98bff516 blt r19,r2,4938 <___vfprintf_internal_r+0x1b3c> + 4964: 10c00c04 addi r3,r2,48 + 4968: d88009c4 addi r2,sp,39 + 496c: 108001c4 addi r2,r2,7 + 4970: 897fffc4 addi r5,r17,-1 + 4974: 88ffffc5 stb r3,-1(r17) + 4978: 2880a72e bgeu r5,r2,4c18 <___vfprintf_internal_r+0x1e1c> + 497c: 1009883a mov r4,r2 + 4980: d9800804 addi r6,sp,32 + 4984: d8c00884 addi r3,sp,34 + 4988: 28800003 ldbu r2,0(r5) + 498c: 29400044 addi r5,r5,1 + 4990: 18800005 stb r2,0(r3) + 4994: 18c00044 addi r3,r3,1 + 4998: 293ffb36 bltu r5,r4,4988 <___vfprintf_internal_r+0x1b8c> + 499c: 1987c83a sub r3,r3,r6 + 49a0: 00800044 movi r2,1 + 49a4: d8c14815 stw r3,1312(sp) + 49a8: 90cf883a add r7,r18,r3 + 49ac: 1480960e bge r2,r18,4c08 <___vfprintf_internal_r+0x1e0c> + 49b0: 39c00044 addi r7,r7,1 + 49b4: d9c14515 stw r7,1300(sp) + 49b8: 38003416 blt r7,zero,4a8c <___vfprintf_internal_r+0x1c90> + 49bc: e0803fcc andi r2,fp,255 + 49c0: 1080201c xori r2,r2,128 + 49c4: 10bfe004 addi r2,r2,-128 + 49c8: 10004e26 beq r2,zero,4b04 <___vfprintf_internal_r+0x1d08> + 49cc: 00800b44 movi r2,45 + 49d0: dc814715 stw r18,1308(sp) + 49d4: d8014615 stw zero,1304(sp) + 49d8: d8800405 stb r2,16(sp) + 49dc: 003bab06 br 388c <___vfprintf_internal_r+0xa90> + 49e0: 00800b44 movi r2,45 + 49e4: d8800405 stb r2,16(sp) + 49e8: 003d2d06 br 3ea0 <___vfprintf_internal_r+0x10a4> + 49ec: d9014f17 ldw r4,1340(sp) + 49f0: b00b883a mov r5,r22 + 49f4: d9800c04 addi r6,sp,48 + 49f8: 0002da40 call 2da4 <__sprint_r> + 49fc: 103ab71e bne r2,zero,34dc <___vfprintf_internal_r+0x6e0> + 4a00: 003ab506 br 34d8 <___vfprintf_internal_r+0x6dc> + 4a04: 38800017 ldw r2,0(r7) + 4a08: 39c00104 addi r7,r7,4 + 4a0c: d9c14015 stw r7,1280(sp) + 4a10: d9414b17 ldw r5,1324(sp) + 4a14: d9c14017 ldw r7,1280(sp) + 4a18: 11400015 stw r5,0(r2) + 4a1c: 00395306 br 2f6c <___vfprintf_internal_r+0x170> + 4a20: 980f883a mov r7,r19 + 4a24: dcc14515 stw r19,1300(sp) + 4a28: d8014615 stw zero,1304(sp) + 4a2c: 003b9506 br 3884 <___vfprintf_internal_r+0xa88> + 4a30: 0027883a mov r19,zero + 4a34: 00397206 br 3000 <___vfprintf_internal_r+0x204> + 4a38: 00c00074 movhi r3,1 + 4a3c: 18c0e304 addi r3,r3,908 + 4a40: 100f883a mov r7,r2 + 4a44: d8814515 stw r2,1300(sp) + 4a48: d8c14115 stw r3,1284(sp) + 4a4c: 0039da06 br 31b8 <___vfprintf_internal_r+0x3bc> + 4a50: 00800074 movhi r2,1 + 4a54: 1080e204 addi r2,r2,904 + 4a58: d8814115 stw r2,1284(sp) + 4a5c: 003d1606 br 3eb8 <___vfprintf_internal_r+0x10bc> + 4a60: d9414d17 ldw r5,1332(sp) + 4a64: 00801984 movi r2,102 + 4a68: 28804926 beq r5,r2,4b90 <___vfprintf_internal_r+0x1d94> + 4a6c: 200f883a mov r7,r4 + 4a70: 24805716 blt r4,r18,4bd0 <___vfprintf_internal_r+0x1dd4> + 4a74: d9414c17 ldw r5,1328(sp) + 4a78: 2880004c andi r2,r5,1 + 4a7c: 10000126 beq r2,zero,4a84 <___vfprintf_internal_r+0x1c88> + 4a80: 21c00044 addi r7,r4,1 + 4a84: d9c14515 stw r7,1300(sp) + 4a88: 383fcc0e bge r7,zero,49bc <___vfprintf_internal_r+0x1bc0> + 4a8c: d8014515 stw zero,1300(sp) + 4a90: 003fca06 br 49bc <___vfprintf_internal_r+0x1bc0> + 4a94: d9000517 ldw r4,20(sp) + 4a98: 00bfff04 movi r2,-4 + 4a9c: 1100480e bge r2,r4,4bc0 <___vfprintf_internal_r+0x1dc4> + 4aa0: 99004716 blt r19,r4,4bc0 <___vfprintf_internal_r+0x1dc4> + 4aa4: d8c14d15 stw r3,1332(sp) + 4aa8: 003ff006 br 4a6c <___vfprintf_internal_r+0x1c70> + 4aac: d8800717 ldw r2,28(sp) + 4ab0: 14bf8b2e bgeu r2,r18,48e0 <___vfprintf_internal_r+0x1ae4> + 4ab4: 9007883a mov r3,r18 + 4ab8: 01000c04 movi r4,48 + 4abc: 11000005 stb r4,0(r2) + 4ac0: 10800044 addi r2,r2,1 + 4ac4: d8800715 stw r2,28(sp) + 4ac8: 18bffc1e bne r3,r2,4abc <___vfprintf_internal_r+0x1cc0> + 4acc: 003f8406 br 48e0 <___vfprintf_internal_r+0x1ae4> + 4ad0: d8814117 ldw r2,1284(sp) + 4ad4: 10c00007 ldb r3,0(r2) + 4ad8: 00800c04 movi r2,48 + 4adc: 18805b26 beq r3,r2,4c4c <___vfprintf_internal_r+0x1e50> + 4ae0: d9000517 ldw r4,20(sp) + 4ae4: 9125883a add r18,r18,r4 + 4ae8: 003f7506 br 48c0 <___vfprintf_internal_r+0x1ac4> + 4aec: d9014c17 ldw r4,1328(sp) + 4af0: 2080004c andi r2,r4,1 + 4af4: 1005003a cmpeq r2,r2,zero + 4af8: 103f6a26 beq r2,zero,48a4 <___vfprintf_internal_r+0x1aa8> + 4afc: d8800717 ldw r2,28(sp) + 4b00: 003f7706 br 48e0 <___vfprintf_internal_r+0x1ae4> + 4b04: d9c14515 stw r7,1300(sp) + 4b08: 38004d16 blt r7,zero,4c40 <___vfprintf_internal_r+0x1e44> + 4b0c: dc814715 stw r18,1308(sp) + 4b10: d8014615 stw zero,1304(sp) + 4b14: 003b5b06 br 3884 <___vfprintf_internal_r+0xa88> + 4b18: d9014f17 ldw r4,1340(sp) + 4b1c: d8800504 addi r2,sp,20 + 4b20: d8800115 stw r2,4(sp) + 4b24: d8c00604 addi r3,sp,24 + 4b28: d8800704 addi r2,sp,28 + 4b2c: 800b883a mov r5,r16 + 4b30: 880d883a mov r6,r17 + 4b34: 01c000c4 movi r7,3 + 4b38: d8c00215 stw r3,8(sp) + 4b3c: d8800315 stw r2,12(sp) + 4b40: dcc00015 stw r19,0(sp) + 4b44: 9829883a mov r20,r19 + 4b48: 00050640 call 5064 <_dtoa_r> + 4b4c: d8814115 stw r2,1284(sp) + 4b50: 003f5106 br 4898 <___vfprintf_internal_r+0x1a9c> + 4b54: d8c14217 ldw r3,1288(sp) + 4b58: d9014317 ldw r4,1292(sp) + 4b5c: 07000b44 movi fp,45 + 4b60: 1821883a mov r16,r3 + 4b64: 2460003c xorhi r17,r4,32768 + 4b68: 003f3106 br 4830 <___vfprintf_internal_r+0x1a34> + 4b6c: 9d000044 addi r20,r19,1 + 4b70: 003f3906 br 4858 <___vfprintf_internal_r+0x1a5c> + 4b74: 983f251e bne r19,zero,480c <___vfprintf_internal_r+0x1a10> + 4b78: 04c00044 movi r19,1 + 4b7c: 003f2306 br 480c <___vfprintf_internal_r+0x1a10> + 4b80: 04c00184 movi r19,6 + 4b84: 003f2106 br 480c <___vfprintf_internal_r+0x1a10> + 4b88: d8014515 stw zero,1300(sp) + 4b8c: 003eee06 br 4748 <___vfprintf_internal_r+0x194c> + 4b90: 200f883a mov r7,r4 + 4b94: 0100370e bge zero,r4,4c74 <___vfprintf_internal_r+0x1e78> + 4b98: 9800031e bne r19,zero,4ba8 <___vfprintf_internal_r+0x1dac> + 4b9c: d9814c17 ldw r6,1328(sp) + 4ba0: 3080004c andi r2,r6,1 + 4ba4: 103fb726 beq r2,zero,4a84 <___vfprintf_internal_r+0x1c88> + 4ba8: 20800044 addi r2,r4,1 + 4bac: 98a7883a add r19,r19,r2 + 4bb0: dcc14515 stw r19,1300(sp) + 4bb4: 980f883a mov r7,r19 + 4bb8: 983f800e bge r19,zero,49bc <___vfprintf_internal_r+0x1bc0> + 4bbc: 003fb306 br 4a8c <___vfprintf_internal_r+0x1c90> + 4bc0: d9814d17 ldw r6,1332(sp) + 4bc4: 31bfff84 addi r6,r6,-2 + 4bc8: d9814d15 stw r6,1332(sp) + 4bcc: 003f4c06 br 4900 <___vfprintf_internal_r+0x1b04> + 4bd0: 0100180e bge zero,r4,4c34 <___vfprintf_internal_r+0x1e38> + 4bd4: 00800044 movi r2,1 + 4bd8: 1485883a add r2,r2,r18 + 4bdc: d8814515 stw r2,1300(sp) + 4be0: 100f883a mov r7,r2 + 4be4: 103f750e bge r2,zero,49bc <___vfprintf_internal_r+0x1bc0> + 4be8: 003fa806 br 4a8c <___vfprintf_internal_r+0x1c90> + 4bec: 80c00c04 addi r3,r16,48 + 4bf0: 00800c04 movi r2,48 + 4bf4: d8c008c5 stb r3,35(sp) + 4bf8: d9800804 addi r6,sp,32 + 4bfc: d8c00904 addi r3,sp,36 + 4c00: d8800885 stb r2,34(sp) + 4c04: 003f6506 br 499c <___vfprintf_internal_r+0x1ba0> + 4c08: d9014c17 ldw r4,1328(sp) + 4c0c: 2084703a and r2,r4,r2 + 4c10: 103f9c26 beq r2,zero,4a84 <___vfprintf_internal_r+0x1c88> + 4c14: 003f6606 br 49b0 <___vfprintf_internal_r+0x1bb4> + 4c18: d9800804 addi r6,sp,32 + 4c1c: d8c00884 addi r3,sp,34 + 4c20: 003f5e06 br 499c <___vfprintf_internal_r+0x1ba0> + 4c24: 00800b44 movi r2,45 + 4c28: 0121c83a sub r16,zero,r4 + 4c2c: d8800845 stb r2,33(sp) + 4c30: 003f3d06 br 4928 <___vfprintf_internal_r+0x1b2c> + 4c34: 00800084 movi r2,2 + 4c38: 1105c83a sub r2,r2,r4 + 4c3c: 003fe606 br 4bd8 <___vfprintf_internal_r+0x1ddc> + 4c40: d8014515 stw zero,1300(sp) + 4c44: dc814715 stw r18,1308(sp) + 4c48: 003fb106 br 4b10 <___vfprintf_internal_r+0x1d14> + 4c4c: 000d883a mov r6,zero + 4c50: 000f883a mov r7,zero + 4c54: 8009883a mov r4,r16 + 4c58: 880b883a mov r5,r17 + 4c5c: 000b8b00 call b8b0 <__nedf2> + 4c60: 103f9f26 beq r2,zero,4ae0 <___vfprintf_internal_r+0x1ce4> + 4c64: 00800044 movi r2,1 + 4c68: 1509c83a sub r4,r2,r20 + 4c6c: d9000515 stw r4,20(sp) + 4c70: 003f9b06 br 4ae0 <___vfprintf_internal_r+0x1ce4> + 4c74: 98000d1e bne r19,zero,4cac <___vfprintf_internal_r+0x1eb0> + 4c78: d8c14c17 ldw r3,1328(sp) + 4c7c: 1880004c andi r2,r3,1 + 4c80: 10000a1e bne r2,zero,4cac <___vfprintf_internal_r+0x1eb0> + 4c84: 01000044 movi r4,1 + 4c88: 200f883a mov r7,r4 + 4c8c: d9014515 stw r4,1300(sp) + 4c90: 003f4a06 br 49bc <___vfprintf_internal_r+0x1bc0> + 4c94: 3cc00017 ldw r19,0(r7) + 4c98: 39c00104 addi r7,r7,4 + 4c9c: 983d0e0e bge r19,zero,40d8 <___vfprintf_internal_r+0x12dc> + 4ca0: b8c00007 ldb r3,0(r23) + 4ca4: 04ffffc4 movi r19,-1 + 4ca8: 0038d306 br 2ff8 <___vfprintf_internal_r+0x1fc> + 4cac: 9cc00084 addi r19,r19,2 + 4cb0: dcc14515 stw r19,1300(sp) + 4cb4: 980f883a mov r7,r19 + 4cb8: 983f400e bge r19,zero,49bc <___vfprintf_internal_r+0x1bc0> + 4cbc: 003f7306 br 4a8c <___vfprintf_internal_r+0x1c90> + +00004cc0 <__vfprintf_internal>: + 4cc0: 00800074 movhi r2,1 + 4cc4: 10887e04 addi r2,r2,8696 + 4cc8: 2013883a mov r9,r4 + 4ccc: 11000017 ldw r4,0(r2) + 4cd0: 2805883a mov r2,r5 + 4cd4: 300f883a mov r7,r6 + 4cd8: 480b883a mov r5,r9 + 4cdc: 100d883a mov r6,r2 + 4ce0: 0002dfc1 jmpi 2dfc <___vfprintf_internal_r> + +00004ce4 <__swsetup_r>: + 4ce4: 00800074 movhi r2,1 + 4ce8: 10887e04 addi r2,r2,8696 + 4cec: 10c00017 ldw r3,0(r2) + 4cf0: defffd04 addi sp,sp,-12 + 4cf4: dc400115 stw r17,4(sp) + 4cf8: dc000015 stw r16,0(sp) + 4cfc: dfc00215 stw ra,8(sp) + 4d00: 2023883a mov r17,r4 + 4d04: 2821883a mov r16,r5 + 4d08: 18000226 beq r3,zero,4d14 <__swsetup_r+0x30> + 4d0c: 18800e17 ldw r2,56(r3) + 4d10: 10001f26 beq r2,zero,4d90 <__swsetup_r+0xac> + 4d14: 8100030b ldhu r4,12(r16) + 4d18: 2080020c andi r2,r4,8 + 4d1c: 10002826 beq r2,zero,4dc0 <__swsetup_r+0xdc> + 4d20: 81400417 ldw r5,16(r16) + 4d24: 28001d26 beq r5,zero,4d9c <__swsetup_r+0xb8> + 4d28: 2080004c andi r2,r4,1 + 4d2c: 1005003a cmpeq r2,r2,zero + 4d30: 10000b26 beq r2,zero,4d60 <__swsetup_r+0x7c> + 4d34: 2080008c andi r2,r4,2 + 4d38: 10001226 beq r2,zero,4d84 <__swsetup_r+0xa0> + 4d3c: 0005883a mov r2,zero + 4d40: 80800215 stw r2,8(r16) + 4d44: 28000b26 beq r5,zero,4d74 <__swsetup_r+0x90> + 4d48: 0005883a mov r2,zero + 4d4c: dfc00217 ldw ra,8(sp) + 4d50: dc400117 ldw r17,4(sp) + 4d54: dc000017 ldw r16,0(sp) + 4d58: dec00304 addi sp,sp,12 + 4d5c: f800283a ret + 4d60: 80800517 ldw r2,20(r16) + 4d64: 80000215 stw zero,8(r16) + 4d68: 0085c83a sub r2,zero,r2 + 4d6c: 80800615 stw r2,24(r16) + 4d70: 283ff51e bne r5,zero,4d48 <__swsetup_r+0x64> + 4d74: 2080200c andi r2,r4,128 + 4d78: 103ff326 beq r2,zero,4d48 <__swsetup_r+0x64> + 4d7c: 00bfffc4 movi r2,-1 + 4d80: 003ff206 br 4d4c <__swsetup_r+0x68> + 4d84: 80800517 ldw r2,20(r16) + 4d88: 80800215 stw r2,8(r16) + 4d8c: 003fed06 br 4d44 <__swsetup_r+0x60> + 4d90: 1809883a mov r4,r3 + 4d94: 00068b00 call 68b0 <__sinit> + 4d98: 003fde06 br 4d14 <__swsetup_r+0x30> + 4d9c: 20c0a00c andi r3,r4,640 + 4da0: 00808004 movi r2,512 + 4da4: 18bfe026 beq r3,r2,4d28 <__swsetup_r+0x44> + 4da8: 8809883a mov r4,r17 + 4dac: 800b883a mov r5,r16 + 4db0: 000765c0 call 765c <__smakebuf_r> + 4db4: 8100030b ldhu r4,12(r16) + 4db8: 81400417 ldw r5,16(r16) + 4dbc: 003fda06 br 4d28 <__swsetup_r+0x44> + 4dc0: 2080040c andi r2,r4,16 + 4dc4: 103fed26 beq r2,zero,4d7c <__swsetup_r+0x98> + 4dc8: 2080010c andi r2,r4,4 + 4dcc: 10001226 beq r2,zero,4e18 <__swsetup_r+0x134> + 4dd0: 81400c17 ldw r5,48(r16) + 4dd4: 28000526 beq r5,zero,4dec <__swsetup_r+0x108> + 4dd8: 80801004 addi r2,r16,64 + 4ddc: 28800226 beq r5,r2,4de8 <__swsetup_r+0x104> + 4de0: 8809883a mov r4,r17 + 4de4: 0006c680 call 6c68 <_free_r> + 4de8: 80000c15 stw zero,48(r16) + 4dec: 8080030b ldhu r2,12(r16) + 4df0: 81400417 ldw r5,16(r16) + 4df4: 80000115 stw zero,4(r16) + 4df8: 10bff6cc andi r2,r2,65499 + 4dfc: 8080030d sth r2,12(r16) + 4e00: 81400015 stw r5,0(r16) + 4e04: 8080030b ldhu r2,12(r16) + 4e08: 10800214 ori r2,r2,8 + 4e0c: 113fffcc andi r4,r2,65535 + 4e10: 8080030d sth r2,12(r16) + 4e14: 003fc306 br 4d24 <__swsetup_r+0x40> + 4e18: 81400417 ldw r5,16(r16) + 4e1c: 003ff906 br 4e04 <__swsetup_r+0x120> + +00004e20 : + 4e20: 28c00417 ldw r3,16(r5) + 4e24: 20800417 ldw r2,16(r4) + 4e28: defff104 addi sp,sp,-60 + 4e2c: dfc00e15 stw ra,56(sp) + 4e30: df000d15 stw fp,52(sp) + 4e34: ddc00c15 stw r23,48(sp) + 4e38: dd800b15 stw r22,44(sp) + 4e3c: dd400a15 stw r21,40(sp) + 4e40: dd000915 stw r20,36(sp) + 4e44: dcc00815 stw r19,32(sp) + 4e48: dc800715 stw r18,28(sp) + 4e4c: dc400615 stw r17,24(sp) + 4e50: dc000515 stw r16,20(sp) + 4e54: d9000315 stw r4,12(sp) + 4e58: d9400415 stw r5,16(sp) + 4e5c: 10c07f16 blt r2,r3,505c + 4e60: 1d3fffc4 addi r20,r3,-1 + 4e64: d8c00417 ldw r3,16(sp) + 4e68: d9000317 ldw r4,12(sp) + 4e6c: a505883a add r2,r20,r20 + 4e70: 1085883a add r2,r2,r2 + 4e74: 1cc00504 addi r19,r3,20 + 4e78: 25c00504 addi r23,r4,20 + 4e7c: 98ad883a add r22,r19,r2 + 4e80: 15c7883a add r3,r2,r23 + 4e84: b1400017 ldw r5,0(r22) + 4e88: 19000017 ldw r4,0(r3) + 4e8c: d8c00015 stw r3,0(sp) + 4e90: 29400044 addi r5,r5,1 + 4e94: d9000215 stw r4,8(sp) + 4e98: 0002c140 call 2c14 <__udivsi3> + 4e9c: 1039883a mov fp,r2 + 4ea0: 10003d1e bne r2,zero,4f98 + 4ea4: d9400417 ldw r5,16(sp) + 4ea8: d9000317 ldw r4,12(sp) + 4eac: 00083880 call 8388 <__mcmp> + 4eb0: 10002c16 blt r2,zero,4f64 + 4eb4: e7000044 addi fp,fp,1 + 4eb8: b80f883a mov r7,r23 + 4ebc: 0011883a mov r8,zero + 4ec0: 0009883a mov r4,zero + 4ec4: 99400017 ldw r5,0(r19) + 4ec8: 38c00017 ldw r3,0(r7) + 4ecc: 9cc00104 addi r19,r19,4 + 4ed0: 28bfffcc andi r2,r5,65535 + 4ed4: 2085883a add r2,r4,r2 + 4ed8: 11bfffcc andi r6,r2,65535 + 4edc: 193fffcc andi r4,r3,65535 + 4ee0: 1004d43a srli r2,r2,16 + 4ee4: 280ad43a srli r5,r5,16 + 4ee8: 2189c83a sub r4,r4,r6 + 4eec: 2209883a add r4,r4,r8 + 4ef0: 1806d43a srli r3,r3,16 + 4ef4: 288b883a add r5,r5,r2 + 4ef8: 200dd43a srai r6,r4,16 + 4efc: 28bfffcc andi r2,r5,65535 + 4f00: 1887c83a sub r3,r3,r2 + 4f04: 1987883a add r3,r3,r6 + 4f08: 3900000d sth r4,0(r7) + 4f0c: 38c0008d sth r3,2(r7) + 4f10: 2808d43a srli r4,r5,16 + 4f14: 39c00104 addi r7,r7,4 + 4f18: 1811d43a srai r8,r3,16 + 4f1c: b4ffe92e bgeu r22,r19,4ec4 + 4f20: a505883a add r2,r20,r20 + 4f24: 1085883a add r2,r2,r2 + 4f28: b885883a add r2,r23,r2 + 4f2c: 10c00017 ldw r3,0(r2) + 4f30: 18000c1e bne r3,zero,4f64 + 4f34: 113fff04 addi r4,r2,-4 + 4f38: b900082e bgeu r23,r4,4f5c + 4f3c: 10bfff17 ldw r2,-4(r2) + 4f40: 10000326 beq r2,zero,4f50 + 4f44: 00000506 br 4f5c + 4f48: 20800017 ldw r2,0(r4) + 4f4c: 1000031e bne r2,zero,4f5c + 4f50: 213fff04 addi r4,r4,-4 + 4f54: a53fffc4 addi r20,r20,-1 + 4f58: b93ffb36 bltu r23,r4,4f48 + 4f5c: d9000317 ldw r4,12(sp) + 4f60: 25000415 stw r20,16(r4) + 4f64: e005883a mov r2,fp + 4f68: dfc00e17 ldw ra,56(sp) + 4f6c: df000d17 ldw fp,52(sp) + 4f70: ddc00c17 ldw r23,48(sp) + 4f74: dd800b17 ldw r22,44(sp) + 4f78: dd400a17 ldw r21,40(sp) + 4f7c: dd000917 ldw r20,36(sp) + 4f80: dcc00817 ldw r19,32(sp) + 4f84: dc800717 ldw r18,28(sp) + 4f88: dc400617 ldw r17,24(sp) + 4f8c: dc000517 ldw r16,20(sp) + 4f90: dec00f04 addi sp,sp,60 + 4f94: f800283a ret + 4f98: b823883a mov r17,r23 + 4f9c: 9825883a mov r18,r19 + 4fa0: d8000115 stw zero,4(sp) + 4fa4: 002b883a mov r21,zero + 4fa8: 94000017 ldw r16,0(r18) + 4fac: e009883a mov r4,fp + 4fb0: 94800104 addi r18,r18,4 + 4fb4: 817fffcc andi r5,r16,65535 + 4fb8: 0002c240 call 2c24 <__mulsi3> + 4fbc: 800ad43a srli r5,r16,16 + 4fc0: e009883a mov r4,fp + 4fc4: a8a1883a add r16,r21,r2 + 4fc8: 0002c240 call 2c24 <__mulsi3> + 4fcc: 89000017 ldw r4,0(r17) + 4fd0: 80ffffcc andi r3,r16,65535 + 4fd4: 8020d43a srli r16,r16,16 + 4fd8: 217fffcc andi r5,r4,65535 + 4fdc: 28cbc83a sub r5,r5,r3 + 4fe0: d8c00117 ldw r3,4(sp) + 4fe4: 2008d43a srli r4,r4,16 + 4fe8: 1405883a add r2,r2,r16 + 4fec: 28cb883a add r5,r5,r3 + 4ff0: 280dd43a srai r6,r5,16 + 4ff4: 10ffffcc andi r3,r2,65535 + 4ff8: 20c9c83a sub r4,r4,r3 + 4ffc: 2189883a add r4,r4,r6 + 5000: 8900008d sth r4,2(r17) + 5004: 2009d43a srai r4,r4,16 + 5008: 8940000d sth r5,0(r17) + 500c: 102ad43a srli r21,r2,16 + 5010: 8c400104 addi r17,r17,4 + 5014: d9000115 stw r4,4(sp) + 5018: b4bfe32e bgeu r22,r18,4fa8 + 501c: d9000217 ldw r4,8(sp) + 5020: 203fa01e bne r4,zero,4ea4 + 5024: d8800017 ldw r2,0(sp) + 5028: 10ffff04 addi r3,r2,-4 + 502c: b8c0082e bgeu r23,r3,5050 + 5030: 10bfff17 ldw r2,-4(r2) + 5034: 10000326 beq r2,zero,5044 + 5038: 00000506 br 5050 + 503c: 18800017 ldw r2,0(r3) + 5040: 1000031e bne r2,zero,5050 + 5044: 18ffff04 addi r3,r3,-4 + 5048: a53fffc4 addi r20,r20,-1 + 504c: b8fffb36 bltu r23,r3,503c + 5050: d8c00317 ldw r3,12(sp) + 5054: 1d000415 stw r20,16(r3) + 5058: 003f9206 br 4ea4 + 505c: 0005883a mov r2,zero + 5060: 003fc106 br 4f68 + +00005064 <_dtoa_r>: + 5064: 22001017 ldw r8,64(r4) + 5068: deffda04 addi sp,sp,-152 + 506c: dd402115 stw r21,132(sp) + 5070: dd002015 stw r20,128(sp) + 5074: dc801e15 stw r18,120(sp) + 5078: dc401d15 stw r17,116(sp) + 507c: dfc02515 stw ra,148(sp) + 5080: df002415 stw fp,144(sp) + 5084: ddc02315 stw r23,140(sp) + 5088: dd802215 stw r22,136(sp) + 508c: dcc01f15 stw r19,124(sp) + 5090: dc001c15 stw r16,112(sp) + 5094: d9001615 stw r4,88(sp) + 5098: 3023883a mov r17,r6 + 509c: 2829883a mov r20,r5 + 50a0: d9c01715 stw r7,92(sp) + 50a4: dc802817 ldw r18,160(sp) + 50a8: 302b883a mov r21,r6 + 50ac: 40000a26 beq r8,zero,50d8 <_dtoa_r+0x74> + 50b0: 20801117 ldw r2,68(r4) + 50b4: 400b883a mov r5,r8 + 50b8: 40800115 stw r2,4(r8) + 50bc: 20c01117 ldw r3,68(r4) + 50c0: 00800044 movi r2,1 + 50c4: 10c4983a sll r2,r2,r3 + 50c8: 40800215 stw r2,8(r8) + 50cc: 000822c0 call 822c <_Bfree> + 50d0: d8c01617 ldw r3,88(sp) + 50d4: 18001015 stw zero,64(r3) + 50d8: 8800a316 blt r17,zero,5368 <_dtoa_r+0x304> + 50dc: 90000015 stw zero,0(r18) + 50e0: a8dffc2c andhi r3,r21,32752 + 50e4: 009ffc34 movhi r2,32752 + 50e8: 18809126 beq r3,r2,5330 <_dtoa_r+0x2cc> + 50ec: 000d883a mov r6,zero + 50f0: 000f883a mov r7,zero + 50f4: a009883a mov r4,r20 + 50f8: a80b883a mov r5,r21 + 50fc: dd001215 stw r20,72(sp) + 5100: dd401315 stw r21,76(sp) + 5104: 000b8b00 call b8b0 <__nedf2> + 5108: 1000171e bne r2,zero,5168 <_dtoa_r+0x104> + 510c: d9802717 ldw r6,156(sp) + 5110: 00800044 movi r2,1 + 5114: 30800015 stw r2,0(r6) + 5118: d8802917 ldw r2,164(sp) + 511c: 10029b26 beq r2,zero,5b8c <_dtoa_r+0xb28> + 5120: d9002917 ldw r4,164(sp) + 5124: 00800074 movhi r2,1 + 5128: 1080f144 addi r2,r2,965 + 512c: 10ffffc4 addi r3,r2,-1 + 5130: 20800015 stw r2,0(r4) + 5134: 1805883a mov r2,r3 + 5138: dfc02517 ldw ra,148(sp) + 513c: df002417 ldw fp,144(sp) + 5140: ddc02317 ldw r23,140(sp) + 5144: dd802217 ldw r22,136(sp) + 5148: dd402117 ldw r21,132(sp) + 514c: dd002017 ldw r20,128(sp) + 5150: dcc01f17 ldw r19,124(sp) + 5154: dc801e17 ldw r18,120(sp) + 5158: dc401d17 ldw r17,116(sp) + 515c: dc001c17 ldw r16,112(sp) + 5160: dec02604 addi sp,sp,152 + 5164: f800283a ret + 5168: d9001617 ldw r4,88(sp) + 516c: d9401217 ldw r5,72(sp) + 5170: d8800104 addi r2,sp,4 + 5174: a80d883a mov r6,r21 + 5178: d9c00204 addi r7,sp,8 + 517c: d8800015 stw r2,0(sp) + 5180: 00088680 call 8868 <__d2b> + 5184: d8800715 stw r2,28(sp) + 5188: a804d53a srli r2,r21,20 + 518c: 1101ffcc andi r4,r2,2047 + 5190: 20008626 beq r4,zero,53ac <_dtoa_r+0x348> + 5194: d8c01217 ldw r3,72(sp) + 5198: 00800434 movhi r2,16 + 519c: 10bfffc4 addi r2,r2,-1 + 51a0: ddc00117 ldw r23,4(sp) + 51a4: a884703a and r2,r21,r2 + 51a8: 1811883a mov r8,r3 + 51ac: 124ffc34 orhi r9,r2,16368 + 51b0: 25bf0044 addi r22,r4,-1023 + 51b4: d8000815 stw zero,32(sp) + 51b8: 0005883a mov r2,zero + 51bc: 00cffe34 movhi r3,16376 + 51c0: 480b883a mov r5,r9 + 51c4: 4009883a mov r4,r8 + 51c8: 180f883a mov r7,r3 + 51cc: 100d883a mov r6,r2 + 51d0: 000b1180 call b118 <__subdf3> + 51d4: 0218dbf4 movhi r8,25455 + 51d8: 4210d844 addi r8,r8,17249 + 51dc: 024ff4f4 movhi r9,16339 + 51e0: 4a61e9c4 addi r9,r9,-30809 + 51e4: 480f883a mov r7,r9 + 51e8: 400d883a mov r6,r8 + 51ec: 180b883a mov r5,r3 + 51f0: 1009883a mov r4,r2 + 51f4: 000b20c0 call b20c <__muldf3> + 51f8: 0222d874 movhi r8,35681 + 51fc: 42322cc4 addi r8,r8,-14157 + 5200: 024ff1f4 movhi r9,16327 + 5204: 4a628a04 addi r9,r9,-30168 + 5208: 480f883a mov r7,r9 + 520c: 400d883a mov r6,r8 + 5210: 180b883a mov r5,r3 + 5214: 1009883a mov r4,r2 + 5218: 000b1980 call b198 <__adddf3> + 521c: b009883a mov r4,r22 + 5220: 1021883a mov r16,r2 + 5224: 1823883a mov r17,r3 + 5228: 000bad00 call bad0 <__floatsidf> + 522c: 021427f4 movhi r8,20639 + 5230: 421e7ec4 addi r8,r8,31227 + 5234: 024ff4f4 movhi r9,16339 + 5238: 4a5104c4 addi r9,r9,17427 + 523c: 480f883a mov r7,r9 + 5240: 400d883a mov r6,r8 + 5244: 180b883a mov r5,r3 + 5248: 1009883a mov r4,r2 + 524c: 000b20c0 call b20c <__muldf3> + 5250: 180f883a mov r7,r3 + 5254: 880b883a mov r5,r17 + 5258: 100d883a mov r6,r2 + 525c: 8009883a mov r4,r16 + 5260: 000b1980 call b198 <__adddf3> + 5264: 1009883a mov r4,r2 + 5268: 180b883a mov r5,r3 + 526c: 1021883a mov r16,r2 + 5270: 1823883a mov r17,r3 + 5274: 000bbc80 call bbc8 <__fixdfsi> + 5278: 000d883a mov r6,zero + 527c: 000f883a mov r7,zero + 5280: 8009883a mov r4,r16 + 5284: 880b883a mov r5,r17 + 5288: d8800d15 stw r2,52(sp) + 528c: 000ba480 call ba48 <__ltdf2> + 5290: 10031716 blt r2,zero,5ef0 <_dtoa_r+0xe8c> + 5294: d8c00d17 ldw r3,52(sp) + 5298: 00800584 movi r2,22 + 529c: 10c1482e bgeu r2,r3,57c0 <_dtoa_r+0x75c> + 52a0: 01000044 movi r4,1 + 52a4: d9000c15 stw r4,48(sp) + 52a8: bd85c83a sub r2,r23,r22 + 52ac: 11bfffc4 addi r6,r2,-1 + 52b0: 30030b16 blt r6,zero,5ee0 <_dtoa_r+0xe7c> + 52b4: d9800a15 stw r6,40(sp) + 52b8: d8001115 stw zero,68(sp) + 52bc: d8c00d17 ldw r3,52(sp) + 52c0: 1802ff16 blt r3,zero,5ec0 <_dtoa_r+0xe5c> + 52c4: d9000a17 ldw r4,40(sp) + 52c8: d8c00915 stw r3,36(sp) + 52cc: d8001015 stw zero,64(sp) + 52d0: 20c9883a add r4,r4,r3 + 52d4: d9000a15 stw r4,40(sp) + 52d8: d9001717 ldw r4,92(sp) + 52dc: 00800244 movi r2,9 + 52e0: 11004636 bltu r2,r4,53fc <_dtoa_r+0x398> + 52e4: 00800144 movi r2,5 + 52e8: 11020416 blt r2,r4,5afc <_dtoa_r+0xa98> + 52ec: 04400044 movi r17,1 + 52f0: d8c01717 ldw r3,92(sp) + 52f4: 00800144 movi r2,5 + 52f8: 10c1ed36 bltu r2,r3,5ab0 <_dtoa_r+0xa4c> + 52fc: 18c5883a add r2,r3,r3 + 5300: 1085883a add r2,r2,r2 + 5304: 00c00034 movhi r3,0 + 5308: 18d4c604 addi r3,r3,21272 + 530c: 10c5883a add r2,r2,r3 + 5310: 11000017 ldw r4,0(r2) + 5314: 2000683a jmp r4 + 5318: 00005404 movi zero,336 + 531c: 00005404 movi zero,336 + 5320: 00005e04 movi zero,376 + 5324: 00005ddc xori zero,zero,375 + 5328: 00005e20 cmpeqi zero,zero,376 + 532c: 00005e2c andhi zero,zero,376 + 5330: d9002717 ldw r4,156(sp) + 5334: 0089c3c4 movi r2,9999 + 5338: 20800015 stw r2,0(r4) + 533c: a0001026 beq r20,zero,5380 <_dtoa_r+0x31c> + 5340: 00c00074 movhi r3,1 + 5344: 18c0fd04 addi r3,r3,1012 + 5348: d9802917 ldw r6,164(sp) + 534c: 303f7926 beq r6,zero,5134 <_dtoa_r+0xd0> + 5350: 188000c7 ldb r2,3(r3) + 5354: 190000c4 addi r4,r3,3 + 5358: 1000101e bne r2,zero,539c <_dtoa_r+0x338> + 535c: d8802917 ldw r2,164(sp) + 5360: 11000015 stw r4,0(r2) + 5364: 003f7306 br 5134 <_dtoa_r+0xd0> + 5368: 00a00034 movhi r2,32768 + 536c: 10bfffc4 addi r2,r2,-1 + 5370: 00c00044 movi r3,1 + 5374: 88aa703a and r21,r17,r2 + 5378: 90c00015 stw r3,0(r18) + 537c: 003f5806 br 50e0 <_dtoa_r+0x7c> + 5380: 00800434 movhi r2,16 + 5384: 10bfffc4 addi r2,r2,-1 + 5388: a884703a and r2,r21,r2 + 538c: 103fec1e bne r2,zero,5340 <_dtoa_r+0x2dc> + 5390: 00c00074 movhi r3,1 + 5394: 18c0fa04 addi r3,r3,1000 + 5398: 003feb06 br 5348 <_dtoa_r+0x2e4> + 539c: d8802917 ldw r2,164(sp) + 53a0: 19000204 addi r4,r3,8 + 53a4: 11000015 stw r4,0(r2) + 53a8: 003f6206 br 5134 <_dtoa_r+0xd0> + 53ac: ddc00117 ldw r23,4(sp) + 53b0: d8800217 ldw r2,8(sp) + 53b4: 01000804 movi r4,32 + 53b8: b8c10c84 addi r3,r23,1074 + 53bc: 18a3883a add r17,r3,r2 + 53c0: 2441b80e bge r4,r17,5aa4 <_dtoa_r+0xa40> + 53c4: 00c01004 movi r3,64 + 53c8: 1c47c83a sub r3,r3,r17 + 53cc: 88bff804 addi r2,r17,-32 + 53d0: a8c6983a sll r3,r21,r3 + 53d4: a084d83a srl r2,r20,r2 + 53d8: 1888b03a or r4,r3,r2 + 53dc: 000bca00 call bca0 <__floatunsidf> + 53e0: 1011883a mov r8,r2 + 53e4: 00bf8434 movhi r2,65040 + 53e8: 01000044 movi r4,1 + 53ec: 10d3883a add r9,r2,r3 + 53f0: 8dbef344 addi r22,r17,-1075 + 53f4: d9000815 stw r4,32(sp) + 53f8: 003f6f06 br 51b8 <_dtoa_r+0x154> + 53fc: d8001715 stw zero,92(sp) + 5400: 04400044 movi r17,1 + 5404: 00bfffc4 movi r2,-1 + 5408: 00c00044 movi r3,1 + 540c: d8800e15 stw r2,56(sp) + 5410: d8002615 stw zero,152(sp) + 5414: d8800f15 stw r2,60(sp) + 5418: d8c00b15 stw r3,44(sp) + 541c: 1021883a mov r16,r2 + 5420: d8801617 ldw r2,88(sp) + 5424: 10001115 stw zero,68(r2) + 5428: d8801617 ldw r2,88(sp) + 542c: 11401117 ldw r5,68(r2) + 5430: 1009883a mov r4,r2 + 5434: 00087ac0 call 87ac <_Balloc> + 5438: d8c01617 ldw r3,88(sp) + 543c: d8800515 stw r2,20(sp) + 5440: 18801015 stw r2,64(r3) + 5444: 00800384 movi r2,14 + 5448: 14006836 bltu r2,r16,55ec <_dtoa_r+0x588> + 544c: 8805003a cmpeq r2,r17,zero + 5450: 1000661e bne r2,zero,55ec <_dtoa_r+0x588> + 5454: d9000d17 ldw r4,52(sp) + 5458: 0102300e bge zero,r4,5d1c <_dtoa_r+0xcb8> + 545c: 208003cc andi r2,r4,15 + 5460: 100490fa slli r2,r2,3 + 5464: 2025d13a srai r18,r4,4 + 5468: 00c00074 movhi r3,1 + 546c: 18c10f04 addi r3,r3,1084 + 5470: 10c5883a add r2,r2,r3 + 5474: 90c0040c andi r3,r18,16 + 5478: 14000017 ldw r16,0(r2) + 547c: 14400117 ldw r17,4(r2) + 5480: 18036a1e bne r3,zero,622c <_dtoa_r+0x11c8> + 5484: 05800084 movi r22,2 + 5488: 90001026 beq r18,zero,54cc <_dtoa_r+0x468> + 548c: 04c00074 movhi r19,1 + 5490: 9cc14104 addi r19,r19,1284 + 5494: 9080004c andi r2,r18,1 + 5498: 1005003a cmpeq r2,r2,zero + 549c: 1000081e bne r2,zero,54c0 <_dtoa_r+0x45c> + 54a0: 99800017 ldw r6,0(r19) + 54a4: 99c00117 ldw r7,4(r19) + 54a8: 880b883a mov r5,r17 + 54ac: 8009883a mov r4,r16 + 54b0: 000b20c0 call b20c <__muldf3> + 54b4: 1021883a mov r16,r2 + 54b8: b5800044 addi r22,r22,1 + 54bc: 1823883a mov r17,r3 + 54c0: 9025d07a srai r18,r18,1 + 54c4: 9cc00204 addi r19,r19,8 + 54c8: 903ff21e bne r18,zero,5494 <_dtoa_r+0x430> + 54cc: a80b883a mov r5,r21 + 54d0: a009883a mov r4,r20 + 54d4: 880f883a mov r7,r17 + 54d8: 800d883a mov r6,r16 + 54dc: 000b5d00 call b5d0 <__divdf3> + 54e0: 1029883a mov r20,r2 + 54e4: 182b883a mov r21,r3 + 54e8: d8c00c17 ldw r3,48(sp) + 54ec: 1805003a cmpeq r2,r3,zero + 54f0: 1000081e bne r2,zero,5514 <_dtoa_r+0x4b0> + 54f4: 0005883a mov r2,zero + 54f8: 00cffc34 movhi r3,16368 + 54fc: 180f883a mov r7,r3 + 5500: a009883a mov r4,r20 + 5504: a80b883a mov r5,r21 + 5508: 100d883a mov r6,r2 + 550c: 000ba480 call ba48 <__ltdf2> + 5510: 1003fe16 blt r2,zero,650c <_dtoa_r+0x14a8> + 5514: b009883a mov r4,r22 + 5518: 000bad00 call bad0 <__floatsidf> + 551c: 180b883a mov r5,r3 + 5520: 1009883a mov r4,r2 + 5524: a00d883a mov r6,r20 + 5528: a80f883a mov r7,r21 + 552c: 000b20c0 call b20c <__muldf3> + 5530: 0011883a mov r8,zero + 5534: 02500734 movhi r9,16412 + 5538: 1009883a mov r4,r2 + 553c: 180b883a mov r5,r3 + 5540: 480f883a mov r7,r9 + 5544: 400d883a mov r6,r8 + 5548: 000b1980 call b198 <__adddf3> + 554c: d9000f17 ldw r4,60(sp) + 5550: 102d883a mov r22,r2 + 5554: 00bf3034 movhi r2,64704 + 5558: 18b9883a add fp,r3,r2 + 555c: e02f883a mov r23,fp + 5560: 20028f1e bne r4,zero,5fa0 <_dtoa_r+0xf3c> + 5564: 0005883a mov r2,zero + 5568: 00d00534 movhi r3,16404 + 556c: a009883a mov r4,r20 + 5570: a80b883a mov r5,r21 + 5574: 180f883a mov r7,r3 + 5578: 100d883a mov r6,r2 + 557c: 000b1180 call b118 <__subdf3> + 5580: 1009883a mov r4,r2 + 5584: e00f883a mov r7,fp + 5588: 180b883a mov r5,r3 + 558c: b00d883a mov r6,r22 + 5590: 1025883a mov r18,r2 + 5594: 1827883a mov r19,r3 + 5598: 000b9380 call b938 <__gtdf2> + 559c: 00834f16 blt zero,r2,62dc <_dtoa_r+0x1278> + 55a0: e0e0003c xorhi r3,fp,32768 + 55a4: 9009883a mov r4,r18 + 55a8: 980b883a mov r5,r19 + 55ac: 180f883a mov r7,r3 + 55b0: b00d883a mov r6,r22 + 55b4: 000ba480 call ba48 <__ltdf2> + 55b8: 1000080e bge r2,zero,55dc <_dtoa_r+0x578> + 55bc: 0027883a mov r19,zero + 55c0: 0025883a mov r18,zero + 55c4: d8802617 ldw r2,152(sp) + 55c8: df000517 ldw fp,20(sp) + 55cc: d8000615 stw zero,24(sp) + 55d0: 0084303a nor r2,zero,r2 + 55d4: d8800d15 stw r2,52(sp) + 55d8: 00019b06 br 5c48 <_dtoa_r+0xbe4> + 55dc: d9801217 ldw r6,72(sp) + 55e0: d8801317 ldw r2,76(sp) + 55e4: 3029883a mov r20,r6 + 55e8: 102b883a mov r21,r2 + 55ec: d8c00217 ldw r3,8(sp) + 55f0: 18008516 blt r3,zero,5808 <_dtoa_r+0x7a4> + 55f4: d9000d17 ldw r4,52(sp) + 55f8: 00800384 movi r2,14 + 55fc: 11008216 blt r2,r4,5808 <_dtoa_r+0x7a4> + 5600: 200490fa slli r2,r4,3 + 5604: d9802617 ldw r6,152(sp) + 5608: 00c00074 movhi r3,1 + 560c: 18c10f04 addi r3,r3,1084 + 5610: 10c5883a add r2,r2,r3 + 5614: 14800017 ldw r18,0(r2) + 5618: 14c00117 ldw r19,4(r2) + 561c: 30031e16 blt r6,zero,6298 <_dtoa_r+0x1234> + 5620: d9000517 ldw r4,20(sp) + 5624: d8c00f17 ldw r3,60(sp) + 5628: a823883a mov r17,r21 + 562c: a021883a mov r16,r20 + 5630: 192b883a add r21,r3,r4 + 5634: 2039883a mov fp,r4 + 5638: 00000f06 br 5678 <_dtoa_r+0x614> + 563c: 0005883a mov r2,zero + 5640: 00d00934 movhi r3,16420 + 5644: 5009883a mov r4,r10 + 5648: 580b883a mov r5,r11 + 564c: 180f883a mov r7,r3 + 5650: 100d883a mov r6,r2 + 5654: 000b20c0 call b20c <__muldf3> + 5658: 180b883a mov r5,r3 + 565c: 000d883a mov r6,zero + 5660: 000f883a mov r7,zero + 5664: 1009883a mov r4,r2 + 5668: 1021883a mov r16,r2 + 566c: 1823883a mov r17,r3 + 5670: 000b8b00 call b8b0 <__nedf2> + 5674: 10004526 beq r2,zero,578c <_dtoa_r+0x728> + 5678: 900d883a mov r6,r18 + 567c: 980f883a mov r7,r19 + 5680: 8009883a mov r4,r16 + 5684: 880b883a mov r5,r17 + 5688: 000b5d00 call b5d0 <__divdf3> + 568c: 180b883a mov r5,r3 + 5690: 1009883a mov r4,r2 + 5694: 000bbc80 call bbc8 <__fixdfsi> + 5698: 1009883a mov r4,r2 + 569c: 1029883a mov r20,r2 + 56a0: 000bad00 call bad0 <__floatsidf> + 56a4: 180f883a mov r7,r3 + 56a8: 9009883a mov r4,r18 + 56ac: 980b883a mov r5,r19 + 56b0: 100d883a mov r6,r2 + 56b4: 000b20c0 call b20c <__muldf3> + 56b8: 180f883a mov r7,r3 + 56bc: 880b883a mov r5,r17 + 56c0: 8009883a mov r4,r16 + 56c4: 100d883a mov r6,r2 + 56c8: 000b1180 call b118 <__subdf3> + 56cc: 1015883a mov r10,r2 + 56d0: a0800c04 addi r2,r20,48 + 56d4: e0800005 stb r2,0(fp) + 56d8: e7000044 addi fp,fp,1 + 56dc: 1817883a mov r11,r3 + 56e0: e57fd61e bne fp,r21,563c <_dtoa_r+0x5d8> + 56e4: 500d883a mov r6,r10 + 56e8: 180f883a mov r7,r3 + 56ec: 5009883a mov r4,r10 + 56f0: 180b883a mov r5,r3 + 56f4: 000b1980 call b198 <__adddf3> + 56f8: 100d883a mov r6,r2 + 56fc: 9009883a mov r4,r18 + 5700: 980b883a mov r5,r19 + 5704: 180f883a mov r7,r3 + 5708: 1021883a mov r16,r2 + 570c: 1823883a mov r17,r3 + 5710: 000ba480 call ba48 <__ltdf2> + 5714: 10000816 blt r2,zero,5738 <_dtoa_r+0x6d4> + 5718: 980b883a mov r5,r19 + 571c: 800d883a mov r6,r16 + 5720: 880f883a mov r7,r17 + 5724: 9009883a mov r4,r18 + 5728: 000b8280 call b828 <__eqdf2> + 572c: 1000171e bne r2,zero,578c <_dtoa_r+0x728> + 5730: a080004c andi r2,r20,1 + 5734: 10001526 beq r2,zero,578c <_dtoa_r+0x728> + 5738: d8800d17 ldw r2,52(sp) + 573c: d8800415 stw r2,16(sp) + 5740: e009883a mov r4,fp + 5744: 213fffc4 addi r4,r4,-1 + 5748: 20c00007 ldb r3,0(r4) + 574c: 00800e44 movi r2,57 + 5750: 1880081e bne r3,r2,5774 <_dtoa_r+0x710> + 5754: d8800517 ldw r2,20(sp) + 5758: 113ffa1e bne r2,r4,5744 <_dtoa_r+0x6e0> + 575c: d8c00417 ldw r3,16(sp) + 5760: d9800517 ldw r6,20(sp) + 5764: 00800c04 movi r2,48 + 5768: 18c00044 addi r3,r3,1 + 576c: d8c00415 stw r3,16(sp) + 5770: 30800005 stb r2,0(r6) + 5774: 20800003 ldbu r2,0(r4) + 5778: d8c00417 ldw r3,16(sp) + 577c: 27000044 addi fp,r4,1 + 5780: 10800044 addi r2,r2,1 + 5784: d8c00d15 stw r3,52(sp) + 5788: 20800005 stb r2,0(r4) + 578c: d9001617 ldw r4,88(sp) + 5790: d9400717 ldw r5,28(sp) + 5794: 000822c0 call 822c <_Bfree> + 5798: e0000005 stb zero,0(fp) + 579c: d9800d17 ldw r6,52(sp) + 57a0: d8c02717 ldw r3,156(sp) + 57a4: d9002917 ldw r4,164(sp) + 57a8: 30800044 addi r2,r6,1 + 57ac: 18800015 stw r2,0(r3) + 57b0: 20029c26 beq r4,zero,6224 <_dtoa_r+0x11c0> + 57b4: d8c00517 ldw r3,20(sp) + 57b8: 27000015 stw fp,0(r4) + 57bc: 003e5d06 br 5134 <_dtoa_r+0xd0> + 57c0: d9800d17 ldw r6,52(sp) + 57c4: 00c00074 movhi r3,1 + 57c8: 18c10f04 addi r3,r3,1084 + 57cc: d9001217 ldw r4,72(sp) + 57d0: 300490fa slli r2,r6,3 + 57d4: d9401317 ldw r5,76(sp) + 57d8: 10c5883a add r2,r2,r3 + 57dc: 12000017 ldw r8,0(r2) + 57e0: 12400117 ldw r9,4(r2) + 57e4: 400d883a mov r6,r8 + 57e8: 480f883a mov r7,r9 + 57ec: 000ba480 call ba48 <__ltdf2> + 57f0: 1000030e bge r2,zero,5800 <_dtoa_r+0x79c> + 57f4: d8800d17 ldw r2,52(sp) + 57f8: 10bfffc4 addi r2,r2,-1 + 57fc: d8800d15 stw r2,52(sp) + 5800: d8000c15 stw zero,48(sp) + 5804: 003ea806 br 52a8 <_dtoa_r+0x244> + 5808: d9000b17 ldw r4,44(sp) + 580c: 202cc03a cmpne r22,r4,zero + 5810: b000c71e bne r22,zero,5b30 <_dtoa_r+0xacc> + 5814: dc001117 ldw r16,68(sp) + 5818: dc801017 ldw r18,64(sp) + 581c: 0027883a mov r19,zero + 5820: 04000b0e bge zero,r16,5850 <_dtoa_r+0x7ec> + 5824: d8c00a17 ldw r3,40(sp) + 5828: 00c0090e bge zero,r3,5850 <_dtoa_r+0x7ec> + 582c: 8005883a mov r2,r16 + 5830: 1c011316 blt r3,r16,5c80 <_dtoa_r+0xc1c> + 5834: d9000a17 ldw r4,40(sp) + 5838: d9801117 ldw r6,68(sp) + 583c: 80a1c83a sub r16,r16,r2 + 5840: 2089c83a sub r4,r4,r2 + 5844: 308dc83a sub r6,r6,r2 + 5848: d9000a15 stw r4,40(sp) + 584c: d9801115 stw r6,68(sp) + 5850: d8801017 ldw r2,64(sp) + 5854: 0080150e bge zero,r2,58ac <_dtoa_r+0x848> + 5858: d8c00b17 ldw r3,44(sp) + 585c: 1805003a cmpeq r2,r3,zero + 5860: 1001c91e bne r2,zero,5f88 <_dtoa_r+0xf24> + 5864: 04800e0e bge zero,r18,58a0 <_dtoa_r+0x83c> + 5868: d9001617 ldw r4,88(sp) + 586c: 980b883a mov r5,r19 + 5870: 900d883a mov r6,r18 + 5874: 00090780 call 9078 <__pow5mult> + 5878: d9001617 ldw r4,88(sp) + 587c: d9800717 ldw r6,28(sp) + 5880: 100b883a mov r5,r2 + 5884: 1027883a mov r19,r2 + 5888: 0008cbc0 call 8cbc <__multiply> + 588c: d9001617 ldw r4,88(sp) + 5890: d9400717 ldw r5,28(sp) + 5894: 1023883a mov r17,r2 + 5898: 000822c0 call 822c <_Bfree> + 589c: dc400715 stw r17,28(sp) + 58a0: d9001017 ldw r4,64(sp) + 58a4: 248dc83a sub r6,r4,r18 + 58a8: 30010e1e bne r6,zero,5ce4 <_dtoa_r+0xc80> + 58ac: d9001617 ldw r4,88(sp) + 58b0: 04400044 movi r17,1 + 58b4: 880b883a mov r5,r17 + 58b8: 0008f100 call 8f10 <__i2b> + 58bc: d9800917 ldw r6,36(sp) + 58c0: 1025883a mov r18,r2 + 58c4: 0180040e bge zero,r6,58d8 <_dtoa_r+0x874> + 58c8: d9001617 ldw r4,88(sp) + 58cc: 100b883a mov r5,r2 + 58d0: 00090780 call 9078 <__pow5mult> + 58d4: 1025883a mov r18,r2 + 58d8: d8801717 ldw r2,92(sp) + 58dc: 8880f30e bge r17,r2,5cac <_dtoa_r+0xc48> + 58e0: 0023883a mov r17,zero + 58e4: d9800917 ldw r6,36(sp) + 58e8: 30019e1e bne r6,zero,5f64 <_dtoa_r+0xf00> + 58ec: 00c00044 movi r3,1 + 58f0: d9000a17 ldw r4,40(sp) + 58f4: 20c5883a add r2,r4,r3 + 58f8: 10c007cc andi r3,r2,31 + 58fc: 1800841e bne r3,zero,5b10 <_dtoa_r+0xaac> + 5900: 00800704 movi r2,28 + 5904: d9000a17 ldw r4,40(sp) + 5908: d9801117 ldw r6,68(sp) + 590c: 80a1883a add r16,r16,r2 + 5910: 2089883a add r4,r4,r2 + 5914: 308d883a add r6,r6,r2 + 5918: d9000a15 stw r4,40(sp) + 591c: d9801115 stw r6,68(sp) + 5920: d8801117 ldw r2,68(sp) + 5924: 0080050e bge zero,r2,593c <_dtoa_r+0x8d8> + 5928: d9400717 ldw r5,28(sp) + 592c: d9001617 ldw r4,88(sp) + 5930: 100d883a mov r6,r2 + 5934: 0008b700 call 8b70 <__lshift> + 5938: d8800715 stw r2,28(sp) + 593c: d8c00a17 ldw r3,40(sp) + 5940: 00c0050e bge zero,r3,5958 <_dtoa_r+0x8f4> + 5944: d9001617 ldw r4,88(sp) + 5948: 900b883a mov r5,r18 + 594c: 180d883a mov r6,r3 + 5950: 0008b700 call 8b70 <__lshift> + 5954: 1025883a mov r18,r2 + 5958: d9000c17 ldw r4,48(sp) + 595c: 2005003a cmpeq r2,r4,zero + 5960: 10016f26 beq r2,zero,5f20 <_dtoa_r+0xebc> + 5964: d9000f17 ldw r4,60(sp) + 5968: 0102170e bge zero,r4,61c8 <_dtoa_r+0x1164> + 596c: d9800b17 ldw r6,44(sp) + 5970: 3005003a cmpeq r2,r6,zero + 5974: 1000881e bne r2,zero,5b98 <_dtoa_r+0xb34> + 5978: 0400050e bge zero,r16,5990 <_dtoa_r+0x92c> + 597c: d9001617 ldw r4,88(sp) + 5980: 980b883a mov r5,r19 + 5984: 800d883a mov r6,r16 + 5988: 0008b700 call 8b70 <__lshift> + 598c: 1027883a mov r19,r2 + 5990: 8804c03a cmpne r2,r17,zero + 5994: 1002541e bne r2,zero,62e8 <_dtoa_r+0x1284> + 5998: 980b883a mov r5,r19 + 599c: dd800517 ldw r22,20(sp) + 59a0: dcc00615 stw r19,24(sp) + 59a4: a700004c andi fp,r20,1 + 59a8: 2827883a mov r19,r5 + 59ac: d9000717 ldw r4,28(sp) + 59b0: 900b883a mov r5,r18 + 59b4: 0004e200 call 4e20 + 59b8: d9000717 ldw r4,28(sp) + 59bc: d9400617 ldw r5,24(sp) + 59c0: 1023883a mov r17,r2 + 59c4: 8dc00c04 addi r23,r17,48 + 59c8: 00083880 call 8388 <__mcmp> + 59cc: d9001617 ldw r4,88(sp) + 59d0: 900b883a mov r5,r18 + 59d4: 980d883a mov r6,r19 + 59d8: 1029883a mov r20,r2 + 59dc: 00089e40 call 89e4 <__mdiff> + 59e0: 102b883a mov r21,r2 + 59e4: 10800317 ldw r2,12(r2) + 59e8: 1001281e bne r2,zero,5e8c <_dtoa_r+0xe28> + 59ec: d9000717 ldw r4,28(sp) + 59f0: a80b883a mov r5,r21 + 59f4: 00083880 call 8388 <__mcmp> + 59f8: d9001617 ldw r4,88(sp) + 59fc: 1021883a mov r16,r2 + 5a00: a80b883a mov r5,r21 + 5a04: 000822c0 call 822c <_Bfree> + 5a08: 8000041e bne r16,zero,5a1c <_dtoa_r+0x9b8> + 5a0c: d8801717 ldw r2,92(sp) + 5a10: 1000021e bne r2,zero,5a1c <_dtoa_r+0x9b8> + 5a14: e004c03a cmpne r2,fp,zero + 5a18: 10011726 beq r2,zero,5e78 <_dtoa_r+0xe14> + 5a1c: a0010616 blt r20,zero,5e38 <_dtoa_r+0xdd4> + 5a20: a000041e bne r20,zero,5a34 <_dtoa_r+0x9d0> + 5a24: d8c01717 ldw r3,92(sp) + 5a28: 1800021e bne r3,zero,5a34 <_dtoa_r+0x9d0> + 5a2c: e004c03a cmpne r2,fp,zero + 5a30: 10010126 beq r2,zero,5e38 <_dtoa_r+0xdd4> + 5a34: 04023d16 blt zero,r16,632c <_dtoa_r+0x12c8> + 5a38: b5c00005 stb r23,0(r22) + 5a3c: d9800517 ldw r6,20(sp) + 5a40: d9000f17 ldw r4,60(sp) + 5a44: b5800044 addi r22,r22,1 + 5a48: 3105883a add r2,r6,r4 + 5a4c: b0806526 beq r22,r2,5be4 <_dtoa_r+0xb80> + 5a50: d9400717 ldw r5,28(sp) + 5a54: d9001617 ldw r4,88(sp) + 5a58: 01800284 movi r6,10 + 5a5c: 000f883a mov r7,zero + 5a60: 0008f4c0 call 8f4c <__multadd> + 5a64: d8800715 stw r2,28(sp) + 5a68: d8800617 ldw r2,24(sp) + 5a6c: 14c10c26 beq r2,r19,5ea0 <_dtoa_r+0xe3c> + 5a70: d9400617 ldw r5,24(sp) + 5a74: d9001617 ldw r4,88(sp) + 5a78: 01800284 movi r6,10 + 5a7c: 000f883a mov r7,zero + 5a80: 0008f4c0 call 8f4c <__multadd> + 5a84: d9001617 ldw r4,88(sp) + 5a88: 980b883a mov r5,r19 + 5a8c: 01800284 movi r6,10 + 5a90: 000f883a mov r7,zero + 5a94: d8800615 stw r2,24(sp) + 5a98: 0008f4c0 call 8f4c <__multadd> + 5a9c: 1027883a mov r19,r2 + 5aa0: 003fc206 br 59ac <_dtoa_r+0x948> + 5aa4: 2445c83a sub r2,r4,r17 + 5aa8: a088983a sll r4,r20,r2 + 5aac: 003e4b06 br 53dc <_dtoa_r+0x378> + 5ab0: 01bfffc4 movi r6,-1 + 5ab4: 00800044 movi r2,1 + 5ab8: d9800e15 stw r6,56(sp) + 5abc: d9800f15 stw r6,60(sp) + 5ac0: d8800b15 stw r2,44(sp) + 5ac4: d8c01617 ldw r3,88(sp) + 5ac8: 008005c4 movi r2,23 + 5acc: 18001115 stw zero,68(r3) + 5ad0: 1580082e bgeu r2,r22,5af4 <_dtoa_r+0xa90> + 5ad4: 00c00104 movi r3,4 + 5ad8: 0009883a mov r4,zero + 5adc: 18c7883a add r3,r3,r3 + 5ae0: 18800504 addi r2,r3,20 + 5ae4: 21000044 addi r4,r4,1 + 5ae8: b0bffc2e bgeu r22,r2,5adc <_dtoa_r+0xa78> + 5aec: d9801617 ldw r6,88(sp) + 5af0: 31001115 stw r4,68(r6) + 5af4: dc000f17 ldw r16,60(sp) + 5af8: 003e4b06 br 5428 <_dtoa_r+0x3c4> + 5afc: d9801717 ldw r6,92(sp) + 5b00: 0023883a mov r17,zero + 5b04: 31bfff04 addi r6,r6,-4 + 5b08: d9801715 stw r6,92(sp) + 5b0c: 003df806 br 52f0 <_dtoa_r+0x28c> + 5b10: 00800804 movi r2,32 + 5b14: 10c9c83a sub r4,r2,r3 + 5b18: 00c00104 movi r3,4 + 5b1c: 19005a16 blt r3,r4,5c88 <_dtoa_r+0xc24> + 5b20: 008000c4 movi r2,3 + 5b24: 113f7e16 blt r2,r4,5920 <_dtoa_r+0x8bc> + 5b28: 20800704 addi r2,r4,28 + 5b2c: 003f7506 br 5904 <_dtoa_r+0x8a0> + 5b30: d9801717 ldw r6,92(sp) + 5b34: 00800044 movi r2,1 + 5b38: 1180a10e bge r2,r6,5dc0 <_dtoa_r+0xd5c> + 5b3c: d9800f17 ldw r6,60(sp) + 5b40: d8c01017 ldw r3,64(sp) + 5b44: 30bfffc4 addi r2,r6,-1 + 5b48: 1881c616 blt r3,r2,6264 <_dtoa_r+0x1200> + 5b4c: 18a5c83a sub r18,r3,r2 + 5b50: d8800f17 ldw r2,60(sp) + 5b54: 10026216 blt r2,zero,64e0 <_dtoa_r+0x147c> + 5b58: dc001117 ldw r16,68(sp) + 5b5c: 1007883a mov r3,r2 + 5b60: d9800a17 ldw r6,40(sp) + 5b64: d8801117 ldw r2,68(sp) + 5b68: d9001617 ldw r4,88(sp) + 5b6c: 30cd883a add r6,r6,r3 + 5b70: 10c5883a add r2,r2,r3 + 5b74: 01400044 movi r5,1 + 5b78: d9800a15 stw r6,40(sp) + 5b7c: d8801115 stw r2,68(sp) + 5b80: 0008f100 call 8f10 <__i2b> + 5b84: 1027883a mov r19,r2 + 5b88: 003f2506 br 5820 <_dtoa_r+0x7bc> + 5b8c: 00c00074 movhi r3,1 + 5b90: 18c0f104 addi r3,r3,964 + 5b94: 003d6706 br 5134 <_dtoa_r+0xd0> + 5b98: dd800517 ldw r22,20(sp) + 5b9c: 04000044 movi r16,1 + 5ba0: 00000706 br 5bc0 <_dtoa_r+0xb5c> + 5ba4: d9400717 ldw r5,28(sp) + 5ba8: d9001617 ldw r4,88(sp) + 5bac: 01800284 movi r6,10 + 5bb0: 000f883a mov r7,zero + 5bb4: 0008f4c0 call 8f4c <__multadd> + 5bb8: d8800715 stw r2,28(sp) + 5bbc: 84000044 addi r16,r16,1 + 5bc0: d9000717 ldw r4,28(sp) + 5bc4: 900b883a mov r5,r18 + 5bc8: 0004e200 call 4e20 + 5bcc: 15c00c04 addi r23,r2,48 + 5bd0: b5c00005 stb r23,0(r22) + 5bd4: d8c00f17 ldw r3,60(sp) + 5bd8: b5800044 addi r22,r22,1 + 5bdc: 80fff116 blt r16,r3,5ba4 <_dtoa_r+0xb40> + 5be0: d8000615 stw zero,24(sp) + 5be4: d9400717 ldw r5,28(sp) + 5be8: d9001617 ldw r4,88(sp) + 5bec: 01800044 movi r6,1 + 5bf0: 0008b700 call 8b70 <__lshift> + 5bf4: 1009883a mov r4,r2 + 5bf8: 900b883a mov r5,r18 + 5bfc: d8800715 stw r2,28(sp) + 5c00: 00083880 call 8388 <__mcmp> + 5c04: 00803c0e bge zero,r2,5cf8 <_dtoa_r+0xc94> + 5c08: b009883a mov r4,r22 + 5c0c: 213fffc4 addi r4,r4,-1 + 5c10: 21400003 ldbu r5,0(r4) + 5c14: 00800e44 movi r2,57 + 5c18: 28c03fcc andi r3,r5,255 + 5c1c: 18c0201c xori r3,r3,128 + 5c20: 18ffe004 addi r3,r3,-128 + 5c24: 1881981e bne r3,r2,6288 <_dtoa_r+0x1224> + 5c28: d9800517 ldw r6,20(sp) + 5c2c: 21bff71e bne r4,r6,5c0c <_dtoa_r+0xba8> + 5c30: d8800d17 ldw r2,52(sp) + 5c34: 37000044 addi fp,r6,1 + 5c38: 10800044 addi r2,r2,1 + 5c3c: d8800d15 stw r2,52(sp) + 5c40: 00800c44 movi r2,49 + 5c44: 30800005 stb r2,0(r6) + 5c48: d9001617 ldw r4,88(sp) + 5c4c: 900b883a mov r5,r18 + 5c50: 000822c0 call 822c <_Bfree> + 5c54: 983ecd26 beq r19,zero,578c <_dtoa_r+0x728> + 5c58: d8c00617 ldw r3,24(sp) + 5c5c: 18000426 beq r3,zero,5c70 <_dtoa_r+0xc0c> + 5c60: 1cc00326 beq r3,r19,5c70 <_dtoa_r+0xc0c> + 5c64: d9001617 ldw r4,88(sp) + 5c68: 180b883a mov r5,r3 + 5c6c: 000822c0 call 822c <_Bfree> + 5c70: d9001617 ldw r4,88(sp) + 5c74: 980b883a mov r5,r19 + 5c78: 000822c0 call 822c <_Bfree> + 5c7c: 003ec306 br 578c <_dtoa_r+0x728> + 5c80: 1805883a mov r2,r3 + 5c84: 003eeb06 br 5834 <_dtoa_r+0x7d0> + 5c88: d9800a17 ldw r6,40(sp) + 5c8c: d8c01117 ldw r3,68(sp) + 5c90: 20bfff04 addi r2,r4,-4 + 5c94: 308d883a add r6,r6,r2 + 5c98: 1887883a add r3,r3,r2 + 5c9c: 80a1883a add r16,r16,r2 + 5ca0: d9800a15 stw r6,40(sp) + 5ca4: d8c01115 stw r3,68(sp) + 5ca8: 003f1d06 br 5920 <_dtoa_r+0x8bc> + 5cac: a03f0c1e bne r20,zero,58e0 <_dtoa_r+0x87c> + 5cb0: 00800434 movhi r2,16 + 5cb4: 10bfffc4 addi r2,r2,-1 + 5cb8: a884703a and r2,r21,r2 + 5cbc: 103f081e bne r2,zero,58e0 <_dtoa_r+0x87c> + 5cc0: a89ffc2c andhi r2,r21,32752 + 5cc4: 103f0626 beq r2,zero,58e0 <_dtoa_r+0x87c> + 5cc8: d8c01117 ldw r3,68(sp) + 5ccc: d9000a17 ldw r4,40(sp) + 5cd0: 18c00044 addi r3,r3,1 + 5cd4: 21000044 addi r4,r4,1 + 5cd8: d8c01115 stw r3,68(sp) + 5cdc: d9000a15 stw r4,40(sp) + 5ce0: 003f0006 br 58e4 <_dtoa_r+0x880> + 5ce4: d9400717 ldw r5,28(sp) + 5ce8: d9001617 ldw r4,88(sp) + 5cec: 00090780 call 9078 <__pow5mult> + 5cf0: d8800715 stw r2,28(sp) + 5cf4: 003eed06 br 58ac <_dtoa_r+0x848> + 5cf8: 1000021e bne r2,zero,5d04 <_dtoa_r+0xca0> + 5cfc: b880004c andi r2,r23,1 + 5d00: 103fc11e bne r2,zero,5c08 <_dtoa_r+0xba4> + 5d04: b5bfffc4 addi r22,r22,-1 + 5d08: b0c00007 ldb r3,0(r22) + 5d0c: 00800c04 movi r2,48 + 5d10: 18bffc26 beq r3,r2,5d04 <_dtoa_r+0xca0> + 5d14: b7000044 addi fp,r22,1 + 5d18: 003fcb06 br 5c48 <_dtoa_r+0xbe4> + 5d1c: d9800d17 ldw r6,52(sp) + 5d20: 018fc83a sub r7,zero,r6 + 5d24: 3801f726 beq r7,zero,6504 <_dtoa_r+0x14a0> + 5d28: 398003cc andi r6,r7,15 + 5d2c: 300c90fa slli r6,r6,3 + 5d30: 01400074 movhi r5,1 + 5d34: 29410f04 addi r5,r5,1084 + 5d38: d9001217 ldw r4,72(sp) + 5d3c: 314d883a add r6,r6,r5 + 5d40: 30c00117 ldw r3,4(r6) + 5d44: 30800017 ldw r2,0(r6) + 5d48: d9401317 ldw r5,76(sp) + 5d4c: 3821d13a srai r16,r7,4 + 5d50: 100d883a mov r6,r2 + 5d54: 180f883a mov r7,r3 + 5d58: 000b20c0 call b20c <__muldf3> + 5d5c: 1011883a mov r8,r2 + 5d60: 1813883a mov r9,r3 + 5d64: 1029883a mov r20,r2 + 5d68: 182b883a mov r21,r3 + 5d6c: 8001e526 beq r16,zero,6504 <_dtoa_r+0x14a0> + 5d70: 05800084 movi r22,2 + 5d74: 04400074 movhi r17,1 + 5d78: 8c414104 addi r17,r17,1284 + 5d7c: 8080004c andi r2,r16,1 + 5d80: 1005003a cmpeq r2,r2,zero + 5d84: 1000081e bne r2,zero,5da8 <_dtoa_r+0xd44> + 5d88: 89800017 ldw r6,0(r17) + 5d8c: 89c00117 ldw r7,4(r17) + 5d90: 480b883a mov r5,r9 + 5d94: 4009883a mov r4,r8 + 5d98: 000b20c0 call b20c <__muldf3> + 5d9c: 1011883a mov r8,r2 + 5da0: b5800044 addi r22,r22,1 + 5da4: 1813883a mov r9,r3 + 5da8: 8021d07a srai r16,r16,1 + 5dac: 8c400204 addi r17,r17,8 + 5db0: 803ff21e bne r16,zero,5d7c <_dtoa_r+0xd18> + 5db4: 4029883a mov r20,r8 + 5db8: 482b883a mov r21,r9 + 5dbc: 003dca06 br 54e8 <_dtoa_r+0x484> + 5dc0: d9000817 ldw r4,32(sp) + 5dc4: 2005003a cmpeq r2,r4,zero + 5dc8: 1001f61e bne r2,zero,65a4 <_dtoa_r+0x1540> + 5dcc: dc001117 ldw r16,68(sp) + 5dd0: dc801017 ldw r18,64(sp) + 5dd4: 18c10cc4 addi r3,r3,1075 + 5dd8: 003f6106 br 5b60 <_dtoa_r+0xafc> + 5ddc: d8000b15 stw zero,44(sp) + 5de0: d9802617 ldw r6,152(sp) + 5de4: d8c00d17 ldw r3,52(sp) + 5de8: 30800044 addi r2,r6,1 + 5dec: 18ad883a add r22,r3,r2 + 5df0: b13fffc4 addi r4,r22,-1 + 5df4: d9000e15 stw r4,56(sp) + 5df8: 0581f60e bge zero,r22,65d4 <_dtoa_r+0x1570> + 5dfc: dd800f15 stw r22,60(sp) + 5e00: 003f3006 br 5ac4 <_dtoa_r+0xa60> + 5e04: d8000b15 stw zero,44(sp) + 5e08: d9002617 ldw r4,152(sp) + 5e0c: 0101eb0e bge zero,r4,65bc <_dtoa_r+0x1558> + 5e10: 202d883a mov r22,r4 + 5e14: d9000e15 stw r4,56(sp) + 5e18: d9000f15 stw r4,60(sp) + 5e1c: 003f2906 br 5ac4 <_dtoa_r+0xa60> + 5e20: 01800044 movi r6,1 + 5e24: d9800b15 stw r6,44(sp) + 5e28: 003ff706 br 5e08 <_dtoa_r+0xda4> + 5e2c: 01000044 movi r4,1 + 5e30: d9000b15 stw r4,44(sp) + 5e34: 003fea06 br 5de0 <_dtoa_r+0xd7c> + 5e38: 04000c0e bge zero,r16,5e6c <_dtoa_r+0xe08> + 5e3c: d9400717 ldw r5,28(sp) + 5e40: d9001617 ldw r4,88(sp) + 5e44: 01800044 movi r6,1 + 5e48: 0008b700 call 8b70 <__lshift> + 5e4c: 1009883a mov r4,r2 + 5e50: 900b883a mov r5,r18 + 5e54: d8800715 stw r2,28(sp) + 5e58: 00083880 call 8388 <__mcmp> + 5e5c: 0081e00e bge zero,r2,65e0 <_dtoa_r+0x157c> + 5e60: bdc00044 addi r23,r23,1 + 5e64: 00800e84 movi r2,58 + 5e68: b881a226 beq r23,r2,64f4 <_dtoa_r+0x1490> + 5e6c: b7000044 addi fp,r22,1 + 5e70: b5c00005 stb r23,0(r22) + 5e74: 003f7406 br 5c48 <_dtoa_r+0xbe4> + 5e78: 00800e44 movi r2,57 + 5e7c: b8819d26 beq r23,r2,64f4 <_dtoa_r+0x1490> + 5e80: 053ffa0e bge zero,r20,5e6c <_dtoa_r+0xe08> + 5e84: 8dc00c44 addi r23,r17,49 + 5e88: 003ff806 br 5e6c <_dtoa_r+0xe08> + 5e8c: d9001617 ldw r4,88(sp) + 5e90: a80b883a mov r5,r21 + 5e94: 04000044 movi r16,1 + 5e98: 000822c0 call 822c <_Bfree> + 5e9c: 003edf06 br 5a1c <_dtoa_r+0x9b8> + 5ea0: d9001617 ldw r4,88(sp) + 5ea4: 980b883a mov r5,r19 + 5ea8: 01800284 movi r6,10 + 5eac: 000f883a mov r7,zero + 5eb0: 0008f4c0 call 8f4c <__multadd> + 5eb4: 1027883a mov r19,r2 + 5eb8: d8800615 stw r2,24(sp) + 5ebc: 003ebb06 br 59ac <_dtoa_r+0x948> + 5ec0: d9801117 ldw r6,68(sp) + 5ec4: d8800d17 ldw r2,52(sp) + 5ec8: d8000915 stw zero,36(sp) + 5ecc: 308dc83a sub r6,r6,r2 + 5ed0: 0087c83a sub r3,zero,r2 + 5ed4: d9801115 stw r6,68(sp) + 5ed8: d8c01015 stw r3,64(sp) + 5edc: 003cfe06 br 52d8 <_dtoa_r+0x274> + 5ee0: 018dc83a sub r6,zero,r6 + 5ee4: d9801115 stw r6,68(sp) + 5ee8: d8000a15 stw zero,40(sp) + 5eec: 003cf306 br 52bc <_dtoa_r+0x258> + 5ef0: d9000d17 ldw r4,52(sp) + 5ef4: 000bad00 call bad0 <__floatsidf> + 5ef8: 880b883a mov r5,r17 + 5efc: 8009883a mov r4,r16 + 5f00: 180f883a mov r7,r3 + 5f04: 100d883a mov r6,r2 + 5f08: 000b8b00 call b8b0 <__nedf2> + 5f0c: 103ce126 beq r2,zero,5294 <_dtoa_r+0x230> + 5f10: d9800d17 ldw r6,52(sp) + 5f14: 31bfffc4 addi r6,r6,-1 + 5f18: d9800d15 stw r6,52(sp) + 5f1c: 003cdd06 br 5294 <_dtoa_r+0x230> + 5f20: d9000717 ldw r4,28(sp) + 5f24: 900b883a mov r5,r18 + 5f28: 00083880 call 8388 <__mcmp> + 5f2c: 103e8d0e bge r2,zero,5964 <_dtoa_r+0x900> + 5f30: d9400717 ldw r5,28(sp) + 5f34: d9001617 ldw r4,88(sp) + 5f38: 01800284 movi r6,10 + 5f3c: 000f883a mov r7,zero + 5f40: 0008f4c0 call 8f4c <__multadd> + 5f44: d9800d17 ldw r6,52(sp) + 5f48: d8800715 stw r2,28(sp) + 5f4c: 31bfffc4 addi r6,r6,-1 + 5f50: d9800d15 stw r6,52(sp) + 5f54: b001a71e bne r22,zero,65f4 <_dtoa_r+0x1590> + 5f58: d8800e17 ldw r2,56(sp) + 5f5c: d8800f15 stw r2,60(sp) + 5f60: 003e8006 br 5964 <_dtoa_r+0x900> + 5f64: 90800417 ldw r2,16(r18) + 5f68: 1085883a add r2,r2,r2 + 5f6c: 1085883a add r2,r2,r2 + 5f70: 1485883a add r2,r2,r18 + 5f74: 11000417 ldw r4,16(r2) + 5f78: 00082540 call 8254 <__hi0bits> + 5f7c: 00c00804 movi r3,32 + 5f80: 1887c83a sub r3,r3,r2 + 5f84: 003e5a06 br 58f0 <_dtoa_r+0x88c> + 5f88: d9400717 ldw r5,28(sp) + 5f8c: d9801017 ldw r6,64(sp) + 5f90: d9001617 ldw r4,88(sp) + 5f94: 00090780 call 9078 <__pow5mult> + 5f98: d8800715 stw r2,28(sp) + 5f9c: 003e4306 br 58ac <_dtoa_r+0x848> + 5fa0: d9800f17 ldw r6,60(sp) + 5fa4: d8800d17 ldw r2,52(sp) + 5fa8: d9800315 stw r6,12(sp) + 5fac: d8800415 stw r2,16(sp) + 5fb0: d8c00b17 ldw r3,44(sp) + 5fb4: 1805003a cmpeq r2,r3,zero + 5fb8: 1000e21e bne r2,zero,6344 <_dtoa_r+0x12e0> + 5fbc: d9000317 ldw r4,12(sp) + 5fc0: 0005883a mov r2,zero + 5fc4: 00cff834 movhi r3,16352 + 5fc8: 200c90fa slli r6,r4,3 + 5fcc: 01000074 movhi r4,1 + 5fd0: 21010f04 addi r4,r4,1084 + 5fd4: 180b883a mov r5,r3 + 5fd8: 310d883a add r6,r6,r4 + 5fdc: 327fff17 ldw r9,-4(r6) + 5fe0: 323ffe17 ldw r8,-8(r6) + 5fe4: 1009883a mov r4,r2 + 5fe8: 480f883a mov r7,r9 + 5fec: 400d883a mov r6,r8 + 5ff0: 000b5d00 call b5d0 <__divdf3> + 5ff4: 180b883a mov r5,r3 + 5ff8: b00d883a mov r6,r22 + 5ffc: b80f883a mov r7,r23 + 6000: 1009883a mov r4,r2 + 6004: 000b1180 call b118 <__subdf3> + 6008: a80b883a mov r5,r21 + 600c: a009883a mov r4,r20 + 6010: d8c01915 stw r3,100(sp) + 6014: d8801815 stw r2,96(sp) + 6018: 000bbc80 call bbc8 <__fixdfsi> + 601c: 1009883a mov r4,r2 + 6020: 1027883a mov r19,r2 + 6024: 000bad00 call bad0 <__floatsidf> + 6028: a80b883a mov r5,r21 + 602c: a009883a mov r4,r20 + 6030: 180f883a mov r7,r3 + 6034: 100d883a mov r6,r2 + 6038: 000b1180 call b118 <__subdf3> + 603c: d9801817 ldw r6,96(sp) + 6040: 1823883a mov r17,r3 + 6044: d8801415 stw r2,80(sp) + 6048: 302d883a mov r22,r6 + 604c: d9800517 ldw r6,20(sp) + 6050: 9cc00c04 addi r19,r19,48 + 6054: dc401515 stw r17,84(sp) + 6058: d8c01917 ldw r3,100(sp) + 605c: 34c00005 stb r19,0(r6) + 6060: d8800517 ldw r2,20(sp) + 6064: d9401917 ldw r5,100(sp) + 6068: d9801417 ldw r6,80(sp) + 606c: b009883a mov r4,r22 + 6070: 880f883a mov r7,r17 + 6074: 182f883a mov r23,r3 + 6078: 17000044 addi fp,r2,1 + 607c: 000b9380 call b938 <__gtdf2> + 6080: 00804e16 blt zero,r2,61bc <_dtoa_r+0x1158> + 6084: d9801417 ldw r6,80(sp) + 6088: 0005883a mov r2,zero + 608c: 00cffc34 movhi r3,16368 + 6090: 180b883a mov r5,r3 + 6094: 880f883a mov r7,r17 + 6098: 1009883a mov r4,r2 + 609c: 000b1180 call b118 <__subdf3> + 60a0: d9401917 ldw r5,100(sp) + 60a4: 180f883a mov r7,r3 + 60a8: b009883a mov r4,r22 + 60ac: 100d883a mov r6,r2 + 60b0: 000b9380 call b938 <__gtdf2> + 60b4: 00bda216 blt zero,r2,5740 <_dtoa_r+0x6dc> + 60b8: d8c00317 ldw r3,12(sp) + 60bc: 00800044 movi r2,1 + 60c0: 10c01216 blt r2,r3,610c <_dtoa_r+0x10a8> + 60c4: 003d4506 br 55dc <_dtoa_r+0x578> + 60c8: d9801417 ldw r6,80(sp) + 60cc: 0005883a mov r2,zero + 60d0: 00cffc34 movhi r3,16368 + 60d4: 180b883a mov r5,r3 + 60d8: 880f883a mov r7,r17 + 60dc: 1009883a mov r4,r2 + 60e0: 000b1180 call b118 <__subdf3> + 60e4: d9c01b17 ldw r7,108(sp) + 60e8: 180b883a mov r5,r3 + 60ec: 1009883a mov r4,r2 + 60f0: b00d883a mov r6,r22 + 60f4: 000ba480 call ba48 <__ltdf2> + 60f8: 103d9116 blt r2,zero,5740 <_dtoa_r+0x6dc> + 60fc: d9800517 ldw r6,20(sp) + 6100: d9000317 ldw r4,12(sp) + 6104: 3105883a add r2,r6,r4 + 6108: e0bd3426 beq fp,r2,55dc <_dtoa_r+0x578> + 610c: 04500934 movhi r17,16420 + 6110: 0021883a mov r16,zero + 6114: b80b883a mov r5,r23 + 6118: b009883a mov r4,r22 + 611c: 800d883a mov r6,r16 + 6120: 880f883a mov r7,r17 + 6124: 000b20c0 call b20c <__muldf3> + 6128: d9401517 ldw r5,84(sp) + 612c: d9001417 ldw r4,80(sp) + 6130: 880f883a mov r7,r17 + 6134: 000d883a mov r6,zero + 6138: d8801a15 stw r2,104(sp) + 613c: d8c01b15 stw r3,108(sp) + 6140: 000b20c0 call b20c <__muldf3> + 6144: 180b883a mov r5,r3 + 6148: 1009883a mov r4,r2 + 614c: 1823883a mov r17,r3 + 6150: 1021883a mov r16,r2 + 6154: 000bbc80 call bbc8 <__fixdfsi> + 6158: 1009883a mov r4,r2 + 615c: 102b883a mov r21,r2 + 6160: 000bad00 call bad0 <__floatsidf> + 6164: 880b883a mov r5,r17 + 6168: 8009883a mov r4,r16 + 616c: 180f883a mov r7,r3 + 6170: 100d883a mov r6,r2 + 6174: 000b1180 call b118 <__subdf3> + 6178: 1021883a mov r16,r2 + 617c: d9001b17 ldw r4,108(sp) + 6180: 1823883a mov r17,r3 + 6184: dc001415 stw r16,80(sp) + 6188: ad400c04 addi r21,r21,48 + 618c: dc401515 stw r17,84(sp) + 6190: d8801a17 ldw r2,104(sp) + 6194: e5400005 stb r21,0(fp) + 6198: 202f883a mov r23,r4 + 619c: d9c01b17 ldw r7,108(sp) + 61a0: d9001417 ldw r4,80(sp) + 61a4: 880b883a mov r5,r17 + 61a8: 100d883a mov r6,r2 + 61ac: 102d883a mov r22,r2 + 61b0: e7000044 addi fp,fp,1 + 61b4: 000ba480 call ba48 <__ltdf2> + 61b8: 103fc30e bge r2,zero,60c8 <_dtoa_r+0x1064> + 61bc: d9000417 ldw r4,16(sp) + 61c0: d9000d15 stw r4,52(sp) + 61c4: 003d7106 br 578c <_dtoa_r+0x728> + 61c8: d9801717 ldw r6,92(sp) + 61cc: 00800084 movi r2,2 + 61d0: 11bde60e bge r2,r6,596c <_dtoa_r+0x908> + 61d4: 203cfb1e bne r4,zero,55c4 <_dtoa_r+0x560> + 61d8: d9001617 ldw r4,88(sp) + 61dc: 900b883a mov r5,r18 + 61e0: 01800144 movi r6,5 + 61e4: 000f883a mov r7,zero + 61e8: 0008f4c0 call 8f4c <__multadd> + 61ec: d9000717 ldw r4,28(sp) + 61f0: 100b883a mov r5,r2 + 61f4: 1025883a mov r18,r2 + 61f8: 00083880 call 8388 <__mcmp> + 61fc: 00bcf10e bge zero,r2,55c4 <_dtoa_r+0x560> + 6200: d8c00d17 ldw r3,52(sp) + 6204: d9000517 ldw r4,20(sp) + 6208: d8000615 stw zero,24(sp) + 620c: 18c00044 addi r3,r3,1 + 6210: d8c00d15 stw r3,52(sp) + 6214: 00800c44 movi r2,49 + 6218: 27000044 addi fp,r4,1 + 621c: 20800005 stb r2,0(r4) + 6220: 003e8906 br 5c48 <_dtoa_r+0xbe4> + 6224: d8c00517 ldw r3,20(sp) + 6228: 003bc206 br 5134 <_dtoa_r+0xd0> + 622c: 01800074 movhi r6,1 + 6230: 31814104 addi r6,r6,1284 + 6234: 30c00917 ldw r3,36(r6) + 6238: 30800817 ldw r2,32(r6) + 623c: d9001217 ldw r4,72(sp) + 6240: d9401317 ldw r5,76(sp) + 6244: 180f883a mov r7,r3 + 6248: 100d883a mov r6,r2 + 624c: 000b5d00 call b5d0 <__divdf3> + 6250: 948003cc andi r18,r18,15 + 6254: 058000c4 movi r22,3 + 6258: 1029883a mov r20,r2 + 625c: 182b883a mov r21,r3 + 6260: 003c8906 br 5488 <_dtoa_r+0x424> + 6264: d9001017 ldw r4,64(sp) + 6268: d9800917 ldw r6,36(sp) + 626c: 0025883a mov r18,zero + 6270: 1105c83a sub r2,r2,r4 + 6274: 2089883a add r4,r4,r2 + 6278: 308d883a add r6,r6,r2 + 627c: d9001015 stw r4,64(sp) + 6280: d9800915 stw r6,36(sp) + 6284: 003e3206 br 5b50 <_dtoa_r+0xaec> + 6288: 28800044 addi r2,r5,1 + 628c: 27000044 addi fp,r4,1 + 6290: 20800005 stb r2,0(r4) + 6294: 003e6c06 br 5c48 <_dtoa_r+0xbe4> + 6298: d8800f17 ldw r2,60(sp) + 629c: 00bce016 blt zero,r2,5620 <_dtoa_r+0x5bc> + 62a0: d9800f17 ldw r6,60(sp) + 62a4: 303cc51e bne r6,zero,55bc <_dtoa_r+0x558> + 62a8: 0005883a mov r2,zero + 62ac: 00d00534 movhi r3,16404 + 62b0: 980b883a mov r5,r19 + 62b4: 180f883a mov r7,r3 + 62b8: 9009883a mov r4,r18 + 62bc: 100d883a mov r6,r2 + 62c0: 000b20c0 call b20c <__muldf3> + 62c4: 180b883a mov r5,r3 + 62c8: a80f883a mov r7,r21 + 62cc: 1009883a mov r4,r2 + 62d0: a00d883a mov r6,r20 + 62d4: 000b9c00 call b9c0 <__gedf2> + 62d8: 103cb80e bge r2,zero,55bc <_dtoa_r+0x558> + 62dc: 0027883a mov r19,zero + 62e0: 0025883a mov r18,zero + 62e4: 003fc606 br 6200 <_dtoa_r+0x119c> + 62e8: 99400117 ldw r5,4(r19) + 62ec: d9001617 ldw r4,88(sp) + 62f0: 00087ac0 call 87ac <_Balloc> + 62f4: 99800417 ldw r6,16(r19) + 62f8: 11000304 addi r4,r2,12 + 62fc: 99400304 addi r5,r19,12 + 6300: 318d883a add r6,r6,r6 + 6304: 318d883a add r6,r6,r6 + 6308: 31800204 addi r6,r6,8 + 630c: 1023883a mov r17,r2 + 6310: 00080140 call 8014 + 6314: d9001617 ldw r4,88(sp) + 6318: 880b883a mov r5,r17 + 631c: 01800044 movi r6,1 + 6320: 0008b700 call 8b70 <__lshift> + 6324: 100b883a mov r5,r2 + 6328: 003d9c06 br 599c <_dtoa_r+0x938> + 632c: 00800e44 movi r2,57 + 6330: b8807026 beq r23,r2,64f4 <_dtoa_r+0x1490> + 6334: b8800044 addi r2,r23,1 + 6338: b7000044 addi fp,r22,1 + 633c: b0800005 stb r2,0(r22) + 6340: 003e4106 br 5c48 <_dtoa_r+0xbe4> + 6344: d8800317 ldw r2,12(sp) + 6348: 01800074 movhi r6,1 + 634c: 31810f04 addi r6,r6,1084 + 6350: b009883a mov r4,r22 + 6354: 100e90fa slli r7,r2,3 + 6358: b80b883a mov r5,r23 + 635c: 398f883a add r7,r7,r6 + 6360: 38bffe17 ldw r2,-8(r7) + 6364: d9800517 ldw r6,20(sp) + 6368: 38ffff17 ldw r3,-4(r7) + 636c: 37000044 addi fp,r6,1 + 6370: 180f883a mov r7,r3 + 6374: 100d883a mov r6,r2 + 6378: 000b20c0 call b20c <__muldf3> + 637c: a80b883a mov r5,r21 + 6380: a009883a mov r4,r20 + 6384: 182f883a mov r23,r3 + 6388: 102d883a mov r22,r2 + 638c: 000bbc80 call bbc8 <__fixdfsi> + 6390: 1009883a mov r4,r2 + 6394: 1027883a mov r19,r2 + 6398: 000bad00 call bad0 <__floatsidf> + 639c: a80b883a mov r5,r21 + 63a0: a009883a mov r4,r20 + 63a4: 180f883a mov r7,r3 + 63a8: 100d883a mov r6,r2 + 63ac: 000b1180 call b118 <__subdf3> + 63b0: 180b883a mov r5,r3 + 63b4: d8c00517 ldw r3,20(sp) + 63b8: 9cc00c04 addi r19,r19,48 + 63bc: 1009883a mov r4,r2 + 63c0: 1cc00005 stb r19,0(r3) + 63c4: 2021883a mov r16,r4 + 63c8: d9000317 ldw r4,12(sp) + 63cc: 00800044 movi r2,1 + 63d0: 2823883a mov r17,r5 + 63d4: 20802226 beq r4,r2,6460 <_dtoa_r+0x13fc> + 63d8: 1029883a mov r20,r2 + 63dc: 0005883a mov r2,zero + 63e0: 00d00934 movhi r3,16420 + 63e4: 180f883a mov r7,r3 + 63e8: 100d883a mov r6,r2 + 63ec: 880b883a mov r5,r17 + 63f0: 8009883a mov r4,r16 + 63f4: 000b20c0 call b20c <__muldf3> + 63f8: 180b883a mov r5,r3 + 63fc: 1009883a mov r4,r2 + 6400: 1823883a mov r17,r3 + 6404: 1021883a mov r16,r2 + 6408: 000bbc80 call bbc8 <__fixdfsi> + 640c: 1009883a mov r4,r2 + 6410: 102b883a mov r21,r2 + 6414: 000bad00 call bad0 <__floatsidf> + 6418: 880b883a mov r5,r17 + 641c: 8009883a mov r4,r16 + 6420: 180f883a mov r7,r3 + 6424: 100d883a mov r6,r2 + 6428: 000b1180 call b118 <__subdf3> + 642c: 180b883a mov r5,r3 + 6430: d8c00517 ldw r3,20(sp) + 6434: 1009883a mov r4,r2 + 6438: ad400c04 addi r21,r21,48 + 643c: 1d05883a add r2,r3,r20 + 6440: 15400005 stb r21,0(r2) + 6444: 2021883a mov r16,r4 + 6448: d9000317 ldw r4,12(sp) + 644c: a5000044 addi r20,r20,1 + 6450: 2823883a mov r17,r5 + 6454: a13fe11e bne r20,r4,63dc <_dtoa_r+0x1378> + 6458: e505883a add r2,fp,r20 + 645c: 173fffc4 addi fp,r2,-1 + 6460: 0025883a mov r18,zero + 6464: 04cff834 movhi r19,16352 + 6468: b009883a mov r4,r22 + 646c: b80b883a mov r5,r23 + 6470: 900d883a mov r6,r18 + 6474: 980f883a mov r7,r19 + 6478: 000b1980 call b198 <__adddf3> + 647c: 180b883a mov r5,r3 + 6480: 1009883a mov r4,r2 + 6484: 800d883a mov r6,r16 + 6488: 880f883a mov r7,r17 + 648c: 000ba480 call ba48 <__ltdf2> + 6490: 103cab16 blt r2,zero,5740 <_dtoa_r+0x6dc> + 6494: 0009883a mov r4,zero + 6498: 980b883a mov r5,r19 + 649c: b80f883a mov r7,r23 + 64a0: b00d883a mov r6,r22 + 64a4: 000b1180 call b118 <__subdf3> + 64a8: 180b883a mov r5,r3 + 64ac: 880f883a mov r7,r17 + 64b0: 1009883a mov r4,r2 + 64b4: 800d883a mov r6,r16 + 64b8: 000b9380 call b938 <__gtdf2> + 64bc: 00bc470e bge zero,r2,55dc <_dtoa_r+0x578> + 64c0: 00c00c04 movi r3,48 + 64c4: e73fffc4 addi fp,fp,-1 + 64c8: e0800007 ldb r2,0(fp) + 64cc: 10fffd26 beq r2,r3,64c4 <_dtoa_r+0x1460> + 64d0: d9800417 ldw r6,16(sp) + 64d4: e7000044 addi fp,fp,1 + 64d8: d9800d15 stw r6,52(sp) + 64dc: 003cab06 br 578c <_dtoa_r+0x728> + 64e0: d8c00f17 ldw r3,60(sp) + 64e4: d9001117 ldw r4,68(sp) + 64e8: 20e1c83a sub r16,r4,r3 + 64ec: 0007883a mov r3,zero + 64f0: 003d9b06 br 5b60 <_dtoa_r+0xafc> + 64f4: 00800e44 movi r2,57 + 64f8: b0800005 stb r2,0(r22) + 64fc: b5800044 addi r22,r22,1 + 6500: 003dc106 br 5c08 <_dtoa_r+0xba4> + 6504: 05800084 movi r22,2 + 6508: 003bf706 br 54e8 <_dtoa_r+0x484> + 650c: d9000f17 ldw r4,60(sp) + 6510: 013c000e bge zero,r4,5514 <_dtoa_r+0x4b0> + 6514: d9800e17 ldw r6,56(sp) + 6518: 01bc300e bge zero,r6,55dc <_dtoa_r+0x578> + 651c: 0005883a mov r2,zero + 6520: 00d00934 movhi r3,16420 + 6524: a80b883a mov r5,r21 + 6528: 180f883a mov r7,r3 + 652c: a009883a mov r4,r20 + 6530: 100d883a mov r6,r2 + 6534: 000b20c0 call b20c <__muldf3> + 6538: b1000044 addi r4,r22,1 + 653c: 1021883a mov r16,r2 + 6540: 1823883a mov r17,r3 + 6544: 000bad00 call bad0 <__floatsidf> + 6548: 880b883a mov r5,r17 + 654c: 8009883a mov r4,r16 + 6550: 180f883a mov r7,r3 + 6554: 100d883a mov r6,r2 + 6558: 000b20c0 call b20c <__muldf3> + 655c: 0011883a mov r8,zero + 6560: 02500734 movhi r9,16412 + 6564: 180b883a mov r5,r3 + 6568: 480f883a mov r7,r9 + 656c: 1009883a mov r4,r2 + 6570: 400d883a mov r6,r8 + 6574: 000b1980 call b198 <__adddf3> + 6578: 102d883a mov r22,r2 + 657c: 00bf3034 movhi r2,64704 + 6580: 10ef883a add r23,r2,r3 + 6584: d8800d17 ldw r2,52(sp) + 6588: d8c00e17 ldw r3,56(sp) + 658c: 8029883a mov r20,r16 + 6590: 10bfffc4 addi r2,r2,-1 + 6594: 882b883a mov r21,r17 + 6598: d8800415 stw r2,16(sp) + 659c: d8c00315 stw r3,12(sp) + 65a0: 003e8306 br 5fb0 <_dtoa_r+0xf4c> + 65a4: d8800117 ldw r2,4(sp) + 65a8: dc001117 ldw r16,68(sp) + 65ac: dc801017 ldw r18,64(sp) + 65b0: 00c00d84 movi r3,54 + 65b4: 1887c83a sub r3,r3,r2 + 65b8: 003d6906 br 5b60 <_dtoa_r+0xafc> + 65bc: 01800044 movi r6,1 + 65c0: 3021883a mov r16,r6 + 65c4: d9800f15 stw r6,60(sp) + 65c8: d9802615 stw r6,152(sp) + 65cc: d9800e15 stw r6,56(sp) + 65d0: 003b9306 br 5420 <_dtoa_r+0x3bc> + 65d4: b021883a mov r16,r22 + 65d8: dd800f15 stw r22,60(sp) + 65dc: 003b9006 br 5420 <_dtoa_r+0x3bc> + 65e0: 103e221e bne r2,zero,5e6c <_dtoa_r+0xe08> + 65e4: b880004c andi r2,r23,1 + 65e8: 1005003a cmpeq r2,r2,zero + 65ec: 103e1f1e bne r2,zero,5e6c <_dtoa_r+0xe08> + 65f0: 003e1b06 br 5e60 <_dtoa_r+0xdfc> + 65f4: d9001617 ldw r4,88(sp) + 65f8: 980b883a mov r5,r19 + 65fc: 01800284 movi r6,10 + 6600: 000f883a mov r7,zero + 6604: 0008f4c0 call 8f4c <__multadd> + 6608: d8c00e17 ldw r3,56(sp) + 660c: 1027883a mov r19,r2 + 6610: d8c00f15 stw r3,60(sp) + 6614: 003cd306 br 5964 <_dtoa_r+0x900> + +00006618 <_fflush_r>: + 6618: defffb04 addi sp,sp,-20 + 661c: dcc00315 stw r19,12(sp) + 6620: dc800215 stw r18,8(sp) + 6624: dfc00415 stw ra,16(sp) + 6628: dc400115 stw r17,4(sp) + 662c: dc000015 stw r16,0(sp) + 6630: 2027883a mov r19,r4 + 6634: 2825883a mov r18,r5 + 6638: 20000226 beq r4,zero,6644 <_fflush_r+0x2c> + 663c: 20800e17 ldw r2,56(r4) + 6640: 10005626 beq r2,zero,679c <_fflush_r+0x184> + 6644: 9100030b ldhu r4,12(r18) + 6648: 20ffffcc andi r3,r4,65535 + 664c: 18e0001c xori r3,r3,32768 + 6650: 18e00004 addi r3,r3,-32768 + 6654: 1880020c andi r2,r3,8 + 6658: 1000261e bne r2,zero,66f4 <_fflush_r+0xdc> + 665c: 90c00117 ldw r3,4(r18) + 6660: 20820014 ori r2,r4,2048 + 6664: 9080030d sth r2,12(r18) + 6668: 1009883a mov r4,r2 + 666c: 00c0400e bge zero,r3,6770 <_fflush_r+0x158> + 6670: 92000a17 ldw r8,40(r18) + 6674: 40004026 beq r8,zero,6778 <_fflush_r+0x160> + 6678: 2084000c andi r2,r4,4096 + 667c: 10005326 beq r2,zero,67cc <_fflush_r+0x1b4> + 6680: 94001417 ldw r16,80(r18) + 6684: 9080030b ldhu r2,12(r18) + 6688: 1080010c andi r2,r2,4 + 668c: 1000481e bne r2,zero,67b0 <_fflush_r+0x198> + 6690: 91400717 ldw r5,28(r18) + 6694: 9809883a mov r4,r19 + 6698: 800d883a mov r6,r16 + 669c: 000f883a mov r7,zero + 66a0: 403ee83a callr r8 + 66a4: 8080261e bne r16,r2,6740 <_fflush_r+0x128> + 66a8: 9080030b ldhu r2,12(r18) + 66ac: 91000417 ldw r4,16(r18) + 66b0: 90000115 stw zero,4(r18) + 66b4: 10bdffcc andi r2,r2,63487 + 66b8: 10ffffcc andi r3,r2,65535 + 66bc: 18c4000c andi r3,r3,4096 + 66c0: 9080030d sth r2,12(r18) + 66c4: 91000015 stw r4,0(r18) + 66c8: 18002b26 beq r3,zero,6778 <_fflush_r+0x160> + 66cc: 0007883a mov r3,zero + 66d0: 1805883a mov r2,r3 + 66d4: 94001415 stw r16,80(r18) + 66d8: dfc00417 ldw ra,16(sp) + 66dc: dcc00317 ldw r19,12(sp) + 66e0: dc800217 ldw r18,8(sp) + 66e4: dc400117 ldw r17,4(sp) + 66e8: dc000017 ldw r16,0(sp) + 66ec: dec00504 addi sp,sp,20 + 66f0: f800283a ret + 66f4: 94400417 ldw r17,16(r18) + 66f8: 88001f26 beq r17,zero,6778 <_fflush_r+0x160> + 66fc: 90800017 ldw r2,0(r18) + 6700: 18c000cc andi r3,r3,3 + 6704: 94400015 stw r17,0(r18) + 6708: 1461c83a sub r16,r2,r17 + 670c: 18002526 beq r3,zero,67a4 <_fflush_r+0x18c> + 6710: 0005883a mov r2,zero + 6714: 90800215 stw r2,8(r18) + 6718: 0400170e bge zero,r16,6778 <_fflush_r+0x160> + 671c: 90c00917 ldw r3,36(r18) + 6720: 91400717 ldw r5,28(r18) + 6724: 880d883a mov r6,r17 + 6728: 800f883a mov r7,r16 + 672c: 9809883a mov r4,r19 + 6730: 183ee83a callr r3 + 6734: 88a3883a add r17,r17,r2 + 6738: 80a1c83a sub r16,r16,r2 + 673c: 00bff616 blt zero,r2,6718 <_fflush_r+0x100> + 6740: 9080030b ldhu r2,12(r18) + 6744: 00ffffc4 movi r3,-1 + 6748: 10801014 ori r2,r2,64 + 674c: 9080030d sth r2,12(r18) + 6750: 1805883a mov r2,r3 + 6754: dfc00417 ldw ra,16(sp) + 6758: dcc00317 ldw r19,12(sp) + 675c: dc800217 ldw r18,8(sp) + 6760: dc400117 ldw r17,4(sp) + 6764: dc000017 ldw r16,0(sp) + 6768: dec00504 addi sp,sp,20 + 676c: f800283a ret + 6770: 90800f17 ldw r2,60(r18) + 6774: 00bfbe16 blt zero,r2,6670 <_fflush_r+0x58> + 6778: 0007883a mov r3,zero + 677c: 1805883a mov r2,r3 + 6780: dfc00417 ldw ra,16(sp) + 6784: dcc00317 ldw r19,12(sp) + 6788: dc800217 ldw r18,8(sp) + 678c: dc400117 ldw r17,4(sp) + 6790: dc000017 ldw r16,0(sp) + 6794: dec00504 addi sp,sp,20 + 6798: f800283a ret + 679c: 00068b00 call 68b0 <__sinit> + 67a0: 003fa806 br 6644 <_fflush_r+0x2c> + 67a4: 90800517 ldw r2,20(r18) + 67a8: 90800215 stw r2,8(r18) + 67ac: 003fda06 br 6718 <_fflush_r+0x100> + 67b0: 90800117 ldw r2,4(r18) + 67b4: 90c00c17 ldw r3,48(r18) + 67b8: 80a1c83a sub r16,r16,r2 + 67bc: 183fb426 beq r3,zero,6690 <_fflush_r+0x78> + 67c0: 90800f17 ldw r2,60(r18) + 67c4: 80a1c83a sub r16,r16,r2 + 67c8: 003fb106 br 6690 <_fflush_r+0x78> + 67cc: 91400717 ldw r5,28(r18) + 67d0: 9809883a mov r4,r19 + 67d4: 000d883a mov r6,zero + 67d8: 01c00044 movi r7,1 + 67dc: 403ee83a callr r8 + 67e0: 1021883a mov r16,r2 + 67e4: 00bfffc4 movi r2,-1 + 67e8: 80800226 beq r16,r2,67f4 <_fflush_r+0x1dc> + 67ec: 92000a17 ldw r8,40(r18) + 67f0: 003fa406 br 6684 <_fflush_r+0x6c> + 67f4: 98c00017 ldw r3,0(r19) + 67f8: 00800744 movi r2,29 + 67fc: 18bfde26 beq r3,r2,6778 <_fflush_r+0x160> + 6800: 9080030b ldhu r2,12(r18) + 6804: 8007883a mov r3,r16 + 6808: 10801014 ori r2,r2,64 + 680c: 9080030d sth r2,12(r18) + 6810: 003fcf06 br 6750 <_fflush_r+0x138> + +00006814 : + 6814: 01400034 movhi r5,0 + 6818: 29598604 addi r5,r5,26136 + 681c: 2007883a mov r3,r4 + 6820: 20000526 beq r4,zero,6838 + 6824: 00800074 movhi r2,1 + 6828: 10887e04 addi r2,r2,8696 + 682c: 11000017 ldw r4,0(r2) + 6830: 180b883a mov r5,r3 + 6834: 00066181 jmpi 6618 <_fflush_r> + 6838: 00800074 movhi r2,1 + 683c: 10887f04 addi r2,r2,8700 + 6840: 11000017 ldw r4,0(r2) + 6844: 00074181 jmpi 7418 <_fwalk_reent> + +00006848 : + 6848: 00800074 movhi r2,1 + 684c: 10a66304 addi r2,r2,-26228 + 6850: 20800b15 stw r2,44(r4) + 6854: 00800074 movhi r2,1 + 6858: 10a69e04 addi r2,r2,-25992 + 685c: 20800815 stw r2,32(r4) + 6860: 00c00074 movhi r3,1 + 6864: 18e67f04 addi r3,r3,-26116 + 6868: 00800074 movhi r2,1 + 686c: 10a66504 addi r2,r2,-26220 + 6870: 2140030d sth r5,12(r4) + 6874: 2180038d sth r6,14(r4) + 6878: 20c00915 stw r3,36(r4) + 687c: 20800a15 stw r2,40(r4) + 6880: 20000015 stw zero,0(r4) + 6884: 20000115 stw zero,4(r4) + 6888: 20000215 stw zero,8(r4) + 688c: 20000415 stw zero,16(r4) + 6890: 20000515 stw zero,20(r4) + 6894: 20000615 stw zero,24(r4) + 6898: 21000715 stw r4,28(r4) + 689c: f800283a ret + +000068a0 <__sfp_lock_acquire>: + 68a0: f800283a ret + +000068a4 <__sfp_lock_release>: + 68a4: f800283a ret + +000068a8 <__sinit_lock_acquire>: + 68a8: f800283a ret + +000068ac <__sinit_lock_release>: + 68ac: f800283a ret + +000068b0 <__sinit>: + 68b0: 20800e17 ldw r2,56(r4) + 68b4: defffd04 addi sp,sp,-12 + 68b8: dc400115 stw r17,4(sp) + 68bc: dc000015 stw r16,0(sp) + 68c0: dfc00215 stw ra,8(sp) + 68c4: 04400044 movi r17,1 + 68c8: 01400104 movi r5,4 + 68cc: 000d883a mov r6,zero + 68d0: 2021883a mov r16,r4 + 68d4: 2200bb04 addi r8,r4,748 + 68d8: 200f883a mov r7,r4 + 68dc: 10000526 beq r2,zero,68f4 <__sinit+0x44> + 68e0: dfc00217 ldw ra,8(sp) + 68e4: dc400117 ldw r17,4(sp) + 68e8: dc000017 ldw r16,0(sp) + 68ec: dec00304 addi sp,sp,12 + 68f0: f800283a ret + 68f4: 21000117 ldw r4,4(r4) + 68f8: 00800034 movhi r2,0 + 68fc: 109a6504 addi r2,r2,27028 + 6900: 00c000c4 movi r3,3 + 6904: 80800f15 stw r2,60(r16) + 6908: 80c0b915 stw r3,740(r16) + 690c: 8200ba15 stw r8,744(r16) + 6910: 84400e15 stw r17,56(r16) + 6914: 8000b815 stw zero,736(r16) + 6918: 00068480 call 6848 + 691c: 81000217 ldw r4,8(r16) + 6920: 880d883a mov r6,r17 + 6924: 800f883a mov r7,r16 + 6928: 01400284 movi r5,10 + 692c: 00068480 call 6848 + 6930: 81000317 ldw r4,12(r16) + 6934: 800f883a mov r7,r16 + 6938: 01400484 movi r5,18 + 693c: 01800084 movi r6,2 + 6940: dfc00217 ldw ra,8(sp) + 6944: dc400117 ldw r17,4(sp) + 6948: dc000017 ldw r16,0(sp) + 694c: dec00304 addi sp,sp,12 + 6950: 00068481 jmpi 6848 + +00006954 <__fp_lock>: + 6954: 0005883a mov r2,zero + 6958: f800283a ret + +0000695c <__fp_unlock>: + 695c: 0005883a mov r2,zero + 6960: f800283a ret + +00006964 <__fp_unlock_all>: + 6964: 00800074 movhi r2,1 + 6968: 10887e04 addi r2,r2,8696 + 696c: 11000017 ldw r4,0(r2) + 6970: 01400034 movhi r5,0 + 6974: 295a5704 addi r5,r5,26972 + 6978: 00074e01 jmpi 74e0 <_fwalk> + +0000697c <__fp_lock_all>: + 697c: 00800074 movhi r2,1 + 6980: 10887e04 addi r2,r2,8696 + 6984: 11000017 ldw r4,0(r2) + 6988: 01400034 movhi r5,0 + 698c: 295a5504 addi r5,r5,26964 + 6990: 00074e01 jmpi 74e0 <_fwalk> + +00006994 <_cleanup_r>: + 6994: 01400074 movhi r5,1 + 6998: 29679504 addi r5,r5,-25004 + 699c: 00074e01 jmpi 74e0 <_fwalk> + +000069a0 <_cleanup>: + 69a0: 00800074 movhi r2,1 + 69a4: 10887f04 addi r2,r2,8700 + 69a8: 11000017 ldw r4,0(r2) + 69ac: 00069941 jmpi 6994 <_cleanup_r> + +000069b0 <__sfmoreglue>: + 69b0: defffc04 addi sp,sp,-16 + 69b4: dc000015 stw r16,0(sp) + 69b8: 2821883a mov r16,r5 + 69bc: dc400115 stw r17,4(sp) + 69c0: 01401704 movi r5,92 + 69c4: 2023883a mov r17,r4 + 69c8: 8009883a mov r4,r16 + 69cc: dfc00315 stw ra,12(sp) + 69d0: dcc00215 stw r19,8(sp) + 69d4: 0002c240 call 2c24 <__mulsi3> + 69d8: 11400304 addi r5,r2,12 + 69dc: 8809883a mov r4,r17 + 69e0: 1027883a mov r19,r2 + 69e4: 00077f00 call 77f0 <_malloc_r> + 69e8: 10c00304 addi r3,r2,12 + 69ec: 1023883a mov r17,r2 + 69f0: 1809883a mov r4,r3 + 69f4: 980d883a mov r6,r19 + 69f8: 000b883a mov r5,zero + 69fc: 10000b26 beq r2,zero,6a2c <__sfmoreglue+0x7c> + 6a00: 14000115 stw r16,4(r2) + 6a04: 10c00215 stw r3,8(r2) + 6a08: 10000015 stw zero,0(r2) + 6a0c: 00081940 call 8194 + 6a10: 8805883a mov r2,r17 + 6a14: dfc00317 ldw ra,12(sp) + 6a18: dcc00217 ldw r19,8(sp) + 6a1c: dc400117 ldw r17,4(sp) + 6a20: dc000017 ldw r16,0(sp) + 6a24: dec00404 addi sp,sp,16 + 6a28: f800283a ret + 6a2c: 0023883a mov r17,zero + 6a30: 8805883a mov r2,r17 + 6a34: dfc00317 ldw ra,12(sp) + 6a38: dcc00217 ldw r19,8(sp) + 6a3c: dc400117 ldw r17,4(sp) + 6a40: dc000017 ldw r16,0(sp) + 6a44: dec00404 addi sp,sp,16 + 6a48: f800283a ret + +00006a4c <__sfp>: + 6a4c: defffd04 addi sp,sp,-12 + 6a50: 00800074 movhi r2,1 + 6a54: 10887f04 addi r2,r2,8700 + 6a58: dc000015 stw r16,0(sp) + 6a5c: 14000017 ldw r16,0(r2) + 6a60: dc400115 stw r17,4(sp) + 6a64: dfc00215 stw ra,8(sp) + 6a68: 80800e17 ldw r2,56(r16) + 6a6c: 2023883a mov r17,r4 + 6a70: 10002626 beq r2,zero,6b0c <__sfp+0xc0> + 6a74: 8400b804 addi r16,r16,736 + 6a78: 80800117 ldw r2,4(r16) + 6a7c: 81000217 ldw r4,8(r16) + 6a80: 10ffffc4 addi r3,r2,-1 + 6a84: 18000916 blt r3,zero,6aac <__sfp+0x60> + 6a88: 2080030f ldh r2,12(r4) + 6a8c: 10000b26 beq r2,zero,6abc <__sfp+0x70> + 6a90: 017fffc4 movi r5,-1 + 6a94: 00000206 br 6aa0 <__sfp+0x54> + 6a98: 2080030f ldh r2,12(r4) + 6a9c: 10000726 beq r2,zero,6abc <__sfp+0x70> + 6aa0: 18ffffc4 addi r3,r3,-1 + 6aa4: 21001704 addi r4,r4,92 + 6aa8: 197ffb1e bne r3,r5,6a98 <__sfp+0x4c> + 6aac: 80800017 ldw r2,0(r16) + 6ab0: 10001926 beq r2,zero,6b18 <__sfp+0xcc> + 6ab4: 1021883a mov r16,r2 + 6ab8: 003fef06 br 6a78 <__sfp+0x2c> + 6abc: 00bfffc4 movi r2,-1 + 6ac0: 00c00044 movi r3,1 + 6ac4: 2080038d sth r2,14(r4) + 6ac8: 20c0030d sth r3,12(r4) + 6acc: 20000015 stw zero,0(r4) + 6ad0: 20000215 stw zero,8(r4) + 6ad4: 20000115 stw zero,4(r4) + 6ad8: 20000415 stw zero,16(r4) + 6adc: 20000515 stw zero,20(r4) + 6ae0: 20000615 stw zero,24(r4) + 6ae4: 20000c15 stw zero,48(r4) + 6ae8: 20000d15 stw zero,52(r4) + 6aec: 20001115 stw zero,68(r4) + 6af0: 20001215 stw zero,72(r4) + 6af4: 2005883a mov r2,r4 + 6af8: dfc00217 ldw ra,8(sp) + 6afc: dc400117 ldw r17,4(sp) + 6b00: dc000017 ldw r16,0(sp) + 6b04: dec00304 addi sp,sp,12 + 6b08: f800283a ret + 6b0c: 8009883a mov r4,r16 + 6b10: 00068b00 call 68b0 <__sinit> + 6b14: 003fd706 br 6a74 <__sfp+0x28> + 6b18: 8809883a mov r4,r17 + 6b1c: 01400104 movi r5,4 + 6b20: 00069b00 call 69b0 <__sfmoreglue> + 6b24: 80800015 stw r2,0(r16) + 6b28: 103fe21e bne r2,zero,6ab4 <__sfp+0x68> + 6b2c: 00800304 movi r2,12 + 6b30: 0009883a mov r4,zero + 6b34: 88800015 stw r2,0(r17) + 6b38: 003fee06 br 6af4 <__sfp+0xa8> + +00006b3c <_malloc_trim_r>: + 6b3c: defffb04 addi sp,sp,-20 + 6b40: dcc00315 stw r19,12(sp) + 6b44: 04c00074 movhi r19,1 + 6b48: 9cc2b004 addi r19,r19,2752 + 6b4c: dc800215 stw r18,8(sp) + 6b50: dc400115 stw r17,4(sp) + 6b54: dc000015 stw r16,0(sp) + 6b58: 2823883a mov r17,r5 + 6b5c: 2025883a mov r18,r4 + 6b60: dfc00415 stw ra,16(sp) + 6b64: 000cb800 call cb80 <__malloc_lock> + 6b68: 98800217 ldw r2,8(r19) + 6b6c: 9009883a mov r4,r18 + 6b70: 000b883a mov r5,zero + 6b74: 10c00117 ldw r3,4(r2) + 6b78: 00bfff04 movi r2,-4 + 6b7c: 18a0703a and r16,r3,r2 + 6b80: 8463c83a sub r17,r16,r17 + 6b84: 8c43fbc4 addi r17,r17,4079 + 6b88: 8822d33a srli r17,r17,12 + 6b8c: 0083ffc4 movi r2,4095 + 6b90: 8c7fffc4 addi r17,r17,-1 + 6b94: 8822933a slli r17,r17,12 + 6b98: 1440060e bge r2,r17,6bb4 <_malloc_trim_r+0x78> + 6b9c: 000991c0 call 991c <_sbrk_r> + 6ba0: 98c00217 ldw r3,8(r19) + 6ba4: 9009883a mov r4,r18 + 6ba8: 044bc83a sub r5,zero,r17 + 6bac: 80c7883a add r3,r16,r3 + 6bb0: 10c00926 beq r2,r3,6bd8 <_malloc_trim_r+0x9c> + 6bb4: 000cba00 call cba0 <__malloc_unlock> + 6bb8: 0005883a mov r2,zero + 6bbc: dfc00417 ldw ra,16(sp) + 6bc0: dcc00317 ldw r19,12(sp) + 6bc4: dc800217 ldw r18,8(sp) + 6bc8: dc400117 ldw r17,4(sp) + 6bcc: dc000017 ldw r16,0(sp) + 6bd0: dec00504 addi sp,sp,20 + 6bd4: f800283a ret + 6bd8: 9009883a mov r4,r18 + 6bdc: 000991c0 call 991c <_sbrk_r> + 6be0: 844dc83a sub r6,r16,r17 + 6be4: 00ffffc4 movi r3,-1 + 6be8: 9009883a mov r4,r18 + 6bec: 000b883a mov r5,zero + 6bf0: 01c00074 movhi r7,1 + 6bf4: 39d0c304 addi r7,r7,17164 + 6bf8: 31800054 ori r6,r6,1 + 6bfc: 10c00926 beq r2,r3,6c24 <_malloc_trim_r+0xe8> + 6c00: 38800017 ldw r2,0(r7) + 6c04: 98c00217 ldw r3,8(r19) + 6c08: 9009883a mov r4,r18 + 6c0c: 1445c83a sub r2,r2,r17 + 6c10: 38800015 stw r2,0(r7) + 6c14: 19800115 stw r6,4(r3) + 6c18: 000cba00 call cba0 <__malloc_unlock> + 6c1c: 00800044 movi r2,1 + 6c20: 003fe606 br 6bbc <_malloc_trim_r+0x80> + 6c24: 000991c0 call 991c <_sbrk_r> + 6c28: 99800217 ldw r6,8(r19) + 6c2c: 100f883a mov r7,r2 + 6c30: 9009883a mov r4,r18 + 6c34: 1187c83a sub r3,r2,r6 + 6c38: 008003c4 movi r2,15 + 6c3c: 19400054 ori r5,r3,1 + 6c40: 10ffdc0e bge r2,r3,6bb4 <_malloc_trim_r+0x78> + 6c44: 00800074 movhi r2,1 + 6c48: 10888304 addi r2,r2,8716 + 6c4c: 10c00017 ldw r3,0(r2) + 6c50: 00800074 movhi r2,1 + 6c54: 1090c304 addi r2,r2,17164 + 6c58: 31400115 stw r5,4(r6) + 6c5c: 38c7c83a sub r3,r7,r3 + 6c60: 10c00015 stw r3,0(r2) + 6c64: 003fd306 br 6bb4 <_malloc_trim_r+0x78> + +00006c68 <_free_r>: + 6c68: defffd04 addi sp,sp,-12 + 6c6c: dc400115 stw r17,4(sp) + 6c70: dc000015 stw r16,0(sp) + 6c74: dfc00215 stw ra,8(sp) + 6c78: 2821883a mov r16,r5 + 6c7c: 2023883a mov r17,r4 + 6c80: 28005a26 beq r5,zero,6dec <_free_r+0x184> + 6c84: 000cb800 call cb80 <__malloc_lock> + 6c88: 823ffe04 addi r8,r16,-8 + 6c8c: 41400117 ldw r5,4(r8) + 6c90: 00bfff84 movi r2,-2 + 6c94: 02800074 movhi r10,1 + 6c98: 5282b004 addi r10,r10,2752 + 6c9c: 288e703a and r7,r5,r2 + 6ca0: 41cd883a add r6,r8,r7 + 6ca4: 30c00117 ldw r3,4(r6) + 6ca8: 51000217 ldw r4,8(r10) + 6cac: 00bfff04 movi r2,-4 + 6cb0: 1892703a and r9,r3,r2 + 6cb4: 5017883a mov r11,r10 + 6cb8: 31006726 beq r6,r4,6e58 <_free_r+0x1f0> + 6cbc: 2880004c andi r2,r5,1 + 6cc0: 1005003a cmpeq r2,r2,zero + 6cc4: 32400115 stw r9,4(r6) + 6cc8: 10001a1e bne r2,zero,6d34 <_free_r+0xcc> + 6ccc: 000b883a mov r5,zero + 6cd0: 3247883a add r3,r6,r9 + 6cd4: 18800117 ldw r2,4(r3) + 6cd8: 1080004c andi r2,r2,1 + 6cdc: 1000231e bne r2,zero,6d6c <_free_r+0x104> + 6ce0: 280ac03a cmpne r5,r5,zero + 6ce4: 3a4f883a add r7,r7,r9 + 6ce8: 2800451e bne r5,zero,6e00 <_free_r+0x198> + 6cec: 31000217 ldw r4,8(r6) + 6cf0: 00800074 movhi r2,1 + 6cf4: 1082b204 addi r2,r2,2760 + 6cf8: 20807b26 beq r4,r2,6ee8 <_free_r+0x280> + 6cfc: 30800317 ldw r2,12(r6) + 6d00: 3a07883a add r3,r7,r8 + 6d04: 19c00015 stw r7,0(r3) + 6d08: 11000215 stw r4,8(r2) + 6d0c: 20800315 stw r2,12(r4) + 6d10: 38800054 ori r2,r7,1 + 6d14: 40800115 stw r2,4(r8) + 6d18: 28001a26 beq r5,zero,6d84 <_free_r+0x11c> + 6d1c: 8809883a mov r4,r17 + 6d20: dfc00217 ldw ra,8(sp) + 6d24: dc400117 ldw r17,4(sp) + 6d28: dc000017 ldw r16,0(sp) + 6d2c: dec00304 addi sp,sp,12 + 6d30: 000cba01 jmpi cba0 <__malloc_unlock> + 6d34: 80bffe17 ldw r2,-8(r16) + 6d38: 50c00204 addi r3,r10,8 + 6d3c: 4091c83a sub r8,r8,r2 + 6d40: 41000217 ldw r4,8(r8) + 6d44: 388f883a add r7,r7,r2 + 6d48: 20c06126 beq r4,r3,6ed0 <_free_r+0x268> + 6d4c: 40800317 ldw r2,12(r8) + 6d50: 3247883a add r3,r6,r9 + 6d54: 000b883a mov r5,zero + 6d58: 11000215 stw r4,8(r2) + 6d5c: 20800315 stw r2,12(r4) + 6d60: 18800117 ldw r2,4(r3) + 6d64: 1080004c andi r2,r2,1 + 6d68: 103fdd26 beq r2,zero,6ce0 <_free_r+0x78> + 6d6c: 38800054 ori r2,r7,1 + 6d70: 3a07883a add r3,r7,r8 + 6d74: 280ac03a cmpne r5,r5,zero + 6d78: 40800115 stw r2,4(r8) + 6d7c: 19c00015 stw r7,0(r3) + 6d80: 283fe61e bne r5,zero,6d1c <_free_r+0xb4> + 6d84: 00807fc4 movi r2,511 + 6d88: 11c01f2e bgeu r2,r7,6e08 <_free_r+0x1a0> + 6d8c: 3806d27a srli r3,r7,9 + 6d90: 1800481e bne r3,zero,6eb4 <_free_r+0x24c> + 6d94: 3804d0fa srli r2,r7,3 + 6d98: 100690fa slli r3,r2,3 + 6d9c: 1acd883a add r6,r3,r11 + 6da0: 31400217 ldw r5,8(r6) + 6da4: 31405926 beq r6,r5,6f0c <_free_r+0x2a4> + 6da8: 28800117 ldw r2,4(r5) + 6dac: 00ffff04 movi r3,-4 + 6db0: 10c4703a and r2,r2,r3 + 6db4: 3880022e bgeu r7,r2,6dc0 <_free_r+0x158> + 6db8: 29400217 ldw r5,8(r5) + 6dbc: 317ffa1e bne r6,r5,6da8 <_free_r+0x140> + 6dc0: 29800317 ldw r6,12(r5) + 6dc4: 41800315 stw r6,12(r8) + 6dc8: 41400215 stw r5,8(r8) + 6dcc: 8809883a mov r4,r17 + 6dd0: 2a000315 stw r8,12(r5) + 6dd4: 32000215 stw r8,8(r6) + 6dd8: dfc00217 ldw ra,8(sp) + 6ddc: dc400117 ldw r17,4(sp) + 6de0: dc000017 ldw r16,0(sp) + 6de4: dec00304 addi sp,sp,12 + 6de8: 000cba01 jmpi cba0 <__malloc_unlock> + 6dec: dfc00217 ldw ra,8(sp) + 6df0: dc400117 ldw r17,4(sp) + 6df4: dc000017 ldw r16,0(sp) + 6df8: dec00304 addi sp,sp,12 + 6dfc: f800283a ret + 6e00: 31000217 ldw r4,8(r6) + 6e04: 003fbd06 br 6cfc <_free_r+0x94> + 6e08: 3806d0fa srli r3,r7,3 + 6e0c: 00800044 movi r2,1 + 6e10: 51400117 ldw r5,4(r10) + 6e14: 180890fa slli r4,r3,3 + 6e18: 1807d0ba srai r3,r3,2 + 6e1c: 22c9883a add r4,r4,r11 + 6e20: 21800217 ldw r6,8(r4) + 6e24: 10c4983a sll r2,r2,r3 + 6e28: 41000315 stw r4,12(r8) + 6e2c: 41800215 stw r6,8(r8) + 6e30: 288ab03a or r5,r5,r2 + 6e34: 22000215 stw r8,8(r4) + 6e38: 8809883a mov r4,r17 + 6e3c: 51400115 stw r5,4(r10) + 6e40: 32000315 stw r8,12(r6) + 6e44: dfc00217 ldw ra,8(sp) + 6e48: dc400117 ldw r17,4(sp) + 6e4c: dc000017 ldw r16,0(sp) + 6e50: dec00304 addi sp,sp,12 + 6e54: 000cba01 jmpi cba0 <__malloc_unlock> + 6e58: 2880004c andi r2,r5,1 + 6e5c: 3a4d883a add r6,r7,r9 + 6e60: 1000071e bne r2,zero,6e80 <_free_r+0x218> + 6e64: 80bffe17 ldw r2,-8(r16) + 6e68: 4091c83a sub r8,r8,r2 + 6e6c: 41000317 ldw r4,12(r8) + 6e70: 40c00217 ldw r3,8(r8) + 6e74: 308d883a add r6,r6,r2 + 6e78: 20c00215 stw r3,8(r4) + 6e7c: 19000315 stw r4,12(r3) + 6e80: 00800074 movhi r2,1 + 6e84: 10888204 addi r2,r2,8712 + 6e88: 11000017 ldw r4,0(r2) + 6e8c: 30c00054 ori r3,r6,1 + 6e90: 52000215 stw r8,8(r10) + 6e94: 40c00115 stw r3,4(r8) + 6e98: 313fa036 bltu r6,r4,6d1c <_free_r+0xb4> + 6e9c: 00800074 movhi r2,1 + 6ea0: 108f7904 addi r2,r2,15844 + 6ea4: 11400017 ldw r5,0(r2) + 6ea8: 8809883a mov r4,r17 + 6eac: 0006b3c0 call 6b3c <_malloc_trim_r> + 6eb0: 003f9a06 br 6d1c <_free_r+0xb4> + 6eb4: 00800104 movi r2,4 + 6eb8: 10c0072e bgeu r2,r3,6ed8 <_free_r+0x270> + 6ebc: 00800504 movi r2,20 + 6ec0: 10c01936 bltu r2,r3,6f28 <_free_r+0x2c0> + 6ec4: 188016c4 addi r2,r3,91 + 6ec8: 100690fa slli r3,r2,3 + 6ecc: 003fb306 br 6d9c <_free_r+0x134> + 6ed0: 01400044 movi r5,1 + 6ed4: 003f7e06 br 6cd0 <_free_r+0x68> + 6ed8: 3804d1ba srli r2,r7,6 + 6edc: 10800e04 addi r2,r2,56 + 6ee0: 100690fa slli r3,r2,3 + 6ee4: 003fad06 br 6d9c <_free_r+0x134> + 6ee8: 22000315 stw r8,12(r4) + 6eec: 22000215 stw r8,8(r4) + 6ef0: 3a05883a add r2,r7,r8 + 6ef4: 38c00054 ori r3,r7,1 + 6ef8: 11c00015 stw r7,0(r2) + 6efc: 41000215 stw r4,8(r8) + 6f00: 40c00115 stw r3,4(r8) + 6f04: 41000315 stw r4,12(r8) + 6f08: 003f8406 br 6d1c <_free_r+0xb4> + 6f0c: 1005d0ba srai r2,r2,2 + 6f10: 00c00044 movi r3,1 + 6f14: 51000117 ldw r4,4(r10) + 6f18: 1886983a sll r3,r3,r2 + 6f1c: 20c8b03a or r4,r4,r3 + 6f20: 51000115 stw r4,4(r10) + 6f24: 003fa706 br 6dc4 <_free_r+0x15c> + 6f28: 00801504 movi r2,84 + 6f2c: 10c00436 bltu r2,r3,6f40 <_free_r+0x2d8> + 6f30: 3804d33a srli r2,r7,12 + 6f34: 10801b84 addi r2,r2,110 + 6f38: 100690fa slli r3,r2,3 + 6f3c: 003f9706 br 6d9c <_free_r+0x134> + 6f40: 00805504 movi r2,340 + 6f44: 10c00436 bltu r2,r3,6f58 <_free_r+0x2f0> + 6f48: 3804d3fa srli r2,r7,15 + 6f4c: 10801dc4 addi r2,r2,119 + 6f50: 100690fa slli r3,r2,3 + 6f54: 003f9106 br 6d9c <_free_r+0x134> + 6f58: 00815504 movi r2,1364 + 6f5c: 10c0032e bgeu r2,r3,6f6c <_free_r+0x304> + 6f60: 00801f84 movi r2,126 + 6f64: 00c0fc04 movi r3,1008 + 6f68: 003f8c06 br 6d9c <_free_r+0x134> + 6f6c: 3804d4ba srli r2,r7,18 + 6f70: 10801f04 addi r2,r2,124 + 6f74: 100690fa slli r3,r2,3 + 6f78: 003f8806 br 6d9c <_free_r+0x134> + +00006f7c <__sfvwrite_r>: + 6f7c: 30800217 ldw r2,8(r6) + 6f80: defff504 addi sp,sp,-44 + 6f84: df000915 stw fp,36(sp) + 6f88: dd800715 stw r22,28(sp) + 6f8c: dc800315 stw r18,12(sp) + 6f90: dfc00a15 stw ra,40(sp) + 6f94: ddc00815 stw r23,32(sp) + 6f98: dd400615 stw r21,24(sp) + 6f9c: dd000515 stw r20,20(sp) + 6fa0: dcc00415 stw r19,16(sp) + 6fa4: dc400215 stw r17,8(sp) + 6fa8: dc000115 stw r16,4(sp) + 6fac: 302d883a mov r22,r6 + 6fb0: 2039883a mov fp,r4 + 6fb4: 2825883a mov r18,r5 + 6fb8: 10001c26 beq r2,zero,702c <__sfvwrite_r+0xb0> + 6fbc: 29c0030b ldhu r7,12(r5) + 6fc0: 3880020c andi r2,r7,8 + 6fc4: 10002726 beq r2,zero,7064 <__sfvwrite_r+0xe8> + 6fc8: 28800417 ldw r2,16(r5) + 6fcc: 10002526 beq r2,zero,7064 <__sfvwrite_r+0xe8> + 6fd0: 3880008c andi r2,r7,2 + 6fd4: b5400017 ldw r21,0(r22) + 6fd8: 10002826 beq r2,zero,707c <__sfvwrite_r+0x100> + 6fdc: 0021883a mov r16,zero + 6fe0: 0023883a mov r17,zero + 6fe4: 880d883a mov r6,r17 + 6fe8: e009883a mov r4,fp + 6fec: 00810004 movi r2,1024 + 6ff0: 80006e26 beq r16,zero,71ac <__sfvwrite_r+0x230> + 6ff4: 800f883a mov r7,r16 + 6ff8: 91400717 ldw r5,28(r18) + 6ffc: 1400012e bgeu r2,r16,7004 <__sfvwrite_r+0x88> + 7000: 100f883a mov r7,r2 + 7004: 90c00917 ldw r3,36(r18) + 7008: 183ee83a callr r3 + 700c: 1007883a mov r3,r2 + 7010: 80a1c83a sub r16,r16,r2 + 7014: 88a3883a add r17,r17,r2 + 7018: 00806d0e bge zero,r2,71d0 <__sfvwrite_r+0x254> + 701c: b0800217 ldw r2,8(r22) + 7020: 10c5c83a sub r2,r2,r3 + 7024: b0800215 stw r2,8(r22) + 7028: 103fee1e bne r2,zero,6fe4 <__sfvwrite_r+0x68> + 702c: 0009883a mov r4,zero + 7030: 2005883a mov r2,r4 + 7034: dfc00a17 ldw ra,40(sp) + 7038: df000917 ldw fp,36(sp) + 703c: ddc00817 ldw r23,32(sp) + 7040: dd800717 ldw r22,28(sp) + 7044: dd400617 ldw r21,24(sp) + 7048: dd000517 ldw r20,20(sp) + 704c: dcc00417 ldw r19,16(sp) + 7050: dc800317 ldw r18,12(sp) + 7054: dc400217 ldw r17,8(sp) + 7058: dc000117 ldw r16,4(sp) + 705c: dec00b04 addi sp,sp,44 + 7060: f800283a ret + 7064: 0004ce40 call 4ce4 <__swsetup_r> + 7068: 1000e41e bne r2,zero,73fc <__sfvwrite_r+0x480> + 706c: 91c0030b ldhu r7,12(r18) + 7070: b5400017 ldw r21,0(r22) + 7074: 3880008c andi r2,r7,2 + 7078: 103fd81e bne r2,zero,6fdc <__sfvwrite_r+0x60> + 707c: 3880004c andi r2,r7,1 + 7080: 1005003a cmpeq r2,r2,zero + 7084: 10005726 beq r2,zero,71e4 <__sfvwrite_r+0x268> + 7088: 0029883a mov r20,zero + 708c: 002f883a mov r23,zero + 7090: a0004226 beq r20,zero,719c <__sfvwrite_r+0x220> + 7094: 3880800c andi r2,r7,512 + 7098: 94000217 ldw r16,8(r18) + 709c: 10008b26 beq r2,zero,72cc <__sfvwrite_r+0x350> + 70a0: 800d883a mov r6,r16 + 70a4: a400a536 bltu r20,r16,733c <__sfvwrite_r+0x3c0> + 70a8: 3881200c andi r2,r7,1152 + 70ac: 10002726 beq r2,zero,714c <__sfvwrite_r+0x1d0> + 70b0: 90800517 ldw r2,20(r18) + 70b4: 92000417 ldw r8,16(r18) + 70b8: 91400017 ldw r5,0(r18) + 70bc: 1087883a add r3,r2,r2 + 70c0: 1887883a add r3,r3,r2 + 70c4: 1808d7fa srli r4,r3,31 + 70c8: 2a21c83a sub r16,r5,r8 + 70cc: 80800044 addi r2,r16,1 + 70d0: 20c9883a add r4,r4,r3 + 70d4: 2027d07a srai r19,r4,1 + 70d8: a085883a add r2,r20,r2 + 70dc: 980d883a mov r6,r19 + 70e0: 9880022e bgeu r19,r2,70ec <__sfvwrite_r+0x170> + 70e4: 1027883a mov r19,r2 + 70e8: 100d883a mov r6,r2 + 70ec: 3881000c andi r2,r7,1024 + 70f0: 1000b826 beq r2,zero,73d4 <__sfvwrite_r+0x458> + 70f4: 300b883a mov r5,r6 + 70f8: e009883a mov r4,fp + 70fc: 00077f00 call 77f0 <_malloc_r> + 7100: 10003126 beq r2,zero,71c8 <__sfvwrite_r+0x24c> + 7104: 91400417 ldw r5,16(r18) + 7108: 1009883a mov r4,r2 + 710c: 800d883a mov r6,r16 + 7110: 1023883a mov r17,r2 + 7114: 00080140 call 8014 + 7118: 90c0030b ldhu r3,12(r18) + 711c: 00beffc4 movi r2,-1025 + 7120: 1886703a and r3,r3,r2 + 7124: 18c02014 ori r3,r3,128 + 7128: 90c0030d sth r3,12(r18) + 712c: 9c07c83a sub r3,r19,r16 + 7130: 8c05883a add r2,r17,r16 + 7134: a00d883a mov r6,r20 + 7138: a021883a mov r16,r20 + 713c: 90800015 stw r2,0(r18) + 7140: 90c00215 stw r3,8(r18) + 7144: 94400415 stw r17,16(r18) + 7148: 94c00515 stw r19,20(r18) + 714c: 91000017 ldw r4,0(r18) + 7150: b80b883a mov r5,r23 + 7154: a023883a mov r17,r20 + 7158: 00080b40 call 80b4 + 715c: 90c00217 ldw r3,8(r18) + 7160: 90800017 ldw r2,0(r18) + 7164: a027883a mov r19,r20 + 7168: 1c07c83a sub r3,r3,r16 + 716c: 1405883a add r2,r2,r16 + 7170: 90c00215 stw r3,8(r18) + 7174: a021883a mov r16,r20 + 7178: 90800015 stw r2,0(r18) + 717c: b0800217 ldw r2,8(r22) + 7180: 1405c83a sub r2,r2,r16 + 7184: b0800215 stw r2,8(r22) + 7188: 103fa826 beq r2,zero,702c <__sfvwrite_r+0xb0> + 718c: a469c83a sub r20,r20,r17 + 7190: 91c0030b ldhu r7,12(r18) + 7194: bcef883a add r23,r23,r19 + 7198: a03fbe1e bne r20,zero,7094 <__sfvwrite_r+0x118> + 719c: adc00017 ldw r23,0(r21) + 71a0: ad000117 ldw r20,4(r21) + 71a4: ad400204 addi r21,r21,8 + 71a8: 003fb906 br 7090 <__sfvwrite_r+0x114> + 71ac: ac400017 ldw r17,0(r21) + 71b0: ac000117 ldw r16,4(r21) + 71b4: ad400204 addi r21,r21,8 + 71b8: 003f8a06 br 6fe4 <__sfvwrite_r+0x68> + 71bc: 91400417 ldw r5,16(r18) + 71c0: e009883a mov r4,fp + 71c4: 0006c680 call 6c68 <_free_r> + 71c8: 00800304 movi r2,12 + 71cc: e0800015 stw r2,0(fp) + 71d0: 9080030b ldhu r2,12(r18) + 71d4: 013fffc4 movi r4,-1 + 71d8: 10801014 ori r2,r2,64 + 71dc: 9080030d sth r2,12(r18) + 71e0: 003f9306 br 7030 <__sfvwrite_r+0xb4> + 71e4: 0027883a mov r19,zero + 71e8: 002f883a mov r23,zero + 71ec: d8000015 stw zero,0(sp) + 71f0: 0029883a mov r20,zero + 71f4: 98001e26 beq r19,zero,7270 <__sfvwrite_r+0x2f4> + 71f8: d8c00017 ldw r3,0(sp) + 71fc: 1804c03a cmpne r2,r3,zero + 7200: 10005e26 beq r2,zero,737c <__sfvwrite_r+0x400> + 7204: 9821883a mov r16,r19 + 7208: a4c0012e bgeu r20,r19,7210 <__sfvwrite_r+0x294> + 720c: a021883a mov r16,r20 + 7210: 91000017 ldw r4,0(r18) + 7214: 90800417 ldw r2,16(r18) + 7218: 91800217 ldw r6,8(r18) + 721c: 91c00517 ldw r7,20(r18) + 7220: 1100022e bgeu r2,r4,722c <__sfvwrite_r+0x2b0> + 7224: 31e3883a add r17,r6,r7 + 7228: 8c001616 blt r17,r16,7284 <__sfvwrite_r+0x308> + 722c: 81c03816 blt r16,r7,7310 <__sfvwrite_r+0x394> + 7230: 90c00917 ldw r3,36(r18) + 7234: 91400717 ldw r5,28(r18) + 7238: e009883a mov r4,fp + 723c: b80d883a mov r6,r23 + 7240: 183ee83a callr r3 + 7244: 1023883a mov r17,r2 + 7248: 00bfe10e bge zero,r2,71d0 <__sfvwrite_r+0x254> + 724c: a469c83a sub r20,r20,r17 + 7250: a0001826 beq r20,zero,72b4 <__sfvwrite_r+0x338> + 7254: b0800217 ldw r2,8(r22) + 7258: 1445c83a sub r2,r2,r17 + 725c: b0800215 stw r2,8(r22) + 7260: 103f7226 beq r2,zero,702c <__sfvwrite_r+0xb0> + 7264: 9c67c83a sub r19,r19,r17 + 7268: bc6f883a add r23,r23,r17 + 726c: 983fe21e bne r19,zero,71f8 <__sfvwrite_r+0x27c> + 7270: adc00017 ldw r23,0(r21) + 7274: acc00117 ldw r19,4(r21) + 7278: ad400204 addi r21,r21,8 + 727c: d8000015 stw zero,0(sp) + 7280: 003fdc06 br 71f4 <__sfvwrite_r+0x278> + 7284: b80b883a mov r5,r23 + 7288: 880d883a mov r6,r17 + 728c: 00080b40 call 80b4 + 7290: 90c00017 ldw r3,0(r18) + 7294: e009883a mov r4,fp + 7298: 900b883a mov r5,r18 + 729c: 1c47883a add r3,r3,r17 + 72a0: 90c00015 stw r3,0(r18) + 72a4: 00066180 call 6618 <_fflush_r> + 72a8: 103fc91e bne r2,zero,71d0 <__sfvwrite_r+0x254> + 72ac: a469c83a sub r20,r20,r17 + 72b0: a03fe81e bne r20,zero,7254 <__sfvwrite_r+0x2d8> + 72b4: e009883a mov r4,fp + 72b8: 900b883a mov r5,r18 + 72bc: 00066180 call 6618 <_fflush_r> + 72c0: 103fc31e bne r2,zero,71d0 <__sfvwrite_r+0x254> + 72c4: d8000015 stw zero,0(sp) + 72c8: 003fe206 br 7254 <__sfvwrite_r+0x2d8> + 72cc: 91000017 ldw r4,0(r18) + 72d0: 90800417 ldw r2,16(r18) + 72d4: 1100022e bgeu r2,r4,72e0 <__sfvwrite_r+0x364> + 72d8: 8023883a mov r17,r16 + 72dc: 85003136 bltu r16,r20,73a4 <__sfvwrite_r+0x428> + 72e0: 91c00517 ldw r7,20(r18) + 72e4: a1c01836 bltu r20,r7,7348 <__sfvwrite_r+0x3cc> + 72e8: 90c00917 ldw r3,36(r18) + 72ec: 91400717 ldw r5,28(r18) + 72f0: e009883a mov r4,fp + 72f4: b80d883a mov r6,r23 + 72f8: 183ee83a callr r3 + 72fc: 1021883a mov r16,r2 + 7300: 00bfb30e bge zero,r2,71d0 <__sfvwrite_r+0x254> + 7304: 1023883a mov r17,r2 + 7308: 1027883a mov r19,r2 + 730c: 003f9b06 br 717c <__sfvwrite_r+0x200> + 7310: b80b883a mov r5,r23 + 7314: 800d883a mov r6,r16 + 7318: 00080b40 call 80b4 + 731c: 90c00217 ldw r3,8(r18) + 7320: 90800017 ldw r2,0(r18) + 7324: 8023883a mov r17,r16 + 7328: 1c07c83a sub r3,r3,r16 + 732c: 1405883a add r2,r2,r16 + 7330: 90c00215 stw r3,8(r18) + 7334: 90800015 stw r2,0(r18) + 7338: 003fc406 br 724c <__sfvwrite_r+0x2d0> + 733c: a00d883a mov r6,r20 + 7340: a021883a mov r16,r20 + 7344: 003f8106 br 714c <__sfvwrite_r+0x1d0> + 7348: b80b883a mov r5,r23 + 734c: a00d883a mov r6,r20 + 7350: 00080b40 call 80b4 + 7354: 90c00217 ldw r3,8(r18) + 7358: 90800017 ldw r2,0(r18) + 735c: a021883a mov r16,r20 + 7360: 1d07c83a sub r3,r3,r20 + 7364: 1505883a add r2,r2,r20 + 7368: a023883a mov r17,r20 + 736c: a027883a mov r19,r20 + 7370: 90c00215 stw r3,8(r18) + 7374: 90800015 stw r2,0(r18) + 7378: 003f8006 br 717c <__sfvwrite_r+0x200> + 737c: b809883a mov r4,r23 + 7380: 01400284 movi r5,10 + 7384: 980d883a mov r6,r19 + 7388: 0007f300 call 7f30 + 738c: 10001726 beq r2,zero,73ec <__sfvwrite_r+0x470> + 7390: 15c5c83a sub r2,r2,r23 + 7394: 15000044 addi r20,r2,1 + 7398: 00800044 movi r2,1 + 739c: d8800015 stw r2,0(sp) + 73a0: 003f9806 br 7204 <__sfvwrite_r+0x288> + 73a4: b80b883a mov r5,r23 + 73a8: 800d883a mov r6,r16 + 73ac: 00080b40 call 80b4 + 73b0: 90c00017 ldw r3,0(r18) + 73b4: e009883a mov r4,fp + 73b8: 900b883a mov r5,r18 + 73bc: 1c07883a add r3,r3,r16 + 73c0: 90c00015 stw r3,0(r18) + 73c4: 8027883a mov r19,r16 + 73c8: 00066180 call 6618 <_fflush_r> + 73cc: 103f6b26 beq r2,zero,717c <__sfvwrite_r+0x200> + 73d0: 003f7f06 br 71d0 <__sfvwrite_r+0x254> + 73d4: 400b883a mov r5,r8 + 73d8: e009883a mov r4,fp + 73dc: 00092b80 call 92b8 <_realloc_r> + 73e0: 103f7626 beq r2,zero,71bc <__sfvwrite_r+0x240> + 73e4: 1023883a mov r17,r2 + 73e8: 003f5006 br 712c <__sfvwrite_r+0x1b0> + 73ec: 00c00044 movi r3,1 + 73f0: 9d000044 addi r20,r19,1 + 73f4: d8c00015 stw r3,0(sp) + 73f8: 003f8206 br 7204 <__sfvwrite_r+0x288> + 73fc: 9080030b ldhu r2,12(r18) + 7400: 00c00244 movi r3,9 + 7404: 013fffc4 movi r4,-1 + 7408: 10801014 ori r2,r2,64 + 740c: 9080030d sth r2,12(r18) + 7410: e0c00015 stw r3,0(fp) + 7414: 003f0606 br 7030 <__sfvwrite_r+0xb4> + +00007418 <_fwalk_reent>: + 7418: defff704 addi sp,sp,-36 + 741c: dcc00315 stw r19,12(sp) + 7420: 24c0b804 addi r19,r4,736 + 7424: dd800615 stw r22,24(sp) + 7428: dd400515 stw r21,20(sp) + 742c: dfc00815 stw ra,32(sp) + 7430: ddc00715 stw r23,28(sp) + 7434: dd000415 stw r20,16(sp) + 7438: dc800215 stw r18,8(sp) + 743c: dc400115 stw r17,4(sp) + 7440: dc000015 stw r16,0(sp) + 7444: 202b883a mov r21,r4 + 7448: 282d883a mov r22,r5 + 744c: 00068a00 call 68a0 <__sfp_lock_acquire> + 7450: 98002126 beq r19,zero,74d8 <_fwalk_reent+0xc0> + 7454: 002f883a mov r23,zero + 7458: 9c800117 ldw r18,4(r19) + 745c: 9c000217 ldw r16,8(r19) + 7460: 90bfffc4 addi r2,r18,-1 + 7464: 10000d16 blt r2,zero,749c <_fwalk_reent+0x84> + 7468: 0023883a mov r17,zero + 746c: 053fffc4 movi r20,-1 + 7470: 8080030f ldh r2,12(r16) + 7474: 8c400044 addi r17,r17,1 + 7478: 10000626 beq r2,zero,7494 <_fwalk_reent+0x7c> + 747c: 8080038f ldh r2,14(r16) + 7480: 800b883a mov r5,r16 + 7484: a809883a mov r4,r21 + 7488: 15000226 beq r2,r20,7494 <_fwalk_reent+0x7c> + 748c: b03ee83a callr r22 + 7490: b8aeb03a or r23,r23,r2 + 7494: 84001704 addi r16,r16,92 + 7498: 947ff51e bne r18,r17,7470 <_fwalk_reent+0x58> + 749c: 9cc00017 ldw r19,0(r19) + 74a0: 983fed1e bne r19,zero,7458 <_fwalk_reent+0x40> + 74a4: 00068a40 call 68a4 <__sfp_lock_release> + 74a8: b805883a mov r2,r23 + 74ac: dfc00817 ldw ra,32(sp) + 74b0: ddc00717 ldw r23,28(sp) + 74b4: dd800617 ldw r22,24(sp) + 74b8: dd400517 ldw r21,20(sp) + 74bc: dd000417 ldw r20,16(sp) + 74c0: dcc00317 ldw r19,12(sp) + 74c4: dc800217 ldw r18,8(sp) + 74c8: dc400117 ldw r17,4(sp) + 74cc: dc000017 ldw r16,0(sp) + 74d0: dec00904 addi sp,sp,36 + 74d4: f800283a ret + 74d8: 002f883a mov r23,zero + 74dc: 003ff106 br 74a4 <_fwalk_reent+0x8c> + +000074e0 <_fwalk>: + 74e0: defff804 addi sp,sp,-32 + 74e4: dcc00315 stw r19,12(sp) + 74e8: 24c0b804 addi r19,r4,736 + 74ec: dd400515 stw r21,20(sp) + 74f0: dfc00715 stw ra,28(sp) + 74f4: dd800615 stw r22,24(sp) + 74f8: dd000415 stw r20,16(sp) + 74fc: dc800215 stw r18,8(sp) + 7500: dc400115 stw r17,4(sp) + 7504: dc000015 stw r16,0(sp) + 7508: 282b883a mov r21,r5 + 750c: 00068a00 call 68a0 <__sfp_lock_acquire> + 7510: 98001f26 beq r19,zero,7590 <_fwalk+0xb0> + 7514: 002d883a mov r22,zero + 7518: 9c800117 ldw r18,4(r19) + 751c: 9c000217 ldw r16,8(r19) + 7520: 90bfffc4 addi r2,r18,-1 + 7524: 10000c16 blt r2,zero,7558 <_fwalk+0x78> + 7528: 0023883a mov r17,zero + 752c: 053fffc4 movi r20,-1 + 7530: 8080030f ldh r2,12(r16) + 7534: 8c400044 addi r17,r17,1 + 7538: 10000526 beq r2,zero,7550 <_fwalk+0x70> + 753c: 8080038f ldh r2,14(r16) + 7540: 8009883a mov r4,r16 + 7544: 15000226 beq r2,r20,7550 <_fwalk+0x70> + 7548: a83ee83a callr r21 + 754c: b0acb03a or r22,r22,r2 + 7550: 84001704 addi r16,r16,92 + 7554: 947ff61e bne r18,r17,7530 <_fwalk+0x50> + 7558: 9cc00017 ldw r19,0(r19) + 755c: 983fee1e bne r19,zero,7518 <_fwalk+0x38> + 7560: 00068a40 call 68a4 <__sfp_lock_release> + 7564: b005883a mov r2,r22 + 7568: dfc00717 ldw ra,28(sp) + 756c: dd800617 ldw r22,24(sp) + 7570: dd400517 ldw r21,20(sp) + 7574: dd000417 ldw r20,16(sp) + 7578: dcc00317 ldw r19,12(sp) + 757c: dc800217 ldw r18,8(sp) + 7580: dc400117 ldw r17,4(sp) + 7584: dc000017 ldw r16,0(sp) + 7588: dec00804 addi sp,sp,32 + 758c: f800283a ret + 7590: 002d883a mov r22,zero + 7594: 003ff206 br 7560 <_fwalk+0x80> + +00007598 <__locale_charset>: + 7598: d0a00517 ldw r2,-32748(gp) + 759c: f800283a ret + +000075a0 <_localeconv_r>: + 75a0: 00800074 movhi r2,1 + 75a4: 10810304 addi r2,r2,1036 + 75a8: f800283a ret + +000075ac : + 75ac: 00800074 movhi r2,1 + 75b0: 10887e04 addi r2,r2,8696 + 75b4: 11000017 ldw r4,0(r2) + 75b8: 00075a01 jmpi 75a0 <_localeconv_r> + +000075bc <_setlocale_r>: + 75bc: defffc04 addi sp,sp,-16 + 75c0: 00c00074 movhi r3,1 + 75c4: 18c0fe04 addi r3,r3,1016 + 75c8: dc800215 stw r18,8(sp) + 75cc: dc400115 stw r17,4(sp) + 75d0: dc000015 stw r16,0(sp) + 75d4: 2023883a mov r17,r4 + 75d8: 2825883a mov r18,r5 + 75dc: dfc00315 stw ra,12(sp) + 75e0: 3021883a mov r16,r6 + 75e4: 3009883a mov r4,r6 + 75e8: 180b883a mov r5,r3 + 75ec: 30000926 beq r6,zero,7614 <_setlocale_r+0x58> + 75f0: 0009ad80 call 9ad8 + 75f4: 8009883a mov r4,r16 + 75f8: 01400074 movhi r5,1 + 75fc: 2940e904 addi r5,r5,932 + 7600: 10000b1e bne r2,zero,7630 <_setlocale_r+0x74> + 7604: 8c000d15 stw r16,52(r17) + 7608: 8c800c15 stw r18,48(r17) + 760c: 00c00074 movhi r3,1 + 7610: 18c0fe04 addi r3,r3,1016 + 7614: 1805883a mov r2,r3 + 7618: dfc00317 ldw ra,12(sp) + 761c: dc800217 ldw r18,8(sp) + 7620: dc400117 ldw r17,4(sp) + 7624: dc000017 ldw r16,0(sp) + 7628: dec00404 addi sp,sp,16 + 762c: f800283a ret + 7630: 0009ad80 call 9ad8 + 7634: 0007883a mov r3,zero + 7638: 103ff226 beq r2,zero,7604 <_setlocale_r+0x48> + 763c: 003ff506 br 7614 <_setlocale_r+0x58> + +00007640 : + 7640: 01800074 movhi r6,1 + 7644: 31887e04 addi r6,r6,8696 + 7648: 2007883a mov r3,r4 + 764c: 31000017 ldw r4,0(r6) + 7650: 280d883a mov r6,r5 + 7654: 180b883a mov r5,r3 + 7658: 00075bc1 jmpi 75bc <_setlocale_r> + +0000765c <__smakebuf_r>: + 765c: 2880030b ldhu r2,12(r5) + 7660: deffed04 addi sp,sp,-76 + 7664: dc401015 stw r17,64(sp) + 7668: 1080008c andi r2,r2,2 + 766c: dc000f15 stw r16,60(sp) + 7670: dfc01215 stw ra,72(sp) + 7674: dc801115 stw r18,68(sp) + 7678: 2821883a mov r16,r5 + 767c: 2023883a mov r17,r4 + 7680: 10000b26 beq r2,zero,76b0 <__smakebuf_r+0x54> + 7684: 28c010c4 addi r3,r5,67 + 7688: 00800044 movi r2,1 + 768c: 28800515 stw r2,20(r5) + 7690: 28c00415 stw r3,16(r5) + 7694: 28c00015 stw r3,0(r5) + 7698: dfc01217 ldw ra,72(sp) + 769c: dc801117 ldw r18,68(sp) + 76a0: dc401017 ldw r17,64(sp) + 76a4: dc000f17 ldw r16,60(sp) + 76a8: dec01304 addi sp,sp,76 + 76ac: f800283a ret + 76b0: 2940038f ldh r5,14(r5) + 76b4: 28002116 blt r5,zero,773c <__smakebuf_r+0xe0> + 76b8: d80d883a mov r6,sp + 76bc: 0009e680 call 9e68 <_fstat_r> + 76c0: 10001e16 blt r2,zero,773c <__smakebuf_r+0xe0> + 76c4: d8800117 ldw r2,4(sp) + 76c8: 00e00014 movui r3,32768 + 76cc: 113c000c andi r4,r2,61440 + 76d0: 20c03126 beq r4,r3,7798 <__smakebuf_r+0x13c> + 76d4: 8080030b ldhu r2,12(r16) + 76d8: 00c80004 movi r3,8192 + 76dc: 10820014 ori r2,r2,2048 + 76e0: 8080030d sth r2,12(r16) + 76e4: 20c01e26 beq r4,r3,7760 <__smakebuf_r+0x104> + 76e8: 04810004 movi r18,1024 + 76ec: 8809883a mov r4,r17 + 76f0: 900b883a mov r5,r18 + 76f4: 00077f00 call 77f0 <_malloc_r> + 76f8: 1009883a mov r4,r2 + 76fc: 10003126 beq r2,zero,77c4 <__smakebuf_r+0x168> + 7700: 80c0030b ldhu r3,12(r16) + 7704: 00800034 movhi r2,0 + 7708: 109a6504 addi r2,r2,27028 + 770c: 88800f15 stw r2,60(r17) + 7710: 18c02014 ori r3,r3,128 + 7714: 84800515 stw r18,20(r16) + 7718: 80c0030d sth r3,12(r16) + 771c: 81000415 stw r4,16(r16) + 7720: 81000015 stw r4,0(r16) + 7724: dfc01217 ldw ra,72(sp) + 7728: dc801117 ldw r18,68(sp) + 772c: dc401017 ldw r17,64(sp) + 7730: dc000f17 ldw r16,60(sp) + 7734: dec01304 addi sp,sp,76 + 7738: f800283a ret + 773c: 80c0030b ldhu r3,12(r16) + 7740: 1880200c andi r2,r3,128 + 7744: 10000426 beq r2,zero,7758 <__smakebuf_r+0xfc> + 7748: 04801004 movi r18,64 + 774c: 18820014 ori r2,r3,2048 + 7750: 8080030d sth r2,12(r16) + 7754: 003fe506 br 76ec <__smakebuf_r+0x90> + 7758: 04810004 movi r18,1024 + 775c: 003ffb06 br 774c <__smakebuf_r+0xf0> + 7760: 8140038f ldh r5,14(r16) + 7764: 8809883a mov r4,r17 + 7768: 0009edc0 call 9edc <_isatty_r> + 776c: 103fde26 beq r2,zero,76e8 <__smakebuf_r+0x8c> + 7770: 8080030b ldhu r2,12(r16) + 7774: 80c010c4 addi r3,r16,67 + 7778: 04810004 movi r18,1024 + 777c: 10800054 ori r2,r2,1 + 7780: 8080030d sth r2,12(r16) + 7784: 00800044 movi r2,1 + 7788: 80c00415 stw r3,16(r16) + 778c: 80800515 stw r2,20(r16) + 7790: 80c00015 stw r3,0(r16) + 7794: 003fd506 br 76ec <__smakebuf_r+0x90> + 7798: 80c00a17 ldw r3,40(r16) + 779c: 00800074 movhi r2,1 + 77a0: 10a66504 addi r2,r2,-26220 + 77a4: 18bfcb1e bne r3,r2,76d4 <__smakebuf_r+0x78> + 77a8: 8080030b ldhu r2,12(r16) + 77ac: 00c10004 movi r3,1024 + 77b0: 1825883a mov r18,r3 + 77b4: 10c4b03a or r2,r2,r3 + 77b8: 8080030d sth r2,12(r16) + 77bc: 80c01315 stw r3,76(r16) + 77c0: 003fca06 br 76ec <__smakebuf_r+0x90> + 77c4: 8100030b ldhu r4,12(r16) + 77c8: 2080800c andi r2,r4,512 + 77cc: 103fb21e bne r2,zero,7698 <__smakebuf_r+0x3c> + 77d0: 80c010c4 addi r3,r16,67 + 77d4: 21000094 ori r4,r4,2 + 77d8: 00800044 movi r2,1 + 77dc: 80800515 stw r2,20(r16) + 77e0: 8100030d sth r4,12(r16) + 77e4: 80c00415 stw r3,16(r16) + 77e8: 80c00015 stw r3,0(r16) + 77ec: 003faa06 br 7698 <__smakebuf_r+0x3c> + +000077f0 <_malloc_r>: + 77f0: defff604 addi sp,sp,-40 + 77f4: 28c002c4 addi r3,r5,11 + 77f8: 00800584 movi r2,22 + 77fc: dc800215 stw r18,8(sp) + 7800: dfc00915 stw ra,36(sp) + 7804: df000815 stw fp,32(sp) + 7808: ddc00715 stw r23,28(sp) + 780c: dd800615 stw r22,24(sp) + 7810: dd400515 stw r21,20(sp) + 7814: dd000415 stw r20,16(sp) + 7818: dcc00315 stw r19,12(sp) + 781c: dc400115 stw r17,4(sp) + 7820: dc000015 stw r16,0(sp) + 7824: 2025883a mov r18,r4 + 7828: 10c01236 bltu r2,r3,7874 <_malloc_r+0x84> + 782c: 04400404 movi r17,16 + 7830: 8940142e bgeu r17,r5,7884 <_malloc_r+0x94> + 7834: 00800304 movi r2,12 + 7838: 0007883a mov r3,zero + 783c: 90800015 stw r2,0(r18) + 7840: 1805883a mov r2,r3 + 7844: dfc00917 ldw ra,36(sp) + 7848: df000817 ldw fp,32(sp) + 784c: ddc00717 ldw r23,28(sp) + 7850: dd800617 ldw r22,24(sp) + 7854: dd400517 ldw r21,20(sp) + 7858: dd000417 ldw r20,16(sp) + 785c: dcc00317 ldw r19,12(sp) + 7860: dc800217 ldw r18,8(sp) + 7864: dc400117 ldw r17,4(sp) + 7868: dc000017 ldw r16,0(sp) + 786c: dec00a04 addi sp,sp,40 + 7870: f800283a ret + 7874: 00bffe04 movi r2,-8 + 7878: 18a2703a and r17,r3,r2 + 787c: 883fed16 blt r17,zero,7834 <_malloc_r+0x44> + 7880: 897fec36 bltu r17,r5,7834 <_malloc_r+0x44> + 7884: 9009883a mov r4,r18 + 7888: 000cb800 call cb80 <__malloc_lock> + 788c: 00807dc4 movi r2,503 + 7890: 14402b2e bgeu r2,r17,7940 <_malloc_r+0x150> + 7894: 8806d27a srli r3,r17,9 + 7898: 18003f1e bne r3,zero,7998 <_malloc_r+0x1a8> + 789c: 880cd0fa srli r6,r17,3 + 78a0: 300490fa slli r2,r6,3 + 78a4: 02c00074 movhi r11,1 + 78a8: 5ac2b004 addi r11,r11,2752 + 78ac: 12cb883a add r5,r2,r11 + 78b0: 2c000317 ldw r16,12(r5) + 78b4: 580f883a mov r7,r11 + 78b8: 2c00041e bne r5,r16,78cc <_malloc_r+0xdc> + 78bc: 00000a06 br 78e8 <_malloc_r+0xf8> + 78c0: 1800860e bge r3,zero,7adc <_malloc_r+0x2ec> + 78c4: 84000317 ldw r16,12(r16) + 78c8: 2c000726 beq r5,r16,78e8 <_malloc_r+0xf8> + 78cc: 80800117 ldw r2,4(r16) + 78d0: 00ffff04 movi r3,-4 + 78d4: 10c8703a and r4,r2,r3 + 78d8: 2447c83a sub r3,r4,r17 + 78dc: 008003c4 movi r2,15 + 78e0: 10fff70e bge r2,r3,78c0 <_malloc_r+0xd0> + 78e4: 31bfffc4 addi r6,r6,-1 + 78e8: 32400044 addi r9,r6,1 + 78ec: 02800074 movhi r10,1 + 78f0: 5282b204 addi r10,r10,2760 + 78f4: 54000217 ldw r16,8(r10) + 78f8: 8280a026 beq r16,r10,7b7c <_malloc_r+0x38c> + 78fc: 80800117 ldw r2,4(r16) + 7900: 00ffff04 movi r3,-4 + 7904: 10ca703a and r5,r2,r3 + 7908: 2c4dc83a sub r6,r5,r17 + 790c: 008003c4 movi r2,15 + 7910: 11808316 blt r2,r6,7b20 <_malloc_r+0x330> + 7914: 52800315 stw r10,12(r10) + 7918: 52800215 stw r10,8(r10) + 791c: 30002916 blt r6,zero,79c4 <_malloc_r+0x1d4> + 7920: 8147883a add r3,r16,r5 + 7924: 18800117 ldw r2,4(r3) + 7928: 9009883a mov r4,r18 + 792c: 10800054 ori r2,r2,1 + 7930: 18800115 stw r2,4(r3) + 7934: 000cba00 call cba0 <__malloc_unlock> + 7938: 80c00204 addi r3,r16,8 + 793c: 003fc006 br 7840 <_malloc_r+0x50> + 7940: 02c00074 movhi r11,1 + 7944: 5ac2b004 addi r11,r11,2752 + 7948: 8ac5883a add r2,r17,r11 + 794c: 14000317 ldw r16,12(r2) + 7950: 580f883a mov r7,r11 + 7954: 8806d0fa srli r3,r17,3 + 7958: 14006c26 beq r2,r16,7b0c <_malloc_r+0x31c> + 795c: 80c00117 ldw r3,4(r16) + 7960: 00bfff04 movi r2,-4 + 7964: 81800317 ldw r6,12(r16) + 7968: 1886703a and r3,r3,r2 + 796c: 80c7883a add r3,r16,r3 + 7970: 18800117 ldw r2,4(r3) + 7974: 81400217 ldw r5,8(r16) + 7978: 9009883a mov r4,r18 + 797c: 10800054 ori r2,r2,1 + 7980: 18800115 stw r2,4(r3) + 7984: 31400215 stw r5,8(r6) + 7988: 29800315 stw r6,12(r5) + 798c: 000cba00 call cba0 <__malloc_unlock> + 7990: 80c00204 addi r3,r16,8 + 7994: 003faa06 br 7840 <_malloc_r+0x50> + 7998: 00800104 movi r2,4 + 799c: 10c0052e bgeu r2,r3,79b4 <_malloc_r+0x1c4> + 79a0: 00800504 movi r2,20 + 79a4: 10c07836 bltu r2,r3,7b88 <_malloc_r+0x398> + 79a8: 198016c4 addi r6,r3,91 + 79ac: 300490fa slli r2,r6,3 + 79b0: 003fbc06 br 78a4 <_malloc_r+0xb4> + 79b4: 8804d1ba srli r2,r17,6 + 79b8: 11800e04 addi r6,r2,56 + 79bc: 300490fa slli r2,r6,3 + 79c0: 003fb806 br 78a4 <_malloc_r+0xb4> + 79c4: 00807fc4 movi r2,511 + 79c8: 1140bb36 bltu r2,r5,7cb8 <_malloc_r+0x4c8> + 79cc: 2806d0fa srli r3,r5,3 + 79d0: 573ffe04 addi fp,r10,-8 + 79d4: 00800044 movi r2,1 + 79d8: 180890fa slli r4,r3,3 + 79dc: 1807d0ba srai r3,r3,2 + 79e0: e1c00117 ldw r7,4(fp) + 79e4: 5909883a add r4,r11,r4 + 79e8: 21400217 ldw r5,8(r4) + 79ec: 10c4983a sll r2,r2,r3 + 79f0: 81000315 stw r4,12(r16) + 79f4: 81400215 stw r5,8(r16) + 79f8: 388eb03a or r7,r7,r2 + 79fc: 2c000315 stw r16,12(r5) + 7a00: 24000215 stw r16,8(r4) + 7a04: e1c00115 stw r7,4(fp) + 7a08: 4807883a mov r3,r9 + 7a0c: 4800cd16 blt r9,zero,7d44 <_malloc_r+0x554> + 7a10: 1807d0ba srai r3,r3,2 + 7a14: 00800044 movi r2,1 + 7a18: 10c8983a sll r4,r2,r3 + 7a1c: 39004436 bltu r7,r4,7b30 <_malloc_r+0x340> + 7a20: 21c4703a and r2,r4,r7 + 7a24: 10000a1e bne r2,zero,7a50 <_malloc_r+0x260> + 7a28: 2109883a add r4,r4,r4 + 7a2c: 00bfff04 movi r2,-4 + 7a30: 4884703a and r2,r9,r2 + 7a34: 3906703a and r3,r7,r4 + 7a38: 12400104 addi r9,r2,4 + 7a3c: 1800041e bne r3,zero,7a50 <_malloc_r+0x260> + 7a40: 2109883a add r4,r4,r4 + 7a44: 3904703a and r2,r7,r4 + 7a48: 4a400104 addi r9,r9,4 + 7a4c: 103ffc26 beq r2,zero,7a40 <_malloc_r+0x250> + 7a50: 480490fa slli r2,r9,3 + 7a54: 4819883a mov r12,r9 + 7a58: 023fff04 movi r8,-4 + 7a5c: 589b883a add r13,r11,r2 + 7a60: 6807883a mov r3,r13 + 7a64: 014003c4 movi r5,15 + 7a68: 1c000317 ldw r16,12(r3) + 7a6c: 1c00041e bne r3,r16,7a80 <_malloc_r+0x290> + 7a70: 0000a706 br 7d10 <_malloc_r+0x520> + 7a74: 3000ab0e bge r6,zero,7d24 <_malloc_r+0x534> + 7a78: 84000317 ldw r16,12(r16) + 7a7c: 1c00a426 beq r3,r16,7d10 <_malloc_r+0x520> + 7a80: 80800117 ldw r2,4(r16) + 7a84: 1204703a and r2,r2,r8 + 7a88: 144dc83a sub r6,r2,r17 + 7a8c: 29bff90e bge r5,r6,7a74 <_malloc_r+0x284> + 7a90: 81000317 ldw r4,12(r16) + 7a94: 80c00217 ldw r3,8(r16) + 7a98: 89400054 ori r5,r17,1 + 7a9c: 8445883a add r2,r16,r17 + 7aa0: 20c00215 stw r3,8(r4) + 7aa4: 19000315 stw r4,12(r3) + 7aa8: 81400115 stw r5,4(r16) + 7aac: 1187883a add r3,r2,r6 + 7ab0: 31000054 ori r4,r6,1 + 7ab4: 50800315 stw r2,12(r10) + 7ab8: 50800215 stw r2,8(r10) + 7abc: 19800015 stw r6,0(r3) + 7ac0: 11000115 stw r4,4(r2) + 7ac4: 12800215 stw r10,8(r2) + 7ac8: 12800315 stw r10,12(r2) + 7acc: 9009883a mov r4,r18 + 7ad0: 000cba00 call cba0 <__malloc_unlock> + 7ad4: 80c00204 addi r3,r16,8 + 7ad8: 003f5906 br 7840 <_malloc_r+0x50> + 7adc: 8109883a add r4,r16,r4 + 7ae0: 20800117 ldw r2,4(r4) + 7ae4: 80c00217 ldw r3,8(r16) + 7ae8: 81400317 ldw r5,12(r16) + 7aec: 10800054 ori r2,r2,1 + 7af0: 20800115 stw r2,4(r4) + 7af4: 28c00215 stw r3,8(r5) + 7af8: 19400315 stw r5,12(r3) + 7afc: 9009883a mov r4,r18 + 7b00: 000cba00 call cba0 <__malloc_unlock> + 7b04: 80c00204 addi r3,r16,8 + 7b08: 003f4d06 br 7840 <_malloc_r+0x50> + 7b0c: 80800204 addi r2,r16,8 + 7b10: 14000317 ldw r16,12(r2) + 7b14: 143f911e bne r2,r16,795c <_malloc_r+0x16c> + 7b18: 1a400084 addi r9,r3,2 + 7b1c: 003f7306 br 78ec <_malloc_r+0xfc> + 7b20: 88c00054 ori r3,r17,1 + 7b24: 8445883a add r2,r16,r17 + 7b28: 80c00115 stw r3,4(r16) + 7b2c: 003fdf06 br 7aac <_malloc_r+0x2bc> + 7b30: e4000217 ldw r16,8(fp) + 7b34: 00bfff04 movi r2,-4 + 7b38: 80c00117 ldw r3,4(r16) + 7b3c: 802d883a mov r22,r16 + 7b40: 18aa703a and r21,r3,r2 + 7b44: ac401636 bltu r21,r17,7ba0 <_malloc_r+0x3b0> + 7b48: ac49c83a sub r4,r21,r17 + 7b4c: 008003c4 movi r2,15 + 7b50: 1100130e bge r2,r4,7ba0 <_malloc_r+0x3b0> + 7b54: 88800054 ori r2,r17,1 + 7b58: 8447883a add r3,r16,r17 + 7b5c: 80800115 stw r2,4(r16) + 7b60: 20800054 ori r2,r4,1 + 7b64: 18800115 stw r2,4(r3) + 7b68: e0c00215 stw r3,8(fp) + 7b6c: 9009883a mov r4,r18 + 7b70: 000cba00 call cba0 <__malloc_unlock> + 7b74: 80c00204 addi r3,r16,8 + 7b78: 003f3106 br 7840 <_malloc_r+0x50> + 7b7c: 39c00117 ldw r7,4(r7) + 7b80: 573ffe04 addi fp,r10,-8 + 7b84: 003fa006 br 7a08 <_malloc_r+0x218> + 7b88: 00801504 movi r2,84 + 7b8c: 10c06736 bltu r2,r3,7d2c <_malloc_r+0x53c> + 7b90: 8804d33a srli r2,r17,12 + 7b94: 11801b84 addi r6,r2,110 + 7b98: 300490fa slli r2,r6,3 + 7b9c: 003f4106 br 78a4 <_malloc_r+0xb4> + 7ba0: d0a6fd17 ldw r2,-25612(gp) + 7ba4: d0e00717 ldw r3,-32740(gp) + 7ba8: 053fffc4 movi r20,-1 + 7bac: 10800404 addi r2,r2,16 + 7bb0: 88a7883a add r19,r17,r2 + 7bb4: 1d000326 beq r3,r20,7bc4 <_malloc_r+0x3d4> + 7bb8: 98c3ffc4 addi r3,r19,4095 + 7bbc: 00bc0004 movi r2,-4096 + 7bc0: 18a6703a and r19,r3,r2 + 7bc4: 9009883a mov r4,r18 + 7bc8: 980b883a mov r5,r19 + 7bcc: 000991c0 call 991c <_sbrk_r> + 7bd0: 1009883a mov r4,r2 + 7bd4: 15000426 beq r2,r20,7be8 <_malloc_r+0x3f8> + 7bd8: 854b883a add r5,r16,r21 + 7bdc: 1029883a mov r20,r2 + 7be0: 11405a2e bgeu r2,r5,7d4c <_malloc_r+0x55c> + 7be4: 87000c26 beq r16,fp,7c18 <_malloc_r+0x428> + 7be8: e4000217 ldw r16,8(fp) + 7bec: 80c00117 ldw r3,4(r16) + 7bf0: 00bfff04 movi r2,-4 + 7bf4: 1884703a and r2,r3,r2 + 7bf8: 14400336 bltu r2,r17,7c08 <_malloc_r+0x418> + 7bfc: 1449c83a sub r4,r2,r17 + 7c00: 008003c4 movi r2,15 + 7c04: 113fd316 blt r2,r4,7b54 <_malloc_r+0x364> + 7c08: 9009883a mov r4,r18 + 7c0c: 000cba00 call cba0 <__malloc_unlock> + 7c10: 0007883a mov r3,zero + 7c14: 003f0a06 br 7840 <_malloc_r+0x50> + 7c18: 05c00074 movhi r23,1 + 7c1c: bdd0c304 addi r23,r23,17164 + 7c20: b8800017 ldw r2,0(r23) + 7c24: 988d883a add r6,r19,r2 + 7c28: b9800015 stw r6,0(r23) + 7c2c: d0e00717 ldw r3,-32740(gp) + 7c30: 00bfffc4 movi r2,-1 + 7c34: 18808e26 beq r3,r2,7e70 <_malloc_r+0x680> + 7c38: 2145c83a sub r2,r4,r5 + 7c3c: 3085883a add r2,r6,r2 + 7c40: b8800015 stw r2,0(r23) + 7c44: 20c001cc andi r3,r4,7 + 7c48: 18005f1e bne r3,zero,7dc8 <_malloc_r+0x5d8> + 7c4c: 000b883a mov r5,zero + 7c50: a4c5883a add r2,r20,r19 + 7c54: 1083ffcc andi r2,r2,4095 + 7c58: 00c40004 movi r3,4096 + 7c5c: 1887c83a sub r3,r3,r2 + 7c60: 28e7883a add r19,r5,r3 + 7c64: 9009883a mov r4,r18 + 7c68: 980b883a mov r5,r19 + 7c6c: 000991c0 call 991c <_sbrk_r> + 7c70: 1007883a mov r3,r2 + 7c74: 00bfffc4 movi r2,-1 + 7c78: 18807a26 beq r3,r2,7e64 <_malloc_r+0x674> + 7c7c: 1d05c83a sub r2,r3,r20 + 7c80: 9885883a add r2,r19,r2 + 7c84: 10c00054 ori r3,r2,1 + 7c88: b8800017 ldw r2,0(r23) + 7c8c: a021883a mov r16,r20 + 7c90: a0c00115 stw r3,4(r20) + 7c94: 9885883a add r2,r19,r2 + 7c98: b8800015 stw r2,0(r23) + 7c9c: e5000215 stw r20,8(fp) + 7ca0: b7003626 beq r22,fp,7d7c <_malloc_r+0x58c> + 7ca4: 018003c4 movi r6,15 + 7ca8: 35404b36 bltu r6,r21,7dd8 <_malloc_r+0x5e8> + 7cac: 00800044 movi r2,1 + 7cb0: a0800115 stw r2,4(r20) + 7cb4: 003fcd06 br 7bec <_malloc_r+0x3fc> + 7cb8: 2808d27a srli r4,r5,9 + 7cbc: 2000371e bne r4,zero,7d9c <_malloc_r+0x5ac> + 7cc0: 2808d0fa srli r4,r5,3 + 7cc4: 200690fa slli r3,r4,3 + 7cc8: 1ad1883a add r8,r3,r11 + 7ccc: 41800217 ldw r6,8(r8) + 7cd0: 41805b26 beq r8,r6,7e40 <_malloc_r+0x650> + 7cd4: 30800117 ldw r2,4(r6) + 7cd8: 00ffff04 movi r3,-4 + 7cdc: 10c4703a and r2,r2,r3 + 7ce0: 2880022e bgeu r5,r2,7cec <_malloc_r+0x4fc> + 7ce4: 31800217 ldw r6,8(r6) + 7ce8: 41bffa1e bne r8,r6,7cd4 <_malloc_r+0x4e4> + 7cec: 32000317 ldw r8,12(r6) + 7cf0: 39c00117 ldw r7,4(r7) + 7cf4: 82000315 stw r8,12(r16) + 7cf8: 81800215 stw r6,8(r16) + 7cfc: 07000074 movhi fp,1 + 7d00: e702b004 addi fp,fp,2752 + 7d04: 34000315 stw r16,12(r6) + 7d08: 44000215 stw r16,8(r8) + 7d0c: 003f3e06 br 7a08 <_malloc_r+0x218> + 7d10: 63000044 addi r12,r12,1 + 7d14: 608000cc andi r2,r12,3 + 7d18: 10005d26 beq r2,zero,7e90 <_malloc_r+0x6a0> + 7d1c: 18c00204 addi r3,r3,8 + 7d20: 003f5106 br 7a68 <_malloc_r+0x278> + 7d24: 8089883a add r4,r16,r2 + 7d28: 003f6d06 br 7ae0 <_malloc_r+0x2f0> + 7d2c: 00805504 movi r2,340 + 7d30: 10c02036 bltu r2,r3,7db4 <_malloc_r+0x5c4> + 7d34: 8804d3fa srli r2,r17,15 + 7d38: 11801dc4 addi r6,r2,119 + 7d3c: 300490fa slli r2,r6,3 + 7d40: 003ed806 br 78a4 <_malloc_r+0xb4> + 7d44: 48c000c4 addi r3,r9,3 + 7d48: 003f3106 br 7a10 <_malloc_r+0x220> + 7d4c: 05c00074 movhi r23,1 + 7d50: bdd0c304 addi r23,r23,17164 + 7d54: b8800017 ldw r2,0(r23) + 7d58: 988d883a add r6,r19,r2 + 7d5c: b9800015 stw r6,0(r23) + 7d60: 293fb21e bne r5,r4,7c2c <_malloc_r+0x43c> + 7d64: 2083ffcc andi r2,r4,4095 + 7d68: 103fb01e bne r2,zero,7c2c <_malloc_r+0x43c> + 7d6c: e4000217 ldw r16,8(fp) + 7d70: 9d45883a add r2,r19,r21 + 7d74: 10800054 ori r2,r2,1 + 7d78: 80800115 stw r2,4(r16) + 7d7c: b8c00017 ldw r3,0(r23) + 7d80: d0a6fe17 ldw r2,-25608(gp) + 7d84: 10c0012e bgeu r2,r3,7d8c <_malloc_r+0x59c> + 7d88: d0e6fe15 stw r3,-25608(gp) + 7d8c: d0a6ff17 ldw r2,-25604(gp) + 7d90: 10ff962e bgeu r2,r3,7bec <_malloc_r+0x3fc> + 7d94: d0e6ff15 stw r3,-25604(gp) + 7d98: 003f9406 br 7bec <_malloc_r+0x3fc> + 7d9c: 00800104 movi r2,4 + 7da0: 11001e36 bltu r2,r4,7e1c <_malloc_r+0x62c> + 7da4: 2804d1ba srli r2,r5,6 + 7da8: 11000e04 addi r4,r2,56 + 7dac: 200690fa slli r3,r4,3 + 7db0: 003fc506 br 7cc8 <_malloc_r+0x4d8> + 7db4: 00815504 movi r2,1364 + 7db8: 10c01d2e bgeu r2,r3,7e30 <_malloc_r+0x640> + 7dbc: 01801f84 movi r6,126 + 7dc0: 0080fc04 movi r2,1008 + 7dc4: 003eb706 br 78a4 <_malloc_r+0xb4> + 7dc8: 00800204 movi r2,8 + 7dcc: 10cbc83a sub r5,r2,r3 + 7dd0: 2169883a add r20,r4,r5 + 7dd4: 003f9e06 br 7c50 <_malloc_r+0x460> + 7dd8: 00bffe04 movi r2,-8 + 7ddc: a93ffd04 addi r4,r21,-12 + 7de0: 2088703a and r4,r4,r2 + 7de4: b10b883a add r5,r22,r4 + 7de8: 00c00144 movi r3,5 + 7dec: 28c00215 stw r3,8(r5) + 7df0: 28c00115 stw r3,4(r5) + 7df4: b0800117 ldw r2,4(r22) + 7df8: 1080004c andi r2,r2,1 + 7dfc: 2084b03a or r2,r4,r2 + 7e00: b0800115 stw r2,4(r22) + 7e04: 313fdd2e bgeu r6,r4,7d7c <_malloc_r+0x58c> + 7e08: b1400204 addi r5,r22,8 + 7e0c: 9009883a mov r4,r18 + 7e10: 0006c680 call 6c68 <_free_r> + 7e14: e4000217 ldw r16,8(fp) + 7e18: 003fd806 br 7d7c <_malloc_r+0x58c> + 7e1c: 00800504 movi r2,20 + 7e20: 11001536 bltu r2,r4,7e78 <_malloc_r+0x688> + 7e24: 210016c4 addi r4,r4,91 + 7e28: 200690fa slli r3,r4,3 + 7e2c: 003fa606 br 7cc8 <_malloc_r+0x4d8> + 7e30: 8804d4ba srli r2,r17,18 + 7e34: 11801f04 addi r6,r2,124 + 7e38: 300490fa slli r2,r6,3 + 7e3c: 003e9906 br 78a4 <_malloc_r+0xb4> + 7e40: 2009d0ba srai r4,r4,2 + 7e44: 01400074 movhi r5,1 + 7e48: 2942b004 addi r5,r5,2752 + 7e4c: 00c00044 movi r3,1 + 7e50: 28800117 ldw r2,4(r5) + 7e54: 1906983a sll r3,r3,r4 + 7e58: 10c4b03a or r2,r2,r3 + 7e5c: 28800115 stw r2,4(r5) + 7e60: 003fa306 br 7cf0 <_malloc_r+0x500> + 7e64: 0027883a mov r19,zero + 7e68: 00c00044 movi r3,1 + 7e6c: 003f8606 br 7c88 <_malloc_r+0x498> + 7e70: d1200715 stw r4,-32740(gp) + 7e74: 003f7306 br 7c44 <_malloc_r+0x454> + 7e78: 00801504 movi r2,84 + 7e7c: 11001936 bltu r2,r4,7ee4 <_malloc_r+0x6f4> + 7e80: 2804d33a srli r2,r5,12 + 7e84: 11001b84 addi r4,r2,110 + 7e88: 200690fa slli r3,r4,3 + 7e8c: 003f8e06 br 7cc8 <_malloc_r+0x4d8> + 7e90: 480b883a mov r5,r9 + 7e94: 6807883a mov r3,r13 + 7e98: 288000cc andi r2,r5,3 + 7e9c: 18fffe04 addi r3,r3,-8 + 7ea0: 297fffc4 addi r5,r5,-1 + 7ea4: 10001526 beq r2,zero,7efc <_malloc_r+0x70c> + 7ea8: 18800217 ldw r2,8(r3) + 7eac: 10fffa26 beq r2,r3,7e98 <_malloc_r+0x6a8> + 7eb0: 2109883a add r4,r4,r4 + 7eb4: 393f1e36 bltu r7,r4,7b30 <_malloc_r+0x340> + 7eb8: 203f1d26 beq r4,zero,7b30 <_malloc_r+0x340> + 7ebc: 21c4703a and r2,r4,r7 + 7ec0: 10000226 beq r2,zero,7ecc <_malloc_r+0x6dc> + 7ec4: 6013883a mov r9,r12 + 7ec8: 003ee106 br 7a50 <_malloc_r+0x260> + 7ecc: 2109883a add r4,r4,r4 + 7ed0: 3904703a and r2,r7,r4 + 7ed4: 63000104 addi r12,r12,4 + 7ed8: 103ffc26 beq r2,zero,7ecc <_malloc_r+0x6dc> + 7edc: 6013883a mov r9,r12 + 7ee0: 003edb06 br 7a50 <_malloc_r+0x260> + 7ee4: 00805504 movi r2,340 + 7ee8: 11000836 bltu r2,r4,7f0c <_malloc_r+0x71c> + 7eec: 2804d3fa srli r2,r5,15 + 7ef0: 11001dc4 addi r4,r2,119 + 7ef4: 200690fa slli r3,r4,3 + 7ef8: 003f7306 br 7cc8 <_malloc_r+0x4d8> + 7efc: 0104303a nor r2,zero,r4 + 7f00: 388e703a and r7,r7,r2 + 7f04: e1c00115 stw r7,4(fp) + 7f08: 003fe906 br 7eb0 <_malloc_r+0x6c0> + 7f0c: 00815504 movi r2,1364 + 7f10: 1100032e bgeu r2,r4,7f20 <_malloc_r+0x730> + 7f14: 01001f84 movi r4,126 + 7f18: 00c0fc04 movi r3,1008 + 7f1c: 003f6a06 br 7cc8 <_malloc_r+0x4d8> + 7f20: 2804d4ba srli r2,r5,18 + 7f24: 11001f04 addi r4,r2,124 + 7f28: 200690fa slli r3,r4,3 + 7f2c: 003f6606 br 7cc8 <_malloc_r+0x4d8> + +00007f30 : + 7f30: 008000c4 movi r2,3 + 7f34: 29403fcc andi r5,r5,255 + 7f38: 2007883a mov r3,r4 + 7f3c: 1180022e bgeu r2,r6,7f48 + 7f40: 2084703a and r2,r4,r2 + 7f44: 10000b26 beq r2,zero,7f74 + 7f48: 313fffc4 addi r4,r6,-1 + 7f4c: 3000051e bne r6,zero,7f64 + 7f50: 00002c06 br 8004 + 7f54: 213fffc4 addi r4,r4,-1 + 7f58: 00bfffc4 movi r2,-1 + 7f5c: 18c00044 addi r3,r3,1 + 7f60: 20802826 beq r4,r2,8004 + 7f64: 18800003 ldbu r2,0(r3) + 7f68: 28bffa1e bne r5,r2,7f54 + 7f6c: 1805883a mov r2,r3 + 7f70: f800283a ret + 7f74: 0011883a mov r8,zero + 7f78: 0007883a mov r3,zero + 7f7c: 01c00104 movi r7,4 + 7f80: 4004923a slli r2,r8,8 + 7f84: 18c00044 addi r3,r3,1 + 7f88: 1151883a add r8,r2,r5 + 7f8c: 19fffc1e bne r3,r7,7f80 + 7f90: 02bfbff4 movhi r10,65279 + 7f94: 52bfbfc4 addi r10,r10,-257 + 7f98: 02602074 movhi r9,32897 + 7f9c: 4a602004 addi r9,r9,-32640 + 7fa0: 02c000c4 movi r11,3 + 7fa4: 20800017 ldw r2,0(r4) + 7fa8: 31bfff04 addi r6,r6,-4 + 7fac: 200f883a mov r7,r4 + 7fb0: 1204f03a xor r2,r2,r8 + 7fb4: 1287883a add r3,r2,r10 + 7fb8: 1a46703a and r3,r3,r9 + 7fbc: 0084303a nor r2,zero,r2 + 7fc0: 10c4703a and r2,r2,r3 + 7fc4: 10000b26 beq r2,zero,7ff4 + 7fc8: 20800003 ldbu r2,0(r4) + 7fcc: 28800f26 beq r5,r2,800c + 7fd0: 20800043 ldbu r2,1(r4) + 7fd4: 21c00044 addi r7,r4,1 + 7fd8: 28800c26 beq r5,r2,800c + 7fdc: 20800083 ldbu r2,2(r4) + 7fe0: 21c00084 addi r7,r4,2 + 7fe4: 28800926 beq r5,r2,800c + 7fe8: 208000c3 ldbu r2,3(r4) + 7fec: 21c000c4 addi r7,r4,3 + 7ff0: 28800626 beq r5,r2,800c + 7ff4: 21000104 addi r4,r4,4 + 7ff8: 59bfea36 bltu r11,r6,7fa4 + 7ffc: 2007883a mov r3,r4 + 8000: 003fd106 br 7f48 + 8004: 0005883a mov r2,zero + 8008: f800283a ret + 800c: 3805883a mov r2,r7 + 8010: f800283a ret + +00008014 : + 8014: 01c003c4 movi r7,15 + 8018: 2007883a mov r3,r4 + 801c: 3980032e bgeu r7,r6,802c + 8020: 2904b03a or r2,r5,r4 + 8024: 108000cc andi r2,r2,3 + 8028: 10000926 beq r2,zero,8050 + 802c: 30000626 beq r6,zero,8048 + 8030: 30cd883a add r6,r6,r3 + 8034: 28800003 ldbu r2,0(r5) + 8038: 29400044 addi r5,r5,1 + 803c: 18800005 stb r2,0(r3) + 8040: 18c00044 addi r3,r3,1 + 8044: 30fffb1e bne r6,r3,8034 + 8048: 2005883a mov r2,r4 + 804c: f800283a ret + 8050: 3811883a mov r8,r7 + 8054: 200f883a mov r7,r4 + 8058: 28c00017 ldw r3,0(r5) + 805c: 31bffc04 addi r6,r6,-16 + 8060: 38c00015 stw r3,0(r7) + 8064: 28800117 ldw r2,4(r5) + 8068: 38800115 stw r2,4(r7) + 806c: 28c00217 ldw r3,8(r5) + 8070: 38c00215 stw r3,8(r7) + 8074: 28800317 ldw r2,12(r5) + 8078: 29400404 addi r5,r5,16 + 807c: 38800315 stw r2,12(r7) + 8080: 39c00404 addi r7,r7,16 + 8084: 41bff436 bltu r8,r6,8058 + 8088: 008000c4 movi r2,3 + 808c: 1180072e bgeu r2,r6,80ac + 8090: 1007883a mov r3,r2 + 8094: 28800017 ldw r2,0(r5) + 8098: 31bfff04 addi r6,r6,-4 + 809c: 29400104 addi r5,r5,4 + 80a0: 38800015 stw r2,0(r7) + 80a4: 39c00104 addi r7,r7,4 + 80a8: 19bffa36 bltu r3,r6,8094 + 80ac: 3807883a mov r3,r7 + 80b0: 003fde06 br 802c + +000080b4 : + 80b4: 2807883a mov r3,r5 + 80b8: 2011883a mov r8,r4 + 80bc: 29000c2e bgeu r5,r4,80f0 + 80c0: 298f883a add r7,r5,r6 + 80c4: 21c00a2e bgeu r4,r7,80f0 + 80c8: 30000726 beq r6,zero,80e8 + 80cc: 2187883a add r3,r4,r6 + 80d0: 198dc83a sub r6,r3,r6 + 80d4: 39ffffc4 addi r7,r7,-1 + 80d8: 38800003 ldbu r2,0(r7) + 80dc: 18ffffc4 addi r3,r3,-1 + 80e0: 18800005 stb r2,0(r3) + 80e4: 19bffb1e bne r3,r6,80d4 + 80e8: 2005883a mov r2,r4 + 80ec: f800283a ret + 80f0: 01c003c4 movi r7,15 + 80f4: 39800a36 bltu r7,r6,8120 + 80f8: 303ffb26 beq r6,zero,80e8 + 80fc: 400f883a mov r7,r8 + 8100: 320d883a add r6,r6,r8 + 8104: 28800003 ldbu r2,0(r5) + 8108: 29400044 addi r5,r5,1 + 810c: 38800005 stb r2,0(r7) + 8110: 39c00044 addi r7,r7,1 + 8114: 39bffb1e bne r7,r6,8104 + 8118: 2005883a mov r2,r4 + 811c: f800283a ret + 8120: 1904b03a or r2,r3,r4 + 8124: 108000cc andi r2,r2,3 + 8128: 103ff31e bne r2,zero,80f8 + 812c: 3811883a mov r8,r7 + 8130: 180b883a mov r5,r3 + 8134: 200f883a mov r7,r4 + 8138: 28c00017 ldw r3,0(r5) + 813c: 31bffc04 addi r6,r6,-16 + 8140: 38c00015 stw r3,0(r7) + 8144: 28800117 ldw r2,4(r5) + 8148: 38800115 stw r2,4(r7) + 814c: 28c00217 ldw r3,8(r5) + 8150: 38c00215 stw r3,8(r7) + 8154: 28800317 ldw r2,12(r5) + 8158: 29400404 addi r5,r5,16 + 815c: 38800315 stw r2,12(r7) + 8160: 39c00404 addi r7,r7,16 + 8164: 41bff436 bltu r8,r6,8138 + 8168: 008000c4 movi r2,3 + 816c: 1180072e bgeu r2,r6,818c + 8170: 1007883a mov r3,r2 + 8174: 28800017 ldw r2,0(r5) + 8178: 31bfff04 addi r6,r6,-4 + 817c: 29400104 addi r5,r5,4 + 8180: 38800015 stw r2,0(r7) + 8184: 39c00104 addi r7,r7,4 + 8188: 19bffa36 bltu r3,r6,8174 + 818c: 3811883a mov r8,r7 + 8190: 003fd906 br 80f8 + +00008194 : + 8194: 008000c4 movi r2,3 + 8198: 29403fcc andi r5,r5,255 + 819c: 2007883a mov r3,r4 + 81a0: 1180022e bgeu r2,r6,81ac + 81a4: 2084703a and r2,r4,r2 + 81a8: 10000826 beq r2,zero,81cc + 81ac: 30000526 beq r6,zero,81c4 + 81b0: 2805883a mov r2,r5 + 81b4: 30cd883a add r6,r6,r3 + 81b8: 18800005 stb r2,0(r3) + 81bc: 18c00044 addi r3,r3,1 + 81c0: 19bffd1e bne r3,r6,81b8 + 81c4: 2005883a mov r2,r4 + 81c8: f800283a ret + 81cc: 2804923a slli r2,r5,8 + 81d0: 020003c4 movi r8,15 + 81d4: 200f883a mov r7,r4 + 81d8: 2884b03a or r2,r5,r2 + 81dc: 1006943a slli r3,r2,16 + 81e0: 10c6b03a or r3,r2,r3 + 81e4: 41800a2e bgeu r8,r6,8210 + 81e8: 4005883a mov r2,r8 + 81ec: 31bffc04 addi r6,r6,-16 + 81f0: 38c00015 stw r3,0(r7) + 81f4: 38c00115 stw r3,4(r7) + 81f8: 38c00215 stw r3,8(r7) + 81fc: 38c00315 stw r3,12(r7) + 8200: 39c00404 addi r7,r7,16 + 8204: 11bff936 bltu r2,r6,81ec + 8208: 008000c4 movi r2,3 + 820c: 1180052e bgeu r2,r6,8224 + 8210: 31bfff04 addi r6,r6,-4 + 8214: 008000c4 movi r2,3 + 8218: 38c00015 stw r3,0(r7) + 821c: 39c00104 addi r7,r7,4 + 8220: 11bffb36 bltu r2,r6,8210 + 8224: 3807883a mov r3,r7 + 8228: 003fe006 br 81ac + +0000822c <_Bfree>: + 822c: 28000826 beq r5,zero,8250 <_Bfree+0x24> + 8230: 28800117 ldw r2,4(r5) + 8234: 21001317 ldw r4,76(r4) + 8238: 1085883a add r2,r2,r2 + 823c: 1085883a add r2,r2,r2 + 8240: 1105883a add r2,r2,r4 + 8244: 10c00017 ldw r3,0(r2) + 8248: 28c00015 stw r3,0(r5) + 824c: 11400015 stw r5,0(r2) + 8250: f800283a ret + +00008254 <__hi0bits>: + 8254: 20bfffec andhi r2,r4,65535 + 8258: 10001426 beq r2,zero,82ac <__hi0bits+0x58> + 825c: 0007883a mov r3,zero + 8260: 20bfc02c andhi r2,r4,65280 + 8264: 1000021e bne r2,zero,8270 <__hi0bits+0x1c> + 8268: 2008923a slli r4,r4,8 + 826c: 18c00204 addi r3,r3,8 + 8270: 20bc002c andhi r2,r4,61440 + 8274: 1000021e bne r2,zero,8280 <__hi0bits+0x2c> + 8278: 2008913a slli r4,r4,4 + 827c: 18c00104 addi r3,r3,4 + 8280: 20b0002c andhi r2,r4,49152 + 8284: 1000031e bne r2,zero,8294 <__hi0bits+0x40> + 8288: 2105883a add r2,r4,r4 + 828c: 18c00084 addi r3,r3,2 + 8290: 1089883a add r4,r2,r2 + 8294: 20000316 blt r4,zero,82a4 <__hi0bits+0x50> + 8298: 2090002c andhi r2,r4,16384 + 829c: 10000626 beq r2,zero,82b8 <__hi0bits+0x64> + 82a0: 18c00044 addi r3,r3,1 + 82a4: 1805883a mov r2,r3 + 82a8: f800283a ret + 82ac: 2008943a slli r4,r4,16 + 82b0: 00c00404 movi r3,16 + 82b4: 003fea06 br 8260 <__hi0bits+0xc> + 82b8: 00c00804 movi r3,32 + 82bc: 1805883a mov r2,r3 + 82c0: f800283a ret + +000082c4 <__lo0bits>: + 82c4: 20c00017 ldw r3,0(r4) + 82c8: 188001cc andi r2,r3,7 + 82cc: 10000a26 beq r2,zero,82f8 <__lo0bits+0x34> + 82d0: 1880004c andi r2,r3,1 + 82d4: 1005003a cmpeq r2,r2,zero + 82d8: 10002126 beq r2,zero,8360 <__lo0bits+0x9c> + 82dc: 1880008c andi r2,r3,2 + 82e0: 1000251e bne r2,zero,8378 <__lo0bits+0xb4> + 82e4: 1804d0ba srli r2,r3,2 + 82e8: 01400084 movi r5,2 + 82ec: 20800015 stw r2,0(r4) + 82f0: 2805883a mov r2,r5 + 82f4: f800283a ret + 82f8: 18bfffcc andi r2,r3,65535 + 82fc: 10001526 beq r2,zero,8354 <__lo0bits+0x90> + 8300: 000b883a mov r5,zero + 8304: 18803fcc andi r2,r3,255 + 8308: 1000021e bne r2,zero,8314 <__lo0bits+0x50> + 830c: 1806d23a srli r3,r3,8 + 8310: 29400204 addi r5,r5,8 + 8314: 188003cc andi r2,r3,15 + 8318: 1000021e bne r2,zero,8324 <__lo0bits+0x60> + 831c: 1806d13a srli r3,r3,4 + 8320: 29400104 addi r5,r5,4 + 8324: 188000cc andi r2,r3,3 + 8328: 1000021e bne r2,zero,8334 <__lo0bits+0x70> + 832c: 1806d0ba srli r3,r3,2 + 8330: 29400084 addi r5,r5,2 + 8334: 1880004c andi r2,r3,1 + 8338: 1000031e bne r2,zero,8348 <__lo0bits+0x84> + 833c: 1806d07a srli r3,r3,1 + 8340: 18000a26 beq r3,zero,836c <__lo0bits+0xa8> + 8344: 29400044 addi r5,r5,1 + 8348: 2805883a mov r2,r5 + 834c: 20c00015 stw r3,0(r4) + 8350: f800283a ret + 8354: 1806d43a srli r3,r3,16 + 8358: 01400404 movi r5,16 + 835c: 003fe906 br 8304 <__lo0bits+0x40> + 8360: 000b883a mov r5,zero + 8364: 2805883a mov r2,r5 + 8368: f800283a ret + 836c: 01400804 movi r5,32 + 8370: 2805883a mov r2,r5 + 8374: f800283a ret + 8378: 1804d07a srli r2,r3,1 + 837c: 01400044 movi r5,1 + 8380: 20800015 stw r2,0(r4) + 8384: 003fda06 br 82f0 <__lo0bits+0x2c> + +00008388 <__mcmp>: + 8388: 20800417 ldw r2,16(r4) + 838c: 28c00417 ldw r3,16(r5) + 8390: 10cfc83a sub r7,r2,r3 + 8394: 38000c1e bne r7,zero,83c8 <__mcmp+0x40> + 8398: 18c5883a add r2,r3,r3 + 839c: 1085883a add r2,r2,r2 + 83a0: 10c00504 addi r3,r2,20 + 83a4: 21000504 addi r4,r4,20 + 83a8: 28cb883a add r5,r5,r3 + 83ac: 2085883a add r2,r4,r2 + 83b0: 10bfff04 addi r2,r2,-4 + 83b4: 297fff04 addi r5,r5,-4 + 83b8: 11800017 ldw r6,0(r2) + 83bc: 28c00017 ldw r3,0(r5) + 83c0: 30c0031e bne r6,r3,83d0 <__mcmp+0x48> + 83c4: 20bffa36 bltu r4,r2,83b0 <__mcmp+0x28> + 83c8: 3805883a mov r2,r7 + 83cc: f800283a ret + 83d0: 30c00336 bltu r6,r3,83e0 <__mcmp+0x58> + 83d4: 01c00044 movi r7,1 + 83d8: 3805883a mov r2,r7 + 83dc: f800283a ret + 83e0: 01ffffc4 movi r7,-1 + 83e4: 003ff806 br 83c8 <__mcmp+0x40> + +000083e8 <__ulp>: + 83e8: 295ffc2c andhi r5,r5,32752 + 83ec: 013f3034 movhi r4,64704 + 83f0: 290b883a add r5,r5,r4 + 83f4: 0145c83a sub r2,zero,r5 + 83f8: 1007d53a srai r3,r2,20 + 83fc: 000d883a mov r6,zero + 8400: 0140040e bge zero,r5,8414 <__ulp+0x2c> + 8404: 280f883a mov r7,r5 + 8408: 3807883a mov r3,r7 + 840c: 3005883a mov r2,r6 + 8410: f800283a ret + 8414: 008004c4 movi r2,19 + 8418: 193ffb04 addi r4,r3,-20 + 841c: 10c00c0e bge r2,r3,8450 <__ulp+0x68> + 8420: 008007c4 movi r2,31 + 8424: 1107c83a sub r3,r2,r4 + 8428: 00800784 movi r2,30 + 842c: 01400044 movi r5,1 + 8430: 11000216 blt r2,r4,843c <__ulp+0x54> + 8434: 00800044 movi r2,1 + 8438: 10ca983a sll r5,r2,r3 + 843c: 000f883a mov r7,zero + 8440: 280d883a mov r6,r5 + 8444: 3807883a mov r3,r7 + 8448: 3005883a mov r2,r6 + 844c: f800283a ret + 8450: 00800234 movhi r2,8 + 8454: 10cfd83a sra r7,r2,r3 + 8458: 000d883a mov r6,zero + 845c: 3005883a mov r2,r6 + 8460: 3807883a mov r3,r7 + 8464: f800283a ret + +00008468 <__b2d>: + 8468: 20800417 ldw r2,16(r4) + 846c: defff904 addi sp,sp,-28 + 8470: dd000415 stw r20,16(sp) + 8474: 1085883a add r2,r2,r2 + 8478: 25000504 addi r20,r4,20 + 847c: 1085883a add r2,r2,r2 + 8480: dc000015 stw r16,0(sp) + 8484: a0a1883a add r16,r20,r2 + 8488: dd400515 stw r21,20(sp) + 848c: 857fff17 ldw r21,-4(r16) + 8490: dc400115 stw r17,4(sp) + 8494: dfc00615 stw ra,24(sp) + 8498: a809883a mov r4,r21 + 849c: 2823883a mov r17,r5 + 84a0: dcc00315 stw r19,12(sp) + 84a4: dc800215 stw r18,8(sp) + 84a8: 00082540 call 8254 <__hi0bits> + 84ac: 100b883a mov r5,r2 + 84b0: 00800804 movi r2,32 + 84b4: 1145c83a sub r2,r2,r5 + 84b8: 88800015 stw r2,0(r17) + 84bc: 00800284 movi r2,10 + 84c0: 80ffff04 addi r3,r16,-4 + 84c4: 11401416 blt r2,r5,8518 <__b2d+0xb0> + 84c8: 008002c4 movi r2,11 + 84cc: 1149c83a sub r4,r2,r5 + 84d0: a0c02736 bltu r20,r3,8570 <__b2d+0x108> + 84d4: 000d883a mov r6,zero + 84d8: 28800544 addi r2,r5,21 + 84dc: a906d83a srl r3,r21,r4 + 84e0: a884983a sll r2,r21,r2 + 84e4: 1ccffc34 orhi r19,r3,16368 + 84e8: 11a4b03a or r18,r2,r6 + 84ec: 9005883a mov r2,r18 + 84f0: 9807883a mov r3,r19 + 84f4: dfc00617 ldw ra,24(sp) + 84f8: dd400517 ldw r21,20(sp) + 84fc: dd000417 ldw r20,16(sp) + 8500: dcc00317 ldw r19,12(sp) + 8504: dc800217 ldw r18,8(sp) + 8508: dc400117 ldw r17,4(sp) + 850c: dc000017 ldw r16,0(sp) + 8510: dec00704 addi sp,sp,28 + 8514: f800283a ret + 8518: a0c00e36 bltu r20,r3,8554 <__b2d+0xec> + 851c: 293ffd44 addi r4,r5,-11 + 8520: 000d883a mov r6,zero + 8524: 20000f26 beq r4,zero,8564 <__b2d+0xfc> + 8528: 00800804 movi r2,32 + 852c: 110bc83a sub r5,r2,r4 + 8530: a0c01236 bltu r20,r3,857c <__b2d+0x114> + 8534: 000f883a mov r7,zero + 8538: a904983a sll r2,r21,r4 + 853c: 3146d83a srl r3,r6,r5 + 8540: 3108983a sll r4,r6,r4 + 8544: 108ffc34 orhi r2,r2,16368 + 8548: 18a6b03a or r19,r3,r2 + 854c: 3924b03a or r18,r7,r4 + 8550: 003fe606 br 84ec <__b2d+0x84> + 8554: 293ffd44 addi r4,r5,-11 + 8558: 81bffe17 ldw r6,-8(r16) + 855c: 80fffe04 addi r3,r16,-8 + 8560: 203ff11e bne r4,zero,8528 <__b2d+0xc0> + 8564: accffc34 orhi r19,r21,16368 + 8568: 3025883a mov r18,r6 + 856c: 003fdf06 br 84ec <__b2d+0x84> + 8570: 18bfff17 ldw r2,-4(r3) + 8574: 110cd83a srl r6,r2,r4 + 8578: 003fd706 br 84d8 <__b2d+0x70> + 857c: 18bfff17 ldw r2,-4(r3) + 8580: 114ed83a srl r7,r2,r5 + 8584: 003fec06 br 8538 <__b2d+0xd0> + +00008588 <__ratio>: + 8588: defff904 addi sp,sp,-28 + 858c: dc400215 stw r17,8(sp) + 8590: 2823883a mov r17,r5 + 8594: d80b883a mov r5,sp + 8598: dfc00615 stw ra,24(sp) + 859c: dd000515 stw r20,20(sp) + 85a0: dcc00415 stw r19,16(sp) + 85a4: dc800315 stw r18,12(sp) + 85a8: 2025883a mov r18,r4 + 85ac: 00084680 call 8468 <__b2d> + 85b0: 8809883a mov r4,r17 + 85b4: d9400104 addi r5,sp,4 + 85b8: 1027883a mov r19,r2 + 85bc: 1829883a mov r20,r3 + 85c0: 00084680 call 8468 <__b2d> + 85c4: 89000417 ldw r4,16(r17) + 85c8: 91c00417 ldw r7,16(r18) + 85cc: d9800117 ldw r6,4(sp) + 85d0: 180b883a mov r5,r3 + 85d4: 390fc83a sub r7,r7,r4 + 85d8: 1009883a mov r4,r2 + 85dc: d8800017 ldw r2,0(sp) + 85e0: 380e917a slli r7,r7,5 + 85e4: 2011883a mov r8,r4 + 85e8: 1185c83a sub r2,r2,r6 + 85ec: 11c5883a add r2,r2,r7 + 85f0: 1006953a slli r3,r2,20 + 85f4: 2813883a mov r9,r5 + 85f8: 00800d0e bge zero,r2,8630 <__ratio+0xa8> + 85fc: 1d29883a add r20,r3,r20 + 8600: a00b883a mov r5,r20 + 8604: 480f883a mov r7,r9 + 8608: 9809883a mov r4,r19 + 860c: 400d883a mov r6,r8 + 8610: 000b5d00 call b5d0 <__divdf3> + 8614: dfc00617 ldw ra,24(sp) + 8618: dd000517 ldw r20,20(sp) + 861c: dcc00417 ldw r19,16(sp) + 8620: dc800317 ldw r18,12(sp) + 8624: dc400217 ldw r17,8(sp) + 8628: dec00704 addi sp,sp,28 + 862c: f800283a ret + 8630: 28d3c83a sub r9,r5,r3 + 8634: 003ff206 br 8600 <__ratio+0x78> + +00008638 <_mprec_log10>: + 8638: defffe04 addi sp,sp,-8 + 863c: 008005c4 movi r2,23 + 8640: dc000015 stw r16,0(sp) + 8644: dfc00115 stw ra,4(sp) + 8648: 2021883a mov r16,r4 + 864c: 11000c16 blt r2,r4,8680 <_mprec_log10+0x48> + 8650: 200490fa slli r2,r4,3 + 8654: 00c00074 movhi r3,1 + 8658: 18c10f04 addi r3,r3,1084 + 865c: 10c5883a add r2,r2,r3 + 8660: 12400117 ldw r9,4(r2) + 8664: 12000017 ldw r8,0(r2) + 8668: 4807883a mov r3,r9 + 866c: 4005883a mov r2,r8 + 8670: dfc00117 ldw ra,4(sp) + 8674: dc000017 ldw r16,0(sp) + 8678: dec00204 addi sp,sp,8 + 867c: f800283a ret + 8680: 0011883a mov r8,zero + 8684: 024ffc34 movhi r9,16368 + 8688: 0005883a mov r2,zero + 868c: 00d00934 movhi r3,16420 + 8690: 480b883a mov r5,r9 + 8694: 4009883a mov r4,r8 + 8698: 180f883a mov r7,r3 + 869c: 100d883a mov r6,r2 + 86a0: 000b20c0 call b20c <__muldf3> + 86a4: 843fffc4 addi r16,r16,-1 + 86a8: 1011883a mov r8,r2 + 86ac: 1813883a mov r9,r3 + 86b0: 803ff51e bne r16,zero,8688 <_mprec_log10+0x50> + 86b4: 4005883a mov r2,r8 + 86b8: 4807883a mov r3,r9 + 86bc: dfc00117 ldw ra,4(sp) + 86c0: dc000017 ldw r16,0(sp) + 86c4: dec00204 addi sp,sp,8 + 86c8: f800283a ret + +000086cc <__copybits>: + 86cc: 297fffc4 addi r5,r5,-1 + 86d0: 30800417 ldw r2,16(r6) + 86d4: 280bd17a srai r5,r5,5 + 86d8: 31800504 addi r6,r6,20 + 86dc: 1085883a add r2,r2,r2 + 86e0: 294b883a add r5,r5,r5 + 86e4: 294b883a add r5,r5,r5 + 86e8: 1085883a add r2,r2,r2 + 86ec: 290b883a add r5,r5,r4 + 86f0: 3087883a add r3,r6,r2 + 86f4: 29400104 addi r5,r5,4 + 86f8: 30c0052e bgeu r6,r3,8710 <__copybits+0x44> + 86fc: 30800017 ldw r2,0(r6) + 8700: 31800104 addi r6,r6,4 + 8704: 20800015 stw r2,0(r4) + 8708: 21000104 addi r4,r4,4 + 870c: 30fffb36 bltu r6,r3,86fc <__copybits+0x30> + 8710: 2140032e bgeu r4,r5,8720 <__copybits+0x54> + 8714: 20000015 stw zero,0(r4) + 8718: 21000104 addi r4,r4,4 + 871c: 217ffd36 bltu r4,r5,8714 <__copybits+0x48> + 8720: f800283a ret + +00008724 <__any_on>: + 8724: 20800417 ldw r2,16(r4) + 8728: 2807d17a srai r3,r5,5 + 872c: 21000504 addi r4,r4,20 + 8730: 10c00d0e bge r2,r3,8768 <__any_on+0x44> + 8734: 1085883a add r2,r2,r2 + 8738: 1085883a add r2,r2,r2 + 873c: 208d883a add r6,r4,r2 + 8740: 2180182e bgeu r4,r6,87a4 <__any_on+0x80> + 8744: 30bfff17 ldw r2,-4(r6) + 8748: 30ffff04 addi r3,r6,-4 + 874c: 1000041e bne r2,zero,8760 <__any_on+0x3c> + 8750: 20c0142e bgeu r4,r3,87a4 <__any_on+0x80> + 8754: 18ffff04 addi r3,r3,-4 + 8758: 18800017 ldw r2,0(r3) + 875c: 103ffc26 beq r2,zero,8750 <__any_on+0x2c> + 8760: 00800044 movi r2,1 + 8764: f800283a ret + 8768: 18800a0e bge r3,r2,8794 <__any_on+0x70> + 876c: 294007cc andi r5,r5,31 + 8770: 28000826 beq r5,zero,8794 <__any_on+0x70> + 8774: 18c5883a add r2,r3,r3 + 8778: 1085883a add r2,r2,r2 + 877c: 208d883a add r6,r4,r2 + 8780: 30c00017 ldw r3,0(r6) + 8784: 1944d83a srl r2,r3,r5 + 8788: 1144983a sll r2,r2,r5 + 878c: 18bff41e bne r3,r2,8760 <__any_on+0x3c> + 8790: 003feb06 br 8740 <__any_on+0x1c> + 8794: 18c5883a add r2,r3,r3 + 8798: 1085883a add r2,r2,r2 + 879c: 208d883a add r6,r4,r2 + 87a0: 003fe706 br 8740 <__any_on+0x1c> + 87a4: 0005883a mov r2,zero + 87a8: f800283a ret + +000087ac <_Balloc>: + 87ac: 20c01317 ldw r3,76(r4) + 87b0: defffb04 addi sp,sp,-20 + 87b4: dcc00315 stw r19,12(sp) + 87b8: dc800215 stw r18,8(sp) + 87bc: dfc00415 stw ra,16(sp) + 87c0: 2825883a mov r18,r5 + 87c4: dc400115 stw r17,4(sp) + 87c8: dc000015 stw r16,0(sp) + 87cc: 2027883a mov r19,r4 + 87d0: 01800404 movi r6,16 + 87d4: 01400104 movi r5,4 + 87d8: 18001726 beq r3,zero,8838 <_Balloc+0x8c> + 87dc: 01400044 movi r5,1 + 87e0: 9485883a add r2,r18,r18 + 87e4: 2ca2983a sll r17,r5,r18 + 87e8: 1085883a add r2,r2,r2 + 87ec: 10c7883a add r3,r2,r3 + 87f0: 1c000017 ldw r16,0(r3) + 87f4: 8c4d883a add r6,r17,r17 + 87f8: 318d883a add r6,r6,r6 + 87fc: 9809883a mov r4,r19 + 8800: 31800504 addi r6,r6,20 + 8804: 80001226 beq r16,zero,8850 <_Balloc+0xa4> + 8808: 80800017 ldw r2,0(r16) + 880c: 18800015 stw r2,0(r3) + 8810: 80000415 stw zero,16(r16) + 8814: 80000315 stw zero,12(r16) + 8818: 8005883a mov r2,r16 + 881c: dfc00417 ldw ra,16(sp) + 8820: dcc00317 ldw r19,12(sp) + 8824: dc800217 ldw r18,8(sp) + 8828: dc400117 ldw r17,4(sp) + 882c: dc000017 ldw r16,0(sp) + 8830: dec00504 addi sp,sp,20 + 8834: f800283a ret + 8838: 0009c0c0 call 9c0c <_calloc_r> + 883c: 1007883a mov r3,r2 + 8840: 0021883a mov r16,zero + 8844: 98801315 stw r2,76(r19) + 8848: 103fe41e bne r2,zero,87dc <_Balloc+0x30> + 884c: 003ff206 br 8818 <_Balloc+0x6c> + 8850: 0009c0c0 call 9c0c <_calloc_r> + 8854: 103ff026 beq r2,zero,8818 <_Balloc+0x6c> + 8858: 1021883a mov r16,r2 + 885c: 14800115 stw r18,4(r2) + 8860: 14400215 stw r17,8(r2) + 8864: 003fea06 br 8810 <_Balloc+0x64> + +00008868 <__d2b>: + 8868: defff504 addi sp,sp,-44 + 886c: dcc00515 stw r19,20(sp) + 8870: 04c00044 movi r19,1 + 8874: dc000215 stw r16,8(sp) + 8878: 2821883a mov r16,r5 + 887c: 980b883a mov r5,r19 + 8880: ddc00915 stw r23,36(sp) + 8884: dd800815 stw r22,32(sp) + 8888: dd400715 stw r21,28(sp) + 888c: dd000615 stw r20,24(sp) + 8890: dc800415 stw r18,16(sp) + 8894: dc400315 stw r17,12(sp) + 8898: dfc00a15 stw ra,40(sp) + 889c: 3023883a mov r17,r6 + 88a0: 382d883a mov r22,r7 + 88a4: ddc00b17 ldw r23,44(sp) + 88a8: 00087ac0 call 87ac <_Balloc> + 88ac: 1025883a mov r18,r2 + 88b0: 00a00034 movhi r2,32768 + 88b4: 10bfffc4 addi r2,r2,-1 + 88b8: 8888703a and r4,r17,r2 + 88bc: 202ad53a srli r21,r4,20 + 88c0: 00800434 movhi r2,16 + 88c4: 10bfffc4 addi r2,r2,-1 + 88c8: 8886703a and r3,r17,r2 + 88cc: a829003a cmpeq r20,r21,zero + 88d0: 800b883a mov r5,r16 + 88d4: d8c00115 stw r3,4(sp) + 88d8: 94000504 addi r16,r18,20 + 88dc: a000021e bne r20,zero,88e8 <__d2b+0x80> + 88e0: 18c00434 orhi r3,r3,16 + 88e4: d8c00115 stw r3,4(sp) + 88e8: 28002726 beq r5,zero,8988 <__d2b+0x120> + 88ec: d809883a mov r4,sp + 88f0: d9400015 stw r5,0(sp) + 88f4: 00082c40 call 82c4 <__lo0bits> + 88f8: 100d883a mov r6,r2 + 88fc: 10003526 beq r2,zero,89d4 <__d2b+0x16c> + 8900: d8c00117 ldw r3,4(sp) + 8904: 00800804 movi r2,32 + 8908: 1185c83a sub r2,r2,r6 + 890c: d9000017 ldw r4,0(sp) + 8910: 1886983a sll r3,r3,r2 + 8914: 1906b03a or r3,r3,r4 + 8918: 90c00515 stw r3,20(r18) + 891c: d8c00117 ldw r3,4(sp) + 8920: 1986d83a srl r3,r3,r6 + 8924: d8c00115 stw r3,4(sp) + 8928: 180b003a cmpeq r5,r3,zero + 892c: 00800084 movi r2,2 + 8930: 114bc83a sub r5,r2,r5 + 8934: 80c00115 stw r3,4(r16) + 8938: 91400415 stw r5,16(r18) + 893c: a0001a1e bne r20,zero,89a8 <__d2b+0x140> + 8940: 3545883a add r2,r6,r21 + 8944: 10bef344 addi r2,r2,-1075 + 8948: 00c00d44 movi r3,53 + 894c: b0800015 stw r2,0(r22) + 8950: 1987c83a sub r3,r3,r6 + 8954: b8c00015 stw r3,0(r23) + 8958: 9005883a mov r2,r18 + 895c: dfc00a17 ldw ra,40(sp) + 8960: ddc00917 ldw r23,36(sp) + 8964: dd800817 ldw r22,32(sp) + 8968: dd400717 ldw r21,28(sp) + 896c: dd000617 ldw r20,24(sp) + 8970: dcc00517 ldw r19,20(sp) + 8974: dc800417 ldw r18,16(sp) + 8978: dc400317 ldw r17,12(sp) + 897c: dc000217 ldw r16,8(sp) + 8980: dec00b04 addi sp,sp,44 + 8984: f800283a ret + 8988: d9000104 addi r4,sp,4 + 898c: 00082c40 call 82c4 <__lo0bits> + 8990: 11800804 addi r6,r2,32 + 8994: d8800117 ldw r2,4(sp) + 8998: 94c00415 stw r19,16(r18) + 899c: 980b883a mov r5,r19 + 89a0: 90800515 stw r2,20(r18) + 89a4: a03fe626 beq r20,zero,8940 <__d2b+0xd8> + 89a8: 2945883a add r2,r5,r5 + 89ac: 1085883a add r2,r2,r2 + 89b0: 1405883a add r2,r2,r16 + 89b4: 113fff17 ldw r4,-4(r2) + 89b8: 30fef384 addi r3,r6,-1074 + 89bc: 2820917a slli r16,r5,5 + 89c0: b0c00015 stw r3,0(r22) + 89c4: 00082540 call 8254 <__hi0bits> + 89c8: 80a1c83a sub r16,r16,r2 + 89cc: bc000015 stw r16,0(r23) + 89d0: 003fe106 br 8958 <__d2b+0xf0> + 89d4: d8800017 ldw r2,0(sp) + 89d8: 90800515 stw r2,20(r18) + 89dc: d8c00117 ldw r3,4(sp) + 89e0: 003fd106 br 8928 <__d2b+0xc0> + +000089e4 <__mdiff>: + 89e4: defffb04 addi sp,sp,-20 + 89e8: dc000015 stw r16,0(sp) + 89ec: 2821883a mov r16,r5 + 89f0: dc800215 stw r18,8(sp) + 89f4: 300b883a mov r5,r6 + 89f8: 2025883a mov r18,r4 + 89fc: 8009883a mov r4,r16 + 8a00: dc400115 stw r17,4(sp) + 8a04: dfc00415 stw ra,16(sp) + 8a08: dcc00315 stw r19,12(sp) + 8a0c: 3023883a mov r17,r6 + 8a10: 00083880 call 8388 <__mcmp> + 8a14: 10004226 beq r2,zero,8b20 <__mdiff+0x13c> + 8a18: 10005016 blt r2,zero,8b5c <__mdiff+0x178> + 8a1c: 0027883a mov r19,zero + 8a20: 81400117 ldw r5,4(r16) + 8a24: 9009883a mov r4,r18 + 8a28: 00087ac0 call 87ac <_Balloc> + 8a2c: 1019883a mov r12,r2 + 8a30: 82800417 ldw r10,16(r16) + 8a34: 88800417 ldw r2,16(r17) + 8a38: 81800504 addi r6,r16,20 + 8a3c: 5287883a add r3,r10,r10 + 8a40: 1085883a add r2,r2,r2 + 8a44: 18c7883a add r3,r3,r3 + 8a48: 1085883a add r2,r2,r2 + 8a4c: 8a000504 addi r8,r17,20 + 8a50: 64c00315 stw r19,12(r12) + 8a54: 30db883a add r13,r6,r3 + 8a58: 4097883a add r11,r8,r2 + 8a5c: 61c00504 addi r7,r12,20 + 8a60: 0013883a mov r9,zero + 8a64: 31000017 ldw r4,0(r6) + 8a68: 41400017 ldw r5,0(r8) + 8a6c: 42000104 addi r8,r8,4 + 8a70: 20bfffcc andi r2,r4,65535 + 8a74: 28ffffcc andi r3,r5,65535 + 8a78: 10c5c83a sub r2,r2,r3 + 8a7c: 1245883a add r2,r2,r9 + 8a80: 2008d43a srli r4,r4,16 + 8a84: 280ad43a srli r5,r5,16 + 8a88: 1007d43a srai r3,r2,16 + 8a8c: 3880000d sth r2,0(r7) + 8a90: 2149c83a sub r4,r4,r5 + 8a94: 20c9883a add r4,r4,r3 + 8a98: 3900008d sth r4,2(r7) + 8a9c: 31800104 addi r6,r6,4 + 8aa0: 39c00104 addi r7,r7,4 + 8aa4: 2013d43a srai r9,r4,16 + 8aa8: 42ffee36 bltu r8,r11,8a64 <__mdiff+0x80> + 8aac: 33400c2e bgeu r6,r13,8ae0 <__mdiff+0xfc> + 8ab0: 30800017 ldw r2,0(r6) + 8ab4: 31800104 addi r6,r6,4 + 8ab8: 10ffffcc andi r3,r2,65535 + 8abc: 1a47883a add r3,r3,r9 + 8ac0: 1004d43a srli r2,r2,16 + 8ac4: 1809d43a srai r4,r3,16 + 8ac8: 38c0000d sth r3,0(r7) + 8acc: 1105883a add r2,r2,r4 + 8ad0: 3880008d sth r2,2(r7) + 8ad4: 1013d43a srai r9,r2,16 + 8ad8: 39c00104 addi r7,r7,4 + 8adc: 337ff436 bltu r6,r13,8ab0 <__mdiff+0xcc> + 8ae0: 38bfff17 ldw r2,-4(r7) + 8ae4: 38ffff04 addi r3,r7,-4 + 8ae8: 1000041e bne r2,zero,8afc <__mdiff+0x118> + 8aec: 18ffff04 addi r3,r3,-4 + 8af0: 18800017 ldw r2,0(r3) + 8af4: 52bfffc4 addi r10,r10,-1 + 8af8: 103ffc26 beq r2,zero,8aec <__mdiff+0x108> + 8afc: 6005883a mov r2,r12 + 8b00: 62800415 stw r10,16(r12) + 8b04: dfc00417 ldw ra,16(sp) + 8b08: dcc00317 ldw r19,12(sp) + 8b0c: dc800217 ldw r18,8(sp) + 8b10: dc400117 ldw r17,4(sp) + 8b14: dc000017 ldw r16,0(sp) + 8b18: dec00504 addi sp,sp,20 + 8b1c: f800283a ret + 8b20: 9009883a mov r4,r18 + 8b24: 000b883a mov r5,zero + 8b28: 00087ac0 call 87ac <_Balloc> + 8b2c: 1019883a mov r12,r2 + 8b30: 00800044 movi r2,1 + 8b34: 60800415 stw r2,16(r12) + 8b38: 6005883a mov r2,r12 + 8b3c: 60000515 stw zero,20(r12) + 8b40: dfc00417 ldw ra,16(sp) + 8b44: dcc00317 ldw r19,12(sp) + 8b48: dc800217 ldw r18,8(sp) + 8b4c: dc400117 ldw r17,4(sp) + 8b50: dc000017 ldw r16,0(sp) + 8b54: dec00504 addi sp,sp,20 + 8b58: f800283a ret + 8b5c: 880d883a mov r6,r17 + 8b60: 04c00044 movi r19,1 + 8b64: 8023883a mov r17,r16 + 8b68: 3021883a mov r16,r6 + 8b6c: 003fac06 br 8a20 <__mdiff+0x3c> + +00008b70 <__lshift>: + 8b70: defff904 addi sp,sp,-28 + 8b74: 28800417 ldw r2,16(r5) + 8b78: dc000015 stw r16,0(sp) + 8b7c: 3021d17a srai r16,r6,5 + 8b80: 28c00217 ldw r3,8(r5) + 8b84: 10800044 addi r2,r2,1 + 8b88: dc400115 stw r17,4(sp) + 8b8c: 80a3883a add r17,r16,r2 + 8b90: dd400515 stw r21,20(sp) + 8b94: dd000415 stw r20,16(sp) + 8b98: dc800215 stw r18,8(sp) + 8b9c: dfc00615 stw ra,24(sp) + 8ba0: 2825883a mov r18,r5 + 8ba4: dcc00315 stw r19,12(sp) + 8ba8: 3029883a mov r20,r6 + 8bac: 202b883a mov r21,r4 + 8bb0: 29400117 ldw r5,4(r5) + 8bb4: 1c40030e bge r3,r17,8bc4 <__lshift+0x54> + 8bb8: 18c7883a add r3,r3,r3 + 8bbc: 29400044 addi r5,r5,1 + 8bc0: 1c7ffd16 blt r3,r17,8bb8 <__lshift+0x48> + 8bc4: a809883a mov r4,r21 + 8bc8: 00087ac0 call 87ac <_Balloc> + 8bcc: 1027883a mov r19,r2 + 8bd0: 11400504 addi r5,r2,20 + 8bd4: 0400090e bge zero,r16,8bfc <__lshift+0x8c> + 8bd8: 2805883a mov r2,r5 + 8bdc: 0007883a mov r3,zero + 8be0: 18c00044 addi r3,r3,1 + 8be4: 10000015 stw zero,0(r2) + 8be8: 10800104 addi r2,r2,4 + 8bec: 80fffc1e bne r16,r3,8be0 <__lshift+0x70> + 8bf0: 8405883a add r2,r16,r16 + 8bf4: 1085883a add r2,r2,r2 + 8bf8: 288b883a add r5,r5,r2 + 8bfc: 90800417 ldw r2,16(r18) + 8c00: 91000504 addi r4,r18,20 + 8c04: a18007cc andi r6,r20,31 + 8c08: 1085883a add r2,r2,r2 + 8c0c: 1085883a add r2,r2,r2 + 8c10: 208f883a add r7,r4,r2 + 8c14: 30001e26 beq r6,zero,8c90 <__lshift+0x120> + 8c18: 00800804 movi r2,32 + 8c1c: 1191c83a sub r8,r2,r6 + 8c20: 0007883a mov r3,zero + 8c24: 20800017 ldw r2,0(r4) + 8c28: 1184983a sll r2,r2,r6 + 8c2c: 1884b03a or r2,r3,r2 + 8c30: 28800015 stw r2,0(r5) + 8c34: 20c00017 ldw r3,0(r4) + 8c38: 21000104 addi r4,r4,4 + 8c3c: 29400104 addi r5,r5,4 + 8c40: 1a06d83a srl r3,r3,r8 + 8c44: 21fff736 bltu r4,r7,8c24 <__lshift+0xb4> + 8c48: 28c00015 stw r3,0(r5) + 8c4c: 18000126 beq r3,zero,8c54 <__lshift+0xe4> + 8c50: 8c400044 addi r17,r17,1 + 8c54: 88bfffc4 addi r2,r17,-1 + 8c58: 98800415 stw r2,16(r19) + 8c5c: a809883a mov r4,r21 + 8c60: 900b883a mov r5,r18 + 8c64: 000822c0 call 822c <_Bfree> + 8c68: 9805883a mov r2,r19 + 8c6c: dfc00617 ldw ra,24(sp) + 8c70: dd400517 ldw r21,20(sp) + 8c74: dd000417 ldw r20,16(sp) + 8c78: dcc00317 ldw r19,12(sp) + 8c7c: dc800217 ldw r18,8(sp) + 8c80: dc400117 ldw r17,4(sp) + 8c84: dc000017 ldw r16,0(sp) + 8c88: dec00704 addi sp,sp,28 + 8c8c: f800283a ret + 8c90: 20800017 ldw r2,0(r4) + 8c94: 21000104 addi r4,r4,4 + 8c98: 28800015 stw r2,0(r5) + 8c9c: 29400104 addi r5,r5,4 + 8ca0: 21ffec2e bgeu r4,r7,8c54 <__lshift+0xe4> + 8ca4: 20800017 ldw r2,0(r4) + 8ca8: 21000104 addi r4,r4,4 + 8cac: 28800015 stw r2,0(r5) + 8cb0: 29400104 addi r5,r5,4 + 8cb4: 21fff636 bltu r4,r7,8c90 <__lshift+0x120> + 8cb8: 003fe606 br 8c54 <__lshift+0xe4> + +00008cbc <__multiply>: + 8cbc: defff004 addi sp,sp,-64 + 8cc0: dc800815 stw r18,32(sp) + 8cc4: dc400715 stw r17,28(sp) + 8cc8: 2c800417 ldw r18,16(r5) + 8ccc: 34400417 ldw r17,16(r6) + 8cd0: dcc00915 stw r19,36(sp) + 8cd4: dc000615 stw r16,24(sp) + 8cd8: dfc00f15 stw ra,60(sp) + 8cdc: df000e15 stw fp,56(sp) + 8ce0: ddc00d15 stw r23,52(sp) + 8ce4: dd800c15 stw r22,48(sp) + 8ce8: dd400b15 stw r21,44(sp) + 8cec: dd000a15 stw r20,40(sp) + 8cf0: 2821883a mov r16,r5 + 8cf4: 3027883a mov r19,r6 + 8cf8: 9440040e bge r18,r17,8d0c <__multiply+0x50> + 8cfc: 8825883a mov r18,r17 + 8d00: 2c400417 ldw r17,16(r5) + 8d04: 2827883a mov r19,r5 + 8d08: 3021883a mov r16,r6 + 8d0c: 80800217 ldw r2,8(r16) + 8d10: 9447883a add r3,r18,r17 + 8d14: d8c00415 stw r3,16(sp) + 8d18: 81400117 ldw r5,4(r16) + 8d1c: 10c0010e bge r2,r3,8d24 <__multiply+0x68> + 8d20: 29400044 addi r5,r5,1 + 8d24: 00087ac0 call 87ac <_Balloc> + 8d28: d8800515 stw r2,20(sp) + 8d2c: d9000417 ldw r4,16(sp) + 8d30: d8c00517 ldw r3,20(sp) + 8d34: 2105883a add r2,r4,r4 + 8d38: 1085883a add r2,r2,r2 + 8d3c: 19000504 addi r4,r3,20 + 8d40: 2085883a add r2,r4,r2 + 8d44: d8800315 stw r2,12(sp) + 8d48: 2080052e bgeu r4,r2,8d60 <__multiply+0xa4> + 8d4c: 2005883a mov r2,r4 + 8d50: d8c00317 ldw r3,12(sp) + 8d54: 10000015 stw zero,0(r2) + 8d58: 10800104 addi r2,r2,4 + 8d5c: 10fffc36 bltu r2,r3,8d50 <__multiply+0x94> + 8d60: 8c45883a add r2,r17,r17 + 8d64: 9487883a add r3,r18,r18 + 8d68: 9dc00504 addi r23,r19,20 + 8d6c: 1085883a add r2,r2,r2 + 8d70: 84000504 addi r16,r16,20 + 8d74: 18c7883a add r3,r3,r3 + 8d78: b885883a add r2,r23,r2 + 8d7c: dc000015 stw r16,0(sp) + 8d80: d8800215 stw r2,8(sp) + 8d84: 80f9883a add fp,r16,r3 + 8d88: b880432e bgeu r23,r2,8e98 <__multiply+0x1dc> + 8d8c: d9000115 stw r4,4(sp) + 8d90: b9000017 ldw r4,0(r23) + 8d94: 253fffcc andi r20,r4,65535 + 8d98: a0001a26 beq r20,zero,8e04 <__multiply+0x148> + 8d9c: dcc00017 ldw r19,0(sp) + 8da0: dc800117 ldw r18,4(sp) + 8da4: 002b883a mov r21,zero + 8da8: 9c400017 ldw r17,0(r19) + 8dac: 94000017 ldw r16,0(r18) + 8db0: a009883a mov r4,r20 + 8db4: 897fffcc andi r5,r17,65535 + 8db8: 0002c240 call 2c24 <__mulsi3> + 8dbc: 880ad43a srli r5,r17,16 + 8dc0: 80ffffcc andi r3,r16,65535 + 8dc4: a8c7883a add r3,r21,r3 + 8dc8: a009883a mov r4,r20 + 8dcc: 10e3883a add r17,r2,r3 + 8dd0: 8020d43a srli r16,r16,16 + 8dd4: 0002c240 call 2c24 <__mulsi3> + 8dd8: 8806d43a srli r3,r17,16 + 8ddc: 1405883a add r2,r2,r16 + 8de0: 9cc00104 addi r19,r19,4 + 8de4: 1887883a add r3,r3,r2 + 8de8: 90c0008d sth r3,2(r18) + 8dec: 9440000d sth r17,0(r18) + 8df0: 182ad43a srli r21,r3,16 + 8df4: 94800104 addi r18,r18,4 + 8df8: 9f3feb36 bltu r19,fp,8da8 <__multiply+0xec> + 8dfc: 95400015 stw r21,0(r18) + 8e00: b9000017 ldw r4,0(r23) + 8e04: 202ad43a srli r21,r4,16 + 8e08: a8001c26 beq r21,zero,8e7c <__multiply+0x1c0> + 8e0c: d9000117 ldw r4,4(sp) + 8e10: dd000017 ldw r20,0(sp) + 8e14: 002d883a mov r22,zero + 8e18: 24c00017 ldw r19,0(r4) + 8e1c: 2025883a mov r18,r4 + 8e20: 9823883a mov r17,r19 + 8e24: a4000017 ldw r16,0(r20) + 8e28: a809883a mov r4,r21 + 8e2c: a5000104 addi r20,r20,4 + 8e30: 817fffcc andi r5,r16,65535 + 8e34: 0002c240 call 2c24 <__mulsi3> + 8e38: 8806d43a srli r3,r17,16 + 8e3c: 800ad43a srli r5,r16,16 + 8e40: 94c0000d sth r19,0(r18) + 8e44: b0c7883a add r3,r22,r3 + 8e48: 10e1883a add r16,r2,r3 + 8e4c: 9400008d sth r16,2(r18) + 8e50: a809883a mov r4,r21 + 8e54: 94800104 addi r18,r18,4 + 8e58: 0002c240 call 2c24 <__mulsi3> + 8e5c: 94400017 ldw r17,0(r18) + 8e60: 8020d43a srli r16,r16,16 + 8e64: 88ffffcc andi r3,r17,65535 + 8e68: 10c5883a add r2,r2,r3 + 8e6c: 80a7883a add r19,r16,r2 + 8e70: 982cd43a srli r22,r19,16 + 8e74: a73feb36 bltu r20,fp,8e24 <__multiply+0x168> + 8e78: 94c00015 stw r19,0(r18) + 8e7c: d8800217 ldw r2,8(sp) + 8e80: bdc00104 addi r23,r23,4 + 8e84: b880042e bgeu r23,r2,8e98 <__multiply+0x1dc> + 8e88: d8c00117 ldw r3,4(sp) + 8e8c: 18c00104 addi r3,r3,4 + 8e90: d8c00115 stw r3,4(sp) + 8e94: 003fbe06 br 8d90 <__multiply+0xd4> + 8e98: d9000417 ldw r4,16(sp) + 8e9c: 01000c0e bge zero,r4,8ed0 <__multiply+0x214> + 8ea0: d8c00317 ldw r3,12(sp) + 8ea4: 18bfff17 ldw r2,-4(r3) + 8ea8: 18ffff04 addi r3,r3,-4 + 8eac: 10000326 beq r2,zero,8ebc <__multiply+0x200> + 8eb0: 00000706 br 8ed0 <__multiply+0x214> + 8eb4: 18800017 ldw r2,0(r3) + 8eb8: 1000051e bne r2,zero,8ed0 <__multiply+0x214> + 8ebc: d9000417 ldw r4,16(sp) + 8ec0: 18ffff04 addi r3,r3,-4 + 8ec4: 213fffc4 addi r4,r4,-1 + 8ec8: d9000415 stw r4,16(sp) + 8ecc: 203ff91e bne r4,zero,8eb4 <__multiply+0x1f8> + 8ed0: d8800417 ldw r2,16(sp) + 8ed4: d8c00517 ldw r3,20(sp) + 8ed8: 18800415 stw r2,16(r3) + 8edc: 1805883a mov r2,r3 + 8ee0: dfc00f17 ldw ra,60(sp) + 8ee4: df000e17 ldw fp,56(sp) + 8ee8: ddc00d17 ldw r23,52(sp) + 8eec: dd800c17 ldw r22,48(sp) + 8ef0: dd400b17 ldw r21,44(sp) + 8ef4: dd000a17 ldw r20,40(sp) + 8ef8: dcc00917 ldw r19,36(sp) + 8efc: dc800817 ldw r18,32(sp) + 8f00: dc400717 ldw r17,28(sp) + 8f04: dc000617 ldw r16,24(sp) + 8f08: dec01004 addi sp,sp,64 + 8f0c: f800283a ret + +00008f10 <__i2b>: + 8f10: defffd04 addi sp,sp,-12 + 8f14: dc000015 stw r16,0(sp) + 8f18: 04000044 movi r16,1 + 8f1c: dc800115 stw r18,4(sp) + 8f20: 2825883a mov r18,r5 + 8f24: 800b883a mov r5,r16 + 8f28: dfc00215 stw ra,8(sp) + 8f2c: 00087ac0 call 87ac <_Balloc> + 8f30: 14000415 stw r16,16(r2) + 8f34: 14800515 stw r18,20(r2) + 8f38: dfc00217 ldw ra,8(sp) + 8f3c: dc800117 ldw r18,4(sp) + 8f40: dc000017 ldw r16,0(sp) + 8f44: dec00304 addi sp,sp,12 + 8f48: f800283a ret + +00008f4c <__multadd>: + 8f4c: defff604 addi sp,sp,-40 + 8f50: dd800615 stw r22,24(sp) + 8f54: 2d800417 ldw r22,16(r5) + 8f58: df000815 stw fp,32(sp) + 8f5c: ddc00715 stw r23,28(sp) + 8f60: dd400515 stw r21,20(sp) + 8f64: dd000415 stw r20,16(sp) + 8f68: dcc00315 stw r19,12(sp) + 8f6c: dc800215 stw r18,8(sp) + 8f70: dfc00915 stw ra,36(sp) + 8f74: dc400115 stw r17,4(sp) + 8f78: dc000015 stw r16,0(sp) + 8f7c: 282f883a mov r23,r5 + 8f80: 2039883a mov fp,r4 + 8f84: 302b883a mov r21,r6 + 8f88: 3829883a mov r20,r7 + 8f8c: 2c800504 addi r18,r5,20 + 8f90: 0027883a mov r19,zero + 8f94: 94400017 ldw r17,0(r18) + 8f98: a80b883a mov r5,r21 + 8f9c: 9cc00044 addi r19,r19,1 + 8fa0: 893fffcc andi r4,r17,65535 + 8fa4: 0002c240 call 2c24 <__mulsi3> + 8fa8: 8808d43a srli r4,r17,16 + 8fac: 1521883a add r16,r2,r20 + 8fb0: a80b883a mov r5,r21 + 8fb4: 0002c240 call 2c24 <__mulsi3> + 8fb8: 8008d43a srli r4,r16,16 + 8fbc: 843fffcc andi r16,r16,65535 + 8fc0: 1105883a add r2,r2,r4 + 8fc4: 1006943a slli r3,r2,16 + 8fc8: 1028d43a srli r20,r2,16 + 8fcc: 1c07883a add r3,r3,r16 + 8fd0: 90c00015 stw r3,0(r18) + 8fd4: 94800104 addi r18,r18,4 + 8fd8: 9dbfee16 blt r19,r22,8f94 <__multadd+0x48> + 8fdc: a0000826 beq r20,zero,9000 <__multadd+0xb4> + 8fe0: b8800217 ldw r2,8(r23) + 8fe4: b080130e bge r22,r2,9034 <__multadd+0xe8> + 8fe8: b585883a add r2,r22,r22 + 8fec: 1085883a add r2,r2,r2 + 8ff0: 15c5883a add r2,r2,r23 + 8ff4: b0c00044 addi r3,r22,1 + 8ff8: 15000515 stw r20,20(r2) + 8ffc: b8c00415 stw r3,16(r23) + 9000: b805883a mov r2,r23 + 9004: dfc00917 ldw ra,36(sp) + 9008: df000817 ldw fp,32(sp) + 900c: ddc00717 ldw r23,28(sp) + 9010: dd800617 ldw r22,24(sp) + 9014: dd400517 ldw r21,20(sp) + 9018: dd000417 ldw r20,16(sp) + 901c: dcc00317 ldw r19,12(sp) + 9020: dc800217 ldw r18,8(sp) + 9024: dc400117 ldw r17,4(sp) + 9028: dc000017 ldw r16,0(sp) + 902c: dec00a04 addi sp,sp,40 + 9030: f800283a ret + 9034: b9400117 ldw r5,4(r23) + 9038: e009883a mov r4,fp + 903c: 29400044 addi r5,r5,1 + 9040: 00087ac0 call 87ac <_Balloc> + 9044: b9800417 ldw r6,16(r23) + 9048: b9400304 addi r5,r23,12 + 904c: 11000304 addi r4,r2,12 + 9050: 318d883a add r6,r6,r6 + 9054: 318d883a add r6,r6,r6 + 9058: 31800204 addi r6,r6,8 + 905c: 1023883a mov r17,r2 + 9060: 00080140 call 8014 + 9064: b80b883a mov r5,r23 + 9068: e009883a mov r4,fp + 906c: 000822c0 call 822c <_Bfree> + 9070: 882f883a mov r23,r17 + 9074: 003fdc06 br 8fe8 <__multadd+0x9c> + +00009078 <__pow5mult>: + 9078: defffa04 addi sp,sp,-24 + 907c: 308000cc andi r2,r6,3 + 9080: dd000415 stw r20,16(sp) + 9084: dcc00315 stw r19,12(sp) + 9088: dc000015 stw r16,0(sp) + 908c: dfc00515 stw ra,20(sp) + 9090: dc800215 stw r18,8(sp) + 9094: dc400115 stw r17,4(sp) + 9098: 3021883a mov r16,r6 + 909c: 2027883a mov r19,r4 + 90a0: 2829883a mov r20,r5 + 90a4: 10002b1e bne r2,zero,9154 <__pow5mult+0xdc> + 90a8: 8025d0ba srai r18,r16,2 + 90ac: 90001b26 beq r18,zero,911c <__pow5mult+0xa4> + 90b0: 9c001217 ldw r16,72(r19) + 90b4: 8000081e bne r16,zero,90d8 <__pow5mult+0x60> + 90b8: 00003006 br 917c <__pow5mult+0x104> + 90bc: 800b883a mov r5,r16 + 90c0: 800d883a mov r6,r16 + 90c4: 9809883a mov r4,r19 + 90c8: 90001426 beq r18,zero,911c <__pow5mult+0xa4> + 90cc: 80800017 ldw r2,0(r16) + 90d0: 10001b26 beq r2,zero,9140 <__pow5mult+0xc8> + 90d4: 1021883a mov r16,r2 + 90d8: 9080004c andi r2,r18,1 + 90dc: 1005003a cmpeq r2,r2,zero + 90e0: 9025d07a srai r18,r18,1 + 90e4: 800d883a mov r6,r16 + 90e8: 9809883a mov r4,r19 + 90ec: a00b883a mov r5,r20 + 90f0: 103ff21e bne r2,zero,90bc <__pow5mult+0x44> + 90f4: 0008cbc0 call 8cbc <__multiply> + 90f8: a00b883a mov r5,r20 + 90fc: 9809883a mov r4,r19 + 9100: 1023883a mov r17,r2 + 9104: 000822c0 call 822c <_Bfree> + 9108: 8829883a mov r20,r17 + 910c: 800b883a mov r5,r16 + 9110: 800d883a mov r6,r16 + 9114: 9809883a mov r4,r19 + 9118: 903fec1e bne r18,zero,90cc <__pow5mult+0x54> + 911c: a005883a mov r2,r20 + 9120: dfc00517 ldw ra,20(sp) + 9124: dd000417 ldw r20,16(sp) + 9128: dcc00317 ldw r19,12(sp) + 912c: dc800217 ldw r18,8(sp) + 9130: dc400117 ldw r17,4(sp) + 9134: dc000017 ldw r16,0(sp) + 9138: dec00604 addi sp,sp,24 + 913c: f800283a ret + 9140: 0008cbc0 call 8cbc <__multiply> + 9144: 80800015 stw r2,0(r16) + 9148: 1021883a mov r16,r2 + 914c: 10000015 stw zero,0(r2) + 9150: 003fe106 br 90d8 <__pow5mult+0x60> + 9154: 1085883a add r2,r2,r2 + 9158: 00c00074 movhi r3,1 + 915c: 18c15504 addi r3,r3,1364 + 9160: 1085883a add r2,r2,r2 + 9164: 10c5883a add r2,r2,r3 + 9168: 11bfff17 ldw r6,-4(r2) + 916c: 000f883a mov r7,zero + 9170: 0008f4c0 call 8f4c <__multadd> + 9174: 1029883a mov r20,r2 + 9178: 003fcb06 br 90a8 <__pow5mult+0x30> + 917c: 9809883a mov r4,r19 + 9180: 01409c44 movi r5,625 + 9184: 0008f100 call 8f10 <__i2b> + 9188: 98801215 stw r2,72(r19) + 918c: 1021883a mov r16,r2 + 9190: 10000015 stw zero,0(r2) + 9194: 003fd006 br 90d8 <__pow5mult+0x60> + +00009198 <__s2b>: + 9198: defff904 addi sp,sp,-28 + 919c: dcc00315 stw r19,12(sp) + 91a0: dc800215 stw r18,8(sp) + 91a4: 2827883a mov r19,r5 + 91a8: 2025883a mov r18,r4 + 91ac: 01400244 movi r5,9 + 91b0: 39000204 addi r4,r7,8 + 91b4: dd000415 stw r20,16(sp) + 91b8: dc400115 stw r17,4(sp) + 91bc: dfc00615 stw ra,24(sp) + 91c0: dd400515 stw r21,20(sp) + 91c4: dc000015 stw r16,0(sp) + 91c8: 3829883a mov r20,r7 + 91cc: 3023883a mov r17,r6 + 91d0: 0002b540 call 2b54 <__divsi3> + 91d4: 00c00044 movi r3,1 + 91d8: 1880350e bge r3,r2,92b0 <__s2b+0x118> + 91dc: 000b883a mov r5,zero + 91e0: 18c7883a add r3,r3,r3 + 91e4: 29400044 addi r5,r5,1 + 91e8: 18bffd16 blt r3,r2,91e0 <__s2b+0x48> + 91ec: 9009883a mov r4,r18 + 91f0: 00087ac0 call 87ac <_Balloc> + 91f4: 1011883a mov r8,r2 + 91f8: d8800717 ldw r2,28(sp) + 91fc: 00c00044 movi r3,1 + 9200: 01800244 movi r6,9 + 9204: 40800515 stw r2,20(r8) + 9208: 40c00415 stw r3,16(r8) + 920c: 3440260e bge r6,r17,92a8 <__s2b+0x110> + 9210: 3021883a mov r16,r6 + 9214: 99ab883a add r21,r19,r6 + 9218: 9c05883a add r2,r19,r16 + 921c: 11c00007 ldb r7,0(r2) + 9220: 400b883a mov r5,r8 + 9224: 9009883a mov r4,r18 + 9228: 39fff404 addi r7,r7,-48 + 922c: 01800284 movi r6,10 + 9230: 0008f4c0 call 8f4c <__multadd> + 9234: 84000044 addi r16,r16,1 + 9238: 1011883a mov r8,r2 + 923c: 8c3ff61e bne r17,r16,9218 <__s2b+0x80> + 9240: ac45883a add r2,r21,r17 + 9244: 117ffe04 addi r5,r2,-8 + 9248: 880d883a mov r6,r17 + 924c: 35000c0e bge r6,r20,9280 <__s2b+0xe8> + 9250: a185c83a sub r2,r20,r6 + 9254: 2821883a mov r16,r5 + 9258: 28a3883a add r17,r5,r2 + 925c: 81c00007 ldb r7,0(r16) + 9260: 400b883a mov r5,r8 + 9264: 9009883a mov r4,r18 + 9268: 39fff404 addi r7,r7,-48 + 926c: 01800284 movi r6,10 + 9270: 0008f4c0 call 8f4c <__multadd> + 9274: 84000044 addi r16,r16,1 + 9278: 1011883a mov r8,r2 + 927c: 847ff71e bne r16,r17,925c <__s2b+0xc4> + 9280: 4005883a mov r2,r8 + 9284: dfc00617 ldw ra,24(sp) + 9288: dd400517 ldw r21,20(sp) + 928c: dd000417 ldw r20,16(sp) + 9290: dcc00317 ldw r19,12(sp) + 9294: dc800217 ldw r18,8(sp) + 9298: dc400117 ldw r17,4(sp) + 929c: dc000017 ldw r16,0(sp) + 92a0: dec00704 addi sp,sp,28 + 92a4: f800283a ret + 92a8: 99400284 addi r5,r19,10 + 92ac: 003fe706 br 924c <__s2b+0xb4> + 92b0: 000b883a mov r5,zero + 92b4: 003fcd06 br 91ec <__s2b+0x54> + +000092b8 <_realloc_r>: + 92b8: defff404 addi sp,sp,-48 + 92bc: dd800815 stw r22,32(sp) + 92c0: dc800415 stw r18,16(sp) + 92c4: dc400315 stw r17,12(sp) + 92c8: dfc00b15 stw ra,44(sp) + 92cc: df000a15 stw fp,40(sp) + 92d0: ddc00915 stw r23,36(sp) + 92d4: dd400715 stw r21,28(sp) + 92d8: dd000615 stw r20,24(sp) + 92dc: dcc00515 stw r19,20(sp) + 92e0: dc000215 stw r16,8(sp) + 92e4: 2825883a mov r18,r5 + 92e8: 3023883a mov r17,r6 + 92ec: 202d883a mov r22,r4 + 92f0: 2800c926 beq r5,zero,9618 <_realloc_r+0x360> + 92f4: 000cb800 call cb80 <__malloc_lock> + 92f8: 943ffe04 addi r16,r18,-8 + 92fc: 88c002c4 addi r3,r17,11 + 9300: 00800584 movi r2,22 + 9304: 82000117 ldw r8,4(r16) + 9308: 10c01b2e bgeu r2,r3,9378 <_realloc_r+0xc0> + 930c: 00bffe04 movi r2,-8 + 9310: 188e703a and r7,r3,r2 + 9314: 3839883a mov fp,r7 + 9318: 38001a16 blt r7,zero,9384 <_realloc_r+0xcc> + 931c: e4401936 bltu fp,r17,9384 <_realloc_r+0xcc> + 9320: 013fff04 movi r4,-4 + 9324: 4126703a and r19,r8,r4 + 9328: 99c02616 blt r19,r7,93c4 <_realloc_r+0x10c> + 932c: 802b883a mov r21,r16 + 9330: 9829883a mov r20,r19 + 9334: 84000204 addi r16,r16,8 + 9338: a80f883a mov r7,r21 + 933c: a70dc83a sub r6,r20,fp + 9340: 008003c4 movi r2,15 + 9344: 1180c136 bltu r2,r6,964c <_realloc_r+0x394> + 9348: 38800117 ldw r2,4(r7) + 934c: a549883a add r4,r20,r21 + 9350: 1080004c andi r2,r2,1 + 9354: a084b03a or r2,r20,r2 + 9358: 38800115 stw r2,4(r7) + 935c: 20c00117 ldw r3,4(r4) + 9360: 18c00054 ori r3,r3,1 + 9364: 20c00115 stw r3,4(r4) + 9368: b009883a mov r4,r22 + 936c: 000cba00 call cba0 <__malloc_unlock> + 9370: 8023883a mov r17,r16 + 9374: 00000606 br 9390 <_realloc_r+0xd8> + 9378: 01c00404 movi r7,16 + 937c: 3839883a mov fp,r7 + 9380: e47fe72e bgeu fp,r17,9320 <_realloc_r+0x68> + 9384: 00800304 movi r2,12 + 9388: 0023883a mov r17,zero + 938c: b0800015 stw r2,0(r22) + 9390: 8805883a mov r2,r17 + 9394: dfc00b17 ldw ra,44(sp) + 9398: df000a17 ldw fp,40(sp) + 939c: ddc00917 ldw r23,36(sp) + 93a0: dd800817 ldw r22,32(sp) + 93a4: dd400717 ldw r21,28(sp) + 93a8: dd000617 ldw r20,24(sp) + 93ac: dcc00517 ldw r19,20(sp) + 93b0: dc800417 ldw r18,16(sp) + 93b4: dc400317 ldw r17,12(sp) + 93b8: dc000217 ldw r16,8(sp) + 93bc: dec00c04 addi sp,sp,48 + 93c0: f800283a ret + 93c4: 00800074 movhi r2,1 + 93c8: 1082b004 addi r2,r2,2752 + 93cc: 12400217 ldw r9,8(r2) + 93d0: 84cd883a add r6,r16,r19 + 93d4: 802b883a mov r21,r16 + 93d8: 3240b926 beq r6,r9,96c0 <_realloc_r+0x408> + 93dc: 31400117 ldw r5,4(r6) + 93e0: 00bfff84 movi r2,-2 + 93e4: 2884703a and r2,r5,r2 + 93e8: 1185883a add r2,r2,r6 + 93ec: 10c00117 ldw r3,4(r2) + 93f0: 18c0004c andi r3,r3,1 + 93f4: 1807003a cmpeq r3,r3,zero + 93f8: 1800a326 beq r3,zero,9688 <_realloc_r+0x3d0> + 93fc: 2908703a and r4,r5,r4 + 9400: 9929883a add r20,r19,r4 + 9404: a1c0a30e bge r20,r7,9694 <_realloc_r+0x3dc> + 9408: 4080004c andi r2,r8,1 + 940c: 1000551e bne r2,zero,9564 <_realloc_r+0x2ac> + 9410: 80800017 ldw r2,0(r16) + 9414: 80afc83a sub r23,r16,r2 + 9418: b8c00117 ldw r3,4(r23) + 941c: 00bfff04 movi r2,-4 + 9420: 1884703a and r2,r3,r2 + 9424: 30002e26 beq r6,zero,94e0 <_realloc_r+0x228> + 9428: 3240b926 beq r6,r9,9710 <_realloc_r+0x458> + 942c: 98a9883a add r20,r19,r2 + 9430: 2509883a add r4,r4,r20 + 9434: d9000015 stw r4,0(sp) + 9438: 21c02a16 blt r4,r7,94e4 <_realloc_r+0x22c> + 943c: 30800317 ldw r2,12(r6) + 9440: 30c00217 ldw r3,8(r6) + 9444: 01400904 movi r5,36 + 9448: 99bfff04 addi r6,r19,-4 + 944c: 18800315 stw r2,12(r3) + 9450: 10c00215 stw r3,8(r2) + 9454: b9000317 ldw r4,12(r23) + 9458: b8800217 ldw r2,8(r23) + 945c: b82b883a mov r21,r23 + 9460: bc000204 addi r16,r23,8 + 9464: 20800215 stw r2,8(r4) + 9468: 11000315 stw r4,12(r2) + 946c: 2980e436 bltu r5,r6,9800 <_realloc_r+0x548> + 9470: 008004c4 movi r2,19 + 9474: 9009883a mov r4,r18 + 9478: 8011883a mov r8,r16 + 947c: 11800f2e bgeu r2,r6,94bc <_realloc_r+0x204> + 9480: 90800017 ldw r2,0(r18) + 9484: ba000404 addi r8,r23,16 + 9488: 91000204 addi r4,r18,8 + 948c: b8800215 stw r2,8(r23) + 9490: 90c00117 ldw r3,4(r18) + 9494: 008006c4 movi r2,27 + 9498: b8c00315 stw r3,12(r23) + 949c: 1180072e bgeu r2,r6,94bc <_realloc_r+0x204> + 94a0: 90c00217 ldw r3,8(r18) + 94a4: ba000604 addi r8,r23,24 + 94a8: 91000404 addi r4,r18,16 + 94ac: b8c00415 stw r3,16(r23) + 94b0: 90800317 ldw r2,12(r18) + 94b4: b8800515 stw r2,20(r23) + 94b8: 3140e726 beq r6,r5,9858 <_realloc_r+0x5a0> + 94bc: 20800017 ldw r2,0(r4) + 94c0: dd000017 ldw r20,0(sp) + 94c4: b80f883a mov r7,r23 + 94c8: 40800015 stw r2,0(r8) + 94cc: 20c00117 ldw r3,4(r4) + 94d0: 40c00115 stw r3,4(r8) + 94d4: 20800217 ldw r2,8(r4) + 94d8: 40800215 stw r2,8(r8) + 94dc: 003f9706 br 933c <_realloc_r+0x84> + 94e0: 98a9883a add r20,r19,r2 + 94e4: a1c01f16 blt r20,r7,9564 <_realloc_r+0x2ac> + 94e8: b8c00317 ldw r3,12(r23) + 94ec: b8800217 ldw r2,8(r23) + 94f0: 99bfff04 addi r6,r19,-4 + 94f4: 01400904 movi r5,36 + 94f8: b82b883a mov r21,r23 + 94fc: 18800215 stw r2,8(r3) + 9500: 10c00315 stw r3,12(r2) + 9504: bc000204 addi r16,r23,8 + 9508: 2980c336 bltu r5,r6,9818 <_realloc_r+0x560> + 950c: 008004c4 movi r2,19 + 9510: 9009883a mov r4,r18 + 9514: 8011883a mov r8,r16 + 9518: 11800f2e bgeu r2,r6,9558 <_realloc_r+0x2a0> + 951c: 90800017 ldw r2,0(r18) + 9520: ba000404 addi r8,r23,16 + 9524: 91000204 addi r4,r18,8 + 9528: b8800215 stw r2,8(r23) + 952c: 90c00117 ldw r3,4(r18) + 9530: 008006c4 movi r2,27 + 9534: b8c00315 stw r3,12(r23) + 9538: 1180072e bgeu r2,r6,9558 <_realloc_r+0x2a0> + 953c: 90c00217 ldw r3,8(r18) + 9540: ba000604 addi r8,r23,24 + 9544: 91000404 addi r4,r18,16 + 9548: b8c00415 stw r3,16(r23) + 954c: 90800317 ldw r2,12(r18) + 9550: b8800515 stw r2,20(r23) + 9554: 3140c726 beq r6,r5,9874 <_realloc_r+0x5bc> + 9558: 20800017 ldw r2,0(r4) + 955c: b80f883a mov r7,r23 + 9560: 003fd906 br 94c8 <_realloc_r+0x210> + 9564: 880b883a mov r5,r17 + 9568: b009883a mov r4,r22 + 956c: 00077f00 call 77f0 <_malloc_r> + 9570: 1023883a mov r17,r2 + 9574: 10002526 beq r2,zero,960c <_realloc_r+0x354> + 9578: 80800117 ldw r2,4(r16) + 957c: 00ffff84 movi r3,-2 + 9580: 893ffe04 addi r4,r17,-8 + 9584: 10c4703a and r2,r2,r3 + 9588: 8085883a add r2,r16,r2 + 958c: 20809526 beq r4,r2,97e4 <_realloc_r+0x52c> + 9590: 99bfff04 addi r6,r19,-4 + 9594: 01c00904 movi r7,36 + 9598: 39804536 bltu r7,r6,96b0 <_realloc_r+0x3f8> + 959c: 008004c4 movi r2,19 + 95a0: 9009883a mov r4,r18 + 95a4: 880b883a mov r5,r17 + 95a8: 11800f2e bgeu r2,r6,95e8 <_realloc_r+0x330> + 95ac: 90800017 ldw r2,0(r18) + 95b0: 89400204 addi r5,r17,8 + 95b4: 91000204 addi r4,r18,8 + 95b8: 88800015 stw r2,0(r17) + 95bc: 90c00117 ldw r3,4(r18) + 95c0: 008006c4 movi r2,27 + 95c4: 88c00115 stw r3,4(r17) + 95c8: 1180072e bgeu r2,r6,95e8 <_realloc_r+0x330> + 95cc: 90c00217 ldw r3,8(r18) + 95d0: 89400404 addi r5,r17,16 + 95d4: 91000404 addi r4,r18,16 + 95d8: 88c00215 stw r3,8(r17) + 95dc: 90800317 ldw r2,12(r18) + 95e0: 88800315 stw r2,12(r17) + 95e4: 31c09126 beq r6,r7,982c <_realloc_r+0x574> + 95e8: 20800017 ldw r2,0(r4) + 95ec: 28800015 stw r2,0(r5) + 95f0: 20c00117 ldw r3,4(r4) + 95f4: 28c00115 stw r3,4(r5) + 95f8: 20800217 ldw r2,8(r4) + 95fc: 28800215 stw r2,8(r5) + 9600: 900b883a mov r5,r18 + 9604: b009883a mov r4,r22 + 9608: 0006c680 call 6c68 <_free_r> + 960c: b009883a mov r4,r22 + 9610: 000cba00 call cba0 <__malloc_unlock> + 9614: 003f5e06 br 9390 <_realloc_r+0xd8> + 9618: 300b883a mov r5,r6 + 961c: dfc00b17 ldw ra,44(sp) + 9620: df000a17 ldw fp,40(sp) + 9624: ddc00917 ldw r23,36(sp) + 9628: dd800817 ldw r22,32(sp) + 962c: dd400717 ldw r21,28(sp) + 9630: dd000617 ldw r20,24(sp) + 9634: dcc00517 ldw r19,20(sp) + 9638: dc800417 ldw r18,16(sp) + 963c: dc400317 ldw r17,12(sp) + 9640: dc000217 ldw r16,8(sp) + 9644: dec00c04 addi sp,sp,48 + 9648: 00077f01 jmpi 77f0 <_malloc_r> + 964c: 38800117 ldw r2,4(r7) + 9650: e54b883a add r5,fp,r21 + 9654: 31000054 ori r4,r6,1 + 9658: 1080004c andi r2,r2,1 + 965c: 1704b03a or r2,r2,fp + 9660: 38800115 stw r2,4(r7) + 9664: 29000115 stw r4,4(r5) + 9668: 2987883a add r3,r5,r6 + 966c: 18800117 ldw r2,4(r3) + 9670: 29400204 addi r5,r5,8 + 9674: b009883a mov r4,r22 + 9678: 10800054 ori r2,r2,1 + 967c: 18800115 stw r2,4(r3) + 9680: 0006c680 call 6c68 <_free_r> + 9684: 003f3806 br 9368 <_realloc_r+0xb0> + 9688: 000d883a mov r6,zero + 968c: 0009883a mov r4,zero + 9690: 003f5d06 br 9408 <_realloc_r+0x150> + 9694: 30c00217 ldw r3,8(r6) + 9698: 30800317 ldw r2,12(r6) + 969c: 800f883a mov r7,r16 + 96a0: 84000204 addi r16,r16,8 + 96a4: 10c00215 stw r3,8(r2) + 96a8: 18800315 stw r2,12(r3) + 96ac: 003f2306 br 933c <_realloc_r+0x84> + 96b0: 8809883a mov r4,r17 + 96b4: 900b883a mov r5,r18 + 96b8: 00080b40 call 80b4 + 96bc: 003fd006 br 9600 <_realloc_r+0x348> + 96c0: 30800117 ldw r2,4(r6) + 96c4: e0c00404 addi r3,fp,16 + 96c8: 1108703a and r4,r2,r4 + 96cc: 9905883a add r2,r19,r4 + 96d0: 10ff4d16 blt r2,r3,9408 <_realloc_r+0x150> + 96d4: 1705c83a sub r2,r2,fp + 96d8: 870b883a add r5,r16,fp + 96dc: 10800054 ori r2,r2,1 + 96e0: 28800115 stw r2,4(r5) + 96e4: 80c00117 ldw r3,4(r16) + 96e8: 00800074 movhi r2,1 + 96ec: 1082b004 addi r2,r2,2752 + 96f0: b009883a mov r4,r22 + 96f4: 18c0004c andi r3,r3,1 + 96f8: e0c6b03a or r3,fp,r3 + 96fc: 11400215 stw r5,8(r2) + 9700: 80c00115 stw r3,4(r16) + 9704: 000cba00 call cba0 <__malloc_unlock> + 9708: 84400204 addi r17,r16,8 + 970c: 003f2006 br 9390 <_realloc_r+0xd8> + 9710: 98a9883a add r20,r19,r2 + 9714: 2509883a add r4,r4,r20 + 9718: e0800404 addi r2,fp,16 + 971c: d9000115 stw r4,4(sp) + 9720: 20bf7016 blt r4,r2,94e4 <_realloc_r+0x22c> + 9724: b8c00317 ldw r3,12(r23) + 9728: b8800217 ldw r2,8(r23) + 972c: 99bfff04 addi r6,r19,-4 + 9730: 01400904 movi r5,36 + 9734: 18800215 stw r2,8(r3) + 9738: 10c00315 stw r3,12(r2) + 973c: bc400204 addi r17,r23,8 + 9740: 29804136 bltu r5,r6,9848 <_realloc_r+0x590> + 9744: 008004c4 movi r2,19 + 9748: 9009883a mov r4,r18 + 974c: 880f883a mov r7,r17 + 9750: 11800f2e bgeu r2,r6,9790 <_realloc_r+0x4d8> + 9754: 90800017 ldw r2,0(r18) + 9758: b9c00404 addi r7,r23,16 + 975c: 91000204 addi r4,r18,8 + 9760: b8800215 stw r2,8(r23) + 9764: 90c00117 ldw r3,4(r18) + 9768: 008006c4 movi r2,27 + 976c: b8c00315 stw r3,12(r23) + 9770: 1180072e bgeu r2,r6,9790 <_realloc_r+0x4d8> + 9774: 90c00217 ldw r3,8(r18) + 9778: b9c00604 addi r7,r23,24 + 977c: 91000404 addi r4,r18,16 + 9780: b8c00415 stw r3,16(r23) + 9784: 90800317 ldw r2,12(r18) + 9788: b8800515 stw r2,20(r23) + 978c: 31404026 beq r6,r5,9890 <_realloc_r+0x5d8> + 9790: 20800017 ldw r2,0(r4) + 9794: 38800015 stw r2,0(r7) + 9798: 20c00117 ldw r3,4(r4) + 979c: 38c00115 stw r3,4(r7) + 97a0: 20800217 ldw r2,8(r4) + 97a4: 38800215 stw r2,8(r7) + 97a8: d8c00117 ldw r3,4(sp) + 97ac: bf0b883a add r5,r23,fp + 97b0: b009883a mov r4,r22 + 97b4: 1f05c83a sub r2,r3,fp + 97b8: 10800054 ori r2,r2,1 + 97bc: 28800115 stw r2,4(r5) + 97c0: b8c00117 ldw r3,4(r23) + 97c4: 00800074 movhi r2,1 + 97c8: 1082b004 addi r2,r2,2752 + 97cc: 11400215 stw r5,8(r2) + 97d0: 18c0004c andi r3,r3,1 + 97d4: e0c6b03a or r3,fp,r3 + 97d8: b8c00115 stw r3,4(r23) + 97dc: 000cba00 call cba0 <__malloc_unlock> + 97e0: 003eeb06 br 9390 <_realloc_r+0xd8> + 97e4: 20800117 ldw r2,4(r4) + 97e8: 00ffff04 movi r3,-4 + 97ec: 800f883a mov r7,r16 + 97f0: 10c4703a and r2,r2,r3 + 97f4: 98a9883a add r20,r19,r2 + 97f8: 84000204 addi r16,r16,8 + 97fc: 003ecf06 br 933c <_realloc_r+0x84> + 9800: 900b883a mov r5,r18 + 9804: 8009883a mov r4,r16 + 9808: 00080b40 call 80b4 + 980c: dd000017 ldw r20,0(sp) + 9810: b80f883a mov r7,r23 + 9814: 003ec906 br 933c <_realloc_r+0x84> + 9818: 900b883a mov r5,r18 + 981c: 8009883a mov r4,r16 + 9820: 00080b40 call 80b4 + 9824: b80f883a mov r7,r23 + 9828: 003ec406 br 933c <_realloc_r+0x84> + 982c: 90c00417 ldw r3,16(r18) + 9830: 89400604 addi r5,r17,24 + 9834: 91000604 addi r4,r18,24 + 9838: 88c00415 stw r3,16(r17) + 983c: 90800517 ldw r2,20(r18) + 9840: 88800515 stw r2,20(r17) + 9844: 003f6806 br 95e8 <_realloc_r+0x330> + 9848: 900b883a mov r5,r18 + 984c: 8809883a mov r4,r17 + 9850: 00080b40 call 80b4 + 9854: 003fd406 br 97a8 <_realloc_r+0x4f0> + 9858: 90c00417 ldw r3,16(r18) + 985c: 91000604 addi r4,r18,24 + 9860: ba000804 addi r8,r23,32 + 9864: b8c00615 stw r3,24(r23) + 9868: 90800517 ldw r2,20(r18) + 986c: b8800715 stw r2,28(r23) + 9870: 003f1206 br 94bc <_realloc_r+0x204> + 9874: 90c00417 ldw r3,16(r18) + 9878: 91000604 addi r4,r18,24 + 987c: ba000804 addi r8,r23,32 + 9880: b8c00615 stw r3,24(r23) + 9884: 90800517 ldw r2,20(r18) + 9888: b8800715 stw r2,28(r23) + 988c: 003f3206 br 9558 <_realloc_r+0x2a0> + 9890: 90c00417 ldw r3,16(r18) + 9894: 91000604 addi r4,r18,24 + 9898: b9c00804 addi r7,r23,32 + 989c: b8c00615 stw r3,24(r23) + 98a0: 90800517 ldw r2,20(r18) + 98a4: b8800715 stw r2,28(r23) + 98a8: 003fb906 br 9790 <_realloc_r+0x4d8> + +000098ac <__isinfd>: + 98ac: 200d883a mov r6,r4 + 98b0: 0109c83a sub r4,zero,r4 + 98b4: 2188b03a or r4,r4,r6 + 98b8: 2008d7fa srli r4,r4,31 + 98bc: 00a00034 movhi r2,32768 + 98c0: 10bfffc4 addi r2,r2,-1 + 98c4: 1144703a and r2,r2,r5 + 98c8: 2088b03a or r4,r4,r2 + 98cc: 009ffc34 movhi r2,32752 + 98d0: 1105c83a sub r2,r2,r4 + 98d4: 0087c83a sub r3,zero,r2 + 98d8: 10c4b03a or r2,r2,r3 + 98dc: 1004d7fa srli r2,r2,31 + 98e0: 00c00044 movi r3,1 + 98e4: 1885c83a sub r2,r3,r2 + 98e8: f800283a ret + +000098ec <__isnand>: + 98ec: 200d883a mov r6,r4 + 98f0: 0109c83a sub r4,zero,r4 + 98f4: 2188b03a or r4,r4,r6 + 98f8: 2008d7fa srli r4,r4,31 + 98fc: 00a00034 movhi r2,32768 + 9900: 10bfffc4 addi r2,r2,-1 + 9904: 1144703a and r2,r2,r5 + 9908: 2088b03a or r4,r4,r2 + 990c: 009ffc34 movhi r2,32752 + 9910: 1105c83a sub r2,r2,r4 + 9914: 1004d7fa srli r2,r2,31 + 9918: f800283a ret + +0000991c <_sbrk_r>: + 991c: defffd04 addi sp,sp,-12 + 9920: dc000015 stw r16,0(sp) + 9924: 04000074 movhi r16,1 + 9928: 840f7c04 addi r16,r16,15856 + 992c: dc400115 stw r17,4(sp) + 9930: 80000015 stw zero,0(r16) + 9934: 2023883a mov r17,r4 + 9938: 2809883a mov r4,r5 + 993c: dfc00215 stw ra,8(sp) + 9940: 000cdbc0 call cdbc + 9944: 1007883a mov r3,r2 + 9948: 00bfffc4 movi r2,-1 + 994c: 18800626 beq r3,r2,9968 <_sbrk_r+0x4c> + 9950: 1805883a mov r2,r3 + 9954: dfc00217 ldw ra,8(sp) + 9958: dc400117 ldw r17,4(sp) + 995c: dc000017 ldw r16,0(sp) + 9960: dec00304 addi sp,sp,12 + 9964: f800283a ret + 9968: 80800017 ldw r2,0(r16) + 996c: 103ff826 beq r2,zero,9950 <_sbrk_r+0x34> + 9970: 88800015 stw r2,0(r17) + 9974: 1805883a mov r2,r3 + 9978: dfc00217 ldw ra,8(sp) + 997c: dc400117 ldw r17,4(sp) + 9980: dc000017 ldw r16,0(sp) + 9984: dec00304 addi sp,sp,12 + 9988: f800283a ret + +0000998c <__sclose>: + 998c: 2940038f ldh r5,14(r5) + 9990: 0009cd41 jmpi 9cd4 <_close_r> + +00009994 <__sseek>: + 9994: defffe04 addi sp,sp,-8 + 9998: dc000015 stw r16,0(sp) + 999c: 2821883a mov r16,r5 + 99a0: 2940038f ldh r5,14(r5) + 99a4: dfc00115 stw ra,4(sp) + 99a8: 0009f4c0 call 9f4c <_lseek_r> + 99ac: 1007883a mov r3,r2 + 99b0: 00bfffc4 movi r2,-1 + 99b4: 18800926 beq r3,r2,99dc <__sseek+0x48> + 99b8: 8080030b ldhu r2,12(r16) + 99bc: 80c01415 stw r3,80(r16) + 99c0: 10840014 ori r2,r2,4096 + 99c4: 8080030d sth r2,12(r16) + 99c8: 1805883a mov r2,r3 + 99cc: dfc00117 ldw ra,4(sp) + 99d0: dc000017 ldw r16,0(sp) + 99d4: dec00204 addi sp,sp,8 + 99d8: f800283a ret + 99dc: 8080030b ldhu r2,12(r16) + 99e0: 10bbffcc andi r2,r2,61439 + 99e4: 8080030d sth r2,12(r16) + 99e8: 1805883a mov r2,r3 + 99ec: dfc00117 ldw ra,4(sp) + 99f0: dc000017 ldw r16,0(sp) + 99f4: dec00204 addi sp,sp,8 + 99f8: f800283a ret + +000099fc <__swrite>: + 99fc: 2880030b ldhu r2,12(r5) + 9a00: defffb04 addi sp,sp,-20 + 9a04: dcc00315 stw r19,12(sp) + 9a08: 1080400c andi r2,r2,256 + 9a0c: dc800215 stw r18,8(sp) + 9a10: dc400115 stw r17,4(sp) + 9a14: dc000015 stw r16,0(sp) + 9a18: 3027883a mov r19,r6 + 9a1c: 3825883a mov r18,r7 + 9a20: dfc00415 stw ra,16(sp) + 9a24: 2821883a mov r16,r5 + 9a28: 000d883a mov r6,zero + 9a2c: 01c00084 movi r7,2 + 9a30: 2023883a mov r17,r4 + 9a34: 10000226 beq r2,zero,9a40 <__swrite+0x44> + 9a38: 2940038f ldh r5,14(r5) + 9a3c: 0009f4c0 call 9f4c <_lseek_r> + 9a40: 8080030b ldhu r2,12(r16) + 9a44: 8140038f ldh r5,14(r16) + 9a48: 8809883a mov r4,r17 + 9a4c: 10bbffcc andi r2,r2,61439 + 9a50: 980d883a mov r6,r19 + 9a54: 900f883a mov r7,r18 + 9a58: 8080030d sth r2,12(r16) + 9a5c: dfc00417 ldw ra,16(sp) + 9a60: dcc00317 ldw r19,12(sp) + 9a64: dc800217 ldw r18,8(sp) + 9a68: dc400117 ldw r17,4(sp) + 9a6c: dc000017 ldw r16,0(sp) + 9a70: dec00504 addi sp,sp,20 + 9a74: 0009b941 jmpi 9b94 <_write_r> + +00009a78 <__sread>: + 9a78: defffe04 addi sp,sp,-8 + 9a7c: dc000015 stw r16,0(sp) + 9a80: 2821883a mov r16,r5 + 9a84: 2940038f ldh r5,14(r5) + 9a88: dfc00115 stw ra,4(sp) + 9a8c: 0009fc40 call 9fc4 <_read_r> + 9a90: 1007883a mov r3,r2 + 9a94: 10000816 blt r2,zero,9ab8 <__sread+0x40> + 9a98: 80801417 ldw r2,80(r16) + 9a9c: 10c5883a add r2,r2,r3 + 9aa0: 80801415 stw r2,80(r16) + 9aa4: 1805883a mov r2,r3 + 9aa8: dfc00117 ldw ra,4(sp) + 9aac: dc000017 ldw r16,0(sp) + 9ab0: dec00204 addi sp,sp,8 + 9ab4: f800283a ret + 9ab8: 8080030b ldhu r2,12(r16) + 9abc: 10bbffcc andi r2,r2,61439 + 9ac0: 8080030d sth r2,12(r16) + 9ac4: 1805883a mov r2,r3 + 9ac8: dfc00117 ldw ra,4(sp) + 9acc: dc000017 ldw r16,0(sp) + 9ad0: dec00204 addi sp,sp,8 + 9ad4: f800283a ret + +00009ad8 : + 9ad8: 2144b03a or r2,r4,r5 + 9adc: 108000cc andi r2,r2,3 + 9ae0: 10001d1e bne r2,zero,9b58 + 9ae4: 200f883a mov r7,r4 + 9ae8: 28800017 ldw r2,0(r5) + 9aec: 21000017 ldw r4,0(r4) + 9af0: 280d883a mov r6,r5 + 9af4: 2080161e bne r4,r2,9b50 + 9af8: 023fbff4 movhi r8,65279 + 9afc: 423fbfc4 addi r8,r8,-257 + 9b00: 2207883a add r3,r4,r8 + 9b04: 01602074 movhi r5,32897 + 9b08: 29602004 addi r5,r5,-32640 + 9b0c: 1946703a and r3,r3,r5 + 9b10: 0104303a nor r2,zero,r4 + 9b14: 10c4703a and r2,r2,r3 + 9b18: 10001c1e bne r2,zero,9b8c + 9b1c: 4013883a mov r9,r8 + 9b20: 2811883a mov r8,r5 + 9b24: 00000106 br 9b2c + 9b28: 1800181e bne r3,zero,9b8c + 9b2c: 39c00104 addi r7,r7,4 + 9b30: 39000017 ldw r4,0(r7) + 9b34: 31800104 addi r6,r6,4 + 9b38: 31400017 ldw r5,0(r6) + 9b3c: 2245883a add r2,r4,r9 + 9b40: 1204703a and r2,r2,r8 + 9b44: 0106303a nor r3,zero,r4 + 9b48: 1886703a and r3,r3,r2 + 9b4c: 217ff626 beq r4,r5,9b28 + 9b50: 3809883a mov r4,r7 + 9b54: 300b883a mov r5,r6 + 9b58: 20c00007 ldb r3,0(r4) + 9b5c: 1800051e bne r3,zero,9b74 + 9b60: 00000606 br 9b7c + 9b64: 21000044 addi r4,r4,1 + 9b68: 20c00007 ldb r3,0(r4) + 9b6c: 29400044 addi r5,r5,1 + 9b70: 18000226 beq r3,zero,9b7c + 9b74: 28800007 ldb r2,0(r5) + 9b78: 18bffa26 beq r3,r2,9b64 + 9b7c: 20c00003 ldbu r3,0(r4) + 9b80: 28800003 ldbu r2,0(r5) + 9b84: 1885c83a sub r2,r3,r2 + 9b88: f800283a ret + 9b8c: 0005883a mov r2,zero + 9b90: f800283a ret + +00009b94 <_write_r>: + 9b94: defffd04 addi sp,sp,-12 + 9b98: dc000015 stw r16,0(sp) + 9b9c: 04000074 movhi r16,1 + 9ba0: 840f7c04 addi r16,r16,15856 + 9ba4: dc400115 stw r17,4(sp) + 9ba8: 80000015 stw zero,0(r16) + 9bac: 2023883a mov r17,r4 + 9bb0: 2809883a mov r4,r5 + 9bb4: 300b883a mov r5,r6 + 9bb8: 380d883a mov r6,r7 + 9bbc: dfc00215 stw ra,8(sp) + 9bc0: 000cea80 call cea8 + 9bc4: 1007883a mov r3,r2 + 9bc8: 00bfffc4 movi r2,-1 + 9bcc: 18800626 beq r3,r2,9be8 <_write_r+0x54> + 9bd0: 1805883a mov r2,r3 + 9bd4: dfc00217 ldw ra,8(sp) + 9bd8: dc400117 ldw r17,4(sp) + 9bdc: dc000017 ldw r16,0(sp) + 9be0: dec00304 addi sp,sp,12 + 9be4: f800283a ret + 9be8: 80800017 ldw r2,0(r16) + 9bec: 103ff826 beq r2,zero,9bd0 <_write_r+0x3c> + 9bf0: 88800015 stw r2,0(r17) + 9bf4: 1805883a mov r2,r3 + 9bf8: dfc00217 ldw ra,8(sp) + 9bfc: dc400117 ldw r17,4(sp) + 9c00: dc000017 ldw r16,0(sp) + 9c04: dec00304 addi sp,sp,12 + 9c08: f800283a ret + +00009c0c <_calloc_r>: + 9c0c: defffe04 addi sp,sp,-8 + 9c10: dc400015 stw r17,0(sp) + 9c14: 2023883a mov r17,r4 + 9c18: 2809883a mov r4,r5 + 9c1c: 300b883a mov r5,r6 + 9c20: dfc00115 stw ra,4(sp) + 9c24: 0002c240 call 2c24 <__mulsi3> + 9c28: 100b883a mov r5,r2 + 9c2c: 8809883a mov r4,r17 + 9c30: 00077f00 call 77f0 <_malloc_r> + 9c34: 1023883a mov r17,r2 + 9c38: 01c00904 movi r7,36 + 9c3c: 10000d26 beq r2,zero,9c74 <_calloc_r+0x68> + 9c40: 10ffff17 ldw r3,-4(r2) + 9c44: 1009883a mov r4,r2 + 9c48: 00bfff04 movi r2,-4 + 9c4c: 1886703a and r3,r3,r2 + 9c50: 1887883a add r3,r3,r2 + 9c54: 180d883a mov r6,r3 + 9c58: 000b883a mov r5,zero + 9c5c: 38c01736 bltu r7,r3,9cbc <_calloc_r+0xb0> + 9c60: 008004c4 movi r2,19 + 9c64: 10c00836 bltu r2,r3,9c88 <_calloc_r+0x7c> + 9c68: 20000215 stw zero,8(r4) + 9c6c: 20000015 stw zero,0(r4) + 9c70: 20000115 stw zero,4(r4) + 9c74: 8805883a mov r2,r17 + 9c78: dfc00117 ldw ra,4(sp) + 9c7c: dc400017 ldw r17,0(sp) + 9c80: dec00204 addi sp,sp,8 + 9c84: f800283a ret + 9c88: 008006c4 movi r2,27 + 9c8c: 88000015 stw zero,0(r17) + 9c90: 88000115 stw zero,4(r17) + 9c94: 89000204 addi r4,r17,8 + 9c98: 10fff32e bgeu r2,r3,9c68 <_calloc_r+0x5c> + 9c9c: 88000215 stw zero,8(r17) + 9ca0: 88000315 stw zero,12(r17) + 9ca4: 89000404 addi r4,r17,16 + 9ca8: 19ffef1e bne r3,r7,9c68 <_calloc_r+0x5c> + 9cac: 89000604 addi r4,r17,24 + 9cb0: 88000415 stw zero,16(r17) + 9cb4: 88000515 stw zero,20(r17) + 9cb8: 003feb06 br 9c68 <_calloc_r+0x5c> + 9cbc: 00081940 call 8194 + 9cc0: 8805883a mov r2,r17 + 9cc4: dfc00117 ldw ra,4(sp) + 9cc8: dc400017 ldw r17,0(sp) + 9ccc: dec00204 addi sp,sp,8 + 9cd0: f800283a ret + +00009cd4 <_close_r>: + 9cd4: defffd04 addi sp,sp,-12 + 9cd8: dc000015 stw r16,0(sp) + 9cdc: 04000074 movhi r16,1 + 9ce0: 840f7c04 addi r16,r16,15856 + 9ce4: dc400115 stw r17,4(sp) + 9ce8: 80000015 stw zero,0(r16) + 9cec: 2023883a mov r17,r4 + 9cf0: 2809883a mov r4,r5 + 9cf4: dfc00215 stw ra,8(sp) + 9cf8: 000c4ec0 call c4ec + 9cfc: 1007883a mov r3,r2 + 9d00: 00bfffc4 movi r2,-1 + 9d04: 18800626 beq r3,r2,9d20 <_close_r+0x4c> + 9d08: 1805883a mov r2,r3 + 9d0c: dfc00217 ldw ra,8(sp) + 9d10: dc400117 ldw r17,4(sp) + 9d14: dc000017 ldw r16,0(sp) + 9d18: dec00304 addi sp,sp,12 + 9d1c: f800283a ret + 9d20: 80800017 ldw r2,0(r16) + 9d24: 103ff826 beq r2,zero,9d08 <_close_r+0x34> + 9d28: 88800015 stw r2,0(r17) + 9d2c: 1805883a mov r2,r3 + 9d30: dfc00217 ldw ra,8(sp) + 9d34: dc400117 ldw r17,4(sp) + 9d38: dc000017 ldw r16,0(sp) + 9d3c: dec00304 addi sp,sp,12 + 9d40: f800283a ret + +00009d44 <_fclose_r>: + 9d44: defffc04 addi sp,sp,-16 + 9d48: dc400115 stw r17,4(sp) + 9d4c: dc000015 stw r16,0(sp) + 9d50: dfc00315 stw ra,12(sp) + 9d54: dc800215 stw r18,8(sp) + 9d58: 2821883a mov r16,r5 + 9d5c: 2023883a mov r17,r4 + 9d60: 28002926 beq r5,zero,9e08 <_fclose_r+0xc4> + 9d64: 00068a00 call 68a0 <__sfp_lock_acquire> + 9d68: 88000226 beq r17,zero,9d74 <_fclose_r+0x30> + 9d6c: 88800e17 ldw r2,56(r17) + 9d70: 10002d26 beq r2,zero,9e28 <_fclose_r+0xe4> + 9d74: 8080030f ldh r2,12(r16) + 9d78: 10002226 beq r2,zero,9e04 <_fclose_r+0xc0> + 9d7c: 8809883a mov r4,r17 + 9d80: 800b883a mov r5,r16 + 9d84: 00066180 call 6618 <_fflush_r> + 9d88: 1025883a mov r18,r2 + 9d8c: 80800b17 ldw r2,44(r16) + 9d90: 10000426 beq r2,zero,9da4 <_fclose_r+0x60> + 9d94: 81400717 ldw r5,28(r16) + 9d98: 8809883a mov r4,r17 + 9d9c: 103ee83a callr r2 + 9da0: 10002a16 blt r2,zero,9e4c <_fclose_r+0x108> + 9da4: 8080030b ldhu r2,12(r16) + 9da8: 1080200c andi r2,r2,128 + 9dac: 1000231e bne r2,zero,9e3c <_fclose_r+0xf8> + 9db0: 81400c17 ldw r5,48(r16) + 9db4: 28000526 beq r5,zero,9dcc <_fclose_r+0x88> + 9db8: 80801004 addi r2,r16,64 + 9dbc: 28800226 beq r5,r2,9dc8 <_fclose_r+0x84> + 9dc0: 8809883a mov r4,r17 + 9dc4: 0006c680 call 6c68 <_free_r> + 9dc8: 80000c15 stw zero,48(r16) + 9dcc: 81401117 ldw r5,68(r16) + 9dd0: 28000326 beq r5,zero,9de0 <_fclose_r+0x9c> + 9dd4: 8809883a mov r4,r17 + 9dd8: 0006c680 call 6c68 <_free_r> + 9ddc: 80001115 stw zero,68(r16) + 9de0: 8000030d sth zero,12(r16) + 9de4: 00068a40 call 68a4 <__sfp_lock_release> + 9de8: 9005883a mov r2,r18 + 9dec: dfc00317 ldw ra,12(sp) + 9df0: dc800217 ldw r18,8(sp) + 9df4: dc400117 ldw r17,4(sp) + 9df8: dc000017 ldw r16,0(sp) + 9dfc: dec00404 addi sp,sp,16 + 9e00: f800283a ret + 9e04: 00068a40 call 68a4 <__sfp_lock_release> + 9e08: 0025883a mov r18,zero + 9e0c: 9005883a mov r2,r18 + 9e10: dfc00317 ldw ra,12(sp) + 9e14: dc800217 ldw r18,8(sp) + 9e18: dc400117 ldw r17,4(sp) + 9e1c: dc000017 ldw r16,0(sp) + 9e20: dec00404 addi sp,sp,16 + 9e24: f800283a ret + 9e28: 8809883a mov r4,r17 + 9e2c: 00068b00 call 68b0 <__sinit> + 9e30: 8080030f ldh r2,12(r16) + 9e34: 103fd11e bne r2,zero,9d7c <_fclose_r+0x38> + 9e38: 003ff206 br 9e04 <_fclose_r+0xc0> + 9e3c: 81400417 ldw r5,16(r16) + 9e40: 8809883a mov r4,r17 + 9e44: 0006c680 call 6c68 <_free_r> + 9e48: 003fd906 br 9db0 <_fclose_r+0x6c> + 9e4c: 04bfffc4 movi r18,-1 + 9e50: 003fd406 br 9da4 <_fclose_r+0x60> + +00009e54 : + 9e54: 00800074 movhi r2,1 + 9e58: 10887e04 addi r2,r2,8696 + 9e5c: 200b883a mov r5,r4 + 9e60: 11000017 ldw r4,0(r2) + 9e64: 0009d441 jmpi 9d44 <_fclose_r> + +00009e68 <_fstat_r>: + 9e68: defffd04 addi sp,sp,-12 + 9e6c: dc000015 stw r16,0(sp) + 9e70: 04000074 movhi r16,1 + 9e74: 840f7c04 addi r16,r16,15856 + 9e78: dc400115 stw r17,4(sp) + 9e7c: 80000015 stw zero,0(r16) + 9e80: 2023883a mov r17,r4 + 9e84: 2809883a mov r4,r5 + 9e88: 300b883a mov r5,r6 + 9e8c: dfc00215 stw ra,8(sp) + 9e90: 000c6780 call c678 + 9e94: 1007883a mov r3,r2 + 9e98: 00bfffc4 movi r2,-1 + 9e9c: 18800626 beq r3,r2,9eb8 <_fstat_r+0x50> + 9ea0: 1805883a mov r2,r3 + 9ea4: dfc00217 ldw ra,8(sp) + 9ea8: dc400117 ldw r17,4(sp) + 9eac: dc000017 ldw r16,0(sp) + 9eb0: dec00304 addi sp,sp,12 + 9eb4: f800283a ret + 9eb8: 80800017 ldw r2,0(r16) + 9ebc: 103ff826 beq r2,zero,9ea0 <_fstat_r+0x38> + 9ec0: 88800015 stw r2,0(r17) + 9ec4: 1805883a mov r2,r3 + 9ec8: dfc00217 ldw ra,8(sp) + 9ecc: dc400117 ldw r17,4(sp) + 9ed0: dc000017 ldw r16,0(sp) + 9ed4: dec00304 addi sp,sp,12 + 9ed8: f800283a ret + +00009edc <_isatty_r>: + 9edc: defffd04 addi sp,sp,-12 + 9ee0: dc000015 stw r16,0(sp) + 9ee4: 04000074 movhi r16,1 + 9ee8: 840f7c04 addi r16,r16,15856 + 9eec: dc400115 stw r17,4(sp) + 9ef0: 80000015 stw zero,0(r16) + 9ef4: 2023883a mov r17,r4 + 9ef8: 2809883a mov r4,r5 + 9efc: dfc00215 stw ra,8(sp) + 9f00: 000c7b00 call c7b0 + 9f04: 1007883a mov r3,r2 + 9f08: 00bfffc4 movi r2,-1 + 9f0c: 18800626 beq r3,r2,9f28 <_isatty_r+0x4c> + 9f10: 1805883a mov r2,r3 + 9f14: dfc00217 ldw ra,8(sp) + 9f18: dc400117 ldw r17,4(sp) + 9f1c: dc000017 ldw r16,0(sp) + 9f20: dec00304 addi sp,sp,12 + 9f24: f800283a ret + 9f28: 80800017 ldw r2,0(r16) + 9f2c: 103ff826 beq r2,zero,9f10 <_isatty_r+0x34> + 9f30: 88800015 stw r2,0(r17) + 9f34: 1805883a mov r2,r3 + 9f38: dfc00217 ldw ra,8(sp) + 9f3c: dc400117 ldw r17,4(sp) + 9f40: dc000017 ldw r16,0(sp) + 9f44: dec00304 addi sp,sp,12 + 9f48: f800283a ret + +00009f4c <_lseek_r>: + 9f4c: defffd04 addi sp,sp,-12 + 9f50: dc000015 stw r16,0(sp) + 9f54: 04000074 movhi r16,1 + 9f58: 840f7c04 addi r16,r16,15856 + 9f5c: dc400115 stw r17,4(sp) + 9f60: 80000015 stw zero,0(r16) + 9f64: 2023883a mov r17,r4 + 9f68: 2809883a mov r4,r5 + 9f6c: 300b883a mov r5,r6 + 9f70: 380d883a mov r6,r7 + 9f74: dfc00215 stw ra,8(sp) + 9f78: 000c9c00 call c9c0 + 9f7c: 1007883a mov r3,r2 + 9f80: 00bfffc4 movi r2,-1 + 9f84: 18800626 beq r3,r2,9fa0 <_lseek_r+0x54> + 9f88: 1805883a mov r2,r3 + 9f8c: dfc00217 ldw ra,8(sp) + 9f90: dc400117 ldw r17,4(sp) + 9f94: dc000017 ldw r16,0(sp) + 9f98: dec00304 addi sp,sp,12 + 9f9c: f800283a ret + 9fa0: 80800017 ldw r2,0(r16) + 9fa4: 103ff826 beq r2,zero,9f88 <_lseek_r+0x3c> + 9fa8: 88800015 stw r2,0(r17) + 9fac: 1805883a mov r2,r3 + 9fb0: dfc00217 ldw ra,8(sp) + 9fb4: dc400117 ldw r17,4(sp) + 9fb8: dc000017 ldw r16,0(sp) + 9fbc: dec00304 addi sp,sp,12 + 9fc0: f800283a ret + +00009fc4 <_read_r>: + 9fc4: defffd04 addi sp,sp,-12 + 9fc8: dc000015 stw r16,0(sp) + 9fcc: 04000074 movhi r16,1 + 9fd0: 840f7c04 addi r16,r16,15856 + 9fd4: dc400115 stw r17,4(sp) + 9fd8: 80000015 stw zero,0(r16) + 9fdc: 2023883a mov r17,r4 + 9fe0: 2809883a mov r4,r5 + 9fe4: 300b883a mov r5,r6 + 9fe8: 380d883a mov r6,r7 + 9fec: dfc00215 stw ra,8(sp) + 9ff0: 000cbc00 call cbc0 + 9ff4: 1007883a mov r3,r2 + 9ff8: 00bfffc4 movi r2,-1 + 9ffc: 18800626 beq r3,r2,a018 <_read_r+0x54> + a000: 1805883a mov r2,r3 + a004: dfc00217 ldw ra,8(sp) + a008: dc400117 ldw r17,4(sp) + a00c: dc000017 ldw r16,0(sp) + a010: dec00304 addi sp,sp,12 + a014: f800283a ret + a018: 80800017 ldw r2,0(r16) + a01c: 103ff826 beq r2,zero,a000 <_read_r+0x3c> + a020: 88800015 stw r2,0(r17) + a024: 1805883a mov r2,r3 + a028: dfc00217 ldw ra,8(sp) + a02c: dc400117 ldw r17,4(sp) + a030: dc000017 ldw r16,0(sp) + a034: dec00304 addi sp,sp,12 + a038: f800283a ret + +0000a03c <__udivdi3>: + a03c: defff104 addi sp,sp,-60 + a040: 0015883a mov r10,zero + a044: 2005883a mov r2,r4 + a048: 3011883a mov r8,r6 + a04c: df000d15 stw fp,52(sp) + a050: dd400a15 stw r21,40(sp) + a054: dcc00815 stw r19,32(sp) + a058: dfc00e15 stw ra,56(sp) + a05c: ddc00c15 stw r23,48(sp) + a060: dd800b15 stw r22,44(sp) + a064: dd000915 stw r20,36(sp) + a068: dc800715 stw r18,28(sp) + a06c: dc400615 stw r17,24(sp) + a070: dc000515 stw r16,20(sp) + a074: da800315 stw r10,12(sp) + a078: 4027883a mov r19,r8 + a07c: 1039883a mov fp,r2 + a080: 282b883a mov r21,r5 + a084: da800415 stw r10,16(sp) + a088: 3800401e bne r7,zero,a18c <__udivdi3+0x150> + a08c: 2a006536 bltu r5,r8,a224 <__udivdi3+0x1e8> + a090: 4000b526 beq r8,zero,a368 <__udivdi3+0x32c> + a094: 00bfffd4 movui r2,65535 + a098: 14c0ad36 bltu r2,r19,a350 <__udivdi3+0x314> + a09c: 00803fc4 movi r2,255 + a0a0: 14c15e36 bltu r2,r19,a61c <__udivdi3+0x5e0> + a0a4: 000b883a mov r5,zero + a0a8: 0005883a mov r2,zero + a0ac: 9884d83a srl r2,r19,r2 + a0b0: 01000074 movhi r4,1 + a0b4: 21015d04 addi r4,r4,1396 + a0b8: 01800804 movi r6,32 + a0bc: 1105883a add r2,r2,r4 + a0c0: 10c00003 ldbu r3,0(r2) + a0c4: 28c7883a add r3,r5,r3 + a0c8: 30e9c83a sub r20,r6,r3 + a0cc: a0010a1e bne r20,zero,a4f8 <__udivdi3+0x4bc> + a0d0: 982ed43a srli r23,r19,16 + a0d4: acebc83a sub r21,r21,r19 + a0d8: 9dbfffcc andi r22,r19,65535 + a0dc: 05000044 movi r20,1 + a0e0: a809883a mov r4,r21 + a0e4: b80b883a mov r5,r23 + a0e8: 0002c140 call 2c14 <__udivsi3> + a0ec: 100b883a mov r5,r2 + a0f0: b009883a mov r4,r22 + a0f4: 1021883a mov r16,r2 + a0f8: 0002c240 call 2c24 <__mulsi3> + a0fc: a809883a mov r4,r21 + a100: b80b883a mov r5,r23 + a104: 1023883a mov r17,r2 + a108: 0002c1c0 call 2c1c <__umodsi3> + a10c: 1004943a slli r2,r2,16 + a110: e006d43a srli r3,fp,16 + a114: 10c4b03a or r2,r2,r3 + a118: 1440042e bgeu r2,r17,a12c <__udivdi3+0xf0> + a11c: 14c5883a add r2,r2,r19 + a120: 843fffc4 addi r16,r16,-1 + a124: 14c00136 bltu r2,r19,a12c <__udivdi3+0xf0> + a128: 14415c36 bltu r2,r17,a69c <__udivdi3+0x660> + a12c: 1463c83a sub r17,r2,r17 + a130: 8809883a mov r4,r17 + a134: b80b883a mov r5,r23 + a138: 0002c140 call 2c14 <__udivsi3> + a13c: 100b883a mov r5,r2 + a140: b009883a mov r4,r22 + a144: 102b883a mov r21,r2 + a148: 0002c240 call 2c24 <__mulsi3> + a14c: 8809883a mov r4,r17 + a150: b80b883a mov r5,r23 + a154: 1025883a mov r18,r2 + a158: 0002c1c0 call 2c1c <__umodsi3> + a15c: 1004943a slli r2,r2,16 + a160: e0ffffcc andi r3,fp,65535 + a164: 10c4b03a or r2,r2,r3 + a168: 1480042e bgeu r2,r18,a17c <__udivdi3+0x140> + a16c: 9885883a add r2,r19,r2 + a170: ad7fffc4 addi r21,r21,-1 + a174: 14c00136 bltu r2,r19,a17c <__udivdi3+0x140> + a178: 14813c36 bltu r2,r18,a66c <__udivdi3+0x630> + a17c: 8004943a slli r2,r16,16 + a180: a009883a mov r4,r20 + a184: a884b03a or r2,r21,r2 + a188: 00001506 br a1e0 <__udivdi3+0x1a4> + a18c: 380d883a mov r6,r7 + a190: 29c06c36 bltu r5,r7,a344 <__udivdi3+0x308> + a194: 00bfffd4 movui r2,65535 + a198: 11c06436 bltu r2,r7,a32c <__udivdi3+0x2f0> + a19c: 00803fc4 movi r2,255 + a1a0: 11c11836 bltu r2,r7,a604 <__udivdi3+0x5c8> + a1a4: 000b883a mov r5,zero + a1a8: 0005883a mov r2,zero + a1ac: 3084d83a srl r2,r6,r2 + a1b0: 01000074 movhi r4,1 + a1b4: 21015d04 addi r4,r4,1396 + a1b8: 01c00804 movi r7,32 + a1bc: 1105883a add r2,r2,r4 + a1c0: 10c00003 ldbu r3,0(r2) + a1c4: 28c7883a add r3,r5,r3 + a1c8: 38edc83a sub r22,r7,r3 + a1cc: b000731e bne r22,zero,a39c <__udivdi3+0x360> + a1d0: 35400136 bltu r6,r21,a1d8 <__udivdi3+0x19c> + a1d4: e4c05b36 bltu fp,r19,a344 <__udivdi3+0x308> + a1d8: 00800044 movi r2,1 + a1dc: 0009883a mov r4,zero + a1e0: d8800315 stw r2,12(sp) + a1e4: d9400317 ldw r5,12(sp) + a1e8: 2007883a mov r3,r4 + a1ec: d9000415 stw r4,16(sp) + a1f0: 2805883a mov r2,r5 + a1f4: dfc00e17 ldw ra,56(sp) + a1f8: df000d17 ldw fp,52(sp) + a1fc: ddc00c17 ldw r23,48(sp) + a200: dd800b17 ldw r22,44(sp) + a204: dd400a17 ldw r21,40(sp) + a208: dd000917 ldw r20,36(sp) + a20c: dcc00817 ldw r19,32(sp) + a210: dc800717 ldw r18,28(sp) + a214: dc400617 ldw r17,24(sp) + a218: dc000517 ldw r16,20(sp) + a21c: dec00f04 addi sp,sp,60 + a220: f800283a ret + a224: 00bfffd4 movui r2,65535 + a228: 12005636 bltu r2,r8,a384 <__udivdi3+0x348> + a22c: 00803fc4 movi r2,255 + a230: 12010036 bltu r2,r8,a634 <__udivdi3+0x5f8> + a234: 000b883a mov r5,zero + a238: 0005883a mov r2,zero + a23c: 9884d83a srl r2,r19,r2 + a240: 01000074 movhi r4,1 + a244: 21015d04 addi r4,r4,1396 + a248: 01800804 movi r6,32 + a24c: 1105883a add r2,r2,r4 + a250: 10c00003 ldbu r3,0(r2) + a254: 28c7883a add r3,r5,r3 + a258: 30cbc83a sub r5,r6,r3 + a25c: 28000626 beq r5,zero,a278 <__udivdi3+0x23c> + a260: 3145c83a sub r2,r6,r5 + a264: e084d83a srl r2,fp,r2 + a268: a946983a sll r3,r21,r5 + a26c: e178983a sll fp,fp,r5 + a270: 9966983a sll r19,r19,r5 + a274: 18aab03a or r21,r3,r2 + a278: 982ed43a srli r23,r19,16 + a27c: a809883a mov r4,r21 + a280: 9cbfffcc andi r18,r19,65535 + a284: b80b883a mov r5,r23 + a288: 0002c140 call 2c14 <__udivsi3> + a28c: 100b883a mov r5,r2 + a290: 9009883a mov r4,r18 + a294: 1021883a mov r16,r2 + a298: 0002c240 call 2c24 <__mulsi3> + a29c: a809883a mov r4,r21 + a2a0: b80b883a mov r5,r23 + a2a4: 1023883a mov r17,r2 + a2a8: 0002c1c0 call 2c1c <__umodsi3> + a2ac: 1004943a slli r2,r2,16 + a2b0: e006d43a srli r3,fp,16 + a2b4: 10c4b03a or r2,r2,r3 + a2b8: 1440042e bgeu r2,r17,a2cc <__udivdi3+0x290> + a2bc: 14c5883a add r2,r2,r19 + a2c0: 843fffc4 addi r16,r16,-1 + a2c4: 14c00136 bltu r2,r19,a2cc <__udivdi3+0x290> + a2c8: 1440ea36 bltu r2,r17,a674 <__udivdi3+0x638> + a2cc: 1463c83a sub r17,r2,r17 + a2d0: 8809883a mov r4,r17 + a2d4: b80b883a mov r5,r23 + a2d8: 0002c140 call 2c14 <__udivsi3> + a2dc: 100b883a mov r5,r2 + a2e0: 9009883a mov r4,r18 + a2e4: 102b883a mov r21,r2 + a2e8: 0002c240 call 2c24 <__mulsi3> + a2ec: 8809883a mov r4,r17 + a2f0: b80b883a mov r5,r23 + a2f4: 1025883a mov r18,r2 + a2f8: 0002c1c0 call 2c1c <__umodsi3> + a2fc: 1004943a slli r2,r2,16 + a300: e0ffffcc andi r3,fp,65535 + a304: 10c4b03a or r2,r2,r3 + a308: 1480042e bgeu r2,r18,a31c <__udivdi3+0x2e0> + a30c: 9885883a add r2,r19,r2 + a310: ad7fffc4 addi r21,r21,-1 + a314: 14c00136 bltu r2,r19,a31c <__udivdi3+0x2e0> + a318: 1480d936 bltu r2,r18,a680 <__udivdi3+0x644> + a31c: 8004943a slli r2,r16,16 + a320: 0009883a mov r4,zero + a324: a884b03a or r2,r21,r2 + a328: 003fad06 br a1e0 <__udivdi3+0x1a4> + a32c: 00804034 movhi r2,256 + a330: 10bfffc4 addi r2,r2,-1 + a334: 11c0b636 bltu r2,r7,a610 <__udivdi3+0x5d4> + a338: 01400404 movi r5,16 + a33c: 2805883a mov r2,r5 + a340: 003f9a06 br a1ac <__udivdi3+0x170> + a344: 0005883a mov r2,zero + a348: 0009883a mov r4,zero + a34c: 003fa406 br a1e0 <__udivdi3+0x1a4> + a350: 00804034 movhi r2,256 + a354: 10bfffc4 addi r2,r2,-1 + a358: 14c0b336 bltu r2,r19,a628 <__udivdi3+0x5ec> + a35c: 01400404 movi r5,16 + a360: 2805883a mov r2,r5 + a364: 003f5106 br a0ac <__udivdi3+0x70> + a368: 01000044 movi r4,1 + a36c: 000b883a mov r5,zero + a370: 0002c140 call 2c14 <__udivsi3> + a374: 1027883a mov r19,r2 + a378: 00bfffd4 movui r2,65535 + a37c: 14fff436 bltu r2,r19,a350 <__udivdi3+0x314> + a380: 003f4606 br a09c <__udivdi3+0x60> + a384: 00804034 movhi r2,256 + a388: 10bfffc4 addi r2,r2,-1 + a38c: 1200ac36 bltu r2,r8,a640 <__udivdi3+0x604> + a390: 01400404 movi r5,16 + a394: 2805883a mov r2,r5 + a398: 003fa806 br a23c <__udivdi3+0x200> + a39c: 3d85c83a sub r2,r7,r22 + a3a0: 3588983a sll r4,r6,r22 + a3a4: 9886d83a srl r3,r19,r2 + a3a8: a8a2d83a srl r17,r21,r2 + a3ac: e084d83a srl r2,fp,r2 + a3b0: 20eeb03a or r23,r4,r3 + a3b4: b824d43a srli r18,r23,16 + a3b8: ad86983a sll r3,r21,r22 + a3bc: 8809883a mov r4,r17 + a3c0: 900b883a mov r5,r18 + a3c4: 1886b03a or r3,r3,r2 + a3c8: d8c00115 stw r3,4(sp) + a3cc: bc3fffcc andi r16,r23,65535 + a3d0: 0002c140 call 2c14 <__udivsi3> + a3d4: 100b883a mov r5,r2 + a3d8: 8009883a mov r4,r16 + a3dc: 1029883a mov r20,r2 + a3e0: 0002c240 call 2c24 <__mulsi3> + a3e4: 900b883a mov r5,r18 + a3e8: 8809883a mov r4,r17 + a3ec: 102b883a mov r21,r2 + a3f0: 0002c1c0 call 2c1c <__umodsi3> + a3f4: d9400117 ldw r5,4(sp) + a3f8: 1004943a slli r2,r2,16 + a3fc: 9da6983a sll r19,r19,r22 + a400: 2806d43a srli r3,r5,16 + a404: 10c4b03a or r2,r2,r3 + a408: 1540032e bgeu r2,r21,a418 <__udivdi3+0x3dc> + a40c: 15c5883a add r2,r2,r23 + a410: a53fffc4 addi r20,r20,-1 + a414: 15c0912e bgeu r2,r23,a65c <__udivdi3+0x620> + a418: 1563c83a sub r17,r2,r21 + a41c: 8809883a mov r4,r17 + a420: 900b883a mov r5,r18 + a424: 0002c140 call 2c14 <__udivsi3> + a428: 100b883a mov r5,r2 + a42c: 8009883a mov r4,r16 + a430: 102b883a mov r21,r2 + a434: 0002c240 call 2c24 <__mulsi3> + a438: 8809883a mov r4,r17 + a43c: 900b883a mov r5,r18 + a440: 1021883a mov r16,r2 + a444: 0002c1c0 call 2c1c <__umodsi3> + a448: da800117 ldw r10,4(sp) + a44c: 1004943a slli r2,r2,16 + a450: 50ffffcc andi r3,r10,65535 + a454: 10c6b03a or r3,r2,r3 + a458: 1c00032e bgeu r3,r16,a468 <__udivdi3+0x42c> + a45c: 1dc7883a add r3,r3,r23 + a460: ad7fffc4 addi r21,r21,-1 + a464: 1dc0792e bgeu r3,r23,a64c <__udivdi3+0x610> + a468: a004943a slli r2,r20,16 + a46c: 982ed43a srli r23,r19,16 + a470: 9cffffcc andi r19,r19,65535 + a474: a8a4b03a or r18,r21,r2 + a478: 947fffcc andi r17,r18,65535 + a47c: 902ad43a srli r21,r18,16 + a480: 8809883a mov r4,r17 + a484: 980b883a mov r5,r19 + a488: 1c21c83a sub r16,r3,r16 + a48c: 0002c240 call 2c24 <__mulsi3> + a490: 8809883a mov r4,r17 + a494: b80b883a mov r5,r23 + a498: 1029883a mov r20,r2 + a49c: 0002c240 call 2c24 <__mulsi3> + a4a0: 980b883a mov r5,r19 + a4a4: a809883a mov r4,r21 + a4a8: 1023883a mov r17,r2 + a4ac: 0002c240 call 2c24 <__mulsi3> + a4b0: a809883a mov r4,r21 + a4b4: b80b883a mov r5,r23 + a4b8: 1027883a mov r19,r2 + a4bc: 0002c240 call 2c24 <__mulsi3> + a4c0: 1009883a mov r4,r2 + a4c4: a004d43a srli r2,r20,16 + a4c8: 8ce3883a add r17,r17,r19 + a4cc: 1447883a add r3,r2,r17 + a4d0: 1cc0022e bgeu r3,r19,a4dc <__udivdi3+0x4a0> + a4d4: 00800074 movhi r2,1 + a4d8: 2089883a add r4,r4,r2 + a4dc: 1804d43a srli r2,r3,16 + a4e0: 2085883a add r2,r4,r2 + a4e4: 80804436 bltu r16,r2,a5f8 <__udivdi3+0x5bc> + a4e8: 80803e26 beq r16,r2,a5e4 <__udivdi3+0x5a8> + a4ec: 9005883a mov r2,r18 + a4f0: 0009883a mov r4,zero + a4f4: 003f3a06 br a1e0 <__udivdi3+0x1a4> + a4f8: 9d26983a sll r19,r19,r20 + a4fc: 3505c83a sub r2,r6,r20 + a500: a8a2d83a srl r17,r21,r2 + a504: 982ed43a srli r23,r19,16 + a508: e084d83a srl r2,fp,r2 + a50c: ad06983a sll r3,r21,r20 + a510: 8809883a mov r4,r17 + a514: b80b883a mov r5,r23 + a518: 1886b03a or r3,r3,r2 + a51c: d8c00015 stw r3,0(sp) + a520: 9dbfffcc andi r22,r19,65535 + a524: 0002c140 call 2c14 <__udivsi3> + a528: 100b883a mov r5,r2 + a52c: b009883a mov r4,r22 + a530: d8800215 stw r2,8(sp) + a534: 0002c240 call 2c24 <__mulsi3> + a538: 8809883a mov r4,r17 + a53c: b80b883a mov r5,r23 + a540: 102b883a mov r21,r2 + a544: 0002c1c0 call 2c1c <__umodsi3> + a548: d9000017 ldw r4,0(sp) + a54c: 1004943a slli r2,r2,16 + a550: 2006d43a srli r3,r4,16 + a554: 10c4b03a or r2,r2,r3 + a558: 1540052e bgeu r2,r21,a570 <__udivdi3+0x534> + a55c: d9400217 ldw r5,8(sp) + a560: 14c5883a add r2,r2,r19 + a564: 297fffc4 addi r5,r5,-1 + a568: d9400215 stw r5,8(sp) + a56c: 14c0462e bgeu r2,r19,a688 <__udivdi3+0x64c> + a570: 1563c83a sub r17,r2,r21 + a574: 8809883a mov r4,r17 + a578: b80b883a mov r5,r23 + a57c: 0002c140 call 2c14 <__udivsi3> + a580: 100b883a mov r5,r2 + a584: b009883a mov r4,r22 + a588: 1025883a mov r18,r2 + a58c: 0002c240 call 2c24 <__mulsi3> + a590: 8809883a mov r4,r17 + a594: b80b883a mov r5,r23 + a598: 1021883a mov r16,r2 + a59c: 0002c1c0 call 2c1c <__umodsi3> + a5a0: da800017 ldw r10,0(sp) + a5a4: 1004943a slli r2,r2,16 + a5a8: 50ffffcc andi r3,r10,65535 + a5ac: 10c6b03a or r3,r2,r3 + a5b0: 1c00062e bgeu r3,r16,a5cc <__udivdi3+0x590> + a5b4: 1cc7883a add r3,r3,r19 + a5b8: 94bfffc4 addi r18,r18,-1 + a5bc: 1cc00336 bltu r3,r19,a5cc <__udivdi3+0x590> + a5c0: 1c00022e bgeu r3,r16,a5cc <__udivdi3+0x590> + a5c4: 94bfffc4 addi r18,r18,-1 + a5c8: 1cc7883a add r3,r3,r19 + a5cc: d9000217 ldw r4,8(sp) + a5d0: e538983a sll fp,fp,r20 + a5d4: 1c2bc83a sub r21,r3,r16 + a5d8: 2004943a slli r2,r4,16 + a5dc: 90a8b03a or r20,r18,r2 + a5e0: 003ebf06 br a0e0 <__udivdi3+0xa4> + a5e4: 1804943a slli r2,r3,16 + a5e8: e588983a sll r4,fp,r22 + a5ec: a0ffffcc andi r3,r20,65535 + a5f0: 10c5883a add r2,r2,r3 + a5f4: 20bfbd2e bgeu r4,r2,a4ec <__udivdi3+0x4b0> + a5f8: 90bfffc4 addi r2,r18,-1 + a5fc: 0009883a mov r4,zero + a600: 003ef706 br a1e0 <__udivdi3+0x1a4> + a604: 01400204 movi r5,8 + a608: 2805883a mov r2,r5 + a60c: 003ee706 br a1ac <__udivdi3+0x170> + a610: 01400604 movi r5,24 + a614: 2805883a mov r2,r5 + a618: 003ee406 br a1ac <__udivdi3+0x170> + a61c: 01400204 movi r5,8 + a620: 2805883a mov r2,r5 + a624: 003ea106 br a0ac <__udivdi3+0x70> + a628: 01400604 movi r5,24 + a62c: 2805883a mov r2,r5 + a630: 003e9e06 br a0ac <__udivdi3+0x70> + a634: 01400204 movi r5,8 + a638: 2805883a mov r2,r5 + a63c: 003eff06 br a23c <__udivdi3+0x200> + a640: 01400604 movi r5,24 + a644: 2805883a mov r2,r5 + a648: 003efc06 br a23c <__udivdi3+0x200> + a64c: 1c3f862e bgeu r3,r16,a468 <__udivdi3+0x42c> + a650: 1dc7883a add r3,r3,r23 + a654: ad7fffc4 addi r21,r21,-1 + a658: 003f8306 br a468 <__udivdi3+0x42c> + a65c: 157f6e2e bgeu r2,r21,a418 <__udivdi3+0x3dc> + a660: a53fffc4 addi r20,r20,-1 + a664: 15c5883a add r2,r2,r23 + a668: 003f6b06 br a418 <__udivdi3+0x3dc> + a66c: ad7fffc4 addi r21,r21,-1 + a670: 003ec206 br a17c <__udivdi3+0x140> + a674: 843fffc4 addi r16,r16,-1 + a678: 14c5883a add r2,r2,r19 + a67c: 003f1306 br a2cc <__udivdi3+0x290> + a680: ad7fffc4 addi r21,r21,-1 + a684: 003f2506 br a31c <__udivdi3+0x2e0> + a688: 157fb92e bgeu r2,r21,a570 <__udivdi3+0x534> + a68c: 297fffc4 addi r5,r5,-1 + a690: 14c5883a add r2,r2,r19 + a694: d9400215 stw r5,8(sp) + a698: 003fb506 br a570 <__udivdi3+0x534> + a69c: 843fffc4 addi r16,r16,-1 + a6a0: 14c5883a add r2,r2,r19 + a6a4: 003ea106 br a12c <__udivdi3+0xf0> + +0000a6a8 <__umoddi3>: + a6a8: defff004 addi sp,sp,-64 + a6ac: 3011883a mov r8,r6 + a6b0: 000d883a mov r6,zero + a6b4: dd400b15 stw r21,44(sp) + a6b8: dcc00915 stw r19,36(sp) + a6bc: dc000615 stw r16,24(sp) + a6c0: dfc00f15 stw ra,60(sp) + a6c4: df000e15 stw fp,56(sp) + a6c8: ddc00d15 stw r23,52(sp) + a6cc: dd800c15 stw r22,48(sp) + a6d0: dd000a15 stw r20,40(sp) + a6d4: dc800815 stw r18,32(sp) + a6d8: dc400715 stw r17,28(sp) + a6dc: 2817883a mov r11,r5 + a6e0: d9800415 stw r6,16(sp) + a6e4: 4027883a mov r19,r8 + a6e8: d9800515 stw r6,20(sp) + a6ec: 2021883a mov r16,r4 + a6f0: 282b883a mov r21,r5 + a6f4: 38002c1e bne r7,zero,a7a8 <__umoddi3+0x100> + a6f8: 2a005636 bltu r5,r8,a854 <__umoddi3+0x1ac> + a6fc: 40009a26 beq r8,zero,a968 <__umoddi3+0x2c0> + a700: 00bfffd4 movui r2,65535 + a704: 14c09236 bltu r2,r19,a950 <__umoddi3+0x2a8> + a708: 00803fc4 movi r2,255 + a70c: 14c15c36 bltu r2,r19,ac80 <__umoddi3+0x5d8> + a710: 000b883a mov r5,zero + a714: 0005883a mov r2,zero + a718: 9884d83a srl r2,r19,r2 + a71c: 01000074 movhi r4,1 + a720: 21015d04 addi r4,r4,1396 + a724: 01800804 movi r6,32 + a728: 1105883a add r2,r2,r4 + a72c: 10c00003 ldbu r3,0(r2) + a730: 28c7883a add r3,r5,r3 + a734: 30e5c83a sub r18,r6,r3 + a738: 9000a41e bne r18,zero,a9cc <__umoddi3+0x324> + a73c: 982ed43a srli r23,r19,16 + a740: acebc83a sub r21,r21,r19 + a744: 9d3fffcc andi r20,r19,65535 + a748: 002d883a mov r22,zero + a74c: a809883a mov r4,r21 + a750: b80b883a mov r5,r23 + a754: 0002c140 call 2c14 <__udivsi3> + a758: 100b883a mov r5,r2 + a75c: a009883a mov r4,r20 + a760: 0002c240 call 2c24 <__mulsi3> + a764: a809883a mov r4,r21 + a768: b80b883a mov r5,r23 + a76c: 1023883a mov r17,r2 + a770: 0002c1c0 call 2c1c <__umodsi3> + a774: 1004943a slli r2,r2,16 + a778: 8006d43a srli r3,r16,16 + a77c: 10c4b03a or r2,r2,r3 + a780: 1440032e bgeu r2,r17,a790 <__umoddi3+0xe8> + a784: 14c5883a add r2,r2,r19 + a788: 14c00136 bltu r2,r19,a790 <__umoddi3+0xe8> + a78c: 14415836 bltu r2,r17,acf0 <__umoddi3+0x648> + a790: 1463c83a sub r17,r2,r17 + a794: 8809883a mov r4,r17 + a798: b80b883a mov r5,r23 + a79c: 0002c140 call 2c14 <__udivsi3> + a7a0: a009883a mov r4,r20 + a7a4: 00005306 br a8f4 <__umoddi3+0x24c> + a7a8: 380d883a mov r6,r7 + a7ac: 29c0132e bgeu r5,r7,a7fc <__umoddi3+0x154> + a7b0: d9000415 stw r4,16(sp) + a7b4: d9400515 stw r5,20(sp) + a7b8: d9400417 ldw r5,16(sp) + a7bc: 5813883a mov r9,r11 + a7c0: 2811883a mov r8,r5 + a7c4: 4005883a mov r2,r8 + a7c8: 4807883a mov r3,r9 + a7cc: dfc00f17 ldw ra,60(sp) + a7d0: df000e17 ldw fp,56(sp) + a7d4: ddc00d17 ldw r23,52(sp) + a7d8: dd800c17 ldw r22,48(sp) + a7dc: dd400b17 ldw r21,44(sp) + a7e0: dd000a17 ldw r20,40(sp) + a7e4: dcc00917 ldw r19,36(sp) + a7e8: dc800817 ldw r18,32(sp) + a7ec: dc400717 ldw r17,28(sp) + a7f0: dc000617 ldw r16,24(sp) + a7f4: dec01004 addi sp,sp,64 + a7f8: f800283a ret + a7fc: 00bfffd4 movui r2,65535 + a800: 11c06636 bltu r2,r7,a99c <__umoddi3+0x2f4> + a804: 00803fc4 movi r2,255 + a808: 11c12036 bltu r2,r7,ac8c <__umoddi3+0x5e4> + a80c: 000b883a mov r5,zero + a810: 0005883a mov r2,zero + a814: 3084d83a srl r2,r6,r2 + a818: 01000074 movhi r4,1 + a81c: 21015d04 addi r4,r4,1396 + a820: 01c00804 movi r7,32 + a824: 1105883a add r2,r2,r4 + a828: 10c00003 ldbu r3,0(r2) + a82c: 28c7883a add r3,r5,r3 + a830: 38e5c83a sub r18,r7,r3 + a834: 9000941e bne r18,zero,aa88 <__umoddi3+0x3e0> + a838: 35405e36 bltu r6,r21,a9b4 <__umoddi3+0x30c> + a83c: 84c05d2e bgeu r16,r19,a9b4 <__umoddi3+0x30c> + a840: 8011883a mov r8,r16 + a844: a813883a mov r9,r21 + a848: dc000415 stw r16,16(sp) + a84c: dd400515 stw r21,20(sp) + a850: 003fdc06 br a7c4 <__umoddi3+0x11c> + a854: 00bfffd4 movui r2,65535 + a858: 12004a36 bltu r2,r8,a984 <__umoddi3+0x2dc> + a85c: 00803fc4 movi r2,255 + a860: 12010d36 bltu r2,r8,ac98 <__umoddi3+0x5f0> + a864: 000b883a mov r5,zero + a868: 0005883a mov r2,zero + a86c: 9884d83a srl r2,r19,r2 + a870: 01000074 movhi r4,1 + a874: 21015d04 addi r4,r4,1396 + a878: 01800804 movi r6,32 + a87c: 1105883a add r2,r2,r4 + a880: 10c00003 ldbu r3,0(r2) + a884: 28c7883a add r3,r5,r3 + a888: 30c7c83a sub r3,r6,r3 + a88c: 1800dc1e bne r3,zero,ac00 <__umoddi3+0x558> + a890: 002d883a mov r22,zero + a894: 982ed43a srli r23,r19,16 + a898: a809883a mov r4,r21 + a89c: 9cbfffcc andi r18,r19,65535 + a8a0: b80b883a mov r5,r23 + a8a4: 0002c140 call 2c14 <__udivsi3> + a8a8: 100b883a mov r5,r2 + a8ac: 9009883a mov r4,r18 + a8b0: 0002c240 call 2c24 <__mulsi3> + a8b4: a809883a mov r4,r21 + a8b8: b80b883a mov r5,r23 + a8bc: 1023883a mov r17,r2 + a8c0: 0002c1c0 call 2c1c <__umodsi3> + a8c4: 1004943a slli r2,r2,16 + a8c8: 8006d43a srli r3,r16,16 + a8cc: 10c4b03a or r2,r2,r3 + a8d0: 1440032e bgeu r2,r17,a8e0 <__umoddi3+0x238> + a8d4: 14c5883a add r2,r2,r19 + a8d8: 14c00136 bltu r2,r19,a8e0 <__umoddi3+0x238> + a8dc: 14410236 bltu r2,r17,ace8 <__umoddi3+0x640> + a8e0: 1463c83a sub r17,r2,r17 + a8e4: 8809883a mov r4,r17 + a8e8: b80b883a mov r5,r23 + a8ec: 0002c140 call 2c14 <__udivsi3> + a8f0: 9009883a mov r4,r18 + a8f4: 100b883a mov r5,r2 + a8f8: 0002c240 call 2c24 <__mulsi3> + a8fc: 8809883a mov r4,r17 + a900: b80b883a mov r5,r23 + a904: 102b883a mov r21,r2 + a908: 0002c1c0 call 2c1c <__umodsi3> + a90c: 1004943a slli r2,r2,16 + a910: 80ffffcc andi r3,r16,65535 + a914: 10c4b03a or r2,r2,r3 + a918: 1540042e bgeu r2,r21,a92c <__umoddi3+0x284> + a91c: 14c5883a add r2,r2,r19 + a920: 14c00236 bltu r2,r19,a92c <__umoddi3+0x284> + a924: 1540012e bgeu r2,r21,a92c <__umoddi3+0x284> + a928: 14c5883a add r2,r2,r19 + a92c: 1545c83a sub r2,r2,r21 + a930: 1584d83a srl r2,r2,r22 + a934: 0013883a mov r9,zero + a938: d8800415 stw r2,16(sp) + a93c: d8c00417 ldw r3,16(sp) + a940: 0005883a mov r2,zero + a944: d8800515 stw r2,20(sp) + a948: 1811883a mov r8,r3 + a94c: 003f9d06 br a7c4 <__umoddi3+0x11c> + a950: 00804034 movhi r2,256 + a954: 10bfffc4 addi r2,r2,-1 + a958: 14c0c636 bltu r2,r19,ac74 <__umoddi3+0x5cc> + a95c: 01400404 movi r5,16 + a960: 2805883a mov r2,r5 + a964: 003f6c06 br a718 <__umoddi3+0x70> + a968: 01000044 movi r4,1 + a96c: 000b883a mov r5,zero + a970: 0002c140 call 2c14 <__udivsi3> + a974: 1027883a mov r19,r2 + a978: 00bfffd4 movui r2,65535 + a97c: 14fff436 bltu r2,r19,a950 <__umoddi3+0x2a8> + a980: 003f6106 br a708 <__umoddi3+0x60> + a984: 00804034 movhi r2,256 + a988: 10bfffc4 addi r2,r2,-1 + a98c: 1200c536 bltu r2,r8,aca4 <__umoddi3+0x5fc> + a990: 01400404 movi r5,16 + a994: 2805883a mov r2,r5 + a998: 003fb406 br a86c <__umoddi3+0x1c4> + a99c: 00804034 movhi r2,256 + a9a0: 10bfffc4 addi r2,r2,-1 + a9a4: 11c0c236 bltu r2,r7,acb0 <__umoddi3+0x608> + a9a8: 01400404 movi r5,16 + a9ac: 2805883a mov r2,r5 + a9b0: 003f9806 br a814 <__umoddi3+0x16c> + a9b4: 84c9c83a sub r4,r16,r19 + a9b8: 8105803a cmpltu r2,r16,r4 + a9bc: a987c83a sub r3,r21,r6 + a9c0: 18abc83a sub r21,r3,r2 + a9c4: 2021883a mov r16,r4 + a9c8: 003f9d06 br a840 <__umoddi3+0x198> + a9cc: 9ca6983a sll r19,r19,r18 + a9d0: 3485c83a sub r2,r6,r18 + a9d4: a8a2d83a srl r17,r21,r2 + a9d8: 982ed43a srli r23,r19,16 + a9dc: ac86983a sll r3,r21,r18 + a9e0: 8084d83a srl r2,r16,r2 + a9e4: 8809883a mov r4,r17 + a9e8: b80b883a mov r5,r23 + a9ec: 18b8b03a or fp,r3,r2 + a9f0: 9d3fffcc andi r20,r19,65535 + a9f4: 0002c140 call 2c14 <__udivsi3> + a9f8: 100b883a mov r5,r2 + a9fc: a009883a mov r4,r20 + aa00: 0002c240 call 2c24 <__mulsi3> + aa04: 8809883a mov r4,r17 + aa08: b80b883a mov r5,r23 + aa0c: 102b883a mov r21,r2 + aa10: 0002c1c0 call 2c1c <__umodsi3> + aa14: 1004943a slli r2,r2,16 + aa18: e006d43a srli r3,fp,16 + aa1c: 902d883a mov r22,r18 + aa20: 10c4b03a or r2,r2,r3 + aa24: 1540022e bgeu r2,r21,aa30 <__umoddi3+0x388> + aa28: 14c5883a add r2,r2,r19 + aa2c: 14c0ab2e bgeu r2,r19,acdc <__umoddi3+0x634> + aa30: 1563c83a sub r17,r2,r21 + aa34: 8809883a mov r4,r17 + aa38: b80b883a mov r5,r23 + aa3c: 0002c140 call 2c14 <__udivsi3> + aa40: 100b883a mov r5,r2 + aa44: a009883a mov r4,r20 + aa48: 0002c240 call 2c24 <__mulsi3> + aa4c: 8809883a mov r4,r17 + aa50: b80b883a mov r5,r23 + aa54: 102b883a mov r21,r2 + aa58: 0002c1c0 call 2c1c <__umodsi3> + aa5c: 1004943a slli r2,r2,16 + aa60: e0ffffcc andi r3,fp,65535 + aa64: 10c4b03a or r2,r2,r3 + aa68: 1540042e bgeu r2,r21,aa7c <__umoddi3+0x3d4> + aa6c: 14c5883a add r2,r2,r19 + aa70: 14c00236 bltu r2,r19,aa7c <__umoddi3+0x3d4> + aa74: 1540012e bgeu r2,r21,aa7c <__umoddi3+0x3d4> + aa78: 14c5883a add r2,r2,r19 + aa7c: 84a0983a sll r16,r16,r18 + aa80: 156bc83a sub r21,r2,r21 + aa84: 003f3106 br a74c <__umoddi3+0xa4> + aa88: 3c8fc83a sub r7,r7,r18 + aa8c: 3486983a sll r3,r6,r18 + aa90: 99c4d83a srl r2,r19,r7 + aa94: a9e2d83a srl r17,r21,r7 + aa98: ac8c983a sll r6,r21,r18 + aa9c: 18acb03a or r22,r3,r2 + aaa0: b02ed43a srli r23,r22,16 + aaa4: 81c4d83a srl r2,r16,r7 + aaa8: 8809883a mov r4,r17 + aaac: b80b883a mov r5,r23 + aab0: 308cb03a or r6,r6,r2 + aab4: d9c00315 stw r7,12(sp) + aab8: d9800215 stw r6,8(sp) + aabc: b53fffcc andi r20,r22,65535 + aac0: 0002c140 call 2c14 <__udivsi3> + aac4: 100b883a mov r5,r2 + aac8: a009883a mov r4,r20 + aacc: 1039883a mov fp,r2 + aad0: 0002c240 call 2c24 <__mulsi3> + aad4: 8809883a mov r4,r17 + aad8: b80b883a mov r5,r23 + aadc: 102b883a mov r21,r2 + aae0: 0002c1c0 call 2c1c <__umodsi3> + aae4: d9000217 ldw r4,8(sp) + aae8: 1004943a slli r2,r2,16 + aaec: 9ca6983a sll r19,r19,r18 + aaf0: 2006d43a srli r3,r4,16 + aaf4: 84a0983a sll r16,r16,r18 + aaf8: dcc00015 stw r19,0(sp) + aafc: 10c4b03a or r2,r2,r3 + ab00: dc000115 stw r16,4(sp) + ab04: 1540032e bgeu r2,r21,ab14 <__umoddi3+0x46c> + ab08: 1585883a add r2,r2,r22 + ab0c: e73fffc4 addi fp,fp,-1 + ab10: 15806e2e bgeu r2,r22,accc <__umoddi3+0x624> + ab14: 1563c83a sub r17,r2,r21 + ab18: 8809883a mov r4,r17 + ab1c: b80b883a mov r5,r23 + ab20: 0002c140 call 2c14 <__udivsi3> + ab24: 100b883a mov r5,r2 + ab28: a009883a mov r4,r20 + ab2c: 1021883a mov r16,r2 + ab30: 0002c240 call 2c24 <__mulsi3> + ab34: b80b883a mov r5,r23 + ab38: 8809883a mov r4,r17 + ab3c: 1029883a mov r20,r2 + ab40: 0002c1c0 call 2c1c <__umodsi3> + ab44: d9400217 ldw r5,8(sp) + ab48: 1004943a slli r2,r2,16 + ab4c: 28ffffcc andi r3,r5,65535 + ab50: 10c4b03a or r2,r2,r3 + ab54: 1500032e bgeu r2,r20,ab64 <__umoddi3+0x4bc> + ab58: 1585883a add r2,r2,r22 + ab5c: 843fffc4 addi r16,r16,-1 + ab60: 1580562e bgeu r2,r22,acbc <__umoddi3+0x614> + ab64: d9800017 ldw r6,0(sp) + ab68: e022943a slli r17,fp,16 + ab6c: 302ed43a srli r23,r6,16 + ab70: 8462b03a or r17,r16,r17 + ab74: 34ffffcc andi r19,r6,65535 + ab78: 882ad43a srli r21,r17,16 + ab7c: 8c7fffcc andi r17,r17,65535 + ab80: 8809883a mov r4,r17 + ab84: 980b883a mov r5,r19 + ab88: 1521c83a sub r16,r2,r20 + ab8c: 0002c240 call 2c24 <__mulsi3> + ab90: 8809883a mov r4,r17 + ab94: b80b883a mov r5,r23 + ab98: 1029883a mov r20,r2 + ab9c: 0002c240 call 2c24 <__mulsi3> + aba0: 980b883a mov r5,r19 + aba4: a809883a mov r4,r21 + aba8: 1023883a mov r17,r2 + abac: 0002c240 call 2c24 <__mulsi3> + abb0: a809883a mov r4,r21 + abb4: b80b883a mov r5,r23 + abb8: 1027883a mov r19,r2 + abbc: 0002c240 call 2c24 <__mulsi3> + abc0: 100b883a mov r5,r2 + abc4: a004d43a srli r2,r20,16 + abc8: 8ce3883a add r17,r17,r19 + abcc: 1449883a add r4,r2,r17 + abd0: 24c0022e bgeu r4,r19,abdc <__umoddi3+0x534> + abd4: 00800074 movhi r2,1 + abd8: 288b883a add r5,r5,r2 + abdc: 2004d43a srli r2,r4,16 + abe0: 2008943a slli r4,r4,16 + abe4: a0ffffcc andi r3,r20,65535 + abe8: 288d883a add r6,r5,r2 + abec: 20c9883a add r4,r4,r3 + abf0: 81800b36 bltu r16,r6,ac20 <__umoddi3+0x578> + abf4: 81804026 beq r16,r6,acf8 <__umoddi3+0x650> + abf8: 818dc83a sub r6,r16,r6 + abfc: 00000f06 br ac3c <__umoddi3+0x594> + ac00: 30c5c83a sub r2,r6,r3 + ac04: 182d883a mov r22,r3 + ac08: 8084d83a srl r2,r16,r2 + ac0c: a8c6983a sll r3,r21,r3 + ac10: 9da6983a sll r19,r19,r22 + ac14: 85a0983a sll r16,r16,r22 + ac18: 18aab03a or r21,r3,r2 + ac1c: 003f1d06 br a894 <__umoddi3+0x1ec> + ac20: d8c00017 ldw r3,0(sp) + ac24: 20c5c83a sub r2,r4,r3 + ac28: 2089803a cmpltu r4,r4,r2 + ac2c: 3587c83a sub r3,r6,r22 + ac30: 1907c83a sub r3,r3,r4 + ac34: 80cdc83a sub r6,r16,r3 + ac38: 1009883a mov r4,r2 + ac3c: d9400117 ldw r5,4(sp) + ac40: 2905c83a sub r2,r5,r4 + ac44: 2887803a cmpltu r3,r5,r2 + ac48: 30c7c83a sub r3,r6,r3 + ac4c: d9800317 ldw r6,12(sp) + ac50: 1484d83a srl r2,r2,r18 + ac54: 1988983a sll r4,r3,r6 + ac58: 1c86d83a srl r3,r3,r18 + ac5c: 2088b03a or r4,r4,r2 + ac60: 2011883a mov r8,r4 + ac64: 1813883a mov r9,r3 + ac68: d9000415 stw r4,16(sp) + ac6c: d8c00515 stw r3,20(sp) + ac70: 003ed406 br a7c4 <__umoddi3+0x11c> + ac74: 01400604 movi r5,24 + ac78: 2805883a mov r2,r5 + ac7c: 003ea606 br a718 <__umoddi3+0x70> + ac80: 01400204 movi r5,8 + ac84: 2805883a mov r2,r5 + ac88: 003ea306 br a718 <__umoddi3+0x70> + ac8c: 01400204 movi r5,8 + ac90: 2805883a mov r2,r5 + ac94: 003edf06 br a814 <__umoddi3+0x16c> + ac98: 01400204 movi r5,8 + ac9c: 2805883a mov r2,r5 + aca0: 003ef206 br a86c <__umoddi3+0x1c4> + aca4: 01400604 movi r5,24 + aca8: 2805883a mov r2,r5 + acac: 003eef06 br a86c <__umoddi3+0x1c4> + acb0: 01400604 movi r5,24 + acb4: 2805883a mov r2,r5 + acb8: 003ed606 br a814 <__umoddi3+0x16c> + acbc: 153fa92e bgeu r2,r20,ab64 <__umoddi3+0x4bc> + acc0: 843fffc4 addi r16,r16,-1 + acc4: 1585883a add r2,r2,r22 + acc8: 003fa606 br ab64 <__umoddi3+0x4bc> + accc: 157f912e bgeu r2,r21,ab14 <__umoddi3+0x46c> + acd0: e73fffc4 addi fp,fp,-1 + acd4: 1585883a add r2,r2,r22 + acd8: 003f8e06 br ab14 <__umoddi3+0x46c> + acdc: 157f542e bgeu r2,r21,aa30 <__umoddi3+0x388> + ace0: 14c5883a add r2,r2,r19 + ace4: 003f5206 br aa30 <__umoddi3+0x388> + ace8: 14c5883a add r2,r2,r19 + acec: 003efc06 br a8e0 <__umoddi3+0x238> + acf0: 14c5883a add r2,r2,r19 + acf4: 003ea606 br a790 <__umoddi3+0xe8> + acf8: d8800117 ldw r2,4(sp) + acfc: 113fc836 bltu r2,r4,ac20 <__umoddi3+0x578> + ad00: 000d883a mov r6,zero + ad04: 003fcd06 br ac3c <__umoddi3+0x594> + +0000ad08 <_fpadd_parts>: + ad08: defff804 addi sp,sp,-32 + ad0c: dcc00315 stw r19,12(sp) + ad10: 2027883a mov r19,r4 + ad14: 21000017 ldw r4,0(r4) + ad18: 00c00044 movi r3,1 + ad1c: dd400515 stw r21,20(sp) + ad20: dd000415 stw r20,16(sp) + ad24: ddc00715 stw r23,28(sp) + ad28: dd800615 stw r22,24(sp) + ad2c: dc800215 stw r18,8(sp) + ad30: dc400115 stw r17,4(sp) + ad34: dc000015 stw r16,0(sp) + ad38: 282b883a mov r21,r5 + ad3c: 3029883a mov r20,r6 + ad40: 1900632e bgeu r3,r4,aed0 <_fpadd_parts+0x1c8> + ad44: 28800017 ldw r2,0(r5) + ad48: 1880812e bgeu r3,r2,af50 <_fpadd_parts+0x248> + ad4c: 00c00104 movi r3,4 + ad50: 20c0dc26 beq r4,r3,b0c4 <_fpadd_parts+0x3bc> + ad54: 10c07e26 beq r2,r3,af50 <_fpadd_parts+0x248> + ad58: 00c00084 movi r3,2 + ad5c: 10c06726 beq r2,r3,aefc <_fpadd_parts+0x1f4> + ad60: 20c07b26 beq r4,r3,af50 <_fpadd_parts+0x248> + ad64: 9dc00217 ldw r23,8(r19) + ad68: 28c00217 ldw r3,8(r5) + ad6c: 9c400317 ldw r17,12(r19) + ad70: 2bc00317 ldw r15,12(r5) + ad74: b8cdc83a sub r6,r23,r3 + ad78: 9c800417 ldw r18,16(r19) + ad7c: 2c000417 ldw r16,16(r5) + ad80: 3009883a mov r4,r6 + ad84: 30009716 blt r6,zero,afe4 <_fpadd_parts+0x2dc> + ad88: 00800fc4 movi r2,63 + ad8c: 11806b16 blt r2,r6,af3c <_fpadd_parts+0x234> + ad90: 0100a40e bge zero,r4,b024 <_fpadd_parts+0x31c> + ad94: 35bff804 addi r22,r6,-32 + ad98: b000bc16 blt r22,zero,b08c <_fpadd_parts+0x384> + ad9c: 8596d83a srl r11,r16,r22 + ada0: 0019883a mov r12,zero + ada4: 0013883a mov r9,zero + ada8: 01000044 movi r4,1 + adac: 0015883a mov r10,zero + adb0: b000be16 blt r22,zero,b0ac <_fpadd_parts+0x3a4> + adb4: 2590983a sll r8,r4,r22 + adb8: 000f883a mov r7,zero + adbc: 00bfffc4 movi r2,-1 + adc0: 3889883a add r4,r7,r2 + adc4: 408b883a add r5,r8,r2 + adc8: 21cd803a cmpltu r6,r4,r7 + adcc: 314b883a add r5,r6,r5 + add0: 7904703a and r2,r15,r4 + add4: 8146703a and r3,r16,r5 + add8: 10c4b03a or r2,r2,r3 + addc: 10000226 beq r2,zero,ade8 <_fpadd_parts+0xe0> + ade0: 02400044 movi r9,1 + ade4: 0015883a mov r10,zero + ade8: 5a5eb03a or r15,r11,r9 + adec: 62a0b03a or r16,r12,r10 + adf0: 99400117 ldw r5,4(r19) + adf4: a8800117 ldw r2,4(r21) + adf8: 28806e26 beq r5,r2,afb4 <_fpadd_parts+0x2ac> + adfc: 28006626 beq r5,zero,af98 <_fpadd_parts+0x290> + ae00: 7c45c83a sub r2,r15,r17 + ae04: 7889803a cmpltu r4,r15,r2 + ae08: 8487c83a sub r3,r16,r18 + ae0c: 1909c83a sub r4,r3,r4 + ae10: 100d883a mov r6,r2 + ae14: 200f883a mov r7,r4 + ae18: 38007716 blt r7,zero,aff8 <_fpadd_parts+0x2f0> + ae1c: a5c00215 stw r23,8(r20) + ae20: a1c00415 stw r7,16(r20) + ae24: a0000115 stw zero,4(r20) + ae28: a1800315 stw r6,12(r20) + ae2c: a2000317 ldw r8,12(r20) + ae30: a2400417 ldw r9,16(r20) + ae34: 00bfffc4 movi r2,-1 + ae38: 408b883a add r5,r8,r2 + ae3c: 2a09803a cmpltu r4,r5,r8 + ae40: 488d883a add r6,r9,r2 + ae44: 01c40034 movhi r7,4096 + ae48: 39ffffc4 addi r7,r7,-1 + ae4c: 218d883a add r6,r4,r6 + ae50: 39801736 bltu r7,r6,aeb0 <_fpadd_parts+0x1a8> + ae54: 31c06526 beq r6,r7,afec <_fpadd_parts+0x2e4> + ae58: a3000217 ldw r12,8(r20) + ae5c: 4209883a add r4,r8,r8 + ae60: 00bfffc4 movi r2,-1 + ae64: 220f803a cmpltu r7,r4,r8 + ae68: 4a4b883a add r5,r9,r9 + ae6c: 394f883a add r7,r7,r5 + ae70: 2095883a add r10,r4,r2 + ae74: 3897883a add r11,r7,r2 + ae78: 510d803a cmpltu r6,r10,r4 + ae7c: 6099883a add r12,r12,r2 + ae80: 32d7883a add r11,r6,r11 + ae84: 00840034 movhi r2,4096 + ae88: 10bfffc4 addi r2,r2,-1 + ae8c: 2011883a mov r8,r4 + ae90: 3813883a mov r9,r7 + ae94: a1000315 stw r4,12(r20) + ae98: a1c00415 stw r7,16(r20) + ae9c: a3000215 stw r12,8(r20) + aea0: 12c00336 bltu r2,r11,aeb0 <_fpadd_parts+0x1a8> + aea4: 58bfed1e bne r11,r2,ae5c <_fpadd_parts+0x154> + aea8: 00bfff84 movi r2,-2 + aeac: 12bfeb2e bgeu r2,r10,ae5c <_fpadd_parts+0x154> + aeb0: a2800417 ldw r10,16(r20) + aeb4: 008000c4 movi r2,3 + aeb8: 00c80034 movhi r3,8192 + aebc: 18ffffc4 addi r3,r3,-1 + aec0: a2400317 ldw r9,12(r20) + aec4: a0800015 stw r2,0(r20) + aec8: 1a802336 bltu r3,r10,af58 <_fpadd_parts+0x250> + aecc: a027883a mov r19,r20 + aed0: 9805883a mov r2,r19 + aed4: ddc00717 ldw r23,28(sp) + aed8: dd800617 ldw r22,24(sp) + aedc: dd400517 ldw r21,20(sp) + aee0: dd000417 ldw r20,16(sp) + aee4: dcc00317 ldw r19,12(sp) + aee8: dc800217 ldw r18,8(sp) + aeec: dc400117 ldw r17,4(sp) + aef0: dc000017 ldw r16,0(sp) + aef4: dec00804 addi sp,sp,32 + aef8: f800283a ret + aefc: 20fff41e bne r4,r3,aed0 <_fpadd_parts+0x1c8> + af00: 31000015 stw r4,0(r6) + af04: 98800117 ldw r2,4(r19) + af08: 30800115 stw r2,4(r6) + af0c: 98c00217 ldw r3,8(r19) + af10: 30c00215 stw r3,8(r6) + af14: 98800317 ldw r2,12(r19) + af18: 30800315 stw r2,12(r6) + af1c: 98c00417 ldw r3,16(r19) + af20: 30c00415 stw r3,16(r6) + af24: 98800117 ldw r2,4(r19) + af28: 28c00117 ldw r3,4(r5) + af2c: 3027883a mov r19,r6 + af30: 10c4703a and r2,r2,r3 + af34: 30800115 stw r2,4(r6) + af38: 003fe506 br aed0 <_fpadd_parts+0x1c8> + af3c: 1dc02616 blt r3,r23,afd8 <_fpadd_parts+0x2d0> + af40: 0023883a mov r17,zero + af44: 182f883a mov r23,r3 + af48: 0025883a mov r18,zero + af4c: 003fa806 br adf0 <_fpadd_parts+0xe8> + af50: a827883a mov r19,r21 + af54: 003fde06 br aed0 <_fpadd_parts+0x1c8> + af58: 01800044 movi r6,1 + af5c: 500497fa slli r2,r10,31 + af60: 4808d07a srli r4,r9,1 + af64: 518ad83a srl r5,r10,r6 + af68: a2000217 ldw r8,8(r20) + af6c: 1108b03a or r4,r2,r4 + af70: 0007883a mov r3,zero + af74: 4984703a and r2,r9,r6 + af78: 208cb03a or r6,r4,r2 + af7c: 28ceb03a or r7,r5,r3 + af80: 42000044 addi r8,r8,1 + af84: a027883a mov r19,r20 + af88: a1c00415 stw r7,16(r20) + af8c: a2000215 stw r8,8(r20) + af90: a1800315 stw r6,12(r20) + af94: 003fce06 br aed0 <_fpadd_parts+0x1c8> + af98: 8bc5c83a sub r2,r17,r15 + af9c: 8889803a cmpltu r4,r17,r2 + afa0: 9407c83a sub r3,r18,r16 + afa4: 1909c83a sub r4,r3,r4 + afa8: 100d883a mov r6,r2 + afac: 200f883a mov r7,r4 + afb0: 003f9906 br ae18 <_fpadd_parts+0x110> + afb4: 7c45883a add r2,r15,r17 + afb8: 13c9803a cmpltu r4,r2,r15 + afbc: 8487883a add r3,r16,r18 + afc0: 20c9883a add r4,r4,r3 + afc4: a1400115 stw r5,4(r20) + afc8: a5c00215 stw r23,8(r20) + afcc: a0800315 stw r2,12(r20) + afd0: a1000415 stw r4,16(r20) + afd4: 003fb606 br aeb0 <_fpadd_parts+0x1a8> + afd8: 001f883a mov r15,zero + afdc: 0021883a mov r16,zero + afe0: 003f8306 br adf0 <_fpadd_parts+0xe8> + afe4: 018dc83a sub r6,zero,r6 + afe8: 003f6706 br ad88 <_fpadd_parts+0x80> + afec: 00bfff84 movi r2,-2 + aff0: 117faf36 bltu r2,r5,aeb0 <_fpadd_parts+0x1a8> + aff4: 003f9806 br ae58 <_fpadd_parts+0x150> + aff8: 0005883a mov r2,zero + affc: 1189c83a sub r4,r2,r6 + b000: 1105803a cmpltu r2,r2,r4 + b004: 01cbc83a sub r5,zero,r7 + b008: 2885c83a sub r2,r5,r2 + b00c: 01800044 movi r6,1 + b010: a1800115 stw r6,4(r20) + b014: a5c00215 stw r23,8(r20) + b018: a1000315 stw r4,12(r20) + b01c: a0800415 stw r2,16(r20) + b020: 003f8206 br ae2c <_fpadd_parts+0x124> + b024: 203f7226 beq r4,zero,adf0 <_fpadd_parts+0xe8> + b028: 35bff804 addi r22,r6,-32 + b02c: b9af883a add r23,r23,r6 + b030: b0003116 blt r22,zero,b0f8 <_fpadd_parts+0x3f0> + b034: 959ad83a srl r13,r18,r22 + b038: 001d883a mov r14,zero + b03c: 000f883a mov r7,zero + b040: 01000044 movi r4,1 + b044: 0011883a mov r8,zero + b048: b0002516 blt r22,zero,b0e0 <_fpadd_parts+0x3d8> + b04c: 2594983a sll r10,r4,r22 + b050: 0013883a mov r9,zero + b054: 00bfffc4 movi r2,-1 + b058: 4889883a add r4,r9,r2 + b05c: 508b883a add r5,r10,r2 + b060: 224d803a cmpltu r6,r4,r9 + b064: 314b883a add r5,r6,r5 + b068: 8904703a and r2,r17,r4 + b06c: 9146703a and r3,r18,r5 + b070: 10c4b03a or r2,r2,r3 + b074: 10000226 beq r2,zero,b080 <_fpadd_parts+0x378> + b078: 01c00044 movi r7,1 + b07c: 0011883a mov r8,zero + b080: 69e2b03a or r17,r13,r7 + b084: 7224b03a or r18,r14,r8 + b088: 003f5906 br adf0 <_fpadd_parts+0xe8> + b08c: 8407883a add r3,r16,r16 + b090: 008007c4 movi r2,31 + b094: 1185c83a sub r2,r2,r6 + b098: 1886983a sll r3,r3,r2 + b09c: 7996d83a srl r11,r15,r6 + b0a0: 8198d83a srl r12,r16,r6 + b0a4: 1ad6b03a or r11,r3,r11 + b0a8: 003f3e06 br ada4 <_fpadd_parts+0x9c> + b0ac: 2006d07a srli r3,r4,1 + b0b0: 008007c4 movi r2,31 + b0b4: 1185c83a sub r2,r2,r6 + b0b8: 1890d83a srl r8,r3,r2 + b0bc: 218e983a sll r7,r4,r6 + b0c0: 003f3e06 br adbc <_fpadd_parts+0xb4> + b0c4: 113f821e bne r2,r4,aed0 <_fpadd_parts+0x1c8> + b0c8: 28c00117 ldw r3,4(r5) + b0cc: 98800117 ldw r2,4(r19) + b0d0: 10ff7f26 beq r2,r3,aed0 <_fpadd_parts+0x1c8> + b0d4: 04c00074 movhi r19,1 + b0d8: 9cc15804 addi r19,r19,1376 + b0dc: 003f7c06 br aed0 <_fpadd_parts+0x1c8> + b0e0: 2006d07a srli r3,r4,1 + b0e4: 008007c4 movi r2,31 + b0e8: 1185c83a sub r2,r2,r6 + b0ec: 1894d83a srl r10,r3,r2 + b0f0: 2192983a sll r9,r4,r6 + b0f4: 003fd706 br b054 <_fpadd_parts+0x34c> + b0f8: 9487883a add r3,r18,r18 + b0fc: 008007c4 movi r2,31 + b100: 1185c83a sub r2,r2,r6 + b104: 1886983a sll r3,r3,r2 + b108: 899ad83a srl r13,r17,r6 + b10c: 919cd83a srl r14,r18,r6 + b110: 1b5ab03a or r13,r3,r13 + b114: 003fc906 br b03c <_fpadd_parts+0x334> + +0000b118 <__subdf3>: + b118: deffea04 addi sp,sp,-88 + b11c: dcc01415 stw r19,80(sp) + b120: dcc00404 addi r19,sp,16 + b124: 2011883a mov r8,r4 + b128: 2813883a mov r9,r5 + b12c: dc401315 stw r17,76(sp) + b130: d809883a mov r4,sp + b134: 980b883a mov r5,r19 + b138: dc400904 addi r17,sp,36 + b13c: dfc01515 stw ra,84(sp) + b140: da400115 stw r9,4(sp) + b144: d9c00315 stw r7,12(sp) + b148: da000015 stw r8,0(sp) + b14c: d9800215 stw r6,8(sp) + b150: 000c2ec0 call c2ec <__unpack_d> + b154: d9000204 addi r4,sp,8 + b158: 880b883a mov r5,r17 + b15c: 000c2ec0 call c2ec <__unpack_d> + b160: d8800a17 ldw r2,40(sp) + b164: 880b883a mov r5,r17 + b168: 9809883a mov r4,r19 + b16c: d9800e04 addi r6,sp,56 + b170: 1080005c xori r2,r2,1 + b174: d8800a15 stw r2,40(sp) + b178: 000ad080 call ad08 <_fpadd_parts> + b17c: 1009883a mov r4,r2 + b180: 000bfd80 call bfd8 <__pack_d> + b184: dfc01517 ldw ra,84(sp) + b188: dcc01417 ldw r19,80(sp) + b18c: dc401317 ldw r17,76(sp) + b190: dec01604 addi sp,sp,88 + b194: f800283a ret + +0000b198 <__adddf3>: + b198: deffea04 addi sp,sp,-88 + b19c: dcc01415 stw r19,80(sp) + b1a0: dcc00404 addi r19,sp,16 + b1a4: 2011883a mov r8,r4 + b1a8: 2813883a mov r9,r5 + b1ac: dc401315 stw r17,76(sp) + b1b0: d809883a mov r4,sp + b1b4: 980b883a mov r5,r19 + b1b8: dc400904 addi r17,sp,36 + b1bc: dfc01515 stw ra,84(sp) + b1c0: da400115 stw r9,4(sp) + b1c4: d9c00315 stw r7,12(sp) + b1c8: da000015 stw r8,0(sp) + b1cc: d9800215 stw r6,8(sp) + b1d0: 000c2ec0 call c2ec <__unpack_d> + b1d4: d9000204 addi r4,sp,8 + b1d8: 880b883a mov r5,r17 + b1dc: 000c2ec0 call c2ec <__unpack_d> + b1e0: d9800e04 addi r6,sp,56 + b1e4: 9809883a mov r4,r19 + b1e8: 880b883a mov r5,r17 + b1ec: 000ad080 call ad08 <_fpadd_parts> + b1f0: 1009883a mov r4,r2 + b1f4: 000bfd80 call bfd8 <__pack_d> + b1f8: dfc01517 ldw ra,84(sp) + b1fc: dcc01417 ldw r19,80(sp) + b200: dc401317 ldw r17,76(sp) + b204: dec01604 addi sp,sp,88 + b208: f800283a ret + +0000b20c <__muldf3>: + b20c: deffe004 addi sp,sp,-128 + b210: dc401815 stw r17,96(sp) + b214: dc400404 addi r17,sp,16 + b218: 2011883a mov r8,r4 + b21c: 2813883a mov r9,r5 + b220: dc001715 stw r16,92(sp) + b224: d809883a mov r4,sp + b228: 880b883a mov r5,r17 + b22c: dc000904 addi r16,sp,36 + b230: dfc01f15 stw ra,124(sp) + b234: da400115 stw r9,4(sp) + b238: d9c00315 stw r7,12(sp) + b23c: da000015 stw r8,0(sp) + b240: d9800215 stw r6,8(sp) + b244: ddc01e15 stw r23,120(sp) + b248: dd801d15 stw r22,116(sp) + b24c: dd401c15 stw r21,112(sp) + b250: dd001b15 stw r20,108(sp) + b254: dcc01a15 stw r19,104(sp) + b258: dc801915 stw r18,100(sp) + b25c: 000c2ec0 call c2ec <__unpack_d> + b260: d9000204 addi r4,sp,8 + b264: 800b883a mov r5,r16 + b268: 000c2ec0 call c2ec <__unpack_d> + b26c: d9000417 ldw r4,16(sp) + b270: 00800044 movi r2,1 + b274: 1100102e bgeu r2,r4,b2b8 <__muldf3+0xac> + b278: d8c00917 ldw r3,36(sp) + b27c: 10c0062e bgeu r2,r3,b298 <__muldf3+0x8c> + b280: 00800104 movi r2,4 + b284: 20800a26 beq r4,r2,b2b0 <__muldf3+0xa4> + b288: 1880cc26 beq r3,r2,b5bc <__muldf3+0x3b0> + b28c: 00800084 movi r2,2 + b290: 20800926 beq r4,r2,b2b8 <__muldf3+0xac> + b294: 1880191e bne r3,r2,b2fc <__muldf3+0xf0> + b298: d8c00a17 ldw r3,40(sp) + b29c: d8800517 ldw r2,20(sp) + b2a0: 8009883a mov r4,r16 + b2a4: 10c4c03a cmpne r2,r2,r3 + b2a8: d8800a15 stw r2,40(sp) + b2ac: 00000706 br b2cc <__muldf3+0xc0> + b2b0: 00800084 movi r2,2 + b2b4: 1880c326 beq r3,r2,b5c4 <__muldf3+0x3b8> + b2b8: d8800517 ldw r2,20(sp) + b2bc: d8c00a17 ldw r3,40(sp) + b2c0: 8809883a mov r4,r17 + b2c4: 10c4c03a cmpne r2,r2,r3 + b2c8: d8800515 stw r2,20(sp) + b2cc: 000bfd80 call bfd8 <__pack_d> + b2d0: dfc01f17 ldw ra,124(sp) + b2d4: ddc01e17 ldw r23,120(sp) + b2d8: dd801d17 ldw r22,116(sp) + b2dc: dd401c17 ldw r21,112(sp) + b2e0: dd001b17 ldw r20,108(sp) + b2e4: dcc01a17 ldw r19,104(sp) + b2e8: dc801917 ldw r18,100(sp) + b2ec: dc401817 ldw r17,96(sp) + b2f0: dc001717 ldw r16,92(sp) + b2f4: dec02004 addi sp,sp,128 + b2f8: f800283a ret + b2fc: dd800717 ldw r22,28(sp) + b300: dc800c17 ldw r18,48(sp) + b304: 002b883a mov r21,zero + b308: 0023883a mov r17,zero + b30c: a80b883a mov r5,r21 + b310: b00d883a mov r6,r22 + b314: 880f883a mov r7,r17 + b318: ddc00817 ldw r23,32(sp) + b31c: dcc00d17 ldw r19,52(sp) + b320: 9009883a mov r4,r18 + b324: 000be340 call be34 <__muldi3> + b328: 001b883a mov r13,zero + b32c: 680f883a mov r7,r13 + b330: b009883a mov r4,r22 + b334: 000b883a mov r5,zero + b338: 980d883a mov r6,r19 + b33c: b82d883a mov r22,r23 + b340: 002f883a mov r23,zero + b344: db401615 stw r13,88(sp) + b348: d8801315 stw r2,76(sp) + b34c: d8c01415 stw r3,80(sp) + b350: dcc01515 stw r19,84(sp) + b354: 000be340 call be34 <__muldi3> + b358: b00d883a mov r6,r22 + b35c: 000b883a mov r5,zero + b360: 9009883a mov r4,r18 + b364: b80f883a mov r7,r23 + b368: 1021883a mov r16,r2 + b36c: 1823883a mov r17,r3 + b370: 000be340 call be34 <__muldi3> + b374: 8085883a add r2,r16,r2 + b378: 140d803a cmpltu r6,r2,r16 + b37c: 88c7883a add r3,r17,r3 + b380: 30cd883a add r6,r6,r3 + b384: 1029883a mov r20,r2 + b388: 302b883a mov r21,r6 + b38c: da801317 ldw r10,76(sp) + b390: dac01417 ldw r11,80(sp) + b394: db001517 ldw r12,84(sp) + b398: db401617 ldw r13,88(sp) + b39c: 3440612e bgeu r6,r17,b524 <__muldf3+0x318> + b3a0: 0009883a mov r4,zero + b3a4: 5105883a add r2,r10,r4 + b3a8: 128d803a cmpltu r6,r2,r10 + b3ac: 5d07883a add r3,r11,r20 + b3b0: 30cd883a add r6,r6,r3 + b3b4: 0021883a mov r16,zero + b3b8: 04400044 movi r17,1 + b3bc: 1025883a mov r18,r2 + b3c0: 3027883a mov r19,r6 + b3c4: 32c06236 bltu r6,r11,b550 <__muldf3+0x344> + b3c8: 59807a26 beq r11,r6,b5b4 <__muldf3+0x3a8> + b3cc: 680b883a mov r5,r13 + b3d0: b80f883a mov r7,r23 + b3d4: 6009883a mov r4,r12 + b3d8: b00d883a mov r6,r22 + b3dc: 000be340 call be34 <__muldi3> + b3e0: 1009883a mov r4,r2 + b3e4: 000f883a mov r7,zero + b3e8: 1545883a add r2,r2,r21 + b3ec: 1111803a cmpltu r8,r2,r4 + b3f0: 19c7883a add r3,r3,r7 + b3f4: 40c7883a add r3,r8,r3 + b3f8: 88cb883a add r5,r17,r3 + b3fc: d8c00617 ldw r3,24(sp) + b400: 8089883a add r4,r16,r2 + b404: d8800b17 ldw r2,44(sp) + b408: 18c00104 addi r3,r3,4 + b40c: 240d803a cmpltu r6,r4,r16 + b410: 10c7883a add r3,r2,r3 + b414: 2013883a mov r9,r4 + b418: d8800a17 ldw r2,40(sp) + b41c: d9000517 ldw r4,20(sp) + b420: 314d883a add r6,r6,r5 + b424: 3015883a mov r10,r6 + b428: 2088c03a cmpne r4,r4,r2 + b42c: 00880034 movhi r2,8192 + b430: 10bfffc4 addi r2,r2,-1 + b434: d9000f15 stw r4,60(sp) + b438: d8c01015 stw r3,64(sp) + b43c: 1180162e bgeu r2,r6,b498 <__muldf3+0x28c> + b440: 1811883a mov r8,r3 + b444: 101f883a mov r15,r2 + b448: 980497fa slli r2,r19,31 + b44c: 9016d07a srli r11,r18,1 + b450: 500697fa slli r3,r10,31 + b454: 480cd07a srli r6,r9,1 + b458: 500ed07a srli r7,r10,1 + b45c: 12d6b03a or r11,r2,r11 + b460: 00800044 movi r2,1 + b464: 198cb03a or r6,r3,r6 + b468: 4888703a and r4,r9,r2 + b46c: 9818d07a srli r12,r19,1 + b470: 001b883a mov r13,zero + b474: 03a00034 movhi r14,32768 + b478: 3013883a mov r9,r6 + b47c: 3815883a mov r10,r7 + b480: 4091883a add r8,r8,r2 + b484: 20000226 beq r4,zero,b490 <__muldf3+0x284> + b488: 5b64b03a or r18,r11,r13 + b48c: 63a6b03a or r19,r12,r14 + b490: 7abfed36 bltu r15,r10,b448 <__muldf3+0x23c> + b494: da001015 stw r8,64(sp) + b498: 00840034 movhi r2,4096 + b49c: 10bfffc4 addi r2,r2,-1 + b4a0: 12801436 bltu r2,r10,b4f4 <__muldf3+0x2e8> + b4a4: da001017 ldw r8,64(sp) + b4a8: 101f883a mov r15,r2 + b4ac: 4a45883a add r2,r9,r9 + b4b0: 124d803a cmpltu r6,r2,r9 + b4b4: 5287883a add r3,r10,r10 + b4b8: 9497883a add r11,r18,r18 + b4bc: 5c8f803a cmpltu r7,r11,r18 + b4c0: 9cd9883a add r12,r19,r19 + b4c4: 01000044 movi r4,1 + b4c8: 30cd883a add r6,r6,r3 + b4cc: 3b0f883a add r7,r7,r12 + b4d0: 423fffc4 addi r8,r8,-1 + b4d4: 1013883a mov r9,r2 + b4d8: 3015883a mov r10,r6 + b4dc: 111ab03a or r13,r2,r4 + b4e0: 98003016 blt r19,zero,b5a4 <__muldf3+0x398> + b4e4: 5825883a mov r18,r11 + b4e8: 3827883a mov r19,r7 + b4ec: 7abfef2e bgeu r15,r10,b4ac <__muldf3+0x2a0> + b4f0: da001015 stw r8,64(sp) + b4f4: 00803fc4 movi r2,255 + b4f8: 488e703a and r7,r9,r2 + b4fc: 00802004 movi r2,128 + b500: 0007883a mov r3,zero + b504: 0011883a mov r8,zero + b508: 38801826 beq r7,r2,b56c <__muldf3+0x360> + b50c: 008000c4 movi r2,3 + b510: d9000e04 addi r4,sp,56 + b514: da801215 stw r10,72(sp) + b518: d8800e15 stw r2,56(sp) + b51c: da401115 stw r9,68(sp) + b520: 003f6a06 br b2cc <__muldf3+0xc0> + b524: 89802126 beq r17,r6,b5ac <__muldf3+0x3a0> + b528: 0009883a mov r4,zero + b52c: 5105883a add r2,r10,r4 + b530: 128d803a cmpltu r6,r2,r10 + b534: 5d07883a add r3,r11,r20 + b538: 30cd883a add r6,r6,r3 + b53c: 0021883a mov r16,zero + b540: 0023883a mov r17,zero + b544: 1025883a mov r18,r2 + b548: 3027883a mov r19,r6 + b54c: 32ff9e2e bgeu r6,r11,b3c8 <__muldf3+0x1bc> + b550: 00800044 movi r2,1 + b554: 8089883a add r4,r16,r2 + b558: 240d803a cmpltu r6,r4,r16 + b55c: 344d883a add r6,r6,r17 + b560: 2021883a mov r16,r4 + b564: 3023883a mov r17,r6 + b568: 003f9806 br b3cc <__muldf3+0x1c0> + b56c: 403fe71e bne r8,zero,b50c <__muldf3+0x300> + b570: 01004004 movi r4,256 + b574: 4904703a and r2,r9,r4 + b578: 10c4b03a or r2,r2,r3 + b57c: 103fe31e bne r2,zero,b50c <__muldf3+0x300> + b580: 94c4b03a or r2,r18,r19 + b584: 103fe126 beq r2,zero,b50c <__muldf3+0x300> + b588: 49c5883a add r2,r9,r7 + b58c: 1251803a cmpltu r8,r2,r9 + b590: 4291883a add r8,r8,r10 + b594: 013fc004 movi r4,-256 + b598: 1112703a and r9,r2,r4 + b59c: 4015883a mov r10,r8 + b5a0: 003fda06 br b50c <__muldf3+0x300> + b5a4: 6813883a mov r9,r13 + b5a8: 003fce06 br b4e4 <__muldf3+0x2d8> + b5ac: 143f7c36 bltu r2,r16,b3a0 <__muldf3+0x194> + b5b0: 003fdd06 br b528 <__muldf3+0x31c> + b5b4: 12bf852e bgeu r2,r10,b3cc <__muldf3+0x1c0> + b5b8: 003fe506 br b550 <__muldf3+0x344> + b5bc: 00800084 movi r2,2 + b5c0: 20bf351e bne r4,r2,b298 <__muldf3+0x8c> + b5c4: 01000074 movhi r4,1 + b5c8: 21015804 addi r4,r4,1376 + b5cc: 003f3f06 br b2cc <__muldf3+0xc0> + +0000b5d0 <__divdf3>: + b5d0: deffed04 addi sp,sp,-76 + b5d4: dcc01115 stw r19,68(sp) + b5d8: dcc00404 addi r19,sp,16 + b5dc: 2011883a mov r8,r4 + b5e0: 2813883a mov r9,r5 + b5e4: dc000e15 stw r16,56(sp) + b5e8: d809883a mov r4,sp + b5ec: 980b883a mov r5,r19 + b5f0: dc000904 addi r16,sp,36 + b5f4: dfc01215 stw ra,72(sp) + b5f8: da400115 stw r9,4(sp) + b5fc: d9c00315 stw r7,12(sp) + b600: da000015 stw r8,0(sp) + b604: d9800215 stw r6,8(sp) + b608: dc801015 stw r18,64(sp) + b60c: dc400f15 stw r17,60(sp) + b610: 000c2ec0 call c2ec <__unpack_d> + b614: d9000204 addi r4,sp,8 + b618: 800b883a mov r5,r16 + b61c: 000c2ec0 call c2ec <__unpack_d> + b620: d9000417 ldw r4,16(sp) + b624: 00800044 movi r2,1 + b628: 11000b2e bgeu r2,r4,b658 <__divdf3+0x88> + b62c: d9400917 ldw r5,36(sp) + b630: 1140762e bgeu r2,r5,b80c <__divdf3+0x23c> + b634: d8800517 ldw r2,20(sp) + b638: d8c00a17 ldw r3,40(sp) + b63c: 01800104 movi r6,4 + b640: 10c4f03a xor r2,r2,r3 + b644: d8800515 stw r2,20(sp) + b648: 21800226 beq r4,r6,b654 <__divdf3+0x84> + b64c: 00800084 movi r2,2 + b650: 2080141e bne r4,r2,b6a4 <__divdf3+0xd4> + b654: 29000926 beq r5,r4,b67c <__divdf3+0xac> + b658: 9809883a mov r4,r19 + b65c: 000bfd80 call bfd8 <__pack_d> + b660: dfc01217 ldw ra,72(sp) + b664: dcc01117 ldw r19,68(sp) + b668: dc801017 ldw r18,64(sp) + b66c: dc400f17 ldw r17,60(sp) + b670: dc000e17 ldw r16,56(sp) + b674: dec01304 addi sp,sp,76 + b678: f800283a ret + b67c: 01000074 movhi r4,1 + b680: 21015804 addi r4,r4,1376 + b684: 000bfd80 call bfd8 <__pack_d> + b688: dfc01217 ldw ra,72(sp) + b68c: dcc01117 ldw r19,68(sp) + b690: dc801017 ldw r18,64(sp) + b694: dc400f17 ldw r17,60(sp) + b698: dc000e17 ldw r16,56(sp) + b69c: dec01304 addi sp,sp,76 + b6a0: f800283a ret + b6a4: 29805b26 beq r5,r6,b814 <__divdf3+0x244> + b6a8: 28802d26 beq r5,r2,b760 <__divdf3+0x190> + b6ac: d8c00617 ldw r3,24(sp) + b6b0: d8800b17 ldw r2,44(sp) + b6b4: d9c00817 ldw r7,32(sp) + b6b8: dc400d17 ldw r17,52(sp) + b6bc: 188bc83a sub r5,r3,r2 + b6c0: d9800717 ldw r6,28(sp) + b6c4: dc000c17 ldw r16,48(sp) + b6c8: d9400615 stw r5,24(sp) + b6cc: 3c403836 bltu r7,r17,b7b0 <__divdf3+0x1e0> + b6d0: 89c03626 beq r17,r7,b7ac <__divdf3+0x1dc> + b6d4: 0015883a mov r10,zero + b6d8: 001d883a mov r14,zero + b6dc: 02c40034 movhi r11,4096 + b6e0: 001f883a mov r15,zero + b6e4: 003f883a mov ra,zero + b6e8: 04800f44 movi r18,61 + b6ec: 00000f06 br b72c <__divdf3+0x15c> + b6f0: 601d883a mov r14,r12 + b6f4: 681f883a mov r15,r13 + b6f8: 400d883a mov r6,r8 + b6fc: 100f883a mov r7,r2 + b700: 3191883a add r8,r6,r6 + b704: 5808d07a srli r4,r11,1 + b708: 4185803a cmpltu r2,r8,r6 + b70c: 39d3883a add r9,r7,r7 + b710: 28c6b03a or r3,r5,r3 + b714: 1245883a add r2,r2,r9 + b718: 1815883a mov r10,r3 + b71c: 2017883a mov r11,r4 + b720: 400d883a mov r6,r8 + b724: 100f883a mov r7,r2 + b728: fc801726 beq ra,r18,b788 <__divdf3+0x1b8> + b72c: 580a97fa slli r5,r11,31 + b730: 5006d07a srli r3,r10,1 + b734: ffc00044 addi ra,ra,1 + b738: 3c7ff136 bltu r7,r17,b700 <__divdf3+0x130> + b73c: 3411c83a sub r8,r6,r16 + b740: 3205803a cmpltu r2,r6,r8 + b744: 3c53c83a sub r9,r7,r17 + b748: 7298b03a or r12,r14,r10 + b74c: 7adab03a or r13,r15,r11 + b750: 4885c83a sub r2,r9,r2 + b754: 89ffe61e bne r17,r7,b6f0 <__divdf3+0x120> + b758: 343fe936 bltu r6,r16,b700 <__divdf3+0x130> + b75c: 003fe406 br b6f0 <__divdf3+0x120> + b760: 9809883a mov r4,r19 + b764: d9800415 stw r6,16(sp) + b768: 000bfd80 call bfd8 <__pack_d> + b76c: dfc01217 ldw ra,72(sp) + b770: dcc01117 ldw r19,68(sp) + b774: dc801017 ldw r18,64(sp) + b778: dc400f17 ldw r17,60(sp) + b77c: dc000e17 ldw r16,56(sp) + b780: dec01304 addi sp,sp,76 + b784: f800283a ret + b788: 00803fc4 movi r2,255 + b78c: 7090703a and r8,r14,r2 + b790: 00802004 movi r2,128 + b794: 0007883a mov r3,zero + b798: 0013883a mov r9,zero + b79c: 40800d26 beq r8,r2,b7d4 <__divdf3+0x204> + b7a0: dbc00815 stw r15,32(sp) + b7a4: db800715 stw r14,28(sp) + b7a8: 003fab06 br b658 <__divdf3+0x88> + b7ac: 343fc92e bgeu r6,r16,b6d4 <__divdf3+0x104> + b7b0: 3185883a add r2,r6,r6 + b7b4: 1189803a cmpltu r4,r2,r6 + b7b8: 39c7883a add r3,r7,r7 + b7bc: 20c9883a add r4,r4,r3 + b7c0: 297fffc4 addi r5,r5,-1 + b7c4: 100d883a mov r6,r2 + b7c8: 200f883a mov r7,r4 + b7cc: d9400615 stw r5,24(sp) + b7d0: 003fc006 br b6d4 <__divdf3+0x104> + b7d4: 483ff21e bne r9,zero,b7a0 <__divdf3+0x1d0> + b7d8: 01004004 movi r4,256 + b7dc: 7104703a and r2,r14,r4 + b7e0: 10c4b03a or r2,r2,r3 + b7e4: 103fee1e bne r2,zero,b7a0 <__divdf3+0x1d0> + b7e8: 31c4b03a or r2,r6,r7 + b7ec: 103fec26 beq r2,zero,b7a0 <__divdf3+0x1d0> + b7f0: 7205883a add r2,r14,r8 + b7f4: 1391803a cmpltu r8,r2,r14 + b7f8: 43d1883a add r8,r8,r15 + b7fc: 013fc004 movi r4,-256 + b800: 111c703a and r14,r2,r4 + b804: 401f883a mov r15,r8 + b808: 003fe506 br b7a0 <__divdf3+0x1d0> + b80c: 8009883a mov r4,r16 + b810: 003f9206 br b65c <__divdf3+0x8c> + b814: 9809883a mov r4,r19 + b818: d8000715 stw zero,28(sp) + b81c: d8000815 stw zero,32(sp) + b820: d8000615 stw zero,24(sp) + b824: 003f8d06 br b65c <__divdf3+0x8c> + +0000b828 <__eqdf2>: + b828: deffef04 addi sp,sp,-68 + b82c: dc400f15 stw r17,60(sp) + b830: dc400404 addi r17,sp,16 + b834: 2005883a mov r2,r4 + b838: 2807883a mov r3,r5 + b83c: dc000e15 stw r16,56(sp) + b840: d809883a mov r4,sp + b844: 880b883a mov r5,r17 + b848: dc000904 addi r16,sp,36 + b84c: d8c00115 stw r3,4(sp) + b850: d8800015 stw r2,0(sp) + b854: d9800215 stw r6,8(sp) + b858: dfc01015 stw ra,64(sp) + b85c: d9c00315 stw r7,12(sp) + b860: 000c2ec0 call c2ec <__unpack_d> + b864: d9000204 addi r4,sp,8 + b868: 800b883a mov r5,r16 + b86c: 000c2ec0 call c2ec <__unpack_d> + b870: d8800417 ldw r2,16(sp) + b874: 00c00044 movi r3,1 + b878: 180d883a mov r6,r3 + b87c: 1880062e bgeu r3,r2,b898 <__eqdf2+0x70> + b880: d8800917 ldw r2,36(sp) + b884: 8809883a mov r4,r17 + b888: 800b883a mov r5,r16 + b88c: 1880022e bgeu r3,r2,b898 <__eqdf2+0x70> + b890: 000c4240 call c424 <__fpcmp_parts_d> + b894: 100d883a mov r6,r2 + b898: 3005883a mov r2,r6 + b89c: dfc01017 ldw ra,64(sp) + b8a0: dc400f17 ldw r17,60(sp) + b8a4: dc000e17 ldw r16,56(sp) + b8a8: dec01104 addi sp,sp,68 + b8ac: f800283a ret + +0000b8b0 <__nedf2>: + b8b0: deffef04 addi sp,sp,-68 + b8b4: dc400f15 stw r17,60(sp) + b8b8: dc400404 addi r17,sp,16 + b8bc: 2005883a mov r2,r4 + b8c0: 2807883a mov r3,r5 + b8c4: dc000e15 stw r16,56(sp) + b8c8: d809883a mov r4,sp + b8cc: 880b883a mov r5,r17 + b8d0: dc000904 addi r16,sp,36 + b8d4: d8c00115 stw r3,4(sp) + b8d8: d8800015 stw r2,0(sp) + b8dc: d9800215 stw r6,8(sp) + b8e0: dfc01015 stw ra,64(sp) + b8e4: d9c00315 stw r7,12(sp) + b8e8: 000c2ec0 call c2ec <__unpack_d> + b8ec: d9000204 addi r4,sp,8 + b8f0: 800b883a mov r5,r16 + b8f4: 000c2ec0 call c2ec <__unpack_d> + b8f8: d8800417 ldw r2,16(sp) + b8fc: 00c00044 movi r3,1 + b900: 180d883a mov r6,r3 + b904: 1880062e bgeu r3,r2,b920 <__nedf2+0x70> + b908: d8800917 ldw r2,36(sp) + b90c: 8809883a mov r4,r17 + b910: 800b883a mov r5,r16 + b914: 1880022e bgeu r3,r2,b920 <__nedf2+0x70> + b918: 000c4240 call c424 <__fpcmp_parts_d> + b91c: 100d883a mov r6,r2 + b920: 3005883a mov r2,r6 + b924: dfc01017 ldw ra,64(sp) + b928: dc400f17 ldw r17,60(sp) + b92c: dc000e17 ldw r16,56(sp) + b930: dec01104 addi sp,sp,68 + b934: f800283a ret + +0000b938 <__gtdf2>: + b938: deffef04 addi sp,sp,-68 + b93c: dc400f15 stw r17,60(sp) + b940: dc400404 addi r17,sp,16 + b944: 2005883a mov r2,r4 + b948: 2807883a mov r3,r5 + b94c: dc000e15 stw r16,56(sp) + b950: d809883a mov r4,sp + b954: 880b883a mov r5,r17 + b958: dc000904 addi r16,sp,36 + b95c: d8c00115 stw r3,4(sp) + b960: d8800015 stw r2,0(sp) + b964: d9800215 stw r6,8(sp) + b968: dfc01015 stw ra,64(sp) + b96c: d9c00315 stw r7,12(sp) + b970: 000c2ec0 call c2ec <__unpack_d> + b974: d9000204 addi r4,sp,8 + b978: 800b883a mov r5,r16 + b97c: 000c2ec0 call c2ec <__unpack_d> + b980: d8800417 ldw r2,16(sp) + b984: 00c00044 movi r3,1 + b988: 01bfffc4 movi r6,-1 + b98c: 1880062e bgeu r3,r2,b9a8 <__gtdf2+0x70> + b990: d8800917 ldw r2,36(sp) + b994: 8809883a mov r4,r17 + b998: 800b883a mov r5,r16 + b99c: 1880022e bgeu r3,r2,b9a8 <__gtdf2+0x70> + b9a0: 000c4240 call c424 <__fpcmp_parts_d> + b9a4: 100d883a mov r6,r2 + b9a8: 3005883a mov r2,r6 + b9ac: dfc01017 ldw ra,64(sp) + b9b0: dc400f17 ldw r17,60(sp) + b9b4: dc000e17 ldw r16,56(sp) + b9b8: dec01104 addi sp,sp,68 + b9bc: f800283a ret + +0000b9c0 <__gedf2>: + b9c0: deffef04 addi sp,sp,-68 + b9c4: dc400f15 stw r17,60(sp) + b9c8: dc400404 addi r17,sp,16 + b9cc: 2005883a mov r2,r4 + b9d0: 2807883a mov r3,r5 + b9d4: dc000e15 stw r16,56(sp) + b9d8: d809883a mov r4,sp + b9dc: 880b883a mov r5,r17 + b9e0: dc000904 addi r16,sp,36 + b9e4: d8c00115 stw r3,4(sp) + b9e8: d8800015 stw r2,0(sp) + b9ec: d9800215 stw r6,8(sp) + b9f0: dfc01015 stw ra,64(sp) + b9f4: d9c00315 stw r7,12(sp) + b9f8: 000c2ec0 call c2ec <__unpack_d> + b9fc: d9000204 addi r4,sp,8 + ba00: 800b883a mov r5,r16 + ba04: 000c2ec0 call c2ec <__unpack_d> + ba08: d8800417 ldw r2,16(sp) + ba0c: 00c00044 movi r3,1 + ba10: 01bfffc4 movi r6,-1 + ba14: 1880062e bgeu r3,r2,ba30 <__gedf2+0x70> + ba18: d8800917 ldw r2,36(sp) + ba1c: 8809883a mov r4,r17 + ba20: 800b883a mov r5,r16 + ba24: 1880022e bgeu r3,r2,ba30 <__gedf2+0x70> + ba28: 000c4240 call c424 <__fpcmp_parts_d> + ba2c: 100d883a mov r6,r2 + ba30: 3005883a mov r2,r6 + ba34: dfc01017 ldw ra,64(sp) + ba38: dc400f17 ldw r17,60(sp) + ba3c: dc000e17 ldw r16,56(sp) + ba40: dec01104 addi sp,sp,68 + ba44: f800283a ret + +0000ba48 <__ltdf2>: + ba48: deffef04 addi sp,sp,-68 + ba4c: dc400f15 stw r17,60(sp) + ba50: dc400404 addi r17,sp,16 + ba54: 2005883a mov r2,r4 + ba58: 2807883a mov r3,r5 + ba5c: dc000e15 stw r16,56(sp) + ba60: d809883a mov r4,sp + ba64: 880b883a mov r5,r17 + ba68: dc000904 addi r16,sp,36 + ba6c: d8c00115 stw r3,4(sp) + ba70: d8800015 stw r2,0(sp) + ba74: d9800215 stw r6,8(sp) + ba78: dfc01015 stw ra,64(sp) + ba7c: d9c00315 stw r7,12(sp) + ba80: 000c2ec0 call c2ec <__unpack_d> + ba84: d9000204 addi r4,sp,8 + ba88: 800b883a mov r5,r16 + ba8c: 000c2ec0 call c2ec <__unpack_d> + ba90: d8800417 ldw r2,16(sp) + ba94: 00c00044 movi r3,1 + ba98: 180d883a mov r6,r3 + ba9c: 1880062e bgeu r3,r2,bab8 <__ltdf2+0x70> + baa0: d8800917 ldw r2,36(sp) + baa4: 8809883a mov r4,r17 + baa8: 800b883a mov r5,r16 + baac: 1880022e bgeu r3,r2,bab8 <__ltdf2+0x70> + bab0: 000c4240 call c424 <__fpcmp_parts_d> + bab4: 100d883a mov r6,r2 + bab8: 3005883a mov r2,r6 + babc: dfc01017 ldw ra,64(sp) + bac0: dc400f17 ldw r17,60(sp) + bac4: dc000e17 ldw r16,56(sp) + bac8: dec01104 addi sp,sp,68 + bacc: f800283a ret + +0000bad0 <__floatsidf>: + bad0: 2006d7fa srli r3,r4,31 + bad4: defff604 addi sp,sp,-40 + bad8: 008000c4 movi r2,3 + badc: dfc00915 stw ra,36(sp) + bae0: dcc00815 stw r19,32(sp) + bae4: dc800715 stw r18,28(sp) + bae8: dc400615 stw r17,24(sp) + baec: dc000515 stw r16,20(sp) + baf0: d8800015 stw r2,0(sp) + baf4: d8c00115 stw r3,4(sp) + baf8: 20000f1e bne r4,zero,bb38 <__floatsidf+0x68> + bafc: 00800084 movi r2,2 + bb00: d8800015 stw r2,0(sp) + bb04: d809883a mov r4,sp + bb08: 000bfd80 call bfd8 <__pack_d> + bb0c: 1009883a mov r4,r2 + bb10: 180b883a mov r5,r3 + bb14: 2005883a mov r2,r4 + bb18: 2807883a mov r3,r5 + bb1c: dfc00917 ldw ra,36(sp) + bb20: dcc00817 ldw r19,32(sp) + bb24: dc800717 ldw r18,28(sp) + bb28: dc400617 ldw r17,24(sp) + bb2c: dc000517 ldw r16,20(sp) + bb30: dec00a04 addi sp,sp,40 + bb34: f800283a ret + bb38: 00800f04 movi r2,60 + bb3c: 1807003a cmpeq r3,r3,zero + bb40: d8800215 stw r2,8(sp) + bb44: 18001126 beq r3,zero,bb8c <__floatsidf+0xbc> + bb48: 0027883a mov r19,zero + bb4c: 2025883a mov r18,r4 + bb50: d9000315 stw r4,12(sp) + bb54: dcc00415 stw r19,16(sp) + bb58: 000bf580 call bf58 <__clzsi2> + bb5c: 11000744 addi r4,r2,29 + bb60: 013fe80e bge zero,r4,bb04 <__floatsidf+0x34> + bb64: 10bfff44 addi r2,r2,-3 + bb68: 10000c16 blt r2,zero,bb9c <__floatsidf+0xcc> + bb6c: 90a2983a sll r17,r18,r2 + bb70: 0021883a mov r16,zero + bb74: d8800217 ldw r2,8(sp) + bb78: dc400415 stw r17,16(sp) + bb7c: dc000315 stw r16,12(sp) + bb80: 1105c83a sub r2,r2,r4 + bb84: d8800215 stw r2,8(sp) + bb88: 003fde06 br bb04 <__floatsidf+0x34> + bb8c: 00a00034 movhi r2,32768 + bb90: 20800a26 beq r4,r2,bbbc <__floatsidf+0xec> + bb94: 0109c83a sub r4,zero,r4 + bb98: 003feb06 br bb48 <__floatsidf+0x78> + bb9c: 9006d07a srli r3,r18,1 + bba0: 008007c4 movi r2,31 + bba4: 1105c83a sub r2,r2,r4 + bba8: 1886d83a srl r3,r3,r2 + bbac: 9922983a sll r17,r19,r4 + bbb0: 9120983a sll r16,r18,r4 + bbb4: 1c62b03a or r17,r3,r17 + bbb8: 003fee06 br bb74 <__floatsidf+0xa4> + bbbc: 0009883a mov r4,zero + bbc0: 01707834 movhi r5,49632 + bbc4: 003fd306 br bb14 <__floatsidf+0x44> + +0000bbc8 <__fixdfsi>: + bbc8: defff804 addi sp,sp,-32 + bbcc: 2005883a mov r2,r4 + bbd0: 2807883a mov r3,r5 + bbd4: d809883a mov r4,sp + bbd8: d9400204 addi r5,sp,8 + bbdc: d8c00115 stw r3,4(sp) + bbe0: d8800015 stw r2,0(sp) + bbe4: dfc00715 stw ra,28(sp) + bbe8: 000c2ec0 call c2ec <__unpack_d> + bbec: d8c00217 ldw r3,8(sp) + bbf0: 00800084 movi r2,2 + bbf4: 1880051e bne r3,r2,bc0c <__fixdfsi+0x44> + bbf8: 0007883a mov r3,zero + bbfc: 1805883a mov r2,r3 + bc00: dfc00717 ldw ra,28(sp) + bc04: dec00804 addi sp,sp,32 + bc08: f800283a ret + bc0c: 00800044 movi r2,1 + bc10: 10fff92e bgeu r2,r3,bbf8 <__fixdfsi+0x30> + bc14: 00800104 movi r2,4 + bc18: 18800426 beq r3,r2,bc2c <__fixdfsi+0x64> + bc1c: d8c00417 ldw r3,16(sp) + bc20: 183ff516 blt r3,zero,bbf8 <__fixdfsi+0x30> + bc24: 00800784 movi r2,30 + bc28: 10c0080e bge r2,r3,bc4c <__fixdfsi+0x84> + bc2c: d8800317 ldw r2,12(sp) + bc30: 1000121e bne r2,zero,bc7c <__fixdfsi+0xb4> + bc34: 00e00034 movhi r3,32768 + bc38: 18ffffc4 addi r3,r3,-1 + bc3c: 1805883a mov r2,r3 + bc40: dfc00717 ldw ra,28(sp) + bc44: dec00804 addi sp,sp,32 + bc48: f800283a ret + bc4c: 00800f04 movi r2,60 + bc50: 10d1c83a sub r8,r2,r3 + bc54: 40bff804 addi r2,r8,-32 + bc58: d9800517 ldw r6,20(sp) + bc5c: d9c00617 ldw r7,24(sp) + bc60: 10000816 blt r2,zero,bc84 <__fixdfsi+0xbc> + bc64: 3888d83a srl r4,r7,r2 + bc68: d8800317 ldw r2,12(sp) + bc6c: 2007883a mov r3,r4 + bc70: 103fe226 beq r2,zero,bbfc <__fixdfsi+0x34> + bc74: 0107c83a sub r3,zero,r4 + bc78: 003fe006 br bbfc <__fixdfsi+0x34> + bc7c: 00e00034 movhi r3,32768 + bc80: 003fde06 br bbfc <__fixdfsi+0x34> + bc84: 39c7883a add r3,r7,r7 + bc88: 008007c4 movi r2,31 + bc8c: 1205c83a sub r2,r2,r8 + bc90: 1886983a sll r3,r3,r2 + bc94: 3208d83a srl r4,r6,r8 + bc98: 1908b03a or r4,r3,r4 + bc9c: 003ff206 br bc68 <__fixdfsi+0xa0> + +0000bca0 <__floatunsidf>: + bca0: defff204 addi sp,sp,-56 + bca4: dfc00d15 stw ra,52(sp) + bca8: ddc00c15 stw r23,48(sp) + bcac: dd800b15 stw r22,44(sp) + bcb0: dd400a15 stw r21,40(sp) + bcb4: dd000915 stw r20,36(sp) + bcb8: dcc00815 stw r19,32(sp) + bcbc: dc800715 stw r18,28(sp) + bcc0: dc400615 stw r17,24(sp) + bcc4: dc000515 stw r16,20(sp) + bcc8: d8000115 stw zero,4(sp) + bccc: 20000f1e bne r4,zero,bd0c <__floatunsidf+0x6c> + bcd0: 00800084 movi r2,2 + bcd4: d8800015 stw r2,0(sp) + bcd8: d809883a mov r4,sp + bcdc: 000bfd80 call bfd8 <__pack_d> + bce0: dfc00d17 ldw ra,52(sp) + bce4: ddc00c17 ldw r23,48(sp) + bce8: dd800b17 ldw r22,44(sp) + bcec: dd400a17 ldw r21,40(sp) + bcf0: dd000917 ldw r20,36(sp) + bcf4: dcc00817 ldw r19,32(sp) + bcf8: dc800717 ldw r18,28(sp) + bcfc: dc400617 ldw r17,24(sp) + bd00: dc000517 ldw r16,20(sp) + bd04: dec00e04 addi sp,sp,56 + bd08: f800283a ret + bd0c: 008000c4 movi r2,3 + bd10: 00c00f04 movi r3,60 + bd14: 002f883a mov r23,zero + bd18: 202d883a mov r22,r4 + bd1c: d8800015 stw r2,0(sp) + bd20: d8c00215 stw r3,8(sp) + bd24: d9000315 stw r4,12(sp) + bd28: ddc00415 stw r23,16(sp) + bd2c: 000bf580 call bf58 <__clzsi2> + bd30: 12400744 addi r9,r2,29 + bd34: 48000b16 blt r9,zero,bd64 <__floatunsidf+0xc4> + bd38: 483fe726 beq r9,zero,bcd8 <__floatunsidf+0x38> + bd3c: 10bfff44 addi r2,r2,-3 + bd40: 10002e16 blt r2,zero,bdfc <__floatunsidf+0x15c> + bd44: b0a2983a sll r17,r22,r2 + bd48: 0021883a mov r16,zero + bd4c: d8800217 ldw r2,8(sp) + bd50: dc400415 stw r17,16(sp) + bd54: dc000315 stw r16,12(sp) + bd58: 1245c83a sub r2,r2,r9 + bd5c: d8800215 stw r2,8(sp) + bd60: 003fdd06 br bcd8 <__floatunsidf+0x38> + bd64: 0255c83a sub r10,zero,r9 + bd68: 51bff804 addi r6,r10,-32 + bd6c: 30001b16 blt r6,zero,bddc <__floatunsidf+0x13c> + bd70: b9a8d83a srl r20,r23,r6 + bd74: 002b883a mov r21,zero + bd78: 000f883a mov r7,zero + bd7c: 01000044 movi r4,1 + bd80: 0011883a mov r8,zero + bd84: 30002516 blt r6,zero,be1c <__floatunsidf+0x17c> + bd88: 21a6983a sll r19,r4,r6 + bd8c: 0025883a mov r18,zero + bd90: 00bfffc4 movi r2,-1 + bd94: 9089883a add r4,r18,r2 + bd98: 988b883a add r5,r19,r2 + bd9c: 248d803a cmpltu r6,r4,r18 + bda0: 314b883a add r5,r6,r5 + bda4: b104703a and r2,r22,r4 + bda8: b946703a and r3,r23,r5 + bdac: 10c4b03a or r2,r2,r3 + bdb0: 10000226 beq r2,zero,bdbc <__floatunsidf+0x11c> + bdb4: 01c00044 movi r7,1 + bdb8: 0011883a mov r8,zero + bdbc: d9000217 ldw r4,8(sp) + bdc0: a1c4b03a or r2,r20,r7 + bdc4: aa06b03a or r3,r21,r8 + bdc8: 2249c83a sub r4,r4,r9 + bdcc: d8c00415 stw r3,16(sp) + bdd0: d9000215 stw r4,8(sp) + bdd4: d8800315 stw r2,12(sp) + bdd8: 003fbf06 br bcd8 <__floatunsidf+0x38> + bddc: bdc7883a add r3,r23,r23 + bde0: 008007c4 movi r2,31 + bde4: 1285c83a sub r2,r2,r10 + bde8: 1886983a sll r3,r3,r2 + bdec: b2a8d83a srl r20,r22,r10 + bdf0: baaad83a srl r21,r23,r10 + bdf4: 1d28b03a or r20,r3,r20 + bdf8: 003fdf06 br bd78 <__floatunsidf+0xd8> + bdfc: b006d07a srli r3,r22,1 + be00: 008007c4 movi r2,31 + be04: 1245c83a sub r2,r2,r9 + be08: 1886d83a srl r3,r3,r2 + be0c: ba62983a sll r17,r23,r9 + be10: b260983a sll r16,r22,r9 + be14: 1c62b03a or r17,r3,r17 + be18: 003fcc06 br bd4c <__floatunsidf+0xac> + be1c: 2006d07a srli r3,r4,1 + be20: 008007c4 movi r2,31 + be24: 1285c83a sub r2,r2,r10 + be28: 18a6d83a srl r19,r3,r2 + be2c: 22a4983a sll r18,r4,r10 + be30: 003fd706 br bd90 <__floatunsidf+0xf0> + +0000be34 <__muldi3>: + be34: defff204 addi sp,sp,-56 + be38: df000c15 stw fp,48(sp) + be3c: 3038d43a srli fp,r6,16 + be40: dd000815 stw r20,32(sp) + be44: dc400515 stw r17,20(sp) + be48: 2028d43a srli r20,r4,16 + be4c: 247fffcc andi r17,r4,65535 + be50: dc000415 stw r16,16(sp) + be54: 343fffcc andi r16,r6,65535 + be58: dcc00715 stw r19,28(sp) + be5c: d9000015 stw r4,0(sp) + be60: 2827883a mov r19,r5 + be64: 8809883a mov r4,r17 + be68: d9400115 stw r5,4(sp) + be6c: 800b883a mov r5,r16 + be70: d9800215 stw r6,8(sp) + be74: dfc00d15 stw ra,52(sp) + be78: d9c00315 stw r7,12(sp) + be7c: dd800a15 stw r22,40(sp) + be80: dd400915 stw r21,36(sp) + be84: 302d883a mov r22,r6 + be88: ddc00b15 stw r23,44(sp) + be8c: dc800615 stw r18,24(sp) + be90: 0002c240 call 2c24 <__mulsi3> + be94: 8809883a mov r4,r17 + be98: e00b883a mov r5,fp + be9c: 102b883a mov r21,r2 + bea0: 0002c240 call 2c24 <__mulsi3> + bea4: 800b883a mov r5,r16 + bea8: a009883a mov r4,r20 + beac: 1023883a mov r17,r2 + beb0: 0002c240 call 2c24 <__mulsi3> + beb4: a009883a mov r4,r20 + beb8: e00b883a mov r5,fp + bebc: 1021883a mov r16,r2 + bec0: 0002c240 call 2c24 <__mulsi3> + bec4: a8ffffcc andi r3,r21,65535 + bec8: a82ad43a srli r21,r21,16 + becc: 8c23883a add r17,r17,r16 + bed0: 1011883a mov r8,r2 + bed4: ac6b883a add r21,r21,r17 + bed8: a804943a slli r2,r21,16 + bedc: b009883a mov r4,r22 + bee0: 980b883a mov r5,r19 + bee4: 10c7883a add r3,r2,r3 + bee8: a812d43a srli r9,r21,16 + beec: 180d883a mov r6,r3 + bef0: ac00022e bgeu r21,r16,befc <__muldi3+0xc8> + bef4: 00800074 movhi r2,1 + bef8: 4091883a add r8,r8,r2 + befc: 4267883a add r19,r8,r9 + bf00: 302d883a mov r22,r6 + bf04: 0002c240 call 2c24 <__mulsi3> + bf08: d9400317 ldw r5,12(sp) + bf0c: d9000017 ldw r4,0(sp) + bf10: 1023883a mov r17,r2 + bf14: 0002c240 call 2c24 <__mulsi3> + bf18: 14cb883a add r5,r2,r19 + bf1c: 894b883a add r5,r17,r5 + bf20: b005883a mov r2,r22 + bf24: 2807883a mov r3,r5 + bf28: dfc00d17 ldw ra,52(sp) + bf2c: df000c17 ldw fp,48(sp) + bf30: ddc00b17 ldw r23,44(sp) + bf34: dd800a17 ldw r22,40(sp) + bf38: dd400917 ldw r21,36(sp) + bf3c: dd000817 ldw r20,32(sp) + bf40: dcc00717 ldw r19,28(sp) + bf44: dc800617 ldw r18,24(sp) + bf48: dc400517 ldw r17,20(sp) + bf4c: dc000417 ldw r16,16(sp) + bf50: dec00e04 addi sp,sp,56 + bf54: f800283a ret + +0000bf58 <__clzsi2>: + bf58: 00bfffd4 movui r2,65535 + bf5c: 11000e36 bltu r2,r4,bf98 <__clzsi2+0x40> + bf60: 00803fc4 movi r2,255 + bf64: 01400204 movi r5,8 + bf68: 0007883a mov r3,zero + bf6c: 11001036 bltu r2,r4,bfb0 <__clzsi2+0x58> + bf70: 000b883a mov r5,zero + bf74: 20c6d83a srl r3,r4,r3 + bf78: 00800074 movhi r2,1 + bf7c: 10815d04 addi r2,r2,1396 + bf80: 1887883a add r3,r3,r2 + bf84: 18800003 ldbu r2,0(r3) + bf88: 00c00804 movi r3,32 + bf8c: 2885883a add r2,r5,r2 + bf90: 1885c83a sub r2,r3,r2 + bf94: f800283a ret + bf98: 01400404 movi r5,16 + bf9c: 00804034 movhi r2,256 + bfa0: 10bfffc4 addi r2,r2,-1 + bfa4: 2807883a mov r3,r5 + bfa8: 113ff22e bgeu r2,r4,bf74 <__clzsi2+0x1c> + bfac: 01400604 movi r5,24 + bfb0: 2807883a mov r3,r5 + bfb4: 20c6d83a srl r3,r4,r3 + bfb8: 00800074 movhi r2,1 + bfbc: 10815d04 addi r2,r2,1396 + bfc0: 1887883a add r3,r3,r2 + bfc4: 18800003 ldbu r2,0(r3) + bfc8: 00c00804 movi r3,32 + bfcc: 2885883a add r2,r5,r2 + bfd0: 1885c83a sub r2,r3,r2 + bfd4: f800283a ret + +0000bfd8 <__pack_d>: + bfd8: 20c00017 ldw r3,0(r4) + bfdc: defffd04 addi sp,sp,-12 + bfe0: dc000015 stw r16,0(sp) + bfe4: dc800215 stw r18,8(sp) + bfe8: dc400115 stw r17,4(sp) + bfec: 00800044 movi r2,1 + bff0: 22000317 ldw r8,12(r4) + bff4: 001f883a mov r15,zero + bff8: 22400417 ldw r9,16(r4) + bffc: 24000117 ldw r16,4(r4) + c000: 10c0552e bgeu r2,r3,c158 <__pack_d+0x180> + c004: 00800104 movi r2,4 + c008: 18804f26 beq r3,r2,c148 <__pack_d+0x170> + c00c: 00800084 movi r2,2 + c010: 18800226 beq r3,r2,c01c <__pack_d+0x44> + c014: 4244b03a or r2,r8,r9 + c018: 10001a1e bne r2,zero,c084 <__pack_d+0xac> + c01c: 000d883a mov r6,zero + c020: 000f883a mov r7,zero + c024: 0011883a mov r8,zero + c028: 00800434 movhi r2,16 + c02c: 10bfffc4 addi r2,r2,-1 + c030: 301d883a mov r14,r6 + c034: 3884703a and r2,r7,r2 + c038: 400a953a slli r5,r8,20 + c03c: 79bffc2c andhi r6,r15,65520 + c040: 308cb03a or r6,r6,r2 + c044: 00e00434 movhi r3,32784 + c048: 18ffffc4 addi r3,r3,-1 + c04c: 800497fa slli r2,r16,31 + c050: 30c6703a and r3,r6,r3 + c054: 1946b03a or r3,r3,r5 + c058: 01600034 movhi r5,32768 + c05c: 297fffc4 addi r5,r5,-1 + c060: 194a703a and r5,r3,r5 + c064: 288ab03a or r5,r5,r2 + c068: 2807883a mov r3,r5 + c06c: 7005883a mov r2,r14 + c070: dc800217 ldw r18,8(sp) + c074: dc400117 ldw r17,4(sp) + c078: dc000017 ldw r16,0(sp) + c07c: dec00304 addi sp,sp,12 + c080: f800283a ret + c084: 21000217 ldw r4,8(r4) + c088: 00bf0084 movi r2,-1022 + c08c: 20803f16 blt r4,r2,c18c <__pack_d+0x1b4> + c090: 0080ffc4 movi r2,1023 + c094: 11002c16 blt r2,r4,c148 <__pack_d+0x170> + c098: 00803fc4 movi r2,255 + c09c: 408c703a and r6,r8,r2 + c0a0: 00802004 movi r2,128 + c0a4: 0007883a mov r3,zero + c0a8: 000f883a mov r7,zero + c0ac: 2280ffc4 addi r10,r4,1023 + c0b0: 30801e26 beq r6,r2,c12c <__pack_d+0x154> + c0b4: 00801fc4 movi r2,127 + c0b8: 4089883a add r4,r8,r2 + c0bc: 220d803a cmpltu r6,r4,r8 + c0c0: 324d883a add r6,r6,r9 + c0c4: 2011883a mov r8,r4 + c0c8: 3013883a mov r9,r6 + c0cc: 00880034 movhi r2,8192 + c0d0: 10bfffc4 addi r2,r2,-1 + c0d4: 12400d36 bltu r2,r9,c10c <__pack_d+0x134> + c0d8: 4804963a slli r2,r9,24 + c0dc: 400cd23a srli r6,r8,8 + c0e0: 480ed23a srli r7,r9,8 + c0e4: 013fffc4 movi r4,-1 + c0e8: 118cb03a or r6,r2,r6 + c0ec: 01400434 movhi r5,16 + c0f0: 297fffc4 addi r5,r5,-1 + c0f4: 3104703a and r2,r6,r4 + c0f8: 3946703a and r3,r7,r5 + c0fc: 5201ffcc andi r8,r10,2047 + c100: 100d883a mov r6,r2 + c104: 180f883a mov r7,r3 + c108: 003fc706 br c028 <__pack_d+0x50> + c10c: 480897fa slli r4,r9,31 + c110: 4004d07a srli r2,r8,1 + c114: 4806d07a srli r3,r9,1 + c118: 52800044 addi r10,r10,1 + c11c: 2084b03a or r2,r4,r2 + c120: 1011883a mov r8,r2 + c124: 1813883a mov r9,r3 + c128: 003feb06 br c0d8 <__pack_d+0x100> + c12c: 383fe11e bne r7,zero,c0b4 <__pack_d+0xdc> + c130: 01004004 movi r4,256 + c134: 4104703a and r2,r8,r4 + c138: 10c4b03a or r2,r2,r3 + c13c: 103fe326 beq r2,zero,c0cc <__pack_d+0xf4> + c140: 3005883a mov r2,r6 + c144: 003fdc06 br c0b8 <__pack_d+0xe0> + c148: 000d883a mov r6,zero + c14c: 000f883a mov r7,zero + c150: 0201ffc4 movi r8,2047 + c154: 003fb406 br c028 <__pack_d+0x50> + c158: 0005883a mov r2,zero + c15c: 00c00234 movhi r3,8 + c160: 408cb03a or r6,r8,r2 + c164: 48ceb03a or r7,r9,r3 + c168: 013fffc4 movi r4,-1 + c16c: 01400434 movhi r5,16 + c170: 297fffc4 addi r5,r5,-1 + c174: 3104703a and r2,r6,r4 + c178: 3946703a and r3,r7,r5 + c17c: 100d883a mov r6,r2 + c180: 180f883a mov r7,r3 + c184: 0201ffc4 movi r8,2047 + c188: 003fa706 br c028 <__pack_d+0x50> + c18c: 1109c83a sub r4,r2,r4 + c190: 00800e04 movi r2,56 + c194: 11004316 blt r2,r4,c2a4 <__pack_d+0x2cc> + c198: 21fff804 addi r7,r4,-32 + c19c: 38004516 blt r7,zero,c2b4 <__pack_d+0x2dc> + c1a0: 49d8d83a srl r12,r9,r7 + c1a4: 001b883a mov r13,zero + c1a8: 0023883a mov r17,zero + c1ac: 01400044 movi r5,1 + c1b0: 0025883a mov r18,zero + c1b4: 38004716 blt r7,zero,c2d4 <__pack_d+0x2fc> + c1b8: 29d6983a sll r11,r5,r7 + c1bc: 0015883a mov r10,zero + c1c0: 00bfffc4 movi r2,-1 + c1c4: 5089883a add r4,r10,r2 + c1c8: 588b883a add r5,r11,r2 + c1cc: 228d803a cmpltu r6,r4,r10 + c1d0: 314b883a add r5,r6,r5 + c1d4: 4104703a and r2,r8,r4 + c1d8: 4946703a and r3,r9,r5 + c1dc: 10c4b03a or r2,r2,r3 + c1e0: 10000226 beq r2,zero,c1ec <__pack_d+0x214> + c1e4: 04400044 movi r17,1 + c1e8: 0025883a mov r18,zero + c1ec: 00803fc4 movi r2,255 + c1f0: 644eb03a or r7,r12,r17 + c1f4: 3892703a and r9,r7,r2 + c1f8: 00802004 movi r2,128 + c1fc: 6c90b03a or r8,r13,r18 + c200: 0015883a mov r10,zero + c204: 48801626 beq r9,r2,c260 <__pack_d+0x288> + c208: 01001fc4 movi r4,127 + c20c: 3905883a add r2,r7,r4 + c210: 11cd803a cmpltu r6,r2,r7 + c214: 320d883a add r6,r6,r8 + c218: 100f883a mov r7,r2 + c21c: 00840034 movhi r2,4096 + c220: 10bfffc4 addi r2,r2,-1 + c224: 3011883a mov r8,r6 + c228: 0007883a mov r3,zero + c22c: 11801b36 bltu r2,r6,c29c <__pack_d+0x2c4> + c230: 4004963a slli r2,r8,24 + c234: 3808d23a srli r4,r7,8 + c238: 400ad23a srli r5,r8,8 + c23c: 1813883a mov r9,r3 + c240: 1108b03a or r4,r2,r4 + c244: 00bfffc4 movi r2,-1 + c248: 00c00434 movhi r3,16 + c24c: 18ffffc4 addi r3,r3,-1 + c250: 208c703a and r6,r4,r2 + c254: 28ce703a and r7,r5,r3 + c258: 4a01ffcc andi r8,r9,2047 + c25c: 003f7206 br c028 <__pack_d+0x50> + c260: 503fe91e bne r10,zero,c208 <__pack_d+0x230> + c264: 01004004 movi r4,256 + c268: 3904703a and r2,r7,r4 + c26c: 0007883a mov r3,zero + c270: 10c4b03a or r2,r2,r3 + c274: 10000626 beq r2,zero,c290 <__pack_d+0x2b8> + c278: 3a45883a add r2,r7,r9 + c27c: 11cd803a cmpltu r6,r2,r7 + c280: 320d883a add r6,r6,r8 + c284: 100f883a mov r7,r2 + c288: 3011883a mov r8,r6 + c28c: 0007883a mov r3,zero + c290: 00840034 movhi r2,4096 + c294: 10bfffc4 addi r2,r2,-1 + c298: 123fe52e bgeu r2,r8,c230 <__pack_d+0x258> + c29c: 00c00044 movi r3,1 + c2a0: 003fe306 br c230 <__pack_d+0x258> + c2a4: 0009883a mov r4,zero + c2a8: 0013883a mov r9,zero + c2ac: 000b883a mov r5,zero + c2b0: 003fe406 br c244 <__pack_d+0x26c> + c2b4: 4a47883a add r3,r9,r9 + c2b8: 008007c4 movi r2,31 + c2bc: 1105c83a sub r2,r2,r4 + c2c0: 1886983a sll r3,r3,r2 + c2c4: 4118d83a srl r12,r8,r4 + c2c8: 491ad83a srl r13,r9,r4 + c2cc: 1b18b03a or r12,r3,r12 + c2d0: 003fb506 br c1a8 <__pack_d+0x1d0> + c2d4: 2806d07a srli r3,r5,1 + c2d8: 008007c4 movi r2,31 + c2dc: 1105c83a sub r2,r2,r4 + c2e0: 1896d83a srl r11,r3,r2 + c2e4: 2914983a sll r10,r5,r4 + c2e8: 003fb506 br c1c0 <__pack_d+0x1e8> + +0000c2ec <__unpack_d>: + c2ec: 20c00117 ldw r3,4(r4) + c2f0: 22400017 ldw r9,0(r4) + c2f4: 00800434 movhi r2,16 + c2f8: 10bfffc4 addi r2,r2,-1 + c2fc: 1808d53a srli r4,r3,20 + c300: 180cd7fa srli r6,r3,31 + c304: 1894703a and r10,r3,r2 + c308: 2201ffcc andi r8,r4,2047 + c30c: 281b883a mov r13,r5 + c310: 4817883a mov r11,r9 + c314: 29800115 stw r6,4(r5) + c318: 5019883a mov r12,r10 + c31c: 40001e1e bne r8,zero,c398 <__unpack_d+0xac> + c320: 4a84b03a or r2,r9,r10 + c324: 10001926 beq r2,zero,c38c <__unpack_d+0xa0> + c328: 4804d63a srli r2,r9,24 + c32c: 500c923a slli r6,r10,8 + c330: 013f0084 movi r4,-1022 + c334: 00c40034 movhi r3,4096 + c338: 18ffffc4 addi r3,r3,-1 + c33c: 118cb03a or r6,r2,r6 + c340: 008000c4 movi r2,3 + c344: 480a923a slli r5,r9,8 + c348: 68800015 stw r2,0(r13) + c34c: 69000215 stw r4,8(r13) + c350: 19800b36 bltu r3,r6,c380 <__unpack_d+0x94> + c354: 200f883a mov r7,r4 + c358: 1811883a mov r8,r3 + c35c: 2945883a add r2,r5,r5 + c360: 1149803a cmpltu r4,r2,r5 + c364: 3187883a add r3,r6,r6 + c368: 20c9883a add r4,r4,r3 + c36c: 100b883a mov r5,r2 + c370: 200d883a mov r6,r4 + c374: 39ffffc4 addi r7,r7,-1 + c378: 413ff82e bgeu r8,r4,c35c <__unpack_d+0x70> + c37c: 69c00215 stw r7,8(r13) + c380: 69800415 stw r6,16(r13) + c384: 69400315 stw r5,12(r13) + c388: f800283a ret + c38c: 00800084 movi r2,2 + c390: 28800015 stw r2,0(r5) + c394: f800283a ret + c398: 0081ffc4 movi r2,2047 + c39c: 40800f26 beq r8,r2,c3dc <__unpack_d+0xf0> + c3a0: 480cd63a srli r6,r9,24 + c3a4: 5006923a slli r3,r10,8 + c3a8: 4804923a slli r2,r9,8 + c3ac: 0009883a mov r4,zero + c3b0: 30c6b03a or r3,r6,r3 + c3b4: 01440034 movhi r5,4096 + c3b8: 110cb03a or r6,r2,r4 + c3bc: 423f0044 addi r8,r8,-1023 + c3c0: 194eb03a or r7,r3,r5 + c3c4: 008000c4 movi r2,3 + c3c8: 69c00415 stw r7,16(r13) + c3cc: 6a000215 stw r8,8(r13) + c3d0: 68800015 stw r2,0(r13) + c3d4: 69800315 stw r6,12(r13) + c3d8: f800283a ret + c3dc: 4a84b03a or r2,r9,r10 + c3e0: 1000031e bne r2,zero,c3f0 <__unpack_d+0x104> + c3e4: 00800104 movi r2,4 + c3e8: 28800015 stw r2,0(r5) + c3ec: f800283a ret + c3f0: 0009883a mov r4,zero + c3f4: 01400234 movhi r5,8 + c3f8: 4904703a and r2,r9,r4 + c3fc: 5146703a and r3,r10,r5 + c400: 10c4b03a or r2,r2,r3 + c404: 10000526 beq r2,zero,c41c <__unpack_d+0x130> + c408: 00800044 movi r2,1 + c40c: 68800015 stw r2,0(r13) + c410: 6b000415 stw r12,16(r13) + c414: 6ac00315 stw r11,12(r13) + c418: f800283a ret + c41c: 68000015 stw zero,0(r13) + c420: 003ffb06 br c410 <__unpack_d+0x124> + +0000c424 <__fpcmp_parts_d>: + c424: 21800017 ldw r6,0(r4) + c428: 00c00044 movi r3,1 + c42c: 19800a2e bgeu r3,r6,c458 <__fpcmp_parts_d+0x34> + c430: 28800017 ldw r2,0(r5) + c434: 1880082e bgeu r3,r2,c458 <__fpcmp_parts_d+0x34> + c438: 00c00104 movi r3,4 + c43c: 30c02626 beq r6,r3,c4d8 <__fpcmp_parts_d+0xb4> + c440: 10c02226 beq r2,r3,c4cc <__fpcmp_parts_d+0xa8> + c444: 00c00084 movi r3,2 + c448: 30c00526 beq r6,r3,c460 <__fpcmp_parts_d+0x3c> + c44c: 10c0071e bne r2,r3,c46c <__fpcmp_parts_d+0x48> + c450: 20800117 ldw r2,4(r4) + c454: 1000091e bne r2,zero,c47c <__fpcmp_parts_d+0x58> + c458: 00800044 movi r2,1 + c45c: f800283a ret + c460: 10c01a1e bne r2,r3,c4cc <__fpcmp_parts_d+0xa8> + c464: 0005883a mov r2,zero + c468: f800283a ret + c46c: 22000117 ldw r8,4(r4) + c470: 28800117 ldw r2,4(r5) + c474: 40800326 beq r8,r2,c484 <__fpcmp_parts_d+0x60> + c478: 403ff726 beq r8,zero,c458 <__fpcmp_parts_d+0x34> + c47c: 00bfffc4 movi r2,-1 + c480: f800283a ret + c484: 20c00217 ldw r3,8(r4) + c488: 28800217 ldw r2,8(r5) + c48c: 10fffa16 blt r2,r3,c478 <__fpcmp_parts_d+0x54> + c490: 18800916 blt r3,r2,c4b8 <__fpcmp_parts_d+0x94> + c494: 21c00417 ldw r7,16(r4) + c498: 28c00417 ldw r3,16(r5) + c49c: 21800317 ldw r6,12(r4) + c4a0: 28800317 ldw r2,12(r5) + c4a4: 19fff436 bltu r3,r7,c478 <__fpcmp_parts_d+0x54> + c4a8: 38c00526 beq r7,r3,c4c0 <__fpcmp_parts_d+0x9c> + c4ac: 38c00236 bltu r7,r3,c4b8 <__fpcmp_parts_d+0x94> + c4b0: 19ffec1e bne r3,r7,c464 <__fpcmp_parts_d+0x40> + c4b4: 30bfeb2e bgeu r6,r2,c464 <__fpcmp_parts_d+0x40> + c4b8: 403fe71e bne r8,zero,c458 <__fpcmp_parts_d+0x34> + c4bc: 003fef06 br c47c <__fpcmp_parts_d+0x58> + c4c0: 11bffa2e bgeu r2,r6,c4ac <__fpcmp_parts_d+0x88> + c4c4: 403fe426 beq r8,zero,c458 <__fpcmp_parts_d+0x34> + c4c8: 003fec06 br c47c <__fpcmp_parts_d+0x58> + c4cc: 28800117 ldw r2,4(r5) + c4d0: 103fe11e bne r2,zero,c458 <__fpcmp_parts_d+0x34> + c4d4: 003fe906 br c47c <__fpcmp_parts_d+0x58> + c4d8: 11bfdd1e bne r2,r6,c450 <__fpcmp_parts_d+0x2c> + c4dc: 28c00117 ldw r3,4(r5) + c4e0: 20800117 ldw r2,4(r4) + c4e4: 1885c83a sub r2,r3,r2 + c4e8: f800283a ret + +0000c4ec : + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + c4ec: defff804 addi sp,sp,-32 + c4f0: dfc00715 stw ra,28(sp) + c4f4: df000615 stw fp,24(sp) + c4f8: df000604 addi fp,sp,24 + c4fc: e13ffc15 stw r4,-16(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + c500: e0bffc17 ldw r2,-16(fp) + c504: 1004803a cmplt r2,r2,zero + c508: 1000091e bne r2,zero,c530 + c50c: e13ffc17 ldw r4,-16(fp) + c510: 01400304 movi r5,12 + c514: 0002c240 call 2c24 <__mulsi3> + c518: 1007883a mov r3,r2 + c51c: 00800074 movhi r2,1 + c520: 1083bc04 addi r2,r2,3824 + c524: 1887883a add r3,r3,r2 + c528: e0ffff15 stw r3,-4(fp) + c52c: 00000106 br c534 + c530: e03fff15 stw zero,-4(fp) + c534: e0bfff17 ldw r2,-4(fp) + c538: e0bffb15 stw r2,-20(fp) + + if (fd) + c53c: e0bffb17 ldw r2,-20(fp) + c540: 1005003a cmpeq r2,r2,zero + c544: 10001d1e bne r2,zero,c5bc + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + c548: e0bffb17 ldw r2,-20(fp) + c54c: 10800017 ldw r2,0(r2) + c550: 10800417 ldw r2,16(r2) + c554: 1005003a cmpeq r2,r2,zero + c558: 1000071e bne r2,zero,c578 + c55c: e0bffb17 ldw r2,-20(fp) + c560: 10800017 ldw r2,0(r2) + c564: 10800417 ldw r2,16(r2) + c568: e13ffb17 ldw r4,-20(fp) + c56c: 103ee83a callr r2 + c570: e0bffe15 stw r2,-8(fp) + c574: 00000106 br c57c + c578: e03ffe15 stw zero,-8(fp) + c57c: e0bffe17 ldw r2,-8(fp) + c580: e0bffa15 stw r2,-24(fp) + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + c584: e13ffc17 ldw r4,-16(fp) + c588: 000cd440 call cd44 + if (rval < 0) + c58c: e0bffa17 ldw r2,-24(fp) + c590: 1004403a cmpge r2,r2,zero + c594: 1000071e bne r2,zero,c5b4 + { + ALT_ERRNO = -rval; + c598: 000c5ec0 call c5ec + c59c: e0fffa17 ldw r3,-24(fp) + c5a0: 00c7c83a sub r3,zero,r3 + c5a4: 10c00015 stw r3,0(r2) + return -1; + c5a8: 00bfffc4 movi r2,-1 + c5ac: e0bffd15 stw r2,-12(fp) + c5b0: 00000806 br c5d4 + } + return 0; + c5b4: e03ffd15 stw zero,-12(fp) + c5b8: 00000606 br c5d4 + } + else + { + ALT_ERRNO = EBADFD; + c5bc: 000c5ec0 call c5ec + c5c0: 1007883a mov r3,r2 + c5c4: 00801444 movi r2,81 + c5c8: 18800015 stw r2,0(r3) + return -1; + c5cc: 00bfffc4 movi r2,-1 + c5d0: e0bffd15 stw r2,-12(fp) + c5d4: e0bffd17 ldw r2,-12(fp) + } +} + c5d8: e037883a mov sp,fp + c5dc: dfc00117 ldw ra,4(sp) + c5e0: df000017 ldw fp,0(sp) + c5e4: dec00204 addi sp,sp,8 + c5e8: f800283a ret + +0000c5ec : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + c5ec: defffd04 addi sp,sp,-12 + c5f0: dfc00215 stw ra,8(sp) + c5f4: df000115 stw fp,4(sp) + c5f8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + c5fc: 00800074 movhi r2,1 + c600: 10888904 addi r2,r2,8740 + c604: 10800017 ldw r2,0(r2) + c608: 1005003a cmpeq r2,r2,zero + c60c: 1000061e bne r2,zero,c628 + c610: 00800074 movhi r2,1 + c614: 10888904 addi r2,r2,8740 + c618: 10800017 ldw r2,0(r2) + c61c: 103ee83a callr r2 + c620: e0bfff15 stw r2,-4(fp) + c624: 00000306 br c634 + c628: 00800074 movhi r2,1 + c62c: 108f7c04 addi r2,r2,15856 + c630: e0bfff15 stw r2,-4(fp) + c634: e0bfff17 ldw r2,-4(fp) +} + c638: e037883a mov sp,fp + c63c: dfc00117 ldw ra,4(sp) + c640: df000017 ldw fp,0(sp) + c644: dec00204 addi sp,sp,8 + c648: f800283a ret + +0000c64c : + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + c64c: defffc04 addi sp,sp,-16 + c650: df000315 stw fp,12(sp) + c654: df000304 addi fp,sp,12 + c658: e13ffd15 stw r4,-12(fp) + c65c: e17ffe15 stw r5,-8(fp) + c660: e1bfff15 stw r6,-4(fp) + return len; + c664: e0bfff17 ldw r2,-4(fp) +} + c668: e037883a mov sp,fp + c66c: df000017 ldw fp,0(sp) + c670: dec00104 addi sp,sp,4 + c674: f800283a ret + +0000c678 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + c678: defff904 addi sp,sp,-28 + c67c: dfc00615 stw ra,24(sp) + c680: df000515 stw fp,20(sp) + c684: df000504 addi fp,sp,20 + c688: e13ffc15 stw r4,-16(fp) + c68c: e17ffd15 stw r5,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + c690: e0bffc17 ldw r2,-16(fp) + c694: 1004803a cmplt r2,r2,zero + c698: 1000091e bne r2,zero,c6c0 + c69c: e13ffc17 ldw r4,-16(fp) + c6a0: 01400304 movi r5,12 + c6a4: 0002c240 call 2c24 <__mulsi3> + c6a8: 1007883a mov r3,r2 + c6ac: 00800074 movhi r2,1 + c6b0: 1083bc04 addi r2,r2,3824 + c6b4: 1887883a add r3,r3,r2 + c6b8: e0ffff15 stw r3,-4(fp) + c6bc: 00000106 br c6c4 + c6c0: e03fff15 stw zero,-4(fp) + c6c4: e0bfff17 ldw r2,-4(fp) + c6c8: e0bffb15 stw r2,-20(fp) + + if (fd) + c6cc: e0bffb17 ldw r2,-20(fp) + c6d0: 1005003a cmpeq r2,r2,zero + c6d4: 1000121e bne r2,zero,c720 + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + c6d8: e0bffb17 ldw r2,-20(fp) + c6dc: 10800017 ldw r2,0(r2) + c6e0: 10800817 ldw r2,32(r2) + c6e4: 1005003a cmpeq r2,r2,zero + c6e8: 1000081e bne r2,zero,c70c + { + return fd->dev->fstat(fd, st); + c6ec: e0bffb17 ldw r2,-20(fp) + c6f0: 10800017 ldw r2,0(r2) + c6f4: 10800817 ldw r2,32(r2) + c6f8: e13ffb17 ldw r4,-20(fp) + c6fc: e17ffd17 ldw r5,-12(fp) + c700: 103ee83a callr r2 + c704: e0bffe15 stw r2,-8(fp) + c708: 00000b06 br c738 + * device. + */ + + else + { + st->st_mode = _IFCHR; + c70c: e0fffd17 ldw r3,-12(fp) + c710: 00880004 movi r2,8192 + c714: 18800115 stw r2,4(r3) + return 0; + c718: e03ffe15 stw zero,-8(fp) + c71c: 00000606 br c738 + } + } + else + { + ALT_ERRNO = EBADFD; + c720: 000c7500 call c750 + c724: 1007883a mov r3,r2 + c728: 00801444 movi r2,81 + c72c: 18800015 stw r2,0(r3) + return -1; + c730: 00bfffc4 movi r2,-1 + c734: e0bffe15 stw r2,-8(fp) + c738: e0bffe17 ldw r2,-8(fp) + } +} + c73c: e037883a mov sp,fp + c740: dfc00117 ldw ra,4(sp) + c744: df000017 ldw fp,0(sp) + c748: dec00204 addi sp,sp,8 + c74c: f800283a ret + +0000c750 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + c750: defffd04 addi sp,sp,-12 + c754: dfc00215 stw ra,8(sp) + c758: df000115 stw fp,4(sp) + c75c: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + c760: 00800074 movhi r2,1 + c764: 10888904 addi r2,r2,8740 + c768: 10800017 ldw r2,0(r2) + c76c: 1005003a cmpeq r2,r2,zero + c770: 1000061e bne r2,zero,c78c + c774: 00800074 movhi r2,1 + c778: 10888904 addi r2,r2,8740 + c77c: 10800017 ldw r2,0(r2) + c780: 103ee83a callr r2 + c784: e0bfff15 stw r2,-4(fp) + c788: 00000306 br c798 + c78c: 00800074 movhi r2,1 + c790: 108f7c04 addi r2,r2,15856 + c794: e0bfff15 stw r2,-4(fp) + c798: e0bfff17 ldw r2,-4(fp) +} + c79c: e037883a mov sp,fp + c7a0: dfc00117 ldw ra,4(sp) + c7a4: df000017 ldw fp,0(sp) + c7a8: dec00204 addi sp,sp,8 + c7ac: f800283a ret + +0000c7b0 : + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + c7b0: deffeb04 addi sp,sp,-84 + c7b4: dfc01415 stw ra,80(sp) + c7b8: df001315 stw fp,76(sp) + c7bc: df001304 addi fp,sp,76 + c7c0: e13ffd15 stw r4,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + c7c4: e0bffd17 ldw r2,-12(fp) + c7c8: 1004803a cmplt r2,r2,zero + c7cc: 1000091e bne r2,zero,c7f4 + c7d0: e13ffd17 ldw r4,-12(fp) + c7d4: 01400304 movi r5,12 + c7d8: 0002c240 call 2c24 <__mulsi3> + c7dc: 1007883a mov r3,r2 + c7e0: 00800074 movhi r2,1 + c7e4: 1083bc04 addi r2,r2,3824 + c7e8: 1887883a add r3,r3,r2 + c7ec: e0ffff15 stw r3,-4(fp) + c7f0: 00000106 br c7f8 + c7f4: e03fff15 stw zero,-4(fp) + c7f8: e0bfff17 ldw r2,-4(fp) + c7fc: e0bfed15 stw r2,-76(fp) + + if (fd) + c800: e0bfed17 ldw r2,-76(fp) + c804: 1005003a cmpeq r2,r2,zero + c808: 10000f1e bne r2,zero,c848 + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + c80c: e0bfed17 ldw r2,-76(fp) + c810: 10800017 ldw r2,0(r2) + c814: 10800817 ldw r2,32(r2) + c818: 1004c03a cmpne r2,r2,zero + c81c: 1000031e bne r2,zero,c82c + { + return 1; + c820: 00800044 movi r2,1 + c824: e0bffe15 stw r2,-8(fp) + c828: 00000c06 br c85c + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + c82c: e17fee04 addi r5,fp,-72 + c830: e13ffd17 ldw r4,-12(fp) + c834: 000c6780 call c678 + return (stat.st_mode == _IFCHR) ? 1 : 0; + c838: e0bfef17 ldw r2,-68(fp) + c83c: 10880020 cmpeqi r2,r2,8192 + c840: e0bffe15 stw r2,-8(fp) + c844: 00000506 br c85c + } + } + else + { + ALT_ERRNO = EBADFD; + c848: 000c8740 call c874 + c84c: 1007883a mov r3,r2 + c850: 00801444 movi r2,81 + c854: 18800015 stw r2,0(r3) + return 0; + c858: e03ffe15 stw zero,-8(fp) + c85c: e0bffe17 ldw r2,-8(fp) + } +} + c860: e037883a mov sp,fp + c864: dfc00117 ldw ra,4(sp) + c868: df000017 ldw fp,0(sp) + c86c: dec00204 addi sp,sp,8 + c870: f800283a ret + +0000c874 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + c874: defffd04 addi sp,sp,-12 + c878: dfc00215 stw ra,8(sp) + c87c: df000115 stw fp,4(sp) + c880: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + c884: 00800074 movhi r2,1 + c888: 10888904 addi r2,r2,8740 + c88c: 10800017 ldw r2,0(r2) + c890: 1005003a cmpeq r2,r2,zero + c894: 1000061e bne r2,zero,c8b0 + c898: 00800074 movhi r2,1 + c89c: 10888904 addi r2,r2,8740 + c8a0: 10800017 ldw r2,0(r2) + c8a4: 103ee83a callr r2 + c8a8: e0bfff15 stw r2,-4(fp) + c8ac: 00000306 br c8bc + c8b0: 00800074 movhi r2,1 + c8b4: 108f7c04 addi r2,r2,15856 + c8b8: e0bfff15 stw r2,-4(fp) + c8bc: e0bfff17 ldw r2,-4(fp) +} + c8c0: e037883a mov sp,fp + c8c4: dfc00117 ldw ra,4(sp) + c8c8: df000017 ldw fp,0(sp) + c8cc: dec00204 addi sp,sp,8 + c8d0: f800283a ret + +0000c8d4 : + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + c8d4: defffe04 addi sp,sp,-8 + c8d8: dfc00115 stw ra,4(sp) + c8dc: df000015 stw fp,0(sp) + c8e0: d839883a mov fp,sp + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + c8e4: 01000074 movhi r4,1 + c8e8: 21088f04 addi r4,r4,8764 + c8ec: 01400074 movhi r5,1 + c8f0: 2941ad04 addi r5,r5,1716 + c8f4: 01800074 movhi r6,1 + c8f8: 31888f04 addi r6,r6,8764 + c8fc: 000c9540 call c954 + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + c900: 01000034 movhi r4,0 + c904: 21000804 addi r4,r4,32 + c908: 01400034 movhi r5,0 + c90c: 29400804 addi r5,r5,32 + c910: 01800034 movhi r6,0 + c914: 31806d04 addi r6,r6,436 + c918: 000c9540 call c954 + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + c91c: 01000074 movhi r4,1 + c920: 213fe404 addi r4,r4,-112 + c924: 01400074 movhi r5,1 + c928: 297fe404 addi r5,r5,-112 + c92c: 01800074 movhi r6,1 + c930: 3181ad04 addi r6,r6,1716 + c934: 000c9540 call c954 + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + c938: 000ee280 call ee28 + alt_icache_flush_all(); + c93c: 000f0200 call f020 +} + c940: e037883a mov sp,fp + c944: dfc00117 ldw ra,4(sp) + c948: df000017 ldw fp,0(sp) + c94c: dec00204 addi sp,sp,8 + c950: f800283a ret + +0000c954 : + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + c954: defffc04 addi sp,sp,-16 + c958: df000315 stw fp,12(sp) + c95c: df000304 addi fp,sp,12 + c960: e13ffd15 stw r4,-12(fp) + c964: e17ffe15 stw r5,-8(fp) + c968: e1bfff15 stw r6,-4(fp) + if (to != from) + c96c: e0fffe17 ldw r3,-8(fp) + c970: e0bffd17 ldw r2,-12(fp) + c974: 18800e26 beq r3,r2,c9b0 + { + while( to != end ) + c978: 00000a06 br c9a4 + { + *to++ = *from++; + c97c: e0bffd17 ldw r2,-12(fp) + c980: 10c00017 ldw r3,0(r2) + c984: e0bffe17 ldw r2,-8(fp) + c988: 10c00015 stw r3,0(r2) + c98c: e0bffe17 ldw r2,-8(fp) + c990: 10800104 addi r2,r2,4 + c994: e0bffe15 stw r2,-8(fp) + c998: e0bffd17 ldw r2,-12(fp) + c99c: 10800104 addi r2,r2,4 + c9a0: e0bffd15 stw r2,-12(fp) + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + c9a4: e0fffe17 ldw r3,-8(fp) + c9a8: e0bfff17 ldw r2,-4(fp) + c9ac: 18bff31e bne r3,r2,c97c + { + *to++ = *from++; + } + } +} + c9b0: e037883a mov sp,fp + c9b4: df000017 ldw fp,0(sp) + c9b8: dec00104 addi sp,sp,4 + c9bc: f800283a ret + +0000c9c0 : + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + c9c0: defff804 addi sp,sp,-32 + c9c4: dfc00715 stw ra,28(sp) + c9c8: df000615 stw fp,24(sp) + c9cc: df000604 addi fp,sp,24 + c9d0: e13ffc15 stw r4,-16(fp) + c9d4: e17ffd15 stw r5,-12(fp) + c9d8: e1bffe15 stw r6,-8(fp) + alt_fd* fd; + off_t rc = 0; + c9dc: e03ffa15 stw zero,-24(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + c9e0: e0bffc17 ldw r2,-16(fp) + c9e4: 1004803a cmplt r2,r2,zero + c9e8: 1000091e bne r2,zero,ca10 + c9ec: e13ffc17 ldw r4,-16(fp) + c9f0: 01400304 movi r5,12 + c9f4: 0002c240 call 2c24 <__mulsi3> + c9f8: 1007883a mov r3,r2 + c9fc: 00800074 movhi r2,1 + ca00: 1083bc04 addi r2,r2,3824 + ca04: 1887883a add r3,r3,r2 + ca08: e0ffff15 stw r3,-4(fp) + ca0c: 00000106 br ca14 + ca10: e03fff15 stw zero,-4(fp) + ca14: e0bfff17 ldw r2,-4(fp) + ca18: e0bffb15 stw r2,-20(fp) + + if (fd) + ca1c: e0bffb17 ldw r2,-20(fp) + ca20: 1005003a cmpeq r2,r2,zero + ca24: 1000111e bne r2,zero,ca6c + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + ca28: e0bffb17 ldw r2,-20(fp) + ca2c: 10800017 ldw r2,0(r2) + ca30: 10800717 ldw r2,28(r2) + ca34: 1005003a cmpeq r2,r2,zero + ca38: 1000091e bne r2,zero,ca60 + { + rc = fd->dev->lseek(fd, ptr, dir); + ca3c: e0bffb17 ldw r2,-20(fp) + ca40: 10800017 ldw r2,0(r2) + ca44: 10800717 ldw r2,28(r2) + ca48: e13ffb17 ldw r4,-20(fp) + ca4c: e17ffd17 ldw r5,-12(fp) + ca50: e1bffe17 ldw r6,-8(fp) + ca54: 103ee83a callr r2 + ca58: e0bffa15 stw r2,-24(fp) + ca5c: 00000506 br ca74 + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + ca60: 00bfde84 movi r2,-134 + ca64: e0bffa15 stw r2,-24(fp) + ca68: 00000206 br ca74 + } + } + else + { + rc = -EBADFD; + ca6c: 00bfebc4 movi r2,-81 + ca70: e0bffa15 stw r2,-24(fp) + } + + if (rc < 0) + ca74: e0bffa17 ldw r2,-24(fp) + ca78: 1004403a cmpge r2,r2,zero + ca7c: 1000071e bne r2,zero,ca9c + { + ALT_ERRNO = -rc; + ca80: 000cab40 call cab4 + ca84: 1007883a mov r3,r2 + ca88: e0bffa17 ldw r2,-24(fp) + ca8c: 0085c83a sub r2,zero,r2 + ca90: 18800015 stw r2,0(r3) + rc = -1; + ca94: 00bfffc4 movi r2,-1 + ca98: e0bffa15 stw r2,-24(fp) + } + + return rc; + ca9c: e0bffa17 ldw r2,-24(fp) +} + caa0: e037883a mov sp,fp + caa4: dfc00117 ldw ra,4(sp) + caa8: df000017 ldw fp,0(sp) + caac: dec00204 addi sp,sp,8 + cab0: f800283a ret + +0000cab4 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + cab4: defffd04 addi sp,sp,-12 + cab8: dfc00215 stw ra,8(sp) + cabc: df000115 stw fp,4(sp) + cac0: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + cac4: 00800074 movhi r2,1 + cac8: 10888904 addi r2,r2,8740 + cacc: 10800017 ldw r2,0(r2) + cad0: 1005003a cmpeq r2,r2,zero + cad4: 1000061e bne r2,zero,caf0 + cad8: 00800074 movhi r2,1 + cadc: 10888904 addi r2,r2,8740 + cae0: 10800017 ldw r2,0(r2) + cae4: 103ee83a callr r2 + cae8: e0bfff15 stw r2,-4(fp) + caec: 00000306 br cafc + caf0: 00800074 movhi r2,1 + caf4: 108f7c04 addi r2,r2,15856 + caf8: e0bfff15 stw r2,-4(fp) + cafc: e0bfff17 ldw r2,-4(fp) +} + cb00: e037883a mov sp,fp + cb04: dfc00117 ldw ra,4(sp) + cb08: df000017 ldw fp,0(sp) + cb0c: dec00204 addi sp,sp,8 + cb10: f800283a ret + +0000cb14 : + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ + cb14: defffd04 addi sp,sp,-12 + cb18: dfc00215 stw ra,8(sp) + cb1c: df000115 stw fp,4(sp) + cb20: df000104 addi fp,sp,4 +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + cb24: 0009883a mov r4,zero + cb28: 000d02c0 call d02c + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + cb2c: 000d0600 call d060 + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); + cb30: 01000074 movhi r4,1 + cb34: 2101a004 addi r4,r4,1664 + cb38: 01400074 movhi r5,1 + cb3c: 2941a004 addi r5,r5,1664 + cb40: 01800074 movhi r6,1 + cb44: 3181a004 addi r6,r6,1664 + cb48: 000f3e00 call f3e0 + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); + cb4c: 000ef580 call ef58 <_do_ctors> + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); + cb50: 01000074 movhi r4,1 + cb54: 213bef04 addi r4,r4,-4164 + cb58: 000fb840 call fb84 + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + cb5c: d1270117 ldw r4,-25596(gp) + cb60: d1670217 ldw r5,-25592(gp) + cb64: d1a70317 ldw r6,-25588(gp) + cb68: 00009000 call 900
+ cb6c: e0bfff15 stw r2,-4(fp) + close(STDOUT_FILENO); + cb70: 01000044 movi r4,1 + cb74: 000c4ec0 call c4ec + exit (result); + cb78: e13fff17 ldw r4,-4(fp) + cb7c: 000fb980 call fb98 + +0000cb80 <__malloc_lock>: + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that malloc is never called by an interrupt service routine. + */ + +void __malloc_lock ( struct _reent *_r ) +{ + cb80: defffe04 addi sp,sp,-8 + cb84: df000115 stw fp,4(sp) + cb88: df000104 addi fp,sp,4 + cb8c: e13fff15 stw r4,-4(fp) +} + cb90: e037883a mov sp,fp + cb94: df000017 ldw fp,0(sp) + cb98: dec00104 addi sp,sp,4 + cb9c: f800283a ret + +0000cba0 <__malloc_unlock>: +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ + cba0: defffe04 addi sp,sp,-8 + cba4: df000115 stw fp,4(sp) + cba8: df000104 addi fp,sp,4 + cbac: e13fff15 stw r4,-4(fp) +} + cbb0: e037883a mov sp,fp + cbb4: df000017 ldw fp,0(sp) + cbb8: dec00104 addi sp,sp,4 + cbbc: f800283a ret + +0000cbc0 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + cbc0: defff704 addi sp,sp,-36 + cbc4: dfc00815 stw ra,32(sp) + cbc8: df000715 stw fp,28(sp) + cbcc: df000704 addi fp,sp,28 + cbd0: e13ffb15 stw r4,-20(fp) + cbd4: e17ffc15 stw r5,-16(fp) + cbd8: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + cbdc: e0bffb17 ldw r2,-20(fp) + cbe0: 1004803a cmplt r2,r2,zero + cbe4: 1000091e bne r2,zero,cc0c + cbe8: e13ffb17 ldw r4,-20(fp) + cbec: 01400304 movi r5,12 + cbf0: 0002c240 call 2c24 <__mulsi3> + cbf4: 1007883a mov r3,r2 + cbf8: 00800074 movhi r2,1 + cbfc: 1083bc04 addi r2,r2,3824 + cc00: 1887883a add r3,r3,r2 + cc04: e0ffff15 stw r3,-4(fp) + cc08: 00000106 br cc10 + cc0c: e03fff15 stw zero,-4(fp) + cc10: e0bfff17 ldw r2,-4(fp) + cc14: e0bffa15 stw r2,-24(fp) + + if (fd) + cc18: e0bffa17 ldw r2,-24(fp) + cc1c: 1005003a cmpeq r2,r2,zero + cc20: 1000241e bne r2,zero,ccb4 + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + cc24: e0bffa17 ldw r2,-24(fp) + cc28: 10800217 ldw r2,8(r2) + cc2c: 108000cc andi r2,r2,3 + cc30: 10800060 cmpeqi r2,r2,1 + cc34: 10001a1e bne r2,zero,cca0 + cc38: e0bffa17 ldw r2,-24(fp) + cc3c: 10800017 ldw r2,0(r2) + cc40: 10800517 ldw r2,20(r2) + cc44: 1005003a cmpeq r2,r2,zero + cc48: 1000151e bne r2,zero,cca0 + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + cc4c: e0bffa17 ldw r2,-24(fp) + cc50: 10800017 ldw r2,0(r2) + cc54: 10800517 ldw r2,20(r2) + cc58: e17ffc17 ldw r5,-16(fp) + cc5c: e1bffd17 ldw r6,-12(fp) + cc60: e13ffa17 ldw r4,-24(fp) + cc64: 103ee83a callr r2 + cc68: e0bff915 stw r2,-28(fp) + cc6c: e0bff917 ldw r2,-28(fp) + cc70: 1004403a cmpge r2,r2,zero + cc74: 1000071e bne r2,zero,cc94 + { + ALT_ERRNO = -rval; + cc78: 000cce40 call cce4 + cc7c: e0fff917 ldw r3,-28(fp) + cc80: 00c7c83a sub r3,zero,r3 + cc84: 10c00015 stw r3,0(r2) + return -1; + cc88: 00bfffc4 movi r2,-1 + cc8c: e0bffe15 stw r2,-8(fp) + cc90: 00000e06 br cccc + } + return rval; + cc94: e0bff917 ldw r2,-28(fp) + cc98: e0bffe15 stw r2,-8(fp) + cc9c: 00000b06 br cccc + } + else + { + ALT_ERRNO = EACCES; + cca0: 000cce40 call cce4 + cca4: 1007883a mov r3,r2 + cca8: 00800344 movi r2,13 + ccac: 18800015 stw r2,0(r3) + ccb0: 00000406 br ccc4 + } + } + else + { + ALT_ERRNO = EBADFD; + ccb4: 000cce40 call cce4 + ccb8: 1007883a mov r3,r2 + ccbc: 00801444 movi r2,81 + ccc0: 18800015 stw r2,0(r3) + } + return -1; + ccc4: 00bfffc4 movi r2,-1 + ccc8: e0bffe15 stw r2,-8(fp) + cccc: e0bffe17 ldw r2,-8(fp) +} + ccd0: e037883a mov sp,fp + ccd4: dfc00117 ldw ra,4(sp) + ccd8: df000017 ldw fp,0(sp) + ccdc: dec00204 addi sp,sp,8 + cce0: f800283a ret + +0000cce4 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + cce4: defffd04 addi sp,sp,-12 + cce8: dfc00215 stw ra,8(sp) + ccec: df000115 stw fp,4(sp) + ccf0: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + ccf4: 00800074 movhi r2,1 + ccf8: 10888904 addi r2,r2,8740 + ccfc: 10800017 ldw r2,0(r2) + cd00: 1005003a cmpeq r2,r2,zero + cd04: 1000061e bne r2,zero,cd20 + cd08: 00800074 movhi r2,1 + cd0c: 10888904 addi r2,r2,8740 + cd10: 10800017 ldw r2,0(r2) + cd14: 103ee83a callr r2 + cd18: e0bfff15 stw r2,-4(fp) + cd1c: 00000306 br cd2c + cd20: 00800074 movhi r2,1 + cd24: 108f7c04 addi r2,r2,15856 + cd28: e0bfff15 stw r2,-4(fp) + cd2c: e0bfff17 ldw r2,-4(fp) +} + cd30: e037883a mov sp,fp + cd34: dfc00117 ldw ra,4(sp) + cd38: df000017 ldw fp,0(sp) + cd3c: dec00204 addi sp,sp,8 + cd40: f800283a ret + +0000cd44 : + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + cd44: defffc04 addi sp,sp,-16 + cd48: dfc00315 stw ra,12(sp) + cd4c: df000215 stw fp,8(sp) + cd50: dc000115 stw r16,4(sp) + cd54: df000104 addi fp,sp,4 + cd58: e13fff15 stw r4,-4(fp) + if (fd > 2) + cd5c: e0bfff17 ldw r2,-4(fp) + cd60: 108000d0 cmplti r2,r2,3 + cd64: 10000f1e bne r2,zero,cda4 + { + alt_fd_list[fd].fd_flags = 0; + cd68: e13fff17 ldw r4,-4(fp) + cd6c: 04000074 movhi r16,1 + cd70: 8403bc04 addi r16,r16,3824 + cd74: 01400304 movi r5,12 + cd78: 0002c240 call 2c24 <__mulsi3> + cd7c: 1405883a add r2,r2,r16 + cd80: 10800204 addi r2,r2,8 + cd84: 10000015 stw zero,0(r2) + alt_fd_list[fd].dev = 0; + cd88: e13fff17 ldw r4,-4(fp) + cd8c: 04000074 movhi r16,1 + cd90: 8403bc04 addi r16,r16,3824 + cd94: 01400304 movi r5,12 + cd98: 0002c240 call 2c24 <__mulsi3> + cd9c: 1405883a add r2,r2,r16 + cda0: 10000015 stw zero,0(r2) + } +} + cda4: e037883a mov sp,fp + cda8: dfc00217 ldw ra,8(sp) + cdac: df000117 ldw fp,4(sp) + cdb0: dc000017 ldw r16,0(sp) + cdb4: dec00304 addi sp,sp,12 + cdb8: f800283a ret + +0000cdbc : +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + cdbc: defff804 addi sp,sp,-32 + cdc0: df000715 stw fp,28(sp) + cdc4: df000704 addi fp,sp,28 + cdc8: e13ffe15 stw r4,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + cdcc: 0005303a rdctl r2,status + cdd0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + cdd4: e0fffb17 ldw r3,-20(fp) + cdd8: 00bfff84 movi r2,-2 + cddc: 1884703a and r2,r3,r2 + cde0: 1001703a wrctl status,r2 + + return context; + cde4: e0bffb17 ldw r2,-20(fp) + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + cde8: e0bffd15 stw r2,-12(fp) + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + cdec: d0a00e17 ldw r2,-32712(gp) + cdf0: 10c000c4 addi r3,r2,3 + cdf4: 00bfff04 movi r2,-4 + cdf8: 1884703a and r2,r3,r2 + cdfc: d0a00e15 stw r2,-32712(gp) + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + ce00: d0e00e17 ldw r3,-32712(gp) + ce04: e0bffe17 ldw r2,-8(fp) + ce08: 1887883a add r3,r3,r2 + ce0c: 008000f4 movhi r2,3 + ce10: 10880004 addi r2,r2,8192 + ce14: 10c0072e bgeu r2,r3,ce34 + ce18: e0bffd17 ldw r2,-12(fp) + ce1c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + ce20: e0bffa17 ldw r2,-24(fp) + ce24: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + return (caddr_t)-1; + ce28: 00bfffc4 movi r2,-1 + ce2c: e0bfff15 stw r2,-4(fp) + ce30: 00000c06 br ce64 + } +#endif + + prev_heap_end = heap_end; + ce34: d0a00e17 ldw r2,-32712(gp) + ce38: e0bffc15 stw r2,-16(fp) + heap_end += incr; + ce3c: d0e00e17 ldw r3,-32712(gp) + ce40: e0bffe17 ldw r2,-8(fp) + ce44: 1885883a add r2,r3,r2 + ce48: d0a00e15 stw r2,-32712(gp) + ce4c: e0bffd17 ldw r2,-12(fp) + ce50: e0bff915 stw r2,-28(fp) + ce54: e0bff917 ldw r2,-28(fp) + ce58: 1001703a wrctl status,r2 + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; + ce5c: e0bffc17 ldw r2,-16(fp) + ce60: e0bfff15 stw r2,-4(fp) + ce64: e0bfff17 ldw r2,-4(fp) +} + ce68: e037883a mov sp,fp + ce6c: df000017 ldw fp,0(sp) + ce70: dec00104 addi sp,sp,4 + ce74: f800283a ret + +0000ce78 : +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us) +#else +unsigned int ALT_USLEEP (unsigned int us) +#endif +{ + ce78: defffd04 addi sp,sp,-12 + ce7c: dfc00215 stw ra,8(sp) + ce80: df000115 stw fp,4(sp) + ce84: df000104 addi fp,sp,4 + ce88: e13fff15 stw r4,-4(fp) + return alt_busy_sleep(us); + ce8c: e13fff17 ldw r4,-4(fp) + ce90: 000eccc0 call eccc +} + ce94: e037883a mov sp,fp + ce98: dfc00117 ldw ra,4(sp) + ce9c: df000017 ldw fp,0(sp) + cea0: dec00204 addi sp,sp,8 + cea4: f800283a ret + +0000cea8 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + cea8: defff704 addi sp,sp,-36 + ceac: dfc00815 stw ra,32(sp) + ceb0: df000715 stw fp,28(sp) + ceb4: df000704 addi fp,sp,28 + ceb8: e13ffb15 stw r4,-20(fp) + cebc: e17ffc15 stw r5,-16(fp) + cec0: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + cec4: e0bffb17 ldw r2,-20(fp) + cec8: 1004803a cmplt r2,r2,zero + cecc: 1000091e bne r2,zero,cef4 + ced0: e13ffb17 ldw r4,-20(fp) + ced4: 01400304 movi r5,12 + ced8: 0002c240 call 2c24 <__mulsi3> + cedc: 1007883a mov r3,r2 + cee0: 00800074 movhi r2,1 + cee4: 1083bc04 addi r2,r2,3824 + cee8: 1887883a add r3,r3,r2 + ceec: e0ffff15 stw r3,-4(fp) + cef0: 00000106 br cef8 + cef4: e03fff15 stw zero,-4(fp) + cef8: e0bfff17 ldw r2,-4(fp) + cefc: e0bffa15 stw r2,-24(fp) + + if (fd) + cf00: e0bffa17 ldw r2,-24(fp) + cf04: 1005003a cmpeq r2,r2,zero + cf08: 1000241e bne r2,zero,cf9c + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + cf0c: e0bffa17 ldw r2,-24(fp) + cf10: 10800217 ldw r2,8(r2) + cf14: 108000cc andi r2,r2,3 + cf18: 1005003a cmpeq r2,r2,zero + cf1c: 10001a1e bne r2,zero,cf88 + cf20: e0bffa17 ldw r2,-24(fp) + cf24: 10800017 ldw r2,0(r2) + cf28: 10800617 ldw r2,24(r2) + cf2c: 1005003a cmpeq r2,r2,zero + cf30: 1000151e bne r2,zero,cf88 + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + cf34: e0bffa17 ldw r2,-24(fp) + cf38: 10800017 ldw r2,0(r2) + cf3c: 10800617 ldw r2,24(r2) + cf40: e17ffc17 ldw r5,-16(fp) + cf44: e1bffd17 ldw r6,-12(fp) + cf48: e13ffa17 ldw r4,-24(fp) + cf4c: 103ee83a callr r2 + cf50: e0bff915 stw r2,-28(fp) + cf54: e0bff917 ldw r2,-28(fp) + cf58: 1004403a cmpge r2,r2,zero + cf5c: 1000071e bne r2,zero,cf7c + { + ALT_ERRNO = -rval; + cf60: 000cfcc0 call cfcc + cf64: e0fff917 ldw r3,-28(fp) + cf68: 00c7c83a sub r3,zero,r3 + cf6c: 10c00015 stw r3,0(r2) + return -1; + cf70: 00bfffc4 movi r2,-1 + cf74: e0bffe15 stw r2,-8(fp) + cf78: 00000e06 br cfb4 + } + return rval; + cf7c: e0bff917 ldw r2,-28(fp) + cf80: e0bffe15 stw r2,-8(fp) + cf84: 00000b06 br cfb4 + } + else + { + ALT_ERRNO = EACCES; + cf88: 000cfcc0 call cfcc + cf8c: 1007883a mov r3,r2 + cf90: 00800344 movi r2,13 + cf94: 18800015 stw r2,0(r3) + cf98: 00000406 br cfac + } + } + else + { + ALT_ERRNO = EBADFD; + cf9c: 000cfcc0 call cfcc + cfa0: 1007883a mov r3,r2 + cfa4: 00801444 movi r2,81 + cfa8: 18800015 stw r2,0(r3) + } + return -1; + cfac: 00bfffc4 movi r2,-1 + cfb0: e0bffe15 stw r2,-8(fp) + cfb4: e0bffe17 ldw r2,-8(fp) +} + cfb8: e037883a mov sp,fp + cfbc: dfc00117 ldw ra,4(sp) + cfc0: df000017 ldw fp,0(sp) + cfc4: dec00204 addi sp,sp,8 + cfc8: f800283a ret + +0000cfcc : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + cfcc: defffd04 addi sp,sp,-12 + cfd0: dfc00215 stw ra,8(sp) + cfd4: df000115 stw fp,4(sp) + cfd8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + cfdc: 00800074 movhi r2,1 + cfe0: 10888904 addi r2,r2,8740 + cfe4: 10800017 ldw r2,0(r2) + cfe8: 1005003a cmpeq r2,r2,zero + cfec: 1000061e bne r2,zero,d008 + cff0: 00800074 movhi r2,1 + cff4: 10888904 addi r2,r2,8740 + cff8: 10800017 ldw r2,0(r2) + cffc: 103ee83a callr r2 + d000: e0bfff15 stw r2,-4(fp) + d004: 00000306 br d014 + d008: 00800074 movhi r2,1 + d00c: 108f7c04 addi r2,r2,15856 + d010: e0bfff15 stw r2,-4(fp) + d014: e0bfff17 ldw r2,-4(fp) +} + d018: e037883a mov sp,fp + d01c: dfc00117 ldw ra,4(sp) + d020: df000017 ldw fp,0(sp) + d024: dec00204 addi sp,sp,8 + d028: f800283a ret + +0000d02c : + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + d02c: defffd04 addi sp,sp,-12 + d030: dfc00215 stw ra,8(sp) + d034: df000115 stw fp,4(sp) + d038: df000104 addi fp,sp,4 + d03c: e13fff15 stw r4,-4(fp) + ALTERA_NIOS2_QSYS_IRQ_INIT ( NIOS2_PROCESSOR, nios2_processor); + d040: 000f8e00 call f8e0 + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK + d044: 00800044 movi r2,1 + d048: 1001703a wrctl status,r2 + alt_irq_cpu_enable_interrupts(); +} + d04c: e037883a mov sp,fp + d050: dfc00117 ldw ra,4(sp) + d054: df000017 ldw fp,0(sp) + d058: dec00204 addi sp,sp,8 + d05c: f800283a ret + +0000d060 : + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + d060: defffe04 addi sp,sp,-8 + d064: dfc00115 stw ra,4(sp) + d068: df000015 stw fp,0(sp) + d06c: d839883a mov fp,sp + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart); + d070: 01000074 movhi r4,1 + d074: 21042604 addi r4,r4,4248 + d078: 000b883a mov r5,zero + d07c: 01800144 movi r6,5 + d080: 000d23c0 call d23c + d084: 01000074 movhi r4,1 + d088: 21041c04 addi r4,r4,4208 + d08c: 000d0bc0 call d0bc + ALTERA_AVALON_LCD_16207_INIT ( LCD_16207_0, lcd_16207_0); + d090: 01000074 movhi r4,1 + d094: 21083e04 addi r4,r4,8440 + d098: 000e9e40 call e9e4 + d09c: 01000074 movhi r4,1 + d0a0: 21083404 addi r4,r4,8400 + d0a4: 000d0bc0 call d0bc +} + d0a8: e037883a mov sp,fp + d0ac: dfc00117 ldw ra,4(sp) + d0b0: df000017 ldw fp,0(sp) + d0b4: dec00204 addi sp,sp,8 + d0b8: f800283a ret + +0000d0bc : + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + d0bc: defffd04 addi sp,sp,-12 + d0c0: dfc00215 stw ra,8(sp) + d0c4: df000115 stw fp,4(sp) + d0c8: df000104 addi fp,sp,4 + d0cc: e13fff15 stw r4,-4(fp) + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); + d0d0: e13fff17 ldw r4,-4(fp) + d0d4: 01400074 movhi r5,1 + d0d8: 29488604 addi r5,r5,8728 + d0dc: 000ee440 call ee44 +} + d0e0: e037883a mov sp,fp + d0e4: dfc00117 ldw ra,4(sp) + d0e8: df000017 ldw fp,0(sp) + d0ec: dec00204 addi sp,sp,8 + d0f0: f800283a ret + +0000d0f4 : + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + d0f4: defffa04 addi sp,sp,-24 + d0f8: dfc00515 stw ra,20(sp) + d0fc: df000415 stw fp,16(sp) + d100: df000404 addi fp,sp,16 + d104: e13ffd15 stw r4,-12(fp) + d108: e17ffe15 stw r5,-8(fp) + d10c: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + d110: e0bffd17 ldw r2,-12(fp) + d114: 10800017 ldw r2,0(r2) + d118: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + d11c: e0bffc17 ldw r2,-16(fp) + d120: 11000a04 addi r4,r2,40 + d124: e0bffd17 ldw r2,-12(fp) + d128: 11c00217 ldw r7,8(r2) + d12c: e17ffe17 ldw r5,-8(fp) + d130: e1bfff17 ldw r6,-4(fp) + d134: 000d73c0 call d73c + fd->fd_flags); +} + d138: e037883a mov sp,fp + d13c: dfc00117 ldw ra,4(sp) + d140: df000017 ldw fp,0(sp) + d144: dec00204 addi sp,sp,8 + d148: f800283a ret + +0000d14c : + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + d14c: defffa04 addi sp,sp,-24 + d150: dfc00515 stw ra,20(sp) + d154: df000415 stw fp,16(sp) + d158: df000404 addi fp,sp,16 + d15c: e13ffd15 stw r4,-12(fp) + d160: e17ffe15 stw r5,-8(fp) + d164: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + d168: e0bffd17 ldw r2,-12(fp) + d16c: 10800017 ldw r2,0(r2) + d170: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + d174: e0bffc17 ldw r2,-16(fp) + d178: 11000a04 addi r4,r2,40 + d17c: e0bffd17 ldw r2,-12(fp) + d180: 11c00217 ldw r7,8(r2) + d184: e17ffe17 ldw r5,-8(fp) + d188: e1bfff17 ldw r6,-4(fp) + d18c: 000d9600 call d960 + fd->fd_flags); +} + d190: e037883a mov sp,fp + d194: dfc00117 ldw ra,4(sp) + d198: df000017 ldw fp,0(sp) + d19c: dec00204 addi sp,sp,8 + d1a0: f800283a ret + +0000d1a4 : + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + d1a4: defffc04 addi sp,sp,-16 + d1a8: dfc00315 stw ra,12(sp) + d1ac: df000215 stw fp,8(sp) + d1b0: df000204 addi fp,sp,8 + d1b4: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + d1b8: e0bfff17 ldw r2,-4(fp) + d1bc: 10800017 ldw r2,0(r2) + d1c0: e0bffe15 stw r2,-8(fp) + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); + d1c4: e0bffe17 ldw r2,-8(fp) + d1c8: 11000a04 addi r4,r2,40 + d1cc: e0bfff17 ldw r2,-4(fp) + d1d0: 11400217 ldw r5,8(r2) + d1d4: 000d5d40 call d5d4 +} + d1d8: e037883a mov sp,fp + d1dc: dfc00117 ldw ra,4(sp) + d1e0: df000017 ldw fp,0(sp) + d1e4: dec00204 addi sp,sp,8 + d1e8: f800283a ret + +0000d1ec : + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + d1ec: defffa04 addi sp,sp,-24 + d1f0: dfc00515 stw ra,20(sp) + d1f4: df000415 stw fp,16(sp) + d1f8: df000404 addi fp,sp,16 + d1fc: e13ffd15 stw r4,-12(fp) + d200: e17ffe15 stw r5,-8(fp) + d204: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + d208: e0bffd17 ldw r2,-12(fp) + d20c: 10800017 ldw r2,0(r2) + d210: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); + d214: e0bffc17 ldw r2,-16(fp) + d218: 11000a04 addi r4,r2,40 + d21c: e17ffe17 ldw r5,-8(fp) + d220: e1bfff17 ldw r6,-4(fp) + d224: 000d6480 call d648 +} + d228: e037883a mov sp,fp + d22c: dfc00117 ldw ra,4(sp) + d230: df000017 ldw fp,0(sp) + d234: dec00204 addi sp,sp,8 + d238: f800283a ret + +0000d23c : + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + d23c: defffa04 addi sp,sp,-24 + d240: dfc00515 stw ra,20(sp) + d244: df000415 stw fp,16(sp) + d248: df000404 addi fp,sp,16 + d24c: e13ffd15 stw r4,-12(fp) + d250: e17ffe15 stw r5,-8(fp) + d254: e1bfff15 stw r6,-4(fp) + ALT_FLAG_CREATE(&sp->events, 0); + ALT_SEM_CREATE(&sp->read_lock, 1); + ALT_SEM_CREATE(&sp->write_lock, 1); + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + d258: e0fffd17 ldw r3,-12(fp) + d25c: 00800044 movi r2,1 + d260: 18800815 stw r2,32(r3) + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + d264: e0bffd17 ldw r2,-12(fp) + d268: 10800017 ldw r2,0(r2) + d26c: 11000104 addi r4,r2,4 + d270: e0bffd17 ldw r2,-12(fp) + d274: 10800817 ldw r2,32(r2) + d278: 1007883a mov r3,r2 + d27c: 2005883a mov r2,r4 + d280: 10c00035 stwio r3,0(r2) + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + d284: e13ffe17 ldw r4,-8(fp) + d288: e17fff17 ldw r5,-4(fp) + d28c: d8000015 stw zero,0(sp) + d290: 01800074 movhi r6,1 + d294: 31b4bf04 addi r6,r6,-11524 + d298: e1fffd17 ldw r7,-12(fp) + d29c: 000f03c0 call f03c +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + d2a0: e0bffd17 ldw r2,-12(fp) + d2a4: 10000915 stw zero,36(r2) + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + d2a8: e0bffd17 ldw r2,-12(fp) + d2ac: 11000204 addi r4,r2,8 + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + d2b0: 00800074 movhi r2,1 + d2b4: 108f8104 addi r2,r2,15876 + d2b8: 10800017 ldw r2,0(r2) + d2bc: 100b883a mov r5,r2 + d2c0: 01800074 movhi r6,1 + d2c4: 31b54904 addi r6,r6,-10972 + d2c8: e1fffd17 ldw r7,-12(fp) + d2cc: 000eb780 call eb78 + d2d0: 1004403a cmpge r2,r2,zero + d2d4: 1000041e bne r2,zero,d2e8 + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + d2d8: e0fffd17 ldw r3,-12(fp) + d2dc: 00a00034 movhi r2,32768 + d2e0: 10bfffc4 addi r2,r2,-1 + d2e4: 18800115 stw r2,4(r3) + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + d2e8: e037883a mov sp,fp + d2ec: dfc00117 ldw ra,4(sp) + d2f0: df000017 ldw fp,0(sp) + d2f4: dec00204 addi sp,sp,8 + d2f8: f800283a ret + +0000d2fc : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + d2fc: defff804 addi sp,sp,-32 + d300: df000715 stw fp,28(sp) + d304: df000704 addi fp,sp,28 + d308: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + d30c: e0bfff17 ldw r2,-4(fp) + d310: e0bffe15 stw r2,-8(fp) + unsigned int base = sp->base; + d314: e0bffe17 ldw r2,-8(fp) + d318: 10800017 ldw r2,0(r2) + d31c: e0bffd15 stw r2,-12(fp) + d320: 00000006 br d324 + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + d324: e0bffd17 ldw r2,-12(fp) + d328: 10800104 addi r2,r2,4 + d32c: 10800037 ldwio r2,0(r2) + d330: e0bffc15 stw r2,-16(fp) + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + d334: e0bffc17 ldw r2,-16(fp) + d338: 1080c00c andi r2,r2,768 + d33c: 1005003a cmpeq r2,r2,zero + d340: 1000741e bne r2,zero,d514 + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + d344: e0bffc17 ldw r2,-16(fp) + d348: 1080400c andi r2,r2,256 + d34c: 1005003a cmpeq r2,r2,zero + d350: 1000351e bne r2,zero,d428 + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + d354: 00800074 movhi r2,1 + d358: e0bffb15 stw r2,-20(fp) + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + d35c: e0bffe17 ldw r2,-8(fp) + d360: 10800a17 ldw r2,40(r2) + d364: 10800044 addi r2,r2,1 + d368: 1081ffcc andi r2,r2,2047 + d36c: e0bffa15 stw r2,-24(fp) + if (next == sp->rx_out) + d370: e0bffe17 ldw r2,-8(fp) + d374: 10c00b17 ldw r3,44(r2) + d378: e0bffa17 ldw r2,-24(fp) + d37c: 18801626 beq r3,r2,d3d8 + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + d380: e0bffd17 ldw r2,-12(fp) + d384: 10800037 ldwio r2,0(r2) + d388: e0bffb15 stw r2,-20(fp) + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + d38c: e0bffb17 ldw r2,-20(fp) + d390: 10a0000c andi r2,r2,32768 + d394: 1005003a cmpeq r2,r2,zero + d398: 10000f1e bne r2,zero,d3d8 + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + d39c: e0bffe17 ldw r2,-8(fp) + d3a0: 10c00a17 ldw r3,40(r2) + d3a4: e0bffb17 ldw r2,-20(fp) + d3a8: 1009883a mov r4,r2 + d3ac: e0bffe17 ldw r2,-8(fp) + d3b0: 1885883a add r2,r3,r2 + d3b4: 10800e04 addi r2,r2,56 + d3b8: 11000005 stb r4,0(r2) + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + d3bc: e0bffe17 ldw r2,-8(fp) + d3c0: 10800a17 ldw r2,40(r2) + d3c4: 10800044 addi r2,r2,1 + d3c8: 10c1ffcc andi r3,r2,2047 + d3cc: e0bffe17 ldw r2,-8(fp) + d3d0: 10c00a15 stw r3,40(r2) + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + } + d3d4: 003fe106 br d35c + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + d3d8: e0bffb17 ldw r2,-20(fp) + d3dc: 10bfffec andhi r2,r2,65535 + d3e0: 1005003a cmpeq r2,r2,zero + d3e4: 1000101e bne r2,zero,d428 + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + d3e8: e0bffe17 ldw r2,-8(fp) + d3ec: 10c00817 ldw r3,32(r2) + d3f0: 00bfff84 movi r2,-2 + d3f4: 1886703a and r3,r3,r2 + d3f8: e0bffe17 ldw r2,-8(fp) + d3fc: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + d400: e0bffd17 ldw r2,-12(fp) + d404: 11000104 addi r4,r2,4 + d408: e0bffe17 ldw r2,-8(fp) + d40c: 10800817 ldw r2,32(r2) + d410: 1007883a mov r3,r2 + d414: 2005883a mov r2,r4 + d418: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + d41c: e0bffd17 ldw r2,-12(fp) + d420: 10800104 addi r2,r2,4 + d424: 10800037 ldwio r2,0(r2) + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + d428: e0bffc17 ldw r2,-16(fp) + d42c: 1080800c andi r2,r2,512 + d430: 1005003a cmpeq r2,r2,zero + d434: 103fbb1e bne r2,zero,d324 + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + d438: e0bffc17 ldw r2,-16(fp) + d43c: 10bfffec andhi r2,r2,65535 + d440: 1004d43a srli r2,r2,16 + d444: e0bff915 stw r2,-28(fp) + + while (space > 0 && sp->tx_out != sp->tx_in) + d448: 00001506 br d4a0 + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + d44c: e13ffd17 ldw r4,-12(fp) + d450: e0bffe17 ldw r2,-8(fp) + d454: 10c00d17 ldw r3,52(r2) + d458: e0bffe17 ldw r2,-8(fp) + d45c: 1885883a add r2,r3,r2 + d460: 10820e04 addi r2,r2,2104 + d464: 10800003 ldbu r2,0(r2) + d468: 10c03fcc andi r3,r2,255 + d46c: 18c0201c xori r3,r3,128 + d470: 18ffe004 addi r3,r3,-128 + d474: 2005883a mov r2,r4 + d478: 10c00035 stwio r3,0(r2) + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + d47c: e0bffe17 ldw r2,-8(fp) + d480: 10800d17 ldw r2,52(r2) + d484: 10800044 addi r2,r2,1 + d488: 10c1ffcc andi r3,r2,2047 + d48c: e0bffe17 ldw r2,-8(fp) + d490: 10c00d15 stw r3,52(r2) + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + d494: e0bff917 ldw r2,-28(fp) + d498: 10bfffc4 addi r2,r2,-1 + d49c: e0bff915 stw r2,-28(fp) + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + d4a0: e0bff917 ldw r2,-28(fp) + d4a4: 1005003a cmpeq r2,r2,zero + d4a8: 1000051e bne r2,zero,d4c0 + d4ac: e0bffe17 ldw r2,-8(fp) + d4b0: 10c00d17 ldw r3,52(r2) + d4b4: e0bffe17 ldw r2,-8(fp) + d4b8: 10800c17 ldw r2,48(r2) + d4bc: 18bfe31e bne r3,r2,d44c + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + d4c0: e0bff917 ldw r2,-28(fp) + d4c4: 1005003a cmpeq r2,r2,zero + d4c8: 103f961e bne r2,zero,d324 + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + d4cc: e0bffe17 ldw r2,-8(fp) + d4d0: 10c00817 ldw r3,32(r2) + d4d4: 00bfff44 movi r2,-3 + d4d8: 1886703a and r3,r3,r2 + d4dc: e0bffe17 ldw r2,-8(fp) + d4e0: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + d4e4: e0bffe17 ldw r2,-8(fp) + d4e8: 10800017 ldw r2,0(r2) + d4ec: 11000104 addi r4,r2,4 + d4f0: e0bffe17 ldw r2,-8(fp) + d4f4: 10800817 ldw r2,32(r2) + d4f8: 1007883a mov r3,r2 + d4fc: 2005883a mov r2,r4 + d500: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + d504: e0bffd17 ldw r2,-12(fp) + d508: 10800104 addi r2,r2,4 + d50c: 10800037 ldwio r2,0(r2) + } + } + } + d510: 003f8406 br d324 +} + d514: e037883a mov sp,fp + d518: df000017 ldw fp,0(sp) + d51c: dec00104 addi sp,sp,4 + d520: f800283a ret + +0000d524 : + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + d524: defffc04 addi sp,sp,-16 + d528: df000315 stw fp,12(sp) + d52c: df000304 addi fp,sp,12 + d530: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + d534: e0bfff17 ldw r2,-4(fp) + d538: e0bffe15 stw r2,-8(fp) + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + d53c: e0bffe17 ldw r2,-8(fp) + d540: 10800017 ldw r2,0(r2) + d544: 10800104 addi r2,r2,4 + d548: 10800037 ldwio r2,0(r2) + d54c: e0bffd15 stw r2,-12(fp) + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + d550: e0bffd17 ldw r2,-12(fp) + d554: 1081000c andi r2,r2,1024 + d558: 1005003a cmpeq r2,r2,zero + d55c: 10000c1e bne r2,zero,d590 + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + d560: e0bffe17 ldw r2,-8(fp) + d564: 10800017 ldw r2,0(r2) + d568: 11000104 addi r4,r2,4 + d56c: e0bffe17 ldw r2,-8(fp) + d570: 10800817 ldw r2,32(r2) + d574: 10810014 ori r2,r2,1024 + d578: 1007883a mov r3,r2 + d57c: 2005883a mov r2,r4 + d580: 10c00035 stwio r3,0(r2) + sp->host_inactive = 0; + d584: e0bffe17 ldw r2,-8(fp) + d588: 10000915 stw zero,36(r2) + d58c: 00000a06 br d5b8 + } + else if (sp->host_inactive < INT_MAX - 2) { + d590: e0bffe17 ldw r2,-8(fp) + d594: 10c00917 ldw r3,36(r2) + d598: 00a00034 movhi r2,32768 + d59c: 10bfff04 addi r2,r2,-4 + d5a0: 10c00536 bltu r2,r3,d5b8 + sp->host_inactive++; + d5a4: e0bffe17 ldw r2,-8(fp) + d5a8: 10800917 ldw r2,36(r2) + d5ac: 10c00044 addi r3,r2,1 + d5b0: e0bffe17 ldw r2,-8(fp) + d5b4: 10c00915 stw r3,36(r2) + d5b8: 00800074 movhi r2,1 + d5bc: 108f8104 addi r2,r2,15876 + d5c0: 10800017 ldw r2,0(r2) + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + } + } + + return alt_ticks_per_second(); +} + d5c4: e037883a mov sp,fp + d5c8: df000017 ldw fp,0(sp) + d5cc: dec00104 addi sp,sp,4 + d5d0: f800283a ret + +0000d5d4 : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + d5d4: defffc04 addi sp,sp,-16 + d5d8: df000315 stw fp,12(sp) + d5dc: df000304 addi fp,sp,12 + d5e0: e13ffd15 stw r4,-12(fp) + d5e4: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + d5e8: 00000706 br d608 + if (flags & O_NONBLOCK) { + d5ec: e0bffe17 ldw r2,-8(fp) + d5f0: 1090000c andi r2,r2,16384 + d5f4: 1005003a cmpeq r2,r2,zero + d5f8: 1000031e bne r2,zero,d608 + return -EWOULDBLOCK; + d5fc: 00bffd44 movi r2,-11 + d600: e0bfff15 stw r2,-4(fp) + d604: 00000b06 br d634 +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + d608: e0bffd17 ldw r2,-12(fp) + d60c: 10c00d17 ldw r3,52(r2) + d610: e0bffd17 ldw r2,-12(fp) + d614: 10800c17 ldw r2,48(r2) + d618: 18800526 beq r3,r2,d630 + d61c: e0bffd17 ldw r2,-12(fp) + d620: 10c00917 ldw r3,36(r2) + d624: e0bffd17 ldw r2,-12(fp) + d628: 10800117 ldw r2,4(r2) + d62c: 18bfef36 bltu r3,r2,d5ec + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + d630: e03fff15 stw zero,-4(fp) + d634: e0bfff17 ldw r2,-4(fp) +} + d638: e037883a mov sp,fp + d63c: df000017 ldw fp,0(sp) + d640: dec00104 addi sp,sp,4 + d644: f800283a ret + +0000d648 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + d648: defff804 addi sp,sp,-32 + d64c: df000715 stw fp,28(sp) + d650: df000704 addi fp,sp,28 + d654: e13ffb15 stw r4,-20(fp) + d658: e17ffc15 stw r5,-16(fp) + d65c: e1bffd15 stw r6,-12(fp) + int rc = -ENOTTY; + d660: 00bff9c4 movi r2,-25 + d664: e0bffa15 stw r2,-24(fp) + + switch (req) + d668: e0bffc17 ldw r2,-16(fp) + d66c: e0bfff15 stw r2,-4(fp) + d670: e0ffff17 ldw r3,-4(fp) + d674: 189a8060 cmpeqi r2,r3,27137 + d678: 1000041e bne r2,zero,d68c + d67c: e0ffff17 ldw r3,-4(fp) + d680: 189a80a0 cmpeqi r2,r3,27138 + d684: 10001b1e bne r2,zero,d6f4 + d688: 00002706 br d728 + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + d68c: e0bffb17 ldw r2,-20(fp) + d690: 10c00117 ldw r3,4(r2) + d694: 00a00034 movhi r2,32768 + d698: 10bfffc4 addi r2,r2,-1 + d69c: 18802226 beq r3,r2,d728 + { + int timeout = *((int *)arg); + d6a0: e0bffd17 ldw r2,-12(fp) + d6a4: 10800017 ldw r2,0(r2) + d6a8: e0bff915 stw r2,-28(fp) + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + d6ac: e0bff917 ldw r2,-28(fp) + d6b0: 10800090 cmplti r2,r2,2 + d6b4: 1000071e bne r2,zero,d6d4 + d6b8: e0fff917 ldw r3,-28(fp) + d6bc: 00a00034 movhi r2,32768 + d6c0: 10bfffc4 addi r2,r2,-1 + d6c4: 18800326 beq r3,r2,d6d4 + d6c8: e0bff917 ldw r2,-28(fp) + d6cc: e0bffe15 stw r2,-8(fp) + d6d0: 00000306 br d6e0 + d6d4: 00e00034 movhi r3,32768 + d6d8: 18ffff84 addi r3,r3,-2 + d6dc: e0fffe15 stw r3,-8(fp) + d6e0: e0bffb17 ldw r2,-20(fp) + d6e4: e0fffe17 ldw r3,-8(fp) + d6e8: 10c00115 stw r3,4(r2) + rc = 0; + d6ec: e03ffa15 stw zero,-24(fp) + } + break; + d6f0: 00000d06 br d728 + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + d6f4: e0bffb17 ldw r2,-20(fp) + d6f8: 10c00117 ldw r3,4(r2) + d6fc: 00a00034 movhi r2,32768 + d700: 10bfffc4 addi r2,r2,-1 + d704: 18800826 beq r3,r2,d728 + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + d708: e13ffd17 ldw r4,-12(fp) + d70c: e0bffb17 ldw r2,-20(fp) + d710: 10c00917 ldw r3,36(r2) + d714: e0bffb17 ldw r2,-20(fp) + d718: 10800117 ldw r2,4(r2) + d71c: 1885803a cmpltu r2,r3,r2 + d720: 20800015 stw r2,0(r4) + rc = 0; + d724: e03ffa15 stw zero,-24(fp) + + default: + break; + } + + return rc; + d728: e0bffa17 ldw r2,-24(fp) +} + d72c: e037883a mov sp,fp + d730: df000017 ldw fp,0(sp) + d734: dec00104 addi sp,sp,4 + d738: f800283a ret + +0000d73c : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + d73c: defff204 addi sp,sp,-56 + d740: dfc00d15 stw ra,52(sp) + d744: df000c15 stw fp,48(sp) + d748: df000c04 addi fp,sp,48 + d74c: e13ffb15 stw r4,-20(fp) + d750: e17ffc15 stw r5,-16(fp) + d754: e1bffd15 stw r6,-12(fp) + d758: e1fffe15 stw r7,-8(fp) + char * ptr = buffer; + d75c: e0bffc17 ldw r2,-16(fp) + d760: e0bffa15 stw r2,-24(fp) + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + d764: 00004806 br d888 + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + d768: e0bffb17 ldw r2,-20(fp) + d76c: 10800a17 ldw r2,40(r2) + d770: e0bff715 stw r2,-36(fp) + out = sp->rx_out; + d774: e0bffb17 ldw r2,-20(fp) + d778: 10800b17 ldw r2,44(r2) + d77c: e0bff615 stw r2,-40(fp) + + if (in >= out) + d780: e0fff717 ldw r3,-36(fp) + d784: e0bff617 ldw r2,-40(fp) + d788: 18800536 bltu r3,r2,d7a0 + n = in - out; + d78c: e0bff717 ldw r2,-36(fp) + d790: e0fff617 ldw r3,-40(fp) + d794: 10c5c83a sub r2,r2,r3 + d798: e0bff815 stw r2,-32(fp) + d79c: 00000406 br d7b0 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + d7a0: 00820004 movi r2,2048 + d7a4: e0fff617 ldw r3,-40(fp) + d7a8: 10c5c83a sub r2,r2,r3 + d7ac: e0bff815 stw r2,-32(fp) + + if (n == 0) + d7b0: e0bff817 ldw r2,-32(fp) + d7b4: 1005003a cmpeq r2,r2,zero + d7b8: 10001f1e bne r2,zero,d838 + break; /* No more data available */ + + if (n > space) + d7bc: e0fffd17 ldw r3,-12(fp) + d7c0: e0bff817 ldw r2,-32(fp) + d7c4: 1880022e bgeu r3,r2,d7d0 + n = space; + d7c8: e0bffd17 ldw r2,-12(fp) + d7cc: e0bff815 stw r2,-32(fp) + + memcpy(ptr, sp->rx_buf + out, n); + d7d0: e0bffb17 ldw r2,-20(fp) + d7d4: 10c00e04 addi r3,r2,56 + d7d8: e0bff617 ldw r2,-40(fp) + d7dc: 1887883a add r3,r3,r2 + d7e0: e0bffa17 ldw r2,-24(fp) + d7e4: 1009883a mov r4,r2 + d7e8: 180b883a mov r5,r3 + d7ec: e1bff817 ldw r6,-32(fp) + d7f0: 00080140 call 8014 + ptr += n; + d7f4: e0fff817 ldw r3,-32(fp) + d7f8: e0bffa17 ldw r2,-24(fp) + d7fc: 10c5883a add r2,r2,r3 + d800: e0bffa15 stw r2,-24(fp) + space -= n; + d804: e0fffd17 ldw r3,-12(fp) + d808: e0bff817 ldw r2,-32(fp) + d80c: 1885c83a sub r2,r3,r2 + d810: e0bffd15 stw r2,-12(fp) + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + d814: e0fff617 ldw r3,-40(fp) + d818: e0bff817 ldw r2,-32(fp) + d81c: 1885883a add r2,r3,r2 + d820: 10c1ffcc andi r3,r2,2047 + d824: e0bffb17 ldw r2,-20(fp) + d828: 10c00b15 stw r3,44(r2) + } + while (space > 0); + d82c: e0bffd17 ldw r2,-12(fp) + d830: 10800048 cmpgei r2,r2,1 + d834: 103fcc1e bne r2,zero,d768 + + /* If we read any data then return it */ + if (ptr != buffer) + d838: e0fffa17 ldw r3,-24(fp) + d83c: e0bffc17 ldw r2,-16(fp) + d840: 1880141e bne r3,r2,d894 + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + d844: e0bffe17 ldw r2,-8(fp) + d848: 1090000c andi r2,r2,16384 + d84c: 1004c03a cmpne r2,r2,zero + d850: 1000101e bne r2,zero,d894 + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; + } +#else + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + d854: e0bffb17 ldw r2,-20(fp) + d858: 10c00a17 ldw r3,40(r2) + d85c: e0bff717 ldw r2,-36(fp) + d860: 1880051e bne r3,r2,d878 + d864: e0bffb17 ldw r2,-20(fp) + d868: 10c00917 ldw r3,36(r2) + d86c: e0bffb17 ldw r2,-20(fp) + d870: 10800117 ldw r2,4(r2) + d874: 18bff736 bltu r3,r2,d854 + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + d878: e0bffb17 ldw r2,-20(fp) + d87c: 10c00a17 ldw r3,40(r2) + d880: e0bff717 ldw r2,-36(fp) + d884: 18800326 beq r3,r2,d894 + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + d888: e0bffd17 ldw r2,-12(fp) + d88c: 10800048 cmpgei r2,r2,1 + d890: 103fb51e bne r2,zero,d768 + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + if (ptr != buffer) + d894: e0fffa17 ldw r3,-24(fp) + d898: e0bffc17 ldw r2,-16(fp) + d89c: 18801926 beq r3,r2,d904 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + d8a0: 0005303a rdctl r2,status + d8a4: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + d8a8: e0fff517 ldw r3,-44(fp) + d8ac: 00bfff84 movi r2,-2 + d8b0: 1884703a and r2,r3,r2 + d8b4: 1001703a wrctl status,r2 + + return context; + d8b8: e0bff517 ldw r2,-44(fp) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + d8bc: e0bff915 stw r2,-28(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + d8c0: e0bffb17 ldw r2,-20(fp) + d8c4: 10800817 ldw r2,32(r2) + d8c8: 10c00054 ori r3,r2,1 + d8cc: e0bffb17 ldw r2,-20(fp) + d8d0: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + d8d4: e0bffb17 ldw r2,-20(fp) + d8d8: 10800017 ldw r2,0(r2) + d8dc: 11000104 addi r4,r2,4 + d8e0: e0bffb17 ldw r2,-20(fp) + d8e4: 10800817 ldw r2,32(r2) + d8e8: 1007883a mov r3,r2 + d8ec: 2005883a mov r2,r4 + d8f0: 10c00035 stwio r3,0(r2) + d8f4: e0bff917 ldw r2,-28(fp) + d8f8: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + d8fc: e0bff417 ldw r2,-48(fp) + d900: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + } + + if (ptr != buffer) + d904: e0fffa17 ldw r3,-24(fp) + d908: e0bffc17 ldw r2,-16(fp) + d90c: 18800526 beq r3,r2,d924 + return ptr - buffer; + d910: e0fffa17 ldw r3,-24(fp) + d914: e0bffc17 ldw r2,-16(fp) + d918: 1887c83a sub r3,r3,r2 + d91c: e0ffff15 stw r3,-4(fp) + d920: 00000906 br d948 + else if (flags & O_NONBLOCK) + d924: e0bffe17 ldw r2,-8(fp) + d928: 1090000c andi r2,r2,16384 + d92c: 1005003a cmpeq r2,r2,zero + d930: 1000031e bne r2,zero,d940 + return -EWOULDBLOCK; + d934: 00bffd44 movi r2,-11 + d938: e0bfff15 stw r2,-4(fp) + d93c: 00000206 br d948 + else + return -EIO; + d940: 00bffec4 movi r2,-5 + d944: e0bfff15 stw r2,-4(fp) + d948: e0bfff17 ldw r2,-4(fp) +} + d94c: e037883a mov sp,fp + d950: dfc00117 ldw ra,4(sp) + d954: df000017 ldw fp,0(sp) + d958: dec00204 addi sp,sp,8 + d95c: f800283a ret + +0000d960 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + d960: defff204 addi sp,sp,-56 + d964: dfc00d15 stw ra,52(sp) + d968: df000c15 stw fp,48(sp) + d96c: df000c04 addi fp,sp,48 + d970: e13ffb15 stw r4,-20(fp) + d974: e17ffc15 stw r5,-16(fp) + d978: e1bffd15 stw r6,-12(fp) + d97c: e1fffe15 stw r7,-8(fp) + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + d980: e03ff915 stw zero,-28(fp) + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + d984: e0bffc17 ldw r2,-16(fp) + d988: e0bff615 stw r2,-40(fp) + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + d98c: 00003a06 br da78 + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + d990: e0bffb17 ldw r2,-20(fp) + d994: 10800c17 ldw r2,48(r2) + d998: e0bffa15 stw r2,-24(fp) + out = sp->tx_out; + d99c: e0bffb17 ldw r2,-20(fp) + d9a0: 10800d17 ldw r2,52(r2) + d9a4: e0bff915 stw r2,-28(fp) + + if (in < out) + d9a8: e0fffa17 ldw r3,-24(fp) + d9ac: e0bff917 ldw r2,-28(fp) + d9b0: 1880062e bgeu r3,r2,d9cc + n = out - 1 - in; + d9b4: e0fff917 ldw r3,-28(fp) + d9b8: e0bffa17 ldw r2,-24(fp) + d9bc: 1885c83a sub r2,r3,r2 + d9c0: 10bfffc4 addi r2,r2,-1 + d9c4: e0bff815 stw r2,-32(fp) + d9c8: 00000c06 br d9fc + else if (out > 0) + d9cc: e0bff917 ldw r2,-28(fp) + d9d0: 1005003a cmpeq r2,r2,zero + d9d4: 1000051e bne r2,zero,d9ec + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + d9d8: 00820004 movi r2,2048 + d9dc: e0fffa17 ldw r3,-24(fp) + d9e0: 10c5c83a sub r2,r2,r3 + d9e4: e0bff815 stw r2,-32(fp) + d9e8: 00000406 br d9fc + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + d9ec: 0081ffc4 movi r2,2047 + d9f0: e0fffa17 ldw r3,-24(fp) + d9f4: 10c5c83a sub r2,r2,r3 + d9f8: e0bff815 stw r2,-32(fp) + + if (n == 0) + d9fc: e0bff817 ldw r2,-32(fp) + da00: 1005003a cmpeq r2,r2,zero + da04: 10001f1e bne r2,zero,da84 + break; + + if (n > count) + da08: e0fffd17 ldw r3,-12(fp) + da0c: e0bff817 ldw r2,-32(fp) + da10: 1880022e bgeu r3,r2,da1c + n = count; + da14: e0bffd17 ldw r2,-12(fp) + da18: e0bff815 stw r2,-32(fp) + + memcpy(sp->tx_buf + in, ptr, n); + da1c: e0bffb17 ldw r2,-20(fp) + da20: 10c20e04 addi r3,r2,2104 + da24: e0bffa17 ldw r2,-24(fp) + da28: 1885883a add r2,r3,r2 + da2c: e0fffc17 ldw r3,-16(fp) + da30: 1009883a mov r4,r2 + da34: 180b883a mov r5,r3 + da38: e1bff817 ldw r6,-32(fp) + da3c: 00080140 call 8014 + ptr += n; + da40: e0fff817 ldw r3,-32(fp) + da44: e0bffc17 ldw r2,-16(fp) + da48: 10c5883a add r2,r2,r3 + da4c: e0bffc15 stw r2,-16(fp) + count -= n; + da50: e0fffd17 ldw r3,-12(fp) + da54: e0bff817 ldw r2,-32(fp) + da58: 1885c83a sub r2,r3,r2 + da5c: e0bffd15 stw r2,-12(fp) + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + da60: e0fffa17 ldw r3,-24(fp) + da64: e0bff817 ldw r2,-32(fp) + da68: 1885883a add r2,r3,r2 + da6c: 10c1ffcc andi r3,r2,2047 + da70: e0bffb17 ldw r2,-20(fp) + da74: 10c00c15 stw r3,48(r2) + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + da78: e0bffd17 ldw r2,-12(fp) + da7c: 10800048 cmpgei r2,r2,1 + da80: 103fc31e bne r2,zero,d990 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + da84: 0005303a rdctl r2,status + da88: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + da8c: e0fff517 ldw r3,-44(fp) + da90: 00bfff84 movi r2,-2 + da94: 1884703a and r2,r3,r2 + da98: 1001703a wrctl status,r2 + + return context; + da9c: e0bff517 ldw r2,-44(fp) + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + daa0: e0bff715 stw r2,-36(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + daa4: e0bffb17 ldw r2,-20(fp) + daa8: 10800817 ldw r2,32(r2) + daac: 10c00094 ori r3,r2,2 + dab0: e0bffb17 ldw r2,-20(fp) + dab4: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + dab8: e0bffb17 ldw r2,-20(fp) + dabc: 10800017 ldw r2,0(r2) + dac0: 11000104 addi r4,r2,4 + dac4: e0bffb17 ldw r2,-20(fp) + dac8: 10800817 ldw r2,32(r2) + dacc: 1007883a mov r3,r2 + dad0: 2005883a mov r2,r4 + dad4: 10c00035 stwio r3,0(r2) + dad8: e0bff717 ldw r2,-36(fp) + dadc: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + dae0: e0bff417 ldw r2,-48(fp) + dae4: 1001703a wrctl status,r2 + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + dae8: e0bffd17 ldw r2,-12(fp) + daec: 10800050 cmplti r2,r2,1 + daf0: 1000111e bne r2,zero,db38 + { + if (flags & O_NONBLOCK) + daf4: e0bffe17 ldw r2,-8(fp) + daf8: 1090000c andi r2,r2,16384 + dafc: 1004c03a cmpne r2,r2,zero + db00: 1000101e bne r2,zero,db44 + /* + * No OS present: Always wait for data to be removed from buffer. Once + * the interrupt routine has removed some data then we will be able to + * insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + db04: e0bffb17 ldw r2,-20(fp) + db08: 10c00d17 ldw r3,52(r2) + db0c: e0bff917 ldw r2,-28(fp) + db10: 1880051e bne r3,r2,db28 + db14: e0bffb17 ldw r2,-20(fp) + db18: 10c00917 ldw r3,36(r2) + db1c: e0bffb17 ldw r2,-20(fp) + db20: 10800117 ldw r2,4(r2) + db24: 18bff736 bltu r3,r2,db04 + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + db28: e0bffb17 ldw r2,-20(fp) + db2c: 10c00d17 ldw r3,52(r2) + db30: e0bff917 ldw r2,-28(fp) + db34: 18800326 beq r3,r2,db44 + break; + } + } + while (count > 0); + db38: e0bffd17 ldw r2,-12(fp) + db3c: 10800048 cmpgei r2,r2,1 + db40: 103fcd1e bne r2,zero,da78 + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + + if (ptr != start) + db44: e0fffc17 ldw r3,-16(fp) + db48: e0bff617 ldw r2,-40(fp) + db4c: 18800526 beq r3,r2,db64 + return ptr - start; + db50: e0fffc17 ldw r3,-16(fp) + db54: e0bff617 ldw r2,-40(fp) + db58: 1887c83a sub r3,r3,r2 + db5c: e0ffff15 stw r3,-4(fp) + db60: 00000906 br db88 + else if (flags & O_NONBLOCK) + db64: e0bffe17 ldw r2,-8(fp) + db68: 1090000c andi r2,r2,16384 + db6c: 1005003a cmpeq r2,r2,zero + db70: 1000031e bne r2,zero,db80 + return -EWOULDBLOCK; + db74: 00bffd44 movi r2,-11 + db78: e0bfff15 stw r2,-4(fp) + db7c: 00000206 br db88 + sp->tx_out = sp->tx_in = 0; + return ptr - start + count; + } +#endif + else + return -EIO; /* Host not connected */ + db80: 00bffec4 movi r2,-5 + db84: e0bfff15 stw r2,-4(fp) + db88: e0bfff17 ldw r2,-4(fp) +} + db8c: e037883a mov sp,fp + db90: dfc00117 ldw ra,4(sp) + db94: df000017 ldw fp,0(sp) + db98: dec00204 addi sp,sp,8 + db9c: f800283a ret + +0000dba0 : + +/* --------------------------------------------------------------------- */ + +static void lcd_write_command(altera_avalon_lcd_16207_state* sp, + unsigned char command) +{ + dba0: defffa04 addi sp,sp,-24 + dba4: dfc00515 stw ra,20(sp) + dba8: df000415 stw fp,16(sp) + dbac: df000404 addi fp,sp,16 + dbb0: e13ffe15 stw r4,-8(fp) + dbb4: e17fff05 stb r5,-4(fp) + unsigned int base = sp->base; + dbb8: e0bffe17 ldw r2,-8(fp) + dbbc: 10800017 ldw r2,0(r2) + dbc0: e0bffd15 stw r2,-12(fp) + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + dbc4: 008003f4 movhi r2,15 + dbc8: 10909004 addi r2,r2,16960 + dbcc: e0bffc15 stw r2,-16(fp) + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + dbd0: e0bffe17 ldw r2,-8(fp) + dbd4: 10800803 ldbu r2,32(r2) + dbd8: 10803fcc andi r2,r2,255 + dbdc: 1080201c xori r2,r2,128 + dbe0: 10bfe004 addi r2,r2,-128 + dbe4: 1004c03a cmpne r2,r2,zero + dbe8: 1000161e bne r2,zero,dc44 + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + dbec: 00000a06 br dc18 + if (--i == 0) + dbf0: e0bffc17 ldw r2,-16(fp) + dbf4: 10bfffc4 addi r2,r2,-1 + dbf8: e0bffc15 stw r2,-16(fp) + dbfc: e0bffc17 ldw r2,-16(fp) + dc00: 1004c03a cmpne r2,r2,zero + dc04: 1000041e bne r2,zero,dc18 + { + sp->broken = 1; + dc08: e0fffe17 ldw r3,-8(fp) + dc0c: 00800044 movi r2,1 + dc10: 18800805 stb r2,32(r3) + return; + dc14: 00000b06 br dc44 + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + dc18: e0bffd17 ldw r2,-12(fp) + dc1c: 10800104 addi r2,r2,4 + dc20: 10800037 ldwio r2,0(r2) + dc24: 1080200c andi r2,r2,128 + dc28: 1004c03a cmpne r2,r2,zero + dc2c: 103ff01e bne r2,zero,dbf0 + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + dc30: 01001904 movi r4,100 + dc34: 000ce780 call ce78 + + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, command); + dc38: e0bffd17 ldw r2,-12(fp) + dc3c: e0ffff03 ldbu r3,-4(fp) + dc40: 10c00035 stwio r3,0(r2) +} + dc44: e037883a mov sp,fp + dc48: dfc00117 ldw ra,4(sp) + dc4c: df000017 ldw fp,0(sp) + dc50: dec00204 addi sp,sp,8 + dc54: f800283a ret + +0000dc58 : + +/* --------------------------------------------------------------------- */ + +static void lcd_write_data(altera_avalon_lcd_16207_state* sp, + unsigned char data) +{ + dc58: defffa04 addi sp,sp,-24 + dc5c: dfc00515 stw ra,20(sp) + dc60: df000415 stw fp,16(sp) + dc64: df000404 addi fp,sp,16 + dc68: e13ffe15 stw r4,-8(fp) + dc6c: e17fff05 stb r5,-4(fp) + unsigned int base = sp->base; + dc70: e0bffe17 ldw r2,-8(fp) + dc74: 10800017 ldw r2,0(r2) + dc78: e0bffd15 stw r2,-12(fp) + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + dc7c: 008003f4 movhi r2,15 + dc80: 10909004 addi r2,r2,16960 + dc84: e0bffc15 stw r2,-16(fp) + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + dc88: e0bffe17 ldw r2,-8(fp) + dc8c: 10800803 ldbu r2,32(r2) + dc90: 10803fcc andi r2,r2,255 + dc94: 1080201c xori r2,r2,128 + dc98: 10bfe004 addi r2,r2,-128 + dc9c: 1004c03a cmpne r2,r2,zero + dca0: 10001d1e bne r2,zero,dd18 + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + dca4: 00000a06 br dcd0 + if (--i == 0) + dca8: e0bffc17 ldw r2,-16(fp) + dcac: 10bfffc4 addi r2,r2,-1 + dcb0: e0bffc15 stw r2,-16(fp) + dcb4: e0bffc17 ldw r2,-16(fp) + dcb8: 1004c03a cmpne r2,r2,zero + dcbc: 1000041e bne r2,zero,dcd0 + { + sp->broken = 1; + dcc0: e0fffe17 ldw r3,-8(fp) + dcc4: 00800044 movi r2,1 + dcc8: 18800805 stb r2,32(r3) + return; + dccc: 00001206 br dd18 + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + dcd0: e0bffd17 ldw r2,-12(fp) + dcd4: 10800104 addi r2,r2,4 + dcd8: 10800037 ldwio r2,0(r2) + dcdc: 1080200c andi r2,r2,128 + dce0: 1004c03a cmpne r2,r2,zero + dce4: 103ff01e bne r2,zero,dca8 + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + dce8: 01001904 movi r4,100 + dcec: 000ce780 call ce78 + + IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data); + dcf0: e0bffd17 ldw r2,-12(fp) + dcf4: 10800204 addi r2,r2,8 + dcf8: e0ffff03 ldbu r3,-4(fp) + dcfc: 10c00035 stwio r3,0(r2) + + sp->address++; + dd00: e0bffe17 ldw r2,-8(fp) + dd04: 108008c3 ldbu r2,35(r2) + dd08: 10800044 addi r2,r2,1 + dd0c: 1007883a mov r3,r2 + dd10: e0bffe17 ldw r2,-8(fp) + dd14: 10c008c5 stb r3,35(r2) +} + dd18: e037883a mov sp,fp + dd1c: dfc00117 ldw ra,4(sp) + dd20: df000017 ldw fp,0(sp) + dd24: dec00204 addi sp,sp,8 + dd28: f800283a ret + +0000dd2c : + +/* --------------------------------------------------------------------- */ + +static void lcd_clear_screen(altera_avalon_lcd_16207_state* sp) +{ + dd2c: defffb04 addi sp,sp,-20 + dd30: dfc00415 stw ra,16(sp) + dd34: df000315 stw fp,12(sp) + dd38: dc000215 stw r16,8(sp) + dd3c: df000204 addi fp,sp,8 + dd40: e13fff15 stw r4,-4(fp) + int y; + + lcd_write_command(sp, LCD_CMD_CLEAR); + dd44: e13fff17 ldw r4,-4(fp) + dd48: 01400044 movi r5,1 + dd4c: 000dba00 call dba0 + + sp->x = 0; + dd50: e0bfff17 ldw r2,-4(fp) + dd54: 10000845 stb zero,33(r2) + sp->y = 0; + dd58: e0bfff17 ldw r2,-4(fp) + dd5c: 10000885 stb zero,34(r2) + sp->address = 0; + dd60: e0bfff17 ldw r2,-4(fp) + dd64: 100008c5 stb zero,35(r2) + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + dd68: e03ffe15 stw zero,-8(fp) + dd6c: 00001c06 br dde0 + { + memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); + dd70: e13ffe17 ldw r4,-8(fp) + dd74: 014018c4 movi r5,99 + dd78: 0002c240 call 2c24 <__mulsi3> + dd7c: 10c01004 addi r3,r2,64 + dd80: e0bfff17 ldw r2,-4(fp) + dd84: 1889883a add r4,r3,r2 + dd88: 01400804 movi r5,32 + dd8c: 01801444 movi r6,81 + dd90: 00081940 call 8194 + memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); + dd94: e13ffe17 ldw r4,-8(fp) + dd98: 014018c4 movi r5,99 + dd9c: 0002c240 call 2c24 <__mulsi3> + dda0: 10c00c04 addi r3,r2,48 + dda4: e0bfff17 ldw r2,-4(fp) + dda8: 1889883a add r4,r3,r2 + ddac: 01400804 movi r5,32 + ddb0: 01800404 movi r6,16 + ddb4: 00081940 call 8194 + sp->line[y].width = 0; + ddb8: e13ffe17 ldw r4,-8(fp) + ddbc: e43fff17 ldw r16,-4(fp) + ddc0: 014018c4 movi r5,99 + ddc4: 0002c240 call 2c24 <__mulsi3> + ddc8: 1405883a add r2,r2,r16 + ddcc: 10802404 addi r2,r2,144 + ddd0: 10000045 stb zero,1(r2) + + sp->x = 0; + sp->y = 0; + sp->address = 0; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + ddd4: e0bffe17 ldw r2,-8(fp) + ddd8: 10800044 addi r2,r2,1 + dddc: e0bffe15 stw r2,-8(fp) + dde0: e0bffe17 ldw r2,-8(fp) + dde4: 10800090 cmplti r2,r2,2 + dde8: 103fe11e bne r2,zero,dd70 + { + memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); + memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); + sp->line[y].width = 0; + } +} + ddec: e037883a mov sp,fp + ddf0: dfc00217 ldw ra,8(sp) + ddf4: df000117 ldw fp,4(sp) + ddf8: dc000017 ldw r16,0(sp) + ddfc: dec00304 addi sp,sp,12 + de00: f800283a ret + +0000de04 : + +/* --------------------------------------------------------------------- */ + +static void lcd_repaint_screen(altera_avalon_lcd_16207_state* sp) +{ + de04: defff404 addi sp,sp,-48 + de08: dfc00b15 stw ra,44(sp) + de0c: df000a15 stw fp,40(sp) + de10: dc800915 stw r18,36(sp) + de14: dc400815 stw r17,32(sp) + de18: dc000715 stw r16,28(sp) + de1c: df000704 addi fp,sp,28 + de20: e13fff15 stw r4,-4(fp) + /* scrollpos controls how much the lines have scrolled round. The speed + * each line scrolls at is controlled by its speed variable - while + * scrolline lines will wrap at the position set by width + */ + + int scrollpos = sp->scrollpos; + de24: e0bfff17 ldw r2,-4(fp) + de28: 10800943 ldbu r2,37(r2) + de2c: 10803fcc andi r2,r2,255 + de30: 1080201c xori r2,r2,128 + de34: 10bfe004 addi r2,r2,-128 + de38: e0bffc15 stw r2,-16(fp) + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + de3c: e03ffe15 stw zero,-8(fp) + de40: 00006a06 br dfec + { + int width = sp->line[y].width; + de44: e13ffe17 ldw r4,-8(fp) + de48: e43fff17 ldw r16,-4(fp) + de4c: 014018c4 movi r5,99 + de50: 0002c240 call 2c24 <__mulsi3> + de54: 1405883a add r2,r2,r16 + de58: 10802404 addi r2,r2,144 + de5c: 10800043 ldbu r2,1(r2) + de60: 10803fcc andi r2,r2,255 + de64: 1080201c xori r2,r2,128 + de68: 10bfe004 addi r2,r2,-128 + de6c: e0bffb15 stw r2,-20(fp) + int offset = (scrollpos * sp->line[y].speed) >> 8; + de70: e13ffe17 ldw r4,-8(fp) + de74: e43fff17 ldw r16,-4(fp) + de78: 014018c4 movi r5,99 + de7c: 0002c240 call 2c24 <__mulsi3> + de80: 1405883a add r2,r2,r16 + de84: 10802404 addi r2,r2,144 + de88: 10800083 ldbu r2,2(r2) + de8c: 11003fcc andi r4,r2,255 + de90: e17ffc17 ldw r5,-16(fp) + de94: 0002c240 call 2c24 <__mulsi3> + de98: 1005d23a srai r2,r2,8 + de9c: e0bffa15 stw r2,-24(fp) + if (offset >= width) + dea0: e0fffa17 ldw r3,-24(fp) + dea4: e0bffb17 ldw r2,-20(fp) + dea8: 18800116 blt r3,r2,deb0 + offset = 0; + deac: e03ffa15 stw zero,-24(fp) + + for (x = 0 ; x < ALT_LCD_WIDTH ; x++) + deb0: e03ffd15 stw zero,-12(fp) + deb4: 00004706 br dfd4 + { + char c = sp->line[y].data[(x + offset) % width]; + deb8: e47ffe17 ldw r17,-8(fp) + debc: e0fffd17 ldw r3,-12(fp) + dec0: e0bffa17 ldw r2,-24(fp) + dec4: 1889883a add r4,r3,r2 + dec8: e17ffb17 ldw r5,-20(fp) + decc: 0002bb40 call 2bb4 <__modsi3> + ded0: 1025883a mov r18,r2 + ded4: e43fff17 ldw r16,-4(fp) + ded8: 8809883a mov r4,r17 + dedc: 014018c4 movi r5,99 + dee0: 0002c240 call 2c24 <__mulsi3> + dee4: 1405883a add r2,r2,r16 + dee8: 1485883a add r2,r2,r18 + deec: 10801004 addi r2,r2,64 + def0: 10800003 ldbu r2,0(r2) + def4: e0bff945 stb r2,-27(fp) + + /* Writing data takes 40us, so don't do it unless required */ + if (sp->line[y].visible[x] != c) + def8: e13ffe17 ldw r4,-8(fp) + defc: e47ffd17 ldw r17,-12(fp) + df00: e43fff17 ldw r16,-4(fp) + df04: 014018c4 movi r5,99 + df08: 0002c240 call 2c24 <__mulsi3> + df0c: 1405883a add r2,r2,r16 + df10: 1445883a add r2,r2,r17 + df14: 10800c04 addi r2,r2,48 + df18: 10800003 ldbu r2,0(r2) + df1c: 10c03fcc andi r3,r2,255 + df20: 18c0201c xori r3,r3,128 + df24: 18ffe004 addi r3,r3,-128 + df28: e0bff947 ldb r2,-27(fp) + df2c: 18802626 beq r3,r2,dfc8 + { + unsigned char address = x + colstart[y]; + df30: e0fffe17 ldw r3,-8(fp) + df34: d0a00f04 addi r2,gp,-32708 + df38: 1885883a add r2,r3,r2 + df3c: 10800003 ldbu r2,0(r2) + df40: 1007883a mov r3,r2 + df44: e0bffd17 ldw r2,-12(fp) + df48: 1885883a add r2,r3,r2 + df4c: e0bff905 stb r2,-28(fp) + + if (address != sp->address) + df50: e0fff903 ldbu r3,-28(fp) + df54: e0bfff17 ldw r2,-4(fp) + df58: 108008c3 ldbu r2,35(r2) + df5c: 10803fcc andi r2,r2,255 + df60: 1080201c xori r2,r2,128 + df64: 10bfe004 addi r2,r2,-128 + df68: 18800926 beq r3,r2,df90 + { + lcd_write_command(sp, LCD_CMD_WRITE_DATA | address); + df6c: e0fff903 ldbu r3,-28(fp) + df70: 00bfe004 movi r2,-128 + df74: 1884b03a or r2,r3,r2 + df78: 11403fcc andi r5,r2,255 + df7c: e13fff17 ldw r4,-4(fp) + df80: 000dba00 call dba0 + sp->address = address; + df84: e0fff903 ldbu r3,-28(fp) + df88: e0bfff17 ldw r2,-4(fp) + df8c: 10c008c5 stb r3,35(r2) + } + + lcd_write_data(sp, c); + df90: e0bff943 ldbu r2,-27(fp) + df94: 11403fcc andi r5,r2,255 + df98: e13fff17 ldw r4,-4(fp) + df9c: 000dc580 call dc58 + sp->line[y].visible[x] = c; + dfa0: e13ffe17 ldw r4,-8(fp) + dfa4: e47ffd17 ldw r17,-12(fp) + dfa8: e43fff17 ldw r16,-4(fp) + dfac: 014018c4 movi r5,99 + dfb0: 0002c240 call 2c24 <__mulsi3> + dfb4: 1405883a add r2,r2,r16 + dfb8: 1445883a add r2,r2,r17 + dfbc: 10c00c04 addi r3,r2,48 + dfc0: e0bff943 ldbu r2,-27(fp) + dfc4: 18800005 stb r2,0(r3) + int width = sp->line[y].width; + int offset = (scrollpos * sp->line[y].speed) >> 8; + if (offset >= width) + offset = 0; + + for (x = 0 ; x < ALT_LCD_WIDTH ; x++) + dfc8: e0bffd17 ldw r2,-12(fp) + dfcc: 10800044 addi r2,r2,1 + dfd0: e0bffd15 stw r2,-12(fp) + dfd4: e0bffd17 ldw r2,-12(fp) + dfd8: 10800410 cmplti r2,r2,16 + dfdc: 103fb61e bne r2,zero,deb8 + * scrolline lines will wrap at the position set by width + */ + + int scrollpos = sp->scrollpos; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + dfe0: e0bffe17 ldw r2,-8(fp) + dfe4: 10800044 addi r2,r2,1 + dfe8: e0bffe15 stw r2,-8(fp) + dfec: e0bffe17 ldw r2,-8(fp) + dff0: 10800090 cmplti r2,r2,2 + dff4: 103f931e bne r2,zero,de44 + lcd_write_data(sp, c); + sp->line[y].visible[x] = c; + } + } + } +} + dff8: e037883a mov sp,fp + dffc: dfc00417 ldw ra,16(sp) + e000: df000317 ldw fp,12(sp) + e004: dc800217 ldw r18,8(sp) + e008: dc400117 ldw r17,4(sp) + e00c: dc000017 ldw r16,0(sp) + e010: dec00504 addi sp,sp,20 + e014: f800283a ret + +0000e018 : + +/* --------------------------------------------------------------------- */ + +static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) +{ + e018: defffb04 addi sp,sp,-20 + e01c: dfc00415 stw ra,16(sp) + e020: df000315 stw fp,12(sp) + e024: dc000215 stw r16,8(sp) + e028: df000204 addi fp,sp,8 + e02c: e13fff15 stw r4,-4(fp) + int y; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + e030: e03ffe15 stw zero,-8(fp) + e034: 00002106 br e0bc + { + if (y < ALT_LCD_HEIGHT-1) + e038: e0bffe17 ldw r2,-8(fp) + e03c: 10800048 cmpgei r2,r2,1 + e040: 1000121e bne r2,zero,e08c + memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); + e044: e13ffe17 ldw r4,-8(fp) + e048: 014018c4 movi r5,99 + e04c: 0002c240 call 2c24 <__mulsi3> + e050: 10c01004 addi r3,r2,64 + e054: e0bfff17 ldw r2,-4(fp) + e058: 18a1883a add r16,r3,r2 + e05c: e0bffe17 ldw r2,-8(fp) + e060: 11000044 addi r4,r2,1 + e064: 014018c4 movi r5,99 + e068: 0002c240 call 2c24 <__mulsi3> + e06c: 10c01004 addi r3,r2,64 + e070: e0bfff17 ldw r2,-4(fp) + e074: 1885883a add r2,r3,r2 + e078: 8009883a mov r4,r16 + e07c: 100b883a mov r5,r2 + e080: 01801404 movi r6,80 + e084: 00080140 call 8014 + e088: 00000906 br e0b0 + else + memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); + e08c: e13ffe17 ldw r4,-8(fp) + e090: 014018c4 movi r5,99 + e094: 0002c240 call 2c24 <__mulsi3> + e098: 10c01004 addi r3,r2,64 + e09c: e0bfff17 ldw r2,-4(fp) + e0a0: 1889883a add r4,r3,r2 + e0a4: 01400804 movi r5,32 + e0a8: 01801404 movi r6,80 + e0ac: 00081940 call 8194 + +static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) +{ + int y; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + e0b0: e0bffe17 ldw r2,-8(fp) + e0b4: 10800044 addi r2,r2,1 + e0b8: e0bffe15 stw r2,-8(fp) + e0bc: e0bffe17 ldw r2,-8(fp) + e0c0: 10800090 cmplti r2,r2,2 + e0c4: 103fdc1e bne r2,zero,e038 + memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); + else + memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); + } + + sp->y--; + e0c8: e0bfff17 ldw r2,-4(fp) + e0cc: 10800883 ldbu r2,34(r2) + e0d0: 10bfffc4 addi r2,r2,-1 + e0d4: 1007883a mov r3,r2 + e0d8: e0bfff17 ldw r2,-4(fp) + e0dc: 10c00885 stb r3,34(r2) +} + e0e0: e037883a mov sp,fp + e0e4: dfc00217 ldw ra,8(sp) + e0e8: df000117 ldw fp,4(sp) + e0ec: dc000017 ldw r16,0(sp) + e0f0: dec00304 addi sp,sp,12 + e0f4: f800283a ret + +0000e0f8 : + +/* --------------------------------------------------------------------- */ + +static void lcd_handle_escape(altera_avalon_lcd_16207_state* sp, char c) +{ + e0f8: defff804 addi sp,sp,-32 + e0fc: dfc00715 stw ra,28(sp) + e100: df000615 stw fp,24(sp) + e104: df000604 addi fp,sp,24 + e108: e13ffd15 stw r4,-12(fp) + e10c: e17ffe05 stb r5,-8(fp) + int parm1 = 0, parm2 = 0; + e110: e03ffc15 stw zero,-16(fp) + e114: e03ffb15 stw zero,-20(fp) + + if (sp->escape[0] == '[') + e118: e0bffd17 ldw r2,-12(fp) + e11c: 10800a03 ldbu r2,40(r2) + e120: 10803fcc andi r2,r2,255 + e124: 1080201c xori r2,r2,128 + e128: 10bfe004 addi r2,r2,-128 + e12c: 108016d8 cmpnei r2,r2,91 + e130: 10004d1e bne r2,zero,e268 + { + char * ptr = sp->escape+1; + e134: e0bffd17 ldw r2,-12(fp) + e138: 10800a04 addi r2,r2,40 + e13c: 10800044 addi r2,r2,1 + e140: e0bffa15 stw r2,-24(fp) + while (isdigit(*ptr)) + e144: 00000f06 br e184 + parm1 = (parm1 * 10) + (*ptr++ - '0'); + e148: e13ffc17 ldw r4,-16(fp) + e14c: 01400284 movi r5,10 + e150: 0002c240 call 2c24 <__mulsi3> + e154: 1007883a mov r3,r2 + e158: e0bffa17 ldw r2,-24(fp) + e15c: 10800003 ldbu r2,0(r2) + e160: 10803fcc andi r2,r2,255 + e164: 1080201c xori r2,r2,128 + e168: 10bfe004 addi r2,r2,-128 + e16c: 1885883a add r2,r3,r2 + e170: 10bff404 addi r2,r2,-48 + e174: e0bffc15 stw r2,-16(fp) + e178: e0bffa17 ldw r2,-24(fp) + e17c: 10800044 addi r2,r2,1 + e180: e0bffa15 stw r2,-24(fp) + int parm1 = 0, parm2 = 0; + + if (sp->escape[0] == '[') + { + char * ptr = sp->escape+1; + while (isdigit(*ptr)) + e184: e0bffa17 ldw r2,-24(fp) + e188: 10800003 ldbu r2,0(r2) + e18c: 10803fcc andi r2,r2,255 + e190: 1080201c xori r2,r2,128 + e194: 10bfe004 addi r2,r2,-128 + e198: 1007883a mov r3,r2 + e19c: 00800074 movhi r2,1 + e1a0: 10887d04 addi r2,r2,8692 + e1a4: 10800017 ldw r2,0(r2) + e1a8: 1885883a add r2,r3,r2 + e1ac: 10800003 ldbu r2,0(r2) + e1b0: 10803fcc andi r2,r2,255 + e1b4: 1080010c andi r2,r2,4 + e1b8: 1004c03a cmpne r2,r2,zero + e1bc: 103fe21e bne r2,zero,e148 + parm1 = (parm1 * 10) + (*ptr++ - '0'); + + if (*ptr == ';') + e1c0: e0bffa17 ldw r2,-24(fp) + e1c4: 10800003 ldbu r2,0(r2) + e1c8: 10803fcc andi r2,r2,255 + e1cc: 1080201c xori r2,r2,128 + e1d0: 10bfe004 addi r2,r2,-128 + e1d4: 10800ed8 cmpnei r2,r2,59 + e1d8: 1000251e bne r2,zero,e270 + { + ptr++; + e1dc: e0bffa17 ldw r2,-24(fp) + e1e0: 10800044 addi r2,r2,1 + e1e4: e0bffa15 stw r2,-24(fp) + while (isdigit(*ptr)) + e1e8: 00000f06 br e228 + parm2 = (parm2 * 10) + (*ptr++ - '0'); + e1ec: e13ffb17 ldw r4,-20(fp) + e1f0: 01400284 movi r5,10 + e1f4: 0002c240 call 2c24 <__mulsi3> + e1f8: 1007883a mov r3,r2 + e1fc: e0bffa17 ldw r2,-24(fp) + e200: 10800003 ldbu r2,0(r2) + e204: 10803fcc andi r2,r2,255 + e208: 1080201c xori r2,r2,128 + e20c: 10bfe004 addi r2,r2,-128 + e210: 1885883a add r2,r3,r2 + e214: 10bff404 addi r2,r2,-48 + e218: e0bffb15 stw r2,-20(fp) + e21c: e0bffa17 ldw r2,-24(fp) + e220: 10800044 addi r2,r2,1 + e224: e0bffa15 stw r2,-24(fp) + parm1 = (parm1 * 10) + (*ptr++ - '0'); + + if (*ptr == ';') + { + ptr++; + while (isdigit(*ptr)) + e228: e0bffa17 ldw r2,-24(fp) + e22c: 10800003 ldbu r2,0(r2) + e230: 10803fcc andi r2,r2,255 + e234: 1080201c xori r2,r2,128 + e238: 10bfe004 addi r2,r2,-128 + e23c: 1007883a mov r3,r2 + e240: 00800074 movhi r2,1 + e244: 10887d04 addi r2,r2,8692 + e248: 10800017 ldw r2,0(r2) + e24c: 1885883a add r2,r3,r2 + e250: 10800003 ldbu r2,0(r2) + e254: 10803fcc andi r2,r2,255 + e258: 1080010c andi r2,r2,4 + e25c: 1004c03a cmpne r2,r2,zero + e260: 103fe21e bne r2,zero,e1ec + e264: 00000206 br e270 + parm2 = (parm2 * 10) + (*ptr++ - '0'); + } + } + else + parm1 = -1; + e268: 00bfffc4 movi r2,-1 + e26c: e0bffc15 stw r2,-16(fp) + + switch (c) + e270: e0bffe07 ldb r2,-8(fp) + e274: e0bfff15 stw r2,-4(fp) + e278: e0ffff17 ldw r3,-4(fp) + e27c: 188012a0 cmpeqi r2,r3,74 + e280: 10002f1e bne r2,zero,e340 + e284: e0ffff17 ldw r3,-4(fp) + e288: 188012c8 cmpgei r2,r3,75 + e28c: 1000041e bne r2,zero,e2a0 + e290: e0ffff17 ldw r3,-4(fp) + e294: 18801220 cmpeqi r2,r3,72 + e298: 1000081e bne r2,zero,e2bc + e29c: 00004a06 br e3c8 + e2a0: e0ffff17 ldw r3,-4(fp) + e2a4: 188012e0 cmpeqi r2,r3,75 + e2a8: 10002b1e bne r2,zero,e358 + e2ac: e0ffff17 ldw r3,-4(fp) + e2b0: 188019a0 cmpeqi r2,r3,102 + e2b4: 1000011e bne r2,zero,e2bc + e2b8: 00004306 br e3c8 + { + case 'H': /* ESC '[' ';' 'H' : Move cursor to location */ + case 'f': /* Same as above */ + if (parm2 > 0) + e2bc: e0bffb17 ldw r2,-20(fp) + e2c0: 10800050 cmplti r2,r2,1 + e2c4: 1000051e bne r2,zero,e2dc + sp->x = parm2 - 1; + e2c8: e0bffb17 ldw r2,-20(fp) + e2cc: 10bfffc4 addi r2,r2,-1 + e2d0: 1007883a mov r3,r2 + e2d4: e0bffd17 ldw r2,-12(fp) + e2d8: 10c00845 stb r3,33(r2) + if (parm1 > 0) + e2dc: e0bffc17 ldw r2,-16(fp) + e2e0: 10800050 cmplti r2,r2,1 + e2e4: 1000381e bne r2,zero,e3c8 + { + sp->y = parm1 - 1; + e2e8: e0bffc17 ldw r2,-16(fp) + e2ec: 10bfffc4 addi r2,r2,-1 + e2f0: 1007883a mov r3,r2 + e2f4: e0bffd17 ldw r2,-12(fp) + e2f8: 10c00885 stb r3,34(r2) + if (sp->y > ALT_LCD_HEIGHT * 2) + e2fc: e0bffd17 ldw r2,-12(fp) + e300: 10800883 ldbu r2,34(r2) + e304: 10803fcc andi r2,r2,255 + e308: 10800170 cmpltui r2,r2,5 + e30c: 1000061e bne r2,zero,e328 + sp->y = ALT_LCD_HEIGHT * 2; + e310: e0fffd17 ldw r3,-12(fp) + e314: 00800104 movi r2,4 + e318: 18800885 stb r2,34(r3) + while (sp->y > ALT_LCD_HEIGHT) + e31c: 00000206 br e328 + lcd_scroll_up(sp); + e320: e13ffd17 ldw r4,-12(fp) + e324: 000e0180 call e018 + if (parm1 > 0) + { + sp->y = parm1 - 1; + if (sp->y > ALT_LCD_HEIGHT * 2) + sp->y = ALT_LCD_HEIGHT * 2; + while (sp->y > ALT_LCD_HEIGHT) + e328: e0bffd17 ldw r2,-12(fp) + e32c: 10800883 ldbu r2,34(r2) + e330: 10803fcc andi r2,r2,255 + e334: 108000e8 cmpgeui r2,r2,3 + e338: 103ff91e bne r2,zero,e320 + lcd_scroll_up(sp); + } + break; + e33c: 00002206 br e3c8 + /* ESC J is clear to beginning of line [unimplemented] + * ESC [ 0 J is clear to bottom of screen [unimplemented] + * ESC [ 1 J is clear to beginning of screen [unimplemented] + * ESC [ 2 J is clear screen + */ + if (parm1 == 2) + e340: e0bffc17 ldw r2,-16(fp) + e344: 10800098 cmpnei r2,r2,2 + e348: 10001f1e bne r2,zero,e3c8 + lcd_clear_screen(sp); + e34c: e13ffd17 ldw r4,-12(fp) + e350: 000dd2c0 call dd2c + break; + e354: 00001c06 br e3c8 + /* ESC K is clear to end of line + * ESC [ 0 K is clear to end of line + * ESC [ 1 K is clear to beginning of line [unimplemented] + * ESC [ 2 K is clear line [unimplemented] + */ + if (parm1 < 1) + e358: e0bffc17 ldw r2,-16(fp) + e35c: 10800048 cmpgei r2,r2,1 + e360: 1000191e bne r2,zero,e3c8 + { + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + e364: e0bffd17 ldw r2,-12(fp) + e368: 10800843 ldbu r2,33(r2) + e36c: 10803fcc andi r2,r2,255 + e370: 10801428 cmpgeui r2,r2,80 + e374: 1000141e bne r2,zero,e3c8 + memset(sp->line[sp->y].data + sp->x, ' ', ALT_LCD_VIRTUAL_WIDTH - sp->x); + e378: e0bffd17 ldw r2,-12(fp) + e37c: 10800883 ldbu r2,34(r2) + e380: 11003fcc andi r4,r2,255 + e384: 014018c4 movi r5,99 + e388: 0002c240 call 2c24 <__mulsi3> + e38c: 10c01004 addi r3,r2,64 + e390: e0bffd17 ldw r2,-12(fp) + e394: 1887883a add r3,r3,r2 + e398: e0bffd17 ldw r2,-12(fp) + e39c: 10800843 ldbu r2,33(r2) + e3a0: 10803fcc andi r2,r2,255 + e3a4: 1889883a add r4,r3,r2 + e3a8: e0bffd17 ldw r2,-12(fp) + e3ac: 10800843 ldbu r2,33(r2) + e3b0: 10c03fcc andi r3,r2,255 + e3b4: 00801404 movi r2,80 + e3b8: 10c5c83a sub r2,r2,r3 + e3bc: 100d883a mov r6,r2 + e3c0: 01400804 movi r5,32 + e3c4: 00081940 call 8194 + } + break; + } +} + e3c8: e037883a mov sp,fp + e3cc: dfc00117 ldw ra,4(sp) + e3d0: df000017 ldw fp,0(sp) + e3d4: dec00204 addi sp,sp,8 + e3d8: f800283a ret + +0000e3dc : + +/* --------------------------------------------------------------------- */ + +int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int len, int flags) +{ + e3dc: defff004 addi sp,sp,-64 + e3e0: dfc00f15 stw ra,60(sp) + e3e4: df000e15 stw fp,56(sp) + e3e8: dc800d15 stw r18,52(sp) + e3ec: dc400c15 stw r17,48(sp) + e3f0: dc000b15 stw r16,44(sp) + e3f4: df000b04 addi fp,sp,44 + e3f8: e13ffc15 stw r4,-16(fp) + e3fc: e17ffd15 stw r5,-12(fp) + e400: e1bffe15 stw r6,-8(fp) + e404: e1ffff15 stw r7,-4(fp) + const char* end = ptr + len; + e408: e0bffe17 ldw r2,-8(fp) + e40c: 1007883a mov r3,r2 + e410: e0bffd17 ldw r2,-12(fp) + e414: 10c5883a add r2,r2,r3 + e418: e0bffb15 stw r2,-20(fp) + + ALT_SEM_PEND (sp->write_lock, 0); + + /* Tell the routine which is called off the timer interrupt that the + * foreground routines are active so it must not repaint the display. */ + sp->active = 1; + e41c: e0fffc17 ldw r3,-16(fp) + e420: 00800044 movi r2,1 + e424: 188009c5 stb r2,39(r3) + + for ( ; ptr < end ; ptr++) + e428: 0000a306 br e6b8 + { + char c = *ptr; + e42c: e0bffd17 ldw r2,-12(fp) + e430: 10800003 ldbu r2,0(r2) + e434: e0bff805 stb r2,-32(fp) + + if (sp->esccount >= 0) + e438: e0bffc17 ldw r2,-16(fp) + e43c: 10800903 ldbu r2,36(r2) + e440: 10803fcc andi r2,r2,255 + e444: 1080201c xori r2,r2,128 + e448: 10bfe004 addi r2,r2,-128 + e44c: 1004803a cmplt r2,r2,zero + e450: 10003b1e bne r2,zero,e540 + { + unsigned int esccount = sp->esccount; + e454: e0bffc17 ldw r2,-16(fp) + e458: 10800903 ldbu r2,36(r2) + e45c: 10803fcc andi r2,r2,255 + e460: 1080201c xori r2,r2,128 + e464: 10bfe004 addi r2,r2,-128 + e468: e0bff715 stw r2,-36(fp) + + /* Single character escape sequences can end with any character + * Multi character escape sequences start with '[' and contain + * digits and semicolons before terminating + */ + if ((esccount == 0 && c != '[') || + e46c: e0bff717 ldw r2,-36(fp) + e470: 1004c03a cmpne r2,r2,zero + e474: 1000031e bne r2,zero,e484 + e478: e0bff807 ldb r2,-32(fp) + e47c: 108016d8 cmpnei r2,r2,91 + e480: 1000111e bne r2,zero,e4c8 + e484: e0bff717 ldw r2,-36(fp) + e488: 1005003a cmpeq r2,r2,zero + e48c: 10001a1e bne r2,zero,e4f8 + e490: e0bff807 ldb r2,-32(fp) + e494: 1007883a mov r3,r2 + e498: 00800074 movhi r2,1 + e49c: 10887d04 addi r2,r2,8692 + e4a0: 10800017 ldw r2,0(r2) + e4a4: 1885883a add r2,r3,r2 + e4a8: 10800003 ldbu r2,0(r2) + e4ac: 10803fcc andi r2,r2,255 + e4b0: 1080010c andi r2,r2,4 + e4b4: 1004c03a cmpne r2,r2,zero + e4b8: 10000f1e bne r2,zero,e4f8 + e4bc: e0bff807 ldb r2,-32(fp) + e4c0: 10800ee0 cmpeqi r2,r2,59 + e4c4: 10000c1e bne r2,zero,e4f8 + (esccount > 0 && !isdigit(c) && c != ';')) + { + sp->escape[esccount] = 0; + e4c8: e0fff717 ldw r3,-36(fp) + e4cc: e0bffc17 ldw r2,-16(fp) + e4d0: 1885883a add r2,r3,r2 + e4d4: 10800a04 addi r2,r2,40 + e4d8: 10000005 stb zero,0(r2) + + lcd_handle_escape(sp, c); + e4dc: e17ff807 ldb r5,-32(fp) + e4e0: e13ffc17 ldw r4,-16(fp) + e4e4: 000e0f80 call e0f8 + + sp->esccount = -1; + e4e8: e0fffc17 ldw r3,-16(fp) + e4ec: 00bfffc4 movi r2,-1 + e4f0: 18800905 stb r2,36(r3) + + /* Single character escape sequences can end with any character + * Multi character escape sequences start with '[' and contain + * digits and semicolons before terminating + */ + if ((esccount == 0 && c != '[') || + e4f4: 00006d06 br e6ac + + lcd_handle_escape(sp, c); + + sp->esccount = -1; + } + else if (sp->esccount < sizeof(sp->escape)-1) + e4f8: e0bffc17 ldw r2,-16(fp) + e4fc: 10800903 ldbu r2,36(r2) + e500: 10803fcc andi r2,r2,255 + e504: 108001e8 cmpgeui r2,r2,7 + e508: 1000681e bne r2,zero,e6ac + { + sp->escape[esccount] = c; + e50c: e0fff717 ldw r3,-36(fp) + e510: e0bffc17 ldw r2,-16(fp) + e514: 1885883a add r2,r3,r2 + e518: 10c00a04 addi r3,r2,40 + e51c: e0bff803 ldbu r2,-32(fp) + e520: 18800005 stb r2,0(r3) + sp->esccount++; + e524: e0bffc17 ldw r2,-16(fp) + e528: 10800903 ldbu r2,36(r2) + e52c: 10800044 addi r2,r2,1 + e530: 1007883a mov r3,r2 + e534: e0bffc17 ldw r2,-16(fp) + e538: 10c00905 stb r3,36(r2) + e53c: 00005b06 br e6ac + } + } + else if (c == 27) /* ESC */ + e540: e0bff807 ldb r2,-32(fp) + e544: 108006d8 cmpnei r2,r2,27 + e548: 1000031e bne r2,zero,e558 + { + sp->esccount = 0; + e54c: e0bffc17 ldw r2,-16(fp) + e550: 10000905 stb zero,36(r2) + e554: 00005506 br e6ac + } + else if (c == '\r') + e558: e0bff807 ldb r2,-32(fp) + e55c: 10800358 cmpnei r2,r2,13 + e560: 1000031e bne r2,zero,e570 + { + sp->x = 0; + e564: e0bffc17 ldw r2,-16(fp) + e568: 10000845 stb zero,33(r2) + e56c: 00004f06 br e6ac + } + else if (c == '\n') + e570: e0bff807 ldb r2,-32(fp) + e574: 10800298 cmpnei r2,r2,10 + e578: 1000101e bne r2,zero,e5bc + { + sp->x = 0; + e57c: e0bffc17 ldw r2,-16(fp) + e580: 10000845 stb zero,33(r2) + sp->y++; + e584: e0bffc17 ldw r2,-16(fp) + e588: 10800883 ldbu r2,34(r2) + e58c: 10800044 addi r2,r2,1 + e590: 1007883a mov r3,r2 + e594: e0bffc17 ldw r2,-16(fp) + e598: 10c00885 stb r3,34(r2) + + /* Let the cursor sit at X=0, Y=HEIGHT without scrolling so the user + * can print two lines of data without losing one. + */ + if (sp->y > ALT_LCD_HEIGHT) + e59c: e0bffc17 ldw r2,-16(fp) + e5a0: 10800883 ldbu r2,34(r2) + e5a4: 10803fcc andi r2,r2,255 + e5a8: 108000f0 cmpltui r2,r2,3 + e5ac: 10003f1e bne r2,zero,e6ac + lcd_scroll_up(sp); + e5b0: e13ffc17 ldw r4,-16(fp) + e5b4: 000e0180 call e018 + e5b8: 00003c06 br e6ac + } + else if (c == '\b') + e5bc: e0bff807 ldb r2,-32(fp) + e5c0: 10800218 cmpnei r2,r2,8 + e5c4: 10000c1e bne r2,zero,e5f8 + { + if (sp->x > 0) + e5c8: e0bffc17 ldw r2,-16(fp) + e5cc: 10800843 ldbu r2,33(r2) + e5d0: 10803fcc andi r2,r2,255 + e5d4: 1005003a cmpeq r2,r2,zero + e5d8: 1000341e bne r2,zero,e6ac + sp->x--; + e5dc: e0bffc17 ldw r2,-16(fp) + e5e0: 10800843 ldbu r2,33(r2) + e5e4: 10bfffc4 addi r2,r2,-1 + e5e8: 1007883a mov r3,r2 + e5ec: e0bffc17 ldw r2,-16(fp) + e5f0: 10c00845 stb r3,33(r2) + e5f4: 00002d06 br e6ac + } + else if (isprint(c)) + e5f8: e0bff807 ldb r2,-32(fp) + e5fc: 1007883a mov r3,r2 + e600: 00800074 movhi r2,1 + e604: 10887d04 addi r2,r2,8692 + e608: 10800017 ldw r2,0(r2) + e60c: 1885883a add r2,r3,r2 + e610: 10800003 ldbu r2,0(r2) + e614: 10803fcc andi r2,r2,255 + e618: 1080201c xori r2,r2,128 + e61c: 10bfe004 addi r2,r2,-128 + e620: 108025cc andi r2,r2,151 + e624: 1005003a cmpeq r2,r2,zero + e628: 1000201e bne r2,zero,e6ac + { + /* If we didn't scroll on the last linefeed then we might need to do + * it now. */ + if (sp->y >= ALT_LCD_HEIGHT) + e62c: e0bffc17 ldw r2,-16(fp) + e630: 10800883 ldbu r2,34(r2) + e634: 10803fcc andi r2,r2,255 + e638: 108000b0 cmpltui r2,r2,2 + e63c: 1000021e bne r2,zero,e648 + lcd_scroll_up(sp); + e640: e13ffc17 ldw r4,-16(fp) + e644: 000e0180 call e018 + + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + e648: e0bffc17 ldw r2,-16(fp) + e64c: 10800843 ldbu r2,33(r2) + e650: 10803fcc andi r2,r2,255 + e654: 10801428 cmpgeui r2,r2,80 + e658: 10000e1e bne r2,zero,e694 + sp->line[sp->y].data[sp->x] = c; + e65c: e0bffc17 ldw r2,-16(fp) + e660: 10800883 ldbu r2,34(r2) + e664: 11003fcc andi r4,r2,255 + e668: e0bffc17 ldw r2,-16(fp) + e66c: 10800843 ldbu r2,33(r2) + e670: 14403fcc andi r17,r2,255 + e674: e43ffc17 ldw r16,-16(fp) + e678: 014018c4 movi r5,99 + e67c: 0002c240 call 2c24 <__mulsi3> + e680: 1405883a add r2,r2,r16 + e684: 1445883a add r2,r2,r17 + e688: 10c01004 addi r3,r2,64 + e68c: e0bff803 ldbu r2,-32(fp) + e690: 18800005 stb r2,0(r3) + + sp->x++; + e694: e0bffc17 ldw r2,-16(fp) + e698: 10800843 ldbu r2,33(r2) + e69c: 10800044 addi r2,r2,1 + e6a0: 1007883a mov r3,r2 + e6a4: e0bffc17 ldw r2,-16(fp) + e6a8: 10c00845 stb r3,33(r2) + + /* Tell the routine which is called off the timer interrupt that the + * foreground routines are active so it must not repaint the display. */ + sp->active = 1; + + for ( ; ptr < end ; ptr++) + e6ac: e0bffd17 ldw r2,-12(fp) + e6b0: 10800044 addi r2,r2,1 + e6b4: e0bffd15 stw r2,-12(fp) + e6b8: e0fffd17 ldw r3,-12(fp) + e6bc: e0bffb17 ldw r2,-20(fp) + e6c0: 18bf5a36 bltu r3,r2,e42c + sp->x++; + } + } + + /* Recalculate the scrolling parameters */ + widthmax = ALT_LCD_WIDTH; + e6c4: 00800404 movi r2,16 + e6c8: e0bff915 stw r2,-28(fp) + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + e6cc: e03ffa15 stw zero,-24(fp) + e6d0: 00003906 br e7b8 + { + int width; + for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) + e6d4: 00801404 movi r2,80 + e6d8: e0bff615 stw r2,-40(fp) + e6dc: 00001206 br e728 + if (sp->line[y].data[width-1] != ' ') + e6e0: e13ffa17 ldw r4,-24(fp) + e6e4: e0bff617 ldw r2,-40(fp) + e6e8: 147fffc4 addi r17,r2,-1 + e6ec: e43ffc17 ldw r16,-16(fp) + e6f0: 014018c4 movi r5,99 + e6f4: 0002c240 call 2c24 <__mulsi3> + e6f8: 1405883a add r2,r2,r16 + e6fc: 1445883a add r2,r2,r17 + e700: 10801004 addi r2,r2,64 + e704: 10800003 ldbu r2,0(r2) + e708: 10803fcc andi r2,r2,255 + e70c: 1080201c xori r2,r2,128 + e710: 10bfe004 addi r2,r2,-128 + e714: 10800818 cmpnei r2,r2,32 + e718: 1000061e bne r2,zero,e734 + /* Recalculate the scrolling parameters */ + widthmax = ALT_LCD_WIDTH; + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + int width; + for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) + e71c: e0bff617 ldw r2,-40(fp) + e720: 10bfffc4 addi r2,r2,-1 + e724: e0bff615 stw r2,-40(fp) + e728: e0bff617 ldw r2,-40(fp) + e72c: 10800048 cmpgei r2,r2,1 + e730: 103feb1e bne r2,zero,e6e0 + + /* The minimum width is the size of the LCD panel. If the real width + * is long enough to require scrolling then add an extra space so the + * end of the message doesn't run into the beginning of it. + */ + if (width <= ALT_LCD_WIDTH) + e734: e0bff617 ldw r2,-40(fp) + e738: 10800448 cmpgei r2,r2,17 + e73c: 1000031e bne r2,zero,e74c + width = ALT_LCD_WIDTH; + e740: 00800404 movi r2,16 + e744: e0bff615 stw r2,-40(fp) + e748: 00000306 br e758 + else + width++; + e74c: e0bff617 ldw r2,-40(fp) + e750: 10800044 addi r2,r2,1 + e754: e0bff615 stw r2,-40(fp) + + sp->line[y].width = width; + e758: e13ffa17 ldw r4,-24(fp) + e75c: e0bff617 ldw r2,-40(fp) + e760: 1023883a mov r17,r2 + e764: e43ffc17 ldw r16,-16(fp) + e768: 014018c4 movi r5,99 + e76c: 0002c240 call 2c24 <__mulsi3> + e770: 1405883a add r2,r2,r16 + e774: 10802404 addi r2,r2,144 + e778: 14400045 stb r17,1(r2) + if (widthmax < width) + e77c: e0fff917 ldw r3,-28(fp) + e780: e0bff617 ldw r2,-40(fp) + e784: 1880020e bge r3,r2,e790 + widthmax = width; + e788: e0bff617 ldw r2,-40(fp) + e78c: e0bff915 stw r2,-28(fp) + sp->line[y].speed = 0; /* By default lines don't scroll */ + e790: e13ffa17 ldw r4,-24(fp) + e794: e43ffc17 ldw r16,-16(fp) + e798: 014018c4 movi r5,99 + e79c: 0002c240 call 2c24 <__mulsi3> + e7a0: 1405883a add r2,r2,r16 + e7a4: 10802404 addi r2,r2,144 + e7a8: 10000085 stb zero,2(r2) + } + } + + /* Recalculate the scrolling parameters */ + widthmax = ALT_LCD_WIDTH; + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + e7ac: e0bffa17 ldw r2,-24(fp) + e7b0: 10800044 addi r2,r2,1 + e7b4: e0bffa15 stw r2,-24(fp) + e7b8: e0bffa17 ldw r2,-24(fp) + e7bc: 10800090 cmplti r2,r2,2 + e7c0: 103fc41e bne r2,zero,e6d4 + if (widthmax < width) + widthmax = width; + sp->line[y].speed = 0; /* By default lines don't scroll */ + } + + if (widthmax <= ALT_LCD_WIDTH) + e7c4: e0bff917 ldw r2,-28(fp) + e7c8: 10800448 cmpgei r2,r2,17 + e7cc: 1000031e bne r2,zero,e7dc + sp->scrollmax = 0; + e7d0: e0bffc17 ldw r2,-16(fp) + e7d4: 10000985 stb zero,38(r2) + e7d8: 00003106 br e8a0 + else + { + widthmax *= 2; + e7dc: e0bff917 ldw r2,-28(fp) + e7e0: 1085883a add r2,r2,r2 + e7e4: e0bff915 stw r2,-28(fp) + sp->scrollmax = widthmax; + e7e8: e0bff917 ldw r2,-28(fp) + e7ec: 1007883a mov r3,r2 + e7f0: e0bffc17 ldw r2,-16(fp) + e7f4: 10c00985 stb r3,38(r2) + + /* Now calculate how fast each of the other lines should go */ + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + e7f8: e03ffa15 stw zero,-24(fp) + e7fc: 00002506 br e894 + if (sp->line[y].width > ALT_LCD_WIDTH) + e800: e13ffa17 ldw r4,-24(fp) + e804: e43ffc17 ldw r16,-16(fp) + e808: 014018c4 movi r5,99 + e80c: 0002c240 call 2c24 <__mulsi3> + e810: 1405883a add r2,r2,r16 + e814: 10802404 addi r2,r2,144 + e818: 10800043 ldbu r2,1(r2) + e81c: 10803fcc andi r2,r2,255 + e820: 1080201c xori r2,r2,128 + e824: 10bfe004 addi r2,r2,-128 + e828: 10800450 cmplti r2,r2,17 + e82c: 1000161e bne r2,zero,e888 + */ +#if 1 + /* This option makes all the lines scroll round at different speeds + * which are chosen so that all the scrolls finish at the same time. + */ + sp->line[y].speed = 256 * sp->line[y].width / widthmax; + e830: e4bffa17 ldw r18,-24(fp) + e834: e13ffa17 ldw r4,-24(fp) + e838: e43ffc17 ldw r16,-16(fp) + e83c: 014018c4 movi r5,99 + e840: 0002c240 call 2c24 <__mulsi3> + e844: 1405883a add r2,r2,r16 + e848: 10802404 addi r2,r2,144 + e84c: 10800043 ldbu r2,1(r2) + e850: 10803fcc andi r2,r2,255 + e854: 1080201c xori r2,r2,128 + e858: 10bfe004 addi r2,r2,-128 + e85c: 1008923a slli r4,r2,8 + e860: e17ff917 ldw r5,-28(fp) + e864: 0002b540 call 2b54 <__divsi3> + e868: 1023883a mov r17,r2 + e86c: e43ffc17 ldw r16,-16(fp) + e870: 9009883a mov r4,r18 + e874: 014018c4 movi r5,99 + e878: 0002c240 call 2c24 <__mulsi3> + e87c: 1405883a add r2,r2,r16 + e880: 10802404 addi r2,r2,144 + e884: 14400085 stb r17,2(r2) + { + widthmax *= 2; + sp->scrollmax = widthmax; + + /* Now calculate how fast each of the other lines should go */ + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + e888: e0bffa17 ldw r2,-24(fp) + e88c: 10800044 addi r2,r2,1 + e890: e0bffa15 stw r2,-24(fp) + e894: e0bffa17 ldw r2,-24(fp) + e898: 10800090 cmplti r2,r2,2 + e89c: 103fd81e bne r2,zero,e800 + * (because active was set when the timer interrupt occurred). If there + * has been a missed repaint then paint again. And again. etc. + */ + for ( ; ; ) + { + int old_scrollpos = sp->scrollpos; + e8a0: e0bffc17 ldw r2,-16(fp) + e8a4: 10800943 ldbu r2,37(r2) + e8a8: 10803fcc andi r2,r2,255 + e8ac: 1080201c xori r2,r2,128 + e8b0: 10bfe004 addi r2,r2,-128 + e8b4: e0bff515 stw r2,-44(fp) + + lcd_repaint_screen(sp); + e8b8: e13ffc17 ldw r4,-16(fp) + e8bc: 000de040 call de04 + + /* Let the timer routines repaint the display again */ + sp->active = 0; + e8c0: e0bffc17 ldw r2,-16(fp) + e8c4: 100009c5 stb zero,39(r2) + + /* Have the timer routines tried to scroll while we were painting? + * If not then we can exit */ + if (sp->scrollpos == old_scrollpos) + e8c8: e0bffc17 ldw r2,-16(fp) + e8cc: 10800943 ldbu r2,37(r2) + e8d0: 10c03fcc andi r3,r2,255 + e8d4: 18c0201c xori r3,r3,128 + e8d8: 18ffe004 addi r3,r3,-128 + e8dc: e0bff517 ldw r2,-44(fp) + e8e0: 18800426 beq r3,r2,e8f4 + break; + + /* We need to repaint again since the display scrolled while we were + * painting last time */ + sp->active = 1; + e8e4: e0fffc17 ldw r3,-16(fp) + e8e8: 00800044 movi r2,1 + e8ec: 188009c5 stb r2,39(r3) + } + e8f0: 003feb06 br e8a0 + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + + return len; + e8f4: e0bffe17 ldw r2,-8(fp) +} + e8f8: e037883a mov sp,fp + e8fc: dfc00417 ldw ra,16(sp) + e900: df000317 ldw fp,12(sp) + e904: dc800217 ldw r18,8(sp) + e908: dc400117 ldw r17,4(sp) + e90c: dc000017 ldw r16,0(sp) + e910: dec00504 addi sp,sp,20 + e914: f800283a ret + +0000e918 : +/* + * Timeout routine is called every second + */ + +static alt_u32 alt_lcd_16207_timeout(void* context) +{ + e918: defffc04 addi sp,sp,-16 + e91c: dfc00315 stw ra,12(sp) + e920: df000215 stw fp,8(sp) + e924: df000204 addi fp,sp,8 + e928: e13fff15 stw r4,-4(fp) + altera_avalon_lcd_16207_state* sp = (altera_avalon_lcd_16207_state*)context; + e92c: e0bfff17 ldw r2,-4(fp) + e930: e0bffe15 stw r2,-8(fp) + + /* Update the scrolling position */ + if (sp->scrollpos + 1 >= sp->scrollmax) + e934: e0bffe17 ldw r2,-8(fp) + e938: 10800943 ldbu r2,37(r2) + e93c: 10803fcc andi r2,r2,255 + e940: 1080201c xori r2,r2,128 + e944: 10bfe004 addi r2,r2,-128 + e948: 10c00044 addi r3,r2,1 + e94c: e0bffe17 ldw r2,-8(fp) + e950: 10800983 ldbu r2,38(r2) + e954: 10803fcc andi r2,r2,255 + e958: 1080201c xori r2,r2,128 + e95c: 10bfe004 addi r2,r2,-128 + e960: 18800316 blt r3,r2,e970 + sp->scrollpos = 0; + e964: e0bffe17 ldw r2,-8(fp) + e968: 10000945 stb zero,37(r2) + e96c: 00000606 br e988 + else + sp->scrollpos = sp->scrollpos + 1; + e970: e0bffe17 ldw r2,-8(fp) + e974: 10800943 ldbu r2,37(r2) + e978: 10800044 addi r2,r2,1 + e97c: 1007883a mov r3,r2 + e980: e0bffe17 ldw r2,-8(fp) + e984: 10c00945 stb r3,37(r2) + + /* Repaint the panel unless the foreground will do it again soon */ + if (sp->scrollmax > 0 && !sp->active) + e988: e0bffe17 ldw r2,-8(fp) + e98c: 10800983 ldbu r2,38(r2) + e990: 10803fcc andi r2,r2,255 + e994: 1080201c xori r2,r2,128 + e998: 10bfe004 addi r2,r2,-128 + e99c: 10800050 cmplti r2,r2,1 + e9a0: 1000091e bne r2,zero,e9c8 + e9a4: e0bffe17 ldw r2,-8(fp) + e9a8: 108009c3 ldbu r2,39(r2) + e9ac: 10803fcc andi r2,r2,255 + e9b0: 1080201c xori r2,r2,128 + e9b4: 10bfe004 addi r2,r2,-128 + e9b8: 1004c03a cmpne r2,r2,zero + e9bc: 1000021e bne r2,zero,e9c8 + lcd_repaint_screen(sp); + e9c0: e13ffe17 ldw r4,-8(fp) + e9c4: 000de040 call de04 + + return sp->period; + e9c8: e0bffe17 ldw r2,-8(fp) + e9cc: 10800717 ldw r2,28(r2) +} + e9d0: e037883a mov sp,fp + e9d4: dfc00117 ldw ra,4(sp) + e9d8: df000017 ldw fp,0(sp) + e9dc: dec00204 addi sp,sp,8 + e9e0: f800283a ret + +0000e9e4 : + +/* + * Called at boot time to initialise the LCD driver + */ +void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp) +{ + e9e4: defffc04 addi sp,sp,-16 + e9e8: dfc00315 stw ra,12(sp) + e9ec: df000215 stw fp,8(sp) + e9f0: df000204 addi fp,sp,8 + e9f4: e13fff15 stw r4,-4(fp) + unsigned int base = sp->base; + e9f8: e0bfff17 ldw r2,-4(fp) + e9fc: 10800017 ldw r2,0(r2) + ea00: e0bffe15 stw r2,-8(fp) + + /* Mark the device as functional */ + sp->broken = 0; + ea04: e0bfff17 ldw r2,-4(fp) + ea08: 10000805 stb zero,32(r2) + * the BUSY bit in the status register doesn't work until the display + * has been reset three times. + */ + + /* Wait for 15 ms then reset */ + usleep(15000); + ea0c: 010ea604 movi r4,15000 + ea10: 000ce780 call ce78 + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + ea14: e0bffe17 ldw r2,-8(fp) + ea18: 1007883a mov r3,r2 + ea1c: 00800c04 movi r2,48 + ea20: 18800035 stwio r2,0(r3) + + /* Wait for another 4.1ms and reset again */ + usleep(4100); + ea24: 01040104 movi r4,4100 + ea28: 000ce780 call ce78 + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + ea2c: e0bffe17 ldw r2,-8(fp) + ea30: 1007883a mov r3,r2 + ea34: 00800c04 movi r2,48 + ea38: 18800035 stwio r2,0(r3) + + /* Wait a further 1 ms and reset a third time */ + usleep(1000); + ea3c: 0100fa04 movi r4,1000 + ea40: 000ce780 call ce78 + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + ea44: e0bffe17 ldw r2,-8(fp) + ea48: 1007883a mov r3,r2 + ea4c: 00800c04 movi r2,48 + ea50: 18800035 stwio r2,0(r3) + + /* Setup interface parameters: 8 bit bus, 2 rows, 5x7 font */ + lcd_write_command(sp, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT | LCD_CMD_TWO_LINE); + ea54: e13fff17 ldw r4,-4(fp) + ea58: 01400e04 movi r5,56 + ea5c: 000dba00 call dba0 + + /* Turn display off */ + lcd_write_command(sp, LCD_CMD_ONOFF); + ea60: e13fff17 ldw r4,-4(fp) + ea64: 01400204 movi r5,8 + ea68: 000dba00 call dba0 + + /* Clear display */ + lcd_clear_screen(sp); + ea6c: e13fff17 ldw r4,-4(fp) + ea70: 000dd2c0 call dd2c + + /* Set mode: increment after writing, don't shift display */ + lcd_write_command(sp, LCD_CMD_MODES | LCD_CMD_MODE_INC); + ea74: e13fff17 ldw r4,-4(fp) + ea78: 01400184 movi r5,6 + ea7c: 000dba00 call dba0 + + /* Turn display on */ + lcd_write_command(sp, LCD_CMD_ONOFF | LCD_CMD_ENABLE_DISP); + ea80: e13fff17 ldw r4,-4(fp) + ea84: 01400304 movi r5,12 + ea88: 000dba00 call dba0 + + sp->esccount = -1; + ea8c: e0ffff17 ldw r3,-4(fp) + ea90: 00bfffc4 movi r2,-1 + ea94: 18800905 stb r2,36(r3) + memset(sp->escape, 0, sizeof(sp->escape)); + ea98: e0bfff17 ldw r2,-4(fp) + ea9c: 11000a04 addi r4,r2,40 + eaa0: 000b883a mov r5,zero + eaa4: 01800204 movi r6,8 + eaa8: 00081940 call 8194 + + sp->scrollpos = 0; + eaac: e0bfff17 ldw r2,-4(fp) + eab0: 10000945 stb zero,37(r2) + sp->scrollmax = 0; + eab4: e0bfff17 ldw r2,-4(fp) + eab8: 10000985 stb zero,38(r2) + sp->active = 0; + eabc: e0bfff17 ldw r2,-4(fp) + eac0: 100009c5 stb zero,39(r2) + eac4: 00800074 movhi r2,1 + eac8: 108f8104 addi r2,r2,15876 + eacc: 10800017 ldw r2,0(r2) + ead0: 1009883a mov r4,r2 + + sp->period = alt_ticks_per_second() / 10; /* Call every 100ms */ + ead4: 01400284 movi r5,10 + ead8: 0002c140 call 2c14 <__udivsi3> + eadc: 1007883a mov r3,r2 + eae0: e0bfff17 ldw r2,-4(fp) + eae4: 10c00715 stw r3,28(r2) + + alt_alarm_start(&sp->alarm, sp->period, &alt_lcd_16207_timeout, sp); + eae8: e0bfff17 ldw r2,-4(fp) + eaec: 11000104 addi r4,r2,4 + eaf0: e0bfff17 ldw r2,-4(fp) + eaf4: 10800717 ldw r2,28(r2) + eaf8: 100b883a mov r5,r2 + eafc: 01800074 movhi r6,1 + eb00: 31ba4604 addi r6,r6,-5864 + eb04: e1ffff17 ldw r7,-4(fp) + eb08: 000eb780 call eb78 +} + eb0c: e037883a mov sp,fp + eb10: dfc00117 ldw ra,4(sp) + eb14: df000017 ldw fp,0(sp) + eb18: dec00204 addi sp,sp,8 + eb1c: f800283a ret + +0000eb20 : +extern int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int count, int flags); + +int +altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* buffer, int space) +{ + eb20: defffa04 addi sp,sp,-24 + eb24: dfc00515 stw ra,20(sp) + eb28: df000415 stw fp,16(sp) + eb2c: df000404 addi fp,sp,16 + eb30: e13ffd15 stw r4,-12(fp) + eb34: e17ffe15 stw r5,-8(fp) + eb38: e1bfff15 stw r6,-4(fp) + altera_avalon_lcd_16207_dev* dev = (altera_avalon_lcd_16207_dev*) fd->dev; + eb3c: e0bffd17 ldw r2,-12(fp) + eb40: 10800017 ldw r2,0(r2) + eb44: e0bffc15 stw r2,-16(fp) + + return altera_avalon_lcd_16207_write(&dev->state, buffer, space, + eb48: e0bffc17 ldw r2,-16(fp) + eb4c: 11000a04 addi r4,r2,40 + eb50: e0bffd17 ldw r2,-12(fp) + eb54: 11c00217 ldw r7,8(r2) + eb58: e17ffe17 ldw r5,-8(fp) + eb5c: e1bfff17 ldw r6,-4(fp) + eb60: 000e3dc0 call e3dc + fd->fd_flags); +} + eb64: e037883a mov sp,fp + eb68: dfc00117 ldw ra,4(sp) + eb6c: df000017 ldw fp,0(sp) + eb70: dec00204 addi sp,sp,8 + eb74: f800283a ret + +0000eb78 : + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + eb78: defff404 addi sp,sp,-48 + eb7c: df000b15 stw fp,44(sp) + eb80: df000b04 addi fp,sp,44 + eb84: e13ffb15 stw r4,-20(fp) + eb88: e17ffc15 stw r5,-16(fp) + eb8c: e1bffd15 stw r6,-12(fp) + eb90: e1fffe15 stw r7,-8(fp) + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + eb94: e03ff915 stw zero,-28(fp) + eb98: 00800074 movhi r2,1 + eb9c: 108f8104 addi r2,r2,15876 + eba0: 10800017 ldw r2,0(r2) + + if (alt_ticks_per_second ()) + eba4: 1005003a cmpeq r2,r2,zero + eba8: 1000411e bne r2,zero,ecb0 + { + if (alarm) + ebac: e0bffb17 ldw r2,-20(fp) + ebb0: 1005003a cmpeq r2,r2,zero + ebb4: 10003b1e bne r2,zero,eca4 + { + alarm->callback = callback; + ebb8: e0fffb17 ldw r3,-20(fp) + ebbc: e0bffd17 ldw r2,-12(fp) + ebc0: 18800315 stw r2,12(r3) + alarm->context = context; + ebc4: e0fffb17 ldw r3,-20(fp) + ebc8: e0bffe17 ldw r2,-8(fp) + ebcc: 18800515 stw r2,20(r3) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + ebd0: 0005303a rdctl r2,status + ebd4: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + ebd8: e0fff817 ldw r3,-32(fp) + ebdc: 00bfff84 movi r2,-2 + ebe0: 1884703a and r2,r3,r2 + ebe4: 1001703a wrctl status,r2 + + return context; + ebe8: e0bff817 ldw r2,-32(fp) + + irq_context = alt_irq_disable_all (); + ebec: e0bffa15 stw r2,-24(fp) + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; + ebf0: 00800074 movhi r2,1 + ebf4: 108f8204 addi r2,r2,15880 + ebf8: 10800017 ldw r2,0(r2) + + current_nticks = alt_nticks(); + ebfc: e0bff915 stw r2,-28(fp) + + alarm->time = nticks + current_nticks + 1; + ec00: e0fffc17 ldw r3,-16(fp) + ec04: e0bff917 ldw r2,-28(fp) + ec08: 1885883a add r2,r3,r2 + ec0c: 10c00044 addi r3,r2,1 + ec10: e0bffb17 ldw r2,-20(fp) + ec14: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + ec18: e0bffb17 ldw r2,-20(fp) + ec1c: 10c00217 ldw r3,8(r2) + ec20: e0bff917 ldw r2,-28(fp) + ec24: 1880042e bgeu r3,r2,ec38 + { + alarm->rollover = 1; + ec28: e0fffb17 ldw r3,-20(fp) + ec2c: 00800044 movi r2,1 + ec30: 18800405 stb r2,16(r3) + ec34: 00000206 br ec40 + } + else + { + alarm->rollover = 0; + ec38: e0bffb17 ldw r2,-20(fp) + ec3c: 10000405 stb zero,16(r2) + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + ec40: e0fffb17 ldw r3,-20(fp) + ec44: 00800074 movhi r2,1 + ec48: 10888d04 addi r2,r2,8756 + ec4c: e0bff615 stw r2,-40(fp) + ec50: e0fff715 stw r3,-36(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + ec54: e0fff717 ldw r3,-36(fp) + ec58: e0bff617 ldw r2,-40(fp) + ec5c: 18800115 stw r2,4(r3) + entry->next = list->next; + ec60: e0bff617 ldw r2,-40(fp) + ec64: 10c00017 ldw r3,0(r2) + ec68: e0bff717 ldw r2,-36(fp) + ec6c: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + ec70: e0bff617 ldw r2,-40(fp) + ec74: 10c00017 ldw r3,0(r2) + ec78: e0bff717 ldw r2,-36(fp) + ec7c: 18800115 stw r2,4(r3) + list->next = entry; + ec80: e0fff617 ldw r3,-40(fp) + ec84: e0bff717 ldw r2,-36(fp) + ec88: 18800015 stw r2,0(r3) + ec8c: e0bffa17 ldw r2,-24(fp) + ec90: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + ec94: e0bff517 ldw r2,-44(fp) + ec98: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); + + return 0; + ec9c: e03fff15 stw zero,-4(fp) + eca0: 00000506 br ecb8 + } + else + { + return -EINVAL; + eca4: 00bffa84 movi r2,-22 + eca8: e0bfff15 stw r2,-4(fp) + ecac: 00000206 br ecb8 + } + } + else + { + return -ENOTSUP; + ecb0: 00bfde84 movi r2,-134 + ecb4: e0bfff15 stw r2,-4(fp) + ecb8: e0bfff17 ldw r2,-4(fp) + } +} + ecbc: e037883a mov sp,fp + ecc0: df000017 ldw fp,0(sp) + ecc4: dec00104 addi sp,sp,4 + ecc8: f800283a ret + +0000eccc : +#include "alt_types.h" + +#include "priv/alt_busy_sleep.h" + +unsigned int alt_busy_sleep (unsigned int us) +{ + eccc: defffa04 addi sp,sp,-24 + ecd0: dfc00515 stw ra,20(sp) + ecd4: df000415 stw fp,16(sp) + ecd8: df000404 addi fp,sp,16 + ecdc: e13fff15 stw r4,-4(fp) + int big_loops; + alt_u32 cycles_per_loop; + + if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) + { + cycles_per_loop = 9; + ece0: 00800244 movi r2,9 + ece4: e0bffc15 stw r2,-16(fp) + { + cycles_per_loop = 3; + } + + + big_loops = us / (INT_MAX/ + ece8: e13ffc17 ldw r4,-16(fp) + ecec: 014003f4 movhi r5,15 + ecf0: 29509004 addi r5,r5,16960 + ecf4: 0002c240 call 2c24 <__mulsi3> + ecf8: 100b883a mov r5,r2 + ecfc: 0100bef4 movhi r4,763 + ed00: 213c2004 addi r4,r4,-3968 + ed04: 0002c140 call 2c14 <__udivsi3> + ed08: 100b883a mov r5,r2 + ed0c: 01200034 movhi r4,32768 + ed10: 213fffc4 addi r4,r4,-1 + ed14: 0002c140 call 2c14 <__udivsi3> + ed18: 100b883a mov r5,r2 + ed1c: e13fff17 ldw r4,-4(fp) + ed20: 0002c140 call 2c14 <__udivsi3> + ed24: e0bffd15 stw r2,-12(fp) + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + + if (big_loops) + ed28: e0bffd17 ldw r2,-12(fp) + ed2c: 1005003a cmpeq r2,r2,zero + ed30: 10002a1e bne r2,zero,eddc + { + for(i=0;i + /* + * Do NOT Try to single step the asm statement below + * (single step will never return) + * Step out of this function or set a breakpoint after the asm statements + */ + __asm__ volatile ( + ed3c: 00a00034 movhi r2,32768 + ed40: 10bfffc4 addi r2,r2,-1 + ed44: 10bfffc4 addi r2,r2,-1 + ed48: 103ffe1e bne r2,zero,ed44 + "\n1:" + "\n\t.pushsection .debug_alt_sim_info" + "\n\t.int 4, 0, 0b, 1b" + "\n\t.popsection" + :: "r" (INT_MAX)); + us -= (INT_MAX/(ALT_CPU_FREQ/ + ed4c: e13ffc17 ldw r4,-16(fp) + ed50: 014003f4 movhi r5,15 + ed54: 29509004 addi r5,r5,16960 + ed58: 0002c240 call 2c24 <__mulsi3> + ed5c: 100b883a mov r5,r2 + ed60: 0100bef4 movhi r4,763 + ed64: 213c2004 addi r4,r4,-3968 + ed68: 0002c140 call 2c14 <__udivsi3> + ed6c: 100b883a mov r5,r2 + ed70: 01200034 movhi r4,32768 + ed74: 213fffc4 addi r4,r4,-1 + ed78: 0002c140 call 2c14 <__udivsi3> + ed7c: 1007883a mov r3,r2 + ed80: e0bfff17 ldw r2,-4(fp) + ed84: 10c5c83a sub r2,r2,r3 + ed88: e0bfff15 stw r2,-4(fp) + big_loops = us / (INT_MAX/ + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + + if (big_loops) + { + for(i=0;i + /* + * Do NOT Try to single step the asm statement below + * (single step will never return) + * Step out of this function or set a breakpoint after the asm statements + */ + __asm__ volatile ( + eda4: e13ffc17 ldw r4,-16(fp) + eda8: 014003f4 movhi r5,15 + edac: 29509004 addi r5,r5,16960 + edb0: 0002c240 call 2c24 <__mulsi3> + edb4: 100b883a mov r5,r2 + edb8: 0100bef4 movhi r4,763 + edbc: 213c2004 addi r4,r4,-3968 + edc0: 0002c140 call 2c14 <__udivsi3> + edc4: 1009883a mov r4,r2 + edc8: e17fff17 ldw r5,-4(fp) + edcc: 0002c240 call 2c24 <__mulsi3> + edd0: 10bfffc4 addi r2,r2,-1 + edd4: 103ffe1e bne r2,zero,edd0 + edd8: 00000d06 br ee10 + /* + * Do NOT Try to single step the asm statement below + * (single step will never return) + * Step out of this function or set a breakpoint after the asm statements + */ + __asm__ volatile ( + eddc: e13ffc17 ldw r4,-16(fp) + ede0: 014003f4 movhi r5,15 + ede4: 29509004 addi r5,r5,16960 + ede8: 0002c240 call 2c24 <__mulsi3> + edec: 100b883a mov r5,r2 + edf0: 0100bef4 movhi r4,763 + edf4: 213c2004 addi r4,r4,-3968 + edf8: 0002c140 call 2c14 <__udivsi3> + edfc: 1009883a mov r4,r2 + ee00: e17fff17 ldw r5,-4(fp) + ee04: 0002c240 call 2c24 <__mulsi3> + ee08: 10bfffc4 addi r2,r2,-1 + ee0c: 00bffe16 blt zero,r2,ee08 + "\n\t.int 4, 0, 0b, 1b" + "\n\t.popsection" + :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000)))); + } +#endif /* #ifndef ALT_SIM_OPTIMIZE */ + return 0; + ee10: 0005883a mov r2,zero +} + ee14: e037883a mov sp,fp + ee18: dfc00117 ldw ra,4(sp) + ee1c: df000017 ldw fp,0(sp) + ee20: dec00204 addi sp,sp,8 + ee24: f800283a ret + +0000ee28 : +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ + ee28: deffff04 addi sp,sp,-4 + ee2c: df000015 stw fp,0(sp) + ee30: d839883a mov fp,sp + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} + ee34: e037883a mov sp,fp + ee38: df000017 ldw fp,0(sp) + ee3c: dec00104 addi sp,sp,4 + ee40: f800283a ret + +0000ee44 : +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + ee44: defff904 addi sp,sp,-28 + ee48: dfc00615 stw ra,24(sp) + ee4c: df000515 stw fp,20(sp) + ee50: df000504 addi fp,sp,20 + ee54: e13ffd15 stw r4,-12(fp) + ee58: e17ffe15 stw r5,-8(fp) + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + ee5c: e0bffd17 ldw r2,-12(fp) + ee60: 1005003a cmpeq r2,r2,zero + ee64: 1000041e bne r2,zero,ee78 + ee68: e0bffd17 ldw r2,-12(fp) + ee6c: 10800217 ldw r2,8(r2) + ee70: 1004c03a cmpne r2,r2,zero + ee74: 1000071e bne r2,zero,ee94 + { + ALT_ERRNO = EINVAL; + ee78: 000eef80 call eef8 + ee7c: 1007883a mov r3,r2 + ee80: 00800584 movi r2,22 + ee84: 18800015 stw r2,0(r3) + return -EINVAL; + ee88: 00bffa84 movi r2,-22 + ee8c: e0bfff15 stw r2,-4(fp) + ee90: 00001306 br eee0 + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + ee94: e0fffd17 ldw r3,-12(fp) + ee98: e0bffe17 ldw r2,-8(fp) + ee9c: e0bffb15 stw r2,-20(fp) + eea0: e0fffc15 stw r3,-16(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + eea4: e0fffc17 ldw r3,-16(fp) + eea8: e0bffb17 ldw r2,-20(fp) + eeac: 18800115 stw r2,4(r3) + entry->next = list->next; + eeb0: e0bffb17 ldw r2,-20(fp) + eeb4: 10c00017 ldw r3,0(r2) + eeb8: e0bffc17 ldw r2,-16(fp) + eebc: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + eec0: e0bffb17 ldw r2,-20(fp) + eec4: 10c00017 ldw r3,0(r2) + eec8: e0bffc17 ldw r2,-16(fp) + eecc: 18800115 stw r2,4(r3) + list->next = entry; + eed0: e0fffb17 ldw r3,-20(fp) + eed4: e0bffc17 ldw r2,-16(fp) + eed8: 18800015 stw r2,0(r3) + + return 0; + eedc: e03fff15 stw zero,-4(fp) + eee0: e0bfff17 ldw r2,-4(fp) +} + eee4: e037883a mov sp,fp + eee8: dfc00117 ldw ra,4(sp) + eeec: df000017 ldw fp,0(sp) + eef0: dec00204 addi sp,sp,8 + eef4: f800283a ret + +0000eef8 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + eef8: defffd04 addi sp,sp,-12 + eefc: dfc00215 stw ra,8(sp) + ef00: df000115 stw fp,4(sp) + ef04: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + ef08: 00800074 movhi r2,1 + ef0c: 10888904 addi r2,r2,8740 + ef10: 10800017 ldw r2,0(r2) + ef14: 1005003a cmpeq r2,r2,zero + ef18: 1000061e bne r2,zero,ef34 + ef1c: 00800074 movhi r2,1 + ef20: 10888904 addi r2,r2,8740 + ef24: 10800017 ldw r2,0(r2) + ef28: 103ee83a callr r2 + ef2c: e0bfff15 stw r2,-4(fp) + ef30: 00000306 br ef40 + ef34: 00800074 movhi r2,1 + ef38: 108f7c04 addi r2,r2,15856 + ef3c: e0bfff15 stw r2,-4(fp) + ef40: e0bfff17 ldw r2,-4(fp) +} + ef44: e037883a mov sp,fp + ef48: dfc00117 ldw ra,4(sp) + ef4c: df000017 ldw fp,0(sp) + ef50: dec00204 addi sp,sp,8 + ef54: f800283a ret + +0000ef58 <_do_ctors>: +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + ef58: defffd04 addi sp,sp,-12 + ef5c: dfc00215 stw ra,8(sp) + ef60: df000115 stw fp,4(sp) + ef64: df000104 addi fp,sp,4 + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + ef68: 00bfff04 movi r2,-4 + ef6c: 00c00074 movhi r3,1 + ef70: 18ffe404 addi r3,r3,-112 + ef74: 1885883a add r2,r3,r2 + ef78: e0bfff15 stw r2,-4(fp) + ef7c: 00000606 br ef98 <_do_ctors+0x40> + (*ctor) (); + ef80: e0bfff17 ldw r2,-4(fp) + ef84: 10800017 ldw r2,0(r2) + ef88: 103ee83a callr r2 + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + ef8c: e0bfff17 ldw r2,-4(fp) + ef90: 10bfff04 addi r2,r2,-4 + ef94: e0bfff15 stw r2,-4(fp) + ef98: e0ffff17 ldw r3,-4(fp) + ef9c: 00800074 movhi r2,1 + efa0: 10bfe304 addi r2,r2,-116 + efa4: 18bff62e bgeu r3,r2,ef80 <_do_ctors+0x28> + (*ctor) (); +} + efa8: e037883a mov sp,fp + efac: dfc00117 ldw ra,4(sp) + efb0: df000017 ldw fp,0(sp) + efb4: dec00204 addi sp,sp,8 + efb8: f800283a ret + +0000efbc <_do_dtors>: +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + efbc: defffd04 addi sp,sp,-12 + efc0: dfc00215 stw ra,8(sp) + efc4: df000115 stw fp,4(sp) + efc8: df000104 addi fp,sp,4 + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + efcc: 00bfff04 movi r2,-4 + efd0: 00c00074 movhi r3,1 + efd4: 18ffe404 addi r3,r3,-112 + efd8: 1885883a add r2,r3,r2 + efdc: e0bfff15 stw r2,-4(fp) + efe0: 00000606 br effc <_do_dtors+0x40> + (*dtor) (); + efe4: e0bfff17 ldw r2,-4(fp) + efe8: 10800017 ldw r2,0(r2) + efec: 103ee83a callr r2 + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + eff0: e0bfff17 ldw r2,-4(fp) + eff4: 10bfff04 addi r2,r2,-4 + eff8: e0bfff15 stw r2,-4(fp) + effc: e0ffff17 ldw r3,-4(fp) + f000: 00800074 movhi r2,1 + f004: 10bfe404 addi r2,r2,-112 + f008: 18bff62e bgeu r3,r2,efe4 <_do_dtors+0x28> + (*dtor) (); +} + f00c: e037883a mov sp,fp + f010: dfc00117 ldw ra,4(sp) + f014: df000017 ldw fp,0(sp) + f018: dec00204 addi sp,sp,8 + f01c: f800283a ret + +0000f020 : +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ + f020: deffff04 addi sp,sp,-4 + f024: df000015 stw fp,0(sp) + f028: d839883a mov fp,sp +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); +#endif +} + f02c: e037883a mov sp,fp + f030: df000017 ldw fp,0(sp) + f034: dec00104 addi sp,sp,4 + f038: f800283a ret + +0000f03c : + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + f03c: defff904 addi sp,sp,-28 + f040: dfc00615 stw ra,24(sp) + f044: df000515 stw fp,20(sp) + f048: df000504 addi fp,sp,20 + f04c: e13ffc15 stw r4,-16(fp) + f050: e17ffd15 stw r5,-12(fp) + f054: e1bffe15 stw r6,-8(fp) + f058: e1ffff15 stw r7,-4(fp) + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); + f05c: e0800217 ldw r2,8(fp) + f060: d8800015 stw r2,0(sp) + f064: e13ffc17 ldw r4,-16(fp) + f068: e17ffd17 ldw r5,-12(fp) + f06c: e1bffe17 ldw r6,-8(fp) + f070: e1ffff17 ldw r7,-4(fp) + f074: 000f2100 call f210 +} + f078: e037883a mov sp,fp + f07c: dfc00117 ldw ra,4(sp) + f080: df000017 ldw fp,0(sp) + f084: dec00204 addi sp,sp,8 + f088: f800283a ret + +0000f08c : + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + f08c: defff904 addi sp,sp,-28 + f090: df000615 stw fp,24(sp) + f094: df000604 addi fp,sp,24 + f098: e13ffe15 stw r4,-8(fp) + f09c: e17fff15 stw r5,-4(fp) + f0a0: e0bfff17 ldw r2,-4(fp) + f0a4: e0bffc15 stw r2,-16(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + f0a8: 0005303a rdctl r2,status + f0ac: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + f0b0: e0fffb17 ldw r3,-20(fp) + f0b4: 00bfff84 movi r2,-2 + f0b8: 1884703a and r2,r3,r2 + f0bc: 1001703a wrctl status,r2 + + return context; + f0c0: e0bffb17 ldw r2,-20(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + f0c4: e0bffd15 stw r2,-12(fp) + + alt_irq_active |= (1 << id); + f0c8: e0fffc17 ldw r3,-16(fp) + f0cc: 00800044 movi r2,1 + f0d0: 10c4983a sll r2,r2,r3 + f0d4: 1007883a mov r3,r2 + f0d8: 00800074 movhi r2,1 + f0dc: 108f8004 addi r2,r2,15872 + f0e0: 10800017 ldw r2,0(r2) + f0e4: 1886b03a or r3,r3,r2 + f0e8: 00800074 movhi r2,1 + f0ec: 108f8004 addi r2,r2,15872 + f0f0: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + f0f4: 00800074 movhi r2,1 + f0f8: 108f8004 addi r2,r2,15872 + f0fc: 10800017 ldw r2,0(r2) + f100: 100170fa wrctl ienable,r2 + f104: e0bffd17 ldw r2,-12(fp) + f108: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + f10c: e0bffa17 ldw r2,-24(fp) + f110: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + f114: 0005883a mov r2,zero + return alt_irq_enable(irq); +} + f118: e037883a mov sp,fp + f11c: df000017 ldw fp,0(sp) + f120: dec00104 addi sp,sp,4 + f124: f800283a ret + +0000f128 : + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + f128: defff904 addi sp,sp,-28 + f12c: df000615 stw fp,24(sp) + f130: df000604 addi fp,sp,24 + f134: e13ffe15 stw r4,-8(fp) + f138: e17fff15 stw r5,-4(fp) + f13c: e0bfff17 ldw r2,-4(fp) + f140: e0bffc15 stw r2,-16(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + f144: 0005303a rdctl r2,status + f148: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + f14c: e0fffb17 ldw r3,-20(fp) + f150: 00bfff84 movi r2,-2 + f154: 1884703a and r2,r3,r2 + f158: 1001703a wrctl status,r2 + + return context; + f15c: e0bffb17 ldw r2,-20(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + f160: e0bffd15 stw r2,-12(fp) + + alt_irq_active &= ~(1 << id); + f164: e0fffc17 ldw r3,-16(fp) + f168: 00800044 movi r2,1 + f16c: 10c4983a sll r2,r2,r3 + f170: 0084303a nor r2,zero,r2 + f174: 1007883a mov r3,r2 + f178: 00800074 movhi r2,1 + f17c: 108f8004 addi r2,r2,15872 + f180: 10800017 ldw r2,0(r2) + f184: 1886703a and r3,r3,r2 + f188: 00800074 movhi r2,1 + f18c: 108f8004 addi r2,r2,15872 + f190: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + f194: 00800074 movhi r2,1 + f198: 108f8004 addi r2,r2,15872 + f19c: 10800017 ldw r2,0(r2) + f1a0: 100170fa wrctl ienable,r2 + f1a4: e0bffd17 ldw r2,-12(fp) + f1a8: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + f1ac: e0bffa17 ldw r2,-24(fp) + f1b0: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + f1b4: 0005883a mov r2,zero + return alt_irq_disable(irq); +} + f1b8: e037883a mov sp,fp + f1bc: df000017 ldw fp,0(sp) + f1c0: dec00104 addi sp,sp,4 + f1c4: f800283a ret + +0000f1c8 : + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + f1c8: defffc04 addi sp,sp,-16 + f1cc: df000315 stw fp,12(sp) + f1d0: df000304 addi fp,sp,12 + f1d4: e13ffe15 stw r4,-8(fp) + f1d8: e17fff15 stw r5,-4(fp) + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + f1dc: 000530fa rdctl r2,ienable + f1e0: e0bffd15 stw r2,-12(fp) + + return (irq_enabled & (1 << irq)) ? 1: 0; + f1e4: e0ffff17 ldw r3,-4(fp) + f1e8: 00800044 movi r2,1 + f1ec: 10c4983a sll r2,r2,r3 + f1f0: 1007883a mov r3,r2 + f1f4: e0bffd17 ldw r2,-12(fp) + f1f8: 1884703a and r2,r3,r2 + f1fc: 1004c03a cmpne r2,r2,zero +} + f200: e037883a mov sp,fp + f204: df000017 ldw fp,0(sp) + f208: dec00104 addi sp,sp,4 + f20c: f800283a ret + +0000f210 : + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + f210: defff404 addi sp,sp,-48 + f214: dfc00b15 stw ra,44(sp) + f218: df000a15 stw fp,40(sp) + f21c: df000a04 addi fp,sp,40 + f220: e13ffb15 stw r4,-20(fp) + f224: e17ffc15 stw r5,-16(fp) + f228: e1bffd15 stw r6,-12(fp) + f22c: e1fffe15 stw r7,-8(fp) + int rc = -EINVAL; + f230: 00bffa84 movi r2,-22 + f234: e0bffa15 stw r2,-24(fp) + int id = irq; /* IRQ interpreted as the interrupt ID. */ + f238: e0bffc17 ldw r2,-16(fp) + f23c: e0bff915 stw r2,-28(fp) + alt_irq_context status; + + if (id < ALT_NIRQ) + f240: e0bff917 ldw r2,-28(fp) + f244: 10800808 cmpgei r2,r2,32 + f248: 1000291e bne r2,zero,f2f0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + f24c: 0005303a rdctl r2,status + f250: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + f254: e0fff717 ldw r3,-36(fp) + f258: 00bfff84 movi r2,-2 + f25c: 1884703a and r2,r3,r2 + f260: 1001703a wrctl status,r2 + + return context; + f264: e0bff717 ldw r2,-36(fp) + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + f268: e0bff815 stw r2,-32(fp) + + alt_irq[id].handler = isr; + f26c: e0bff917 ldw r2,-28(fp) + f270: 00c00074 movhi r3,1 + f274: 18d0d104 addi r3,r3,17220 + f278: 100490fa slli r2,r2,3 + f27c: 10c7883a add r3,r2,r3 + f280: e0bffd17 ldw r2,-12(fp) + f284: 18800015 stw r2,0(r3) + alt_irq[id].context = isr_context; + f288: e0bff917 ldw r2,-28(fp) + f28c: 00c00074 movhi r3,1 + f290: 18d0d104 addi r3,r3,17220 + f294: 100490fa slli r2,r2,3 + f298: 10c5883a add r2,r2,r3 + f29c: 10c00104 addi r3,r2,4 + f2a0: e0bffe17 ldw r2,-8(fp) + f2a4: 18800015 stw r2,0(r3) + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + f2a8: e0bffd17 ldw r2,-12(fp) + f2ac: 1005003a cmpeq r2,r2,zero + f2b0: 1000051e bne r2,zero,f2c8 + f2b4: e17ff917 ldw r5,-28(fp) + f2b8: e13ffb17 ldw r4,-20(fp) + f2bc: 000f08c0 call f08c + f2c0: e0bfff15 stw r2,-4(fp) + f2c4: 00000406 br f2d8 + f2c8: e17ff917 ldw r5,-28(fp) + f2cc: e13ffb17 ldw r4,-20(fp) + f2d0: 000f1280 call f128 + f2d4: e0bfff15 stw r2,-4(fp) + f2d8: e0bfff17 ldw r2,-4(fp) + f2dc: e0bffa15 stw r2,-24(fp) + f2e0: e0bff817 ldw r2,-32(fp) + f2e4: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + f2e8: e0bff617 ldw r2,-40(fp) + f2ec: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + } + + return rc; + f2f0: e0bffa17 ldw r2,-24(fp) +} + f2f4: e037883a mov sp,fp + f2f8: dfc00117 ldw ra,4(sp) + f2fc: df000017 ldw fp,0(sp) + f300: dec00204 addi sp,sp,8 + f304: f800283a ret + +0000f308 : + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + f308: defff804 addi sp,sp,-32 + f30c: dfc00715 stw ra,28(sp) + f310: df000615 stw fp,24(sp) + f314: dc000515 stw r16,20(sp) + f318: df000504 addi fp,sp,20 + f31c: e13ffc15 stw r4,-16(fp) + f320: e17ffd15 stw r5,-12(fp) + f324: e1bffe15 stw r6,-8(fp) + f328: e1ffff15 stw r7,-4(fp) + int old; + + old = open (name, flags, mode); + f32c: e13ffd17 ldw r4,-12(fp) + f330: e17ffe17 ldw r5,-8(fp) + f334: e1bfff17 ldw r6,-4(fp) + f338: 000f5500 call f550 + f33c: e0bffb15 stw r2,-20(fp) + + if (old >= 0) + f340: e0bffb17 ldw r2,-20(fp) + f344: 1004803a cmplt r2,r2,zero + f348: 10001f1e bne r2,zero,f3c8 + { + fd->dev = alt_fd_list[old].dev; + f34c: e13ffb17 ldw r4,-20(fp) + f350: 04000074 movhi r16,1 + f354: 8403bc04 addi r16,r16,3824 + f358: 01400304 movi r5,12 + f35c: 0002c240 call 2c24 <__mulsi3> + f360: 1405883a add r2,r2,r16 + f364: 10c00017 ldw r3,0(r2) + f368: e0bffc17 ldw r2,-16(fp) + f36c: 10c00015 stw r3,0(r2) + fd->priv = alt_fd_list[old].priv; + f370: e13ffb17 ldw r4,-20(fp) + f374: 04000074 movhi r16,1 + f378: 8403bc04 addi r16,r16,3824 + f37c: 01400304 movi r5,12 + f380: 0002c240 call 2c24 <__mulsi3> + f384: 1405883a add r2,r2,r16 + f388: 10800104 addi r2,r2,4 + f38c: 10c00017 ldw r3,0(r2) + f390: e0bffc17 ldw r2,-16(fp) + f394: 10c00115 stw r3,4(r2) + fd->fd_flags = alt_fd_list[old].fd_flags; + f398: e13ffb17 ldw r4,-20(fp) + f39c: 04000074 movhi r16,1 + f3a0: 8403bc04 addi r16,r16,3824 + f3a4: 01400304 movi r5,12 + f3a8: 0002c240 call 2c24 <__mulsi3> + f3ac: 1405883a add r2,r2,r16 + f3b0: 10800204 addi r2,r2,8 + f3b4: 10c00017 ldw r3,0(r2) + f3b8: e0bffc17 ldw r2,-16(fp) + f3bc: 10c00215 stw r3,8(r2) + + alt_release_fd (old); + f3c0: e13ffb17 ldw r4,-20(fp) + f3c4: 000cd440 call cd44 + } +} + f3c8: e037883a mov sp,fp + f3cc: dfc00217 ldw ra,8(sp) + f3d0: df000117 ldw fp,4(sp) + f3d4: dc000017 ldw r16,0(sp) + f3d8: dec00304 addi sp,sp,12 + f3dc: f800283a ret + +0000f3e0 : + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + f3e0: defffb04 addi sp,sp,-20 + f3e4: dfc00415 stw ra,16(sp) + f3e8: df000315 stw fp,12(sp) + f3ec: df000304 addi fp,sp,12 + f3f0: e13ffd15 stw r4,-12(fp) + f3f4: e17ffe15 stw r5,-8(fp) + f3f8: e1bfff15 stw r6,-4(fp) + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + f3fc: 01000074 movhi r4,1 + f400: 2103bf04 addi r4,r4,3836 + f404: e17ffd17 ldw r5,-12(fp) + f408: 01800044 movi r6,1 + f40c: 01c07fc4 movi r7,511 + f410: 000f3080 call f308 + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + f414: 01000074 movhi r4,1 + f418: 2103bc04 addi r4,r4,3824 + f41c: e17ffe17 ldw r5,-8(fp) + f420: 000d883a mov r6,zero + f424: 01c07fc4 movi r7,511 + f428: 000f3080 call f308 + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); + f42c: 01000074 movhi r4,1 + f430: 2103c204 addi r4,r4,3848 + f434: e17fff17 ldw r5,-4(fp) + f438: 01800044 movi r6,1 + f43c: 01c07fc4 movi r7,511 + f440: 000f3080 call f308 +} + f444: e037883a mov sp,fp + f448: dfc00117 ldw ra,4(sp) + f44c: df000017 ldw fp,0(sp) + f450: dec00204 addi sp,sp,8 + f454: f800283a ret + +0000f458 : + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + f458: defffa04 addi sp,sp,-24 + f45c: dfc00515 stw ra,20(sp) + f460: df000415 stw fp,16(sp) + f464: dc000315 stw r16,12(sp) + f468: df000304 addi fp,sp,12 + f46c: e13ffe15 stw r4,-8(fp) + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + f470: e0bffe17 ldw r2,-8(fp) + f474: 10800217 ldw r2,8(r2) + f478: 10d00034 orhi r3,r2,16384 + f47c: e0bffe17 ldw r2,-8(fp) + f480: 10c00215 stw r3,8(r2) + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + f484: e03ffd15 stw zero,-12(fp) + f488: 00002306 br f518 + { + if ((alt_fd_list[i].dev == fd->dev) && + f48c: e13ffd17 ldw r4,-12(fp) + f490: 04000074 movhi r16,1 + f494: 8403bc04 addi r16,r16,3824 + f498: 01400304 movi r5,12 + f49c: 0002c240 call 2c24 <__mulsi3> + f4a0: 1405883a add r2,r2,r16 + f4a4: 10c00017 ldw r3,0(r2) + f4a8: e0bffe17 ldw r2,-8(fp) + f4ac: 10800017 ldw r2,0(r2) + f4b0: 1880161e bne r3,r2,f50c + f4b4: e13ffd17 ldw r4,-12(fp) + f4b8: 04000074 movhi r16,1 + f4bc: 8403bc04 addi r16,r16,3824 + f4c0: 01400304 movi r5,12 + f4c4: 0002c240 call 2c24 <__mulsi3> + f4c8: 1405883a add r2,r2,r16 + f4cc: 10800204 addi r2,r2,8 + f4d0: 10800017 ldw r2,0(r2) + f4d4: 1004403a cmpge r2,r2,zero + f4d8: 10000c1e bne r2,zero,f50c + f4dc: e13ffd17 ldw r4,-12(fp) + f4e0: 01400304 movi r5,12 + f4e4: 0002c240 call 2c24 <__mulsi3> + f4e8: 1007883a mov r3,r2 + f4ec: 00800074 movhi r2,1 + f4f0: 1083bc04 addi r2,r2,3824 + f4f4: 1887883a add r3,r3,r2 + f4f8: e0bffe17 ldw r2,-8(fp) + f4fc: 18800326 beq r3,r2,f50c + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + f500: 00bffcc4 movi r2,-13 + f504: e0bfff15 stw r2,-4(fp) + f508: 00000a06 br f534 + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + f50c: e0bffd17 ldw r2,-12(fp) + f510: 10800044 addi r2,r2,1 + f514: e0bffd15 stw r2,-12(fp) + f518: 00800074 movhi r2,1 + f51c: 10888804 addi r2,r2,8736 + f520: 10800017 ldw r2,0(r2) + f524: 1007883a mov r3,r2 + f528: e0bffd17 ldw r2,-12(fp) + f52c: 18bfd72e bgeu r3,r2,f48c + } + } + + /* The device is not locked */ + + return 0; + f530: e03fff15 stw zero,-4(fp) + f534: e0bfff17 ldw r2,-4(fp) +} + f538: e037883a mov sp,fp + f53c: dfc00217 ldw ra,8(sp) + f540: df000117 ldw fp,4(sp) + f544: dc000017 ldw r16,0(sp) + f548: dec00304 addi sp,sp,12 + f54c: f800283a ret + +0000f550 : + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + f550: defff404 addi sp,sp,-48 + f554: dfc00b15 stw ra,44(sp) + f558: df000a15 stw fp,40(sp) + f55c: df000a04 addi fp,sp,40 + f560: e13ffb15 stw r4,-20(fp) + f564: e17ffc15 stw r5,-16(fp) + f568: e1bffd15 stw r6,-12(fp) + alt_dev* dev; + alt_fd* fd; + int index = -1; + f56c: 00bfffc4 movi r2,-1 + f570: e0bff815 stw r2,-32(fp) + int status = -ENODEV; + f574: 00bffb44 movi r2,-19 + f578: e0bff715 stw r2,-36(fp) + int isafs = 0; + f57c: e03ff615 stw zero,-40(fp) + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + f580: e13ffb17 ldw r4,-20(fp) + f584: 01400074 movhi r5,1 + f588: 29488604 addi r5,r5,8728 + f58c: 000f9000 call f900 + f590: e0bffa15 stw r2,-24(fp) + f594: e0bffa17 ldw r2,-24(fp) + f598: 1004c03a cmpne r2,r2,zero + f59c: 1000051e bne r2,zero,f5b4 + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + f5a0: e13ffb17 ldw r4,-20(fp) + f5a4: 000f9940 call f994 + f5a8: e0bffa15 stw r2,-24(fp) + isafs = 1; + f5ac: 00800044 movi r2,1 + f5b0: e0bff615 stw r2,-40(fp) + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + f5b4: e0bffa17 ldw r2,-24(fp) + f5b8: 1005003a cmpeq r2,r2,zero + f5bc: 1000311e bne r2,zero,f684 + { + if ((index = alt_get_fd (dev)) < 0) + f5c0: e13ffa17 ldw r4,-24(fp) + f5c4: 000fab40 call fab4 + f5c8: e0bff815 stw r2,-32(fp) + f5cc: e0bff817 ldw r2,-32(fp) + f5d0: 1004403a cmpge r2,r2,zero + f5d4: 1000031e bne r2,zero,f5e4 + { + status = index; + f5d8: e0bff817 ldw r2,-32(fp) + f5dc: e0bff715 stw r2,-36(fp) + f5e0: 00002a06 br f68c + } + else + { + fd = &alt_fd_list[index]; + f5e4: e13ff817 ldw r4,-32(fp) + f5e8: 01400304 movi r5,12 + f5ec: 0002c240 call 2c24 <__mulsi3> + f5f0: 1007883a mov r3,r2 + f5f4: 00800074 movhi r2,1 + f5f8: 1083bc04 addi r2,r2,3824 + f5fc: 1885883a add r2,r3,r2 + f600: e0bff915 stw r2,-28(fp) + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + f604: e0fffc17 ldw r3,-16(fp) + f608: 00900034 movhi r2,16384 + f60c: 10bfffc4 addi r2,r2,-1 + f610: 1886703a and r3,r3,r2 + f614: e0bff917 ldw r2,-28(fp) + f618: 10c00215 stw r3,8(r2) + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + f61c: e0bff617 ldw r2,-40(fp) + f620: 1004c03a cmpne r2,r2,zero + f624: 1000061e bne r2,zero,f640 + f628: e13ff917 ldw r4,-28(fp) + f62c: 000f4580 call f458 + f630: e0bff715 stw r2,-36(fp) + f634: e0bff717 ldw r2,-36(fp) + f638: 1004803a cmplt r2,r2,zero + f63c: 1000131e bne r2,zero,f68c + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + f640: e0bffa17 ldw r2,-24(fp) + f644: 10800317 ldw r2,12(r2) + f648: 1005003a cmpeq r2,r2,zero + f64c: 1000091e bne r2,zero,f674 + f650: e0bffa17 ldw r2,-24(fp) + f654: 10800317 ldw r2,12(r2) + f658: e13ff917 ldw r4,-28(fp) + f65c: e17ffb17 ldw r5,-20(fp) + f660: e1bffc17 ldw r6,-16(fp) + f664: e1fffd17 ldw r7,-12(fp) + f668: 103ee83a callr r2 + f66c: e0bfff15 stw r2,-4(fp) + f670: 00000106 br f678 + f674: e03fff15 stw zero,-4(fp) + f678: e0bfff17 ldw r2,-4(fp) + f67c: e0bff715 stw r2,-36(fp) + f680: 00000206 br f68c + } + } + } + else + { + status = -ENODEV; + f684: 00bffb44 movi r2,-19 + f688: e0bff715 stw r2,-36(fp) + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + f68c: e0bff717 ldw r2,-36(fp) + f690: 1004403a cmpge r2,r2,zero + f694: 1000091e bne r2,zero,f6bc + { + alt_release_fd (index); + f698: e13ff817 ldw r4,-32(fp) + f69c: 000cd440 call cd44 + ALT_ERRNO = -status; + f6a0: 000f6dc0 call f6dc + f6a4: e0fff717 ldw r3,-36(fp) + f6a8: 00c7c83a sub r3,zero,r3 + f6ac: 10c00015 stw r3,0(r2) + return -1; + f6b0: 00bfffc4 movi r2,-1 + f6b4: e0bffe15 stw r2,-8(fp) + f6b8: 00000206 br f6c4 + } + + /* return the reference upon success */ + + return index; + f6bc: e0bff817 ldw r2,-32(fp) + f6c0: e0bffe15 stw r2,-8(fp) + f6c4: e0bffe17 ldw r2,-8(fp) +} + f6c8: e037883a mov sp,fp + f6cc: dfc00117 ldw ra,4(sp) + f6d0: df000017 ldw fp,0(sp) + f6d4: dec00204 addi sp,sp,8 + f6d8: f800283a ret + +0000f6dc : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + f6dc: defffd04 addi sp,sp,-12 + f6e0: dfc00215 stw ra,8(sp) + f6e4: df000115 stw fp,4(sp) + f6e8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + f6ec: 00800074 movhi r2,1 + f6f0: 10888904 addi r2,r2,8740 + f6f4: 10800017 ldw r2,0(r2) + f6f8: 1005003a cmpeq r2,r2,zero + f6fc: 1000061e bne r2,zero,f718 + f700: 00800074 movhi r2,1 + f704: 10888904 addi r2,r2,8740 + f708: 10800017 ldw r2,0(r2) + f70c: 103ee83a callr r2 + f710: e0bfff15 stw r2,-4(fp) + f714: 00000306 br f724 + f718: 00800074 movhi r2,1 + f71c: 108f7c04 addi r2,r2,15856 + f720: e0bfff15 stw r2,-4(fp) + f724: e0bfff17 ldw r2,-4(fp) +} + f728: e037883a mov sp,fp + f72c: dfc00117 ldw ra,4(sp) + f730: df000017 ldw fp,0(sp) + f734: dec00204 addi sp,sp,8 + f738: f800283a ret + +0000f73c : + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + f73c: defffa04 addi sp,sp,-24 + f740: df000515 stw fp,20(sp) + f744: df000504 addi fp,sp,20 + f748: e13fff15 stw r4,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + f74c: 0005303a rdctl r2,status + f750: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + f754: e0fffd17 ldw r3,-12(fp) + f758: 00bfff84 movi r2,-2 + f75c: 1884703a and r2,r3,r2 + f760: 1001703a wrctl status,r2 + + return context; + f764: e0bffd17 ldw r2,-12(fp) + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + f768: e0bffe15 stw r2,-8(fp) + alt_llist_remove (&alarm->llist); + f76c: e0bfff17 ldw r2,-4(fp) + f770: e0bffc15 stw r2,-16(fp) + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + f774: e0bffc17 ldw r2,-16(fp) + f778: 10c00017 ldw r3,0(r2) + f77c: e0bffc17 ldw r2,-16(fp) + f780: 10800117 ldw r2,4(r2) + f784: 18800115 stw r2,4(r3) + entry->previous->next = entry->next; + f788: e0bffc17 ldw r2,-16(fp) + f78c: 10c00117 ldw r3,4(r2) + f790: e0bffc17 ldw r2,-16(fp) + f794: 10800017 ldw r2,0(r2) + f798: 18800015 stw r2,0(r3) + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + f79c: e0fffc17 ldw r3,-16(fp) + f7a0: e0bffc17 ldw r2,-16(fp) + f7a4: 18800115 stw r2,4(r3) + entry->next = entry; + f7a8: e0fffc17 ldw r3,-16(fp) + f7ac: e0bffc17 ldw r2,-16(fp) + f7b0: 18800015 stw r2,0(r3) + f7b4: e0bffe17 ldw r2,-8(fp) + f7b8: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + f7bc: e0bffb17 ldw r2,-20(fp) + f7c0: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); +} + f7c4: e037883a mov sp,fp + f7c8: df000017 ldw fp,0(sp) + f7cc: dec00104 addi sp,sp,4 + f7d0: f800283a ret + +0000f7d4 : + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + f7d4: defffb04 addi sp,sp,-20 + f7d8: dfc00415 stw ra,16(sp) + f7dc: df000315 stw fp,12(sp) + f7e0: df000304 addi fp,sp,12 + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + f7e4: d0a01117 ldw r2,-32700(gp) + f7e8: e0bffe15 stw r2,-8(fp) + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + f7ec: d0a70617 ldw r2,-25576(gp) + f7f0: 10800044 addi r2,r2,1 + f7f4: d0a70615 stw r2,-25576(gp) + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + f7f8: 00003106 br f8c0 + { + next = (alt_alarm*) alarm->llist.next; + f7fc: e0bffe17 ldw r2,-8(fp) + f800: 10800017 ldw r2,0(r2) + f804: e0bfff15 stw r2,-4(fp) + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + f808: e0bffe17 ldw r2,-8(fp) + f80c: 10800403 ldbu r2,16(r2) + f810: 10803fcc andi r2,r2,255 + f814: 1005003a cmpeq r2,r2,zero + f818: 1000051e bne r2,zero,f830 + f81c: d0a70617 ldw r2,-25576(gp) + f820: 1004c03a cmpne r2,r2,zero + f824: 1000021e bne r2,zero,f830 + { + alarm->rollover = 0; + f828: e0bffe17 ldw r2,-8(fp) + f82c: 10000405 stb zero,16(r2) + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + f830: e0bffe17 ldw r2,-8(fp) + f834: 10c00217 ldw r3,8(r2) + f838: d0a70617 ldw r2,-25576(gp) + f83c: 10c01e36 bltu r2,r3,f8b8 + f840: e0bffe17 ldw r2,-8(fp) + f844: 10800403 ldbu r2,16(r2) + f848: 10803fcc andi r2,r2,255 + f84c: 1004c03a cmpne r2,r2,zero + f850: 1000191e bne r2,zero,f8b8 + { + next_callback = alarm->callback (alarm->context); + f854: e0bffe17 ldw r2,-8(fp) + f858: 10c00317 ldw r3,12(r2) + f85c: e0bffe17 ldw r2,-8(fp) + f860: 11000517 ldw r4,20(r2) + f864: 183ee83a callr r3 + f868: e0bffd15 stw r2,-12(fp) + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + f86c: e0bffd17 ldw r2,-12(fp) + f870: 1004c03a cmpne r2,r2,zero + f874: 1000031e bne r2,zero,f884 + { + alt_alarm_stop (alarm); + f878: e13ffe17 ldw r4,-8(fp) + f87c: 000f73c0 call f73c + f880: 00000d06 br f8b8 + } + else + { + alarm->time += next_callback; + f884: e0bffe17 ldw r2,-8(fp) + f888: 10c00217 ldw r3,8(r2) + f88c: e0bffd17 ldw r2,-12(fp) + f890: 1887883a add r3,r3,r2 + f894: e0bffe17 ldw r2,-8(fp) + f898: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + f89c: e0bffe17 ldw r2,-8(fp) + f8a0: 10c00217 ldw r3,8(r2) + f8a4: d0a70617 ldw r2,-25576(gp) + f8a8: 1880032e bgeu r3,r2,f8b8 + { + alarm->rollover = 1; + f8ac: e0fffe17 ldw r3,-8(fp) + f8b0: 00800044 movi r2,1 + f8b4: 18800405 stb r2,16(r3) + } + } + } + alarm = next; + f8b8: e0bfff17 ldw r2,-4(fp) + f8bc: e0bffe15 stw r2,-8(fp) + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + f8c0: d0e01104 addi r3,gp,-32700 + f8c4: e0bffe17 ldw r2,-8(fp) + f8c8: 10ffcc1e bne r2,r3,f7fc + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); +} + f8cc: e037883a mov sp,fp + f8d0: dfc00117 ldw ra,4(sp) + f8d4: df000017 ldw fp,0(sp) + f8d8: dec00204 addi sp,sp,8 + f8dc: f800283a ret + +0000f8e0 : +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + f8e0: deffff04 addi sp,sp,-4 + f8e4: df000015 stw fp,0(sp) + f8e8: d839883a mov fp,sp + NIOS2_WRITE_IENABLE(0); + f8ec: 000170fa wrctl ienable,zero +} + f8f0: e037883a mov sp,fp + f8f4: df000017 ldw fp,0(sp) + f8f8: dec00104 addi sp,sp,4 + f8fc: f800283a ret + +0000f900 : + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + f900: defff904 addi sp,sp,-28 + f904: dfc00615 stw ra,24(sp) + f908: df000515 stw fp,20(sp) + f90c: df000504 addi fp,sp,20 + f910: e13ffd15 stw r4,-12(fp) + f914: e17ffe15 stw r5,-8(fp) + alt_dev* next = (alt_dev*) llist->next; + f918: e0bffe17 ldw r2,-8(fp) + f91c: 10800017 ldw r2,0(r2) + f920: e0bffc15 stw r2,-16(fp) + alt_32 len; + + len = strlen(name) + 1; + f924: e13ffd17 ldw r4,-12(fp) + f928: 0002d300 call 2d30 + f92c: 10800044 addi r2,r2,1 + f930: e0bffb15 stw r2,-20(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + f934: 00000d06 br f96c + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + f938: e0bffc17 ldw r2,-16(fp) + f93c: 11000217 ldw r4,8(r2) + f940: e1bffb17 ldw r6,-20(fp) + f944: e17ffd17 ldw r5,-12(fp) + f948: 000fbd00 call fbd0 + f94c: 1004c03a cmpne r2,r2,zero + f950: 1000031e bne r2,zero,f960 + { + /* match found */ + + return next; + f954: e0bffc17 ldw r2,-16(fp) + f958: e0bfff15 stw r2,-4(fp) + f95c: 00000706 br f97c + } + next = (alt_dev*) next->llist.next; + f960: e0bffc17 ldw r2,-16(fp) + f964: 10800017 ldw r2,0(r2) + f968: e0bffc15 stw r2,-16(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + f96c: e0fffe17 ldw r3,-8(fp) + f970: e0bffc17 ldw r2,-16(fp) + f974: 10fff01e bne r2,r3,f938 + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + f978: e03fff15 stw zero,-4(fp) + f97c: e0bfff17 ldw r2,-4(fp) +} + f980: e037883a mov sp,fp + f984: dfc00117 ldw ra,4(sp) + f988: df000017 ldw fp,0(sp) + f98c: dec00204 addi sp,sp,8 + f990: f800283a ret + +0000f994 : + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + f994: defffa04 addi sp,sp,-24 + f998: dfc00515 stw ra,20(sp) + f99c: df000415 stw fp,16(sp) + f9a0: df000404 addi fp,sp,16 + f9a4: e13ffe15 stw r4,-8(fp) + alt_dev* next = (alt_dev*) alt_fs_list.next; + f9a8: 00800074 movhi r2,1 + f9ac: 10888404 addi r2,r2,8720 + f9b0: 10800017 ldw r2,0(r2) + f9b4: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + f9b8: 00003306 br fa88 + { + len = strlen(next->name); + f9bc: e0bffd17 ldw r2,-12(fp) + f9c0: 11000217 ldw r4,8(r2) + f9c4: 0002d300 call 2d30 + f9c8: e0bffc15 stw r2,-16(fp) + + if (next->name[len-1] == '/') + f9cc: e0bffd17 ldw r2,-12(fp) + f9d0: 10c00217 ldw r3,8(r2) + f9d4: e0bffc17 ldw r2,-16(fp) + f9d8: 1885883a add r2,r3,r2 + f9dc: 10bfffc4 addi r2,r2,-1 + f9e0: 10800003 ldbu r2,0(r2) + f9e4: 10803fcc andi r2,r2,255 + f9e8: 1080201c xori r2,r2,128 + f9ec: 10bfe004 addi r2,r2,-128 + f9f0: 10800bd8 cmpnei r2,r2,47 + f9f4: 1000031e bne r2,zero,fa04 + { + len -= 1; + f9f8: e0bffc17 ldw r2,-16(fp) + f9fc: 10bfffc4 addi r2,r2,-1 + fa00: e0bffc15 stw r2,-16(fp) + } + + if (((name[len] == '/') || (name[len] == '\0')) && + fa04: e0bffc17 ldw r2,-16(fp) + fa08: 1007883a mov r3,r2 + fa0c: e0bffe17 ldw r2,-8(fp) + fa10: 1885883a add r2,r3,r2 + fa14: 10800003 ldbu r2,0(r2) + fa18: 10803fcc andi r2,r2,255 + fa1c: 1080201c xori r2,r2,128 + fa20: 10bfe004 addi r2,r2,-128 + fa24: 10800be0 cmpeqi r2,r2,47 + fa28: 10000a1e bne r2,zero,fa54 + fa2c: e0bffc17 ldw r2,-16(fp) + fa30: 1007883a mov r3,r2 + fa34: e0bffe17 ldw r2,-8(fp) + fa38: 1885883a add r2,r3,r2 + fa3c: 10800003 ldbu r2,0(r2) + fa40: 10803fcc andi r2,r2,255 + fa44: 1080201c xori r2,r2,128 + fa48: 10bfe004 addi r2,r2,-128 + fa4c: 1004c03a cmpne r2,r2,zero + fa50: 10000a1e bne r2,zero,fa7c + fa54: e0bffd17 ldw r2,-12(fp) + fa58: 11000217 ldw r4,8(r2) + fa5c: e1bffc17 ldw r6,-16(fp) + fa60: e17ffe17 ldw r5,-8(fp) + fa64: 000fbd00 call fbd0 + fa68: 1004c03a cmpne r2,r2,zero + fa6c: 1000031e bne r2,zero,fa7c + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + fa70: e0bffd17 ldw r2,-12(fp) + fa74: e0bfff15 stw r2,-4(fp) + fa78: 00000806 br fa9c + } + next = (alt_dev*) next->llist.next; + fa7c: e0bffd17 ldw r2,-12(fp) + fa80: 10800017 ldw r2,0(r2) + fa84: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + fa88: 00c00074 movhi r3,1 + fa8c: 18c88404 addi r3,r3,8720 + fa90: e0bffd17 ldw r2,-12(fp) + fa94: 10ffc91e bne r2,r3,f9bc + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + fa98: e03fff15 stw zero,-4(fp) + fa9c: e0bfff17 ldw r2,-4(fp) +} + faa0: e037883a mov sp,fp + faa4: dfc00117 ldw ra,4(sp) + faa8: df000017 ldw fp,0(sp) + faac: dec00204 addi sp,sp,8 + fab0: f800283a ret + +0000fab4 : + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + fab4: defffa04 addi sp,sp,-24 + fab8: dfc00515 stw ra,20(sp) + fabc: df000415 stw fp,16(sp) + fac0: dc000315 stw r16,12(sp) + fac4: df000304 addi fp,sp,12 + fac8: e13fff15 stw r4,-4(fp) + alt_32 i; + int rc = -EMFILE; + facc: 00bffa04 movi r2,-24 + fad0: e0bffd15 stw r2,-12(fp) + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + fad4: e03ffe15 stw zero,-8(fp) + fad8: 00002006 br fb5c + { + if (!alt_fd_list[i].dev) + fadc: e13ffe17 ldw r4,-8(fp) + fae0: 04000074 movhi r16,1 + fae4: 8403bc04 addi r16,r16,3824 + fae8: 01400304 movi r5,12 + faec: 0002c240 call 2c24 <__mulsi3> + faf0: 1405883a add r2,r2,r16 + faf4: 10800017 ldw r2,0(r2) + faf8: 1004c03a cmpne r2,r2,zero + fafc: 1000141e bne r2,zero,fb50 + { + alt_fd_list[i].dev = dev; + fb00: e13ffe17 ldw r4,-8(fp) + fb04: 04000074 movhi r16,1 + fb08: 8403bc04 addi r16,r16,3824 + fb0c: 01400304 movi r5,12 + fb10: 0002c240 call 2c24 <__mulsi3> + fb14: 1407883a add r3,r2,r16 + fb18: e0bfff17 ldw r2,-4(fp) + fb1c: 18800015 stw r2,0(r3) + if (i > alt_max_fd) + fb20: 00800074 movhi r2,1 + fb24: 10888804 addi r2,r2,8736 + fb28: 10c00017 ldw r3,0(r2) + fb2c: e0bffe17 ldw r2,-8(fp) + fb30: 1880040e bge r3,r2,fb44 + { + alt_max_fd = i; + fb34: 00c00074 movhi r3,1 + fb38: 18c88804 addi r3,r3,8736 + fb3c: e0bffe17 ldw r2,-8(fp) + fb40: 18800015 stw r2,0(r3) + } + rc = i; + fb44: e0bffe17 ldw r2,-8(fp) + fb48: e0bffd15 stw r2,-12(fp) + goto alt_get_fd_exit; + fb4c: 00000606 br fb68 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + fb50: e0bffe17 ldw r2,-8(fp) + fb54: 10800044 addi r2,r2,1 + fb58: e0bffe15 stw r2,-8(fp) + fb5c: e0bffe17 ldw r2,-8(fp) + fb60: 10800810 cmplti r2,r2,32 + fb64: 103fdd1e bne r2,zero,fadc + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + + return rc; + fb68: e0bffd17 ldw r2,-12(fp) +} + fb6c: e037883a mov sp,fp + fb70: dfc00217 ldw ra,8(sp) + fb74: df000117 ldw fp,4(sp) + fb78: dc000017 ldw r16,0(sp) + fb7c: dec00304 addi sp,sp,12 + fb80: f800283a ret + +0000fb84 : + fb84: 200b883a mov r5,r4 + fb88: 000d883a mov r6,zero + fb8c: 0009883a mov r4,zero + fb90: 000f883a mov r7,zero + fb94: 000fc441 jmpi fc44 <__register_exitproc> + +0000fb98 : + fb98: defffe04 addi sp,sp,-8 + fb9c: 000b883a mov r5,zero + fba0: dc000015 stw r16,0(sp) + fba4: dfc00115 stw ra,4(sp) + fba8: 2021883a mov r16,r4 + fbac: 000fd7c0 call fd7c <__call_exitprocs> + fbb0: 00800074 movhi r2,1 + fbb4: 10887f04 addi r2,r2,8700 + fbb8: 11000017 ldw r4,0(r2) + fbbc: 20800f17 ldw r2,60(r4) + fbc0: 10000126 beq r2,zero,fbc8 + fbc4: 103ee83a callr r2 + fbc8: 8009883a mov r4,r16 + fbcc: 000ff6c0 call ff6c <_exit> + +0000fbd0 : + fbd0: 00c000c4 movi r3,3 + fbd4: 1980032e bgeu r3,r6,fbe4 + fbd8: 2144b03a or r2,r4,r5 + fbdc: 10c4703a and r2,r2,r3 + fbe0: 10000f26 beq r2,zero,fc20 + fbe4: 31ffffc4 addi r7,r6,-1 + fbe8: 3000061e bne r6,zero,fc04 + fbec: 00000a06 br fc18 + fbf0: 39ffffc4 addi r7,r7,-1 + fbf4: 00bfffc4 movi r2,-1 + fbf8: 21000044 addi r4,r4,1 + fbfc: 29400044 addi r5,r5,1 + fc00: 38800526 beq r7,r2,fc18 + fc04: 20c00003 ldbu r3,0(r4) + fc08: 28800003 ldbu r2,0(r5) + fc0c: 18bff826 beq r3,r2,fbf0 + fc10: 1885c83a sub r2,r3,r2 + fc14: f800283a ret + fc18: 0005883a mov r2,zero + fc1c: f800283a ret + fc20: 180f883a mov r7,r3 + fc24: 20c00017 ldw r3,0(r4) + fc28: 28800017 ldw r2,0(r5) + fc2c: 18bfed1e bne r3,r2,fbe4 + fc30: 31bfff04 addi r6,r6,-4 + fc34: 21000104 addi r4,r4,4 + fc38: 29400104 addi r5,r5,4 + fc3c: 39bff936 bltu r7,r6,fc24 + fc40: 003fe806 br fbe4 + +0000fc44 <__register_exitproc>: + fc44: defffa04 addi sp,sp,-24 + fc48: 00800074 movhi r2,1 + fc4c: 10887f04 addi r2,r2,8700 + fc50: dc000015 stw r16,0(sp) + fc54: 14000017 ldw r16,0(r2) + fc58: dd000415 stw r20,16(sp) + fc5c: 2829883a mov r20,r5 + fc60: 81405217 ldw r5,328(r16) + fc64: dcc00315 stw r19,12(sp) + fc68: dc800215 stw r18,8(sp) + fc6c: dc400115 stw r17,4(sp) + fc70: dfc00515 stw ra,20(sp) + fc74: 2023883a mov r17,r4 + fc78: 3027883a mov r19,r6 + fc7c: 3825883a mov r18,r7 + fc80: 28002526 beq r5,zero,fd18 <__register_exitproc+0xd4> + fc84: 29000117 ldw r4,4(r5) + fc88: 008007c4 movi r2,31 + fc8c: 11002716 blt r2,r4,fd2c <__register_exitproc+0xe8> + fc90: 8800101e bne r17,zero,fcd4 <__register_exitproc+0x90> + fc94: 2105883a add r2,r4,r4 + fc98: 1085883a add r2,r2,r2 + fc9c: 20c00044 addi r3,r4,1 + fca0: 1145883a add r2,r2,r5 + fca4: 0009883a mov r4,zero + fca8: 15000215 stw r20,8(r2) + fcac: 28c00115 stw r3,4(r5) + fcb0: 2005883a mov r2,r4 + fcb4: dfc00517 ldw ra,20(sp) + fcb8: dd000417 ldw r20,16(sp) + fcbc: dcc00317 ldw r19,12(sp) + fcc0: dc800217 ldw r18,8(sp) + fcc4: dc400117 ldw r17,4(sp) + fcc8: dc000017 ldw r16,0(sp) + fccc: dec00604 addi sp,sp,24 + fcd0: f800283a ret + fcd4: 29802204 addi r6,r5,136 + fcd8: 00800044 movi r2,1 + fcdc: 110e983a sll r7,r2,r4 + fce0: 30c04017 ldw r3,256(r6) + fce4: 2105883a add r2,r4,r4 + fce8: 1085883a add r2,r2,r2 + fcec: 1185883a add r2,r2,r6 + fcf0: 19c6b03a or r3,r3,r7 + fcf4: 14802015 stw r18,128(r2) + fcf8: 14c00015 stw r19,0(r2) + fcfc: 00800084 movi r2,2 + fd00: 30c04015 stw r3,256(r6) + fd04: 88bfe31e bne r17,r2,fc94 <__register_exitproc+0x50> + fd08: 30804117 ldw r2,260(r6) + fd0c: 11c4b03a or r2,r2,r7 + fd10: 30804115 stw r2,260(r6) + fd14: 003fdf06 br fc94 <__register_exitproc+0x50> + fd18: 00800074 movhi r2,1 + fd1c: 10911104 addi r2,r2,17476 + fd20: 100b883a mov r5,r2 + fd24: 80805215 stw r2,328(r16) + fd28: 003fd606 br fc84 <__register_exitproc+0x40> + fd2c: 00800034 movhi r2,0 + fd30: 10800004 addi r2,r2,0 + fd34: 1000021e bne r2,zero,fd40 <__register_exitproc+0xfc> + fd38: 013fffc4 movi r4,-1 + fd3c: 003fdc06 br fcb0 <__register_exitproc+0x6c> + fd40: 01006404 movi r4,400 + fd44: 103ee83a callr r2 + fd48: 1007883a mov r3,r2 + fd4c: 103ffa26 beq r2,zero,fd38 <__register_exitproc+0xf4> + fd50: 80805217 ldw r2,328(r16) + fd54: 180b883a mov r5,r3 + fd58: 18000115 stw zero,4(r3) + fd5c: 18800015 stw r2,0(r3) + fd60: 80c05215 stw r3,328(r16) + fd64: 18006215 stw zero,392(r3) + fd68: 18006315 stw zero,396(r3) + fd6c: 0009883a mov r4,zero + fd70: 883fc826 beq r17,zero,fc94 <__register_exitproc+0x50> + fd74: 003fd706 br fcd4 <__register_exitproc+0x90> + +0000fd78 : + fd78: f800283a ret + +0000fd7c <__call_exitprocs>: + fd7c: 00800074 movhi r2,1 + fd80: 10887f04 addi r2,r2,8700 + fd84: 10800017 ldw r2,0(r2) + fd88: defff304 addi sp,sp,-52 + fd8c: df000b15 stw fp,44(sp) + fd90: d8800115 stw r2,4(sp) + fd94: 00800034 movhi r2,0 + fd98: 10800004 addi r2,r2,0 + fd9c: 1005003a cmpeq r2,r2,zero + fda0: d8800215 stw r2,8(sp) + fda4: d8800117 ldw r2,4(sp) + fda8: dd400815 stw r21,32(sp) + fdac: dd000715 stw r20,28(sp) + fdb0: 10805204 addi r2,r2,328 + fdb4: dfc00c15 stw ra,48(sp) + fdb8: ddc00a15 stw r23,40(sp) + fdbc: dd800915 stw r22,36(sp) + fdc0: dcc00615 stw r19,24(sp) + fdc4: dc800515 stw r18,20(sp) + fdc8: dc400415 stw r17,16(sp) + fdcc: dc000315 stw r16,12(sp) + fdd0: 282b883a mov r21,r5 + fdd4: 2039883a mov fp,r4 + fdd8: d8800015 stw r2,0(sp) + fddc: 2829003a cmpeq r20,r5,zero + fde0: d8800117 ldw r2,4(sp) + fde4: 14405217 ldw r17,328(r2) + fde8: 88001026 beq r17,zero,fe2c <__call_exitprocs+0xb0> + fdec: ddc00017 ldw r23,0(sp) + fdf0: 88800117 ldw r2,4(r17) + fdf4: 8c802204 addi r18,r17,136 + fdf8: 143fffc4 addi r16,r2,-1 + fdfc: 80000916 blt r16,zero,fe24 <__call_exitprocs+0xa8> + fe00: 05bfffc4 movi r22,-1 + fe04: a000151e bne r20,zero,fe5c <__call_exitprocs+0xe0> + fe08: 8409883a add r4,r16,r16 + fe0c: 2105883a add r2,r4,r4 + fe10: 1485883a add r2,r2,r18 + fe14: 10c02017 ldw r3,128(r2) + fe18: a8c01126 beq r21,r3,fe60 <__call_exitprocs+0xe4> + fe1c: 843fffc4 addi r16,r16,-1 + fe20: 85bff81e bne r16,r22,fe04 <__call_exitprocs+0x88> + fe24: d8800217 ldw r2,8(sp) + fe28: 10003126 beq r2,zero,fef0 <__call_exitprocs+0x174> + fe2c: dfc00c17 ldw ra,48(sp) + fe30: df000b17 ldw fp,44(sp) + fe34: ddc00a17 ldw r23,40(sp) + fe38: dd800917 ldw r22,36(sp) + fe3c: dd400817 ldw r21,32(sp) + fe40: dd000717 ldw r20,28(sp) + fe44: dcc00617 ldw r19,24(sp) + fe48: dc800517 ldw r18,20(sp) + fe4c: dc400417 ldw r17,16(sp) + fe50: dc000317 ldw r16,12(sp) + fe54: dec00d04 addi sp,sp,52 + fe58: f800283a ret + fe5c: 8409883a add r4,r16,r16 + fe60: 88c00117 ldw r3,4(r17) + fe64: 2105883a add r2,r4,r4 + fe68: 1445883a add r2,r2,r17 + fe6c: 18ffffc4 addi r3,r3,-1 + fe70: 11800217 ldw r6,8(r2) + fe74: 1c001526 beq r3,r16,fecc <__call_exitprocs+0x150> + fe78: 10000215 stw zero,8(r2) + fe7c: 303fe726 beq r6,zero,fe1c <__call_exitprocs+0xa0> + fe80: 00c00044 movi r3,1 + fe84: 1c06983a sll r3,r3,r16 + fe88: 90804017 ldw r2,256(r18) + fe8c: 8cc00117 ldw r19,4(r17) + fe90: 1884703a and r2,r3,r2 + fe94: 10001426 beq r2,zero,fee8 <__call_exitprocs+0x16c> + fe98: 90804117 ldw r2,260(r18) + fe9c: 1884703a and r2,r3,r2 + fea0: 10000c1e bne r2,zero,fed4 <__call_exitprocs+0x158> + fea4: 2105883a add r2,r4,r4 + fea8: 1485883a add r2,r2,r18 + feac: 11400017 ldw r5,0(r2) + feb0: e009883a mov r4,fp + feb4: 303ee83a callr r6 + feb8: 88800117 ldw r2,4(r17) + febc: 98bfc81e bne r19,r2,fde0 <__call_exitprocs+0x64> + fec0: b8800017 ldw r2,0(r23) + fec4: 147fd526 beq r2,r17,fe1c <__call_exitprocs+0xa0> + fec8: 003fc506 br fde0 <__call_exitprocs+0x64> + fecc: 8c000115 stw r16,4(r17) + fed0: 003fea06 br fe7c <__call_exitprocs+0x100> + fed4: 2105883a add r2,r4,r4 + fed8: 1485883a add r2,r2,r18 + fedc: 11000017 ldw r4,0(r2) + fee0: 303ee83a callr r6 + fee4: 003ff406 br feb8 <__call_exitprocs+0x13c> + fee8: 303ee83a callr r6 + feec: 003ff206 br feb8 <__call_exitprocs+0x13c> + fef0: 88800117 ldw r2,4(r17) + fef4: 1000081e bne r2,zero,ff18 <__call_exitprocs+0x19c> + fef8: 89000017 ldw r4,0(r17) + fefc: 20000726 beq r4,zero,ff1c <__call_exitprocs+0x1a0> + ff00: b9000015 stw r4,0(r23) + ff04: 8809883a mov r4,r17 + ff08: 00000000 call 0 <__alt_mem_onchip_memory> + ff0c: bc400017 ldw r17,0(r23) + ff10: 883fb71e bne r17,zero,fdf0 <__call_exitprocs+0x74> + ff14: 003fc506 br fe2c <__call_exitprocs+0xb0> + ff18: 89000017 ldw r4,0(r17) + ff1c: 882f883a mov r23,r17 + ff20: 2023883a mov r17,r4 + ff24: 883fb21e bne r17,zero,fdf0 <__call_exitprocs+0x74> + ff28: 003fc006 br fe2c <__call_exitprocs+0xb0> + +0000ff2c : + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + ff2c: defffd04 addi sp,sp,-12 + ff30: df000215 stw fp,8(sp) + ff34: df000204 addi fp,sp,8 + ff38: e13fff15 stw r4,-4(fp) + int r2 = exit_code; + ff3c: e0bfff17 ldw r2,-4(fp) + ff40: e0bffe15 stw r2,-8(fp) + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + ff44: e0bffe17 ldw r2,-8(fp) + ff48: 1005003a cmpeq r2,r2,zero + ff4c: 1000021e bne r2,zero,ff58 + ALT_SIM_FAIL(); + ff50: 002af070 cmpltui zero,zero,43969 + ff54: 00000106 br ff5c + } else { + ALT_SIM_PASS(); + ff58: 002af0b0 cmpltui zero,zero,43970 + } +#endif /* DEBUG_STUB */ +} + ff5c: e037883a mov sp,fp + ff60: df000017 ldw fp,0(sp) + ff64: dec00104 addi sp,sp,4 + ff68: f800283a ret + +0000ff6c <_exit>: + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + ff6c: defffd04 addi sp,sp,-12 + ff70: dfc00215 stw ra,8(sp) + ff74: df000115 stw fp,4(sp) + ff78: df000104 addi fp,sp,4 + ff7c: e13fff15 stw r4,-4(fp) + ALT_OS_STOP(); + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + ff80: e13fff17 ldw r4,-4(fp) + ff84: 000ff2c0 call ff2c + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); + ff88: 003fff06 br ff88 <_exit+0x1c> + ff8c: 0000fd78 rdprs zero,zero,1013 diff --git a/software/DE2_115_ASM/LCD.c b/software/DE2_115_ASM/LCD.c new file mode 100644 index 0000000..10ff2ea --- /dev/null +++ b/software/DE2_115_ASM/LCD.c @@ -0,0 +1,50 @@ +#include +#include +#include +#include "system.h" +#include "LCD.h" +//------------------------------------------------------------------------- +void LCD_Init() +{ + lcd_write_cmd(LCD_16207_0_BASE,0x38); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x0C); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x01); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x06); + usleep(2000); + lcd_write_cmd(LCD_16207_0_BASE,0x80); + usleep(2000); +} +//------------------------------------------------------------------------- +void LCD_Show_Text(const char* Text) +{ + int i; + for(i=0;i /c/dir). This will ensture +# paths are readable by GNU Make. +# +# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no +# adjustment is necessary +# +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # COMSPEC + +ifdef COMSPEC # if Windows OS + +ifeq ($(MAKE_VERSION),3.81) +# +# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows +# +# Example Usage: +# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb +# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb +# + +# +# adjust-path +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not contain the string ":/", then return input arg +# - using sed, convert mixed path [c:/...] into mingw path [/c/...] +define adjust-path +$(strip \ +$(if $1,\ +$(if $(findstring :/,$(subst \,/,$1)),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\ +$(subst \,/,$1)))) +endef + +# +# adjust-path-mixed +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not begin with a forward slash '/' char, then +# return input arg +# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] +# into a mixed path [c:/...] +define adjust-path-mixed +$(strip \ +$(if $1,\ +$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ +$(subst \,/,$1),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,')))) +endef + +else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) +# +# adjust-path for Cygwin Gnu Make +# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb +# +adjust-path = $(if $1,$(shell cygpath -u "$1"),) +adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) +endif + +else # !COMSPEC + +adjust-path = $1 +adjust-path-mixed = $1 + +endif # COMSPEC + + +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv +# GENERATED SETTINGS START v +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv + +#START GENERATED +ACTIVE_BUILD_CONFIG := default +BUILD_CONFIGS := default + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: APP_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Define path to the application ELF. +# It may be used by the makefile fragments so is defined before including them. +# +ELF := DE2_115_ASM.elf + +# Paths to C, C++, and assembly source files. +C_SRCS += LCD.c +C_SRCS += hello_world_small.c +C_SRCS += hex_encoder.c +C_SRCS += hex_out.c +C_SRCS += input_int.c +C_SRCS += inst_decoder.c +C_SRCS += lcd_out.c +C_SRCS += sys_debug.c +C_SRCS += sys_except.c +C_SRCS += sys_memory.c +C_SRCS += sys_prog.c +C_SRCS += sys_register.c +CXX_SRCS := +ASM_SRCS := + + +# Path to root of object file tree. +OBJ_ROOT_DIR := obj + +# Options to control objdump. +CREATE_OBJDUMP := 1 +OBJDUMP_INCLUDE_SOURCE := 1 +OBJDUMP_FULL_CONTENTS := 0 + +# Options to enable/disable optional files. +CREATE_ELF_DERIVED_FILES := 0 +CREATE_LINKER_MAP := 1 + +# Common arguments for ALT_CFLAGSs +APP_CFLAGS_DEFINED_SYMBOLS := +APP_CFLAGS_UNDEFINED_SYMBOLS := +APP_CFLAGS_OPTIMIZATION := -O0 +APP_CFLAGS_DEBUG_LEVEL := -g +APP_CFLAGS_WARNINGS := -Wall +APP_CFLAGS_USER_FLAGS := + +APP_ASFLAGS_USER := +APP_LDFLAGS_USER := + +# Linker options that have default values assigned later if not +# assigned here. +LINKER_SCRIPT := +CRT0 := +SYS_LIB := + +# Define path to the root of the BSP. +BSP_ROOT_DIR := ../DE2_115_ASM_bsp/ + +# List of application specific include directories, library directories and library names +APP_INCLUDE_DIRS := +APP_LIBRARY_DIRS := +APP_LIBRARY_NAMES := + +# Pre- and post- processor settings. +BUILD_PRE_PROCESS := +BUILD_POST_PROCESS := + +QUARTUS_PROJECT_DIR := ../../ + + +#END GENERATED + +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +# GENERATED SETTINGS END ^ +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +#------------------------------------------------------------------------------ + +# Define the variable used to echo output if not already defined. +ifeq ($(ECHO),) +ECHO := echo +endif + +# Put "all" rule before included makefile fragments because they may +# define rules and we don't want one of those to become the default rule. +.PHONY : all + +all: + @$(ECHO) [$(APP_NAME) build complete] + +all : build_pre_process libs app build_post_process + + +#------------------------------------------------------------------------------ +# VARIABLES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ + +# Define object file directory per build configuration +CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) + +ifeq ($(BSP_ROOT_DIR),) +$(error Edit Makefile and provide a value for BSP_ROOT_DIR) +endif + +ifeq ($(wildcard $(BSP_ROOT_DIR)),) +$(error BSP directory does not exist: $(BSP_ROOT_DIR)) +endif + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) + +# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before +# including each makefile fragment so that it knows the path to itself. +BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk +ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) +include $(BSP_INCLUDE_FILE) +# C2H will need this to touch the BSP public.mk and avoid the sopc file +# out-of-date error during a BSP make +ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk + + +ifneq ($(WARNING.SMALL_STACK_SIZE),) +# This WARNING is here to protect you from unknowingly using a very small stack +# If the warning is set, increase your stack size or enable the BSP small stack +# setting to eliminate the warning +$(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) +endif + + +# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF +# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. +ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) +ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) +endif + +# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to +# download_elf target +ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) +GMON_OUT_FILENAME := gmon.out +WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) +endif + +# Name of ELF application. +APP_NAME := $(basename $(ELF)) + +# Set to defaults if variables not already defined in settings. +ifeq ($(LINKER_SCRIPT),) +LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) +endif +ifeq ($(CRT0),) +CRT0 := $(BSP_CRT0) +endif +ifeq ($(SYS_LIB),) +SYS_LIB := $(BSP_SYS_LIB) +endif + +OBJDUMP_NAME := $(APP_NAME).objdump +OBJDUMP_FLAGS := --disassemble --syms --all-header +ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) +OBJDUMP_FLAGS += --source +endif +ifeq ($(OBJDUMP_FULL_CONTENTS),1) +OBJDUMP_FLAGS += --full-contents +endif + +# Create list of linker dependencies (*.a files). +APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) + +# Take lists and add required prefixes. +APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +ASM_INC_PREFIX := -Wa,-I +APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) +APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# +# Avoid Nios II GCC 3.X options. +# + +# Detect if small newlib C library is requested. +# If yes, remove the -msmallc option because it is +# now handled by other means. +ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) + ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) + ALT_C_LIBRARY := smallc +else + ALT_C_LIBRARY := c +endif + +# Put each BSP dependent library in a group to avoid circular dependencies. +APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# +# Use Nios II GCC 3.X options. +# +APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. +APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ + $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(APP_CFLAGS_OPTIMIZATION) \ + $(APP_CFLAGS_DEBUG_LEVEL) \ + $(APP_CFLAGS_WARNINGS) \ + $(APP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Arguments only for the C++ compiler. +APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) + +# Arguments only for the C preprocessor. +# Prefix each include directory with -I. +APP_CPPFLAGS := $(APP_INC_DIRS) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Arguments only for the assembler. +APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ + $(ALT_ASFLAGS) \ + $(APP_ASFLAGS_USER) \ + $(ASFLAGS) + +# Arguments only for the linker. +APP_LDFLAGS := $(APP_LDFLAGS_USER) + +ifneq ($(LINKER_SCRIPT),) +APP_LDFLAGS += -T'$(LINKER_SCRIPT)' +endif + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# Avoid Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += $(CRT0) +endif + +# The equivalent of the -msys-lib option is provided +# by the GROUP() command in the linker script. +# Note this means the SYS_LIB variable is now ignored. + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# Use Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += -msys-crt0='$(CRT0)' +endif +ifneq ($(SYS_LIB),) +APP_LDFLAGS += -msys-lib=$(SYS_LIB) +endif + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +APP_LDFLAGS += \ + $(APP_LIB_DIRS) \ + $(ALT_LDFLAGS) \ + $(LDFLAGS) + +LINKER_MAP_NAME := $(APP_NAME).map +ifeq ($(CREATE_LINKER_MAP), 1) +APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) +endif + +# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the +# mem_init_install target of the mem_init.mk (located in the associated BSP) +# to know how to copy memory initialization files (e.g. .dat, .hex) into +# directories required for Quartus compilation or RTL simulation. + +# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory +# initialization files into your Quartus project directory. This is required +# to provide the initial memory contents of FPGA memories that can be +# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used +# for VHDL simulation of on-chip memories. + +# Defining SOPC_NAME causes the mem_init_install target to copy memory +# initialization files into your RTL simulation directory. This is required +# to provide the initial memory contents of all memories that can be +# initialized by RTL simulation. This variable should be set to the same name +# as your SOPC Builder system name. For example, if you have a system called +# "foo.sopc", this variable should be set to "foo". + +# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. +ifeq ($(SOPC_NAME),) +ifneq ($(QUARTUS_PROJECT_DIR),) +SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) +endif +endif + +# Defining JDI_FILE is required to specify the JTAG Debug Information File +# path. This file is generated by Quartus, and is needed along with the +# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU +# systems. For multi-CPU systems, the processor instance ID is used to select +# from multiple CPU's during ELF download. + +# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during +# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then +# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be +# multiple .sopcinfo files in a Quartus project. +ifeq ($(JDI_FILE),) +ifneq ($(QUARTUS_PROJECT_DIR),) +JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) +endif +endif + +# Path to root runtime directory used for hdl simulation +RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime + + + +#------------------------------------------------------------------------------ +# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ +# mem_init.mk is a generated makefile fragment. This file defines all targets +# used to generate HDL initialization simulation files and pre-initialized +# onchip memory files. +MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk +include $(MEM_INIT_FILE) + +# Create list of object files to be built using the list of source files. +# The source file hierarchy is preserved in the object tree. +# The supported file extensions are: +# +# .c - for C files +# .cxx .cc .cpp - for C++ files +# .S .s - for assembler files +# +# Handle source files specified by --src-dir & --src-rdir differently, to +# save some processing time in calling the adjust-path macro. + +OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) +OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) +OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) +OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) +OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) +OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) + +OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ + $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) + +SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) +SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) +SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) + +SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ + $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ + $(SDIR_OBJ_LIST_SS)) + +# Relative-pathed objects that being with "../" are handled differently. +# +# Regular objects are created as +# $(CONFIG_OBJ_DIR)//.o +# where the path structure is maintained under the obj directory. This +# applies for both absolute and relative paths; in the absolute path +# case this means the entire source path will be recreated under the obj +# directory. This is done to allow two source files with the same name +# to be included as part of the project. +# +# Note: On Cygwin, the path recreated under the obj directory will be +# the cygpath -u output path. +# +# Relative-path objects that begin with "../" cause problems under this +# scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object +# files anywhere in the system, creating clutter and polluting the source tree. +# As such, their paths are flattened - the object file created will be +# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with +# "../" in the beginning cannot have the same name in the project. VPATH +# will be set for these sources to allow make to relocate the source file +# via %.o rules. +# +# The following lines separate the object list into the flatten and regular +# lists, and then handles them as appropriate. + +FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) +FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) + +REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) +REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) + +FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) +FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) + +REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) + +VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) + +APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_C) \ + $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) + +APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CPP) \ + $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) + +APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CXX) \ + $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) + +APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CC) \ + $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) + +APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_S) \ + $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) + +APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_SS) \ + $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) + +APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ + $(APP_OBJS_S) $(APP_OBJS_SS) \ + $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) + +# Add any extra user-provided object files. +APP_OBJS += $(OBJS) + +# Create list of dependancy files for each object file. +APP_DEPS := $(APP_OBJS:.o=.d) + +# Patch the Elf file with system specific information + +# Patch the Elf with the name of the sopc system +ifneq ($(SOPC_NAME),) +ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) +endif + +# Patch the Elf with the absolute path to the Quartus Project Directory +ifneq ($(QUARTUS_PROJECT_DIR),) +ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) +ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" +endif + +# Patch the Elf and download args with the JDI_FILE if specified +ifneq ($(wildcard $(JDI_FILE)),) +ELF_PATCH_FLAG += --jdi $(JDI_FILE) +DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) +endif + +# Patch the Elf with the SOPCINFO_FILE if specified +ifneq ($(wildcard $(SOPCINFO_FILE)),) +ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) +endif + +# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. +# This is not needed if you only have one cable. +ifneq ($(DOWNLOAD_CABLE),) +DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' +endif + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +# +# Set tool default variables if not already defined. +# If these are defined, they would typically be defined in an +# included makefile fragment. +# +ifeq ($(DEFAULT_CROSS_COMPILE),) +DEFAULT_CROSS_COMPILE := nios2-elf- +endif + +ifeq ($(DEFAULT_STACK_REPORT),) +DEFAULT_STACKREPORT := nios2-stackreport +endif + +ifeq ($(DEFAULT_DOWNLOAD),) +DEFAULT_DOWNLOAD := nios2-download +endif + +ifeq ($(DEFAULT_FLASHPROG),) +DEFAULT_FLASHPROG := nios2-flash-programmer +endif + +ifeq ($(DEFAULT_ELFPATCH),) +DEFAULT_ELFPATCH := nios2-elf-insert +endif + +ifeq ($(DEFAULT_RM),) +DEFAULT_RM := rm -f +endif + +ifeq ($(DEFAULT_CP),) +DEFAULT_CP := cp -f +endif + +ifeq ($(DEFAULT_MKDIR),) +DEFAULT_MKDIR := mkdir -p +endif + +# +# Set tool variables to defaults if not already defined. +# If these are defined, they would typically be defined by a +# setting in the generated portion of this makefile. +# +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) +endif + +ifeq ($(origin CC),default) +CC := $(CROSS_COMPILE)gcc -xc +endif + +ifeq ($(origin CXX),default) +CXX := $(CROSS_COMPILE)gcc -xc++ +endif + +ifeq ($(origin AS),default) +AS := $(CROSS_COMPILE)gcc +endif + +ifeq ($(origin AR),default) +AR := $(CROSS_COMPILE)ar +endif + +ifeq ($(origin LD),default) +LD := $(CROSS_COMPILE)g++ +endif + +ifeq ($(origin NM),default) +NM := $(CROSS_COMPILE)nm +endif + +ifeq ($(origin RM),default) +RM := $(DEFAULT_RM) +endif + +ifeq ($(origin CP),default) +CP := $(DEFAULT_CP) +endif + +ifeq ($(OBJDUMP),) +OBJDUMP := $(CROSS_COMPILE)objdump +endif + +ifeq ($(OBJCOPY),) +OBJCOPY := $(CROSS_COMPILE)objcopy +endif + +ifeq ($(STACKREPORT),) +ifeq ($(CROSS_COMPILE),nios2-elf-) +STACKREPORT := $(DEFAULT_STACKREPORT) +else +DISABLE_STACKREPORT := 1 +endif +endif + +ifeq ($(DOWNLOAD),) +DOWNLOAD := $(DEFAULT_DOWNLOAD) +endif + +ifeq ($(FLASHPROG),) +FLASHPROG := $(DEFAULT_FLASHPROG) +endif + +ifeq ($(ELFPATCH),) +ELFPATCH := $(DEFAULT_ELFPATCH) +endif + +ifeq ($(MKDIR),) +MKDIR := $(DEFAULT_MKDIR) +endif + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ + +define compile.c +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< +$(CC_POST_PROCESS) +endef + +define compile.cpp +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< +$(CXX_POST_PROCESS) +endef + +# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS +ifeq ($(AS),$(patsubst %as,%,$(AS))) +COMMA := , +APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) +endif + +define compile.s +@$(ECHO) Info: Assembling $< to $@ +@$(MKDIR) $(@D) +$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< +$(AS_POST_PROCESS) +endef + +ifeq ($(MAKE_VERSION),3.81) +.SECONDEXPANSION: + +$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) + $(compile.c) + +$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) + $(compile.cpp) + +$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) + $(compile.cpp) + +$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) + $(compile.cpp) + +$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) + $(compile.s) + +$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) + $(compile.s) + +endif # MAKE_VERSION != 3.81 + +$(CONFIG_OBJ_DIR)/%.o: %.c + $(compile.c) + +$(CONFIG_OBJ_DIR)/%.o: %.cpp + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cc + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cxx + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.S + $(compile.s) + +$(CONFIG_OBJ_DIR)/%.o: %.s + $(compile.s) + + +#------------------------------------------------------------------------------ +# PATTERN RULES TO INTERMEDIATE FILES +#------------------------------------------------------------------------------ + +$(CONFIG_OBJ_DIR)/%.s: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + + +#------------------------------------------------------------------------------ +# TARGET RULES +#------------------------------------------------------------------------------ + +.PHONY : help +help : + @$(ECHO) "Summary of Makefile targets" + @$(ECHO) " Build targets:" + @$(ECHO) " all (default) - Application and all libraries (including BSP)" + @$(ECHO) " bsp - Just the BSP" + @$(ECHO) " libs - All libraries (including BSP)" + @$(ECHO) " flash - All flash files" + @$(ECHO) " mem_init_generate - All memory initialization files" +ifeq ($(QSYS),1) + @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" + @$(ECHO) " --> Use the mem_init_generate target and then" + @$(ECHO) " add the generated meminit.qip file to your" + @$(ECHO) " Quartus II Project." +else # if QSYS != 1 + @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" +endif # QSYS == 1 + @$(ECHO) + @$(ECHO) " Clean targets:" + @$(ECHO) " clean_all - Application and all libraries (including BSP)" + @$(ECHO) " clean - Just the application" + @$(ECHO) " clean_bsp - Just the BSP" + @$(ECHO) " clean_libs - All libraries (including BSP)" + @$(ECHO) + @$(ECHO) " Run targets:" + @$(ECHO) " download-elf - Download and run your elf executable" + @$(ECHO) " program-flash - Program flash contents to the board" + +# Handy rule to skip making libraries and just make application. +.PHONY : app +app : $(ELF) + +ifeq ($(CREATE_OBJDUMP), 1) +app : $(OBJDUMP_NAME) +endif + +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +app : elf_derived_files +endif + +.PHONY: elf_derived_files +elf_derived_files: default_mem_init + +# Handy rule for making just the BSP. +.PHONY : bsp +bsp : + @$(ECHO) Info: Building $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) + + +# Make sure all makeable libraries (including the BSP) are up-to-date. +LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : libs +libs : $(LIB_TARGETS) + +ifneq ($(strip $(LIB_TARGETS)),) +$(LIB_TARGETS): %-recurs-make-lib: + @$(ECHO) Info: Building $* + $(MAKE) --no-print-directory -C $* +endif + +ifneq ($(strip $(APP_LDDEPS)),) +$(APP_LDDEPS): libs + @true +endif + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) + +$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) + + +# Clean just the application. +.PHONY : clean +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +clean : clean_elf_derived_files +endif + +clean : + @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) + @$(ECHO) [$(APP_NAME) clean complete] + +# Clean just the BSP. +.PHONY : clean_bsp +clean_bsp : + @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean + +# Clean all makeable libraries including the BSP. +LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : clean_libs +clean_libs : $(LIB_CLEAN_TARGETS) + +ifneq ($(strip $(LIB_CLEAN_TARGETS)),) +$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: + @$(ECHO) Info: Cleaning $* + $(MAKE) --no-print-directory -C $* clean +endif + +.PHONY: clean_elf_derived_files +clean_elf_derived_files: mem_init_clean + +# Clean application and all makeable libraries including the BSP. +.PHONY : clean_all +clean_all : clean mem_init_clean clean_libs + +# Include the dependency files unless the make goal is performing a clean +# of the application. +ifneq ($(firstword $(MAKECMDGOALS)),clean) +ifneq ($(firstword $(MAKECMDGOALS)),clean_all) +-include $(APP_DEPS) +endif +endif + +.PHONY : download-elf +download-elf : $(ELF) + @if [ "$(DOWNLOAD)" = "none" ]; \ + then \ + $(ECHO) Downloading $(ELF) not supported; \ + else \ + $(ECHO) Info: Downloading $(ELF); \ + $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ + fi + +# Delete the target of a rule if it has changed and its commands exit +# with a nonzero exit status. +.DELETE_ON_ERROR: + +# Rules for flash programming commands +PROGRAM_FLASH_SUFFIX := -program +PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) + +.PHONY : program-flash +program-flash : $(PROGRAM_FLASH_TARGET) + +.PHONY : $(PROGRAM_FLASH_TARGET) +$(PROGRAM_FLASH_TARGET) : flash + @if [ "$(FLASHPROG)" = "none" ]; \ + then \ + $(ECHO) Programming flash not supported; \ + else \ + $(ECHO) Info: Programming $(basename $@).flash; \ + if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ + then \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + else \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + fi \ + fi + + +# Rules for simulating with an HDL Simulator [QSYS only] +ifeq ($(QSYS),1) +IP_MAKE_SIMSCRIPT := ip-make-simscript + +ifeq ($(VSIM),) +VSIM_EXE := "$(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim" +ifeq ($(ENABLE_VSIM_GUI),1) +VSIM := $(VSIM_EXE) -gui +else +VSIM := $(VSIM_EXE) -c +endif # ENABLE_VSIM_GUI == 1 +endif # VSIM not set + +ifeq ($(SPD),) +ifneq ($(ABS_QUARTUS_PROJECT_DIR),) +ifneq ($(SOPC_NAME),) +SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd +endif # SOPC_NAME set +endif # ABS_QUARTUS_PROJECT_DIR set +endif # SPD == empty string + +ifeq ($(MSIM_SCRIPT),) +SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim +MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl +endif # MSIM_SCRIPT == empty string + +ifeq ($(MAKE_VERSION),3.81) +ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) +else +ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) +endif + +$(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) +ifeq ($(SPD),) + $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) +endif + @$(MKDIR) $(SIM_SCRIPT_DIR) + $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) + +VSIM_COMMAND = \ + cd $(dir $(MSIM_SCRIPT)) && \ + $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" + +.PHONY: sim +sim: $(MSIM_SCRIPT) mem_init_generate +ifeq ($(MSIM_SCRIPT),) + $(error MSIM_SCRIPT not set) +endif + $(VSIM_COMMAND) + +endif # QSYS == 1 + + +#------------------------------------------------------------------------------ +# ELF TARGET RULE +#------------------------------------------------------------------------------ +# Rule for constructing the executable elf file. +$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) + @$(ECHO) Info: Linking $@ + $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) +ifneq ($(DISABLE_ELFPATCH),1) + $(ELFPATCH) $@ $(ELF_PATCH_FLAG) +endif +ifneq ($(DISABLE_STACKREPORT),1) + @bash -c "$(STACKREPORT) $@" +endif + +$(OBJDUMP_NAME) : $(ELF) + @$(ECHO) Info: Creating $@ + $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ + +# Rule for printing the name of the elf file +.PHONY: print-elf-name +print-elf-name: + @$(ECHO) $(ELF) + + diff --git a/software/DE2_115_ASM/create-this-app b/software/DE2_115_ASM/create-this-app new file mode 100644 index 0000000..f02aa29 --- /dev/null +++ b/software/DE2_115_ASM/create-this-app @@ -0,0 +1,114 @@ +#!/bin/bash +# +# This script creates the hello_world application in this directory. + + +BSP_DIR=../DE2_115_ASM_bsp +QUARTUS_PROJECT_DIR=../../ +NIOS2_APP_GEN_ARGS="--elf-name DE2_115_ASM.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_world.c" + + +# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. +# This variable is required for the command line tools to execute correctly. +if [ -z "${SOPC_KIT_NIOS2}" ] +then + echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! + exit 1 +fi + + +# Also make sure that the APP has not been created already. Check for +# existence of Makefile in the app directory +if [ -f ./Makefile ] +then + echo Application has already been created! Delete Makefile if you want to create a new application makefile + exit 1 +fi + + +# We are selecting hal_default bsp because it supports this application. +# Check to see if the hal_default has already been generated by checking for +# existence of the public.mk file. If not, we need to run +# create-this-bsp file to generate the bsp. +if [ ! -f ${BSP_DIR}/public.mk ]; then + # Since BSP doesn't exist, create the BSP + # Pass any command line arguments passed to this script to the BSP. + pushd ${BSP_DIR} >> /dev/null + ./create-this-bsp "$@" || { + echo "create-this-bsp failed" + exit 1 + } + popd >> /dev/null +fi + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + esac + shift +done + + +# Now we also need to go copy the sources for this application to the +# local directory. +find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { + echo "failed during copying example source files" + exit 1 +} + +find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { + echo "failed copying readme file" +} + +if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" ] +then + cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" . || { + echo "failed during copying project support files" + exit 1 + } +fi + +chmod -R +w . || { + echo "failed during changing file permissions" + exit 1 +} + +cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" + +echo "create-this-app: Running \"${cmd}\"" +$cmd || { + echo "nios2-app-generate-makefile failed" + exit 1 +} + +if [ -z "$SKIP_MAKE" ]; then + cmd="make" + + echo "create-this-app: Running \"$cmd\"" + $cmd || { + echo "make failed" + exit 1 + } + + echo + echo "To download and run the application:" + echo " 1. Make sure the board is connected to the system." + echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." + echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." + echo " 4. Run 'make download-elf' from the application directory." + echo + echo "To debug the application:" + echo " Import the project into Nios II Software Build Tools for Eclipse." + echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." + echo + echo -e "" +fi + + +exit 0 diff --git a/software/DE2_115_ASM/hello_world_small.c b/software/DE2_115_ASM/hello_world_small.c new file mode 100644 index 0000000..5d06d9b --- /dev/null +++ b/software/DE2_115_ASM/hello_world_small.c @@ -0,0 +1,214 @@ +#include "sys/alt_stdio.h" +#include +#include "system.h" +#include "hex_out.h" +#include "lcd_out.h" +#include "sys_register.h" +#include "sys_memory.h" +#include "input_int.h" +#include "sys_debug.h" +#include "sys_prog.h" + +#define ledrs (volatile int *) LEDRS_BASE + +static void init() { + // lcd + lcd_init(); + lcd_print("Starting now..."); + + registers_init(); + memory_init(); + // hex + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + print_block("he", 2, HEX6_7); + print_block("lo", 2, HEX4_5); + print_block("you1", 4, HEX0_3); + delay10ms(200); + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + + lcd_caret_reset2(); + lcd_print("Ok!"); +} + +char stack[5]; + +void store_value(){ + unsigned int memi = global_registers[Ssw_memi]; + memory_store(memi, Ssw_data); + + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "%02x", (unsigned char)memi); + print_block(buf, 2, HEX6_7); + print_block("--", 2, HEX4_5); + sprintf(buf, "%04d", global_registers[Ssw_data]); + print_block(buf, 4, HEX0_3); + + display_mem((unsigned char)memi, global_registers[Ssw_data]); + } +} +void store_inst(){ + char inst; + char mem_index; + char reg_index; + unsigned int stored_pc; + struct InstRec inst_rec; + + // �K�v�ȏ��̎擾 + inst = global_registers[Ssw_inst]; + mem_index = global_registers[Ssw_memi]; + reg_index = global_registers[Ssw_regi]; + inst_rec.inst = (unsigned int)inst; + inst_rec.memi = (unsigned int)mem_index; + inst_rec.regi = (unsigned int)reg_index; + + // �X�g�A���� + stored_pc = get_pc(); + inst_memory_store(get_pc(), inst_rec); + inc_pc(); + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "%04d", inst_rec.inst); + print_block(buf, 4, HEX0_3); + sprintf(buf, "%02x", get_pc()); + print_block(buf, 2, HEX4_5); + + display_inst(inst_rec, stored_pc); + } +} + +void print_change_memory(unsigned int current_memory) { + char buf[17]; + sprintf(buf, "Current page:%2d", current_memory); + lcd_caret_reset(); + lcd_print("Change program"); + lcd_caret_reset2(); + lcd_print(buf); + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); +} + +static void reset_mem_cancel() { + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again -> NG"); +} +static char reset_mem(char confirmed) { + if (confirmed == 0) { + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again"); + // �m�F�v�� + return 1; + } else { + int i; + for (i = 0; i < MEM_SIZE; i++){ + memory_store(i,Szero); + } + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again -> OK"); + + // PC���Z�b�g���� + return 0; + } +} +static void reset_pc_cancel() { + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again -> NG"); +} +static char reset_pc(char confirmed) { + if (confirmed == 0) { + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again"); + // �m�F�v�� + return 1; + } else { + set_pc(0); + + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again -> OK"); + + // PC���Z�b�g���� + return 0; + } +} + + +int main() +{ + init(); + + enum RunMode fRun = RUN_STOP; + char reset_pc_confirmed = 0; + char reset_mem_confirmed = 0; + + while(1) { + // interrupt + in_int(); + + // event + // CANCEL + if (global_registers[Ssw_rw] == 0 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_VALSTR))) { + if (reset_mem_confirmed == 1) { + reset_mem_confirmed = 0; //�m�F�L�����Z�� + reset_mem_cancel(); + } + } + if (global_registers[Ssw_rw] == 0 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_INSSTR))) { + if (reset_pc_confirmed == 1) { + reset_pc_confirmed = 0; //�m�F�L�����Z�� + reset_pc_cancel(); + } + } + // CONFIRM + if (PUSH_EVENT & PUSH_VALSTR) { + // �l�̃X�g�A + if (global_registers[Ssw_rw] == 1) { + //�폜 + char res = reset_mem(reset_mem_confirmed);//���m�F�̏��F + if (1 == res) reset_mem_confirmed = 1; //���m�F + if (0 == res) reset_mem_confirmed = 0; //���Z�b�g�̊m�F + } else { + store_value(); + } + } + if (PUSH_EVENT & PUSH_INSSTR) { + // ���߂̃X�g�A + if (global_registers[Ssw_rw] == 1) { + //PC�̃��Z�b�g + char res = reset_pc(reset_pc_confirmed);//���m�F�̏��F + if (1 == res) reset_pc_confirmed = 1; //���m�F + if (0 == res) reset_pc_confirmed = 0; //���Z�b�g�̊m�F + } else { + store_inst(); + } + } + // RUN + if (PUSH_EVENT & PUSH_RUN) { + if (global_current_memory != (unsigned int)global_registers[Ssw_psel]) { + global_current_memory = (unsigned int)global_registers[Ssw_psel]; + print_change_memory(global_current_memory); + } + else { + // �v���O�����������ݒ� + fRun = RUN_INIT; + } + } + if (fRun != RUN_STOP) { + // �v���O�������s���荞�� & ���s���[�h�X�V + fRun = run_proc(fRun); + } + } + return 0; +} diff --git a/software/DE2_115_ASM/hex_encoder.c b/software/DE2_115_ASM/hex_encoder.c new file mode 100644 index 0000000..9639775 --- /dev/null +++ b/software/DE2_115_ASM/hex_encoder.c @@ -0,0 +1,205 @@ +/* + * hex_encoder.c + * + * Created on: 2016/11/17 + * Author: takayun + */ + +#include "hex_encoder.h" +#include + +void encodeNumHex(int hex_i, int num) { + char encoded = 0; + switch (num) { + case 0: + encoded = (char)0x40; // 100 0000 + break; + case 1: + encoded = (char)0xF9; // 111 1001 + break; + case 2: + encoded = (char)0x24; // 010 0100 + break; + case 3: + encoded = (char)0x30; // 011 0000 + break; + case 4: + encoded = (char)0x19; // 001 1001 + break; + case 5: + encoded = (char)0x12; // 001 0010 + break; + case 6: + encoded = (char)0x02; // 000 0010 + break; + case 7: + encoded = (char)0x58; // 101 1000 + break; + case 8: + encoded = (char)0x00; // 000 0000 + break; + case 9: + encoded = (char)0x10; // 001 0000 + break; + default: + encoded = 0; + break; + } + + switch (hex_i) { + case 0: + *hex0 = encoded; + break; + case 1: + *hex1 = encoded; + break; + case 2: + *hex2 = encoded; + break; + case 3: + *hex3 = encoded; + break; + case 4: + *hex4 = encoded; + break; + case 5: + *hex5 = encoded; + break; + case 6: + *hex6 = encoded; + break; + case 7: + *hex7 = encoded; + break; + default: + break; + } +} + +void encodeLatHex(int hex_i, char c) { + char encoded = 0; + + if (isdigit(c)) { + encodeNumHex(hex_i, c-'0'); + return; + } + + switch (c) { + case ' ': + encoded = (char)0xFF; // 111 1111 + break; + case '-': + encoded = (char)0x3F; // 011 1111 + break; + case 'a': + encoded = (char)0x08; // 000 1000 + break; + case 'b': + encoded = (char)0x03; // 000 0011 + break; + case 'c': + encoded = (char)0x27; // 010 0111 + break; + case 'd': + encoded = (char)0x21; // 010 0001 + break; + case 'e': + encoded = (char)0x06; // 000 0110 + break; + case 'f': + encoded = (char)0x0E; // 000 1110 + break; + case 'g': + encoded = (char)0x42; // 100 0010 + break; + case 'h': + encoded = (char)0x0B; // 000 1011 + break; + case 'i': + encoded = (char)0xFB; // 111 1011 + break; + case 'j': + encoded = (char)0x61; // 110 0001 + break; + case 'k': + encoded = (char)0x0A; // 000 1010 + break; + case 'l': + encoded = (char)0x47; // 100 0111 + break; + case 'm': + encoded = (char)0x48; // 100 1000 + break; + case 'n': + encoded = (char)0x2B; // 010 1011 + break; + case 'o': + encoded = (char)0x23; // 010 0011 + break; + case 'p': + encoded = (char)0x0C; // 000 1100 + break; + case 'q': + encoded = (char)0x04; // 000 0100 + break; + case 'r': + encoded = (char)0x2F; // 010 1111 + break; + case 's': + encoded = (char)0x13; // 001 0011 + break; + case 't': + encoded = (char)0x07; // 000 0111 + break; + case 'u': + encoded = (char)0x63; // 110 0011 + break; + case 'v': + encoded = (char)0x41; // 100 0001 + break; + case 'w': + encoded = (char)0x01; // 000 0001 + break; + case 'x': + encoded = (char)0x09; // 000 1001 + break; + case 'y': + encoded = (char)0x11; // 001 0001 + break; + case 'z': + encoded = (char)0x64; // 110 0100 + break; + default: + encoded = 0; + break; + } + + switch (hex_i) { + case 0: + *hex0 = encoded; + break; + case 1: + *hex1 = encoded; + break; + case 2: + *hex2 = encoded; + break; + case 3: + *hex3 = encoded; + break; + case 4: + *hex4 = encoded; + break; + case 5: + *hex5 = encoded; + break; + case 6: + *hex6 = encoded; + break; + case 7: + *hex7 = encoded; + break; + default: + break; + } +} diff --git a/software/DE2_115_ASM/hex_encoder.h b/software/DE2_115_ASM/hex_encoder.h new file mode 100644 index 0000000..7909cf8 --- /dev/null +++ b/software/DE2_115_ASM/hex_encoder.h @@ -0,0 +1,38 @@ +/* + * hex_encoder.h + * + * Created on: 2016/11/17 + * Author: takayun + */ + +#ifndef HEX_ENCODER_H_ +#define HEX_ENCODER_H_ + +#include "system.h" + +/************************************************** + * Defines + **************************************************/ + +#define hex0 (volatile char *) HEX0_BASE +#define hex1 (volatile char *) HEX1_BASE +#define hex2 (volatile char *) HEX2_BASE +#define hex3 (volatile char *) HEX3_BASE +#define hex4 (volatile char *) HEX4_BASE +#define hex5 (volatile char *) HEX5_BASE +#define hex6 (volatile char *) HEX6_BASE +#define hex7 (volatile char *) HEX7_BASE + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void encodeNumHex(int hex_i, int num); +void encodeLatHex(int hex_i, char c); + +#endif /* HEX_ENCODER_H_ */ diff --git a/software/DE2_115_ASM/hex_out.c b/software/DE2_115_ASM/hex_out.c new file mode 100644 index 0000000..874dbac --- /dev/null +++ b/software/DE2_115_ASM/hex_out.c @@ -0,0 +1,67 @@ +/* + * hex_out.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "hex_out.h" +#include "hex_encoder.h" +#include "sys_except.h" + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { + int i; + if (block_i == HEX0_3) { + if (size > 4) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i,str[size-1-i]); + } + } + else if (block_i == HEX4_5) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i+4,str[size-1-i]); + } + } + else if (block_i == HEX6_7) { + if (size > 2) panic(); + for (i = 0; i < size; i++) { + encodeLatHex(i+6,str[size-1-i]); + } + } +} + +void clear_block(enum BLOCK_N block_i) { + if (block_i == HEX0_3) { + print_block(" ", 4, HEX0_3); + } + else if (block_i == HEX4_5) { + print_block(" ", 2, HEX4_5); + } + else if (block_i == HEX6_7) { + print_block(" ", 2, HEX6_7); + } +} + +void print_number(char num) { + int i; + char buf[5]; + char val; + for (i = 0; i < 4; i++) { + if (num < 0) { + buf[0] = '-'; + val = -num; + } else { + buf[0] = ' '; + val = num; + } + buf[1] = val/100%10 + '0'; + buf[2] = val/10%10 + '0'; + buf[3] = val%10 + '0'; + } + clear_block(HEX0_3); + print_block(buf, 4, HEX0_3); +} + + + + diff --git a/software/DE2_115_ASM/hex_out.h b/software/DE2_115_ASM/hex_out.h new file mode 100644 index 0000000..99219b5 --- /dev/null +++ b/software/DE2_115_ASM/hex_out.h @@ -0,0 +1,33 @@ +/* + * hex_out.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef HEX_IO_H_ +#define HEX_IO_H_ + +/************************************************** + * Defines + **************************************************/ + +enum BLOCK_N { + HEX0_3, HEX4_5, HEX6_7 +}; + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void print_block(char * str, unsigned int size, enum BLOCK_N block_i); +void clear_block(enum BLOCK_N block_i); +void print_number(char num); + + +#endif /* HEX_IO_H_ */ diff --git a/software/DE2_115_ASM/input_int.c b/software/DE2_115_ASM/input_int.c new file mode 100644 index 0000000..0145286 --- /dev/null +++ b/software/DE2_115_ASM/input_int.c @@ -0,0 +1,71 @@ +/* + * input_int.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "input_int.h" +#include "sys_register.h" + +unsigned char PUSH_EVENT = PUSH_NONE; + +void in_int() { + push_int(); +} + +static void update_sw_reg(sw_t s) { + global_registers[Ssw_data] = (char)s.data.value; + global_registers[Ssw_inst] = (char)s.splited.instruction_code; + global_registers[Ssw_memi] = (char)s.splited.memory_index; + global_registers[Ssw_regi] = (char)s.splited.register_index; + global_registers[Ssw_psel] = (char)s.splited.program_selecter; + global_registers[Ssw_rw] = (char)s.splited.rw_mode; + global_registers[Ssw_run] = (char)s.splited.run_mode; +} + +enum PushEvent push_decode(char psw) { + int result = PUSH_NONE; + switch(psw) { + case 0x3: + result += PUSH_ANY; + result += PUSH_VALSTR; + break; + case 0x5: + result += PUSH_ANY; + result += PUSH_INSSTR; + break; + case 0x6: + result += PUSH_ANY; + result += PUSH_RUN; + break; + } + return result; +} + +void push_int() { + static unsigned char status = 0; + static enum PushEvent event_code; + volatile sw_t s; + s.sw = *switches; + + switch (status) { + case 0: + PUSH_EVENT = PUSH_NONE; + if (*push_switches != 7) { + event_code = push_decode(*push_switches); + status = 1; + } + update_sw_reg(s); // �X�C�b�`���W�X�^�X�V + break; + case 1: + if (*push_switches == 7) status = 2; + break; + case 2: + PUSH_EVENT = event_code; + status = 0; + break; + default: + status = 0; + break; + } +} diff --git a/software/DE2_115_ASM/input_int.h b/software/DE2_115_ASM/input_int.h new file mode 100644 index 0000000..e1d0612 --- /dev/null +++ b/software/DE2_115_ASM/input_int.h @@ -0,0 +1,62 @@ +/* + * input_int.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SWITCHES_INT_H_ +#define SWITCHES_INT_H_ + +#include "system.h" + +/************************************************** + * Defines + **************************************************/ + +#define switches (volatile int *) SWITCHES_BASE +#define push_switches (volatile char *) PUSH_SWITCHES_BASE + +typedef union { + int sw; + struct { + unsigned int run_mode : 1; + unsigned int rw_mode : 1; + unsigned int program_selecter : 4; + unsigned int memory_index : 4; + unsigned int register_index : 4; + unsigned int instruction_code : 4; + } splited; + struct { + unsigned int : 10; + unsigned int value : 8; + } data; +} sw_t; + +enum PushEvent{ + PUSH_NONE = 1<<0, + PUSH_ANY = 1<<1, + PUSH_VALSTR = 1<<2, + PUSH_INSSTR = 1<<3, + PUSH_RUN = 1<<4 +}; + +/************************************************** + * Variables + **************************************************/ + +extern unsigned char PUSH_EVENT; + +/************************************************** + * Functions + **************************************************/ + +/* Function: in_int + * Sammary: + * �S�Ă̓��͊��荞�݂��s�� + * */ +void in_int(); + +void push_int(); + +#endif /* SWITCHES_INT_H_ */ diff --git a/software/DE2_115_ASM/inst_decoder.c b/software/DE2_115_ASM/inst_decoder.c new file mode 100644 index 0000000..3e6e8a9 --- /dev/null +++ b/software/DE2_115_ASM/inst_decoder.c @@ -0,0 +1,120 @@ +/* + * inst_decoder.c + * + * Created on: 2016/11/25 + * Author: takayun + */ + +#include "inst_decoder.h" +#include "sys_memory.h" +#include "sys_register.h" +#include "hex_out.h" +#include "sys_prog.h" +#include +#include + +struct InstRec inst_fetch(){ + struct InstRec rec = inst_memory_load((unsigned int)global_registers[Spc]); + inc_pc(); + return rec; +} + +void inst_decode(struct InstRec inst_rec){ + switch(inst_rec.inst) { + case INST_END: + break; + case INST_JUMP: + inst_jump(inst_rec.regi, inst_rec.memi); + break; + case INST_OUTPUT: + inst_output(inst_rec.regi, inst_rec.memi); + break; + case INST_LOAD: + inst_load(inst_rec.regi, inst_rec.memi); + break; + case INST_STORE: + inst_store(inst_rec.regi, inst_rec.memi); + break; + case INST_DELAY: + inst_delay(inst_rec.regi, inst_rec.memi); + break; + case INST_ADD: + inst_add(inst_rec.regi, inst_rec.memi); + break; + case INST_SUB: + inst_sub(inst_rec.regi, inst_rec.memi); + break; + case INST_COMP: + inst_comp(inst_rec.regi, inst_rec.memi); + break; + case INST_JEQ: + inst_jeq(inst_rec.regi, inst_rec.memi); + break; + case INST_JNE: + inst_jne(inst_rec.regi, inst_rec.memi); + break; + case INST_JIEQ: + inst_jieq(inst_rec.regi, inst_rec.memi); + break; + case INST_JINE: + inst_jine(inst_rec.regi, inst_rec.memi); + break; + } +} + +void inst_jump(enum Register reg, unsigned char memory_index){ + set_pc(global_registers[reg]+memory_index); +} +void inst_output(enum Register reg, unsigned char memory_index){ + //�������̒l��7�Z�O�ɕ\�� + char buf[5]; + memory_load(memory_index, Sseg); + sprintf(buf, "%04d", global_registers[Sseg]); + print_block(buf, 4, HEX0_3); +} +void inst_load(enum Register reg, unsigned char memory_index){ + memory_load(memory_index, reg); +} +void inst_store(enum Register reg, unsigned char memory_index){ + memory_store(memory_index, reg); +} +void inst_delay(enum Register reg, unsigned char memory_index){ + //���W�X�^�̒l*10ms�҂� + usleep((int)global_registers[reg]*10000); +} +void inst_add(enum Register reg, unsigned char memory_index){ + global_registers[Sacc]+=global_registers[reg]; +} +void inst_sub(enum Register reg, unsigned char memory_index){ + global_registers[Sacc]-=global_registers[reg]; +} +void inst_comp(enum Register reg, unsigned char memory_index){ + if(global_registers[Sacc]==global_registers[reg]){ + global_registers[Sflg]=0; + } else if(global_registers[Sacc] > global_registers[reg]){ + global_registers[Sflg]=-1; + }else{ + global_registers[Sflg]=1; + } +} +void inst_jeq(enum Register reg, unsigned char memory_index){ + if(global_registers[Sflg]==global_registers[reg]){ + inc_pc(); + } +} +void inst_jne(enum Register reg, unsigned char memory_index){ + if(global_registers[Sflg]!=global_registers[reg]){ + inc_pc(); + } +} +void inst_jieq(char im, unsigned char memory_index){ + if(global_registers[Sflg]==im){ + inc_pc(); + } +} +void inst_jine(char im, unsigned char memory_index){ + if(global_registers[Sflg]!=im){ + inc_pc(); + } +} + diff --git a/software/DE2_115_ASM/inst_decoder.h b/software/DE2_115_ASM/inst_decoder.h new file mode 100644 index 0000000..036e179 --- /dev/null +++ b/software/DE2_115_ASM/inst_decoder.h @@ -0,0 +1,51 @@ +/* + * inst_decoder.h + * + * Created on: 2016/11/25 + * Author: takayun + */ + +#ifndef INST_DECODER_H_ +#define INST_DECODER_H_ + +#include "sys_register.h" + +#define INST_END 0x0 +#define INST_JUMP 0x1 +#define INST_OUTPUT 0x2 +#define INST_LOAD 0x3 +#define INST_STORE 0x4 +#define INST_DELAY 0x5 +#define INST_ADD 0x6 +#define INST_COMP 0x7 +#define INST_JEQ 0x8 +#define INST_JNE 0x9 +#define INST_JIEQ 0xA +#define INST_JINE 0xB +#define INST_SUB 0xC + +struct InstRec { + unsigned int inst : 4; + unsigned int memi : 4; + unsigned int regi : 4; +}; + +struct InstRec inst_fetch(); + +void inst_decode(struct InstRec inst_rec); + +void inst_jump(enum Register reg, unsigned char memory_index); +void inst_output(enum Register reg, unsigned char memory_index); +void inst_load(enum Register reg, unsigned char memory_index); +void inst_store(enum Register reg, unsigned char memory_index); +void inst_delay(enum Register reg, unsigned char memory_index); +void inst_add(enum Register reg, unsigned char memory_index); +void inst_sub(enum Register reg, unsigned char memory_index); +void inst_comp(enum Register reg, unsigned char memory_index); +void inst_jeq(enum Register reg, unsigned char memory_index); +void inst_jne(enum Register reg, unsigned char memory_index); +void inst_jieq(char im, unsigned char memory_index); +void inst_jine(char im, unsigned char memory_index); + + +#endif /* INST_DECODER_H_ */ diff --git a/software/DE2_115_ASM/lcd_out.c b/software/DE2_115_ASM/lcd_out.c new file mode 100644 index 0000000..b09a0bb --- /dev/null +++ b/software/DE2_115_ASM/lcd_out.c @@ -0,0 +1,29 @@ +#include "lcd_out.h" +#include +#include +#include +#include +#include "system.h" +#include "LCD.h" + +// LCD�̏����� +void lcd_init() { + *lcd_on = 1; + *lcd_blon = 1; + LCD_Init(); +} + +// LCD�̃L�����b�g���P�s�ڂ̂͂��߂Ɉړ����� +void lcd_caret_reset() { + LCD_Init(); +} + +// LCD�̃L�����b�g���Q�s�ڂ̂͂��߂Ɉړ����� +void lcd_caret_reset2() { + LCD_Line2(); +} + +// LCD�ɕ�����\������ +void lcd_print(const char *str) { + LCD_Show_Text(str); +} diff --git a/software/DE2_115_ASM/lcd_out.h b/software/DE2_115_ASM/lcd_out.h new file mode 100644 index 0000000..7c51dd4 --- /dev/null +++ b/software/DE2_115_ASM/lcd_out.h @@ -0,0 +1,28 @@ +/* + * lcd_out.h + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#ifndef LCD_OUT_H_ +#define LCD_OUT_H_ + +#include "system.h" + +#define lcd_on (volatile char *) LCD_ON_BASE +#define lcd_blon (volatile char *) LCD_BLON_BASE + +// LCD�̏����� +void lcd_init(); + +// LCD�̃L�����b�g���P�s�ڂ̂͂��߂Ɉړ����� +void lcd_caret_reset(); + +// LCD�̃L�����b�g���Q�s�ڂ̂͂��߂Ɉړ����� +void lcd_caret_reset2(); + +// LCD�ɕ�����\������ +void lcd_print(const char *str); + +#endif /* LCD_OUT_H_ */ diff --git a/software/DE2_115_ASM/obj/default/.force_relink b/software/DE2_115_ASM/obj/default/.force_relink new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/.force_relink diff --git a/software/DE2_115_ASM/obj/default/LCD.d b/software/DE2_115_ASM/obj/default/LCD.d new file mode 100644 index 0000000..45a1357 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/LCD.d @@ -0,0 +1,13 @@ +obj/default/LCD.o: LCD.c ../DE2_115_ASM_bsp//HAL/inc/io.h \ + ../DE2_115_ASM_bsp//HAL/inc/alt_types.h ../DE2_115_ASM_bsp/system.h \ + ../DE2_115_ASM_bsp/linker.h LCD.h + +../DE2_115_ASM_bsp//HAL/inc/io.h: + +../DE2_115_ASM_bsp//HAL/inc/alt_types.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: + +LCD.h: diff --git a/software/DE2_115_ASM/obj/default/LCD.o b/software/DE2_115_ASM/obj/default/LCD.o new file mode 100644 index 0000000..52ae901 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/LCD.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/hello_world_small.d b/software/DE2_115_ASM/obj/default/hello_world_small.d new file mode 100644 index 0000000..4620298 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/hello_world_small.d @@ -0,0 +1,26 @@ +obj/default/hello_world_small.o: hello_world_small.c \ + ../DE2_115_ASM_bsp//HAL/inc/sys/alt_stdio.h ../DE2_115_ASM_bsp/system.h \ + ../DE2_115_ASM_bsp/linker.h hex_out.h lcd_out.h sys_register.h \ + sys_memory.h inst_decoder.h input_int.h sys_debug.h sys_prog.h + +../DE2_115_ASM_bsp//HAL/inc/sys/alt_stdio.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: + +hex_out.h: + +lcd_out.h: + +sys_register.h: + +sys_memory.h: + +inst_decoder.h: + +input_int.h: + +sys_debug.h: + +sys_prog.h: diff --git a/software/DE2_115_ASM/obj/default/hello_world_small.o b/software/DE2_115_ASM/obj/default/hello_world_small.o new file mode 100644 index 0000000..1732ec2 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/hello_world_small.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/hex_encoder.d b/software/DE2_115_ASM/obj/default/hex_encoder.d new file mode 100644 index 0000000..9c3616e --- /dev/null +++ b/software/DE2_115_ASM/obj/default/hex_encoder.d @@ -0,0 +1,8 @@ +obj/default/hex_encoder.o: hex_encoder.c hex_encoder.h \ + ../DE2_115_ASM_bsp/system.h ../DE2_115_ASM_bsp/linker.h + +hex_encoder.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: diff --git a/software/DE2_115_ASM/obj/default/hex_encoder.o b/software/DE2_115_ASM/obj/default/hex_encoder.o new file mode 100644 index 0000000..541f60a --- /dev/null +++ b/software/DE2_115_ASM/obj/default/hex_encoder.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/hex_out.d b/software/DE2_115_ASM/obj/default/hex_out.d new file mode 100644 index 0000000..613323b --- /dev/null +++ b/software/DE2_115_ASM/obj/default/hex_out.d @@ -0,0 +1,12 @@ +obj/default/hex_out.o: hex_out.c hex_out.h hex_encoder.h \ + ../DE2_115_ASM_bsp/system.h ../DE2_115_ASM_bsp/linker.h sys_except.h + +hex_out.h: + +hex_encoder.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: + +sys_except.h: diff --git a/software/DE2_115_ASM/obj/default/hex_out.o b/software/DE2_115_ASM/obj/default/hex_out.o new file mode 100644 index 0000000..d2780d1 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/hex_out.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/input_int.d b/software/DE2_115_ASM/obj/default/input_int.d new file mode 100644 index 0000000..cb5f901 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/input_int.d @@ -0,0 +1,10 @@ +obj/default/input_int.o: input_int.c input_int.h \ + ../DE2_115_ASM_bsp/system.h ../DE2_115_ASM_bsp/linker.h sys_register.h + +input_int.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: + +sys_register.h: diff --git a/software/DE2_115_ASM/obj/default/input_int.o b/software/DE2_115_ASM/obj/default/input_int.o new file mode 100644 index 0000000..e26ee6b --- /dev/null +++ b/software/DE2_115_ASM/obj/default/input_int.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/inst_decoder.d b/software/DE2_115_ASM/obj/default/inst_decoder.d new file mode 100644 index 0000000..760a64b --- /dev/null +++ b/software/DE2_115_ASM/obj/default/inst_decoder.d @@ -0,0 +1,12 @@ +obj/default/inst_decoder.o: inst_decoder.c inst_decoder.h sys_register.h \ + sys_memory.h hex_out.h sys_prog.h + +inst_decoder.h: + +sys_register.h: + +sys_memory.h: + +hex_out.h: + +sys_prog.h: diff --git a/software/DE2_115_ASM/obj/default/inst_decoder.o b/software/DE2_115_ASM/obj/default/inst_decoder.o new file mode 100644 index 0000000..f0d9b27 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/inst_decoder.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/lcd_out.d b/software/DE2_115_ASM/obj/default/lcd_out.d new file mode 100644 index 0000000..4676ad5 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/lcd_out.d @@ -0,0 +1,10 @@ +obj/default/lcd_out.o: lcd_out.c lcd_out.h ../DE2_115_ASM_bsp/system.h \ + ../DE2_115_ASM_bsp/linker.h LCD.h + +lcd_out.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: + +LCD.h: diff --git a/software/DE2_115_ASM/obj/default/lcd_out.o b/software/DE2_115_ASM/obj/default/lcd_out.o new file mode 100644 index 0000000..4bba397 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/lcd_out.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/sys_debug.d b/software/DE2_115_ASM/obj/default/sys_debug.d new file mode 100644 index 0000000..be9f474 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_debug.d @@ -0,0 +1,15 @@ +obj/default/sys_debug.o: sys_debug.c sys_debug.h inst_decoder.h \ + sys_register.h lcd_out.h ../DE2_115_ASM_bsp/system.h \ + ../DE2_115_ASM_bsp/linker.h + +sys_debug.h: + +inst_decoder.h: + +sys_register.h: + +lcd_out.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: diff --git a/software/DE2_115_ASM/obj/default/sys_debug.o b/software/DE2_115_ASM/obj/default/sys_debug.o new file mode 100644 index 0000000..7c05a1d --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_debug.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/sys_except.d b/software/DE2_115_ASM/obj/default/sys_except.d new file mode 100644 index 0000000..bb8976f --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_except.d @@ -0,0 +1,8 @@ +obj/default/sys_except.o: sys_except.c ../DE2_115_ASM_bsp/system.h \ + ../DE2_115_ASM_bsp/linker.h hex_out.h + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: + +hex_out.h: diff --git a/software/DE2_115_ASM/obj/default/sys_except.o b/software/DE2_115_ASM/obj/default/sys_except.o new file mode 100644 index 0000000..bdecd6b --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_except.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/sys_memory.d b/software/DE2_115_ASM/obj/default/sys_memory.d new file mode 100644 index 0000000..d6373a1 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_memory.d @@ -0,0 +1,15 @@ +obj/default/sys_memory.o: sys_memory.c ../DE2_115_ASM_bsp/system.h \ + ../DE2_115_ASM_bsp/linker.h sys_memory.h sys_register.h inst_decoder.h \ + sys_except.h + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: + +sys_memory.h: + +sys_register.h: + +inst_decoder.h: + +sys_except.h: diff --git a/software/DE2_115_ASM/obj/default/sys_memory.o b/software/DE2_115_ASM/obj/default/sys_memory.o new file mode 100644 index 0000000..5ec0baf --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_memory.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/sys_prog.d b/software/DE2_115_ASM/obj/default/sys_prog.d new file mode 100644 index 0000000..996ae7f --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_prog.d @@ -0,0 +1,21 @@ +obj/default/sys_prog.o: sys_prog.c sys_prog.h sys_debug.h inst_decoder.h \ + sys_register.h sys_memory.h hex_out.h lcd_out.h \ + ../DE2_115_ASM_bsp/system.h ../DE2_115_ASM_bsp/linker.h + +sys_prog.h: + +sys_debug.h: + +inst_decoder.h: + +sys_register.h: + +sys_memory.h: + +hex_out.h: + +lcd_out.h: + +../DE2_115_ASM_bsp/system.h: + +../DE2_115_ASM_bsp/linker.h: diff --git a/software/DE2_115_ASM/obj/default/sys_prog.o b/software/DE2_115_ASM/obj/default/sys_prog.o new file mode 100644 index 0000000..c6a99eb --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_prog.o Binary files differ diff --git a/software/DE2_115_ASM/obj/default/sys_register.d b/software/DE2_115_ASM/obj/default/sys_register.d new file mode 100644 index 0000000..42e349a --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_register.d @@ -0,0 +1,3 @@ +obj/default/sys_register.o: sys_register.c sys_register.h + +sys_register.h: diff --git a/software/DE2_115_ASM/obj/default/sys_register.o b/software/DE2_115_ASM/obj/default/sys_register.o new file mode 100644 index 0000000..62d1be4 --- /dev/null +++ b/software/DE2_115_ASM/obj/default/sys_register.o Binary files differ diff --git a/software/DE2_115_ASM/readme.txt b/software/DE2_115_ASM/readme.txt new file mode 100644 index 0000000..a949aa6 --- /dev/null +++ b/software/DE2_115_ASM/readme.txt @@ -0,0 +1,26 @@ +Readme - Hello World Software Example + +DESCRIPTION: +Simple program that prints "Hello from Nios II" + +The memory footprint of this hosted application is intended to be small (under 100 kbytes) by default +using a standard reference deisgn. + +For an even smaller, reduced footprint version of this template, and an explanation of how +to reduce the memory footprint for a given application, see the +"small_hello_world" template. + + +PERIPHERALS USED: +This example exercises the following peripherals: +- STDOUT device (UART or JTAG UART) + +SOFTWARE SOURCE FILES: +This example includes the following software source files: +- hello_world.c: Everyone needs a Hello World program, right? + +BOARD/HOST REQUIREMENTS: +This example requires only a JTAG connection with a Nios Development board. If +the host communication settings are changed from JTAG UART (default) to use a +conventional UART, a serial cable between board DB-9 connector and the host is +required. diff --git a/software/DE2_115_ASM/sys_debug.c b/software/DE2_115_ASM/sys_debug.c new file mode 100644 index 0000000..190b908 --- /dev/null +++ b/software/DE2_115_ASM/sys_debug.c @@ -0,0 +1,121 @@ +/* + * sys_debug.c + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#include "sys_debug.h" +#include +#include "lcd_out.h" +#include + +void display_inst(struct InstRec inst, unsigned int pc) { + char inst_name[INST_NAME_ARRAY_LEN]; // ���ߖ� + char reg_name[REG_NAME_ARRAY_LEN]; // ���W�X�^�� + char buf[17]; + + // ���߂̖��O�̎擾 + convertInstName(inst_name, inst.inst); + // ���W�X�^�̖��O�̎擾 + convertRegName(reg_name, inst.regi); + + lcd_caret_reset(); + sprintf(buf, "PC:0x%02x -> %4s",pc,inst_name); + lcd_print(buf); + lcd_caret_reset2(); + sprintf(buf, "REG:%3s,MEM:0x%1x",reg_name,inst.memi); + lcd_print(buf); +} + +void display_mem(unsigned char memi, char memv) { + char buf[17]; + + lcd_caret_reset(); + sprintf(buf, "MEM:0x%1x",memi); + lcd_print(buf); + lcd_caret_reset2(); + sprintf(buf, "value:%d",memv); + lcd_print(buf); +} + +void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code) { + switch(reg_code) { + case Szero: + sprintf(reg_name, STRING_REG_ZERO); + break; + case Spc: + sprintf(reg_name, STRING_REG_PC); + break; + case Ssp: + sprintf(reg_name, STRING_REG_SP); + break; + case Sgp0: + sprintf(reg_name, STRING_REG_GP0); + break; + case Sgp1: + sprintf(reg_name, STRING_REG_GP1); + break; + case Sacc: + sprintf(reg_name, STRING_REG_ACC); + break; + case Sflg: + sprintf(reg_name, STRING_REG_FLG); + break; + default: + sprintf(reg_name, "non"); + break; + } +} + + +void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code) { + switch(inst_code) { + case INST_END: + sprintf(inst_name, STRING_INST_END); + break; + case INST_JUMP: + sprintf(inst_name, STRING_INST_JUMP); + break; + case INST_OUTPUT: + sprintf(inst_name, STRING_INST_OUTPUT); + break; + case INST_LOAD: + sprintf(inst_name, STRING_INST_LOAD); + break; + case INST_STORE: + sprintf(inst_name, STRING_INST_STORE); + break; + case INST_DELAY: + sprintf(inst_name, STRING_INST_DELAY); + break; + case INST_ADD: + sprintf(inst_name, STRING_INST_ADD); + break; + case INST_SUB: + sprintf(inst_name, STRING_INST_SUB); + break; + case INST_COMP: + sprintf(inst_name, STRING_INST_COMP); + break; + case INST_JEQ: + sprintf(inst_name, STRING_INST_JEQ); + break; + case INST_JNE: + sprintf(inst_name, STRING_INST_JNE); + break; + case INST_JIEQ: + sprintf(inst_name, STRING_INST_JIEQ); + break; + case INST_JINE: + sprintf(inst_name, STRING_INST_JINE); + break; + default: + sprintf(inst_name, "NoOp"); + break; + } +} + +void delay10ms(unsigned int s) { + usleep(s*10000); +} diff --git a/software/DE2_115_ASM/sys_debug.h b/software/DE2_115_ASM/sys_debug.h new file mode 100644 index 0000000..bb1fb1c --- /dev/null +++ b/software/DE2_115_ASM/sys_debug.h @@ -0,0 +1,62 @@ +/* + * sys_debug.h + * + * Created on: 2016/12/02 + * Author: takayun + */ + +#ifndef SYS_DEBUG_H_ +#define SYS_DEBUG_H_ + +#include "inst_decoder.h" +#include "sys_register.h" + +/************************************************** + * Defines + **************************************************/ + +#define INST_NAME_ARRAY_LEN 5 + +#define STRING_INST_END "END" +#define STRING_INST_JUMP "JUMP" +#define STRING_INST_OUTPUT "OUT" +#define STRING_INST_LOAD "LOAD" +#define STRING_INST_STORE "STOR" +#define STRING_INST_DELAY "DELY" +#define STRING_INST_ADD "ADD" +#define STRING_INST_COMP "COMP" +#define STRING_INST_JEQ "JEQ" +#define STRING_INST_JNE "JNE" +#define STRING_INST_JIEQ "JIEQ" +#define STRING_INST_JINE "JINE" +#define STRING_INST_SUB "SUB" + + +#define REG_NAME_ARRAY_LEN 4 + +#define STRING_REG_ZERO "ZE" +#define STRING_REG_PC "PC" +#define STRING_REG_SP "SP" +#define STRING_REG_GP0 "GP0" +#define STRING_REG_GP1 "GP1" +#define STRING_REG_ACC "ACC" +#define STRING_REG_FLG "FLG" + +/************************************************** + * Variables + **************************************************/ + + +/************************************************** + * Functions + **************************************************/ + +void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code); +void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code); + +void display_inst(struct InstRec inst, unsigned int pc); +void display_mem(unsigned char memi, char memv); + +void delay10ms(unsigned int s); + +#endif /* SYS_DEBUG_H_ */ diff --git a/software/DE2_115_ASM/sys_except.c b/software/DE2_115_ASM/sys_except.c new file mode 100644 index 0000000..82420a4 --- /dev/null +++ b/software/DE2_115_ASM/sys_except.c @@ -0,0 +1,14 @@ +/* + * sys_except.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "system.h" +#include "hex_out.h" + +void panic() { + clear_block(HEX0_3); + print_block("err ", 4, HEX0_3); +} + diff --git a/software/DE2_115_ASM/sys_except.h b/software/DE2_115_ASM/sys_except.h new file mode 100644 index 0000000..fa6f420 --- /dev/null +++ b/software/DE2_115_ASM/sys_except.h @@ -0,0 +1,13 @@ +/* + * sys_except.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYSTEM_H_ +#define SYSTEM_H_ + +void panic(); + +#endif /* SYSTEM_H_ */ diff --git a/software/DE2_115_ASM/sys_memory.c b/software/DE2_115_ASM/sys_memory.c new file mode 100644 index 0000000..71b9d69 --- /dev/null +++ b/software/DE2_115_ASM/sys_memory.c @@ -0,0 +1,59 @@ +/* + * sys_memory.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "system.h" +#include "sys_memory.h" +#include "sys_register.h" +#include "sys_except.h" + +/************************************************** + * Public + **************************************************/ + +// �����������̂ǂ̃�������(0 < global_current_memory < MEMS_COUNT) +unsigned int global_current_memory = 0; + +/************************************************** + * Private + **************************************************/ + +// �����������̕ϐ� +static char memory[MEMS_COUNT][MEM_SIZE]; + +static struct InstRec inst_memory[MEMS_COUNT][MEM_SIZE]; + + +/************************************************** + * Impl + **************************************************/ + +void memory_init() { + int i, j; + for (i = 0; i < MEMS_COUNT; i++) + for (j = 0; j < MEM_SIZE; j++) { + memory[i][j] = 0; + } +} + +void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec){ + inst_memory[global_current_memory][mem_addr] = inst_rec; +} +struct InstRec inst_memory_load(unsigned int mem_addr){ + return inst_memory[global_current_memory][mem_addr]; +} + +char memory_store(unsigned int mem_addr, enum Register reg) { + if (!(mem_addr < MEM_SIZE)) panic(); + memory[global_current_memory][mem_addr] = global_registers[reg]; + return memory[global_current_memory][mem_addr]; +} + +char memory_load(unsigned int mem_addr, enum Register reg) { + if (!(mem_addr < MEM_SIZE)) panic(); + global_registers[reg] = memory[global_current_memory][mem_addr]; + return global_registers[reg]; +} + diff --git a/software/DE2_115_ASM/sys_memory.h b/software/DE2_115_ASM/sys_memory.h new file mode 100644 index 0000000..f67c9a4 --- /dev/null +++ b/software/DE2_115_ASM/sys_memory.h @@ -0,0 +1,67 @@ +/* + * sys_memory.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYS_MEMORY_H_ +#define SYS_MEMORY_H_ + +#include "sys_register.h" +#include "inst_decoder.h" + +/************************************************** + * Defines + **************************************************/ + +// �������̐� +#define MEMS_COUNT 16 + +// 1�������̃T�C�Y +#define MEM_SIZE 16 + +/************************************************** + * Variables + **************************************************/ + +extern unsigned int global_current_memory; + +/************************************************** + * Functions + **************************************************/ + +/* Function: memory_init + * Sammary: + * ������������������(All 0) */ +void memory_init(); + +/* ���ߗp�������ɖ��߂̃X�g�A&���[�h */ + +/* Function: memory_store -> char + * Sammary: + * �������̎w��Ԓn�Ɏw�肵�����W�X�^����l���i�[���� + * Return: + * �������Ɋi�[���ꂽ�l */ +void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec); +struct InstRec inst_memory_load(unsigned int mem_addr); + + +/* ������-���W�X�^�Ԃ̑��� */ + +/* Function: memory_store -> char + * Sammary: + * �������̎w��Ԓn�Ɏw�肵�����W�X�^����l���i�[���� + * Return: + * �������Ɋi�[���ꂽ�l */ +char memory_store(unsigned int mem_addr, enum Register reg); + +/* Function: memory_store -> char + * Sammary: + * �w�肵�����W�X�^�Ƀ������̎w��Ԓn����l���i�[���� + * Return: + * ���W�X�^�Ɋi�[���ꂽ�l */ +char memory_load(unsigned int mem_addr, enum Register reg); + + +#endif /* SYS_MEMORY_H_ */ diff --git a/software/DE2_115_ASM/sys_prog.c b/software/DE2_115_ASM/sys_prog.c new file mode 100644 index 0000000..bbcc395 --- /dev/null +++ b/software/DE2_115_ASM/sys_prog.c @@ -0,0 +1,84 @@ +/* + * sys_prog.c + * + * Created on: 2016/12/15 + * Author: takayun + */ + +#include "sys_prog.h" +#include +#include "sys_debug.h" +#include "sys_register.h" +#include "sys_memory.h" +#include "hex_out.h" +#include "lcd_out.h" + +unsigned int inc_pc() { + if ((unsigned char)global_registers[Spc]+1 < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + global_registers[Spc] = (unsigned char)global_registers[Spc] + 1; + } else { + global_registers[Spc] = 0; + } + return 0; +} +unsigned int add_pc(unsigned int cnt) { + int i; + for (i = 0; i < cnt; i++) inc_pc(); + return 0; +} +unsigned int set_pc(unsigned int cnt) { + global_registers[Spc]=cnt; + return 0; +} +unsigned int get_pc() { + if ((unsigned char)global_registers[Spc] < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + return (unsigned int)global_registers[Spc]; + } else { + return 0; + } +} + +enum RunMode run_proc(enum RunMode mode) { + volatile struct InstRec inst_rec; + + if (RUN_INIT == mode) { + lcd_caret_reset(); + lcd_print("Run...now"); + + global_registers[Spc] = 0; + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + + // �v���O�������s���֑J�� + return RUN_PROC; + } + + if (RUN_PROC == mode) { + // ���߃t�F�b�` + inst_rec = inst_fetch(); + // ���߃f�R�[�h���s + inst_decode(inst_rec); + // pc�\�� + { + char buf[5]; + sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); + print_block("pc", 2, HEX6_7); + print_block(buf, 2, HEX4_5); + } + + // �f�o�b�N�p + if ( global_registers[Ssw_run] ) delay10ms(100U); + + // �v���O�����I������ + if (inst_rec.inst != INST_END) return RUN_PROC; + return RUN_TERM; + } + + if (RUN_TERM == mode) { + lcd_caret_reset(); + lcd_print("Run...Exit"); + return RUN_STOP; + } + + // Default + return RUN_STOP; +} diff --git a/software/DE2_115_ASM/sys_prog.h b/software/DE2_115_ASM/sys_prog.h new file mode 100644 index 0000000..b112e4c --- /dev/null +++ b/software/DE2_115_ASM/sys_prog.h @@ -0,0 +1,34 @@ +/* + * sys_prog.h + * + * Created on: 2016/12/15 + * Author: takayun + */ + +#ifndef SYS_PROG_H_ +#define SYS_PROG_H_ + +/************************************************** + * Defines + **************************************************/ + +// �v���O�������s��� +enum RunMode { RUN_STOP, RUN_INIT, RUN_PROC, RUN_TERM }; + +/************************************************** + * Variables + **************************************************/ + +/************************************************** + * Functions + **************************************************/ + +// ���S��PC�̃J�E���g�A�b�v���s�� +unsigned int inc_pc(); +unsigned int add_pc(unsigned int); +unsigned int set_pc(unsigned int); +unsigned int get_pc(); + +enum RunMode run_proc(enum RunMode mode); + +#endif /* SYS_PROG_H_ */ diff --git a/software/DE2_115_ASM/sys_register.c b/software/DE2_115_ASM/sys_register.c new file mode 100644 index 0000000..26ba99b --- /dev/null +++ b/software/DE2_115_ASM/sys_register.c @@ -0,0 +1,17 @@ +/* + * sys_register.c + * + * Created on: 2016/11/24 + * Author: takayun + */ +#include "sys_register.h" + +char global_registers[REG_MAX_COUNT]; + +void registers_init() { + int i; + for (i = 0; i < REG_MAX_COUNT; i++) global_registers[i] = 0; +} + + + diff --git a/software/DE2_115_ASM/sys_register.h b/software/DE2_115_ASM/sys_register.h new file mode 100644 index 0000000..2603f26 --- /dev/null +++ b/software/DE2_115_ASM/sys_register.h @@ -0,0 +1,54 @@ +/* + * sys_register.h + * + * Created on: 2016/11/24 + * Author: takayun + */ + +#ifndef SYS_REGISTER_H_ +#define SYS_REGISTER_H_ + +/************************************************** + * Defines + **************************************************/ + +// ���W�X�^�̒�` +enum Register { + /* �ʏ�̃��W�X�^ */ + Szero, //�[�����W�X�^ + Spc, //�v���O�����J�E���^ + Ssp, //�X�^�b�N�|�C���^ + Sgp0, //�ėp���W�X�^0 + Sgp1, //�ėp���W�X�^1 + Sacc, //�A�L�������[�^ + Sflg, //�t���O���W�X�^ + /* �X�C�b�`�ǂݏo���p���W�X�^ */ + Ssw_data, //�f�[�^(8bit) + Ssw_inst, //����(4bit) + Ssw_regi, //���W�X�^�ԍ�(4bit) + Ssw_memi, //�������Ԓn(4bit) + Ssw_psel, //�v���O�����Z���N�^(4bit) + Ssw_rw, //�ǂݏ������[�h(1bit) + Ssw_run, //���s���[�h(1bit) + /* 7�Z�O�p���W�X�^ */ + Sseg, + + /* �z��錾�p */ + REG_MAX_COUNT +}; + +/************************************************** + * Variables + **************************************************/ + +// ���W�X�^�p�̕ϐ� +extern char global_registers[REG_MAX_COUNT]; + +/************************************************** + * Functions + **************************************************/ + +void registers_init(); + + +#endif /* SYS_REGISTER_H_ */ diff --git a/software/DE2_115_ASM_bsp/.cproject b/software/DE2_115_ASM_bsp/.cproject new file mode 100644 index 0000000..4eebd52 --- /dev/null +++ b/software/DE2_115_ASM_bsp/.cproject @@ -0,0 +1,481 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/DE2_115_ASM_bsp/.project b/software/DE2_115_ASM_bsp/.project new file mode 100644 index 0000000..8c2089c --- /dev/null +++ b/software/DE2_115_ASM_bsp/.project @@ -0,0 +1,85 @@ + + + DE2_115_ASM_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://DE2_115_ASM_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/software/DE2_115_ASM_bsp/HAL/inc/alt_types.h b/software/DE2_115_ASM_bsp/HAL/inc/alt_types.h new file mode 100644 index 0000000..8eb438f --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/alt_types.h @@ -0,0 +1,54 @@ +#ifndef __ALT_TYPES_H__ +#define __ALT_TYPES_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Don't declare these typedefs if this file is included by assembly source. + */ +#ifndef ALT_ASM_SRC +typedef signed char alt_8; +typedef unsigned char alt_u8; +typedef signed short alt_16; +typedef unsigned short alt_u16; +typedef signed long alt_32; +typedef unsigned long alt_u32; +typedef long long alt_64; +typedef unsigned long long alt_u64; +#endif + +#define ALT_INLINE __inline__ +#define ALT_ALWAYS_INLINE __attribute__ ((always_inline)) +#define ALT_WEAK __attribute__((weak)) + +#endif /* __ALT_TYPES_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/altera_nios2_qsys_irq.h b/software/DE2_115_ASM_bsp/HAL/inc/altera_nios2_qsys_irq.h new file mode 100644 index 0000000..910c91c --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/altera_nios2_qsys_irq.h @@ -0,0 +1,80 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * Support for the Nios II internal interrupt controller. + */ + +#ifndef __ALT_NIOS2_QSYS_IRQ_H__ +#define __ALT_NIOS2_QSYS_IRQ_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The macro ALTERA_NIOS2_IRQ_INSTANCE is used by the alt_irq_init() + * function in the auto-generated file alt_sys_init.c to create an + * instance of this interrupt controller device driver state if this + * module contains an interrupt controller. + * Only one instance of a Nios II is allowed so this macro is just empty. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INSTANCE(name, state) + +/* + * altera_nios2_irq_init() is called by the auto-generated function + * alt_irq_init() once for the Nios II if it contains an interrupt controller. + * The altera_nios2_irq_init() routine is called using the + * ALTERA_NIOS2_IRQ_INIT macro given below. + * + * This function initializes the internal interrupt controller + * so is not called if the Nios II contains an external interrupt + * controller port (because the internal interrupt controller + * is removed if this port is present). + */ + +extern void altera_nios2_qsys_irq_init( void ); + +/* + * The macro ALTERA_NIOS2_IRQ_INIT is used by the alt_irq_init() routine + * in the auto-generated file alt_sys_init.c to initialize an instance + * of the interrupt controller device driver state. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INIT(name, state) altera_nios2_qsys_irq_init() + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_NIOS2_QSYS_IRQ_H__ */ + diff --git a/software/DE2_115_ASM_bsp/HAL/inc/io.h b/software/DE2_115_ASM_bsp/HAL/inc/io.h new file mode 100644 index 0000000..867e87d --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/io.h @@ -0,0 +1,81 @@ +#ifndef __IO_H__ +#define __IO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* IO Header file for Nios II Toolchain */ + +#include "alt_types.h" +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#ifndef SYSTEM_BUS_WIDTH +#error SYSTEM_BUS_WIDTH undefined +#endif + +/* Dynamic bus access functions */ + +#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \ + ((void *)(((alt_u8*)BASE) + (OFFSET))) + +#define IORD_32DIRECT(BASE, OFFSET) \ + __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_16DIRECT(BASE, OFFSET) \ + __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_8DIRECT(BASE, OFFSET) \ + __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) + +#define IOWR_32DIRECT(BASE, OFFSET, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_16DIRECT(BASE, OFFSET, DATA) \ + __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_8DIRECT(BASE, OFFSET, DATA) \ + __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) + +/* Native bus access functions */ + +#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \ + ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8)))) + +#define IORD(BASE, REGNUM) \ + __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM))) +#define IOWR(BASE, REGNUM, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA)) + +#ifdef __cplusplus +} +#endif + +#endif /* __IO_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/nios2.h b/software/DE2_115_ASM_bsp/HAL/inc/nios2.h new file mode 100644 index 0000000..eec4e35 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/nios2.h @@ -0,0 +1,230 @@ +#ifndef __NIOS2_H__ +#define __NIOS2_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This header provides processor specific macros for accessing the Nios2 + * control registers. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros for accessing selected processor registers + */ + +#define NIOS2_READ_ET(et) \ + do { __asm ("mov %0, et" : "=r" (et) ); } while (0) + +#define NIOS2_WRITE_ET(et) \ + do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0) + +#define NIOS2_READ_SP(sp) \ + do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0) + +/* + * Macros for useful processor instructions + */ + +#define NIOS2_BREAK() \ + do { __asm volatile ("break"); } while (0) + +#define NIOS2_REPORT_STACK_OVERFLOW() \ + do { __asm volatile("break 3"); } while (0) + +/* + * Macros for accessing the control registers. + */ + +#define NIOS2_READ_STATUS(dest) \ + do { dest = __builtin_rdctl(0); } while (0) + +#define NIOS2_WRITE_STATUS(src) \ + do { __builtin_wrctl(0, src); } while (0) + +#define NIOS2_READ_ESTATUS(dest) \ + do { dest = __builtin_rdctl(1); } while (0) + +#define NIOS2_READ_BSTATUS(dest) \ + do { dest = __builtin_rdctl(2); } while (0) + +#define NIOS2_READ_IENABLE(dest) \ + do { dest = __builtin_rdctl(3); } while (0) + +#define NIOS2_WRITE_IENABLE(src) \ + do { __builtin_wrctl(3, src); } while (0) + +#define NIOS2_READ_IPENDING(dest) \ + do { dest = __builtin_rdctl(4); } while (0) + +#define NIOS2_READ_CPUID(dest) \ + do { dest = __builtin_rdctl(5); } while (0) + + +/* + * Macros for accessing extra exception registers. These + * are always enabled wit the MPU or MMU, and optionally + * with other advanced exception types/ + */ +#define NIOS2_READ_EXCEPTION(dest) \ + do { dest = __builtin_rdctl(7); } while (0) + +#define NIOS2_READ_BADADDR(dest) \ + do { dest = __builtin_rdctl(12); } while (0) + + +/* + * Macros for accessing control registers for MPU + * operation. These should not be used unless the + * MPU is enabled. + * + * The config register may be augmented for future + * enhancements. For now, only MPU support is provided. + */ +/* Config register */ +#define NIOS2_WRITE_CONFIG(src) \ + do { __builtin_wrctl(13, src); } while (0) + +#define NIOS2_READ_CONFIG(dest) \ + do { dest = __builtin_rdctl(13); } while (0) + +/* MPU Base Address Register */ +#define NIOS2_WRITE_MPUBASE(src) \ + do { __builtin_wrctl(14, src); } while (0) + +#define NIOS2_READ_MPUBASE(dest) \ + do { dest = __builtin_rdctl(14); } while (0) + +/* MPU Access Register */ +#define NIOS2_WRITE_MPUACC(src) \ + do { __builtin_wrctl(15, src); } while (0) + +#define NIOS2_READ_MPUACC(dest) \ + do { dest = __builtin_rdctl(15); } while (0) + + +/* + * Nios II control registers that are always present + */ +#define NIOS2_STATUS status +#define NIOS2_ESTATUS estatus +#define NIOS2_BSTATUS bstatus +#define NIOS2_IENABLE ienable +#define NIOS2_IPENDING ipending +#define NIOS2_CPUID cpuid + +/* + * STATUS, BSTATUS, ESTATUS, and SSTATUS fields. + * The presence of fields is a function of the Nios II configuration. + */ +#define NIOS2_STATUS_PIE_MSK (0x00000001) +#define NIOS2_STATUS_PIE_OFST (0) +#define NIOS2_STATUS_U_MSK (0x00000002) +#define NIOS2_STATUS_U_OFST (1) +#define NIOS2_STATUS_EH_MSK (0x00000004) +#define NIOS2_STATUS_EH_OFST (2) +#define NIOS2_STATUS_IH_MSK (0x00000008) +#define NIOS2_STATUS_IH_OFST (3) +#define NIOS2_STATUS_IL_MSK (0x000003f0) +#define NIOS2_STATUS_IL_OFST (4) +#define NIOS2_STATUS_CRS_MSK (0x0000fc00) +#define NIOS2_STATUS_CRS_OFST (10) +#define NIOS2_STATUS_PRS_MSK (0x003f0000) +#define NIOS2_STATUS_PRS_OFST (16) +#define NIOS2_STATUS_NMI_MSK (0x00400000) +#define NIOS2_STATUS_NMI_OFST (22) +#define NIOS2_STATUS_RSIE_MSK (0x00800000) +#define NIOS2_STATUS_RSIE_OFST (23) +#define NIOS2_STATUS_SRS_MSK (0x80000000) +#define NIOS2_STATUS_SRS_OFST (31) + +/* + * Bit masks & offsets available with extra exceptions support + */ + +/* Exception register */ +#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) +#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) + +/* + * Bit masks & offsets for MPU support + * + * All bit-masks are expressed relative to the position + * of the data with a register. To read data that is LSB- + * aligned, the register read data should be masked, then + * right-shifted by the designated "OFST" macro value. The + * opposite should be used for register writes when starting + * with LSB-aligned data. + */ + +/* Config register */ +#define NIOS2_CONFIG_REG_PE_MASK (0x00000001) +#define NIOS2_CONFIG_REG_PE_OFST (0) +#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) +#define NIOS2_CONFIG_REG_ANI_OFST (1) + +/* MPU Base Address Register */ +#define NIOS2_MPUBASE_D_MASK (0x00000001) +#define NIOS2_MPUBASE_D_OFST (0) +#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) +#define NIOS2_MPUBASE_INDEX_OFST (1) +#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) +#define NIOS2_MPUBASE_BASE_ADDR_OFST (6) + +/* MPU Access Register */ +#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) +#define NIOS2_MPUACC_LIMIT_OFST (6) +#define NIOS2_MPUACC_MASK_MASK (0xffffffc0) +#define NIOS2_MPUACC_MASK_OFST (6) +#define NIOS2_MPUACC_C_MASK (0x00000020) +#define NIOS2_MPUACC_C_OFST (5) +#define NIOS2_MPUACC_PERM_MASK (0x0000001c) +#define NIOS2_MPUACC_PERM_OFST (2) +#define NIOS2_MPUACC_RD_MASK (0x00000002) +#define NIOS2_MPUACC_RD_OFST (1) +#define NIOS2_MPUACC_WR_MASK (0x00000001) +#define NIOS2_MPUACC_WR_OFST (0) + +/* + * Number of available IRQs in internal interrupt controller. + */ +#define NIOS2_NIRQ 32 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NIOS2_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/os/alt_flag.h b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_flag.h new file mode 100644 index 0000000..86493c2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_flag.h @@ -0,0 +1,98 @@ +#ifndef __ALT_FLAG_H__ +#define __ALT_FLAG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * uc/OS-II style event flags. These macros can be used in both a uC/OS-II based + * environment, and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. + * + * The following macros are available: + * + * ALT_FLAG_GRP - Create a flag group instance. + * ALT_EXTERN_FLAG_GRP - Create a reference to an external flag group instance. + * ALT_STATIC_FLAG_GRP - Create a static flag group instance. + * ALT_FLAG_CREATE - Initialise a flag group. + * ALT_FLAG_PEND - Pend on a flag group. + * ALT_FLAG_POST - Set a flag condition. + + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_FLAG_GRP, + * ALT_EXTERN_FLAG_GRP, and ALT_STATIC_FLAG_GRP. In these three cases the + * semi-colon is included in the macro definition; so, for example, you should + * use: + * + * ALT_FLAG_GRP(mygroup) + * + * not: + * + * ALT_FLAG_GRP(mygroup); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_no_error.h" + +#define ALT_FLAG_GRP(group) +#define ALT_EXTERN_FLAG_GRP(group) +#define ALT_STATIC_FLAG_GRP(group) + +#define ALT_FLAG_CREATE(group, flags) alt_no_error () +#define ALT_FLAG_PEND(group, flags, wait_type, timeout) alt_no_error () +#define ALT_FLAG_POST(group, flags, opt) alt_no_error () + +#ifndef ALT_SINGLE_THREADED +#define ALT_SINGLE_THREADED +#endif + +#endif /* __ALT_FLAG_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/os/alt_hooks.h b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_hooks.h new file mode 100644 index 0000000..ba1100e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_hooks.h @@ -0,0 +1,61 @@ +#ifndef __ALT_HOOKS_H__ +#define __ALT_HOOKS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides "do-nothing" macro definitions for operating system + * hooks within the HAL. The O/S component can override these to provide it's + * own implementation. + */ + +#define ALT_OS_TIME_TICK() while(0) +#define ALT_OS_INIT() while(0) +#define ALT_OS_STOP() while(0) + +/* Call from assembly code */ +#define ALT_OS_INT_ENTER_ASM +#define ALT_OS_INT_EXIT_ASM + +/* Call from C code */ +#define ALT_OS_INT_ENTER() while(0) +#define ALT_OS_INT_EXIT() while(0) + + +#endif /* __ALT_HOOKS_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/os/alt_sem.h b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_sem.h new file mode 100644 index 0000000..ed0f4a8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_sem.h @@ -0,0 +1,96 @@ +#ifndef __ALT_SEM_H__ +#define __ALT_SEM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This header provides macro definitions that can be used to create and use + * semaphores. These macros can be used in both a uC/OS-II based environment, + * and a single threaded HAL based environment. + * + * The motivation for these macros is to allow code to be developed which is + * thread safe under uC/OS-II, but incurs no additional overhead when used in a + * single threaded HAL environment. + * + * In the case of a single threaded HAL environment, they compile to + * "do nothing" directives, which ensures they do not contribute to the final + * executable. + * + * The following macros are available: + * + * ALT_SEM - Create a semaphore instance. + * ALT_EXTERN_SEM - Create a reference to an external semaphore instance. + * ALT_STATIC_SEM - Create a static semaphore instance. + * ALT_SEM_CREATE - Initialise a semaphore. + * ALT_SEM_PEND - Pend on a semaphore. + * ALT_SEM_POST - Increment a semaphore. + * + * Input arguments and return codes are all consistant with the equivalent + * uC/OS-II function. + * + * It's important to be careful in the use of the macros: ALT_SEM, + * ALT_EXTERN_SEM, and ALT_STATIC_SEM. In these three cases the semi-colon is + * included in the macro definition; so, for example, you should use: + * + * ALT_SEM(mysem) + * + * not: + * + * ALT_SEM(mysem); + * + * The inclusion of the semi-colon has been necessary to ensure the macros can + * compile with no warnings when used in a single threaded HAL environment. + * + */ + +#include "priv/alt_no_error.h" + +#define ALT_SEM(sem) +#define ALT_EXTERN_SEM(sem) +#define ALT_STATIC_SEM(sem) + +#define ALT_SEM_CREATE(sem, value) alt_no_error () +#define ALT_SEM_PEND(sem, timeout) alt_no_error () +#define ALT_SEM_POST(sem) alt_no_error () + +#ifndef ALT_SINGLE_THREADED +#define ALT_SINGLE_THREADED +#endif + +#endif /* __ALT_SEM_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/os/alt_syscall.h b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_syscall.h new file mode 100644 index 0000000..2b1165a --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/os/alt_syscall.h @@ -0,0 +1,75 @@ +#ifndef __ALT_SYSCALL_H__ +#define __ALT_SYSCALL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The macros defined in this file are used to provide the function names used + * for the HAL 'UNIX style' interface, e.g. read(), write() etc. + * + * Operating systems which are ported to the HAL can provide their own + * version of this file, which will be used in preference. This allows + * the operating system to provide it's own implementation of the top level + * system calls, while retaining the HAL functions under a different name, + * for example, alt_read(), alt_write() etc. + */ + +#define ALT_CLOSE close +#define ALT_ENVIRON environ +#define ALT_EXECVE execve +#define ALT_EXIT _exit +#define ALT_FCNTL fcntl +#define ALT_FORK fork +#define ALT_FSTAT fstat +#define ALT_GETPID getpid +#define ALT_GETTIMEOFDAY gettimeofday +#define ALT_IOCTL ioctl +#define ALT_ISATTY isatty +#define ALT_KILL kill +#define ALT_LINK link +#define ALT_LSEEK lseek +#define ALT_OPEN open +#define ALT_READ read +#define ALT_RENAME _rename +#define ALT_SBRK sbrk +#define ALT_SETTIMEOFDAY settimeofday +#define ALT_STAT stat +#define ALT_UNLINK unlink +#define ALT_USLEEP usleep +#define ALT_WAIT wait +#define ALT_WRITE write +#define ALT_TIMES times + +/* + * + */ + +#endif /* __ALT_SYSCALL_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_alarm.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_alarm.h new file mode 100644 index 0000000..ae687bb --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_alarm.h @@ -0,0 +1,101 @@ +#ifndef __ALT_PRIV_ALARM_H__ +#define __ALT_PRIV_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required by the public + * interface alt_alarm.h. These variables and structures are not guaranteed to + * exist in future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm_s" is a structure type used to maintain lists of alarm callback + * functions. + */ + +struct alt_alarm_s +{ + alt_llist llist; /* linked list */ + alt_u32 time; /* time in system ticks of the callback */ + alt_u32 (*callback) (void* context); /* callback function. The return + * value is the period for the next callback; where + * zero indicates that the alarm should be removed + * from the list. + */ + alt_u8 rollover; /* set when desired alarm time + current time causes + overflow, to prevent premature alarm */ + void* context; /* Argument for the callback */ +}; + +/* + * "_alt_tick_rate" is a global variable used to store the system clock rate + * in ticks per second. This is initialised to zero, which coresponds to there + * being no system clock available. + * + * It is then set to it's final value by the system clock driver through a call + * to alt_sysclk_init(). + */ + +extern alt_u32 _alt_tick_rate; + +/* + * "_alt_nticks" is a global variable which records the elapsed number of + * system clock ticks since the last call to settimeofday() or since reset if + * settimeofday() has not been called. + */ + +extern volatile alt_u32 _alt_nticks; + +/* The list of registered alarms. */ + +extern alt_llist alt_alarm_list; + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_PRIV_ALARM_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_busy_sleep.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_busy_sleep.h new file mode 100644 index 0000000..a165e93 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_busy_sleep.h @@ -0,0 +1,35 @@ +#ifndef __ALT_BUSY_SLEEP_H +#define __ALT_BUSY_SLEEP_H + +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * The function alt_busy_sleep provides a busy loop implementation of usleep. + * This is used to provide usleep for the standalone HAL, or when the timer is + * unavailable in uC/OS-II. + */ + +extern unsigned int alt_busy_sleep (unsigned int us); + +#endif /* __ALT_BUSY_SLEEP_H */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_dev_llist.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_dev_llist.h new file mode 100644 index 0000000..0ab7a28 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_dev_llist.h @@ -0,0 +1,77 @@ +#ifndef __ALT_DEV_LLIST_H__ +#define __ALT_DEV_LLIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_llist.h" +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The alt_dev_llist is an internal structure used to form a common base + * class for all device types. The use of this structure allows common code + * to be used to manipulate the various device lists. + */ + +typedef struct { + alt_llist llist; + const char* name; +} alt_dev_llist; + +/* + * + */ + +extern int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_LLIST_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_exception_handler_registry.h new file mode 100644 index 0000000..4502ea7 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_exception_handler_registry.h @@ -0,0 +1,39 @@ +#ifndef __ALT_EXCEPTION_HANDLER_REGISTRY_H__ +#define __ALT_EXCEPTION_HANDLER_REGISTRY_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "sys/alt_exceptions.h" + +/* Function pointer to exception callback routine */ +extern alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32); + +#endif /* __ALT_EXCEPTION_HANDLER_REGISTRY_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_file.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_file.h new file mode 100644 index 0000000..94007a6 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_file.h @@ -0,0 +1,179 @@ +#ifndef __ALT_FILE_H__ +#define __ALT_FILE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "sys/alt_llist.h" +#include "os/alt_sem.h" + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_find_dev() is used to search the device list "list" to + * locate a device named "name". If a match is found, then a pointer to the + * device is returned, otherwise NULL is returned. + */ + +extern alt_dev* alt_find_dev (const char* name, alt_llist* list); + +/* + * alt_find_file() is used to search the list of registered file systems to + * find the filesystem that the file named "name" belongs to. If a match is + * found, then a pointer to the filesystems alt_dev structure is returned, + * otherwise NULL is returned. + * + * Note that a match does not indicate that the file exists, only that a + * filesystem exists that is registered for a partition that could contain + * the file. The filesystems open() function would need to be called in order + * to determine if the file exists. + */ + +extern alt_dev* alt_find_file (const char* name); + +/* + * alt_get_fd() is used to allocate a file descriptor for the device or + * filesystem "dev". A negative return value indicates an error, otherwise the + * return value is the index of the file descriptor within the file descriptor + * pool. + */ + +extern int alt_get_fd (alt_dev* dev); + +/* + * alt_release_fd() is called to free the file descriptor with index "fd". + */ + +extern void alt_release_fd (int fd); + +/* + * alt_fd_lock() is called by ioctl() to mark the file descriptor "fd" as + * being open for exclusive access. Subsequent calls to open() for the device + * associated with "fd" will fail. A device is unlocked by either calling + * close() for "fd", or by an alternate call to ioctl() (see ioctl.c for + * details). + */ + +extern int alt_fd_lock (alt_fd* fd); + +/* + * alt_fd_unlock() is called by ioctl() to unlock a descriptor previously + * locked by a call to alt_fd_lock(). + */ + +extern int alt_fd_unlock (alt_fd* fd); + +/* + * "alt_fd_list" is the pool of file descriptors. + */ + +extern alt_fd alt_fd_list[]; + +/* + * flags used by alt_fd. + * + * ALT_FD_EXCL is used to mark a file descriptor as locked for exclusive + * access, i.e. further calls to open() for the associated device should + * fail. + * + * ALT_FD_DEV marks a dile descriptor as belonging to a device as oposed to a + * filesystem. + */ + +#define ALT_FD_EXCL 0x80000000 +#define ALT_FD_DEV 0x40000000 + +#define ALT_FD_FLAGS_MASK (ALT_FD_EXCL | ALT_FD_DEV) + +/* + * "alt_dev_list" is the head of the linked list of registered devices. + */ + +extern alt_llist alt_dev_list; + +/* + * "alt_fs_list" is the head of the linked list of registered filesystems. + */ + +extern alt_llist alt_fs_list; + +/* + * "alt_fd_list_lock" is a semaphore used to ensure that access to the pool + * of file descriptors is thread safe. + */ + +ALT_EXTERN_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is a 'high water mark'. It indicates the highest file + * descriptor allocated. Use of this can save searching the entire pool + * for active file descriptors, which helps avoid contention on access + * to the file descriptor pool. + */ + +extern alt_32 alt_max_fd; + +/* + * alt_io_redirect() is called at startup to redirect stdout, stdin, and + * stderr to the devices named in the input arguments. By default these streams + * are directed at /dev/null, and are then redirected using this function once + * all of the devices have been registered within the system. + */ + +extern void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FILE_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_iic_isr_register.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_iic_isr_register.h new file mode 100644 index 0000000..6c53c86 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_iic_isr_register.h @@ -0,0 +1,39 @@ +#ifndef __ALT_IIC_ISR_REGISTER_H_ +#define __ALT_IIC_ISR_REGISTER_H_ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "sys/alt_irq.h" + +extern int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags); + +#endif /* __ALT_IIC_ISR_REGISTER_H_ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_irq_table.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_irq_table.h new file mode 100644 index 0000000..5b4a787 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_irq_table.h @@ -0,0 +1,59 @@ +#ifndef __ALT_IRQ_TABLE_H__ +#define __ALT_IRQ_TABLE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definition of a table describing each interrupt handler. The index into + * the array is the interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + * + * The table is physically created in alt_irq_handler.c + */ +extern struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +#endif diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_legacy_irq.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_legacy_irq.h new file mode 100644 index 0000000..0e19af2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_legacy_irq.h @@ -0,0 +1,158 @@ +#ifndef __ALT_LEGACY_IRQ_H__ +#define __ALT_LEGACY_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides prototypes and inline implementations of certain routines + * used by the legacy interrupt API. Do not include this in your driver or + * application source files, use "sys/alt_irq.h" instead to access the proper + * public API. + */ + +#include +#include "system.h" + +#ifndef NIOS2_EIC_PRESENT + +#include "nios2.h" +#include "alt_types.h" + +#include "sys/alt_irq.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_irq_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler); + +/* + * alt_irq_disable() disables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active &= ~(1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +/* + * alt_irq_enable() enables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active |= (1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +#ifndef ALT_EXCEPTION_STACK +/* + * alt_irq_initerruptable() should only be called from within an ISR. It is used + * to allow higer priority interrupts to interrupt the current ISR. The input + * argument, "priority", is the priority, i.e. interrupt number of the current + * interrupt. + * + * If this function is called, then the ISR is required to make a call to + * alt_irq_non_interruptible() before returning. The input argument to + * alt_irq_non_interruptible() is the return value from alt_irq_interruptible(). + * + * Care should be taken when using this pair of functions, since they increasing + * the system overhead associated with interrupt handling. + * + * If you are using an exception stack then nested interrupts won't work, so + * these functions are not available in that case. + */ +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_interruptible (alt_u32 priority) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + alt_u32 old_priority; + + old_priority = alt_priority_mask; + alt_priority_mask = (1 << priority) - 1; + + NIOS2_WRITE_IENABLE (alt_irq_active & alt_priority_mask); + + NIOS2_WRITE_STATUS (1); + + return old_priority; +} + +/* + * See Comments above for alt_irq_interruptible() for an explanation of the use of this + * function. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE alt_irq_non_interruptible (alt_u32 mask) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + NIOS2_WRITE_STATUS (0); + + alt_priority_mask = mask; + + NIOS2_WRITE_IENABLE (mask & alt_irq_active); +} +#endif /* ALT_EXCEPTION_STACK */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NIOS2_EIC_PRESENT */ + +#endif /* __ALT_LEGACY_IRQ_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_no_error.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_no_error.h new file mode 100644 index 0000000..06a036c --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/alt_no_error.h @@ -0,0 +1,77 @@ +#ifndef __ALT_NO_ERROR_H__ +#define __ALT_NO_ERROR_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_no_error() is a dummy function used by alt_sem.h and alt_flag.h. It + * substitutes for functions that have a return code by creating a function + * that always returns zero. + * + * This may seem a little obscure, but what happens is that the compiler can + * then optomise away the call to this function, and any code written which + * handles the error path (i.e. non zero return values). + * + * This allows code to be written which correctly use the uC/OS-II semaphore + * and flag utilities, without the use of those utilities impacting on + * excutables built for a single threaded HAL environment. + * + * This function is considered to be part of the internal implementation of + * the HAL, and should not be called directly by application code or device + * drivers. It is not guaranteed to be preserved in future versions of the + * HAL. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void) +{ + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_NO_ERROR_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/priv/nios2_gmon_data.h b/software/DE2_115_ASM_bsp/HAL/inc/priv/nios2_gmon_data.h new file mode 100644 index 0000000..4bc058d --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/priv/nios2_gmon_data.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#ifndef NIOS2_GMON_DATA_H +#define NIOS2_GMON_DATA_H + +#define GMON_DATA_SIG 0 +#define GMON_DATA_WORDS 1 +#define GMON_DATA_PROFILE_DATA 2 +#define GMON_DATA_PROFILE_LOWPC 3 +#define GMON_DATA_PROFILE_HIGHPC 4 +#define GMON_DATA_PROFILE_BUCKET 5 +#define GMON_DATA_PROFILE_RATE 6 +#define GMON_DATA_MCOUNT_START 7 +#define GMON_DATA_MCOUNT_LIMIT 8 + +#define GMON_DATA_SIZE 9 + +extern unsigned int alt_gmon_data[GMON_DATA_SIZE]; + +#endif diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_alarm.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_alarm.h new file mode 100644 index 0000000..9093080 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_alarm.h @@ -0,0 +1,126 @@ +#ifndef __ALT_ALARM_H__ +#define __ALT_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_llist.h" +#include "alt_types.h" + +#include "priv/alt_alarm.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm" is a structure type used by applications to register an alarm + * callback function. An instance of this type must be passed as an input + * argument to alt_alarm_start(). The user is not responsible for initialising + * the contents of the instance. This is done by alt_alarm_start(). + */ + +typedef struct alt_alarm_s alt_alarm; + +/* + * alt_alarm_start() can be called by an application/driver in order to register + * a function for periodic callback at the system clock frequency. Be aware that + * this callback is likely to occur in interrupt context. + */ + +extern int alt_alarm_start (alt_alarm* the_alarm, + alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context); + +/* + * alt_alarm_stop() is used to unregister a callback. Alternatively the callback + * can return zero to unregister. + */ + +extern void alt_alarm_stop (alt_alarm* the_alarm); + +/* + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; +} + +/* + * alt_sysclk_init() is intended to be only used by the system clock driver + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + { + _alt_tick_rate = nticks; + return 0; + } + else + { + return -1; + } +} + +/* + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; +} + +/* + * alt_tick() should only be called by the system clock driver. This is used + * to notify the system that the system timer period has expired. + */ + +extern void alt_tick (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_ALARM_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_cache.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_cache.h new file mode 100644 index 0000000..44d976c --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_cache.h @@ -0,0 +1,117 @@ +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "alt_types.h" + +/* + * alt_cache.h defines the processor specific functions for manipulating the + * cache. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +extern void alt_icache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are written back to memory. + */ + +extern void alt_dcache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are NOT written back to memory. + */ + +extern void alt_dcache_flush_no_writeback (void* start, alt_u32 len); + +/* + * Flush the entire instruction cache. + */ + +extern void alt_icache_flush_all (void); + +/* + * Flush the entire data cache. + */ + +extern void alt_dcache_flush_all (void); + +/* + * Allocate a block of uncached memory. + */ + +extern volatile void* alt_uncached_malloc (size_t size); + +/* + * Free a block of uncached memory. + */ + +extern void alt_uncached_free (volatile void* ptr); + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +extern volatile void* alt_remap_uncached (void* ptr, alt_u32 len); + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +extern void* alt_remap_cached (volatile void* ptr, alt_u32 len); + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_debug.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_debug.h new file mode 100644 index 0000000..af509d8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_debug.h @@ -0,0 +1,45 @@ +#ifndef __ALT_DEBUG_H__ +#define __ALT_DEBUG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The ALT_DEVUG_ASSERT macro can be used to generate a debugger break + * from within software. The break is generated if "condition" evaluates to + * false. + */ + +#define ALT_DEBUG_ASSERT(condition) if (!condition) \ +{ \ + __asm__ volatile ("break"); \ +} + +#endif /* __ALT_DEBUG_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dev.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dev.h new file mode 100644 index 0000000..d96327e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dev.h @@ -0,0 +1,115 @@ +#ifndef __ALT_DEV_H__ +#define __ALT_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "system.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The value ALT_IRQ_NOT_CONNECTED is used to represent an unconnected + * interrupt line. It cannot evaluate to a valid interrupt number. + */ + +#define ALT_IRQ_NOT_CONNECTED (-1) + +typedef struct alt_dev_s alt_dev; + +struct stat; + +/* + * The file descriptor structure definition. + */ + +typedef struct alt_fd_s +{ + alt_dev* dev; + alt_u8* priv; + int fd_flags; +} alt_fd; + +/* + * The device structure definition. + */ + +struct alt_dev_s { + alt_llist llist; /* for internal use */ + const char* name; + int (*open) (alt_fd* fd, const char* name, int flags, int mode); + int (*close) (alt_fd* fd); + int (*read) (alt_fd* fd, char* ptr, int len); + int (*write) (alt_fd* fd, const char* ptr, int len); + int (*lseek) (alt_fd* fd, int ptr, int dir); + int (*fstat) (alt_fd* fd, struct stat* buf); + int (*ioctl) (alt_fd* fd, int req, void* arg); +}; + +/* + * Functions used to register device for access through the C standard + * library. + * + * The only difference between alt_dev_reg() and alt_fs_reg() is the + * interpretation that open() places on the device name. In the case of + * alt_dev_reg the device is assumed to be a particular character device, + * and so there must be an exact match in the name for open to succeed. + * In the case of alt_fs_reg() the name of the device is treated as the + * mount point for a directory, and so any call to open() where the name + * is the root of the device filename will succeed. + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dma.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dma.h new file mode 100644 index 0000000..88dcda0 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dma.h @@ -0,0 +1,226 @@ +#ifndef __ALT_DMA_H__ +#define __ALT_DMA_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dma_dev.h" +#include "alt_types.h" + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the application side interface for accessing DMA + * resources. See alt_dma_dev.h for the dma device driver interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * The application can supply data for transmit using an "alt_dma_txchan" + * descriptor. Alternatively an "alt_dma_rxchan" descriptor can be used to + * receive data. + */ + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_txchan alt_dma_txchan_open (const char* name); + +/* + * alt_dma_txchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA transmit channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_txchan_close (alt_dma_txchan dma) +{ + return 0; +} + +/* + * alt_dma_txchan_send() posts a transmit request to a DMA transmit channel. + * The input arguments are: + * + * dma: the channel to use. + * from: a pointer to the start of the data to send. + * length: the length of the data to send in bytes. + * done: callback function that will be called once the data has been sent. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_txchan_send (alt_dma_txchan dma, + const void* from, + alt_u32 length, + alt_txchan_done* done, + void* handle) +{ + return dma ? dma->dma_send (dma, + from, + length, + done, + handle) : -ENODEV; +} + +/* + * alt_dma_txchan_space() returns the number of tranmit requests that can be + * posted to the specified DMA transmit channel. + * + * A negative value indicates that the value could not be determined. + */ + +static ALT_INLINE int alt_dma_txchan_space (alt_dma_txchan dma) +{ + return dma ? dma->space (dma) : -ENODEV; +} + +/* + * alt_dma_txchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA transmit channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_txchan_ioctl (alt_dma_txchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_open() is used to obtain an "alt_dma_rxchan" descriptor for + * a DMA receive channel. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_rxchan alt_dma_rxchan_open (const char* dev); + +/* + * alt_dma_rxchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA receive channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_rxchan_close (alt_dma_rxchan dma) +{ + return 0; +} + +/* + * + */ + +/* + * alt_dma_rxchan_prepare() posts a receive request to a DMA receive channel. + * + * The input arguments are: + * + * dma: the channel to use. + * data: a pointer to the location that data is to be received to. + * len: the maximum length of the data to receive. + * done: callback function that will be called once the data has been + * received. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_rxchan_prepare (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle) +{ + return dma ? dma->prepare (dma, data, len, done, handle) : -ENODEV; +} + +/* + * alt_dma_rxchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA receive channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_rxchan_ioctl (alt_dma_rxchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_depth() returns the depth of the receive FIFO used to store + * receive requests. + */ + +static ALT_INLINE alt_u32 alt_dma_rxchan_depth(alt_dma_rxchan dma) +{ + return dma->depth; +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dma_dev.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dma_dev.h new file mode 100644 index 0000000..65063bd --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_dma_dev.h @@ -0,0 +1,200 @@ +#ifndef __ALT_DMA_DEV_H__ +#define __ALT_DMA_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the device driver interface for accessing DMA + * resources. See alt_dma.h for the DMA application side interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * An "alt_dma_txchan_dev" is used to describe the device associated with a + * DMA transmit channel. An "alt_dma_rxchan_dev" is used to describe the + * device associated with a DMA receive channel. + */ + +/* + * List of generic ioctl requests that may be supported by a DMA device. + * + * ALT_DMA_RX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the receiver is under software control. + * The other side reads continously from a single + * location. The address to read is the argument to + * this request. + * ALT_DMA_RX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_TX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the transmitter is under software control. + * The other side writes continously to a single + * location. The address to write to is the argument to + * this request. + * ALT_DMA_TX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_SET_MODE_8: Transfer data in units of 8 bits. + * ALT_DMA_SET_MODE_16: Transfer data in units of 16 bits. + * ALT_DMA_SET_MODE_32: Transfer data in units of 32 bits. + * ALT_DMA_SET_MODE_64: Transfer data in units of 64 bits. + * ALT_DMA_SET_MODE_128: Transfer data in units of 128 bits. + * ALT_DMA_GET_MODE: Get the current transfer mode. + * + * The use of the macros: ALT_DMA_TX_STREAM_ON, ALT_DMA_TX_STREAM_OFF + * ALT_DMA_RX_STREAM_OFF and ALT_DMA_RX_STREAM_ON are depreciated. You should + * instead use the macros: ALT_DMA_RX_ONLY_ON, ALT_DMA_RX_ONLY_OFF, + * ALT_DMA_TX_ONLY_ON and ALT_DMA_TX_ONLY_OFF. + */ + +#define ALT_DMA_TX_STREAM_ON (0x1) +#define ALT_DMA_TX_STREAM_OFF (0x2) +#define ALT_DMA_RX_STREAM_ON (0x3) +#define ALT_DMA_RX_STREAM_OFF (0x4) +#define ALT_DMA_SET_MODE_8 (0x5) +#define ALT_DMA_SET_MODE_16 (0x6) +#define ALT_DMA_SET_MODE_32 (0x7) +#define ALT_DMA_SET_MODE_64 (0x8) +#define ALT_DMA_SET_MODE_128 (0x9) +#define ALT_DMA_GET_MODE (0xa) + +#define ALT_DMA_RX_ONLY_ON ALT_DMA_TX_STREAM_ON +#define ALT_DMA_RX_ONLY_OFF ALT_DMA_TX_STREAM_OFF +#define ALT_DMA_TX_ONLY_ON ALT_DMA_RX_STREAM_ON +#define ALT_DMA_TX_ONLY_OFF ALT_DMA_RX_STREAM_OFF + +/* + * + */ + +typedef struct alt_dma_txchan_dev_s alt_dma_txchan_dev; +typedef struct alt_dma_rxchan_dev_s alt_dma_rxchan_dev; + +typedef alt_dma_txchan_dev* alt_dma_txchan; +typedef alt_dma_rxchan_dev* alt_dma_rxchan; + +typedef void (alt_txchan_done)(void* handle); +typedef void (alt_rxchan_done)(void* handle, void* data); + +/* + * devices that provide a DMA transmit channel are required to provide an + * instance of the "alt_dma_txchan_dev" structure. + */ + +struct alt_dma_txchan_dev_s { + alt_llist llist; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + int (*space) (alt_dma_txchan dma); /* returns the maximum number of + * transmit requests that can be posted + */ + int (*dma_send) (alt_dma_txchan dma, + const void* from, + alt_u32 len, + alt_txchan_done* done, + void* handle); /* post a transmit request */ + int (*ioctl) (alt_dma_txchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * devices that provide a DMA receive channel are required to provide an + * instance of the "alt_dma_rxchan_dev" structure. + */ + +struct alt_dma_rxchan_dev_s { + alt_llist list; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + alt_u32 depth; /* maximum number of receive requests that + * can be posted. + */ + int (*prepare) (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle); /* post a receive request */ + int (*ioctl) (alt_dma_rxchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * Register a DMA transmit channel with the system. + */ + +static ALT_INLINE int alt_dma_txchan_reg (alt_dma_txchan_dev* dev) +{ + extern alt_llist alt_dma_txchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_txchan_list); +} + +/* + * Register a DMA receive channel with the system. + */ + +static ALT_INLINE int alt_dma_rxchan_reg (alt_dma_rxchan_dev* dev) +{ + extern alt_llist alt_dma_rxchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_rxchan_list); +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_DEV_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_driver.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_driver.h new file mode 100644 index 0000000..ca7aea1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_driver.h @@ -0,0 +1,168 @@ +#ifndef __ALT_DRIVER_H__ +#define __ALT_DRIVER_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Macros used to access a driver without HAL file descriptors. + */ + +/* + * ALT_MODULE_CLASS + * + * This macro returns the module class name for the specified module instance. + * It uses information in the system.h file. + * Neither the instance name or class name are quoted (so that they can + * be used with other pre-processor macros). + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_MODULE_CLASS(uart1) returns altera_avalon_uart. + */ + +#define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance + + +/* + * ALT_DRIVER_FUNC_NAME + * + * --> instance Instance name. + * --> func Function name. + * + * This macro returns the device driver function name of the specified + * module instance for the specified function name. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_FUNC_NAME(uart1, write) returns + * altera_avalon_uart_write. + */ + +#define ALT_DRIVER_FUNC_NAME(instance, func) \ + ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) +#define ALT_DRIVER_FUNC_NAME1(module_class, func) \ + ALT_DRIVER_FUNC_NAME2(module_class, func) +#define ALT_DRIVER_FUNC_NAME2(module_class, func) \ + module_class ## _ ## func + +/* + * ALT_DRIVER_STATE_STRUCT + * + * --> instance Instance name. + * + * This macro returns the device driver state type name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE_STRUCT(uart1) returns: + * struct altera_avalon_uart_state_s + * + * Note that the ALT_DRIVER_FUNC_NAME macro is used even though "state" isn't + * really a function but it does match the required naming convention. + */ +#define ALT_DRIVER_STATE_STRUCT(instance) \ + struct ALT_DRIVER_FUNC_NAME(instance, state_s) + +/* + * ALT_DRIVER_STATE + * + * --> instance Instance name. + * + * This macro returns the device driver state name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE(uart1) returns uart1. + */ +#define ALT_DRIVER_STATE(instance) instance + +/* + * ALT_DRIVER_WRITE + * + * --> instance Instance name. + * --> buffer Write buffer. + * --> len Length of write buffer data. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "write" function of the specified driver instance. + */ + +#define ALT_DRIVER_WRITE_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, write) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_WRITE(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, write)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + + +/* + * ALT_DRIVER_READ + * + * --> instance Instance name. + * <-- buffer Read buffer. + * --> len Length of read buffer. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "read" function of the specified driver instance. + */ + +#define ALT_DRIVER_READ_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, read) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_READ(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, read)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + +/* + * ALT_DRIVER_IOCTL + * + * --> instance Instance name. + * --> req ioctl request (e.g. TIOCSTIMEOUT) + * --> arg Optional argument (void*) + * + * This macro calls the "ioctl" function of the specified driver instance + */ + +#define ALT_DRIVER_IOCTL_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, ioctl) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, int, void*); + +#define ALT_DRIVER_IOCTL(instance, req, arg) \ + ALT_DRIVER_FUNC_NAME(instance, ioctl)(&ALT_DRIVER_STATE(instance), req, arg) + +#endif /* __ALT_DRIVER_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_errno.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_errno.h new file mode 100644 index 0000000..23e3096 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_errno.h @@ -0,0 +1,87 @@ +#ifndef __ALT_ERRNO_H__ +#define __ALT_ERRNO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * errno is defined in so that it uses the thread local version + * stored in the location pointed to by "_impure_ptr". This means that the + * accesses to errno within the HAL library can cause the entirety of + * of the structure pointed to by "_impure_ptr" to be added to the + * users application. This can be undesirable in very small footprint systems. + * + * To avoid this happening, the HAL uses the macro ALT_ERRNO, defined below, + * to access errno, rather than accessing it directly. This macro will only + * use the thread local version if some other code has already caused it to be + * included into the system, otherwise it will use the global errno value. + * + * This causes a slight increases in code size where errno is accessed, but + * can lead to significant overall benefits in very small systems. The + * increase is inconsequential when compared to the size of the structure + * pointed to by _impure_ptr. + * + * Note that this macro accesses __errno() using an externally declared + * function pointer (alt_errno). This is done so that the function call uses the + * subroutine call instruction via a register rather than an immediate address. + * This is important in the case that the code has been linked for a high + * address, but __errno() is not being used. In this case the weak linkage + * would have resulted in the instruction: "call 0" which would fail to link. + */ + +extern int* (*alt_errno) (void); + +/* Must define this so that values such as EBADFD are defined in errno.h. */ +#define __LINUX_ERRNO_EXTENSIONS__ + +#include + +#include "alt_types.h" + +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + return ((alt_errno) ? alt_errno() : &errno); +} + +#define ALT_ERRNO *alt_get_errno() + +#endif /* __ALT_ERRNO_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_exceptions.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_exceptions.h new file mode 100644 index 0000000..b6b82e2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_exceptions.h @@ -0,0 +1,127 @@ +#ifndef __ALT_EXCEPTIONS_H__ +#define __ALT_EXCEPTIONS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This file defines instruction-generated exception handling and registry + * API, exception type enumeration, and handler return value enumeration for + * Nios II. + */ + +/* + * The following enumeration describes the value in the CPU EXCEPTION + * register CAUSE bit field. Not all exception types will cause the + * processor to go to the exception vector; these are provided for + * reference. + */ +enum alt_exception_cause_e { + /* Exeption causes that will cause jump to exception vector */ + NIOS2_EXCEPTION_INTERRUPT = 2, + NIOS2_EXCEPTION_TRAP_INST = 3, + NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4, + NIOS2_EXCEPTION_ILLEGAL_INST = 5, + NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6, + NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7, + NIOS2_EXCEPTION_DIVISION_ERROR = 8, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11, + NIOS2_EXCEPTION_TLB_MISS = 12, + NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13, + NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16, + + /* Exception causes that will NOT cause a jump to exception vector */ + NIOS2_EXCEPTION_RESET = 0, + NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1, + NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14, + NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15, + NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17, + /* + * This value is passed to an exception handler's cause argument if + * "extra exceptions" information (EXECPTION) register is not + * present in the processor hardware configuration. + */ + NIOS2_EXCEPTION_CAUSE_NOT_PRESENT = -1 +}; +typedef enum alt_exception_cause_e alt_exception_cause; + +/* + * These define valid return values for a user-defined instruction-generated + * exception handler. The handler should return one of these to indicate + * whether to re-issue the instruction that triggered the exception, or to + * skip it. + */ +enum alt_exception_result_e { + NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0, + NIOS2_EXCEPTION_RETURN_SKIP_INST = 1 +}; +typedef enum alt_exception_result_e alt_exception_result; + +/* + * alt_instruction_exception_register() can be used to register an exception + * handler for instruction-generated exceptions that are not handled by the + * built-in exception handler (i.e. for interrupts). + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ); +#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * alt_exception_cause_generated_bad_addr() indicates whether a particular + * exception cause value was from an exception-type that generated a valid + * address in the BADADDR register. The contents of BADADDR is passed to + * a user-registered exception handler in all cases, whether valid or not. + * This routine should be called to validate the bad_addr argument to + * your exception handler. + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_EXCEPTIONS_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash.h new file mode 100644 index 0000000..7e903a8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash.h @@ -0,0 +1,166 @@ +#ifndef __ALT_FLASH_H__ +#define __ALT_FLASH_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.h - User interface for flash code * +* * +* Use this interface to avoid being exposed to the internals of the device * +* driver architecture. If you chose to use the flash driver internal * +* structures we don't guarantee not to change them * +* * +* Author PRR * +* * +******************************************************************************/ + + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "alt_types.h" +#include "alt_flash_types.h" +#include "alt_flash_dev.h" +#include "sys/alt_cache.h" + +alt_flash_fd* alt_flash_open_dev(const char* name); +void alt_flash_close_dev(alt_flash_fd* fd ); + +/* + * alt_write_flash + * + * Program a buffer into flash. + * + * This routine erases all the affected erase blocks (if necessary) + * and then programs the data. However it does not read the data out first + * and preserve and none overwritten data, because this would require very + * large buffers on the target. If you need + * that functionality use the functions below. + */ +static __inline__ int __attribute__ ((always_inline)) alt_write_flash( + alt_flash_fd* fd, + int offset, + const void* src_addr, + int length ) +{ + return fd->write( fd, offset, src_addr, length ); +} + +/* + * alt_read_flash + * + * Read a block of flash for most flashes this is just memcpy + * it's here for completeness in case we need it for some serial flash device + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_read_flash( + alt_flash_fd* fd, int offset, + void* dest_addr, int length ) +{ + return fd->read( fd, offset, dest_addr, length ); +} + +/* + * alt_get_flash_info + * + * Return the information on the flash sectors. + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( + alt_flash_fd* fd, flash_region** info, + int* number_of_regions) +{ + return fd->get_info( fd, info, number_of_regions); +} + +/* + * alt_erase_flash_block + * + * Erase a particular erase block, pass in the offset to the start of + * the block and it's size + */ +static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block( + alt_flash_fd* fd, int offset, int length) +{ + int ret_code; + ret_code = fd->erase_block( fd, offset ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + offset, length); + + return ret_code; +} + +/* + * alt_write_flash_block + * + * Write a particular flash block, block_offset is the offset + * (from the base of flash) to start of the block + * data_offset is the offset (from the base of flash) + * where you wish to start programming + * + * NB this function DOES NOT check that you are only writing a single + * block of data as that would slow down this function. + * + * Use alt_write_flash if you want that level of error checking. + */ + +static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block( + alt_flash_fd* fd, int block_offset, + int data_offset, + const void *data, int length) +{ + + int ret_code; + ret_code = fd->write_block( fd, block_offset, data_offset, data, length ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length); + + return ret_code; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FLASH_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash_dev.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash_dev.h new file mode 100644 index 0000000..1c5692e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash_dev.h @@ -0,0 +1,98 @@ +#ifndef __ALT_FLASH_DEV_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_dev.h - Generic Flash device interfaces * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_DEV_H__ + +#include "alt_flash_types.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +typedef struct alt_flash_dev alt_flash_dev; +typedef alt_flash_dev alt_flash_fd; + +static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd) +{ + extern alt_llist alt_flash_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); +} + +typedef alt_flash_dev* (*alt_flash_open)(alt_flash_dev* flash, + const char* name ); +typedef int (*alt_flash_close)(alt_flash_dev* flash_info); + +typedef int (*alt_flash_write)( alt_flash_dev* flash, int offset, + const void* src_addr, int length ); + +typedef int (*alt_flash_get_flash_info)( alt_flash_dev* flash, flash_region** info, + int* number_of_regions); +typedef int (*alt_flash_write_block)( alt_flash_dev* flash, int block_offset, + int data_offset, const void* data, + int length); +typedef int (*alt_flash_erase_block)( alt_flash_dev* flash, int offset); +typedef int (*alt_flash_read)(alt_flash_dev* flash, int offset, + void* dest_addr, int length ); + +struct alt_flash_dev +{ + alt_llist llist; + const char* name; + alt_flash_open open; + alt_flash_close close; + alt_flash_write write; + alt_flash_read read; + alt_flash_get_flash_info get_info; + alt_flash_erase_block erase_block; + alt_flash_write_block write_block; + void* base_addr; + int length; + int number_of_regions; + flash_region region_info[ALT_MAX_NUMBER_OF_FLASH_REGIONS]; +}; + +#endif /* __ALT_FLASH_DEV_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash_types.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash_types.h new file mode 100644 index 0000000..10f1f01 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_flash_types.h @@ -0,0 +1,64 @@ +#ifndef __ALT_FLASH_TYPES_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_types.h - Some generic types and defines used by the flash code * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_TYPES_H__ + +#ifndef ALT_MAX_NUMBER_OF_FLASH_REGIONS +#define ALT_MAX_NUMBER_OF_FLASH_REGIONS 8 +#endif /* ALT_MAX_NUMBER_OF_FLASH_REGIONS */ + +/* + * Description of a single Erase region + */ +typedef struct flash_region +{ + int offset; + int region_size; + int number_of_blocks; + int block_size; +}flash_region; + +#endif /* __ALT_FLASH_TYPES_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_irq.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_irq.h new file mode 100644 index 0000000..96c010d --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_irq.h @@ -0,0 +1,245 @@ +#ifndef __ALT_IRQ_H__ +#define __ALT_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_irq.h is the Nios II specific implementation of the interrupt controller + * interface. + * + * Nios II includes optional support for an external interrupt controller. + * When an external controller is present, the "Enhanced" interrupt API + * must be used to manage individual interrupts. The enhanced API also + * supports the processor's internal interrupt controller. Certain API + * members are accessible from either the "legacy" or "enhanced" interrpt + * API. + * + * Regardless of which API is in use, this file should be included by + * application code and device drivers that register ISRs or manage interrpts. + */ +#include + +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros used by alt_irq_enabled + */ +#define ALT_IRQ_ENABLED 1 +#define ALT_IRQ_DISABLED 0 + +/* + * Number of available interrupts in internal interrupt controller. + */ +#define ALT_NIRQ NIOS2_NIRQ + +/* + * Used by alt_irq_disable_all() and alt_irq_enable_all(). + */ +typedef int alt_irq_context; + +/* ISR Prototype */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +typedef void (*alt_isr_func)(void* isr_context); +#else +typedef void (*alt_isr_func)(void* isr_context, alt_u32 id); +#endif + +/* + * The following protypes and routines are supported by both + * the enhanced and legacy interrupt APIs + */ + +/* + * alt_irq_enabled can be called to determine if the processor's global + * interrupt enable is asserted. The return value is zero if interrupts + * are disabled, and non-zero otherwise. + * + * Whether the internal or external interrupt controller is present, + * individual interrupts may still be disabled. Use the other API to query + * a specific interrupt. + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enabled (void) +{ + int status; + + NIOS2_READ_STATUS (status); + + return status & NIOS2_STATUS_PIE_MSK; +} + +/* + * alt_irq_disable_all() + * + * This routine inhibits all interrupts by negating the status register PIE + * bit. It returns the previous contents of the CPU status register (IRQ + * context) which can be used to restore the status register PIE bit to its + * state before this routine was called. + */ +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + + return context; +} + +/* + * alt_irq_enable_all() + * + * Enable all interrupts that were previously disabled by alt_irq_disable_all() + * + * This routine accepts a context to restore the CPU status register PIE bit + * to the state prior to a call to alt_irq_disable_all(). + + * In the case of nested calls to alt_irq_disable_all()/alt_irq_enable_all(), + * this means that alt_irq_enable_all() does not necessarily re-enable + * interrupts. + * + * This routine will perform a read-modify-write sequence to restore only + * status.PIE if the processor is configured with options that add additional + * writeable status register bits. These include the MMU, MPU, the enhanced + * interrupt controller port, and shadow registers. Otherwise, as a performance + * enhancement, status is overwritten with the prior context. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_enable_all (alt_irq_context context) +{ +#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || (defined NIOS2_EIC_PRESENT) || \ + (defined NIOS2_MMU_PRESENT) || (defined NIOS2_MPU_PRESENT) + alt_irq_context status; + + NIOS2_READ_STATUS (status); + + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); +#endif +} + +/* + * The function alt_irq_init() is defined within the auto-generated file + * alt_sys_init.c. This function calls the initilization macros for all + * interrupt controllers in the system at config time, before any other + * non-interrupt controller driver is initialized. + * + * The "base" parameter is ignored and only present for backwards-compatibility. + * It is recommended that NULL is passed in for the "base" parameter. + */ +extern void alt_irq_init (const void* base); + +/* + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK +#if defined(NIOS2_EIC_PRESENT) && (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) + | NIOS2_STATUS_RSIE_MSK +#endif + ); +} + + +/* + * Prototypes for the enhanced interrupt API. + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +/* + * alt_ic_isr_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_ic_isr_register(alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void *isr_context, + void *flags); + +/* + * alt_ic_irq_enable() and alt_ic_irq_disable() enable/disable a specific + * interrupt by using IRQ port and interrupt controller instance. + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq); +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq); + + /* + * alt_ic_irq_enabled() indicates whether a specific interrupt, as + * specified by IRQ port and interrupt controller instance is enabled. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq); + +#else +/* + * Prototypes for the legacy interrupt API. + */ +#include "priv/alt_legacy_irq.h" +#endif + + +/* + * alt_irq_pending() returns a bit list of the current pending interrupts. + * This is used by alt_irq_handler() to determine which registered interrupt + * handlers should be called. + * + * This routine is only available for the Nios II internal interrupt + * controller. + */ +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + + return active; +} +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_IRQ_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_irq_entry.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_irq_entry.h new file mode 100644 index 0000000..549811c --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_irq_entry.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file pulls in the IRQ entry assembler and C code, which is only + * required if there are any interruptes in the system. + */ + +__asm__( "\n\t.globl alt_irq_entry" ); + +__asm__( "\n\t.globl alt_irq_handler" ); + diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h new file mode 100644 index 0000000..1d1f16f --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h @@ -0,0 +1,77 @@ +#ifndef __ALT_LICENSE_REMINDER_UCOSII_H__ +#define __ALT_LICENSE_REMINDER_UCOSII_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include + +#define ALT_LICENSE_REMINDER_UCOSII_STRING \ + "============== Software License Reminder ===============\n" \ + "\n" \ + "uC/OS-II is provided in source form for FREE evaluation,\n" \ + "for educational use, or for peaceful research. If you\n" \ + "plan on using uC/OS-II in a commercial product you need\n" \ + "to contact Micrium to properly license its use in your\n" \ + "product. Micrium provides ALL the source code on the\n" \ + "Altera distribution for your convenience and to help you\n" \ + "experience uC/OS-II. The fact that the source is provided\n" \ + "does NOT mean that you can use it without paying a\n" \ + "licensing fee. Please help us continue to provide the\n" \ + "Embedded community with the finest software available.\n" \ + "Your honesty is greatly appreciated.\n" \ + "\n" \ + "Please contact:\n" \ + "\n" \ + "M I C R I U M\n" \ + "949 Crestview Circle\n" \ + "Weston, FL 33327-1848\n" \ + "U.S.A.\n" \ + "\n" \ + "Phone : +1 954 217 2036\n" \ + "FAX : +1 954 217 2037\n" \ + "WEB : www.micrium.com\n" \ + "E-mail: Sales@Micrium.com\n" \ + "\n" \ + "========================================================\n" + +#define alt_license_reminder_ucosii() puts(ALT_LICENSE_REMINDER_UCOSII_STRING) + + +#endif /* __ALT_LICENSE_REMINDER_UCOSII_H__ */ + diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_llist.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_llist.h new file mode 100644 index 0000000..84cb051 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_llist.h @@ -0,0 +1,123 @@ +#ifndef __ALT_LIST_H__ +#define __ALT_LIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * alt_llist.h defines structures and functions for use in manipulating linked + * lists. A list is considered to be constructed from a chain of objects of + * type alt_llist, with one object being defined to be the head element. + * + * A list is considered to be empty if it only contains the head element. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_llist is the structure used to represent an element within a linked + * list. + */ + +typedef struct alt_llist_s alt_llist; + +struct alt_llist_s { + alt_llist* next; /* Pointer to the next element in the list. */ + alt_llist* previous; /* Pointer to the previous element in the list. */ +}; + +/* + * ALT_LLIST_HEAD is a macro that can be used to create the head of a new + * linked list. This is named "head". The head element is initialised to + * represent an empty list. + */ + +#define ALT_LLIST_HEAD(head) alt_llist head = {&head, &head} + +/* + * ALT_LLIST_ENTRY is a macro used to define an uninitialised linked list + * entry. This is used to reserve space in structure initialisation for + * structures that inherit form alt_llist. + */ + +#define ALT_LLIST_ENTRY {0, 0} + +/* + * alt_llist_insert() insert adds the linked list entry "entry" as the + * first entry in the linked list "list". "list" is the list head element. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + entry->next = list->next; + + list->next->previous = entry; + list->next = entry; +} + +/* + * alt_llist_remove() is called to remove an element from a linked list. The + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + entry->previous->next = entry->next; + + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + entry->next = entry; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_LLIST_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_load.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_load.h new file mode 100644 index 0000000..e4c4c46 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_load.h @@ -0,0 +1,78 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This macro is used to load code/data from its load address to its + * execution address for a given section. The section name is the input + * argument. Note that a leading '.' is assumed in the name. For example + * to load the section .onchip_ram, use: + * + * ALT_LOAD_SECTION_BY_NAME(onchip_ram); + * + * This requires that the apropriate linker symbols have been generated + * for the section in question. This will be the case if you are using the + * default linker script. + */ + +#define ALT_LOAD_SECTION_BY_NAME(name) \ + { \ + extern void _alt_partition_##name##_start; \ + extern void _alt_partition_##name##_end; \ + extern void _alt_partition_##name##_load_addr; \ + \ + alt_load_section(&_alt_partition_##name##_load_addr, \ + &_alt_partition_##name##_start, \ + &_alt_partition_##name##_end); \ + } + +/* + * Function used to load an individual section from flash to RAM. + * + * There is an implicit assumption here that the linker script will ensure + * that all sections are word aligned. + * + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + { + *to++ = *from++; + } + } +} diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_log_printf.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_log_printf.h new file mode 100644 index 0000000..9890091 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_log_printf.h @@ -0,0 +1,349 @@ +/* alt_log_printf.h + * + * ALT_LOG is designed to provide extra logging/debugging messages from HAL + * through a different port than stdout. It is enabled by the ALT_LOG_ENABLE + * define, which needs to supplied at compile time. When logging is turned off, + * code size is unaffected. Thus, this should be transparent to the user + * when it is not actively turned on, and should not affect projects in any way. + * + * There are macros sprinkled within different components, such as the jtag uart + * and timer, in the HAL code. They are always named ALT_LOG_, and can be + * safely ignored if ALT_LOG is turned off. + * + * To turn on ALT_LOG, ALT_LOG_ENABLE must be defined, and ALT_LOG_PORT_TYPE and + * ALT_LOG_PORT_BASE must be set in system.h. This is done through editing + * .ptf, by editing the alt_log_port_type & alt_log_port_base settings. + * See the documentation html file for examples. + * + * When it is turned on, it will output extra HAL messages to a port specified + * in system.h. This can be a UART or JTAG UART port. By default it will + * output boot messages, detailing every step of the boot process. + * + * Extra logging is designed to be enabled by flags, which are defined in + * alt_log_printf.c. The default value is that all flags are off, so only the + * boot up logging messages show up. ALT_LOG_FLAGS can be set to enable certain + * groupings of flags, and that grouping is done in this file. Each flag can + * also be overridden with a -D at compile time. + * + * This header file includes the necessary prototypes for using the alt_log + * functions. It also contains all the macros that are used to remove the code + * from alt log is turned off. Also, the macros in other HAL files are defined + * here at the bottom. These macros all call some C function that is in + * alt_log_printf.c. + * + * The logging has functions for printing in C (ALT_LOG_PRINTF) and in assembly + * (ALT_LOG_PUTS). This was needed because the assembly printing occurs before + * the device is initialized. The assembly function corrupts register R4-R7, + * which are not used in the normal boot process. For this reason, do not call + * the assembly function in C. + * + * author: gkwan + */ + + +#ifndef __ALT_LOG_PRINTF_H__ +#define __ALT_LOG_PRINTF_H__ + +#include + +/* Global switch to turn on logging functions */ +#ifdef ALT_LOG_ENABLE + + /* ALT_LOG_PORT_TYPE values as defined in system.h. They are defined as + * numbers here first becasue the C preprocessor does not handle string + * comparisons. */ + #define ALTERA_AVALON_JTAG_UART 1 + #define ALTERA_AVALON_UART 0 + + /* If this .h file is included by an assembly file, skip over include files + * that won't compile in assembly. */ + #ifndef ALT_ASM_SRC + #include + #include "sys/alt_alarm.h" + #include "sys/alt_dev.h" + #ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #endif + #endif /* ALT_ASM_SRC */ + + /* These are included for the port register offsets and masks, needed + * to write to the port. Only include if the port type is set correctly, + * otherwise error. If alt_log is turned on and the port to output to is + * incorrect or does not exist, then should exit. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #ifdef __ALTERA_AVALON_JTAG_UART + #include + #else + #error ALT_LOG: JTAG_UART port chosen, but no JTAG_UART in system. + #endif + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #ifdef __ALTERA_AVALON_UART + #include + #else + #error ALT_LOG: UART Port chosen, but no UART in system. + #endif + #else + #error ALT_LOG: alt_log_port_type declaration invalid! + #endif + + /* ALT_LOG_ENABLE turns on the basic printing function */ + #define ALT_LOG_PRINTF(...) do {alt_log_printf_proc(__VA_ARGS__);} while (0) + + /* Assembly macro for printing in assembly, calls tx_log_str + * which is in alt_log_macro.S. + * If alt_log_boot_on_flag is 0, skips the printing */ + #define ALT_LOG_PUTS(str) movhi r4, %hiadj(alt_log_boot_on_flag) ; \ + addi r4, r4, %lo(alt_log_boot_on_flag) ; \ + ldwio r5, 0(r4) ; \ + beq r0, r5, 0f ; \ + movhi r4, %hiadj(str) ; \ + addi r4, r4, %lo(str) ; \ + call tx_log_str ; \ + 0: + + /* These defines are here to faciliate the use of one output function + * (alt_log_txchar) to print to both the JTAG UART or the UART. Depending + * on the port type, the status register, read mask, and output register + * are set to the appropriate value for the port. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_JTAG_UART_CONTROL + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_JTAG_UART_DATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_JTAG_UART_CONTROL_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_JTAG_UART_DATA_REG*0x4) + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_UART_STATUS + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_UART_STATUS_TRDY_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_UART_TXDATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_UART_STATUS_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_UART_TXDATA_REG*0x4) + #endif /* ALT_LOG_PORT */ + + /* Grouping of flags via ALT_LOG_FLAGS. Each specific flag can be set via + * -D at compile time, or else they'll be set to a default value according + * to ALT_LOG_FLAGS. ALT_LOG_FLAGS = 0 or not set is the default, where + * only the boot messages will be printed. As ALT_LOG_FLAGS increase, they + * increase in intrusiveness to the program, and will affect performance. + * + * Flag Level 1 - turns on system clock and JTAG UART startup status + * 2 - turns on write echo and JTAG_UART alarm (periodic report) + * 3 - turns on JTAG UART ISR logging - will slow performance + * significantly. + * -1 - All logging output is off, but if ALT_LOG_ENABLE is + * defined all logging function is built and code size + * remains constant + * + * Flag settings - 1 = on, 0 = off. */ + + /* This flag turns on "boot" messages for printing. This includes messages + * during crt0.S, then alt_main, and finally alt_exit. */ + #ifndef ALT_LOG_BOOT_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #endif + #endif /* ALT_LOG_BOOT_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_SYS_CLK_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_SYS_CLK_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_WRITE_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_WRITE_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_STARTUP_INFO_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING */ + +#ifndef ALT_ASM_SRC + /* Function Prototypes */ + void alt_log_txchar(int c,char *uartBase); + void alt_log_private_printf(const char *fmt,int base,va_list args); + void alt_log_repchar(char c,int r,int base); + int alt_log_printf_proc(const char *fmt, ... ); + void alt_log_system_clock(); + #ifdef __ALTERA_AVALON_JTAG_UART + alt_u32 altera_avalon_jtag_uart_report_log(void * context); + void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base); + void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, \ + int base, const char* header); + void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev); + #endif + void alt_log_write(const void *ptr, size_t len); + + /* extern all global variables */ + extern volatile alt_u32 alt_log_boot_on_flag; + extern volatile alt_u8 alt_log_write_on_flag; + extern volatile alt_u8 alt_log_sys_clk_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_isr_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag; + extern volatile int alt_log_sys_clk_count; + extern volatile int alt_system_clock_in_sec; + extern alt_alarm alt_log_jtag_uart_alarm_1; +#endif /* ALT_ASM_SRC */ + + + /* Below are the MACRO defines used in various HAL files. They check + * if their specific flag is turned on; if it is, then it executes its + * code. + * + * To keep this file reasonable, most of these macros calls functions, + * which are defined in alt_log_printf.c. Look there for implementation + * details. */ + + /* Boot Messages Logging */ + #define ALT_LOG_PRINT_BOOT(...) \ + do { if (alt_log_boot_on_flag==1) {ALT_LOG_PRINTF(__VA_ARGS__);} \ + } while (0) + + /* JTAG UART Logging */ + /* number of ticks before alarm runs logging function */ + #ifndef ALT_LOG_JTAG_UART_TICKS_DIVISOR + #define ALT_LOG_JTAG_UART_TICKS_DIVISOR 10 + #endif + #ifndef ALT_LOG_JTAG_UART_TICKS + #define ALT_LOG_JTAG_UART_TICKS \ + (alt_ticks_per_second()/ALT_LOG_JTAG_UART_TICKS_DIVISOR) + #endif + + /* if there's a JTAG UART defined, then enable these macros */ + #ifdef __ALTERA_AVALON_JTAG_UART + + /* Macro in altera_avalon_jtag_uart.c, to register the alarm function. + * Also, the startup register info is also printed here, as this is + * called within the device driver initialization. */ + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) \ + do { if (alt_log_jtag_uart_alarm_on_flag==1) { \ + alt_alarm_start(&alt_log_jtag_uart_alarm_1, \ + ALT_LOG_JTAG_UART_TICKS, &altera_avalon_jtag_uart_report_log,\ + dev);} \ + if (alt_log_jtag_uart_startup_info_on_flag==1) {\ + alt_log_jtag_uart_startup_info(dev, base);} \ + } while (0) + + /* JTAG UART IRQ Logging (when buffer is empty) + * Inserted in the ISR in altera_avalon_jtag_uart.c */ + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) \ + do { alt_log_jtag_uart_isr_proc(base, dev); } while (0) + /* else, define macros to nothing. Or else the jtag_uart specific types + * will throw compiler errors */ + #else + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #endif + + /* System clock logging + * How often (in seconds) the system clock logging prints. + * The default value is every 1 second */ + #ifndef ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER + #define ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER 1 + #endif + #ifndef ALT_LOG_SYS_CLK_INTERVAL + #define ALT_LOG_SYS_CLK_INTERVAL \ + (alt_ticks_per_second()*ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER) + #endif + + /* System clock logging - prints a message every interval (set above) + * to show that the system clock is alive. + * This macro is used in altera_avalon_timer_sc.c */ + #define ALT_LOG_SYS_CLK_HEARTBEAT() \ + do { alt_log_system_clock(); } while (0) + + /* alt_write_logging - echos a message every time write() is called, + * displays the first ALT_LOG_WRITE_ECHO_LEN characters. + * This macro is used in alt_write.c */ + #ifndef ALT_LOG_WRITE_ECHO_LEN + #define ALT_LOG_WRITE_ECHO_LEN 15 + #endif + + #define ALT_LOG_WRITE_FUNCTION(ptr,len) \ + do { alt_log_write(ptr,len); } while (0) + +#else /* ALT_LOG_ENABLE not defined */ + + /* logging is off, set all relevant macros to null */ + #define ALT_LOG_PRINT_BOOT(...) + #define ALT_LOG_PRINTF(...) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_SYS_CLK_HEARTBEAT() + #define ALT_LOG_PUTS(str) + #define ALT_LOG_WRITE_FUNCTION(ptr,len) + +#endif /* ALT_LOG_ENABLE */ + +#endif /* __ALT_LOG_PRINTF_H__ */ + diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_set_args.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_set_args.h new file mode 100644 index 0000000..a9372c5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_set_args.h @@ -0,0 +1,71 @@ +#ifndef __ALT_SET_ARGS_H__ +#define __ALT_SET_ARGS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_set_args() is provided in order to define the input + * arguments to main(). If this function is not called before main() then the + * argument list passed to main() will be empty. + * + * It is expected that this function will only be used by the ihost/iclient + * utility. + */ + +static inline void alt_set_args (int argc, char** argv, char** envp) +{ + extern int alt_argc; + extern char** alt_argv; + extern char** alt_envp; + + alt_argc = argc; + alt_argv = argv; + alt_envp = envp; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SET_ARGS_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sim.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sim.h new file mode 100644 index 0000000..63afad9 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sim.h @@ -0,0 +1,91 @@ +#ifndef __ALT_SIM_H__ +#define __ALT_SIM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" +#include "alt_types.h" + +/* + * Instructions that might mean something special to a simulator. + * These have no special effect on real hardware (they are just nops). + */ +#define ALT_SIM_FAIL() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc1"); } while (0) + +#define ALT_SIM_PASS() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc2"); } while (0) + +#define ALT_SIM_IN_TOP_OF_HOT_LOOP() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc3"); } while (0) + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + int r2 = exit_code; + +#if defined(NIOS2_HAS_DEBUG_STUB) && (defined(ALT_BREAK_ON_EXIT) || defined(ALT_PROVIDE_GMON)) + + int r3 = (1 << 2); + +#ifdef ALT_PROVIDE_GMON + extern unsigned int alt_gmon_data[]; + int r4 = (int)alt_gmon_data; + r3 |= (1 << 4); +#define ALT_GMON_DATA ,"D04"(r4) +#else +#define ALT_GMON_DATA +#endif /* ALT_PROVIDE_GMON */ + + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } + + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } +#endif /* DEBUG_STUB */ +} + +#define ALT_SIM_HALT(exit_code) \ + alt_sim_halt(exit_code) + +#endif /* __ALT_SIM_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_stack.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_stack.h new file mode 100644 index 0000000..ebcad7a --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_stack.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_STACK_H__ +#define __ALT_STACK_H__ + +/* + * alt_stack.h is the nios2 specific implementation of functions used by the + * stack overflow code. + */ + +#include "nios2.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +extern char * alt_stack_limit_value; + +#ifdef ALT_EXCEPTION_STACK +extern char __alt_exception_stack_pointer[]; /* set by the linker */ +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_stack_limit can be called to determine the current value of the stack + * limit register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_limit (void) +{ + char * limit; + NIOS2_READ_ET(limit); + + return limit; +} + +/* + * alt_stack_pointer can be called to determine the current value of the stack + * pointer register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_pointer (void) +{ + char * pointer; + NIOS2_READ_SP(pointer); + + return pointer; +} + + +#ifdef ALT_EXCEPTION_STACK + +/* + * alt_exception_stack_pointer returns the normal stack pointer from + * where it is stored on the exception stack (uppermost 4 bytes). This + * is really only useful during exception processing, and is only + * available if a separate exception stack has been configured. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_exception_stack_pointer (void) +{ + return (char *) *(alt_u32 *)(__alt_exception_stack_pointer - sizeof(alt_u32)); +} + +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_set_stack_limit can be called to update the current value of the stack + * limit register. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_set_stack_limit (char * limit) +{ + alt_stack_limit_value = limit; + NIOS2_WRITE_ET(limit); +} + +/* + * alt_report_stack_overflow reports that a stack overflow happened. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_report_stack_overflow (void) +{ + NIOS2_REPORT_STACK_OVERFLOW(); +} + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_STACK_H__ */ + diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_stdio.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_stdio.h new file mode 100644 index 0000000..7ae05d4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_stdio.h @@ -0,0 +1,62 @@ +#ifndef __ALT_STDIO_H__ +#define __ALT_STDIO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definitions for ALT stdio routines. + */ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +int alt_getchar(); +int alt_putchar(int c); +int alt_putstr(const char* str); +void alt_printf(const char *fmt, ...); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_STDIO_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sys_init.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sys_init.h new file mode 100644 index 0000000..3b18059 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sys_init.h @@ -0,0 +1,62 @@ +#ifndef __ALT_SYS_INIT_H__ +#define __ALT_SYS_INIT_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_sys_init() is defined within the auto-generated file: + * alt_sys_init.c. This function calls the initilisation macros for all + * devices, file systems, and software components within the system. + * + * The list of initilisation macros to use is constructed using the PTF and + * STF files associated with the system. + */ + +extern void alt_sys_init (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SYS_INIT_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sys_wrappers.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sys_wrappers.h new file mode 100644 index 0000000..eea552d --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_sys_wrappers.h @@ -0,0 +1,100 @@ +#ifndef __ALT_SYS_WRAPPERS_H__ +#define __ALT_SYS_WRAPPERS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides the prototypes for the HAL 'UNIX style functions. The + * names of these functions are defined in alt_syscall.h. THese are defined to + * be the standard names when running the standalone HAL, e.g. open(), close() + * etc., but the names may be redefined as a part of an operating system port + * in order to avoid name clashes. + */ + +#include "os/alt_syscall.h" + +#include +#include +#include +#include +#include +#include + +extern int ALT_CLOSE (int __fd); +extern int ALT_EXECVE (const char *__path, + char * const __argv[], + char * const __envp[]); +extern void ALT_EXIT (int __status); +extern int ALT_FSTAT (int file, struct stat *st); +extern int ALT_FCNTL (int file, int cmd, ...); +extern pid_t ALT_FORK (void); +extern pid_t ALT_GETPID (void); + +#if defined (__GNUC__) && __GNUC__ >= 4 +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + void *ptimezone); +#else +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + struct timezone *ptimezone); +#endif + +extern int ALT_IOCTL (int file, int req, void* arg); +extern int ALT_ISATTY (int file); +extern int ALT_KILL (int pid, int sig); +extern int ALT_LINK (const char *existing, const char *new); +extern off_t ALT_LSEEK (int file, off_t ptr, int dir); +extern int ALT_OPEN (const char* file, int flags, ...); +extern int ALT_READ (int file, void *ptr, size_t len); +extern int ALT_RENAME (char *existing, char *new); +extern void* ALT_SBRK (ptrdiff_t incr); +extern int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz); +extern int ALT_STAT (const char *file, struct stat *st); +extern clock_t ALT_TIMES (struct tms *buf); +extern int ALT_UNLINK (const char *name); + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us); +#else +unsigned int ALT_USLEEP (unsigned int us); +#endif + +extern int ALT_WAIT (int *status); +extern int ALT_WRITE (int file, const void *ptr, size_t len); + + +extern char** ALT_ENVIRON; + +/* + * + */ + +#endif /* __ALT_SYS_WRAPPERS_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_timestamp.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_timestamp.h new file mode 100644 index 0000000..ec704ba --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_timestamp.h @@ -0,0 +1,60 @@ +#ifndef __ALT_TIMESTAMP_H__ +#define __ALT_TIMESTAMP_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "altera_avalon_timer.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +extern int alt_timestamp_start (void); + +extern alt_timestamp_type alt_timestamp (void); + +extern alt_u32 alt_timestamp_freq (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_TIMESTAMP_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_warning.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_warning.h new file mode 100644 index 0000000..01318bd --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/alt_warning.h @@ -0,0 +1,75 @@ +#ifndef __WARNING_H__ +#define __WARNING_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_warning.h provides macro definitions that can be used to generate link + * time warnings. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The symbol "__alt_invalid" is used to force a link error. There should be + * no corresponding implementation of this function. + */ + +extern void __alt_invalid (void); + +#define ALT_LINK_WARNING(symbol, msg) \ + __asm__(".ifndef __evoke_link_warning_" #symbol \ + "\n\t .section .gnu.warning." #symbol \ + "\n__evoke_link_warning_" #symbol ":\n\t .string \x22" msg "\x22 \n\t .previous" \ + "\n .endif"); + +/* A canned warning for sysdeps/stub functions. */ + +#define ALT_STUB_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is not implemented and will always fail") + +#define ALT_OBSOLETE_FUNCTION_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is a deprecated function") + +#define ALT_LINK_ERROR(msg) \ + ALT_LINK_WARNING (__alt_invalid, msg); \ + __alt_invalid() + +#ifdef __cplusplus +} +#endif + +#endif /* __WARNING_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/ioctl.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/ioctl.h new file mode 100644 index 0000000..453283b --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/ioctl.h @@ -0,0 +1,90 @@ +#ifndef __IOCTL_H__ +#define __IOCTL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The ioctl() system call be used to initiate a variety of control operations + * on a file descriptor. For the most part this simply translates to a call to + * the ioctl() function of the associated device driver (TIOCEXCL and + * TIOCNXCL are notable exceptions - see ioctl.c for details). + * + * The interpretation of the ioctl requests are therefore device specific. + * + * This function is equivalent to the standard Posix ioctl() call. + */ + +extern int ioctl (int fd, int req, void* arg); + +/* + * list of ioctl calls handled by the system ioctl implementation. + */ + +#define TIOCEXCL 0x740d /* exclusive use of the device */ +#define TIOCNXCL 0x740e /* allow multiple use of the device */ + +/* + * ioctl calls which can be handled by device drivers. + */ + +#define TIOCOUTQ 0x7472 /* get output queue size */ +#define TIOCMGET 0x741d /* get termios flags */ +#define TIOCMSET 0x741a /* set termios flags */ + +/* + * ioctl calls specific to JTAG UART. + */ + +#define TIOCSTIMEOUT 0x6a01 /* Set Timeout before assuming no host present */ +#define TIOCGCONNECTED 0x6a02 /* Get indication of whether host is connected */ + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IOCTL_H__ */ diff --git a/software/DE2_115_ASM_bsp/HAL/inc/sys/termios.h b/software/DE2_115_ASM_bsp/HAL/inc/sys/termios.h new file mode 100644 index 0000000..d271387 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/inc/sys/termios.h @@ -0,0 +1,181 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This is the termios.h file provided with newlib. The only modification has + * been to the baud rate macro definitions, and an increase in the size of the + * termios structure to accomodate this. + */ + + +#ifndef _SYS_TERMIOS_H +# define _SYS_TERMIOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +# define _XCGETA (('x'<<8)|1) +# define _XCSETA (('x'<<8)|2) +# define _XCSETAW (('x'<<8)|3) +# define _XCSETAF (('x'<<8)|4) +# define _TCSBRK (('T'<<8)|5) +# define _TCFLSH (('T'<<8)|7) +# define _TCXONC (('T'<<8)|6) + +# define TCOOFF 0 +# define TCOON 1 +# define TCIOFF 2 +# define TCION 3 + +# define TCIFLUSH 0 +# define TCOFLUSH 1 +# define TCIOFLUSH 2 + +# define NCCS 13 + +# define TCSAFLUSH _XCSETAF +# define TCSANOW _XCSETA +# define TCSADRAIN _XCSETAW +# define TCSADFLUSH _XCSETAF + +# define IGNBRK 000001 +# define BRKINT 000002 +# define IGNPAR 000004 +# define INPCK 000020 +# define ISTRIP 000040 +# define INLCR 000100 +# define IGNCR 000200 +# define ICRNL 000400 +# define IXON 002000 +# define IXOFF 010000 + +# define OPOST 000001 +# define OCRNL 000004 +# define ONLCR 000010 +# define ONOCR 000020 +# define TAB3 014000 + +# define CLOCAL 004000 +# define CREAD 000200 +# define CSIZE 000060 +# define CS5 0 +# define CS6 020 +# define CS7 040 +# define CS8 060 +# define CSTOPB 000100 +# define HUPCL 002000 +# define PARENB 000400 +# define PAODD 001000 + +#define CCTS_OFLOW 010000 +#define CRTS_IFLOW 020000 +#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) + +# define ECHO 0000010 +# define ECHOE 0000020 +# define ECHOK 0000040 +# define ECHONL 0000100 +# define ICANON 0000002 +# define IEXTEN 0000400 /* anybody know *what* this does?! */ +# define ISIG 0000001 +# define NOFLSH 0000200 +# define TOSTOP 0001000 + +# define VEOF 4 /* also VMIN -- thanks, AT&T */ +# define VEOL 5 /* also VTIME -- thanks again */ +# define VERASE 2 +# define VINTR 0 +# define VKILL 3 +# define VMIN 4 /* also VEOF */ +# define VQUIT 1 +# define VSUSP 10 +# define VTIME 5 /* also VEOL */ +# define VSTART 11 +# define VSTOP 12 + +# define B0 0 +# define B50 50 +# define B75 75 +# define B110 110 +# define B134 134 +# define B150 150 +# define B200 200 +# define B300 300 +# define B600 600 +# define B1200 1200 +# define B1800 1800 +# define B2400 2400 +# define B4800 4800 +# define B9600 9600 +# define B19200 19200 +# define B38400 38400 +# define B57600 57600 +# define B115200 115200 + +typedef unsigned char cc_t; +typedef unsigned short tcflag_t; +typedef unsigned long speed_t; + +struct termios { + tcflag_t c_iflag; + tcflag_t c_oflag; + tcflag_t c_cflag; + tcflag_t c_lflag; + char c_line; + cc_t c_cc[NCCS]; + speed_t c_ispeed; + speed_t c_ospeed; +}; + +# ifndef _NO_MACROS + +# define cfgetospeed(tp) ((tp)->c_ospeed) +# define cfgetispeed(tp) ((tp)->c_ispeed) +# define cfsetospeed(tp,s) (((tp)->c_ospeed = (s)), 0) +# define cfsetispeed(tp,s) (((tp)->c_ispeed = (s)), 0) +# define tcdrain(fd) _ioctl (fd, _TCSBRK, 1) +# endif /* _NO_MACROS */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_TERMIOS_H */ + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_alarm_start.c b/software/DE2_115_ASM_bsp/HAL/src/alt_alarm_start.c new file mode 100644 index 0000000..2bd672f --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_alarm_start.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_irq.h" + +/* + * alt_alarm_start is called to register an alarm with the system. The + * "alarm" structure passed as an input argument does not need to be + * initialised by the user. This is done within this function. + * + * The remaining input arguments are: + * + * nticks - The time to elapse until the alarm executes. This is specified in + * system clock ticks. + * callback - The function to run when the indicated time has elapsed. + * context - An opaque value, passed to the callback function. +* + * Care should be taken when defining the callback function since it is + * likely to execute in interrupt context. In particular, this mean that + * library calls like printf() should not be made, since they can result in + * deadlock. + * + * The interval to be used for the next callback is the return + * value from the callback function. A return value of zero indicates that the + * alarm should be unregistered. + * + * alt_alarm_start() will fail if the timer facility has not been enabled + * (i.e. there is no system clock). Failure is indicated by a negative return + * value. + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + + if (alt_ticks_per_second ()) + { + if (alarm) + { + alarm->callback = callback; + alarm->context = context; + + irq_context = alt_irq_disable_all (); + + current_nticks = alt_nticks(); + + alarm->time = nticks + current_nticks + 1; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + { + alarm->rollover = 1; + } + else + { + alarm->rollover = 0; + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + alt_irq_enable_all (irq_context); + + return 0; + } + else + { + return -EINVAL; + } + } + else + { + return -ENOTSUP; + } +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_busy_sleep.c b/software/DE2_115_ASM_bsp/HAL/src/alt_busy_sleep.c new file mode 100644 index 0000000..1b910a5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_busy_sleep.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + * + * alt_busy_sleep.c - Microsecond delay routine which uses a calibrated busy + * loop to perform the delay. This is used to implement + * usleep for both uC/OS-II and the standalone HAL. + * + * Author PRR + * + * Calibrated delay with no timer required + * + * The ASM instructions in the routine are equivalent to + * + * for (i=0;i +#include + +#include "system.h" +#include "alt_types.h" + +#include "priv/alt_busy_sleep.h" + +unsigned int alt_busy_sleep (unsigned int us) +{ +/* + * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software + * is built targetting ModelSim RTL simulation, the delay will be + * skipped to speed up simulation. + */ +#ifndef ALT_SIM_OPTIMIZE + int i; + int big_loops; + alt_u32 cycles_per_loop; + + if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) + { + cycles_per_loop = 9; + } + else + { + cycles_per_loop = 3; + } + + + big_loops = us / (INT_MAX/ + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + + if (big_loops) + { + for(i=0;i + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_CLOSE (int fildes) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(close); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * close() is called by an application to release a file descriptor. If the + * associated file system/device has a close() callback function registered + * then this called. The file descriptor is then marked as free. + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + + if (fd) + { + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + if (rval < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return 0; + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush.c b/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush.c new file mode 100644 index 0000000..8afe062 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * Nios II version 1.2 and newer supports the "flush by address" instruction, in + * addition to the "flush by line" instruction provided by older versions of + * the core. This newer instruction is used by preference when it is + * available. + */ + +#ifdef NIOS2_FLUSHDA_SUPPORTED +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i)); +#else +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushd (%0)" :: "r" (i)); +#endif /* NIOS2_FLUSHDA_SUPPORTED */ + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are written back to memory. + */ + +void alt_dcache_flush (void* start, alt_u32 len) +{ +#if NIOS2_DCACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + * + * SPR 196942, 2006.01.13: The cache flush loop below will use the + * 'flushda' instruction if its available; in that case each line + * must be flushed individually, and thus 'len' cannot be trimmed. + */ + #ifndef NIOS2_FLUSHDA_SUPPORTED + if (len > NIOS2_DCACHE_SIZE) + { + len = NIOS2_DCACHE_SIZE; + } + #endif + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA(i); + } + +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush_all.c b/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush_all.c new file mode 100644 index 0000000..80735b7 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush_all.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush_no_writeback.c b/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush_no_writeback.c new file mode 100644 index 0000000..3b277d2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_dcache_flush_no_writeback.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * The INITDA instruction was added to Nios II in the 8.0 release. + * + * The INITDA instruction has one of the following possible behaviors + * depending on the processor configuration: + * 1) Flushes a line by address but does NOT write back dirty data. + * Occurs when a data cache is present that supports INITDA. + * The macro NIOS2_INITDA_SUPPORTED is defined in system.h. + * 2) Takes an unimplemented instruction exception. + * Occurs when a data cache is present that doesn't support INITDA. + * 3) Performs no operation + * Occurs when there is no data cache present. + * The macro NIOS2_DCACHE_SIZE is 0 in system.h. + */ + +#define ALT_FLUSH_DATA_NO_WRITEBACK(i) \ + __asm__ volatile ("initda (%0)" :: "r" (i)); + +/* + * alt_dcache_flush_no_writeback() is called to flush the data cache for a + * memory region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are NOT written back to memory. + * Make sure you really want this behavior. If you aren't 100% sure, + * use the alt_dcache_flush() routine instead. + */ + +void alt_dcache_flush_no_writeback (void* start, alt_u32 len) +{ +#if defined(NIOS2_INITDA_SUPPORTED) + + char* i; + char* end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + +#endif /* NIOS2_INITDA_SUPPORTED */ +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_dev.c b/software/DE2_115_ASM_bsp/HAL/src/alt_dev.c new file mode 100644 index 0000000..92f3f2a --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_dev.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * This file contains the data constructs used to control access to device and + * filesytems. + */ + +/* + * "alt_fs_list" is the head of a linked list of registered filesystems. It is + * initialised as an empty list. New entries can be added using the + * alt_fs_reg() function. + */ + +ALT_LLIST_HEAD(alt_fs_list); + + +/* + * "alt_dev_list" is the head of a linked list of registered devices. It is + * configured at startup to include a single device, "alt_dev_null". This + * device is discussed below. + */ + +extern alt_dev alt_dev_null; /* forward declaration */ + +alt_llist alt_dev_list = {&alt_dev_null.llist, &alt_dev_null.llist}; + +/* + * alt_dev_null_write() is the implementation of the write() function used + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + return len; +} + +/* + * "alt_dev_null" is used to allow output to be redirected to nowhere. It is + * the only device registered before the call to alt_sys_init(). At startup + * stin, stdout & stderr are all directed towards this device so that library + * calls like printf() will be safe but inefectual. + */ + +alt_dev alt_dev_null = { + { + &alt_dev_list, + &alt_dev_list + }, + "/dev/null", + NULL, /* open */ + NULL, /* close */ + NULL, /* write */ + alt_dev_null_write, /* write */ + NULL, /* lseek */ + NULL, /* fstat */ + NULL /* ioctl */ + }; + +/* + * "alt_fd_list_lock" is a semaphore used to control access to the file + * descriptor list. This is used to ensure that access to the list is thread + * safe. + */ + +ALT_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is used to make access to the file descriptor list more + * efficent. It is set to be the value of the highest allocated file + * descriptor. This saves having to search the entire pool of unallocated + * file descriptors when looking for a match. + */ + +alt_32 alt_max_fd = -1; + +/* + * "alt_fd_list" is the file descriptor pool. The first three entries in the + * array are configured as standard in, standard out, and standard error. These + * are all initialised so that accesses are directed to the alt_dev_null + * device. The remaining file descriptors are initialised as unallocated. + * + * The maximum number of file descriptors within the system is specified by the + * user defined macro "ALT_MAX_FD". This is defined in "system.h", which is + * auto-genereated using the projects PTF and STF files. + */ + +alt_fd alt_fd_list[ALT_MAX_FD] = + { + { + &alt_dev_null, /* standard in */ + 0, + 0 + }, + { + &alt_dev_null, /* standard out */ + 0, + 0 + }, + { + &alt_dev_null, /* standard error */ + 0, + 0 + } + /* all other elements are set to zero */ + }; diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_dev_llist_insert.c b/software/DE2_115_ASM_bsp/HAL/src/alt_dev_llist_insert.c new file mode 100644 index 0000000..5e8a952 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_dev_llist_insert.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" +#include "sys/alt_errno.h" + +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + { + ALT_ERRNO = EINVAL; + return -EINVAL; + } + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + + return 0; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_dma_rxchan_open.c b/software/DE2_115_ASM_bsp/HAL/src/alt_dma_rxchan_open.c new file mode 100644 index 0000000..5d461d9 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_dma_rxchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered DMA receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_rxchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_rxchan alt_dma_rxchan_open (const char* name) +{ + alt_dma_rxchan dev; + + dev = (alt_dma_rxchan) alt_find_dev (name, &alt_dma_rxchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_dma_txchan_open.c b/software/DE2_115_ASM_bsp/HAL/src/alt_dma_txchan_open.c new file mode 100644 index 0000000..99f9181 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_dma_txchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_txchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_txchan alt_dma_txchan_open (const char* name) +{ + alt_dma_txchan dev; + + dev = (alt_dma_txchan) alt_find_dev (name, &alt_dma_txchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_do_ctors.c b/software/DE2_115_ASM_bsp/HAL/src/alt_do_ctors.c new file mode 100644 index 0000000..be1c134 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_do_ctors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*constructor) (void); +extern constructor __CTOR_LIST__[]; +extern constructor __CTOR_END__[]; + +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + (*ctor) (); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_do_dtors.c b/software/DE2_115_ASM_bsp/HAL/src/alt_do_dtors.c new file mode 100644 index 0000000..b61166a --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_do_dtors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*destructor) (void); +extern destructor __DTOR_LIST__[]; +extern destructor __DTOR_END__[]; + +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + (*dtor) (); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_env_lock.c b/software/DE2_115_ASM_bsp/HAL/src/alt_env_lock.c new file mode 100644 index 0000000..0c5d522 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_env_lock.c @@ -0,0 +1,53 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +/* + * These are the empty env lock/unlock stubs required by newlib. These are + * used to make accesses to environment variables thread safe. The default HAL + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that environment variables are never manipulated by an interrupt + * service routine. + */ + +void __env_lock ( struct _reent *_r ) +{ +} + +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_environ.c b/software/DE2_115_ASM_bsp/HAL/src/alt_environ.c new file mode 100644 index 0000000..780635a --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_environ.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * These are the environment variables passed to the C code. By default there + * are no variables registered. An application can manipulate this list using + * getenv() and setenv(). + */ + +char *__env[1] = { 0 }; +char **ALT_ENVIRON = __env; diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_errno.c b/software/DE2_115_ASM_bsp/HAL/src/alt_errno.c new file mode 100644 index 0000000..4c5ca3e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_errno.c @@ -0,0 +1,44 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file defines the alt_errno global variable. See comments in + * alt_errno.h for the use of this variable. + */ + + +#include "sys/alt_errno.h" +#include "alt_types.h" + +extern int ALT_WEAK *__errno (void); + +int* (*alt_errno) (void) = __errno; diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_exception_entry.S b/software/DE2_115_ASM_bsp/HAL/src/alt_exception_entry.S new file mode 100644 index 0000000..486465b --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_exception_entry.S @@ -0,0 +1,360 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the exception entry point code, which saves all the caller saved + * registers and then handles the appropriate exception. It should be pulled + * in using a .globl from all the exception handler routines. This scheme is + * used so that if an interrupt is never registered, then this code will not + * appear in the generated executable, thereby improving code footprint. + * + * If an external interrpt controller (EIC) is present, it will supply an + * interrupt vector address to the processor when an interrupt occurs. For + * The Altera Vectored Interrupt Controller (VIC) driver will establish a + * vector table and the processor will jump directly to the appropriate + * table entry, funnel routine, and then user ISR. This will bypass this code + * in entirety. This code might still be linked into a system with an EIC, + * but would then be used only for non-interrupt exceptions. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + + /* + * The top and bottom of the exception stack + */ +#ifdef ALT_EXCEPTION_STACK + + .globl __alt_exception_stack_pointer + +#ifdef ALT_STACK_CHECK + + .globl __alt_exception_stack_limit + + /* + * We need to store the value of the stack limit after interrupt somewhere. + */ + .globl alt_exception_old_stack_limit + +#endif +#endif + + .section .exceptions.entry.label, "xa" + + .globl alt_exception + .type alt_exception, @function +alt_exception: + + .section .exceptions.entry, "xa" + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + movhi et, %hiadj(__alt_exception_stack_pointer - 80) + addi et, et, %lo(__alt_exception_stack_pointer - 80) + stw sp, 76(et) + mov sp, et + +#ifdef ALT_STACK_CHECK + movhi et, %hiadj(__alt_exception_stack_limit) + addi et, et, %lo(__alt_exception_stack_limit) + stw et, %gprel(alt_stack_limit_value)(gp) +#endif + +#else + /* + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + +#ifdef ALT_STACK_CHECK + + bltu sp, et, .Lstack_overflow + +#endif + +#endif + + stw ra, 0(sp) + + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + stw r2, 12(sp) + stw r3, 16(sp) + stw r4, 20(sp) + stw r5, 24(sp) + stw r6, 28(sp) + stw r7, 32(sp) + + rdctl r5, estatus + + stw r8, 36(sp) + stw r9, 40(sp) + stw r10, 44(sp) + stw r11, 48(sp) + stw r12, 52(sp) + stw r13, 56(sp) + stw r14, 60(sp) + stw r15, 64(sp) + + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + + /* + * The interrupt testing code (.exceptions.irqtest) will be + * linked here. If the Internal Interrupt Controller (IIC) is + * present (an EIC is not present), the presense of an interrupt + * is determined by examining CPU control registers or an interrupt + * custom instruction, if present. + * + * If the IIC is used and an interrupt is active, the code linked + * here will call the HAL IRQ handler (alt_irq_handler()) which + * successively calls registered interrupt handler(s) until no + * interrupts remain pending. It then jumps to .exceptions.exit. If + * there is no interrupt then it continues to .exception.notirq, below. + */ + + .section .exceptions.notirq, "xa" + + /* + * Prepare to service unimplemtned instructions or traps, + * each of which is optionally inked into section .exceptions.soft, + * which will preceed .exceptions.unknown below. + * + * Unlike interrupts, we want to skip the exception-causing instructon + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + ldw r2, -4(ea) /* Instruction that caused exception */ + + /* + * Other exception handling code, if enabled, will be linked here. + * This includes unimplemted (multiply/divide) instruction support + * (a BSP generaton option), and a trap handler (that would typically + * be augmented with user-specific code). These are not linked in by + * default. + */ + + /* + * In the context of linker sections, "unknown" are all exceptions + * not handled by the built-in handlers above (interupt, and trap or + * unimplemented instruction decoding, if enabled). + * + * Advanced exception types can be serviced by registering a handler. + * To do so, enable the "Enable Instruction-related Exception API" HAL + * BSP setting. If this setting is disabled, this handler code will + * either break (if the debug core is present) or enter an infinite + * loop because we don't how how to handle the exception. + */ + .section .exceptions.unknown +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + /* + * The C-based HAL routine alt_instruction_exception_entry() will + * attempt to service the exception by calling a user-registered + * exception handler using alt_instruction_exception_register(). + * If no handler was registered it will either break (if the + * debugger is present) or go into an infinite loop since the + * handling behavior is undefined; in that case we will not return here. + */ + + /* Load exception-causing address as first argument (r4) */ + addi r4, ea, -4 + + /* Call the instruction-exception entry */ + call alt_instruction_exception_entry + + /* + * If alt_instruction_exception_entry() returned, the exception was + * serviced by a user-registered routine. Its return code (now in r2) + * indicates whether to re-issue or skip the exception-causing + * instruction + * + * Return code was 0: Skip. The instruction after the exception is + * already stored in 72(sp). + */ + bne r2, r0, .Lexception_exit + + /* + * Otherwise, modify 72(sp) to re-issue the instruction that caused the + * exception. + */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + +#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */ + + /* + * We got here because an instruction-related exception occured, but the + * handler API was not compiled in. We do not presume to know how to + * handle it. If the debugger is present, break, otherwise hang. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious + * interrupts) + */ +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break +#else + /* + * If there is no debug stub then a BREAK will probably cause a reboot. + * An infinate loop will probably be more useful. + */ +0: + br 0b +#endif /* NIOS2_HAS_DEBUG_STUB */ + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + + .section .exceptions.exit.label +.Lexception_exit: + + .section .exceptions.exit, "xa" + + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + ldw ra, 0(sp) + + wrctl estatus, r5 + + ldw r1, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + +#ifdef ALT_EXCEPTION_STACK +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_stack_limit_value)(gp) + stw zero, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + +#endif + + /* + * Return to the interrupted instruction. + */ + + eret + +#ifdef ALT_STACK_CHECK + +.Lstack_overflow: + break 3 + +#endif + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_exception_muldiv.S b/software/DE2_115_ASM_bsp/HAL/src/alt_exception_muldiv.S new file mode 100644 index 0000000..6a794a3 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_exception_muldiv.S @@ -0,0 +1,583 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the software multiply/divide handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_muldiv +alt_exception_muldiv: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + + .section .exceptions.soft, "xa" + + + /* INSTRUCTION EMULATION + * --------------------- + * + * Nios II processors generate exceptions for unimplemented instructions. + * The routines below emulate these instructions. Depending on the + * processor core, the only instructions that might need to be emulated + * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu. + * + * The emulations match the instructions, except for the following + * limitations: + * + * 1) The emulation routines do not emulate the use of the exception + * temporary register (et) as a source operand because the exception + * handler already has modified it. + * + * 2) The routines do not emulate the use of the stack pointer (sp) or the + * exception return address register (ea) as a destination because + * modifying these registers crashes the exception handler or the + * interrupted routine. + * + * 3) To save code size, the routines do not emulate the use of the + * breakpoint registers (ba and bt) as operands. + * + * Detailed Design + * --------------- + * + * The emulation routines expect the contents of integer registers r0-r31 + * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The + * routines retrieve source operands from the stack and modify the + * destination register's value on the stack prior to the end of the + * exception handler. Then all registers except the destination register + * are restored to their previous values. + * + * The instruction that causes the exception is found at address -4(ea). + * The instruction's OP and OPX fields identify the operation to be + * performed. + * + * One instruction, muli, is an I-type instruction that is identified by + * an OP field of 0x24. + * + * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24- + * 27 22 6 0 <-- LSB of field + * + * The remaining emulated instructions are R-type and have an OP field + * of 0x3a. Their OPX fields identify them. + * + * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a- + * 27 22 17 11 6 0 <-- LSB of field + * + * + */ + + + /* + * Split the instruction into its fields. We need 4*A, 4*B, and 4*C as + * offsets to the stack pointer for access to the stored register values. + */ + /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */ + roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */ + roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */ + roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */ + srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */ + xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */ + roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */ + andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */ + xori r3, r3, 0x40 + andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */ + andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */ + andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */ + + /* Now either + * r5 = OP + * r3 = 4*(A^16) + * r4 = IMM16 (sign extended) + * r6 = 4*(B^16) + * r7 = 4*(C^16) + * or + * r5 = OP + */ + + + /* + * Save everything on the stack to make it easy for the emulation routines + * to retrieve the source register operands. The exception entry code has + * already saved some of this so we don't need to do it all again. + */ + + addi sp, sp, -60 + stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */ + /* Register at and r2-r15 have already been saved. */ + + stw r16, 0(sp) + stw r17, 4(sp) + stw r18, 8(sp) + stw r19, 12(sp) + stw r20, 16(sp) + stw r21, 20(sp) + stw r22, 24(sp) + stw r23, 28(sp) + /* et @ 32 - Has already been changed.*/ + /* bt @ 36 - Usually isn't an operand. */ + stw gp, 40(sp) + stw sp, 44(sp) + stw fp, 48(sp) + /* ea @ 52 - Don't bother to save - it's already been changed */ + /* ba @ 56 - Breakpoint register usually isn't an operand */ + /* ra @ 60 - Has already been saved */ + + + /* + * Prepare for either multiplication or division loop. + * They both loop 32 times. + */ + movi r14, 32 + + + /* + * Get the operands. + * + * It is necessary to check for muli because it uses an I-type instruction + * format, while the other instructions are have an R-type format. + */ + add r3, r3, sp /* r3 = address of A-operand. */ + ldw r3, 0(r3) /* r3 = A-operand. */ + movi r15, 0x24 /* muli opcode (I-type instruction format) */ + beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */ + + add r6, r6, sp /* r6 = address of B-operand. */ + ldw r6, 0(r6) /* r6 = B-operand. */ + /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */ + /* IMM16 not needed, align OPX portion */ + /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */ + srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */ + andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */ + + /* Now + * r5 = OP + * r3 = src1 + * r6 = src2 + * r4 = OPX (no longer can be muli) + * r7 = 4*(C^16) + * r14 = loop counter + */ + + /* ILLEGAL-INSTRUCTION EXCEPTION + * ----------------------------- + * + * This code is for Nios II cores that generate exceptions when attempting + * to execute illegal instructions. Nios II cores that support an + * illegal-instruction exception are identified by the presence of the + * macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h . + * + * Remember that illegal instructions are different than unimplemented + * instructions. Illegal instructions are instruction encodings that + * have not been defined by the Nios II ISA. Unimplemented instructions + * are legal instructions that must be emulated by some Nios II cores. + * + * If we get here, all instructions except multiplies and divides + * are illegal. + * + * This code assumes that OP is not muli (because muli was tested above). + * All other multiplies and divides are legal. Anything else is illegal. + */ + + movi r8, 0x3a /* OP for R-type mul* and div* */ + bne r5, r8, .Lnot_muldiv + + /* r15 already is 0x24 */ /* OPX of divu */ + beq r4, r15, .Ldivide + + movi r15,0x27 /* OPX of mul */ + beq r4, r15, .Lmultiply + + movi r15,0x07 /* OPX of mulxuu */ + beq r4, r15, .Lmultiply + + movi r15,0x17 /* OPX of mulxsu */ + beq r4, r15, .Lmultiply + + movi r15,0x1f /* OPX of mulxss */ + beq r4, r15, .Lmultiply + + movi r15,0x25 /* OPX of div */ + bne r4, r15, .Lnot_muldiv + + + /* DIVISION + * + * Divide an unsigned dividend by an unsigned divisor using + * a shift-and-subtract algorithm. The example below shows + * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a + * single register to store both the dividend and the quotient, + * allowing both values to be shifted with a single instruction. + * + * remainder dividend:quotient + * --------- ----------------- + * initialize 00000000 00101011: + * shift 00000000 0101011:_ + * remainder >= divisor? no 00000000 0101011:0 + * shift 00000000 101011:0_ + * remainder >= divisor? no 00000000 101011:00 + * shift 00000001 01011:00_ + * remainder >= divisor? no 00000001 01011:000 + * shift 00000010 1011:000_ + * remainder >= divisor? no 00000010 1011:0000 + * shift 00000101 011:0000_ + * remainder >= divisor? no 00000101 011:00000 + * shift 00001010 11:00000_ + * remainder >= divisor? yes 00001010 11:000001 + * remainder -= divisor - 00000111 + * ---------- + * 00000011 11:000001 + * shift 00000111 1:000001_ + * remainder >= divisor? yes 00000111 1:0000011 + * remainder -= divisor - 00000111 + * ---------- + * 00000000 1:0000011 + * shift 00000001 :0000011_ + * remainder >= divisor? no 00000001 :00000110 + * + * The quotient is 00000110. + */ + +.Ldivide: + /* + * Prepare for division by assuming the result + * is unsigned, and storing its "sign" as 0. + */ + movi r17, 0 + + + /* Which division opcode? */ + xori r15, r4, 0x25 /* OPX of div */ + bne r15, zero, .Lunsigned_division + + + /* + * OPX is div. Determine and store the sign of the quotient. + * Then take the absolute value of both operands. + */ + xor r17, r3, r6 /* MSB contains sign of quotient */ + bge r3, zero, 0f + sub r3, zero, r3 /* -r3 */ +0: + bge r6, zero, 0f + sub r6, zero, r6 /* -r6 */ +0: + + +.Lunsigned_division: + /* Initialize the unsigned-division loop. */ + movi r13, 0 /* remainder = 0 */ + + /* Now + * r3 = dividend : quotient + * r4 = 0x25 for div, 0x24 for divu + * r6 = divisor + * r13 = remainder + * r14 = loop counter (already initialized to 32) + * r17 = MSB contains sign of quotient + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Ldivide_loop: + + /* + * Division: + * + * (remainder:dividend:quotient) <<= 1; + */ + slli r13, r13, 1 + cmplt r15, r3, zero /* r15 = MSB of r3 */ + or r13, r13, r15 + slli r3, r3, 1 + + + /* + * if (remainder >= divisor) + * { + * set LSB of quotient + * remainder -= divisor; + * } + */ + bltu r13, r6, .Ldiv_skip + ori r3, r3, 1 + sub r13, r13, r6 +.Ldiv_skip: + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Ldivide_loop + + mov r9, r3 + + + /* Now + * r9 = quotient + * r4 = 0x25 for div, 0x24 for divu + * r7 = 4*(C^16) + * r17 = MSB contains sign of quotient + */ + + + /* + * Conditionally negate signed quotient. If quotient is unsigned, + * the sign already is initialized to 0. + */ + bge r17, zero, .Lstore_result + sub r9, zero, r9 /* -r9 */ + + br .Lstore_result + + + + + /* MULTIPLICATION + * + * A "product" is the number that one gets by summing a "multiplicand" + * several times. The "multiplier" specifies the number of copies of the + * multiplicand that are summed. + * + * Actual multiplication algorithms don't use repeated addition, however. + * Shift-and-add algorithms get the same answer as repeated addition, and + * they are faster. To compute the lower half of a product (pppp below) + * one shifts the product left before adding in each of the partial products + * (a * mmmm) through (d * mmmm). + * + * To compute the upper half of a product (PPPP below), one adds in the + * partial products (d * mmmm) through (a * mmmm), each time following the + * add by a right shift of the product. + * + * mmmm + * * abcd + * ------ + * #### = d * mmmm + * #### = c * mmmm + * #### = b * mmmm + * #### = a * mmmm + * -------- + * PPPPpppp + * + * The example above shows 4 partial products. Computing actual Nios II + * products requires 32 partials. + * + * It is possible to compute the result of mulxsu from the result of mulxuu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rA. + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + * + * It is possible to compute the result of mulxss from the result of mulxsu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rB. + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + * + */ + +.Lmul_immed: + /* Opcode is muli. Change it into mul for remainder of algorithm. */ + mov r7, r6 /* Field B is dest register, not field C. */ + mov r6, r4 /* Field IMM16 is src2, not field B. */ + movi r4, 0x27 /* OPX of mul is 0x27 */ + +.Lmultiply: + /* Initialize the multiplication loop. */ + movi r9, 0 /* mul_product = 0 */ + movi r10, 0 /* mulxuu_product = 0 */ + mov r11, r6 /* save original multiplier for mulxsu and mulxss */ + mov r12, r6 /* mulxuu_multiplier (will be shifted) */ + movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */ + + /* Now + * r3 = multiplicand + * r6 = mul_multiplier + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r12 = mulxuu_multiplier + * r14 = loop counter (already initialized) + * r15 = temp + * r16 = 1 + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Lmultiply_loop: + + /* + * mul_product <<= 1; + * lsb = multiplier & 1; + */ + slli r9, r9, 1 + andi r15, r12, 1 + + /* + * if (lsb == 1) + * { + * mulxuu_product += multiplicand; + * } + */ + beq r15, zero, .Lmulx_skip + add r10, r10, r3 + cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */ + ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */ +.Lmulx_skip: + + /* + * if (MSB of mul_multiplier == 1) + * { + * mul_product += multiplicand; + * } + */ + bge r6, zero, .Lmul_skip + add r9, r9, r3 +.Lmul_skip: + + /* + * mulxuu_product >>= 1; logical shift + * mul_multiplier <<= 1; done with MSB + * mulx_multiplier >>= 1; done with LSB + */ + srli r10, r10, 1 + or r10, r10, r15 /* OR in the saved carry bit. */ + slli r6, r6, 1 + srli r12, r12, 1 + + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Lmultiply_loop + + + /* + * Multiply emulation loop done. + */ + + /* Now + * r3 = multiplicand + * r4 = OPX + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r15 = temp + */ + + + /* + * Select/compute the result based on OPX. + */ + + + /* OPX == mul? Then store. */ + xori r15, r4, 0x27 + beq r15, zero, .Lstore_result + + /* It's one of the mulx.. opcodes. Move over the result. */ + mov r9, r10 + + /* OPX == mulxuu? Then store. */ + xori r15, r4, 0x07 + beq r15, zero, .Lstore_result + + /* Compute mulxsu + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + */ + bge r3, zero, .Lmulxsu_skip + sub r9, r9, r11 +.Lmulxsu_skip: + + /* OPX == mulxsu? Then store. */ + xori r15, r4, 0x17 + beq r15, zero, .Lstore_result + + /* Compute mulxss + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + */ + bge r11, zero, .Lmulxss_skip + sub r9, r9, r3 +.Lmulxss_skip: + /* At this point, assume that OPX is mulxss, so store */ + + +.Lstore_result: + add r7, r7, sp + stw r9, 0(r7) + + ldw r16, 0(sp) + ldw r17, 4(sp) + ldw r18, 8(sp) + ldw r19, 12(sp) + ldw r20, 16(sp) + ldw r21, 20(sp) + ldw r22, 24(sp) + ldw r23, 28(sp) + + /* bt @ 32 - Breakpoint register usually isn't an operand. */ + /* et @ 36 - Don't corrupt et. */ + /* gp @ 40 - Don't corrupt gp. */ + /* sp @ 44 - Don't corrupt sp. */ + ldw fp, 48(sp) + /* ea @ 52 - Don't corrupt ea. */ + /* ba @ 56 - Breakpoint register usually isn't an operand. */ + + addi sp, sp, 60 + + br .Lexception_exit + + +.Lnot_muldiv: + + addi sp, sp, 60 + + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_exception_trap.S b/software/DE2_115_ASM_bsp/HAL/src/alt_exception_trap.S new file mode 100644 index 0000000..bd9a9f5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_exception_trap.S @@ -0,0 +1,81 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the trap exception handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_trap +alt_exception_trap: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + .section .exceptions.soft, "xa" + +.Ltrap_handler: + + /* + * Did a trap instruction cause the exception? + * + * The instruction which the exception occurred on has been loaded + * into r2 by code in alt_exception_entry.S + * + */ + + movhi r3,0x003b /* upper half of trap opcode */ + ori r3,r3,0x683a /* lower half of trap opcode */ + bne r2,r3,.Lnot_trap + + /* + * There is no trap handler defined here, and so executing a trap + * instruction causes a software break. If you provide a trap handler, + * then you must replace the break instruction below with your handler. + * Your handler must preserve ea and the usual callee saved registers. + */ + + break + + br .Lexception_exit + +.Lnot_trap: + + + .section .exceptions.exit.label +.Lexception_exit: + + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_execve.c b/software/DE2_115_ASM_bsp/HAL/src/alt_execve.c new file mode 100644 index 0000000..51bfcc4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_execve.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * execve() is used by newlib to launch new processes. This is unsupported in + * the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_EXECVE is mapped onto the execve() system call in alt_syscall.h + */ + +int ALT_EXECVE (char *name, char ** argv, char** env) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(execve); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_exit.c b/software/DE2_115_ASM_bsp/HAL/src/alt_exit.c new file mode 100644 index 0000000..46cbe18 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_exit.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_sim.h" +#include "os/alt_hooks.h" +#include "os/alt_syscall.h" + +#include "alt_types.h" +#include "sys/alt_log_printf.h" +/* + * _exit() is called by exit() in order to terminate the current process. + * Typically this is called when main() completes. It should never return. + * Since there is nowhere to go once this process completes, this + * implementation simply blocks forever. + * + * Note that interrupts are not disabled so that execution outside of this + * thread is allowed to continue. + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + /* ALT_LOG - please see HAL/inc/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_fcntl.c b/software/DE2_115_ASM_bsp/HAL/src/alt_fcntl.c new file mode 100644 index 0000000..382fa43 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_fcntl.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include +#include + +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#define ALT_FCNTL_FLAGS_MASK ((alt_u32) (O_APPEND | O_NONBLOCK)) + +/* + * fcntl() is a limited implementation of the standard fcntl() system call. + * It can be used to change the state of the flags associated with an open + * file descriptor. Normally these flags are set during the call to + * open(). It is anticipated that the main use of this function will be to + * change the state of a device from blocking to non-blocking (where this is + * supported). + * + * The input argument "fd" is the file descriptor to be manipulated. "cmd" + * is the command to execute. This can be either F_GETFL (return the + * current value of the flags) or F_SETFL (set the value of the flags). + * + * If "cmd" is F_SETFL then the argument "arg" is the new value of flags, + * otherwise "arg" is ignored. Only the flags: O_APPEND and O_NONBLOCK + * can be updated by a call to fcntl(). All other flags remain + * unchanged. + * + * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h + */ + +int ALT_FCNTL (int file, int cmd, ...) +{ + alt_fd* fd; + long flags; + va_list argp; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + switch (cmd) + { + case F_GETFL: + return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK); + case F_SETFL: + va_start(argp, cmd); + flags = va_arg(argp, long); + fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK; + fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK); + va_end(argp); + return 0; + default: + ALT_ERRNO = EINVAL; + return -1; + } + } + + ALT_ERRNO = EBADFD; + return -1; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_fd_lock.c b/software/DE2_115_ASM_bsp/HAL/src/alt_fd_lock.c new file mode 100644 index 0000000..162295a --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_fd_lock.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_lock() is called as a consequence of an ioctl call to gain exclusive + * access to a device, i.e.: + * + * ioctl (fd, TIOCEXCL, NULL); + * + * If there are no other open file descriptors which reference the same + * device, then alt_fd_lock() will grant the lock. Further calls to open() + * for this device will fail until the lock is released. + * + * This is done by calling close() for this file descriptor, or by calling: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * The return value is zero for success, or negative in the case of failure. + */ + +int alt_fd_lock (alt_fd* fd) +{ + int i; + int rc = 0; + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + for (i = 0; i < alt_max_fd; i++) + { + if ((&alt_fd_list[i] != fd) && (alt_fd_list[i].dev == fd->dev)) + { + rc = -EACCES; + goto alt_fd_lock_exit; + } + } + fd->fd_flags |= ALT_FD_EXCL; + + alt_fd_lock_exit: + + ALT_SEM_POST(alt_fd_list_lock); + return rc; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_fd_unlock.c b/software/DE2_115_ASM_bsp/HAL/src/alt_fd_unlock.c new file mode 100644 index 0000000..5f50386 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_fd_unlock.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_unlock() is the inverse of alt_fd_lock(). It is called as a + * consequence of a TIOCNXCL ioctl request, e.g: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * It enables multiple file descriptors to exist for the same device. This + * is normally the case, but it may have been disabled by a previous call to + * alt_fd_lock(). + * + * Return zero on sucess, and a negative value on failure. + * + * The current implementation always succeeds. + */ + +int alt_fd_unlock (alt_fd* fd) +{ + fd->fd_flags &= ~ALT_FD_EXCL; + return 0; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_find_dev.c b/software/DE2_115_ASM_bsp/HAL/src/alt_find_dev.c new file mode 100644 index 0000000..964f63f --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_find_dev.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_dev() is used by open() in order to locate a previously registered + * device with the name "name". The input argument "llist" is a pointer to the + * head of the device list to search. + * + * The return value is a pointer to the matching device, or NULL if there is + * no match. + * + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + alt_dev* next = (alt_dev*) llist->next; + alt_32 len; + + len = strlen(name) + 1; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + { + + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_find_file.c b/software/DE2_115_ASM_bsp/HAL/src/alt_find_file.c new file mode 100644 index 0000000..ae30e93 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_find_file.c @@ -0,0 +1,89 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_file() is used by open() in order to locate a previously registered + * filesystem that owns that mount point that contains the file named "name". + * + * The return value is a pointer to the matching filesystem, or NULL if there is + * no match. + * + * A match is considered to have been found if the filesystem name followed by + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + alt_dev* next = (alt_dev*) alt_fs_list.next; + + alt_32 len; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + { + len = strlen(next->name); + + if (next->name[len-1] == '/') + { + len -= 1; + } + + if (((name[len] == '/') || (name[len] == '\0')) && + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_flash_dev.c b/software/DE2_115_ASM_bsp/HAL/src/alt_flash_dev.c new file mode 100644 index 0000000..0acffc7 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_flash_dev.c @@ -0,0 +1,69 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.c - Functions to register a flash device to the "generic" flash * +* interface * +* * +* Author PRR * +* * +******************************************************************************/ + +#include +#include "sys/alt_llist.h" +#include "sys/alt_flash_dev.h" +#include "priv/alt_file.h" + +ALT_LLIST_HEAD(alt_flash_dev_list); + +alt_flash_fd* alt_flash_open_dev(const char* name) +{ + alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list); + + if ((dev) && dev->open) + { + return dev->open(dev, name); + } + + return dev; +} + +void alt_flash_close_dev(alt_flash_fd* fd) +{ + if (fd && fd->close) + { + fd->close(fd); + } + return; +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_fork.c b/software/DE2_115_ASM_bsp/HAL/src/alt_fork.c new file mode 100644 index 0000000..b6edbb5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_fork.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * The fork() system call is used by newlib to create a duplicate copy of the + * curent process. This is unsupported in the HAL environment. However a + * "do-nothing" implementation is still provied for newlib compatability. + * + * ALT_FORK is mapped onto the fork() system call in alt_syscall.h + */ + +int ALT_FORK (void) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(fork); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_fs_reg.c b/software/DE2_115_ASM_bsp/HAL/src/alt_fs_reg.c new file mode 100644 index 0000000..e88a340 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_fs_reg.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * The alt_fs_reg() function is used to register a file system. Once registered + * a device can be accessed using the standard posix calls: open(), read(), + * write() etc. + * + * System behaviour is undefined in the event that a file system is registered + * with a name that conflicts with an existing device or file system. + * + * alt_fs_reg() is not thread safe in the sense that there should be no other + * thread using the file system list at the time that alt_dev_reg() is called. In + * practice this means that alt_fs_reg() should only be called while operating + * in a single threaded mode. The expectation is that it will only be called + * by the file system initilisation functions invoked by alt_sys_init(), which in + * turn should only be called by the single threaded C startup code. + * + * A return value of zero indicates success. A negative return value indicates + * failure. + */ + +int alt_fs_reg (alt_dev* dev) +{ + /* + * check that the device has a name. + */ + + if (!dev->name) + { + return -ENODEV; + } + + /* + * register the file system. + */ + + alt_llist_insert(&alt_fs_list, &dev->llist); + + return 0; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_fstat.c b/software/DE2_115_ASM_bsp/HAL/src/alt_fstat.c new file mode 100644 index 0000000..3248764 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_fstat.c @@ -0,0 +1,128 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The fstat() system call is used to obtain information about the capabilities + * of an open file descriptor. By default file descriptors are marked as + * being character devices. If a device or file system wishes to advertise + * alternative capabilities then they can register an fstat() function within + * their associated alt_dev structure. This will be called to fill in the + * entries in the imput "st" structure. + * + * This function is provided for compatability with newlib. + * + * ALT_FSTAT is mapped onto the fstat() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as character devices for provided stdio devices. + */ +int ALT_FSTAT (int file, struct stat *st) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + st->st_mode = _IFCHR; + return 0; + default: + return -1; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(fstat); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + alt_fd* fd; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + { + return fd->dev->fstat(fd, st); + } + + /* + * If no function is provided, mark the fd as belonging to a character + * device. + */ + + else + { + st->st_mode = _IFCHR; + return 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_get_fd.c b/software/DE2_115_ASM_bsp/HAL/src/alt_get_fd.c new file mode 100644 index 0000000..f42944b --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_get_fd.c @@ -0,0 +1,105 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * alt_get_fd() is called to allocate a new file descriptor from the file + * descriptor pool. If a file descriptor is succesfully allocated, it is + * configured to refer to device "dev". + * + * The return value is the index of the file descriptor structure (i.e. + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + alt_32 i; + int rc = -EMFILE; + + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + /* + * Search through the list of file descriptors, and allocate the first + * free descriptor that's found. + * + * If a free descriptor is found, then the value of "alt_max_fd" is + * updated accordingly. "alt_max_fd" is a 'highwater mark' which + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + { + if (!alt_fd_list[i].dev) + { + alt_fd_list[i].dev = dev; + if (i > alt_max_fd) + { + alt_max_fd = i; + } + rc = i; + goto alt_get_fd_exit; + } + } + + alt_get_fd_exit: + + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + + return rc; +} + + + + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_getchar.c b/software/DE2_115_ASM_bsp/HAL/src/alt_getchar.c new file mode 100644 index 0000000..3e7df79 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_getchar.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#include "priv/alt_file.h" +#include "unistd.h" +#endif + +/* + * Uses the ALT_DRIVER_READ() macro to call directly to driver if available. + * Otherwise, uses newlib provided getchar() routine. + */ +int +alt_getchar(void) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); + char c; + + if (ALT_DRIVER_READ(ALT_STDIN_DEV, &c, 1, alt_fd_list[STDIN_FILENO].fd_flags) <= 0) { + return -1; + } + return c; +#else + return getchar(); +#endif +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_getpid.c b/software/DE2_115_ASM_bsp/HAL/src/alt_getpid.c new file mode 100644 index 0000000..b63ec33 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_getpid.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * The getpid() system call is used by newlib to obtain the current process + * id. Since there is only ever a single process in the HAL environment, + * this just returns a constant. + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + return 0; +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_gettod.c b/software/DE2_115_ASM_bsp/HAL/src/alt_gettod.c new file mode 100644 index 0000000..46b12c2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_gettod.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_alarm.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +struct timezone alt_timezone = {0, 0}; +struct timeval alt_resettime = {0, 0}; + +/* + * gettimeofday() can be called to obtain a time structure which indicates the + * current "wall clock" time. This is calculated using the elapsed number of + * system clock ticks, and the value of "alt_resettime" and "alt_timezone" set + * through the last call to settimeofday(). + * + * Warning: if this function is called concurrently with a call to + * settimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_GETTIMEOFDAY is mapped onto the gettimeofday() system call in + * alt_syscall.h + */ + + +#if defined (__GNUC__) && (__GNUC__ >= 4) +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, void *ptimezone_vptr) +{ + struct timezone *ptimezone = (struct timezone*)ptimezone_vptr; +#else +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, struct timezone *ptimezone) +{ +#endif + + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* + * Check to see if the system clock is running. This is indicated by a + * non-zero system clock rate. If the system clock is not running, an error + * is generated and the contents of "ptimeval" and "ptimezone" are not + * updated. + */ + + if (tick_rate) + { + ptimeval->tv_sec = alt_resettime.tv_sec + nticks/tick_rate; + ptimeval->tv_usec = alt_resettime.tv_usec + + (alt_u32)(((alt_u64)nticks*(ALT_US/tick_rate))%ALT_US); + + while(ptimeval->tv_usec < 0) { + if (ptimeval->tv_sec <= 0) + { + ptimeval->tv_sec = 0; + ptimeval->tv_usec = 0; + break; + } + else + { + ptimeval->tv_sec--; + ptimeval->tv_usec += ALT_US; + } + } + + while(ptimeval->tv_usec >= ALT_US) { + ptimeval->tv_sec++; + ptimeval->tv_usec -= ALT_US; + } + + if (ptimezone) + { + ptimezone->tz_minuteswest = alt_timezone.tz_minuteswest; + ptimezone->tz_dsttime = alt_timezone.tz_dsttime; + } + + return 0; + } + + return -ENOTSUP; +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_gmon.c b/software/DE2_115_ASM_bsp/HAL/src/alt_gmon.c new file mode 100644 index 0000000..fce7587 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_gmon.c @@ -0,0 +1,272 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include + +#include "priv/nios2_gmon_data.h" + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" + + +/* Macros */ + +/* How large should the bins be which we use to generate the histogram */ +#define PCSAMPLE_BYTES_PER_BUCKET 32 + +#define NIOS2_READ_EA(dest) __asm__ ("mov %0, ea" : "=r" (dest)) + +/* The compiler inserts calls to mcount() at the start of + * every function call. The structure mcount_fn_arc records t + * he return address of the function called (in from_pc) + * and the return address of the mcount function + * (in self_pc). The number of times this arc is executed is + * recorded in the field count. + */ +struct mcount_fn_arc +{ + struct mcount_fn_arc * next; + void * from_pc; + unsigned int count; +}; + +/* We need to maintain a list of pointers to the heads of each adjacency + * list so that we can find them when writing out the gmon.out file. Since + * we don't know at the start of program execution how many functions will + * be called we use a list structure to do this. + */ +struct mcount_fn_entry +{ + struct mcount_fn_entry * next; + void * self_pc; + struct mcount_fn_arc * arc_head; +}; + +/* function prototypes */ + +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) __attribute__ ((no_instrument_function)); + +static __inline__ void * mcount_allocate(unsigned int size) __attribute__ ((no_instrument_function)); +static int nios2_pcsample_init(void) __attribute__ ((no_instrument_function)); +static alt_u32 nios2_pcsample(void* alarm) __attribute__ ((no_instrument_function)); + +/* global variables */ + +/* stext and etext are defined in the linker script */ +extern char stext[]; +extern char etext[]; + +/* Is the PC sampling stuff enabled yet? */ +static int pcsample_need_init = 1; + +#define HASH_BUCKETS 64 /* Must be a power of 2 */ + +/* This points to the list of adjacency list pointers. */ +struct mcount_fn_entry * __mcount_fn_head[HASH_BUCKETS]; + +/* pointer to the in-memory buffer containing the histogram */ +static unsigned short* s_pcsamples = 0; + +/* the address of the start and end of text section */ +static const unsigned int s_low_pc = (unsigned int)stext; +static const unsigned int s_high_pc = (unsigned int)etext; + +/* the alarm structure to register for pc sampling */ +static alt_alarm s_nios2_pcsample_alarm; + +unsigned int alt_gmon_data[GMON_DATA_SIZE] = +{ + 0x6e6f6d67, /* "gmon" */ + GMON_DATA_SIZE, + 0, + (unsigned int)stext, + (unsigned int)etext, + PCSAMPLE_BYTES_PER_BUCKET, + 0, + (unsigned int)__mcount_fn_head, + (unsigned int)(__mcount_fn_head + HASH_BUCKETS) +}; + +/* This holds the current slab of memory we're allocating out of */ +static char * mcount_slab_ptr = 0; +static int mcount_slab_size = 0; + +#define MCOUNT_SLAB_INCREMENT 1020 + + +/* + * We can't use malloc to allocate memory because that's too complicated, and + * can't be called at interrupt time. Use the lower level allocator instead + * because that's interrupt safe (and because we never free anything). + * + * For speed, we allocate a block of data at once. + */ +static __inline__ void * mcount_allocate(unsigned int size) +{ + void * data; + + if (size > mcount_slab_size) + { + mcount_slab_ptr = sbrk(MCOUNT_SLAB_INCREMENT); + mcount_slab_size = MCOUNT_SLAB_INCREMENT; + } + + data = mcount_slab_ptr; + mcount_slab_ptr += size; + mcount_slab_size -= size; + + return data; +} + + +/* + * Add the arc with the values of frompc and topc given to the graph. + * This function might be called at interrupt time so must be able to + * cope with reentrancy. + * + * The fast case, where we have already allocated a function arc, has been + * handled by the assmebler code. + */ +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) +{ + alt_irq_context context; + struct mcount_fn_arc * arc_entry; + + /* Keep trying to start up the PC sampler until it is running. + * (It can't start until the timer is going). + */ + if (pcsample_need_init) + { + pcsample_need_init = 0; + pcsample_need_init = nios2_pcsample_init(); + } + + /* + * We must disable interrupts around the allocation and the list update to + * prevent corruption if the instrumented function is re-entrant. + * + * It's safe for the code above to be stepping through the chain and be + * interrupted by this code modifying it - there is an edge case which will + * leave two copies of the same arc on the list (both with count=1), but + * this is dealt with on the host. + */ + context = alt_irq_disable_all(); + + if (fn_entry == NULL) + { + /* Add it to the list of functions we must output later. */ + fn_entry = (struct mcount_fn_entry *)mcount_allocate(sizeof(struct mcount_fn_entry)); + + fn_entry->self_pc = self_pc; + fn_entry->arc_head = NULL; + + fn_entry->next = *fn_head; + *fn_head = fn_entry; + } + + /* We will need a new list entry - if there was a list entry before + * then the assembler code would have handled it. */ + arc_entry = (struct mcount_fn_arc *)mcount_allocate(sizeof(struct mcount_fn_arc)); + + arc_entry->from_pc = from_pc; + arc_entry->count = 1; + + arc_entry->next = fn_entry->arc_head; + fn_entry->arc_head = arc_entry; + + alt_irq_enable_all(context); +} + + +/* + * nios2_pcsample_init starts profiling. + * It is called the first time mcount is called, and on subsequent calls to + * mcount until it returns zero. It initializes the pc histogram and turns on + * timer driven pc sampling. + */ +static int nios2_pcsample_init(void) +{ + unsigned int pcsamples_size; + + /* We sample the PC every tick */ + unsigned int prof_rate = alt_ticks_per_second(); + if (prof_rate == 0) + return 1; + + /* allocate the histogram buffer s_pcsamples */ + pcsamples_size = (s_high_pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples = (unsigned short*)sbrk(pcsamples_size * sizeof(unsigned short)); + + if (s_pcsamples != 0) + { + /* initialize the buffer to zero */ + memset(s_pcsamples, 0, pcsamples_size * sizeof(unsigned short)); + + alt_gmon_data[GMON_DATA_PROFILE_DATA] = (int)s_pcsamples; + alt_gmon_data[GMON_DATA_PROFILE_RATE] = prof_rate; + + /* Sample every tick (it's cheap) */ + alt_alarm_start(&s_nios2_pcsample_alarm, 1, nios2_pcsample, 0); + } + + return 0; +} + + +/* + * Sample the PC value and store it in the histogram + */ +static alt_u32 nios2_pcsample(void* context) +{ + unsigned int pc; + unsigned int bucket; + + /* read the exception return address - this will be + * inaccurate if there are nested interrupts but we + * assume that this is rare and the inaccuracy will + * not be great */ + NIOS2_READ_EA(pc); + + /* + * If we're within the profilable range then increment the relevant + * bucket in the histogram + */ + if (pc >= s_low_pc && pc < s_high_pc && s_pcsamples != 0) + { + bucket = (pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples[bucket]++; + } + + /* Sample every tick */ + return 1; +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_icache_flush.c b/software/DE2_115_ASM_bsp/HAL/src/alt_icache_flush.c new file mode 100644 index 0000000..1662991 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_icache_flush.c @@ -0,0 +1,84 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ +#if NIOS2_ICACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + { + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_icache_flush_all.c b/software/DE2_115_ASM_bsp/HAL/src/alt_icache_flush_all.c new file mode 100644 index 0000000..dc40ea8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_icache_flush_all.c @@ -0,0 +1,46 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); +#endif +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_iic.c b/software/DE2_115_ASM_bsp/HAL/src/alt_iic.c new file mode 100644 index 0000000..4821f25 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_iic.c @@ -0,0 +1,106 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" + +/* + * This file implements the HAL Enhanced interrupt API for Nios II processors + * with an internal interrupt controller (IIC). For most routines, this serves + * as a wrapper layer over the legacy interrupt API (which must be used with + * the IIC only). + * + * Use of the enhanced API is recommended so that application and device + * drivers are compatible with a Nios II system configured with an external + * interrupt controller (EIC), or IIC. This will afford maximum portability. + * + * If an EIC is present, the EIC device driver must provide these routines, + * because their operation will be specific to that EIC type. + */ +#ifndef NIOS2_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" +#include "priv/alt_legacy_irq.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); +} + +/** @Function Description: This function enables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_enable(irq); +} + +/** @Function Description: This function disables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_disable(irq); +} + +/** @Function Description: This function to determine if corresponding + * interrupt is enabled. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + + return (irq_enabled & (1 << irq)) ? 1: 0; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* NIOS2_EIC_PRESENT */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_iic_isr_register.c b/software/DE2_115_ASM_bsp/HAL/src/alt_iic_isr_register.c new file mode 100644 index 0000000..2e6bf5b --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_iic_isr_register.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * Provides an interrupt registry mechanism for the any CPUs internal interrupt + * controller (IIC) when the enhanced interrupt API is active. + */ +#ifndef ALT_CPU_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "alt_types.h" +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled + * upon return. Registering a NULL handler will disable the interrupt. + * + * @API Type: External + * @param ic_id Interrupt controller ID + * @param irq IRQ ID number + * @param isr Pointer to interrupt service routine + * @param isr_context Opaque pointer passed to ISR + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + int rc = -EINVAL; + int id = irq; /* IRQ interpreted as the interrupt ID. */ + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + + alt_irq[id].handler = isr; + alt_irq[id].context = isr_context; + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + + alt_irq_enable_all(status); + } + + return rc; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_instruction_exception_entry.c b/software/DE2_115_ASM_bsp/HAL/src/alt_instruction_exception_entry.c new file mode 100644 index 0000000..5cc8767 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_instruction_exception_entry.c @@ -0,0 +1,203 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. This handler could also be reached + * in the event of a spurious interrupt. + * + * The handler code is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* Function pointer to exception callback routine */ +alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32) = 0x0; + +/* Link entry routine to .exceptions section */ +int alt_instruction_exception_entry (alt_u32 exception_pc) + __attribute__ ((section (".exceptions"))); + +/* + * This is the entry point for instruction-generated exceptions handling. + * This routine will be called by alt_exceptions_entry.S, after it determines + * that an exception could not be handled by handlers that preceed that + * of instruction-generated exceptions (such as interrupts). + * + * For this to function properly, you must register an exception handler + * using alt_instruction_exception_register(). This routine will call + * that handler if it has been registered. Absent a handler, it will + * break break or hang as discussed below. + */ +int alt_instruction_exception_entry (alt_u32 exception_pc) +{ + alt_u32 cause, badaddr; + +/* + * If the processor hardware has the optional EXCEPTIONS & BADADDR registers, + * read them and pass their content to the user handler. These are always + * present if the MMU or MPU is enabled, and optionally for other advanced + * exception types via the "Extra exceptions information" setting in the + * processor (hardware) configuration. + * + * If these registers are not present, the cause field will be set to + * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should + * check the validity of the cause argument before proceeding. + */ +#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO + /* Get exception cause & "badaddr" */ + NIOS2_READ_EXCEPTION(cause); + cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> + NIOS2_EXCEPTION_REG_CAUSE_OFST ); + + NIOS2_READ_BADADDR(badaddr); +#else + cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; + badaddr = 0; +#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ + + if(alt_instruction_exception_handler) { + /* + * Call handler. Its return value indicates whether the exception-causing + * instruction should be re-issued. The code that called us, + * alt_eceptions_entry.S, will look at this value and adjust the ea + * register as necessary + */ + return alt_instruction_exception_handler(cause, exception_pc, badaddr); + } + /* + * We got here because an instruction-generated exception occured, but no + * handler is present. We do not presume to know how to handle it. If the + * debugger is present, break, otherwise hang. + * + * If you've reached here in the debugger, consider examining the + * EXCEPTIONS register cause bit-field, which was read into the 'cause' + * variable above, and compare it against the exceptions-type enumeration + * in alt_exceptions.h. This register is availabe if the MMU or MPU is + * present, or if the "Extra exceptions information" hardware option is + * selected. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious interrupts) + */ + else { +#ifdef NIOS2_HAS_DEBUG_STUB + NIOS2_BREAK(); +#else + while(1) + ; +#endif /* NIOS2_HAS_DEBUG_STUB */ + } + + /* // We should not get here. Remove compiler warning. */ + return NIOS2_EXCEPTION_RETURN_REISSUE_INST; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * This routine indicates whether a particular exception cause will have + * set a valid address into the BADADDR register, which is included + * in the arguments to a user-registered instruction-generated exception + * handler. Many exception types do not set valid contents in BADADDR; + * this is a convenience routine to easily test the validity of that + * argument in your handler. + * + * Note that this routine will return false (0) for cause '12', + * TLB miss. This is because there are four exception types that + * share that cause, two of which do not have a valid BADADDR. You + * must determine BADADDR's validity for these. + * + * Arguments: + * cause: The 5-bit exception cause field of the EXCEPTIONS register, + * shifted to the LSB position. You may pass the 'cause' argument + * in a handler you registered directy to this routine. + * + * Return: 1: BADADDR (bad_addr argument to handler) is valid + * 0: BADADDR is not valid + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause) +{ + switch (cause) { + case NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: + return 1; + case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: + return 1; + default: + return 0; + } +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_instruction_exception_register.c b/software/DE2_115_ASM_bsp/HAL/src/alt_instruction_exception_register.c new file mode 100644 index 0000000..395c644 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_instruction_exception_register.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* + * The header, alt_exception_handler_registry.h contains a struct describing + * the registered exception handler + */ +#include "priv/alt_exception_handler_registry.h" + +/* + * Pull in the exception entry assembly code. This will not be linked in + * unless this object is linked into the executable (i.e. only if + * alt_instruction_exception_register() is called). + */ +__asm__( "\n\t.globl alt_exception" ); + +/* + * alt_instruction_exception_register() is called to register a handler to + * service instruction-generated exceptions that are not handled by the + * default exception handler code (interrupts, and optionally unimplemented + * instructions and traps). + * + * Passing null (0x0) in the handler argument will disable a previously- + * registered handler. + * + * Note that if no handler is registered, exceptions that are not processed + * using the built-in handler (interrupts, and optionally unimplemented + * instructions and traps) are treated as unknown exceptions, resulting + * in either a break or an infinite loop. + */ +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ) +{ + alt_instruction_exception_handler = exception_handler; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_io_redirect.c b/software/DE2_115_ASM_bsp/HAL/src/alt_io_redirect.c new file mode 100644 index 0000000..049ed62 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_io_redirect.c @@ -0,0 +1,98 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + + +/* + * alt_open_fd() is similar to open() in that it is used to obtain a file + * descriptor for the file named "name". The "flags" and "mode" arguments are + * identical to the "flags" and "mode" arguments of open(). + * + * The distinction between the two functions is that the file descriptor + * structure to use is passed in as an argument, rather than allocated from the + * list of free file descriptors. + * + * This is used by alt_io_redirect() to redirect the stdin, stdout and stderr + * file descriptors to point to new devices. + * + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + int old; + + old = open (name, flags, mode); + + if (old >= 0) + { + fd->dev = alt_fd_list[old].dev; + fd->priv = alt_fd_list[old].priv; + fd->fd_flags = alt_fd_list[old].fd_flags; + + alt_release_fd (old); + } +} + +/* + * alt_io_redirect() is called once the device/filesystem lists have been + * initialised, but before main(). Its function is to redirect standard in, + * standard out and standard error so that they point to the devices selected by + * the user (as defined in system.h). + * + * Prior to the call to this function, io is directed towards /dev/null. If + * i/o can not be redirected to the requested device, for example if the device + * does not exist, then it remains directed at /dev/null. + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); +} + + + + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_ioctl.c b/software/DE2_115_ASM_bsp/HAL/src/alt_ioctl.c new file mode 100644 index 0000000..510b40d --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_ioctl.c @@ -0,0 +1,170 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/ioctl.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The ioctl() system call is provided so that application code can manipulate + * the i/o capabilities of a device in device specific ways. This is identical + * to the standard posix ioctl() function. + * + * In general this implementation simply vectors ioctl requests to the + * apropriate drivers ioctl function (as registered in the drivers alt_dev + * structure). + * + * However in the case of devices (as oposed to filesystem), the TIOCEXCL and + * TIOCNXCL requests are handled without reference to the driver. These + * requests are used to lock/release a device for exclusive access. + * + * Handling these requests centrally eases the task of device driver + * development. + * + * ALT_IOCTL is mapped onto the ioctl() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that calls ioctl routine of provided stdio devices. + */ +int ALT_IOCTL (int file, int req, void* arg) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDIN_DEV); +#endif +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(ioctl); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDIN_DEV, req, arg); +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDOUT_DEV, req, arg); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDERR_DEV, req, arg); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_IOCTL (int file, int req, void* arg) +{ + alt_fd* fd; + int rc; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + + /* + * In the case of device drivers (not file systems) handle the TIOCEXCL + * and TIOCNXCL requests as special cases. + */ + + if (fd->fd_flags & ALT_FD_DEV) + { + if (req == TIOCEXCL) + { + rc = alt_fd_lock (fd); + goto ioctl_done; + } + else if (req == TIOCNXCL) + { + rc = alt_fd_unlock (fd); + goto ioctl_done; + } + } + + /* + * If the driver provides an ioctl() function, call that to handle the + * request, otherwise set the return code to indicate that the request + * could not be processed. + */ + + if (fd->dev->ioctl) + { + rc = fd->dev->ioctl(fd, req, arg); + } + else + { + rc = -ENOTTY; + } + } + else + { + rc = -EBADFD; + } + +ioctl_done: + + if (rc < 0) + { + ALT_ERRNO = -rc; + } + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_irq_entry.S b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_entry.S new file mode 100644 index 0000000..8ee89e1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_entry.S @@ -0,0 +1,108 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the interrupt exception entry point code, which saves all the + * registers and calls the interrupt handler. It should be pulled in using + * a .globl from alt_irq_register.c. This scheme is used so that if an + * interrupt is never registered, then this code will not appear in the + * generated executable, thereby improving code footprint. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the compiler. + */ + .set noat + + /* + * Pull in the exception handler register save code. + */ + .globl alt_exception + + .globl alt_irq_entry + .section .exceptions.entry.label, "xa" +alt_irq_entry: + + /* + * Section .exceptions.entry is in alt_exception_entry.S + * This saves all the caller saved registers and reads estatus into r5 + */ + + .section .exceptions.irqtest, "xa" + +#ifdef ALT_CI_INTERRUPT_VECTOR_N + /* + * Use the interrupt vector custom instruction if present to accelerate + * this code. + * If the interrupt vector custom instruction returns a negative + * value, there are no interrupts active (estatus.pie is 0 + * or ipending is 0) so assume it is a software exception. + */ + custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0 + blt r4, r0, .Lnot_irq +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + andi r2, r5, 1 + beq r2, zero, .Lnot_irq + beq r4, zero, .Lnot_irq +#endif /* ALT_CI_INTERRUPT_VECTOR_N */ + + .section .exceptions.irqhandler, "xa" + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + + .section .exceptions.notirq.label, "xa" + +.Lnot_irq: + + /* + * Section .exceptions.exit is in alt_exception_entry.S + * This restores all the caller saved registers + */ + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_irq_handler.c b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_handler.c new file mode 100644 index 0000000..bb52fc8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_handler.c @@ -0,0 +1,169 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include "system.h" + +/* + * This interrupt handler only works with an internal interrupt controller + * (IIC). Processors with an external interrupt controller (EIC) use an + * implementation provided by an EIC driver. + */ +#ifndef ALT_CPU_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * A table describing each interrupt handler. The index into the array is the + * interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + */ +struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +/* + * alt_irq_handler() is called by the interrupt exception handler in order to + * process any outstanding interrupts. + * + * It is defined here since it is linked in using weak linkage. + * This means that if there is never a call to alt_irq_register() (above) then + * this function will not get linked in to the executable. This is acceptable + * since if no handler is ever registered, then an interrupt can never occur. + * + * If Nios II interrupt vector custom instruction exists, use it to accelerate + * the dispatch of interrupt handlers. The Nios II interrupt vector custom + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ +#ifdef ALT_CI_INTERRUPT_VECTOR + alt_32 offset; + char* alt_irq_base = (char*)alt_irq; +#else + alt_u32 active; + alt_u32 mask; + alt_u32 i; +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + +#ifdef ALT_CI_INTERRUPT_VECTOR + /* + * Call the interrupt vector custom instruction using the + * ALT_CI_INTERRUPT_VECTOR macro. + * It returns the offset into the vector table of the lowest-valued pending + * interrupt (corresponds to highest priority) or a negative value if none. + * The custom instruction assumes that each table entry is eight bytes. + */ + while ((offset = ALT_CI_INTERRUPT_VECTOR) >= 0) { + struct ALT_IRQ_HANDLER* handler_entry = + (struct ALT_IRQ_HANDLER*)(alt_irq_base + offset); +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + handler_entry->handler(handler_entry->context); +#else + handler_entry->handler(handler_entry->context, offset >> 3); +#endif + } +#else /* ALT_CI_INTERRUPT_VECTOR */ + /* + * Obtain from the interrupt controller a bit list of pending interrupts, + * and then process the highest priority interrupt. This process loops, + * loading the active interrupt list on each pass until alt_irq_pending() + * return zero. + * + * The maximum interrupt latency for the highest priority interrupt is + * reduced by finding out which interrupts are pending as late as possible. + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + + do + { + i = 0; + mask = 1; + + /* + * Test each bit in turn looking for an active interrupt. Once one is + * found, the interrupt handler asigned by a call to alt_irq_register() is + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + + } while (active); +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); +} + +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_irq_register.c b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_register.c new file mode 100644 index 0000000..cf7261e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_register.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * This interrupt registry mechanism works with the Nios II internal interrupt + * controller (IIC) only. Systems with an external interrupt controller (EIC), + * or those with the IIC who are using the enhanced interrupt API will + * utilize the alt_ic_isr_register() routine to register an interrupt. + */ +#ifndef NIOS2_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_legacy_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/* + * alt_irq_handler() is called to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * + * The return value is 0 if the interrupt handler was registered and the + * interrupt was enabled, otherwise it is negative. + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + int rc = -EINVAL; + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + + alt_irq[id].handler = handler; + alt_irq[id].context = context; + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + + alt_irq_enable_all(status); + } + return rc; +} +#endif /* NIOS2_EIC_PRESENT */ + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_irq_vars.c b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_vars.c new file mode 100644 index 0000000..4f4d140 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_irq_vars.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#include "system.h" + +/* + * These global variables are used to save the current list of enabled + * interrupts. See alt_irq.h for further details. + */ + +volatile alt_u32 alt_irq_active = 0; + +#ifndef ALT_EXCEPTION_STACK + +volatile alt_u32 alt_priority_mask = (alt_u32) -1; + +#endif + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_isatty.c b/software/DE2_115_ASM_bsp/HAL/src/alt_isatty.c new file mode 100644 index 0000000..73677dd --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_isatty.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as tty devices for provided stdio devices. + */ +int ALT_ISATTY (int file) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + return 1; + default: + return 0; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(isatty); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ +/* + * isatty() can be used to determine whether the input file descriptor "file" + * refers to a terminal device or not. If it is a terminal device then the + * return value is one, otherwise it is zero. + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + alt_fd* fd; + struct stat stat; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + { + return 1; + } + + /* + * If a driver does provide an implementation of the fstat() function, then + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + return (stat.st_mode == _IFCHR) ? 1 : 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return 0; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_kill.c b/software/DE2_115_ASM_bsp/HAL/src/alt_kill.c new file mode 100644 index 0000000..58097d1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_kill.c @@ -0,0 +1,121 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + + +/* + * kill() is used by newlib in order to send signals to processes. Since there + * is only a single process in the HAL, the only valid values for pid are + * either the current process id, or the broadcast values, i.e. pid must be + * less than or equal to zero. + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + int status = 0; + + if (pid <= 0) + { + switch (sig) + { + case 0: + + /* The null signal is used to check that a pid is valid. */ + + break; + + case SIGABRT: + case SIGALRM: + case SIGFPE: + case SIGILL: + case SIGKILL: + case SIGPIPE: + case SIGQUIT: + case SIGSEGV: + case SIGTERM: + case SIGUSR1: + case SIGUSR2: + case SIGBUS: + case SIGPOLL: + case SIGPROF: + case SIGSYS: + case SIGTRAP: + case SIGVTALRM: + case SIGXCPU: + case SIGXFSZ: + + /* + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + case SIGCHLD: + case SIGURG: + + /* + * The Posix standard defines these signals to be ignored by default. No + * mechanism is provided to change this behaviour. + */ + + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + } + } + + else if (pid > 0) + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + } + + if (status) + { + ALT_ERRNO = status; + return -1; + } + + return 0; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_link.c b/software/DE2_115_ASM_bsp/HAL/src/alt_link.c new file mode 100644 index 0000000..a57a5c4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_link.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * link() is used by newlib to create a new link to an existing file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_LINK is mapped onto the link() system call in alt_syscall.h + */ + +int ALT_LINK ( char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(link); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_load.c b/software/DE2_115_ASM_bsp/HAL/src/alt_load.c new file mode 100644 index 0000000..27d492b --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_load.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_load.h" +#include "sys/alt_cache.h" + +/* + * Linker defined symbols. + */ + +extern void __flash_rwdata_start; +extern void __ram_rwdata_start; +extern void __ram_rwdata_end; +extern void __flash_rodata_start; +extern void __ram_rodata_start; +extern void __ram_rodata_end; +extern void __flash_exceptions_start; +extern void __ram_exceptions_start; +extern void __ram_exceptions_end; + +/* + * alt_load() is called when the code is executing from flash. In this case + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + &__ram_rwdata_start, + &__ram_rwdata_end); + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + &__ram_exceptions_start, + &__ram_exceptions_end); + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + &__ram_rodata_start, + &__ram_rodata_end); + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + alt_icache_flush_all(); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_log_macro.S b/software/DE2_115_ASM_bsp/HAL/src/alt_log_macro.S new file mode 100644 index 0000000..2e3cc26 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_log_macro.S @@ -0,0 +1,56 @@ +/* alt_log_macro.S + * + * Implements the function tx_log_str, called by the assembly macro + * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, + * and this function will not be compiled. When logging is on, + * this function is used to print out the strings defined in the beginning + * of alt_log_printf.c, using port information taken from system.h and + * alt_log_printf.h. + * + * This routine only handles strings, and sends a character into the defined + * output device's output buffer when the device is ready. It's intended for + * debugging purposes, where messages can be set to print out at certain + * points in the boot code to indicate the progress of the program. + * + */ + +#ifndef __ALT_LOG_MACROS__ +#define __ALT_LOG_MACROS__ + +/* define this flag to skip assembly-incompatible parts + * of various include files. */ +#define ALT_ASM_SRC + +#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. + + #include "system.h" + #include "sys/alt_log_printf.h" + + .global tx_log_str +tx_log_str: + /* load base uart / jtag uart address into r6 */ + movhi r6, %hiadj(ALT_LOG_PORT_BASE) + addi r6, r6, %lo(ALT_LOG_PORT_BASE) +tx_next_char: + /* if pointer points to null, return + * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ + ldb r7, (r4) + beq r0, r7, end_tx + + /* check device transmit ready */ +wait_tx_ready_loop: + ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6) + andi r5, r5, ALT_LOG_PRINT_MSK + beq r5, r0, wait_tx_ready_loop + /* write char */ + stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) + /* advance string pointer */ + addi r4, r4, 1 + br tx_next_char +end_tx: + ret + +#endif + +#endif /* __ALT_LOG_MACROS__ */ + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_log_printf.c b/software/DE2_115_ASM_bsp/HAL/src/alt_log_printf.c new file mode 100644 index 0000000..af0116f --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_log_printf.c @@ -0,0 +1,479 @@ + +/* alt_log_printf.c + * + * This file implements the various C functions used for the + * alt_log logging/debugging print functions. The functions + * sit as is here - the job of hiding them from the compiler + * if logging is disabled is accomplished in the .h file. + * + * All the global variables for alt_log are defined here. + * These include the various flags that turn on additional + * logging options; the strings for assembly printing; and + * other globals needed by different logging options. + * + * There are 4 functions that handle the actual printing: + * alt_log_txchar: Actual function that puts 1 char to UART/JTAG UART. + * alt_log_repchar: Calls alt_log_txchar 'n' times - used by + * alt_log_private_printf for formatting. + * alt_log_private_printf: + * Stripped down implementation of printf - no floats. + * alt_log_printf_proc: + * Wrapper function for private_printf. + * + * The rest of the functions are called by the macros which + * were called by code in the other components. Each function + * is preceded by a comment, about which file it gets called + * in, and what its purpose is. + * + * author: gkwan + */ + +/* skip all code if enable is off */ +#ifdef ALT_LOG_ENABLE + +#include +#include +#include +#ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #include +#endif +#include "sys/alt_log_printf.h" + +/* strings for assembly puts */ +char alt_log_msg_bss[] = "[crt0.S] Clearing BSS \r\n";; +char alt_log_msg_alt_main[] = "[crt0.S] Calling alt_main.\r\n"; +char alt_log_msg_stackpointer[] \ + = "[crt0.S] Setting up stack and global pointers.\r\n"; +char alt_log_msg_cache[] = "[crt0.S] Inst & Data Cache Initialized.\r\n"; +/* char array allocation for alt_write */ +char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2]; + +/* global variables for all 'on' flags */ + +/* + * The boot message flag is linked into the data (rwdata) section + * because if it is zero, it would otherwise be placed in the bss section. + * alt_log examines this variable before the BSS is cleared in the boot-up + * process. + */ +volatile alt_u32 alt_log_boot_on_flag \ + __attribute__ ((section (".data"))) = ALT_LOG_BOOT_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_sys_clk_on_flag = ALT_LOG_SYS_CLK_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_alarm_on_flag = \ + ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_isr_on_flag = \ + ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag = \ + ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING; + +/* Global alarm object for recurrent JTAG UART status printing */ +alt_alarm alt_log_jtag_uart_alarm_1; + +/* Global ints for system clock printing and count */ +volatile int alt_log_sys_clk_count; +volatile int alt_system_clock_in_sec; + +/* enum used by alt_log_private_printf */ +enum +{ + pfState_chars, + pfState_firstFmtChar, + pfState_otherFmtChar +}; + + + + +/* Function to put one char onto the UART/JTAG UART txdata register. */ +void alt_log_txchar(int c,char *base) +{ + /* Wait until the device is ready for a character */ + while((ALT_LOG_PRINT_REG_RD(base) & ALT_LOG_PRINT_MSK) == 0) + ; + /* And pop the character into the register */ + ALT_LOG_PRINT_TXDATA_WR(base,c); +} + + +/* Called by alt_log_private_printf to print out characters repeatedly */ +void alt_log_repchar(char c,int r,int base) +{ + while(r-- > 0) + alt_log_txchar(c,(char*) base); +} + + +/* Stripped down printf function */ +void alt_log_private_printf(const char *fmt,int base,va_list args) + { + const char *w; + char c; + int state; + int fmtLeadingZero = 0; /* init these all to 0 for -W warnings. */ + int fmtLong = 0; + int fmtBeforeDecimal = 0; + int fmtAfterDecimal = 0; + int fmtBase = 0; + int fmtSigned = 0; + int fmtCase = 0; /* For hex format, if 1, A-F, else a-f. */ + + w = fmt; + state = pfState_chars; + + while(0 != (c = *w++)) + { + switch(state) + { + case pfState_chars: + if(c == '%') + { + fmtLeadingZero = 0; + fmtLong = 0; + fmtBase = 10; + fmtSigned = 1; + fmtCase = 0; /* Only %X sets this. */ + fmtBeforeDecimal = -1; + fmtAfterDecimal = -1; + state = pfState_firstFmtChar; + } + else + { + alt_log_txchar(c,(char*)base); + } + break; + + case pfState_firstFmtChar: + if(c == '0') + { + fmtLeadingZero = 1; + state = pfState_otherFmtChar; + } + else if(c == '%') + { + alt_log_txchar(c,(char*)base); + state = pfState_chars; + } + else + { + state = pfState_otherFmtChar; + goto otherFmtChar; + } + break; + + case pfState_otherFmtChar: +otherFmtChar: + if(c == '.') + { + fmtAfterDecimal = 0; + } + else if('0' <= c && c <= '9') + { + c -= '0'; + if(fmtAfterDecimal < 0) /* still before decimal */ + { + if(fmtBeforeDecimal < 0) + { + fmtBeforeDecimal = 0; + } + else + { + fmtBeforeDecimal *= 10; + } + fmtBeforeDecimal += c; + } + else + { + fmtAfterDecimal = (fmtAfterDecimal * 10) + c; + } + } + else if(c == 'l') + { + fmtLong = 1; + } + else /* we're up to the letter which determines type */ + { + switch(c) + { + case 'd': + case 'i': +doIntegerPrint: + { + unsigned long v; + unsigned long p; /* biggest power of fmtBase */ + unsigned long vShrink; /* used to count digits */ + int sign; + int digitCount; + + /* Get the value */ + if(fmtLong) + { + if (fmtSigned) + { + v = va_arg(args,long); + } + else + { + v = va_arg(args,unsigned long); + } + } + else + { + if (fmtSigned) + { + v = va_arg(args,int); + } + else + { + v = va_arg(args,unsigned int); + } + } + + /* Strip sign */ + sign = 0; + /* (assumes sign bit is #31) */ + if( fmtSigned && (v & (0x80000000)) ) + { + v = ~v + 1; + sign = 1; + } + + /* Count digits, and get largest place value */ + vShrink = v; + p = 1; + digitCount = 1; + while( (vShrink = vShrink / fmtBase) > 0 ) + { + digitCount++; + p *= fmtBase; + } + + /* Print leading characters & sign */ + fmtBeforeDecimal -= digitCount; + if(fmtLeadingZero) + { + if(sign) + { + alt_log_txchar('-',(char*)base); + fmtBeforeDecimal--; + } + alt_log_repchar('0',fmtBeforeDecimal,base); + } + else + { + if(sign) + { + fmtBeforeDecimal--; + } + alt_log_repchar(' ',fmtBeforeDecimal,base); + if(sign) + { + alt_log_txchar('-',(char*)base); + } + } + + /* Print numbery parts */ + while(p) + { + unsigned char d; + + d = v / p; + d += '0'; + if(d > '9') + { + d += (fmtCase ? 'A' : 'a') - '0' - 10; + } + alt_log_txchar(d,(char*)base); + + v = v % p; + p = p / fmtBase; + } + } + + state = pfState_chars; + break; + + case 'u': + fmtSigned = 0; + goto doIntegerPrint; + case 'o': + fmtSigned = 0; + fmtBase = 8; + goto doIntegerPrint; + case 'x': + fmtSigned = 0; + fmtBase = 16; + goto doIntegerPrint; + case 'X': + fmtSigned = 0; + fmtBase = 16; + fmtCase = 1; + goto doIntegerPrint; + + case 'c': + alt_log_repchar(' ',fmtBeforeDecimal-1,base); + alt_log_txchar(va_arg(args,int),(char*)base); + break; + + case 's': + { + char *s; + + s = va_arg(args,char *); + alt_log_repchar(' ',fmtBeforeDecimal-strlen(s),base); + + while(*s) + alt_log_txchar(*s++,(char*)base); + } + break; + } /* switch last letter of fmt */ + state=pfState_chars; + } + break; + } /* switch */ + } /* while chars left */ + } /* printf */ + +/* Main logging printf function */ +int alt_log_printf_proc(const char *fmt, ... ) +{ + va_list args; + + va_start (args, fmt); + alt_log_private_printf(fmt,ALT_LOG_PORT_BASE,args); + return (0); +} + +/* Below are the functions called by different macros in various components. */ + +/* If the system has a JTAG_UART, include JTAG_UART debugging functions */ +#ifdef __ALTERA_AVALON_JTAG_UART + +/* The alarm function in altera_avalon_jtag_uart.c. + * This function, when turned on, prints out the status + * of the JTAG UART Control register, every ALT_LOG_JTAG_UART_TICKS. + * If the flag is off, the alarm should never be registered, and this + * function should never run */ +alt_u32 altera_avalon_jtag_uart_report_log(void * context) +{ + if (alt_log_jtag_uart_alarm_on_flag) { + altera_avalon_jtag_uart_state* dev = (altera_avalon_jtag_uart_state*) context; + const char* header="JTAG Alarm:"; + alt_log_jtag_uart_print_control_reg(dev, dev->base, header); + return ALT_LOG_JTAG_UART_TICKS; + } + else + { + /* If flag is not on, return 0 to disable future alarms. + * Should never be here, alarm should not be enabled at all. */ + return 0; + } +} + +void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, int base, const char* header) +{ + unsigned int control, space, ac, wi, ri, we, re; + control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + we= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST; + re= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST; + ri= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST; + wi= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST; + ac= (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST; + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + ALT_LOG_PRINTF( + "%s HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,space,ac,wi,ri,we,re); +#else + ALT_LOG_PRINTF( + "%s SW CirBuf = %d, HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,(dev->tx_out-dev->tx_in),space,ac,wi,ri,we,re); +#endif + + return; + +} + +/* In altera_avalon_jtag_uart.c + * Same output as the alarm function above, but this is called in the driver + * init function. Hence, it gives the status of the JTAG UART control register + * right at the initialization of the driver */ +void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base) +{ + const char* header="JTAG Startup Info:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + return; +} + +/* In altera_avalon_jtag_uart.c + * When turned on, this function will print out the status of the jtag uart + * control register every time there is a jtag uart "almost-empty" interrupt. */ +void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev) +{ + if (alt_log_jtag_uart_isr_on_flag) { + const char* header="JTAG IRQ:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + } + return; +} + +#endif /* __ALTERA_AVALON_JTAG_UART */ + +/* In alt_write.c + * When the alt_log_write_on_flag is turned on, this function gets called + * every time alt_write gets called. The first + * ALT_LOG_WRITE_ECHO_LEN characters of every printf command (or any command + * that eventually calls write()) gets echoed to the alt_log output. */ +void alt_log_write(const void *ptr, size_t len) +{ + if (alt_log_write_on_flag) { + int temp_cnt; + int length=(ALT_LOG_WRITE_ECHO_LEN>len) ? len : ALT_LOG_WRITE_ECHO_LEN; + + if (length < 2) return; + + strncpy (alt_log_write_buf,ptr,length); + alt_log_write_buf[length-1]='\n'; + alt_log_write_buf[length]='\r'; + alt_log_write_buf[length+1]='\0'; + + /* Escape Ctrl-D's. If the Ctrl-D gets sent it might kill the terminal + * connection of alt_log. It will get replaced by 'D'. */ + for (temp_cnt=0;temp_cnt < length; temp_cnt++) { + if (alt_log_write_buf[temp_cnt]== 0x4) { + alt_log_write_buf[temp_cnt]='D'; + } + } + ALT_LOG_PRINTF("Write Echo: %s",alt_log_write_buf); + } +} + +/* In altera_avalon_timer_sc + * This function prints out a system clock is alive message + * every ALT_LOG_SYS_CLK_INTERVAL (in ticks). */ +void alt_log_system_clock() +{ + if (alt_log_sys_clk_on_flag) { + alt_log_sys_clk_count++; + if (alt_log_sys_clk_count > ALT_LOG_SYS_CLK_INTERVAL) { + alt_log_sys_clk_count = 0; + ALT_LOG_PRINTF("System Clock On %u\r\n",alt_system_clock_in_sec++); + } + } +} + + +#endif diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_lseek.c b/software/DE2_115_ASM_bsp/HAL/src/alt_lseek.c new file mode 100644 index 0000000..a56dbfb --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_lseek.c @@ -0,0 +1,117 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(lseek); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * lseek() can be called to move the read/write pointer associated with the + * file descriptor "file". This function simply vectors the call to the lseek() + * function provided by the driver associated with the file descriptor. + * + * If the driver does not provide an implementation of lseek() an error is + * indicated. + * + * lseek() corresponds to the standard lseek() function. + * + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + alt_fd* fd; + off_t rc = 0; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + { + rc = fd->dev->lseek(fd, ptr, dir); + } + /* + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + } + } + else + { + rc = -EBADFD; + } + + if (rc < 0) + { + ALT_ERRNO = -rc; + rc = -1; + } + + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_main.c b/software/DE2_115_ASM_bsp/HAL/src/alt_main.c new file mode 100644 index 0000000..33e3463 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_main.c @@ -0,0 +1,161 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_sys_init.h" +#include "sys/alt_irq.h" +#include "sys/alt_dev.h" + +#include "os/alt_hooks.h" + +#include "priv/alt_file.h" +#include "alt_types.h" + +#include "system.h" + +#include "sys/alt_log_printf.h" + +extern void _do_ctors(void); +extern void _do_dtors(void); + +/* + * Standard arguments for main. By default, no arguments are passed to main. + * However a device driver may choose to configure these arguments by calling + * alt_set_args(). The expectation is that this facility will only be used by + * the iclient/ihost utility. + */ + +int alt_argc = 0; +char** alt_argv = {NULL}; +char** alt_envp = {NULL}; + +/* + * Prototype for the entry point to the users application. + */ + +extern int main (int, char **, char **); + +/* + * alt_main is the C entry point for the HAL. It is called by the assembler + * startup code in the processor specific crt0.S. It is responsible for: + * completing the C runtime configuration; configuring all the + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ +#ifndef ALT_NO_EXIT + int result; +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + + /* + * Initialize the semaphore used to control access to the file descriptor + * list. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_sys_init.\r\n"); + +#if !defined(ALT_USE_DIRECT_DRIVERS) && (defined(ALT_STDIN_PRESENT) || defined(ALT_STDOUT_PRESENT) || defined(ALT_STDERR_PRESENT)) + + /* + * Redirect stdio to the apropriate devices now that the devices have + * been initialized. This is only done if the user has requested these + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); +#endif + +#ifndef ALT_NO_C_PLUS_PLUS + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); +#endif /* ALT_NO_C_PLUS_PLUS */ + +#if !defined(ALT_NO_C_PLUS_PLUS) && !defined(ALT_NO_CLEAN_EXIT) && !defined(ALT_NO_EXIT) + /* + * Set the C++ destructors to be called at system shutdown. This is only done + * if a clean exit has been requested (i.e. the exit() function has not been + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); +#endif + + /* + * Finally, call main(). The return code is then passed to a subsequent + * call to exit() unless the application is never supposed to exit. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + close(STDOUT_FILENO); + exit (result); +#endif + + ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n"); +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_malloc_lock.c b/software/DE2_115_ASM_bsp/HAL/src/alt_malloc_lock.c new file mode 100644 index 0000000..89c2dd4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_malloc_lock.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +/* + * These are the empty malloc lock/unlock stubs required by newlib. These are + * used to make newlib's malloc() function thread safe. The default HAL + * configuration is single threaded, so there is nothing to do here. Note that + * this requires that malloc is never called by an interrupt service routine. + */ + +void __malloc_lock ( struct _reent *_r ) +{ +} + +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_mcount.S b/software/DE2_115_ASM_bsp/HAL/src/alt_mcount.S new file mode 100644 index 0000000..cf510da --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_mcount.S @@ -0,0 +1,198 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* mcount or _mcount is inserted by GCC before the function prologue of every + * function when a program is compiled for profiling. At the start of mcount, + * we guarantee that: + * ra = self_pc (an address in the function which called mcount) + * r8 = from_pc (an address in the function which called mcount's caller) + * + * Because this is always called at the start of a function we can corrupt + * r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain + * function arguments for the instrumented function) or r8 (which holds ra + * for the instrumented function). + */ + + .global __mcount_fn_head + + .global mcount + + /* _mcount is used by gcc4 */ + .global _mcount + +_mcount: +mcount: + /* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose + * the bucket because bits 1:0 will always be 0, and because the distribution + * of values for bits 4:2 won't be even (aligning on cache line boundaries + * will skew it). Higher bits should be fairly random. + */ + /* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */ + + srli r2, ra, 3 + movhi r3, %hiadj(__mcount_fn_head) + addi r3, r3, %lo(__mcount_fn_head) + andi r2, r2, 0xFC + add r11, r2, r3 + + /* The fast case is where we have already allocated a function arc, and so + * also a function pointer. + */ + + /* First find the function being called (using self_pc) */ + mov r10, r11 +0: + ldw r10, 0(r10) + beq r10, zero, .Lnew_arc + ldw r2, 4(r10) + bne r2, ra, 0b + + /* Found a function entry for this PC. Now look for an arc with a matching + * from_pc value. There will always be at least one arc. */ + ldw r3, 8(r10) +0: + ldw r2, 4(r3) + beq r2, r8, .Lfound_arc + ldw r3, 0(r3) + bne r3, zero, 0b + +.Lnew_arc: + addi sp, sp, -24 + +.LCFI0: + stw ra, 0(sp) + stw r4, 4(sp) + stw r5, 8(sp) + stw r6, 12(sp) + stw r7, 16(sp) + stw r8, 20(sp) + +.LCFI1: + /* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */ + mov r4, ra + mov r5, r8 + mov r6, r10 + mov r7, r11 + call __mcount_record + + /* restore registers from the stack */ + ldw ra, 0(sp) + ldw r4, 4(sp) + ldw r5, 8(sp) + ldw r6, 12(sp) + ldw r7, 16(sp) + ldw r8, 20(sp) + + addi sp, sp, 24 + +.LCFI2: + ret + +.Lfound_arc: + /* We've found the correct arc record. Increment the count and return */ + ldw r2, 8(r3) + addi r2, r2, 1 + stw r2, 8(r3) + ret + +.Lmcount_end: + + + +/* + * Dwarf2 debug information for the function. This provides GDB with the + * information it needs to backtrace out of this function. + */ + + .section .debug_frame,"",@progbits +.LCIE: + .4byte 2f - 1f /* Length */ +1: + .4byte 0xffffffff /* CIE id */ + .byte 0x1 /* Version */ + .string "" /* Augmentation */ + .uleb128 0x1 /* Code alignment factor */ + .sleb128 -4 /* Data alignment factor */ + .byte 0x1f /* Return address register */ + + .byte 0xc /* Define CFA */ + .uleb128 0x1b /* Register 27 (sp) */ + .uleb128 0x0 /* Offset 0 */ + + .align 2 /* Padding */ +2: + +.LFDE_mcount: + .4byte 2f - 1f /* Length */ +1: + .4byte .LCIE /* Pointer to CIE */ + .4byte mcount /* Start of table entry */ + .4byte .Lmcount_end - mcount /* Size of table entry */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI0 - mcount /* to .LCFI0 */ + .byte 0xe /* Define CFA offset */ + .uleb128 24 /* to 24 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI1 - .LCFI0 /* to .LCFI1 */ + .byte 0x9f /* Store ra */ + .uleb128 0x6 /* at CFA-24 */ + .byte 0x84 /* Store r4 */ + .uleb128 0x5 /* at CFA-20 */ + .byte 0x85 /* Store r5 */ + .uleb128 0x4 /* at CFA-16 */ + .byte 0x86 /* Store r6 */ + .uleb128 0x3 /* at CFA-12 */ + .byte 0x87 /* Store r7 */ + .uleb128 0x2 /* at CFA-8 */ + .byte 0x88 /* Store r8 */ + .uleb128 0x1 /* at CFA-4 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI2 - .LCFI1 /* to .LCFI2 */ + .byte 0xe /* Define CFA offset */ + .uleb128 0 /* to 0 */ + .byte 0x8 /* Same value */ + .uleb128 31 /* for ra */ + .byte 0x8 /* Same value */ + .uleb128 4 /* for r4 */ + .byte 0x8 /* Same value */ + .uleb128 5 /* for r5 */ + .byte 0x8 /* Same value */ + .uleb128 6 /* for r6 */ + .byte 0x8 /* Same value */ + .uleb128 7 /* for r7 */ + .byte 0x8 /* Same value */ + .uleb128 8 /* for r8 */ + + .align 2 +2: + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_open.c b/software/DE2_115_ASM_bsp/HAL/src/alt_open.c new file mode 100644 index 0000000..d7040bc --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_open.c @@ -0,0 +1,173 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_OPEN (const char* file, int flags, int mode) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(open); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +extern alt_llist alt_dev_list; + +/* + * alt_file_locked() is used by open() to ensure that a device has not been + * previously locked for exclusive access using ioctl(). This test is only + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + alt_u32 i; + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + { + if ((alt_fd_list[i].dev == fd->dev) && + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + } + } + + /* The device is not locked */ + + return 0; +} + +/* + * open() is called in order to get a file descriptor that reference the file + * or device named "name". This descriptor can then be used to manipulate the + * file/device using the standard system calls, e.g. write(), read(), ioctl() + * etc. + * + * This is equivalent to the standard open() system call. + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + alt_dev* dev; + alt_fd* fd; + int index = -1; + int status = -ENODEV; + int isafs = 0; + + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + isafs = 1; + } + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + { + if ((index = alt_get_fd (dev)) < 0) + { + status = index; + } + else + { + fd = &alt_fd_list[index]; + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + { + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + } + } + } + else + { + status = -ENODEV; + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + { + alt_release_fd (index); + ALT_ERRNO = -status; + return -1; + } + + /* return the reference upon success */ + + return index; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_printf.c b/software/DE2_115_ASM_bsp/HAL/src/alt_printf.c new file mode 100644 index 0000000..fe5bcd3 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_printf.c @@ -0,0 +1,127 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file provides a very minimal printf implementation for use with very + * small applications. Only the following format strings are supported: + * %x + * %s + * %c + * %% + */ + +#include +#include "sys/alt_stdio.h" + +/* + * ALT printf function + */ +void +alt_printf(const char* fmt, ... ) +{ + va_list args; + va_start(args, fmt); + const char *w; + char c; + + /* Process format string. */ + w = fmt; + while ((c = *w++) != 0) + { + /* If not a format escape character, just print */ + /* character. Otherwise, process format string. */ + if (c != '%') + { + alt_putchar(c); + } + else + { + /* Get format character. If none */ + /* available, processing is complete. */ + if ((c = *w++) != 0) + { + if (c == '%') + { + /* Process "%" escape sequence. */ + alt_putchar(c); + } + else if (c == 'c') + { + int v = va_arg(args, int); + alt_putchar(v); + } + else if (c == 'x') + { + /* Process hexadecimal number format. */ + unsigned long v = va_arg(args, unsigned long); + unsigned long digit; + int digit_shift; + + /* If the number value is zero, just print and continue. */ + if (v == 0) + { + alt_putchar('0'); + continue; + } + + /* Find first non-zero digit. */ + digit_shift = 28; + while (!(v & (0xF << digit_shift))) + digit_shift -= 4; + + /* Print digits. */ + for (; digit_shift >= 0; digit_shift -= 4) + { + digit = (v & (0xF << digit_shift)) >> digit_shift; + if (digit <= 9) + c = '0' + digit; + else + c = 'a' + digit - 10; + alt_putchar(c); + } + } + else if (c == 's') + { + /* Process string format. */ + char *s = va_arg(args, char *); + + while(*s) + alt_putchar(*s++); + } + } + else + { + break; + } + } + } +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_putchar.c b/software/DE2_115_ASM_bsp/HAL/src/alt_putchar.c new file mode 100644 index 0000000..900bb9f --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_putchar.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided putchar() routine. + */ +int +alt_putchar(int c) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + char c1 = (char)(c & 0xff); + + if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) { + return -1; + } + return c; +#else + return putchar(c); +#endif +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_putstr.c b/software/DE2_115_ASM_bsp/HAL/src/alt_putstr.c new file mode 100644 index 0000000..131ba19 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_putstr.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided fputs() routine. + */ +int +alt_putstr(const char* str) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0); +#else + return fputs(str, stdout); +#endif +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_read.c b/software/DE2_115_ASM_bsp/HAL/src/alt_read.c new file mode 100644 index 0000000..920ab13 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_read.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The read() system call is used to read a block of data from a file or device. + * This function simply vectors the request to the device driver associated + * with the input file descriptor "file". + * + * ALT_READ is mapped onto the read() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just reads from the stdin device when provided. + */ + +int ALT_READ (int file, void *ptr, size_t len) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(read); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_READ(ALT_STDIN_DEV, ptr, len, 0); +#endif /* ALT_STDIN_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_release_fd.c b/software/DE2_115_ASM_bsp/HAL/src/alt_release_fd.c new file mode 100644 index 0000000..c22a97f --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_release_fd.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * alt_release_fd() is called to free an allocated file descriptor. This is + * done by setting the device pointer in the file descriptor structure to zero. + * + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + if (fd > 2) + { + alt_fd_list[fd].fd_flags = 0; + alt_fd_list[fd].dev = 0; + } +} + + + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_remap_cached.c b/software/DE2_115_ASM_bsp/HAL/src/alt_remap_cached.c new file mode 100644 index 0000000..6afc465 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_remap_cached.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +void* alt_remap_cached (volatile void* ptr, alt_u32 len) +{ + return (void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_remap_uncached.c b/software/DE2_115_ASM_bsp/HAL/src/alt_remap_uncached.c new file mode 100644 index 0000000..e533f94 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_remap_uncached.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +volatile void* alt_remap_uncached (void* ptr, alt_u32 len) +{ + alt_dcache_flush (ptr, len); + return (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_rename.c b/software/DE2_115_ASM_bsp/HAL/src/alt_rename.c new file mode 100644 index 0000000..26db44d --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_rename.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * _rename() is used by newlib to rename an existing file. This is unsupported + * in the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_RENAME is mapped onto the _rename() system call in alt_syscall.h + */ + +int ALT_RENAME (char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(_rename); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_sbrk.c b/software/DE2_115_ASM_bsp/HAL/src/alt_sbrk.c new file mode 100644 index 0000000..7ab3367 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_sbrk.c @@ -0,0 +1,136 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "os/alt_syscall.h" + +#include "sys/alt_irq.h" +#include "sys/alt_stack.h" + +#include "system.h" + +/* + * sbrk() is called to dynamically extend the data segment for the application. + * Thie input argument "incr" is the size of the block to allocate. + * + * This simple implementation does not perform any bounds checking. Memory will + * be allocated, even if the request region colides with the stack or overflows + * the available physical memory. + * + * ALT_SBRK is mapped onto the sbrk() system call in alt_syscall.h + * + * This function is called by the profiling code to allocate memory so must be + * safe if called from an interrupt context. It must also not be instrumented + * because that would lead to an infinate loop. + */ + +extern char __alt_heap_start[]; /* set by linker */ +extern char __alt_heap_limit[]; /* set by linker */ + +static char *heap_end = __alt_heap_start; + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) +char * alt_exception_old_stack_limit = NULL; +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + +#ifdef ALT_MAX_HEAP_BYTES + /* + * User specified a maximum heap size. Return -1 if it would + * be exceeded by this sbrk call. + */ + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#endif + + prev_heap_end = heap_end; + heap_end += incr; + +#ifdef ALT_STACK_CHECK + /* + * If the stack and heap are contiguous then extending the heap reduces the + * space available for the stack. If we are still using the default stack + * then adjust the stack limit to note this, while checking for stack + * pointer overflow. + * If the stack limit isn't pointing at the top of the heap then the code + * is using a different stack so none of this needs to be done. + */ + + if (alt_stack_limit() == prev_heap_end) + { + if (alt_stack_pointer() <= heap_end) + alt_report_stack_overflow(); + + alt_set_stack_limit(heap_end); + } + +#ifdef ALT_EXCEPTION_STACK + /* + * If we are executing from the exception stack then compare against the + * stack we switched away from as well. The exception stack is a fixed + * size so doesn't need to be checked. + */ + + if (alt_exception_old_stack_limit == prev_heap_end) + { + if (alt_exception_old_stack_limit <= heap_end) + alt_report_stack_overflow(); + + alt_exception_old_stack_limit = heap_end; + } +#endif + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_settod.c b/software/DE2_115_ASM_bsp/HAL/src/alt_settod.c new file mode 100644 index 0000000..13349b8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_settod.c @@ -0,0 +1,96 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +extern struct timezone alt_timezone; +extern struct timeval alt_resettime; + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + + +/* + * settimeofday() can be called to calibrate the system clock, so that + * subsequent calls to gettimeofday() will return the elapsed "wall clock" + * time. + * + * This is done by updating the global structures "alt_resettime" and + * "alt_timezone" so that an immediate call to gettimeofday() would return + * the value specified by "t" and "tz". + * + * Warning: if this function is called concurrently with a call to + * gettimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_SETTIMEOFDAY is mapped onto the settimeofday() system call in + * alt_syscall.h + */ + +int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz) +{ + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* If there is a system clock available, update the current time */ + + if (tick_rate) + { + alt_resettime.tv_sec = t->tv_sec - nticks/tick_rate; + alt_resettime.tv_usec = t->tv_usec - + ((nticks*(ALT_US/tick_rate))%ALT_US); + + alt_timezone.tz_minuteswest = tz->tz_minuteswest; + alt_timezone.tz_dsttime = tz->tz_dsttime; + + return 0; + } + + /* There's no system clock available */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_software_exception.S b/software/DE2_115_ASM_bsp/HAL/src/alt_software_exception.S new file mode 100644 index 0000000..0a9381e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_software_exception.S @@ -0,0 +1,53 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This file provides the global symbol: software_exception. It is provided to + * support legacy code, and should not be used by new software. + * + * It is used by legacy code to invoke the software exception handler as + * defined by version 1.0 of the Nios II kit. It should only be used when you + * are providing your own interrupt entry point, i.e. you are not using + * alt_irq_entry. + */ + +#include "system.h" + + /* + * Pull in the exception handler. + */ + + .globl alt_exception + + .section .exceptions.entry.label, "xa" + + .globl software_exception + .type software_exception, @function +software_exception: diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_stat.c b/software/DE2_115_ASM_bsp/HAL/src/alt_stat.c new file mode 100644 index 0000000..c196d0c --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_stat.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "os/alt_syscall.h" + +/* + * The stat() function is similar to the fstat() function in that it is used to + * obtain status information about a file. Instead of using an open file + * descriptor (like fstat()), stat() takes the name of a file as an input + * argument. + * + * ALT_STAT is mapped onto the stat() system call in alt_syscall.h + */ + +int ALT_STAT (const char *file, struct stat *st) +{ + int fd; + int rc; + + fd = open (file, 0); + rc = fstat (fd, st); + close (fd); + + return rc; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_tick.c b/software/DE2_115_ASM_bsp/HAL/src/alt_tick.c new file mode 100644 index 0000000..23719b1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_tick.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "os/alt_hooks.h" +#include "alt_types.h" + +/* + * "_alt_tick_rate" is used to store the value of the system clock frequency + * in ticks per second. It is initialised to zero, which corresponds to there + * being no system clock facility available. + */ + +alt_u32 _alt_tick_rate = 0; + +/* + * "_alt_nticks" is the number of system clock ticks that have elapsed since + * reset. + */ + +volatile alt_u32 _alt_nticks = 0; + +/* + * "alt_alarm_list" is the head of a linked list of registered alarms. This is + * initialised to be an empty list. + */ + +ALT_LLIST_HEAD(alt_alarm_list); + +/* + * alt_alarm_stop() is called to remove an alarm from the list of registered + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + alt_llist_remove (&alarm->llist); + alt_irq_enable_all (irq_context); +} + +/* + * alt_tick() is periodically called by the system clock driver in order to + * process the registered list of alarms. Each alarm is registed with a + * callback interval, and a callback function, "callback". + * + * The return value of the callback function indicates how many ticks are to + * elapse until the next callback. A return value of zero indicates that the + * alarm should be deactivated. + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + { + next = (alt_alarm*) alarm->llist.next; + + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + { + alarm->rollover = 0; + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + { + next_callback = alarm->callback (alarm->context); + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + { + alt_alarm_stop (alarm); + } + else + { + alarm->time += next_callback; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + { + alarm->rollover = 1; + } + } + } + alarm = next; + } + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_times.c b/software/DE2_115_ASM_bsp/HAL/src/alt_times.c new file mode 100644 index 0000000..6543164 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_times.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * The times() function is used by newlib to obtain elapsed time information. + * The return value is the elapsed time since reset in system clock ticks. Note + * that this is distinct from the strict Posix version of times(), which should + * return the time since: 0 hours, 0 minutes, 0 seconds, January 1, 1970, GMT. + * + * The input structure is filled in with time accounting information. This + * implementation attributes all cpu time to the system. + * + * ALT_TIMES is mapped onto the times() system call in alt_syscall.h + */ + +clock_t ALT_TIMES (struct tms *buf) +{ + clock_t ticks = alt_nticks(); + + /* If there is no system clock present, generate an error */ + + if (!alt_ticks_per_second()) + { + ALT_ERRNO = ENOSYS; + return 0; + } + + /* Otherwise return the elapsed time */ + + buf->tms_utime = 0; + buf->tms_stime = ticks; + buf->tms_cutime = 0; + buf->tms_cstime = 0; + + return ticks; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_uncached_free.c b/software/DE2_115_ASM_bsp/HAL/src/alt_uncached_free.c new file mode 100644 index 0000000..37f4ac1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_uncached_free.c @@ -0,0 +1,49 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Free a block of uncached memory. + */ + +void alt_uncached_free (volatile void* ptr) +{ + free ((void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK)); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_uncached_malloc.c b/software/DE2_115_ASM_bsp/HAL/src/alt_uncached_malloc.c new file mode 100644 index 0000000..325132e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_uncached_malloc.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Allocate a block of uncached memory. + */ + +volatile void* alt_uncached_malloc (size_t size) +{ + void* ptr; + + ptr = malloc (size); + + alt_dcache_flush (ptr, size); + + return ptr ? (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK) : NULL; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_unlink.c b/software/DE2_115_ASM_bsp/HAL/src/alt_unlink.c new file mode 100644 index 0000000..606f019 --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_unlink.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * unlink() is used by newlib to delete an existing link to a file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_UNLINK is mapped onto the unlink() system call in alt_syscall.h + */ + +int ALT_UNLINK (char *name) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(unlink); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_usleep.c b/software/DE2_115_ASM_bsp/HAL/src/alt_usleep.c new file mode 100644 index 0000000..eea89cd --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_usleep.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + * + * usleep.c - Microsecond delay routine + */ + +#include + +#include "priv/alt_busy_sleep.h" +#include "os/alt_syscall.h" + +/* + * This function simply calls alt_busy_sleep() to perform the delay. This + * function implements the delay as a calibrated "busy loop". + * + * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h + */ + + + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us) +#else +unsigned int ALT_USLEEP (unsigned int us) +#endif +{ + return alt_busy_sleep(us); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_wait.c b/software/DE2_115_ASM_bsp/HAL/src/alt_wait.c new file mode 100644 index 0000000..dd768ad --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_wait.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * wait() is used by newlib to wait for all child processes to exit. Since the + * HAL does not support spawning child processes, this returns immediately as + * there can't be anythign to wait for. + * + * ALT_WAIT is mapped onto the wait() system call in alt_syscall.h + */ + +int ALT_WAIT (int *status) +{ + *status = 0; + + ALT_ERRNO = ECHILD; + + return -1; +} + diff --git a/software/DE2_115_ASM_bsp/HAL/src/alt_write.c b/software/DE2_115_ASM_bsp/HAL/src/alt_write.c new file mode 100644 index 0000000..d161cdf --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/alt_write.c @@ -0,0 +1,138 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#include "sys/alt_log_printf.h" + +/* + * The write() system call is used to write a block of data to a file or + * device. This function simply vectors the request to the device driver + * associated with the input file descriptor "file". + * + * ALT_WRITE is mapped onto the write() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just writes to the stdout/stderr devices + * when provided. + */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(write); +#endif + + switch (file) { +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, ptr, len, 0); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDERR_DEV, ptr, len, 0); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/software/DE2_115_ASM_bsp/HAL/src/altera_nios2_qsys_irq.c b/software/DE2_115_ASM_bsp/HAL/src/altera_nios2_qsys_irq.c new file mode 100644 index 0000000..c719dbc --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/altera_nios2_qsys_irq.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * altera_nios2_irq.c - Support for Nios II internal interrupt controller. + * + */ + +#include "sys/alt_irq.h" +#include "altera_nios2_qsys_irq.h" + +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + NIOS2_WRITE_IENABLE(0); +} diff --git a/software/DE2_115_ASM_bsp/HAL/src/crt0.S b/software/DE2_115_ASM_bsp/HAL/src/crt0.S new file mode 100644 index 0000000..739e45e --- /dev/null +++ b/software/DE2_115_ASM_bsp/HAL/src/crt0.S @@ -0,0 +1,456 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" +#include "nios2.h" + +/* Setup header files to work with assembler code. */ +#define ALT_ASM_SRC + +/* Debug logging facility */ +#include "sys/alt_log_printf.h" + +/*************************************************************************\ +| MACROS | +\*************************************************************************/ + +/* + * The new build tools explicitly define macros when alt_load() + * must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that + * those macros are controlling if alt_load() needs to be called. + */ +#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED + +/* Need to call alt_load() if any of these sections are being copied. */ +#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS) +#define CALL_ALT_LOAD +#endif + +#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * The legacy build tools use the following macros to detect when alt_load() + * needs to be called. + */ + +#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + ((res##_BASE != rodata##_BASE) || \ + (res##_BASE != rwdata##_BASE) || \ + (res##_BASE != exc##_BASE)) + +#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + __ALT_LOAD_SECTIONS(res, text, rodata, exc) + +#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \ + ALT_RODATA_DEVICE, \ + ALT_RWDATA_DEVICE, \ + ALT_EXCEPTIONS_DEVICE) + +/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */ +#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS +#define CALL_ALT_LOAD +#endif + +#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * When the legacy build tools define a macro called ALT_NO_BOOTLOADER, + * it indicates that initialization code is allowed at the reset address. + * The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for + * the same purpose. + */ +#ifdef ALT_NO_BOOTLOADER +#define ALT_ALLOW_CODE_AT_RESET +#endif + +/*************************************************************************\ +| EXTERNAL REFERENCES | +\*************************************************************************/ + +/* + * The entry point for user code is either "main" in hosted mode, or + * "alt_main" in standalone mode. These are explicitly referenced here, + * to ensure they are built into the executable. This allows the user + * to build them into libraries, rather than supplying them in object + * files at link time. + */ + .globl main + .globl alt_main + +/* + * Create a reference to the software multiply/divide and trap handers, + * so that if they are provided, they will appear in the executable. + */ +#ifndef ALT_NO_INSTRUCTION_EMULATION + .globl alt_exception_muldiv +#endif +#ifdef ALT_TRAP_HANDLER + .globl alt_exception_trap +#endif + +/* + * Linker defined symbols used to initialize bss. + */ +.globl __bss_start +.globl __bss_end + +/*************************************************************************\ +| RESET SECTION (.entry) | +\*************************************************************************/ + +/* + * This is the reset entry point for Nios II. + * + * At reset, only the cache line which contain the reset vector is + * initialized by the hardware. The code within the first cache line + * initializes the remainder of the instruction cache. + */ + + .section .entry, "xa" + .align 5 + +/* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + +/* + * Some tools want to know where the reset vector is. + * Code isn't always provided at the reset vector but at least the + * __reset label always contains the reset vector address because + * it is defined at the start of the .entry section. + */ + + .globl __reset + .type __reset, @function +__reset: + +/* + * Initialize the instruction cache if present (i.e. size > 0) and + * reset code is allowed unless optimizing for RTL simulation. + * RTL simulations can ensure the instruction cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE +#endif + +0: + initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 1, 1, 0b, 1b + .popsection +#endif /* Initialize Instruction Cache */ + +/* + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + ori r1, r1, %lo(_start) + jmp r1 + + .size __reset, . - __reset +#endif /* Jump to _start */ + +/* + * When not using exit, provide an _exit symbol to prevent unresolved + * references to _exit from the linker script. + */ +#ifdef ALT_NO_EXIT + .globl _exit +_exit: +#endif + +/*************************************************************************\ +| TEXT SECTION (.text) | +\*************************************************************************/ + +/* + * Start of the .text section, and also the code entry point when + * the code is executed by a bootloader rather than directly from reset. + */ + .section .text + .align 2 + + .globl _start + .type _start, @function +_start: + +/* + * Initialize the data cache if present (i.e. size > 0) and not + * optimizing for RTL simulation. + * RTL simulations can ensure the data cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_DCACHE_SIZE > 0 && !defined(ALT_SIM_OPTIMIZE) + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE +#endif + +0: + initd 0(r2) + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 2, 1, 0b, 1b + .popsection + +#endif /* Initialize Data Cache */ + + /* Log that caches have been initialized. */ + ALT_LOG_PUTS(alt_log_msg_cache) + + /* Log that the stack pointer is about to be setup. */ + ALT_LOG_PUTS(alt_log_msg_stackpointer) + +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +#else /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */ + + /* + * Set up the GP and SP in all shadow register sets. + */ + + /* + * Check current register set number, if CPU resets into a shadow register + * set, switch register set to 0 by writing zero to SSTATUS register and + * execute an ERET instruction that just jumps to the next PC address + * (use the NEXTPC instruction to get this). + */ + + rdctl r2, status + + /* Get the current register set number (STATUS.CRS). */ + andi r3, r2, NIOS2_STATUS_CRS_MSK + + /* Skip switch register set if STATUS.CRS is 0. */ + beq r3, zero, .Lskip_switch_reg_set + + .set nobreak + + /* Current register set is non-zero, set SSTATUS to 0. */ + mov sstatus, zero + + /* Get next pc and store in ea. */ + nextpc ea + + /* Point to instruction after eret. */ + addi ea, ea, 8 + + /* + * Execute ERET instruction that just jumps to the next PC address + */ + eret + +.Lskip_switch_reg_set: + mov r2, zero + + /* Reset STATUS register */ + wrctl status, r2 + + movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS + + /* Set up the stack pointer in register set 0. */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer in register set 0. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +.Lsetup_sp_and_gp_loop: + /* + * Setup GP and SP for shadow register set + * from NIOS2_NUM_OF_SHADOW_REG_SETS to 0 + */ + + /* Skip if number of register sets is 0. */ + beq r3, zero, .Lno_shadow_register_set + + + /* Add previous register set STATUS.PRS by 1 */ + movhi r4, 1 + add r2, r2, r4 + + /* Write STATUS */ + wrctl status, r2 + + /* Clear r0 in the shadow register set (not done by hardware) */ + wrprs r0, r0 + + /* Write the GP in previous register set */ + wrprs gp, gp + + /* Only write the SP in previous register set + * if using the seperate exception stack. For normal case (single stack), + * funnel code would read the SP from previous register set. + */ +#ifdef ALT_INTERRUPT_STACK + + movhi et, %hiadj(__alt_interrupt_stack_pointer) + addi et, et, %lo(__alt_interrupt_stack_pointer) + wrprs sp, et + +#endif /* ALT_INTERRUPT_STACK */ + + /* Decrease number of register set counter by 1 */ + addi r3, r3, -1 + + br .Lsetup_sp_and_gp_loop +.Lno_shadow_register_set: + +#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS */ +/* + * Clear the BSS if not optimizing for RTL simulation. + * + * This uses the symbols: __bss_start and __bss_end, which are defined + * by the linker script. They mark the begining and the end of the bss + * region. The linker script guarantees that these values are word aligned. + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + ori r2, r2, %lo(__bss_start) + + movhi r3, %hi(__bss_end) + ori r3, r3, %lo(__bss_end) + + beq r2, r3, 1f + +0: + stw zero, (r2) + addi r2, r2, 4 + bltu r2, r3, 0b + +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 3, 1, 0b, 1b + .popsection +#endif /* ALT_SIM_OPTIMIZE */ + +/* + * The alt_load() facility is normally used when there is no bootloader. + * It copies some sections into RAM so it acts like a mini-bootloader. + */ +#ifdef CALL_ALT_LOAD + +#ifdef ALT_STACK_CHECK + /* + * If the user has selected stack checking then we need to set up a safe + * value in the stack limit register so that the relocation functions + * don't think the stack has overflowed (the contents of the rwdata + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + +#endif /* CALL_ALT_LOAD */ + +#ifdef ALT_STACK_CHECK + /* + * Set up the stack limit (if required). The linker has set up the + * copy of the variable which is in memory. + */ + + ldw et, %gprel(alt_stack_limit_value)(gp) +#endif + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + + .size _start, . - _start + +/* + * Add information about the stack base if stack overflow checking is enabled. + */ +#ifdef ALT_STACK_CHECK + .globl alt_stack_limit_value + .section .sdata,"aws",@progbits + .align 2 + .type alt_stack_limit_value, @object + .size alt_stack_limit_value, 4 +alt_stack_limit_value: + .long __alt_stack_limit +#endif diff --git a/software/DE2_115_ASM_bsp/Makefile b/software/DE2_115_ASM_bsp/Makefile new file mode 100644 index 0000000..0e63d38 --- /dev/null +++ b/software/DE2_115_ASM_bsp/Makefile @@ -0,0 +1,775 @@ +#------------------------------------------------------------------------------ +# BSP MAKEFILE +# +# This makefile was automatically generated by the nios2-bsp-generate-files +# command. Its purpose is to build a custom Board Support Package (BSP) +# targeting a specific Nios II processor in an SOPC Builder-based design. +# +# To create an application or library Makefile which uses this BSP, try the +# nios2-app-generate-makefile or nios2-lib-generate-makefile commands. +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +MKDIR := mkdir -p +ECHO := echo +SPACE := $(empty) $(empty) + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC is defined, Make is launched from Windows through +# Cygwin. This adjust-path macro will call 'cygpath -u' on all +# paths to ensure they are readable by Make. +# +# If COMSPEC is not defined, Make is launched from *nix, and no adjustment +# is necessary +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # !COMSPEC + +ifdef COMSPEC + adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1")) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1")) +else + adjust-path = $(subst $(SPACE),\$(SPACE),$1) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1) +endif + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +# +# The default target, "all", must appear before any other target in the +# Makefile. Note that extra prerequisites are added to the "all" rule later. +#------------------------------------------------------------------------------ +.PHONY: all +all: + @$(ECHO) [BSP build complete] + + +#------------------------------------------------------------------------------ +# PATHS & DIRECTORY NAMES +# +# Explicitly locate absolute path of the BSP root +#------------------------------------------------------------------------------ + +BSP_ROOT_DIR := . + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd)) + +# Stash all BSP object files here +OBJ_DIR := ./obj + +NEWLIB_DIR = $(BSP_ROOT_DIR)/newlib + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +# +# Note that most variable assignments in this section have a corresponding BSP +# setting that can be changed by using the nios2-bsp-create-settings or +# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you +# want any variable set to a specific value when this Makefile is re-generated +# (to prevent hand-edits from being over-written), use the BSP settings +# facilities above. +#------------------------------------------------------------------------------ + +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PRIVATE_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +SETTINGS_FILE := settings.bsp +SOPC_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + +#------------------------------------------------------------------------------- +# TOOL & COMMAND DEFINITIONS +# +# The base command for each build operation are expressed here. Additional +# switches may be expressed here. They will run for all instances of the +# utility. +#------------------------------------------------------------------------------- + +# Archiver command. Creates library files. +AR = nios2-elf-ar + +# Assembler command. Note that CC is used for .S files. +AS = nios2-elf-gcc + +# Custom flags only passed to the archiver. This content of this variable is +# directly passed to the archiver rather than the more standard "ARFLAGS". The +# reason for this is that GNU Make assumes some default content in ARFLAGS. +# This setting defines the value of BSP_ARFLAGS in Makefile. +BSP_ARFLAGS = -src + +# Custom flags only passed to the assembler. This setting defines the value of +# BSP_ASFLAGS in Makefile. +BSP_ASFLAGS = -Wa,-gdwarf2 + +# C/C++ compiler debug level. '-g' provides the default set of debug symbols +# typically required to debug a typical application. Omitting '-g' removes +# debug symbols from the ELF. This setting defines the value of +# BSP_CFLAGS_DEBUG in Makefile. +BSP_CFLAGS_DEBUG = -g + +# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" +# optimization, etc. "-O0" is recommended for code that you want to debug since +# compiler optimization can remove variables and produce non-sequential +# execution of code while debugging. This setting defines the value of +# BSP_CFLAGS_OPTIMIZATION in Makefile. +BSP_CFLAGS_OPTIMIZATION = -O0 + +# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines +# the value of BSP_CFLAGS_WARNINGS in Makefile. +BSP_CFLAGS_WARNINGS = -Wall + +# C compiler command. +CC = nios2-elf-gcc -xc + +# C++ compiler command. +CXX = nios2-elf-gcc -xc++ + +# Command used to remove files during 'clean' target. +RM = rm -f + + +#------------------------------------------------------------------------------- +# BUILD PRE & POST PROCESS COMMANDS +# +# The following variables are treated as shell commands in the rule +# definitions for each file-type associated with the BSP build, as well as +# commands run at the beginning and end of the entire BSP build operation. +# Pre-process commands are executed before the relevant command (for example, +# a command defined in the "CC_PRE_PROCESS" variable executes before the C +# compiler for building .c files), while post-process commands are executed +# immediately afterwards. +# +# You can view each pre/post-process command in the "Build Rules: All & +# Clean", "Pattern Rules to Build Objects", and "Library Rules" sections of +# this Makefile. +#------------------------------------------------------------------------------- + + +#------------------------------------------------------------------------------- +# BSP SOURCE BUILD SETTINGS (FLAG GENERATION) +# +# Software build settings such as compiler optimization, debug level, warning +# flags, etc., may be defined in the following variables. The variables below +# are concatenated together in the 'Flags' section of this Makefile to form +# final variables of flags passed to the build tools. +# +# These settings are considered private to the BSP and apply to all library & +# driver files in it; they do NOT automatically propagate to, for example, the +# build settings for an application. +# # For additional detail and syntax requirements, please refer to GCC help +# (example: "nios2-elf-gcc --help --verbose"). +# +# Unless indicated otherwise, multiple entries in each variable should be +# space-separated. +#------------------------------------------------------------------------------- + +# Altera HAL alt_sys_init.c generated source file +GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c +GENERATED_C_LIB_SRCS += alt_sys_init.c + + +#------------------------------------------------------------------------------- +# BSP SOURCE FILE LISTING +# +# All source files that comprise the BSP are listed here, along with path +# information to each file expressed relative to the BSP root. The precise +# list and location of each file is derived from the driver, operating system, +# or software package source file declarations. +# +# Following specification of the source files for each component, driver, etc., +# each source file type (C, assembly, etc.) is concatenated together and used +# to construct a list of objects. Pattern rules to build each object are then +# used to build each file. +#------------------------------------------------------------------------------- + +# altera_avalon_jtag_uart_driver sources root +altera_avalon_jtag_uart_driver_SRCS_ROOT := drivers + +# altera_avalon_jtag_uart_driver sources +altera_avalon_jtag_uart_driver_C_LIB_SRCS := \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_init.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_read.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_write.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_ioctl.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_fd.c + +# altera_avalon_lcd_16207_driver sources root +altera_avalon_lcd_16207_driver_SRCS_ROOT := drivers + +# altera_avalon_lcd_16207_driver sources +altera_avalon_lcd_16207_driver_C_LIB_SRCS := \ + $(altera_avalon_lcd_16207_driver_SRCS_ROOT)/src/altera_avalon_lcd_16207.c \ + $(altera_avalon_lcd_16207_driver_SRCS_ROOT)/src/altera_avalon_lcd_16207_fd.c + +# altera_avalon_pio_driver sources root +altera_avalon_pio_driver_SRCS_ROOT := drivers + +# altera_avalon_pio_driver sources +# altera_nios2_qsys_hal_driver sources root +altera_nios2_qsys_hal_driver_SRCS_ROOT := HAL + +# altera_nios2_qsys_hal_driver sources +altera_nios2_qsys_hal_driver_C_LIB_SRCS := \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/altera_nios2_qsys_irq.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_usleep.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_busy_sleep.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_vars.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_icache_flush.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_icache_flush_all.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_all.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_dcache_flush_no_writeback.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_instruction_exception_entry.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_register.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_iic.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_remap_cached.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_remap_uncached.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_uncached_free.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_uncached_malloc.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_do_ctors.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_do_dtors.c \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_gmon.c + +altera_nios2_qsys_hal_driver_ASM_LIB_SRCS := \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_entry.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_trap.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_exception_muldiv.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_irq_entry.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_software_exception.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_mcount.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/alt_log_macro.S \ + $(altera_nios2_qsys_hal_driver_SRCS_ROOT)/src/crt0.S + +# hal sources root +hal_SRCS_ROOT := HAL + +# hal sources +hal_C_LIB_SRCS := \ + $(hal_SRCS_ROOT)/src/alt_alarm_start.c \ + $(hal_SRCS_ROOT)/src/alt_close.c \ + $(hal_SRCS_ROOT)/src/alt_dev.c \ + $(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \ + $(hal_SRCS_ROOT)/src/alt_dma_rxchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_dma_txchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_environ.c \ + $(hal_SRCS_ROOT)/src/alt_env_lock.c \ + $(hal_SRCS_ROOT)/src/alt_errno.c \ + $(hal_SRCS_ROOT)/src/alt_execve.c \ + $(hal_SRCS_ROOT)/src/alt_exit.c \ + $(hal_SRCS_ROOT)/src/alt_fcntl.c \ + $(hal_SRCS_ROOT)/src/alt_fd_lock.c \ + $(hal_SRCS_ROOT)/src/alt_fd_unlock.c \ + $(hal_SRCS_ROOT)/src/alt_find_dev.c \ + $(hal_SRCS_ROOT)/src/alt_find_file.c \ + $(hal_SRCS_ROOT)/src/alt_flash_dev.c \ + $(hal_SRCS_ROOT)/src/alt_fork.c \ + $(hal_SRCS_ROOT)/src/alt_fs_reg.c \ + $(hal_SRCS_ROOT)/src/alt_fstat.c \ + $(hal_SRCS_ROOT)/src/alt_get_fd.c \ + $(hal_SRCS_ROOT)/src/alt_getchar.c \ + $(hal_SRCS_ROOT)/src/alt_getpid.c \ + $(hal_SRCS_ROOT)/src/alt_gettod.c \ + $(hal_SRCS_ROOT)/src/alt_iic_isr_register.c \ + $(hal_SRCS_ROOT)/src/alt_instruction_exception_register.c \ + $(hal_SRCS_ROOT)/src/alt_ioctl.c \ + $(hal_SRCS_ROOT)/src/alt_io_redirect.c \ + $(hal_SRCS_ROOT)/src/alt_irq_handler.c \ + $(hal_SRCS_ROOT)/src/alt_isatty.c \ + $(hal_SRCS_ROOT)/src/alt_kill.c \ + $(hal_SRCS_ROOT)/src/alt_link.c \ + $(hal_SRCS_ROOT)/src/alt_load.c \ + $(hal_SRCS_ROOT)/src/alt_log_printf.c \ + $(hal_SRCS_ROOT)/src/alt_lseek.c \ + $(hal_SRCS_ROOT)/src/alt_main.c \ + $(hal_SRCS_ROOT)/src/alt_malloc_lock.c \ + $(hal_SRCS_ROOT)/src/alt_open.c \ + $(hal_SRCS_ROOT)/src/alt_printf.c \ + $(hal_SRCS_ROOT)/src/alt_putchar.c \ + $(hal_SRCS_ROOT)/src/alt_putstr.c \ + $(hal_SRCS_ROOT)/src/alt_read.c \ + $(hal_SRCS_ROOT)/src/alt_release_fd.c \ + $(hal_SRCS_ROOT)/src/alt_rename.c \ + $(hal_SRCS_ROOT)/src/alt_sbrk.c \ + $(hal_SRCS_ROOT)/src/alt_settod.c \ + $(hal_SRCS_ROOT)/src/alt_stat.c \ + $(hal_SRCS_ROOT)/src/alt_tick.c \ + $(hal_SRCS_ROOT)/src/alt_times.c \ + $(hal_SRCS_ROOT)/src/alt_unlink.c \ + $(hal_SRCS_ROOT)/src/alt_wait.c \ + $(hal_SRCS_ROOT)/src/alt_write.c + + +# Assemble all component C source files +COMPONENT_C_LIB_SRCS += \ + $(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \ + $(altera_avalon_lcd_16207_driver_C_LIB_SRCS) \ + $(altera_nios2_qsys_hal_driver_C_LIB_SRCS) \ + $(hal_C_LIB_SRCS) + +# Assemble all component assembly source files +COMPONENT_ASM_LIB_SRCS += \ + $(altera_nios2_qsys_hal_driver_ASM_LIB_SRCS) + +# Assemble all component C++ source files +COMPONENT_CPP_LIB_SRCS += \ + +#END MANAGED + +#------------------------------------------------------------------------------ +# PUBLIC.MK +# +# The generated public.mk file contains BSP information that is shared with +# other external makefiles, such as a Nios II application makefile. System- +# dependent information such as hardware-specific compiler flags and +# simulation file generation are stored here. +# +# In addition, public.mk contains include paths that various software, +# such as a device driver, may need for the C compiler. These paths are +# written to public.mk with respect to the BSP root. In public.mk, each +# path is prefixed with a special variable, $(ALT_LIBRARY_ROOT_DIR). The +# purpose of this variable is to allow an external Makefile to append on +# path information to precisely locate paths expressed in public.mk +# Since this is the BSP Makefile, we set ALT_LIBRARY_ROOT_DIR to point right +# here ("."), at the BSP root. +# +# ALT_LIBRARY_ROOT_DIR must always be set before public.mk is included. +#------------------------------------------------------------------------------ +ALT_LIBRARY_ROOT_DIR := . +include public.mk + + +#------------------------------------------------------------------------------ +# FLAGS +# +# Include paths for BSP files are written into the public.mk file and must +# be added to the existing list of pre-processor flags. In addition, "hooks" +# for standard flags left intentionally empty (CFLAGS, CPPFLAGS, ASFLAGS, +# and CXXFLAGS) are provided for conveniently adding to the relevant flags +# on the command-line or via script that calls make. +#------------------------------------------------------------------------------ +# Assemble final list of compiler flags from generated content +BSP_CFLAGS += \ + $(BSP_CFLAGS_DEFINED_SYMBOLS) \ + $(BSP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(BSP_CFLAGS_OPTIMIZATION) \ + $(BSP_CFLAGS_DEBUG) \ + $(BSP_CFLAGS_WARNINGS) \ + $(BSP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Make ready the final list of include directories and other C pre-processor +# flags. Each include path is made ready by prefixing it with "-I". +BSP_CPPFLAGS += \ + $(addprefix -I, $(BSP_INC_DIRS)) \ + $(addprefix -I, $(ALT_INCLUDE_DIRS)) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Finish off assembler flags with any user-provided flags +BSP_ASFLAGS += $(ASFLAGS) + +# Finish off C++ flags with any user-provided flags +BSP_CXXFLAGS += $(CXXFLAGS) + +# And finally, the ordered list +C_SRCS += $(GENERATED_C_LIB_SRCS) \ + $(COMPONENT_C_LIB_SRCS) + +CXX_SRCS += $(GENERATED_CPP_LIB_SRCS) \ + $(COMPONENT_CPP_LIB_SRCS) + +ASM_SRCS += $(GENERATED_ASM_LIB_SRCS) \ + $(COMPONENT_ASM_LIB_SRCS) + + +#------------------------------------------------------------------------------ +# LIST OF GENERATED FILES +# +# A Nios II BSP relies on the generation of several source files used +# by both the BSP and any applications referencing the BSP. +#------------------------------------------------------------------------------ + + +GENERATED_H_FILES := $(ABS_BSP_ROOT)/system.h + +GENERATED_LINKER_SCRIPT := $(ABS_BSP_ROOT)/linker.x + +GENERATED_FILES += $(GENERATED_H_FILES) \ + $(GENERATED_LINKER_SCRIPT) + + +#------------------------------------------------------------------------------ +# SETUP TO BUILD OBJECTS +# +# List of object files which are to be built. This is constructed from the input +# list of C source files (C_SRCS), C++ source files (CXX_SRCS), and assembler +# source file (ASM_SRCS). The permitted file extensions are: +# +# .c .C - for C files +# .cxx .cc .cpp .CXX .CC .CPP - for C++ files +# .S .s - for assembly files +# +# Extended description: The list of objects is a sorted list (duplicates +# removed) of all possible objects, placed beneath the ./obj directory, +# including any path information stored in the "*_SRCS" variable. The +# "patsubst" commands are used to concatenate together multiple file suffix +# types for common files (i.e. c++ as .cxx, .cc, .cpp). +# +# File extensions are case-insensitive in build rules with the exception of +# assembly sources. Nios II assembly sources with the ".S" extension are first +# run through the C preprocessor. Sources with the ".s" extension are not. +#------------------------------------------------------------------------------ +OBJS = $(sort $(addprefix $(OBJ_DIR)/, \ + $(patsubst %.c, %.o, $(patsubst %.C, %.o, $(C_SRCS))) \ + $(patsubst %.cxx, %.o, $(patsubst %.CXX, %.o, \ + $(patsubst %.cc, %.o, $(patsubst %.CC, %.o, \ + $(patsubst %.cpp, %.o, $(patsubst %.CPP, %.o, \ + $(CXX_SRCS) )))))) \ + $(patsubst %.S, %.o, $(patsubst %.s, %.o, $(ASM_SRCS))) )) + +# List of dependancy files for each object file. +DEPS = $(OBJS:.o=.d) + + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(FORCE_RELINK_DEP) $(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP)) + + +#------------------------------------------------------------------------------ +# BUILD RULES: ALL & CLEAN +#------------------------------------------------------------------------------ +.DELETE_ON_ERROR: + +.PHONY: all +all: build_pre_process +all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR) +all: build_post_process + + +# clean: remove .o/.a/.d +.PHONY: clean +clean: + @$(RM) -r $(BSP_LIB) $(OBJ_DIR) $(FORCE_REBUILD_DEP_LIST) +ifneq ($(wildcard $(NEWLIB_DIR)),) + @$(RM) -r $(NEWLIB_DIR) +endif + @$(ECHO) [BSP clean complete] + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + + +#------------------------------------------------------------------------------ +# MAKEFILE UP TO DATE? +# +# Is this very Makefile up to date? Someone may have changed the BSP settings +# file or the associated target hardware. +#------------------------------------------------------------------------------ +# Skip this check when clean is the only target +ifneq ($(MAKECMDGOALS),clean) + +ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE)) +$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) +endif + +Makefile: $(wildcard $(SETTINGS_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) +$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) +endif + +public.mk: $(wildcard $(SOPC_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +endif # $(MAKECMDGOALS) != clean + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ +$(OBJ_DIR)/%.o: %.c + @$(ECHO) Compiling $( + +/* + * Device headers + */ + +#include "altera_nios2_qsys_irq.h" +#include "altera_avalon_jtag_uart.h" +#include "altera_avalon_lcd_16207.h" + +/* + * Allocate the device storage + */ + +ALTERA_NIOS2_QSYS_IRQ_INSTANCE ( NIOS2_PROCESSOR, nios2_processor); +ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART, jtag_uart); +ALTERA_AVALON_LCD_16207_INSTANCE ( LCD_16207_0, lcd_16207_0); + +/* + * Initialize the interrupt controller devices + * and then enable interrupts in the CPU. + * Called before alt_sys_init(). + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + ALTERA_NIOS2_QSYS_IRQ_INIT ( NIOS2_PROCESSOR, nios2_processor); + alt_irq_cpu_enable_interrupts(); +} + +/* + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart); + ALTERA_AVALON_LCD_16207_INIT ( LCD_16207_0, lcd_16207_0); +} diff --git a/software/DE2_115_ASM_bsp/create-this-bsp b/software/DE2_115_ASM_bsp/create-this-bsp new file mode 100644 index 0000000..1228b16 --- /dev/null +++ b/software/DE2_115_ASM_bsp/create-this-bsp @@ -0,0 +1,49 @@ +#!/bin/bash +# +# This script creates the ucosii_net_zipfs Board Support Package (BSP). + +BSP_TYPE=hal +BSP_DIR=. +SOPC_DIR=../../ +SOPC_FILE=C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo +NIOS2_BSP_ARGS="" +CPU_NAME= + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + *) + NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" + ;; + esac + shift +done + + +# Run nios2-bsp utility to create a hal BSP in this directory +# for the system with a .sopc file in $SOPC_FILE. +# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. + +if [ -z "$SOPC_FILE" ]; then + echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS $CPU_NAME" +else + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS $CPU_NAME" +fi + + +echo "create-this-bsp: Running \"$cmd\"" +$cmd || { + echo "$cmd failed" + exit 1 +} +if [ -z "$SKIP_MAKE" ]; then + echo "create-this-bsp: Running make" + make +fi diff --git a/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart.h b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart.h new file mode 100644 index 0000000..3168183 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart.h @@ -0,0 +1,198 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_H__ +#define __ALT_AVALON_JTAG_UART_H__ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_warning.h" + +#include "os/alt_sem.h" +#include "os/alt_flag.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * If the user wants all drivers to be small rather than fast then make sure + * this one is marked as needing to be small. + */ +#if defined ALT_USE_SMALL_DRIVERS && !defined ALTERA_AVALON_JTAG_UART_SMALL +#define ALTERA_AVALON_JTAG_UART_SMALL +#endif + +/* + * If the user wants to ignore FIFO full error after timeout + */ +#if defined ALT_JTAG_UART_IGNORE_FIFO_FULL_ERROR && !defined ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR +#define ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR +#endif + +/* + * Constants that can be overriden. + */ +#ifndef ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT +#define ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT 10 +#endif + +#ifndef ALTERA_AVALON_JTAG_UART_BUF_LEN +#define ALTERA_AVALON_JTAG_UART_BUF_LEN 2048 +#endif + +/* + * ALT_JTAG_UART_READ_RDY and ALT_JTAG_UART_WRITE_RDY are the bitmasks + * that define uC/OS-II event flags that are releated to this device. + * + * ALT_JTAG_UART_READ_RDY indicates that there is read data in the buffer + * ready to be processed. ALT_JTAG_UART_WRITE_RDY indicates that the transmitter is + * ready for more data. + */ +#define ALT_JTAG_UART_READ_RDY 0x1 +#define ALT_JTAG_UART_WRITE_RDY 0x2 +#define ALT_JTAG_UART_TIMEOUT 0x4 + +/* + * State structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ + +typedef struct altera_avalon_jtag_uart_state_s +{ + unsigned int base; + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + + unsigned int timeout; /* Timeout until host is assumed inactive */ + alt_alarm alarm; + unsigned int irq_enable; + unsigned int host_inactive; + + ALT_SEM (read_lock) + ALT_SEM (write_lock) + ALT_FLAG_GRP (events) + + /* The variables below are volatile because they are modified by the + * interrupt routine. Making them volatile and reading them atomically + * means that we don't need any large critical sections. + */ + volatile unsigned int rx_in; + unsigned int rx_out; + unsigned int tx_in; + volatile unsigned int tx_out; + char rx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + char tx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +} altera_avalon_jtag_uart_state; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility isn't used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + } + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } + +/* + * Externally referenced routines + */ +extern void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq); + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) \ + { \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \ + "You have selected the interrupt driven version of " \ + "the ALTERA Avalon JTAG UART driver, but the " \ + "interrupt is not connected for this device. You can " \ + "select a polled mode driver by checking the 'small " \ + "driver' option in the HAL configuration window, or " \ + "by using the -DALTERA_AVALON_JTAG_UART_SMALL " \ + "preprocessor flag."); \ + } \ + else \ + altera_avalon_jtag_uart_init(&state, \ + name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_jtag_uart_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_JTAG_UART_INIT(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_JTAG_UART_INIT(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_H__ */ diff --git a/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h new file mode 100644 index 0000000..183bd3f --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_FD_H__ +#define __ALT_AVALON_JTAG_UART_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_jtag_uart_read_fd (alt_fd* fd, char* ptr, int len); +extern int altera_avalon_jtag_uart_write_fd (alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ + +typedef struct altera_avalon_jtag_uart_dev_s +{ + alt_dev dev; + altera_avalon_jtag_uart_state state; +} altera_avalon_jtag_uart_dev; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +extern int altera_avalon_jtag_uart_close_fd(alt_fd* fd); +extern int altera_avalon_jtag_uart_ioctl_fd (alt_fd* fd, int req, void* arg); + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + altera_avalon_jtag_uart_close_fd, \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + altera_avalon_jtag_uart_ioctl_fd, \ + }, \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_FD_H__ */ diff --git a/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h new file mode 100644 index 0000000..8fe6b80 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h @@ -0,0 +1,73 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_JTAG_UART_REGS_H__ +#define __ALTERA_AVALON_JTAG_UART_REGS_H__ + +#include + +#define ALTERA_AVALON_JTAG_UART_DATA_REG 0 +#define IOADDR_ALTERA_AVALON_JTAG_UART_DATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_DATA(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_DATA_REG, data) + +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FF) +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) + + +#define ALTERA_AVALON_JTAG_UART_CONTROL_REG 1 +#define IOADDR_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG, data) + +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) + +#endif /* __ALTERA_AVALON_JTAG_UART_REGS_H__ */ diff --git a/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207.h b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207.h new file mode 100644 index 0000000..526ef17 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_H__ +#define __ALTERA_AVALON_LCD_16207_H__ + +#include + +#include "sys/alt_alarm.h" +#include "os/alt_sem.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The altera_avalon_lcd_16207_dev structure is used to hold device specific + * data. This includes the transmit and receive buffers. + * + * An instance of this structure is created in the auto-generated + * alt_sys_init.c file for each UART listed in the systems PTF file. This is + * done using the ALTERA_AVALON_LCD_16207_STATE_INSTANCE macro given below. + */ + +#define ALT_LCD_HEIGHT 2 +#define ALT_LCD_WIDTH 16 +#define ALT_LCD_VIRTUAL_WIDTH 80 + +typedef struct altera_avalon_lcd_16207_state_s +{ + int base; + + alt_alarm alarm; + int period; + + char broken; + + unsigned char x; + unsigned char y; + char address; + char esccount; + + char scrollpos; + char scrollmax; + char active; /* If non-zero then the foreground routines are + * active so the timer call must not update the + * display. */ + + char escape[8]; + + struct + { + char visible[ALT_LCD_WIDTH]; + char data[ALT_LCD_VIRTUAL_WIDTH+1]; + char width; + unsigned char speed; + + } line[ALT_LCD_HEIGHT]; + + ALT_SEM (write_lock)/* Semaphore used to control access to the + * write buffer in multi-threaded mode */ +} altera_avalon_lcd_16207_state; + +/* + * Called by alt_sys_init.c to initialize the driver. + */ +extern void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp); + +/* + * The LCD panel driver is not trivial, so leave it out in the small + * drivers case. Also leave it out in simulation because there is no + * simulated hardware for the LCD panel. These two can be overridden + * by defining ALT_USE_LCE_16207 if you really want it. + */ + +#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 + +/* + * Used by the auto-generated file + * alt_sys_init.c to create an instance of this device driver. + */ +#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) \ + altera_avalon_lcd_16207_state state = \ + { \ + name##_BASE \ + } + +/* + * The macro ALTERA_AVALON_LCD_16207_INIT is used by the auto-generated file + * alt_sys_init.c to initialize an instance of the device driver. + */ +#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) \ + altera_avalon_lcd_16207_init(&state) + +#else /* exclude driver */ + +#define ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) extern int alt_no_storage +#define ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) while (0) + +#endif /* exclude driver */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_lcd_16207_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_LCD_16207_INSTANCE(name, state) \ + ALTERA_AVALON_LCD_16207_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_LCD_16207_INIT(name, state) \ + ALTERA_AVALON_LCD_16207_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_LCD_16207_INSTANCE(name, dev) \ + ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_LCD_16207_INIT(name, dev) \ + ALTERA_AVALON_LCD_16207_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_LCD_16207_H__ */ diff --git a/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h new file mode 100644 index 0000000..88436c0 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207_fd.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_FD_H__ +#define __ALTERA_AVALON_LCD_16207_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ + +typedef struct altera_avalon_lcd_16207_dev_s +{ + alt_dev dev; + altera_avalon_lcd_16207_state state; +} altera_avalon_lcd_16207_dev; + +/* + * The LCD panel driver is not trivial, so leave it out in the small + * drivers case. Also leave it out in simulation because there is no + * simulated hardware for the LCD panel. These two can be overridden + * by defining ALT_USE_LCE_16207 if you really want it. + */ + +#if (!defined(ALT_USE_SMALL_DRIVERS) && !defined(ALT_SIM_OPTIMIZE)) || defined ALT_USE_LCD_16207 + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ +#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) \ + static altera_avalon_lcd_16207_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + NULL, /* read */ \ + altera_avalon_lcd_16207_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE \ + }, \ + } + +#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_LCD_16207_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#else /* exclude driver */ + +#define ALTERA_AVALON_LCD_16207_DEV_INSTANCE(name, d) extern int alt_no_storage +#define ALTERA_AVALON_LCD_16207_DEV_INIT(name, d) while (0) + +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_AVALON_LCD_16207_FD_H__ */ diff --git a/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h new file mode 100644 index 0000000..bc35f1a --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_lcd_16207_regs.h @@ -0,0 +1,83 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_LCD_16207_REGS_H__ +#define __ALTERA_AVALON_LCD_16207_REGS_H__ + +/* +/////////////////////////////////////////////////////////////////////////// +// +// ALTERA_AVALON_LCD_16207 PERIPHERAL +// +// Provides a hardware interface that allows software to +// access the two (2) internal 8-bit registers in an Optrex +// model 16207 (or equivalent) character LCD display (the kind +// shipped with the Nios Development Kit, 2 rows x 16 columns). +// +// Because the interface to the LCD module is "not quite Avalon," +// the hardware in this module ends-up mapping the module's +// two physical read-write registers into four Avalon-visible +// registers: Two read-only registers and two write-only registers. +// A picture is worth a thousand words: +// +// THE REGISTER MAP +// +// 7 6 5 4 3 2 1 0 Offset +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 0 | Command Register (WRITE-Only) | 0 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 0 | Status Register (READ -Only) | 1 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 1 | Data Register (WRITE-Only) | 2 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// RS = 1 | Data Register (READ -Only) | 3 +// +-----+-----+-----+-----+-----+-----+-----+-----+ +// +/////////////////////////////////////////////////////////////////////////// +*/ + +#include + +#define IOADDR_ALTERA_AVALON_LCD_16207_COMMAND(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_LCD_16207_STATUS(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_LCD_16207_STATUS(base) IORD(base, 1) + +#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK (0x00000080u) +#define ALTERA_AVALON_LCD_16207_STATUS_BUSY_OFST (7) + +#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_WR(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_LCD_16207_DATA_RD(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_LCD_16207_DATA(base) IORD(base, 3) + +#endif diff --git a/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_pio_regs.h b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_pio_regs.h new file mode 100644 index 0000000..a829ddd --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/inc/altera_avalon_pio_regs.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_PIO_REGS_H__ +#define __ALTERA_AVALON_PIO_REGS_H__ + +#include + +#define IOADDR_ALTERA_AVALON_PIO_DATA(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IORD_ALTERA_AVALON_PIO_DATA(base) IORD(base, 0) +#define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_PIO_DIRECTION(base) IORD(base, 1) +#define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) + +#define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) +#define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base) IORD(base, 3) +#define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) + + +#define IOADDR_ALTERA_AVALON_PIO_SET_BIT(base) __IO_CALC_ADDRESS_NATIVE(base, 4) +#define IORD_ALTERA_AVALON_PIO_SET_BITS(base) IORD(base, 4) +#define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data) IOWR(base, 4, data) + +#define IOADDR_ALTERA_AVALON_PIO_CLEAR_BITS(base) __IO_CALC_ADDRESS_NATIVE(base, 5) +#define IORD_ALTERA_AVALON_PIO_CLEAR_BITS(base) IORD(base, 5) +#define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data) IOWR(base, 5, data) + + + +/* Defintions for direction-register operation with bi-directional PIOs */ +#define ALTERA_AVALON_PIO_DIRECTION_INPUT 0 +#define ALTERA_AVALON_PIO_DIRECTION_OUTPUT 1 + +#endif /* __ALTERA_AVALON_PIO_REGS_H__ */ diff --git a/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_fd.c b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_fd.c new file mode 100644 index 0000000..c2a882a --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_fd.c @@ -0,0 +1,86 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_jtag_uart.h" + +extern int altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags); +extern int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char* ptr, int count, int flags); +extern int altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, + int req, void* arg); +extern int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, + int flags); + +/* ----------------------------------------------------------------------- */ +/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */ +/* + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + fd->fd_flags); +} + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + fd->fd_flags); +} + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); +} + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_init.c b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_init.c new file mode 100644 index 0000000..16376e3 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_init.c @@ -0,0 +1,256 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context); +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id); +#endif +static alt_u32 altera_avalon_jtag_uart_timeout(void* context); + +/* + * Driver initialization code. Register interrupts and start a timer + * which we can use to check whether the host is there. + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + ALT_FLAG_CREATE(&sp->events, 0); + ALT_SEM_CREATE(&sp->read_lock, 1); + ALT_SEM_CREATE(&sp->write_lock, 1); + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + sp, NULL); +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + +/* + * Interrupt routine + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + unsigned int base = sp->base; + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + if (next == sp->rx_out) + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + } +} + +/* + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + sp->host_inactive = 0; + } + else if (sp->host_inactive < INT_MAX - 2) { + sp->host_inactive++; + + if (sp->host_inactive >= sp->timeout) { + /* Post an event to indicate host is inactive (for jtag_uart_read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + } + } + + return alt_ticks_per_second(); +} + +/* + * The close() routine is implemented to drain the JTAG UART transmit buffer + * when not in "small" mode. This routine will wait for transimt data to be + * emptied unless a timeout from host-activity occurs. If the driver flags + * have been set to non-blocking mode, this routine will exit immediately if + * any data remains. This routine should be called indirectly (i.e. though + * the C library close() routine) so that the file descriptor associated + * with the relevant stream (i.e. stdout) can be closed as well. This routine + * does not manage file descriptors. + * + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c new file mode 100644 index 0000000..15d97a6 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c @@ -0,0 +1,86 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + int rc = -ENOTTY; + + switch (req) + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + { + int timeout = *((int *)arg); + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + rc = 0; + } + break; + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + rc = 0; + } + break; + + default: + break; + } + + return rc; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_read.c b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_read.c new file mode 100644 index 0000000..f97baa8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_read.c @@ -0,0 +1,205 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ----------------------- SMALL DRIVER ---------------------- */ +/* ----------------------------------------------------------- */ + +/* Read routine. The small version blocks until it has at least one byte + * available, it then returns as much as is immediately available without + * waiting any more. It's performance will be very poor without + * interrupts. + */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags) +{ + unsigned int base = sp->base; + + char * ptr = buffer; + char * end = buffer + space; + + while (ptr < end) + { + unsigned int data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) + *ptr++ = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + else if (ptr != buffer) + break; + else if(flags & O_NONBLOCK) + break; + + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ----------------------- FAST DRIVER ----------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + char * ptr = buffer; + + alt_irq_context context; + unsigned int n; + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + { + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + out = sp->rx_out; + + if (in >= out) + n = in - out; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + + if (n == 0) + break; /* No more data available */ + + if (n > space) + n = space; + + memcpy(ptr, sp->rx_buf + out, n); + ptr += n; + space -= n; + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + while (space > 0); + + /* If we read any data then return it */ + if (ptr != buffer) + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the read event + * flag set and timeout event flag set in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_READ_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* Spin until more data arrives or until host disconnects */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; + } +#else + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + break; + } + + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + if (ptr != buffer) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_write.c b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_write.c new file mode 100644 index 0000000..9562562 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_jtag_uart_write.c @@ -0,0 +1,217 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------ SMALL DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* Write routine. The small version blocks when there is no space to write + * into, so it's performance will be very bad if you are writing more than + * one FIFOs worth of data. But you said you didn't want to use interrupts :-) + */ + +int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + unsigned int base = sp->base; + + const char * end = ptr + count; + + while (ptr < end) + if ((IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) != 0) + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, *ptr++); + + return count; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + out = sp->tx_out; + + if (in < out) + n = out - 1 - in; + else if (out > 0) + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + + if (n == 0) + break; + + if (n > count) + n = count; + + memcpy(sp->tx_buf + in, ptr, n); + ptr += n; + count -= n; + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + + /* + * If interrupts are disabled then we could transmit here, we only need + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + { + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the write event + * flag set or the timeout flag in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ +#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + if(!sp->host_inactive) +#endif + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_WRITE_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* + * OS not running: Wait for data to be removed from buffer. + * Once the interrupt routine has removed some data then we + * will be able to insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; + } +#else + /* + * No OS present: Always wait for data to be removed from buffer. Once + * the interrupt routine has removed some data then we will be able to + * insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + break; + } + } + while (count > 0); + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + + if (ptr != start) + return ptr - start; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; +#ifdef ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + else if (sp->host_inactive >= sp->timeout) { + /* + * Reset the software FIFO, hardware FIFO could not be reset. + * Just throw away characters without reporting error. + */ + sp->tx_out = sp->tx_in = 0; + return ptr - start + count; + } +#endif + else + return -EIO; /* Host not connected */ +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_lcd_16207.c b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_lcd_16207.c new file mode 100644 index 0000000..102e202 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_lcd_16207.c @@ -0,0 +1,605 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* ===================================================================== */ + +/* + * This file provides the implementation of the functions used to drive a + * LCD panel. + * + * Characters written to the device will appear on the LCD panel as though + * it is a very small terminal. If the lines written to the terminal are + * longer than the number of characters on the terminal then it will scroll + * the lines of text automatically to display them all. + * + * If more lines are written than will fit on the terminal then it will scroll + * when characters are written to the line "below" the last displayed one - + * the cursor is allowed to sit below the visible area of the screen providing + * that this line is entirely blank. + * + * The following control sequences may be used to move around and do useful + * stuff: + * CR Moves back to the start of the current line + * LF Moves down a line and back to the start + * BS Moves back a character without erasing + * ESC Starts a VT100 style escape sequence + * + * The following escape sequences are recognised: + * ESC [ ; H Move to row and column specified (positions are + * counted from the top left which is 1;1) + * ESC [ K Clear from current position to end of line + * ESC [ 2 J Clear screen and go to top left + * + */ + +/* ===================================================================== */ + +#include +#include + +#include +#include +#include + +#include "sys/alt_alarm.h" + +#include "altera_avalon_lcd_16207_regs.h" +#include "altera_avalon_lcd_16207.h" + +/* --------------------------------------------------------------------- */ + +/* Commands which can be written to the COMMAND register */ + +enum /* Write to character RAM */ +{ + LCD_CMD_WRITE_DATA = 0x80 + /* Bits 6:0 hold character RAM address */ +}; + +enum /* Write to character generator RAM */ +{ + LCD_CMD_WRITE_CGR = 0x40 + /* Bits 5:0 hold character generator RAM address */ +}; + +enum /* Function Set command */ +{ + LCD_CMD_FUNCTION_SET = 0x20, + LCD_CMD_8BIT = 0x10, + LCD_CMD_TWO_LINE = 0x08, + LCD_CMD_BIGFONT = 0x04 +}; + +enum /* Shift command */ +{ + LCD_CMD_SHIFT = 0x10, + LCD_CMD_SHIFT_DISPLAY = 0x08, + LCD_CMD_SHIFT_RIGHT = 0x04 +}; + +enum /* On/Off command */ +{ + LCD_CMD_ONOFF = 0x08, + LCD_CMD_ENABLE_DISP = 0x04, + LCD_CMD_ENABLE_CURSOR = 0x02, + LCD_CMD_ENABLE_BLINK = 0x01 +}; + +enum /* Entry Mode command */ +{ + LCD_CMD_MODES = 0x04, + LCD_CMD_MODE_INC = 0x02, + LCD_CMD_MODE_SHIFT = 0x01 +}; + +enum /* Home command */ +{ + LCD_CMD_HOME = 0x02 +}; + +enum /* Clear command */ +{ + LCD_CMD_CLEAR = 0x01 +}; + +/* Where in LCD character space do the rows start */ +static char colstart[4] = { 0x00, 0x40, 0x20, 0x60 }; + +/* --------------------------------------------------------------------- */ + +static void lcd_write_command(altera_avalon_lcd_16207_state* sp, + unsigned char command) +{ + unsigned int base = sp->base; + + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + if (--i == 0) + { + sp->broken = 1; + return; + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, command); +} + +/* --------------------------------------------------------------------- */ + +static void lcd_write_data(altera_avalon_lcd_16207_state* sp, + unsigned char data) +{ + unsigned int base = sp->base; + + /* We impose a timeout on the driver in case the LCD panel isn't connected. + * The first time we call this function the timeout is approx 25ms + * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems + * with slower clocks, or debug builds, or slower memory will take longer. + */ + int i = 1000000; + + /* Don't bother if the LCD panel didn't work before */ + if (sp->broken) + return; + + /* Wait until LCD isn't busy. */ + while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) + if (--i == 0) + { + sp->broken = 1; + return; + } + + /* Despite what it says in the datasheet, the LCD isn't ready to accept + * a write immediately after it returns BUSY=0. Wait for 100us more. + */ + usleep(100); + + IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data); + + sp->address++; +} + +/* --------------------------------------------------------------------- */ + +static void lcd_clear_screen(altera_avalon_lcd_16207_state* sp) +{ + int y; + + lcd_write_command(sp, LCD_CMD_CLEAR); + + sp->x = 0; + sp->y = 0; + sp->address = 0; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); + memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); + sp->line[y].width = 0; + } +} + +/* --------------------------------------------------------------------- */ + +static void lcd_repaint_screen(altera_avalon_lcd_16207_state* sp) +{ + int y, x; + + /* scrollpos controls how much the lines have scrolled round. The speed + * each line scrolls at is controlled by its speed variable - while + * scrolline lines will wrap at the position set by width + */ + + int scrollpos = sp->scrollpos; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + int width = sp->line[y].width; + int offset = (scrollpos * sp->line[y].speed) >> 8; + if (offset >= width) + offset = 0; + + for (x = 0 ; x < ALT_LCD_WIDTH ; x++) + { + char c = sp->line[y].data[(x + offset) % width]; + + /* Writing data takes 40us, so don't do it unless required */ + if (sp->line[y].visible[x] != c) + { + unsigned char address = x + colstart[y]; + + if (address != sp->address) + { + lcd_write_command(sp, LCD_CMD_WRITE_DATA | address); + sp->address = address; + } + + lcd_write_data(sp, c); + sp->line[y].visible[x] = c; + } + } + } +} + +/* --------------------------------------------------------------------- */ + +static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) +{ + int y; + + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + if (y < ALT_LCD_HEIGHT-1) + memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); + else + memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); + } + + sp->y--; +} + +/* --------------------------------------------------------------------- */ + +static void lcd_handle_escape(altera_avalon_lcd_16207_state* sp, char c) +{ + int parm1 = 0, parm2 = 0; + + if (sp->escape[0] == '[') + { + char * ptr = sp->escape+1; + while (isdigit(*ptr)) + parm1 = (parm1 * 10) + (*ptr++ - '0'); + + if (*ptr == ';') + { + ptr++; + while (isdigit(*ptr)) + parm2 = (parm2 * 10) + (*ptr++ - '0'); + } + } + else + parm1 = -1; + + switch (c) + { + case 'H': /* ESC '[' ';' 'H' : Move cursor to location */ + case 'f': /* Same as above */ + if (parm2 > 0) + sp->x = parm2 - 1; + if (parm1 > 0) + { + sp->y = parm1 - 1; + if (sp->y > ALT_LCD_HEIGHT * 2) + sp->y = ALT_LCD_HEIGHT * 2; + while (sp->y > ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + } + break; + + case 'J': + /* ESC J is clear to beginning of line [unimplemented] + * ESC [ 0 J is clear to bottom of screen [unimplemented] + * ESC [ 1 J is clear to beginning of screen [unimplemented] + * ESC [ 2 J is clear screen + */ + if (parm1 == 2) + lcd_clear_screen(sp); + break; + + case 'K': + /* ESC K is clear to end of line + * ESC [ 0 K is clear to end of line + * ESC [ 1 K is clear to beginning of line [unimplemented] + * ESC [ 2 K is clear line [unimplemented] + */ + if (parm1 < 1) + { + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + memset(sp->line[sp->y].data + sp->x, ' ', ALT_LCD_VIRTUAL_WIDTH - sp->x); + } + break; + } +} + +/* --------------------------------------------------------------------- */ + +int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int len, int flags) +{ + const char* end = ptr + len; + + int y; + int widthmax; + + /* When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + + /* Tell the routine which is called off the timer interrupt that the + * foreground routines are active so it must not repaint the display. */ + sp->active = 1; + + for ( ; ptr < end ; ptr++) + { + char c = *ptr; + + if (sp->esccount >= 0) + { + unsigned int esccount = sp->esccount; + + /* Single character escape sequences can end with any character + * Multi character escape sequences start with '[' and contain + * digits and semicolons before terminating + */ + if ((esccount == 0 && c != '[') || + (esccount > 0 && !isdigit(c) && c != ';')) + { + sp->escape[esccount] = 0; + + lcd_handle_escape(sp, c); + + sp->esccount = -1; + } + else if (sp->esccount < sizeof(sp->escape)-1) + { + sp->escape[esccount] = c; + sp->esccount++; + } + } + else if (c == 27) /* ESC */ + { + sp->esccount = 0; + } + else if (c == '\r') + { + sp->x = 0; + } + else if (c == '\n') + { + sp->x = 0; + sp->y++; + + /* Let the cursor sit at X=0, Y=HEIGHT without scrolling so the user + * can print two lines of data without losing one. + */ + if (sp->y > ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + } + else if (c == '\b') + { + if (sp->x > 0) + sp->x--; + } + else if (isprint(c)) + { + /* If we didn't scroll on the last linefeed then we might need to do + * it now. */ + if (sp->y >= ALT_LCD_HEIGHT) + lcd_scroll_up(sp); + + if (sp->x < ALT_LCD_VIRTUAL_WIDTH) + sp->line[sp->y].data[sp->x] = c; + + sp->x++; + } + } + + /* Recalculate the scrolling parameters */ + widthmax = ALT_LCD_WIDTH; + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + { + int width; + for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) + if (sp->line[y].data[width-1] != ' ') + break; + + /* The minimum width is the size of the LCD panel. If the real width + * is long enough to require scrolling then add an extra space so the + * end of the message doesn't run into the beginning of it. + */ + if (width <= ALT_LCD_WIDTH) + width = ALT_LCD_WIDTH; + else + width++; + + sp->line[y].width = width; + if (widthmax < width) + widthmax = width; + sp->line[y].speed = 0; /* By default lines don't scroll */ + } + + if (widthmax <= ALT_LCD_WIDTH) + sp->scrollmax = 0; + else + { + widthmax *= 2; + sp->scrollmax = widthmax; + + /* Now calculate how fast each of the other lines should go */ + for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) + if (sp->line[y].width > ALT_LCD_WIDTH) + { + /* You have three options for how to make the display scroll, chosen + * using the preprocessor directives below + */ +#if 1 + /* This option makes all the lines scroll round at different speeds + * which are chosen so that all the scrolls finish at the same time. + */ + sp->line[y].speed = 256 * sp->line[y].width / widthmax; +#elif 1 + /* This option pads the shorter lines with spaces so that they all + * scroll together. + */ + sp->line[y].width = widthmax / 2; + sp->line[y].speed = 256/2; +#else + /* This option makes the shorter lines stop after they have rotated + * and waits for the longer lines to catch up + */ + sp->line[y].speed = 256/2; +#endif + } + } + + /* Repaint once, then check whether there has been a missed repaint + * (because active was set when the timer interrupt occurred). If there + * has been a missed repaint then paint again. And again. etc. + */ + for ( ; ; ) + { + int old_scrollpos = sp->scrollpos; + + lcd_repaint_screen(sp); + + /* Let the timer routines repaint the display again */ + sp->active = 0; + + /* Have the timer routines tried to scroll while we were painting? + * If not then we can exit */ + if (sp->scrollpos == old_scrollpos) + break; + + /* We need to repaint again since the display scrolled while we were + * painting last time */ + sp->active = 1; + } + + /* Now that access to the display is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + + return len; +} + +/* --------------------------------------------------------------------- */ + +/* This should be in a top level header file really */ +#define container_of(ptr, type, member) ((type *)((char *)ptr - offsetof(type, member))) + +/* + * Timeout routine is called every second + */ + +static alt_u32 alt_lcd_16207_timeout(void* context) +{ + altera_avalon_lcd_16207_state* sp = (altera_avalon_lcd_16207_state*)context; + + /* Update the scrolling position */ + if (sp->scrollpos + 1 >= sp->scrollmax) + sp->scrollpos = 0; + else + sp->scrollpos = sp->scrollpos + 1; + + /* Repaint the panel unless the foreground will do it again soon */ + if (sp->scrollmax > 0 && !sp->active) + lcd_repaint_screen(sp); + + return sp->period; +} + +/* --------------------------------------------------------------------- */ + +/* + * Called at boot time to initialise the LCD driver + */ +void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp) +{ + unsigned int base = sp->base; + + /* Mark the device as functional */ + sp->broken = 0; + + ALT_SEM_CREATE (&sp->write_lock, 1); + + /* The initialisation sequence below is copied from the datasheet for + * the 16207 LCD display. The first commands need to be timed because + * the BUSY bit in the status register doesn't work until the display + * has been reset three times. + */ + + /* Wait for 15 ms then reset */ + usleep(15000); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Wait for another 4.1ms and reset again */ + usleep(4100); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Wait a further 1 ms and reset a third time */ + usleep(1000); + IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); + + /* Setup interface parameters: 8 bit bus, 2 rows, 5x7 font */ + lcd_write_command(sp, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT | LCD_CMD_TWO_LINE); + + /* Turn display off */ + lcd_write_command(sp, LCD_CMD_ONOFF); + + /* Clear display */ + lcd_clear_screen(sp); + + /* Set mode: increment after writing, don't shift display */ + lcd_write_command(sp, LCD_CMD_MODES | LCD_CMD_MODE_INC); + + /* Turn display on */ + lcd_write_command(sp, LCD_CMD_ONOFF | LCD_CMD_ENABLE_DISP); + + sp->esccount = -1; + memset(sp->escape, 0, sizeof(sp->escape)); + + sp->scrollpos = 0; + sp->scrollmax = 0; + sp->active = 0; + + sp->period = alt_ticks_per_second() / 10; /* Call every 100ms */ + + alt_alarm_start(&sp->alarm, sp->period, &alt_lcd_16207_timeout, sp); +} diff --git a/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_lcd_16207_fd.c b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_lcd_16207_fd.c new file mode 100644 index 0000000..08c9371 --- /dev/null +++ b/software/DE2_115_ASM_bsp/drivers/src/altera_avalon_lcd_16207_fd.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_lcd_16207.h" + +extern int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, + const char* ptr, int count, int flags); + +int +altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_lcd_16207_dev* dev = (altera_avalon_lcd_16207_dev*) fd->dev; + + return altera_avalon_lcd_16207_write(&dev->state, buffer, space, + fd->fd_flags); +} diff --git a/software/DE2_115_ASM_bsp/libhal_bsp.a b/software/DE2_115_ASM_bsp/libhal_bsp.a new file mode 100644 index 0000000..430ad5f --- /dev/null +++ b/software/DE2_115_ASM_bsp/libhal_bsp.a Binary files differ diff --git a/software/DE2_115_ASM_bsp/linker.h b/software/DE2_115_ASM_bsp/linker.h new file mode 100644 index 0000000..3dcbf16 --- /dev/null +++ b/software/DE2_115_ASM_bsp/linker.h @@ -0,0 +1,101 @@ +/* + * linker.h - Linker script mapping information + * + * Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' + * SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + * + * Generated: Thu Dec 22 10:08:01 JST 2016 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __LINKER_H_ +#define __LINKER_H_ + + +/* + * BSP controls alt_load() behavior in crt0. + * + */ + +#define ALT_LOAD_EXPLICITLY_CONTROLLED + + +/* + * Base address and span (size in bytes) of each linker region + * + */ + +#define ONCHIP_MEMORY_REGION_BASE 0x20 +#define ONCHIP_MEMORY_REGION_SPAN 204768 +#define RESET_REGION_BASE 0x0 +#define RESET_REGION_SPAN 32 + + +/* + * Devices associated with code sections + * + */ + +#define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY +#define ALT_RESET_DEVICE ONCHIP_MEMORY +#define ALT_RODATA_DEVICE ONCHIP_MEMORY +#define ALT_RWDATA_DEVICE ONCHIP_MEMORY +#define ALT_TEXT_DEVICE ONCHIP_MEMORY + + +/* + * Initialization code at the reset address is allowed (e.g. no external bootloader). + * + */ + +#define ALT_ALLOW_CODE_AT_RESET + + +/* + * The alt_load() facility is called from crt0 to copy sections into RAM. + * + */ + +#define ALT_LOAD_COPY_RWDATA + +#endif /* __LINKER_H_ */ diff --git a/software/DE2_115_ASM_bsp/linker.x b/software/DE2_115_ASM_bsp/linker.x new file mode 100644 index 0000000..0d9509a --- /dev/null +++ b/software/DE2_115_ASM_bsp/linker.x @@ -0,0 +1,385 @@ +/* + * linker.x - Linker script + * + * Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' + * SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + * + * Generated: Thu Dec 22 10:08:01 JST 2016 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +MEMORY +{ + reset : ORIGIN = 0x0, LENGTH = 32 + onchip_memory : ORIGIN = 0x20, LENGTH = 204768 +} + +/* Define symbols for each memory base-address */ +__alt_mem_onchip_memory = 0x0; + +OUTPUT_FORMAT( "elf32-littlenios2", + "elf32-littlenios2", + "elf32-littlenios2" ) +OUTPUT_ARCH( nios2 ) +ENTRY( _start ) + +/* + * The alt_load() facility is enabled. This typically happens when there isn't + * an external bootloader (e.g. flash bootloader). + * The LMA (aka physical address) of each loaded section is + * set to the .text memory device. + * The HAL alt_load() routine called from crt0 copies sections from + * the .text memory to RAM as needed. + */ + +SECTIONS +{ + + /* + * Output sections associated with reset and exceptions (they have to be first) + */ + + .entry : + { + KEEP (*(.entry)) + } > reset + + .exceptions : + { + PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); + . = ALIGN(0x20); + KEEP (*(.irq)); + KEEP (*(.exceptions.entry.label)); + KEEP (*(.exceptions.entry.user)); + KEEP (*(.exceptions.entry)); + KEEP (*(.exceptions.irqtest.user)); + KEEP (*(.exceptions.irqtest)); + KEEP (*(.exceptions.irqhandler.user)); + KEEP (*(.exceptions.irqhandler)); + KEEP (*(.exceptions.irqreturn.user)); + KEEP (*(.exceptions.irqreturn)); + KEEP (*(.exceptions.notirq.label)); + KEEP (*(.exceptions.notirq.user)); + KEEP (*(.exceptions.notirq)); + KEEP (*(.exceptions.soft.user)); + KEEP (*(.exceptions.soft)); + KEEP (*(.exceptions.unknown.user)); + KEEP (*(.exceptions.unknown)); + KEEP (*(.exceptions.exit.label)); + KEEP (*(.exceptions.exit.user)); + KEEP (*(.exceptions.exit)); + KEEP (*(.exceptions)); + PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); + } > onchip_memory + + PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); + + .text : + { + /* + * All code sections are merged into the text output section, along with + * the read only data sections. + * + */ + + PROVIDE (stext = ABSOLUTE(.)); + + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + + KEEP (*(.init)) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + + /* .gnu.warning sections are handled specially by elf32.em. */ + + *(.gnu.warning.*) + KEEP (*(.fini)) + PROVIDE (__etext = ABSOLUTE(.)); + PROVIDE (_etext = ABSOLUTE(.)); + PROVIDE (etext = ABSOLUTE(.)); + + *(.eh_frame_hdr) + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(4); + PROVIDE (__preinit_array_start = ABSOLUTE(.)); + *(.preinit_array) + PROVIDE (__preinit_array_end = ABSOLUTE(.)); + PROVIDE (__init_array_start = ABSOLUTE(.)); + *(.init_array) + PROVIDE (__init_array_end = ABSOLUTE(.)); + PROVIDE (__fini_array_start = ABSOLUTE(.)); + *(.fini_array) + PROVIDE (__fini_array_end = ABSOLUTE(.)); + SORT(CONSTRUCTORS) + KEEP (*(.eh_frame)) + *(.gcc_except_table) + *(.dynamic) + PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.ctors)) + KEEP (*(SORT(.ctors.*))) + PROVIDE (__CTOR_END__ = ABSOLUTE(.)); + PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.dtors)) + KEEP (*(SORT(.dtors.*))) + PROVIDE (__DTOR_END__ = ABSOLUTE(.)); + KEEP (*(.jcr)) + . = ALIGN(4); + } > onchip_memory = 0x3a880100 /* Nios II NOP instruction */ + + .rodata : + { + PROVIDE (__ram_rodata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + . = ALIGN(4); + PROVIDE (__ram_rodata_end = ABSOLUTE(.)); + } > onchip_memory + + PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + * .rwdata region equals the .text region, and is set to be loaded into .text region. + * This requires two copies of .rwdata in the .text region. One read writable at VMA. + * and one read-only at LMA. crt0 will copy from LMA to VMA on reset + * + */ + + .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) + { + PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.got.plt) *(.got) + *(.data1) + *(.data .data.* .gnu.linkonce.d.*) + + _gp = ABSOLUTE(. + 0x8000); + PROVIDE(gp = _gp); + + *(.rwdata .rwdata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + PROVIDE (edata = ABSOLUTE(.)); + PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); + } > onchip_memory + + PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) + { + __bss_start = ABSOLUTE(.); + PROVIDE (__sbss_start = ABSOLUTE(.)); + PROVIDE (___sbss_start = ABSOLUTE(.)); + + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.scommon) + + PROVIDE (__sbss_end = ABSOLUTE(.)); + PROVIDE (___sbss_end = ABSOLUTE(.)); + + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > onchip_memory + + /* + * + * One output section mapped to the associated memory device for each of + * the available memory devices. These are not used by default, but can + * be used by user applications by using the .section directive. + * + * The output section used for the heap is treated in a special way, + * i.e. the symbols "end" and "_end" are added to point to the heap start. + * + * Because alt_load() is enabled, these sections have + * their LMA set to be loaded into the .text memory region. + * However, the alt_load() code will NOT automatically copy + * these sections into their mapped memory region. + * + */ + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .onchip_memory LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) + { + PROVIDE (_alt_partition_onchip_memory_start = ABSOLUTE(.)); + *(.onchip_memory. onchip_memory.*) + . = ALIGN(4); + PROVIDE (_alt_partition_onchip_memory_end = ABSOLUTE(.)); + _end = ABSOLUTE(.); + end = ABSOLUTE(.); + __alt_stack_base = ABSOLUTE(.); + } > onchip_memory + + PROVIDE (_alt_partition_onchip_memory_load_addr = LOADADDR(.onchip_memory)); + + /* + * Stabs debugging sections. + * + */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Altera debug extensions */ + .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } +} + +/* provide a pointer for the stack */ + +/* + * Don't override this, override the __alt_stack_* symbols instead. + */ +__alt_data_end = 0x32000; + +/* + * The next two symbols define the location of the default stack. You can + * override them to move the stack to a different memory. + */ +PROVIDE( __alt_stack_pointer = __alt_data_end ); +PROVIDE( __alt_stack_limit = __alt_stack_base ); + +/* + * This symbol controls where the start of the heap is. If the stack is + * contiguous with the heap then the stack will contract as memory is + * allocated to the heap. + * Override this symbol to put the heap in a different memory. + */ +PROVIDE( __alt_heap_start = end ); +PROVIDE( __alt_heap_limit = 0x32000 ); diff --git a/software/DE2_115_ASM_bsp/mem_init.mk b/software/DE2_115_ASM_bsp/mem_init.mk new file mode 100644 index 0000000..4bdd7f1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/mem_init.mk @@ -0,0 +1,322 @@ + +######################################################################### +####### M E M I N I T M A K E F I L E C O N T E N T ###### +######################################################################### + +######################################################################### +# This file is intended to be included by public.mk +# +# +# The following variables must be defined before including this file: +# - ELF +# +# The following variables may be defined to override the default behavior: +# - HDL_SIM_DIR +# - HDL_SIM_INSTALL_DIR +# - MEM_INIT_DIR +# - MEM_INIT_INSTALL_DIR +# - QUARTUS_PROJECT_DIR +# - SOPC_NAME +# - SIM_OPTIMIZE +# - RESET_ADDRESS +# +######################################################################### + +ifeq ($(MEM_INIT_FILE),) +# MEM_INIT_FILE should be set equal to the working relative path to this +# mem_init.mk makefile fragment +MEM_INIT_FILE := $(wildcard $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))) +endif + +ifeq ($(ELF2DAT),) +ELF2DAT := elf2dat +endif + +ifeq ($(ELF2HEX),) +ELF2HEX := elf2hex +endif + +ifeq ($(ELF2FLASH),) +ELF2FLASH := elf2flash +endif + +ifeq ($(FLASH2DAT),) +FLASH2DAT := flash2dat +endif + +ifeq ($(NM),) +NM := nios2-elf-nm +endif + +ifeq ($(MKDIR),) +MKDIR := mkdir -p +endif + +ifeq ($(RM),) +RM := rm -f +endif + +ifeq ($(CP),) +CP := cp +endif + +ifeq ($(ECHO),) +ECHO := echo +endif + +MEM_INIT_DIR ?= mem_init +HDL_SIM_DIR ?= $(MEM_INIT_DIR)/hdl_sim + +ifdef QUARTUS_PROJECT_DIR +MEM_INIT_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR)) +ifdef SOPC_NAME +HDL_SIM_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))/$(SOPC_NAME)_sim +endif +endif + +MEM_INIT_DESCRIPTOR_FILE ?= $(MEM_INIT_DIR)/meminit.spd + +MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip + +#------------------------------------- +# Default Flash Boot Loaders +#------------------------------------- + +BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2 +BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec +BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec + + +#------------------------------------- +# Default Target +#------------------------------------- + +.PHONY: default_mem_init +ifeq ($(QSYS),1) +default_mem_init: mem_init_generate +else +default_mem_init: mem_init_install +endif +#------------------------------------- +# Runtime Macros +#------------------------------------- + +define post-process-info + @echo Post-processing to create $@... +endef + +target_stem = $(notdir $(basename $@)) + +mem_start_address = $($(target_stem)_START) +mem_end_address = $($(target_stem)_END) +mem_width = $($(target_stem)_WIDTH) +mem_endianness = $($(target_stem)_ENDIANNESS) +mem_create_lanes = $($(target_stem)_CREATE_LANES) + +mem_pad_flag = $($(target_stem)_PAD_FLAG) +mem_reloc_input_flag = $($(target_stem)_RELOC_INPUT_FLAG) +mem_no_zero_fill_flag = $($(target_stem)_NO_ZERO_FILL_FLAG) + +flash_mem_epcs_flag = $($(target_stem)_EPCS_FLAGS) +flash_mem_cfi_flag = $($(target_stem)_CFI_FLAGS) +flash_mem_boot_loader_flag = $($(target_stem)_BOOT_LOADER_FLAG) + +elf2dat_extra_args = $(mem_pad_flag) +elf2hex_extra_args = $(mem_no_zero_fill_flag) +elf2flash_extra_args = $(flash_mem_cfi_flag) $(flash_mem_epcs_flag) $(flash_mem_boot_loader_flag) +flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag) + +#------------------------------------------------------------------------------ +# BSP SPECIFIC CONTENT +# +# The content below is controlled by the BSP and SOPC System +#------------------------------------------------------------------------------ +#START OF BSP SPECIFIC + +#------------------------------------- +# Global Settings +#------------------------------------- + + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_MEMINIT_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Optimize for simulation +SIM_OPTIMIZE ?= 0 + +# The CPU reset address as needed by elf2flash +RESET_ADDRESS ?= 0x00000000 + +#------------------------------------- +# Pre-Initialized Memory Descriptions +#------------------------------------- + +# Memory: onchip_memory +MEM_0 := nios_system_onchip_memory +$(MEM_0)_NAME := onchip_memory +$(MEM_0)_MEM_INIT_FILE_PARAM_NAME := INIT_FILE +HEX_FILES += $(MEM_INIT_DIR)/$(MEM_0).hex +MEM_INIT_INSTALL_FILES += $(MEM_INIT_INSTALL_DIR)/$(MEM_0).hex +DAT_FILES += $(HDL_SIM_DIR)/$(MEM_0).dat +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat +SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym +$(MEM_0)_START := 0x00000000 +$(MEM_0)_END := 0x00031fff +$(MEM_0)_HIERARCHICAL_PATH := onchip_memory +$(MEM_0)_WIDTH := 32 +$(MEM_0)_ENDIANNESS := --little-endian-mem +$(MEM_0)_CREATE_LANES := 0 + +.PHONY: onchip_memory +onchip_memory: check_elf_exists $(MEM_INIT_DIR)/$(MEM_0).hex $(HDL_SIM_DIR)/$(MEM_0).dat $(HDL_SIM_DIR)/$(MEM_0).sym + + +#END OF BSP SPECIFIC + +#------------------------------------- +# Pre-Initialized Memory Targets +#------------------------------------- + +.PHONY: mem_init_install mem_init_generate mem_init_clean + +ifeq ($(QSYS),1) +# Target mem_init_install is deprecated for QSys based systems +# To initialize onchip memories for Quartus II Synthesis with Qsys based systems: +# 1) Use "make mem_init_genearate" +# 2) Add the generated mem_init/meminit.qip file to your Quartus II Project +# +mem_init_install: + $(error Deprecated Makefile Target: '$@'. Use target 'mem_init_generate' and then add $(MEM_INIT_QIP_FILE) to your Quartus II Project) + +else # QSYS != 1, if SopcBuilder based system + +ifneq ($(MEM_INIT_INSTALL_DIR),) +mem_init_install: $(MEM_INIT_INSTALL_FILES) +endif + +ifneq ($(HDL_SIM_INSTALL_DIR),) +mem_init_install: $(HDL_SIM_INSTALL_FILES) +endif + +mem_init_install: mem_init_generate +ifeq ($(MEM_INIT_INSTALL_DIR),) + @echo "WARNING: MEM_INIT_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR environment variable." +endif +ifeq ($(HDL_SIM_INSTALL_DIR),) + @echo "WARNING: HDL_SIM_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR and SOPC_NAME environment variable." +endif + +$(MEM_INIT_INSTALL_FILES): $(MEM_INIT_INSTALL_DIR)/%: $(MEM_INIT_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +$(HDL_SIM_INSTALL_FILES): $(HDL_SIM_INSTALL_DIR)/%: $(HDL_SIM_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +endif # QSYS == 1 + + +mem_init_generate: hex dat sym flash $(MEM_INIT_DESCRIPTOR_FILE) $(MEM_INIT_QIP_FILE) + +mem_init_clean: + @$(RM) -r $(MEM_INIT_DIR) $(HDL_SIM_DIR) $(FLASH_FILES) + +.PHONY: hex dat sym flash + +hex: check_elf_exists $(HEX_FILES) + +dat: check_elf_exists $(DAT_FILES) + +sym: check_elf_exists $(SYM_FILES) + +flash: check_elf_exists $(FLASH_FILES) + +#------------------------------------- +# Pre-Initialized Memory Rules +#------------------------------------- + +.PHONY: check_elf_exists +check_elf_exists: $(ELF) +ifeq ($(ELF),) + $(error ELF var not set in mem_init.mk) +endif + +$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2DAT) --infile=$< --outfile=$@ \ + --base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)' + +$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat + @true + +$(HEX_FILES): %.hex: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@' + +$(SYM_FILES): %.sym: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + $(NM) -n $< > $@ + +$(FLASH_FILES): %.flash: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \ + $(elf2flash_extra_args)' + +# +# Function generate_spd_entry +# Arg1: path to the memory initialization file +# Arg2: Type HEX or DAT +# Arg3: Output spd file to append +gen_spd_entry.BASE_FILE = $(basename $(notdir $1)) +gen_spd_entry.PARAM_NAME = $($(gen_spd_entry.BASE_FILE)_MEM_INIT_FILE_PARAM_NAME) +gen_spd_entry.MEM_PATH = $($(gen_spd_entry.BASE_FILE)_HIERARCHICAL_PATH) +gen_spd_entry.SETTINGS = $(strip \ + path=\"$1\" \ + type=\"$2\" \ + $(if $(gen_spd_entry.PARAM_NAME),initParamName=\"$(gen_spd_entry.PARAM_NAME)\") \ + $(if $(gen_spd_entry.MEM_PATH),memoryPath=\"$(gen_spd_entry.MEM_PATH)\") \ +) +define gen_spd_entry +$(ECHO) "" >> $3 +endef + +$(MEM_INIT_DESCRIPTOR_FILE).DAT_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(DAT_FILES)) +$(MEM_INIT_DESCRIPTOR_FILE).HEX_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(HEX_FILES)) + +$(MEM_INIT_DESCRIPTOR_FILE): %.spd: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "" > $@ + @$(ECHO) "" >> $@ + @$(foreach dat_file,$($@.DAT_FILESET),$(call gen_spd_entry,$(dat_file),DAT,$@) &&)true + @$(foreach hex_file,$($@.HEX_FILESET),$(call gen_spd_entry,$(hex_file),HEX,$@) &&)true + @$(ECHO) "" >> $@ + +.DELETE_ON_ERROR: $(MEM_INIT_DESCRIPTOR_FILE) + +$(MEM_INIT_QIP_FILE): %.qip: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "set_global_assignment -name SEARCH_PATH $$::quartus(qip_path)" > $@ + +.DELETE_ON_ERROR: $(MEM_INIT_QIP_FILE) diff --git a/software/DE2_115_ASM_bsp/memory.gdb b/software/DE2_115_ASM_bsp/memory.gdb new file mode 100644 index 0000000..c73c453 --- /dev/null +++ b/software/DE2_115_ASM_bsp/memory.gdb @@ -0,0 +1,50 @@ +# memory.gdb - GDB memory region definitions +# +# Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' +# SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo +# +# Generated: Thu Dec 22 10:08:01 JST 2016 + +# DO NOT MODIFY THIS FILE +# +# Changing this file will have subtle consequences +# which will almost certainly lead to a nonfunctioning +# system. If you do modify this file, be aware that your +# changes will be overwritten and lost when this file +# is generated again. +# +# DO NOT MODIFY THIS FILE + +# License Agreement +# +# Copyright (c) 2008 +# Altera Corporation, San Jose, California, USA. +# All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# This agreement shall be governed in all respects by the laws of the State +# of California and by the laws of the United States of America. + +# Define memory regions for each memory connected to the CPU. +# The cache attribute is specified which improves GDB performance +# by allowing GDB to cache memory contents on the host. + +# onchip_memory +memory 0x0 0x32000 cache diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_alarm_start.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_alarm_start.d new file mode 100644 index 0000000..a293917 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_alarm_start.d @@ -0,0 +1,22 @@ +obj/HAL/src/alt_alarm_start.o: HAL/src/alt_alarm_start.c \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h linker.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_alarm_start.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_alarm_start.o new file mode 100644 index 0000000..4f3bca0 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_alarm_start.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_busy_sleep.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_busy_sleep.d new file mode 100644 index 0000000..0441737 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_busy_sleep.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_busy_sleep.o: HAL/src/alt_busy_sleep.c system.h linker.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_busy_sleep.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_busy_sleep.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_busy_sleep.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_busy_sleep.o new file mode 100644 index 0000000..2a164b8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_busy_sleep.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_close.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_close.d new file mode 100644 index 0000000..c678dc5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_close.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_close.o: HAL/src/alt_close.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_close.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_close.o new file mode 100644 index 0000000..04d3b24 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_close.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush.d new file mode 100644 index 0000000..cc01756 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush.o: HAL/src/alt_dcache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush.o new file mode 100644 index 0000000..7d27351 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_all.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_all.d new file mode 100644 index 0000000..9b4b55d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush_all.o: HAL/src/alt_dcache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_all.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_all.o new file mode 100644 index 0000000..31cfc13 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_all.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d new file mode 100644 index 0000000..a1291f0 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_dcache_flush_no_writeback.o: \ + HAL/src/alt_dcache_flush_no_writeback.c HAL/inc/nios2.h system.h \ + linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h \ + HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o new file mode 100644 index 0000000..8fd2093 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev.d new file mode 100644 index 0000000..89b9883 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_dev.o: HAL/src/alt_dev.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev.o new file mode 100644 index 0000000..ebfcb30 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev_llist_insert.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev_llist_insert.d new file mode 100644 index 0000000..f23980f --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev_llist_insert.d @@ -0,0 +1,13 @@ +obj/HAL/src/alt_dev_llist_insert.o: HAL/src/alt_dev_llist_insert.c \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev_llist_insert.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev_llist_insert.o new file mode 100644 index 0000000..b692363 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dev_llist_insert.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_rxchan_open.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_rxchan_open.d new file mode 100644 index 0000000..71aa62d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_rxchan_open.d @@ -0,0 +1,35 @@ +obj/HAL/src/alt_dma_rxchan_open.o: HAL/src/alt_dma_rxchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_rxchan_open.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_rxchan_open.o new file mode 100644 index 0000000..365a4cb --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_rxchan_open.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_txchan_open.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_txchan_open.d new file mode 100644 index 0000000..2a33dba --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_txchan_open.d @@ -0,0 +1,35 @@ +obj/HAL/src/alt_dma_txchan_open.o: HAL/src/alt_dma_txchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_txchan_open.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_txchan_open.o new file mode 100644 index 0000000..0c1b725 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_dma_txchan_open.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_ctors.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_ctors.d new file mode 100644 index 0000000..0898fbc --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_ctors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_ctors.o: HAL/src/alt_do_ctors.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_ctors.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_ctors.o new file mode 100644 index 0000000..60716f5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_ctors.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_dtors.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_dtors.d new file mode 100644 index 0000000..abdadfa --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_dtors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_dtors.o: HAL/src/alt_do_dtors.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_dtors.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_dtors.o new file mode 100644 index 0000000..4ad3900 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_do_dtors.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_env_lock.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_env_lock.d new file mode 100644 index 0000000..fd8a733 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_env_lock.d @@ -0,0 +1 @@ +obj/HAL/src/alt_env_lock.o: HAL/src/alt_env_lock.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_env_lock.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_env_lock.o new file mode 100644 index 0000000..0d3164d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_env_lock.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_environ.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_environ.d new file mode 100644 index 0000000..b622e4b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_environ.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_environ.o: HAL/src/alt_environ.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_environ.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_environ.o new file mode 100644 index 0000000..2649aa8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_environ.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_errno.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_errno.d new file mode 100644 index 0000000..51c7dcd --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_errno.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_errno.o: HAL/src/alt_errno.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_errno.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_errno.o new file mode 100644 index 0000000..937978d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_errno.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_entry.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_entry.d new file mode 100644 index 0000000..7960631 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_entry.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_exception_entry.o: HAL/src/alt_exception_entry.S system.h \ + linker.h + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_entry.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_entry.o new file mode 100644 index 0000000..6ea2624 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_entry.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_muldiv.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_muldiv.d new file mode 100644 index 0000000..a1e5556 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_muldiv.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_muldiv.o: HAL/src/alt_exception_muldiv.S diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_muldiv.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_muldiv.o new file mode 100644 index 0000000..6b29f2a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_muldiv.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_trap.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_trap.d new file mode 100644 index 0000000..ef4edc6 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_trap.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_trap.o: HAL/src/alt_exception_trap.S diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_trap.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_trap.o new file mode 100644 index 0000000..c6ae459 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exception_trap.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_execve.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_execve.d new file mode 100644 index 0000000..0060a9d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_execve.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_execve.o: HAL/src/alt_execve.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_execve.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_execve.o new file mode 100644 index 0000000..44ac212 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_execve.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exit.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exit.d new file mode 100644 index 0000000..09ed618 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exit.d @@ -0,0 +1,26 @@ +obj/HAL/src/alt_exit.o: HAL/src/alt_exit.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_sim.h HAL/inc/os/alt_hooks.h HAL/inc/os/alt_syscall.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_sim.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exit.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exit.o new file mode 100644 index 0000000..d0a1f5c --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_exit.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fcntl.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fcntl.d new file mode 100644 index 0000000..b8835a6 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fcntl.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_fcntl.o: HAL/src/alt_fcntl.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fcntl.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fcntl.o new file mode 100644 index 0000000..51a1893 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fcntl.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_lock.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_lock.d new file mode 100644 index 0000000..f6d94e1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_lock.d @@ -0,0 +1,27 @@ +obj/HAL/src/alt_fd_lock.o: HAL/src/alt_fd_lock.c HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_lock.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_lock.o new file mode 100644 index 0000000..14a91cd --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_lock.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_unlock.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_unlock.d new file mode 100644 index 0000000..9778463 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_unlock.d @@ -0,0 +1,27 @@ +obj/HAL/src/alt_fd_unlock.o: HAL/src/alt_fd_unlock.c \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_unlock.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_unlock.o new file mode 100644 index 0000000..b864aaf --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fd_unlock.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_dev.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_dev.d new file mode 100644 index 0000000..7b37308 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_dev.d @@ -0,0 +1,31 @@ +obj/HAL/src/alt_find_dev.o: HAL/src/alt_find_dev.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_dev.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_dev.o new file mode 100644 index 0000000..a5d234e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_dev.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_file.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_file.d new file mode 100644 index 0000000..4f15c6d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_file.d @@ -0,0 +1,32 @@ +obj/HAL/src/alt_find_file.o: HAL/src/alt_find_file.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_file.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_file.o new file mode 100644 index 0000000..7eb6407 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_find_file.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_flash_dev.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_flash_dev.d new file mode 100644 index 0000000..e665b37 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_flash_dev.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_flash_dev.o: HAL/src/alt_flash_dev.c \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/sys/alt_flash_dev.h \ + HAL/inc/sys/alt_flash_types.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_flash_dev.h: + +HAL/inc/sys/alt_flash_types.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_flash_dev.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_flash_dev.o new file mode 100644 index 0000000..f94c9bb --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_flash_dev.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fork.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fork.d new file mode 100644 index 0000000..ef5b637 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fork.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_fork.o: HAL/src/alt_fork.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fork.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fork.o new file mode 100644 index 0000000..fc9ff9e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fork.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fs_reg.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fs_reg.d new file mode 100644 index 0000000..f56b56f --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fs_reg.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_fs_reg.o: HAL/src/alt_fs_reg.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fs_reg.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fs_reg.o new file mode 100644 index 0000000..5dac05e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fs_reg.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fstat.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fstat.d new file mode 100644 index 0000000..b1c4a1e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fstat.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_fstat.o: HAL/src/alt_fstat.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fstat.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fstat.o new file mode 100644 index 0000000..c336fad --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_fstat.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_get_fd.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_get_fd.d new file mode 100644 index 0000000..5524f68 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_get_fd.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_get_fd.o: HAL/src/alt_get_fd.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/alt_types.h \ + system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_get_fd.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_get_fd.o new file mode 100644 index 0000000..99a830d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_get_fd.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getchar.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getchar.d new file mode 100644 index 0000000..aa88591 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_getchar.o: HAL/src/alt_getchar.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getchar.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getchar.o new file mode 100644 index 0000000..9510525 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getchar.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getpid.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getpid.d new file mode 100644 index 0000000..365651b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getpid.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_getpid.o: HAL/src/alt_getpid.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getpid.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getpid.o new file mode 100644 index 0000000..d6d72cd --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_getpid.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gettod.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gettod.d new file mode 100644 index 0000000..ffd23b8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gettod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_gettod.o: HAL/src/alt_gettod.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gettod.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gettod.o new file mode 100644 index 0000000..f31c5e4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gettod.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gmon.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gmon.d new file mode 100644 index 0000000..6a213bf --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gmon.d @@ -0,0 +1,24 @@ +obj/HAL/src/alt_gmon.o: HAL/src/alt_gmon.c HAL/inc/priv/nios2_gmon_data.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h + +HAL/inc/priv/nios2_gmon_data.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gmon.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gmon.o new file mode 100644 index 0000000..aa23eb5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_gmon.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush.d new file mode 100644 index 0000000..a6048d7 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush.o: HAL/src/alt_icache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush.o new file mode 100644 index 0000000..422343c --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush_all.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush_all.d new file mode 100644 index 0000000..19ee42e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush_all.o: HAL/src/alt_icache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush_all.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush_all.o new file mode 100644 index 0000000..3238a51 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_icache_flush_all.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic.d new file mode 100644 index 0000000..444ca68 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_iic.o: HAL/src/alt_iic.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_irq.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_iic_isr_register.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic.o new file mode 100644 index 0000000..ac4935a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic_isr_register.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic_isr_register.d new file mode 100644 index 0000000..93b9138 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic_isr_register.d @@ -0,0 +1,30 @@ +obj/HAL/src/alt_iic_isr_register.o: HAL/src/alt_iic_isr_register.c \ + system.h linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_iic_isr_register.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_iic_isr_register.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic_isr_register.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic_isr_register.o new file mode 100644 index 0000000..c29d140 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_iic_isr_register.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_entry.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_entry.d new file mode 100644 index 0000000..f91b75a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_entry.d @@ -0,0 +1,18 @@ +obj/HAL/src/alt_instruction_exception_entry.o: \ + HAL/src/alt_instruction_exception_entry.c HAL/inc/sys/alt_exceptions.h \ + HAL/inc/alt_types.h system.h linker.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_entry.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_entry.o new file mode 100644 index 0000000..0684da4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_entry.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_register.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_register.d new file mode 100644 index 0000000..24c4435 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_register.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_instruction_exception_register.o: \ + HAL/src/alt_instruction_exception_register.c \ + HAL/inc/sys/alt_exceptions.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_register.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_register.o new file mode 100644 index 0000000..4801278 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_instruction_exception_register.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_io_redirect.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_io_redirect.d new file mode 100644 index 0000000..d84ac28 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_io_redirect.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_io_redirect.o: HAL/src/alt_io_redirect.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_io_redirect.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_io_redirect.o new file mode 100644 index 0000000..09e3da5 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_io_redirect.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_ioctl.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_ioctl.d new file mode 100644 index 0000000..0b46e82 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_ioctl.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_ioctl.o: HAL/src/alt_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_ioctl.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_ioctl.o new file mode 100644 index 0000000..450be60 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_ioctl.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_entry.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_entry.d new file mode 100644 index 0000000..c2477c1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_entry.d @@ -0,0 +1,5 @@ +obj/HAL/src/alt_irq_entry.o: HAL/src/alt_irq_entry.S system.h linker.h + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_entry.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_entry.o new file mode 100644 index 0000000..5231892 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_entry.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_handler.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_handler.d new file mode 100644 index 0000000..c6ee821 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_handler.d @@ -0,0 +1,19 @@ +obj/HAL/src/alt_irq_handler.o: HAL/src/alt_irq_handler.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/os/alt_hooks.h HAL/inc/alt_types.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_handler.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_handler.o new file mode 100644 index 0000000..b426af1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_handler.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_register.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_register.d new file mode 100644 index 0000000..ad1830e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_register.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_irq_register.o: HAL/src/alt_irq_register.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/os/alt_hooks.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_register.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_register.o new file mode 100644 index 0000000..0972295 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_register.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_vars.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_vars.d new file mode 100644 index 0000000..c339fc6 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_vars.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_irq_vars.o: HAL/src/alt_irq_vars.c HAL/inc/alt_types.h \ + system.h linker.h + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_vars.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_vars.o new file mode 100644 index 0000000..5959d94 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_irq_vars.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_isatty.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_isatty.d new file mode 100644 index 0000000..1b9868b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_isatty.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_isatty.o: HAL/src/alt_isatty.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_isatty.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_isatty.o new file mode 100644 index 0000000..1037442 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_isatty.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_kill.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_kill.d new file mode 100644 index 0000000..7ced1b6 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_kill.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_kill.o: HAL/src/alt_kill.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_kill.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_kill.o new file mode 100644 index 0000000..97c2fd2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_kill.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_link.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_link.d new file mode 100644 index 0000000..2156c3d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_link.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_link.o: HAL/src/alt_link.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_link.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_link.o new file mode 100644 index 0000000..9f255ee --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_link.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_load.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_load.d new file mode 100644 index 0000000..ff64508 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_load.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_load.o: HAL/src/alt_load.c HAL/inc/sys/alt_load.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h + +HAL/inc/sys/alt_load.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_load.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_load.o new file mode 100644 index 0000000..e0c7367 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_load.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_macro.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_macro.d new file mode 100644 index 0000000..b6c30c4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_macro.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_macro.o: HAL/src/alt_log_macro.S diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_macro.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_macro.o new file mode 100644 index 0000000..489e2cc --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_macro.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_printf.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_printf.d new file mode 100644 index 0000000..ddd7cdb --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_printf.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_printf.o: HAL/src/alt_log_printf.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_printf.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_printf.o new file mode 100644 index 0000000..a03c33d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_log_printf.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_lseek.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_lseek.d new file mode 100644 index 0000000..a103673 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_lseek.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_lseek.o: HAL/src/alt_lseek.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_lseek.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_lseek.o new file mode 100644 index 0000000..47d3ab4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_lseek.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_main.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_main.d new file mode 100644 index 0000000..67b6a7b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_main.d @@ -0,0 +1,47 @@ +obj/HAL/src/alt_main.o: HAL/src/alt_main.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_sys_init.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/os/alt_hooks.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h system.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_main.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_main.o new file mode 100644 index 0000000..8cbd03c --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_main.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_malloc_lock.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_malloc_lock.d new file mode 100644 index 0000000..981b056 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_malloc_lock.d @@ -0,0 +1 @@ +obj/HAL/src/alt_malloc_lock.o: HAL/src/alt_malloc_lock.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_malloc_lock.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_malloc_lock.o new file mode 100644 index 0000000..fa7f6c1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_malloc_lock.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_mcount.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_mcount.d new file mode 100644 index 0000000..4fa3643 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_mcount.d @@ -0,0 +1 @@ +obj/HAL/src/alt_mcount.o: HAL/src/alt_mcount.S diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_mcount.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_mcount.o new file mode 100644 index 0000000..25a99a8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_mcount.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_open.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_open.d new file mode 100644 index 0000000..a5c2358 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_open.d @@ -0,0 +1,36 @@ +obj/HAL/src/alt_open.o: HAL/src/alt_open.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_open.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_open.o new file mode 100644 index 0000000..2c3dce1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_open.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_printf.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_printf.d new file mode 100644 index 0000000..0fe3550 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_printf.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_printf.o: HAL/src/alt_printf.c HAL/inc/sys/alt_stdio.h + +HAL/inc/sys/alt_stdio.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_printf.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_printf.o new file mode 100644 index 0000000..98fe49b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_printf.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putchar.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putchar.d new file mode 100644 index 0000000..fa6d19f --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putchar.o: HAL/src/alt_putchar.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putchar.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putchar.o new file mode 100644 index 0000000..619c07a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putchar.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putstr.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putstr.d new file mode 100644 index 0000000..a28ce55 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putstr.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putstr.o: HAL/src/alt_putstr.c diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putstr.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putstr.o new file mode 100644 index 0000000..ffcb95a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_putstr.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_read.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_read.d new file mode 100644 index 0000000..f5d459d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_read.d @@ -0,0 +1,34 @@ +obj/HAL/src/alt_read.o: HAL/src/alt_read.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_read.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_read.o new file mode 100644 index 0000000..6e5b532 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_read.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_release_fd.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_release_fd.d new file mode 100644 index 0000000..137f496 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_release_fd.d @@ -0,0 +1,29 @@ +obj/HAL/src/alt_release_fd.o: HAL/src/alt_release_fd.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_release_fd.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_release_fd.o new file mode 100644 index 0000000..e26e93e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_release_fd.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_cached.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_cached.d new file mode 100644 index 0000000..abacaa4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_cached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_cached.o: HAL/src/alt_remap_cached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_cached.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_cached.o new file mode 100644 index 0000000..0977747 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_cached.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_uncached.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_uncached.d new file mode 100644 index 0000000..19b8e4c --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_uncached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_uncached.o: HAL/src/alt_remap_uncached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_uncached.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_uncached.o new file mode 100644 index 0000000..6690e93 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_remap_uncached.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_rename.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_rename.d new file mode 100644 index 0000000..f16ad38 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_rename.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_rename.o: HAL/src/alt_rename.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_rename.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_rename.o new file mode 100644 index 0000000..efd10ac --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_rename.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_sbrk.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_sbrk.d new file mode 100644 index 0000000..cc6de28 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_sbrk.d @@ -0,0 +1,19 @@ +obj/HAL/src/alt_sbrk.o: HAL/src/alt_sbrk.c HAL/inc/os/alt_syscall.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/sys/alt_stack.h system.h + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_stack.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_sbrk.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_sbrk.o new file mode 100644 index 0000000..ce37cb2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_sbrk.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_settod.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_settod.d new file mode 100644 index 0000000..f8e7109 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_settod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_settod.o: HAL/src/alt_settod.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_settod.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_settod.o new file mode 100644 index 0000000..69ee2bd --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_settod.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_software_exception.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_software_exception.d new file mode 100644 index 0000000..d17d10b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_software_exception.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_software_exception.o: HAL/src/alt_software_exception.S \ + system.h linker.h + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_software_exception.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_software_exception.o new file mode 100644 index 0000000..f9e01c2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_software_exception.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_stat.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_stat.d new file mode 100644 index 0000000..b66e05e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_stat.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_stat.o: HAL/src/alt_stat.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_stat.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_stat.o new file mode 100644 index 0000000..447fdd4 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_stat.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_tick.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_tick.d new file mode 100644 index 0000000..88d8e2a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_tick.d @@ -0,0 +1,27 @@ +obj/HAL/src/alt_tick.o: HAL/src/alt_tick.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_hooks.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_hooks.h: + +HAL/inc/alt_types.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_tick.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_tick.o new file mode 100644 index 0000000..804371d --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_tick.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_times.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_times.d new file mode 100644 index 0000000..e0ded1e --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_times.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_times.o: HAL/src/alt_times.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_times.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_times.o new file mode 100644 index 0000000..f55a589 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_times.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_free.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_free.d new file mode 100644 index 0000000..7d5ae2b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_free.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_free.o: HAL/src/alt_uncached_free.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_free.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_free.o new file mode 100644 index 0000000..fb1dd20 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_free.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_malloc.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_malloc.d new file mode 100644 index 0000000..05d57d8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_malloc.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_malloc.o: HAL/src/alt_uncached_malloc.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_malloc.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_malloc.o new file mode 100644 index 0000000..c34d431 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_uncached_malloc.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_unlink.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_unlink.d new file mode 100644 index 0000000..04b6dcd --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_unlink.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_unlink.o: HAL/src/alt_unlink.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_unlink.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_unlink.o new file mode 100644 index 0000000..f9f197a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_unlink.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_usleep.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_usleep.d new file mode 100644 index 0000000..c3ccee2 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_usleep.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_usleep.o: HAL/src/alt_usleep.c \ + HAL/inc/priv/alt_busy_sleep.h HAL/inc/os/alt_syscall.h + +HAL/inc/priv/alt_busy_sleep.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_usleep.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_usleep.o new file mode 100644 index 0000000..c0fce84 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_usleep.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_wait.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_wait.d new file mode 100644 index 0000000..98bf5df --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_wait.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_wait.o: HAL/src/alt_wait.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_wait.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_wait.o new file mode 100644 index 0000000..5414f98 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_wait.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_write.d b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_write.d new file mode 100644 index 0000000..722e8bc --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_write.d @@ -0,0 +1,38 @@ +obj/HAL/src/alt_write.o: HAL/src/alt_write.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h \ + HAL/inc/os/alt_syscall.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/alt_write.o b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_write.o new file mode 100644 index 0000000..76bbfa3 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/alt_write.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/altera_nios2_qsys_irq.d b/software/DE2_115_ASM_bsp/obj/HAL/src/altera_nios2_qsys_irq.d new file mode 100644 index 0000000..45223c8 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/altera_nios2_qsys_irq.d @@ -0,0 +1,15 @@ +obj/HAL/src/altera_nios2_qsys_irq.o: HAL/src/altera_nios2_qsys_irq.c \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/altera_nios2_qsys_irq.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/altera_nios2_qsys_irq.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/altera_nios2_qsys_irq.o b/software/DE2_115_ASM_bsp/obj/HAL/src/altera_nios2_qsys_irq.o new file mode 100644 index 0000000..c44ed71 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/altera_nios2_qsys_irq.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/crt0.d b/software/DE2_115_ASM_bsp/obj/HAL/src/crt0.d new file mode 100644 index 0000000..c1049a0 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/crt0.d @@ -0,0 +1,12 @@ +obj/HAL/src/crt0.o: HAL/src/crt0.S system.h linker.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_log_printf.h system.h + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/HAL/src/crt0.o b/software/DE2_115_ASM_bsp/obj/HAL/src/crt0.o new file mode 100644 index 0000000..b1e00ac --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/HAL/src/crt0.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/alt_sys_init.d b/software/DE2_115_ASM_bsp/obj/alt_sys_init.d new file mode 100644 index 0000000..df7e15a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/alt_sys_init.d @@ -0,0 +1,59 @@ +obj/alt_sys_init.o: alt_sys_init.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/sys/alt_sys_init.h HAL/inc/altera_nios2_qsys_irq.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_lcd_16207.h \ + drivers/inc/altera_avalon_lcd_16207_fd.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/altera_nios2_qsys_irq.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: diff --git a/software/DE2_115_ASM_bsp/obj/alt_sys_init.o b/software/DE2_115_ASM_bsp/obj/alt_sys_init.o new file mode 100644 index 0000000..f3cc066 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/alt_sys_init.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d new file mode 100644 index 0000000..5fd0251 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d @@ -0,0 +1,48 @@ +obj/drivers/src/altera_avalon_jtag_uart_fd.o: \ + drivers/src/altera_avalon_jtag_uart_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o new file mode 100644 index 0000000..ab5f6c0 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d new file mode 100644 index 0000000..39101c1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d @@ -0,0 +1,66 @@ +obj/drivers/src/altera_avalon_jtag_uart_init.o: \ + drivers/src/altera_avalon_jtag_uart_init.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o new file mode 100644 index 0000000..a4ae140 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d new file mode 100644 index 0000000..39508a1 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d @@ -0,0 +1,58 @@ +obj/drivers/src/altera_avalon_jtag_uart_ioctl.o: \ + drivers/src/altera_avalon_jtag_uart_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/os/alt_sem.h HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o new file mode 100644 index 0000000..3de41e3 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d new file mode 100644 index 0000000..915c27a --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d @@ -0,0 +1,66 @@ +obj/drivers/src/altera_avalon_jtag_uart_read.o: \ + drivers/src/altera_avalon_jtag_uart_read.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o new file mode 100644 index 0000000..5684a51 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d new file mode 100644 index 0000000..4e67aaa --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d @@ -0,0 +1,66 @@ +obj/drivers/src/altera_avalon_jtag_uart_write.o: \ + drivers/src/altera_avalon_jtag_uart_write.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h HAL/inc/os/alt_flag.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +HAL/inc/os/alt_flag.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o new file mode 100644 index 0000000..7e753e7 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207.d b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207.d new file mode 100644 index 0000000..238baea --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207.d @@ -0,0 +1,47 @@ +obj/drivers/src/altera_avalon_lcd_16207.o: \ + drivers/src/altera_avalon_lcd_16207.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_lcd_16207.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207.o b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207.o new file mode 100644 index 0000000..4c2016c --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d new file mode 100644 index 0000000..d45be02 --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.d @@ -0,0 +1,43 @@ +obj/drivers/src/altera_avalon_lcd_16207_fd.o: \ + drivers/src/altera_avalon_lcd_16207_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_lcd_16207.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/os/alt_sem.h \ + HAL/inc/priv/alt_no_error.h drivers/inc/altera_avalon_lcd_16207_fd.h \ + HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_lcd_16207.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/os/alt_sem.h: + +HAL/inc/priv/alt_no_error.h: + +drivers/inc/altera_avalon_lcd_16207_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.o b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.o new file mode 100644 index 0000000..a926c2b --- /dev/null +++ b/software/DE2_115_ASM_bsp/obj/drivers/src/altera_avalon_lcd_16207_fd.o Binary files differ diff --git a/software/DE2_115_ASM_bsp/public.mk b/software/DE2_115_ASM_bsp/public.mk new file mode 100644 index 0000000..a8f9076 --- /dev/null +++ b/software/DE2_115_ASM_bsp/public.mk @@ -0,0 +1,377 @@ +#------------------------------------------------------------------------------ +# BSP "PUBLIC" MAKEFILE CONTENT +# +# This file is intended to be included in an application or library +# Makefile that is using this BSP. You can create such a Makefile with +# the nios2-app-generate-makefile or nios2-lib-generate-makefile +# commands. +# +# The following variables must be defined before including this file: +# +# ALT_LIBRARY_ROOT_DIR +# Contains the path to the BSP top-level (aka root) directory +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# PATHS +#------------------------------------------------------------------------------ + + + +# Path to the provided linker script. +BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x + +# Include paths: +# The path to root of all header files that a library wishes to make +# available for an application's use is specified here. Note that this +# may not be *all* folders within a hierarchy. For example, if it is +# desired that the application developer type: +# #include +# #include +# With files laid out like this: +# /inc/sockets.h +# /inc/ip/tcpip.h +# +# Then, only /inc need be added to the list of include +# directories. Alternatively, if you wish to be able to directly include +# all files in a hierarchy, separate paths to each folder in that +# hierarchy must be defined. + +# The following are the "base" set of include paths for a BSP. +# These paths are appended to the list that individual software +# components, drivers, etc., add in the generated portion of this +# file (below). +ALT_INCLUDE_DIRS_TO_APPEND += \ + $(ALT_LIBRARY_ROOT_DIR) \ + $(ALT_LIBRARY_ROOT_DIR)/drivers/inc + +# Additions to linker library search-path: +# Here we provide a path to "our self" for the application to construct a +# "-L " out of. This should contain a list of directories, +# relative to the library root, of all directories with .a files to link +# against. +ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) + + +#------------------------------------------------------------------------------ +# COMPILATION FLAGS +#------------------------------------------------------------------------------ +# Default C pre-processor flags for a BSP: +ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ + -pipe + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +#------------------------------------------------------------------------------ +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PUBLIC_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 13.0sp1 +ACDS_VERSION := 13.0sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 232 + +# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with +# design component names. +SOPCINFO_FILE := C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + +# Big-Endian operation. +# setting BIG_ENDIAN is false +ALT_CFLAGS += -EL + +# Path to the provided C language runtime initialization code. +BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o + +# Name of BSP library as provided to linker using the "-msys-lib" flag or +# linker script GROUP command. +# setting BSP_SYS_LIB is hal_bsp +BSP_SYS_LIB := hal_bsp +ELF_PATCH_FLAG += --thread_model hal + +# Type identifier of the BSP library +# setting BSP_TYPE is hal +ALT_CPPFLAGS += -D__hal__ +BSP_TYPE := hal + +# CPU Name +# setting CPU_NAME is nios2_processor +CPU_NAME = nios2_processor +ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) + +# Hardware Divider present. +# setting HARDWARE_DIVIDE is false +ALT_CFLAGS += -mno-hw-div + +# Hardware Multiplier present. +# setting HARDWARE_MULTIPLY is false +ALT_CFLAGS += -mno-hw-mul + +# Hardware Mulx present. +# setting HARDWARE_MULX is false +ALT_CFLAGS += -mno-hw-mulx + +# Debug Core present. +# setting HAS_DEBUG_CORE is true +CPU_HAS_DEBUG_CORE = 1 + +# Qsys generated design +# setting QSYS is 1 +QSYS := 1 +ELF_PATCH_FLAG += --qsys true + +# Design Name +# setting SOPC_NAME is nios_system +SOPC_NAME := nios_system + +# SopcBuilder Simulation Enabled +# setting SOPC_SIMULATION_ENABLED is false +ELF_PATCH_FLAG += --simulation_enabled false + +# Enable JTAG UART driver to recover when host is inactive causing buffer to +# full without returning error. Printf will not fail with this recovery. none +# setting altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error is false + +# Small-footprint (polled mode) driver none +# setting altera_avalon_jtag_uart_driver.enable_small_driver is false + +# Build a custom version of newlib with the specified space-separated compiler +# flags. The custom newlib build will be placed in the <bsp root>/newlib +# directory, and will be used only for applications that utilize this BSP. +# setting hal.custom_newlib_flags is none + +# Enable support for a subset of the C++ language. This option increases code +# footprint by adding support for C++ constructors. Certain features, such as +# multiple inheritance and exceptions are not supported. If false, adds +# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code +# footprint. none +# setting hal.enable_c_plus_plus is true + +# When your application exits, close file descriptors, call C++ destructors, +# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds +# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to +# ALT_LDFLAGS in public.mk. none +# setting hal.enable_clean_exit is true + +# Add exit() support. This option increases code footprint if your "main()" +# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to +# ALT_CPPFLAGS in public.mk, and reduces footprint none +# setting hal.enable_exit is true + +# Causes code to be compiled with gprof profiling enabled and the application +# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to +# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none +# setting hal.enable_gprof is false + +# Enables lightweight device driver API. This reduces code and data footprint +# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file +# descriptors. Instead, driver routines are called directly. The open(), +# close(), and lseek() routines will always fail if called. The read(), +# write(), fstat(), ioctl(), and isatty() routines only work for the stdio +# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. +# The Altera Host and read-only ZIP file systems can't be used if +# hal.enable_lightweight_device_driver_api is true. +# setting hal.enable_lightweight_device_driver_api is false + +# Adds code to emulate multiply and divide instructions in case they are +# executed but aren't present in the CPU. Normally this isn't required because +# the compiler won't use multiply and divide instructions that aren't present +# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_mul_div_emulation is false +ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION + +# Certain drivers are compiled with reduced functionality to reduce code +# footprint. Not all drivers observe this setting. The altera_avalon_uart and +# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled +# operation. CAUTION: Several device drivers are disabled entirely. These +# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and +# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash +# access routines) to fail. You can define a symbol provided by each driver to +# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to +# ALT_CPPFLAGS in public.mk. none +# setting hal.enable_reduced_device_drivers is false + +# Turns on HAL runtime stack checking feature. Enabling this setting causes +# additional code to be placed into each subroutine call to generate an +# exception if a stack collision occurs with the heap or statically allocated +# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_runtime_stack_checking is false + +# The BSP is compiled with optimizations to speedup HDL simulation such as +# initializing the cache, clearing the .bss section, and skipping long delay +# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When +# this setting is true, the BSP shouldn't be used to build applications that +# are expected to run real hardware. +# setting hal.enable_sim_optimize is false + +# Causes the small newlib (C library) to be used. This reduces code and data +# footprint at the expense of reduced functionality. Several newlib features +# are removed such as floating-point support in printf(), stdin input routines, +# and buffered I/O. The small C library is not compatible with Micrium +# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none +# setting hal.enable_small_c_library is false + +# Enable SOPC Builder System ID. If a System ID SOPC Builder component is +# connected to the CPU associated with this BSP, it will be enabled in the +# creation of command-line arguments to download an ELF to the target. +# Otherwise, system ID and timestamp values are left out of public.mk for +# application Makefile "download-elf" target definition. With the system ID +# check disabled, the Nios II EDS tools will not automatically ensure that the +# application .elf file (and BSP it is linked against) corresponds to the +# hardware design on the target. If false, adds --accept-bad-sysid to +# SOPC_SYSID_FLAG in public.mk. none +# setting hal.enable_sopc_sysid_check is true + +# Enable BSP generation to query if SOPC system is big endian. If true ignores +# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true +# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none +# setting hal.make.ignore_system_derived.big_endian is false + +# Enable BSP generation to query if SOPC system has a debug core present. If +# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core +# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if +# no debug core is found in the system. none +# setting hal.make.ignore_system_derived.debug_core_present is false + +# Enable BSP generation to query if SOPC system has FPU present. If true +# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found +# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU +# is not found in the system. none +# setting hal.make.ignore_system_derived.fpu_present is false + +# Enable BSP generation to query if SOPC system has hardware divide present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no +# division is found in system. If true ignores export of 'ALT_CFLAGS += +# -mhw-div' if division is found in the system. none +# setting hal.make.ignore_system_derived.hardware_divide_present is false + +# Enable BSP generation to query if SOPC system floating point custom +# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS +# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to +# public.mk if the custom instruction is found in the system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false + +# Enable BSP generation to query if SOPC system floating point custom +# instruction without a divider is present. If true ignores export of +# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += +# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the +# system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false + +# Enable BSP generation to query if SOPC system has multiplier present. If true +# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if +# multiplier is found in the system. none +# setting hal.make.ignore_system_derived.hardware_multiplier_present is false + +# Enable BSP generation to query if SOPC system has hardware mulx present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' +# if mulx is found in the system. none +# setting hal.make.ignore_system_derived.hardware_mulx_present is false + +# Enable BSP generation to query if SOPC system has simulation enabled. If true +# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_simulation_enabled is false + +# Enable BSP generation to query SOPC system for system ID base address. If +# true ignores export of 'SOPC_SYSID_FLAG += --sidp=
' and +# 'ELF_PATCH_FLAG += --sidp=
' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_base_address is false + +# Enable BSP generation to query SOPC system for system ID. If true ignores +# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += +# --id=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_id is false + +# Enable BSP generation to query SOPC system for system timestamp. If true +# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and +# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_timestamp is false + +# Slave descriptor of STDERR character-mode device. This setting is used by the +# ALT_STDERR family of defines in system.h. none +# setting hal.stderr is jtag_uart +ELF_PATCH_FLAG += --stderr_dev jtag_uart + +# Slave descriptor of STDIN character-mode device. This setting is used by the +# ALT_STDIN family of defines in system.h. none +# setting hal.stdin is jtag_uart +ELF_PATCH_FLAG += --stdin_dev jtag_uart + +# Slave descriptor of STDOUT character-mode device. This setting is used by the +# ALT_STDOUT family of defines in system.h. none +# setting hal.stdout is jtag_uart +ELF_PATCH_FLAG += --stdout_dev jtag_uart + + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS +#------------------------------------------------------------------------------ + +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS +#------------------------------------------------------------------------------ + +ALT_CPPFLAGS += -DALT_SINGLE_THREADED + +#END MANAGED + + +#------------------------------------------------------------------------------ +# LIBRARY INFORMATION +#------------------------------------------------------------------------------ +# Assemble the name of the BSP *.a file using the BSP library name +# (BSP_SYS_LIB) in generated content above. +BSP_LIB := lib$(BSP_SYS_LIB).a + +# Additional libraries to link against: +# An application including this file will prefix each library with "-l". +# For example, to include the Newlib math library "m" is included, which +# becomes "-lm" when linking the application. +ALT_LIBRARY_NAMES += m + +# Additions to linker dependencies: +# An application Makefile will typically add these directly to the list +# of dependencies required to build the executable target(s). The BSP +# library (*.a) file is specified here. +ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) + +# Is this library "Makeable"? +# Add to list of root library directories that support running 'make' +# to build them. Because libraries may or may not have a Makefile in their +# root, appending to this variable tells an application to run 'make' in +# the library root to build/update this library. +MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) + +# Additional Assembler Flags +# -gdwarf2 flag is required for stepping through assembly code +ALT_ASFLAGS += -gdwarf2 + +#------------------------------------------------------------------------------ +# FINAL INCLUDE PATH LIST +#------------------------------------------------------------------------------ +# Append static include paths to paths specified by OS/driver/sw package +# additions to the BSP thus giving them precedence in case a BSP addition +# is attempting to override BSP sources. +ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) + + + diff --git a/software/DE2_115_ASM_bsp/settings.bsp b/software/DE2_115_ASM_bsp/settings.bsp new file mode 100644 index 0000000..b972903 --- /dev/null +++ b/software/DE2_115_ASM_bsp/settings.bsp @@ -0,0 +1,991 @@ + + + hal + default + 2016/12/22 10:07:59 + 1482368879543 + C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\DE2_115_ASM_bsp + .\settings.bsp + C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo + default + nios2_processor + 1.9 + + hal.sys_clk_timer + ALT_SYS_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. + none + false + common + + + hal.timestamp_timer + ALT_TIMESTAMP_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. + none + false + common + + + hal.max_file_descriptors + ALT_MAX_FD + DecimalNumber + 32 + 32 + system_h_define + Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. + If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. + false + + + + hal.enable_instruction_related_exceptions_api + ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + BooleanDefineOnly + false + false + system_h_define + Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. + These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. + false + + + + hal.linker.allow_code_at_reset + ALT_ALLOW_CODE_AT_RESET + Boolean + 1 + 0 + none + Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. + If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load + NONE + Boolean + 1 + 0 + none + Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. + This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load_copy_rodata + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_rwdata + NONE + Boolean + 1 + 0 + none + Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_exceptions + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. + none + false + + + + hal.linker.enable_exception_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. + The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.exception_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the exception stack in bytes. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.exception_stack_memory_region_name + NONE + UnquotedString + onchip_memory + none + none + Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.enable_interrupt_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. + The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.interrupt_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the interrupt stack in bytes. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.linker.interrupt_stack_memory_region_name + NONE + UnquotedString + onchip_memory + none + none + Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.stdin + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. + none + false + common + + + hal.stdout + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. + none + false + common + + + hal.stderr + NONE + UnquotedString + jtag_uart + none + system_h_define + Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. + none + false + common + + + hal.log_port + NONE + UnquotedString + none + none + public_mk_define + Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. + none + false + none + + + hal.make.build_pre_process + BUILD_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before BSP built. + none + false + none + + + hal.make.ar_pre_process + AR_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before archiver execution. + none + false + none + + + hal.make.bsp_cflags_defined_symbols + BSP_CFLAGS_DEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.ar_post_process + AR_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after archiver execution. + none + false + none + + + hal.make.as + AS + UnquotedString + nios2-elf-gcc + nios2-elf-gcc + makefile_variable + Assembler command. Note that CC is used for .S files. + none + false + none + + + hal.make.build_post_process + BUILD_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after BSP built. + none + false + none + + + hal.make.bsp_cflags_debug + BSP_CFLAGS_DEBUG + UnquotedString + -g + -g + makefile_variable + C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. + none + false + common + + + hal.make.ar + AR + UnquotedString + nios2-elf-ar + nios2-elf-ar + makefile_variable + Archiver command. Creates library files. + none + false + none + + + hal.make.rm + RM + UnquotedString + rm -f + rm -f + makefile_variable + Command used to remove files during 'clean' target. + none + false + none + + + hal.make.cxx_pre_process + CXX_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.bsp_cflags_warnings + BSP_CFLAGS_WARNINGS + UnquotedString + -Wall + -Wall + makefile_variable + C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. + none + false + none + + + hal.make.bsp_arflags + BSP_ARFLAGS + UnquotedString + -src + -src + makefile_variable + Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. + none + false + none + + + hal.make.bsp_cflags_optimization + BSP_CFLAGS_OPTIMIZATION + UnquotedString + -O0 + -O0 + makefile_variable + C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. + none + false + common + + + hal.make.as_post_process + AS_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each assembly file is compiled. + none + false + none + + + hal.make.cc_pre_process + CC_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each .c/.S file is compiled. + none + false + none + + + hal.make.bsp_asflags + BSP_ASFLAGS + UnquotedString + -Wa,-gdwarf2 + -Wa,-gdwarf2 + makefile_variable + Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. + none + false + none + + + hal.make.as_pre_process + AS_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each assembly file is compiled. + none + false + none + + + hal.make.bsp_cflags_undefined_symbols + BSP_CFLAGS_UNDEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.cc_post_process + CC_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each .c/.S file is compiled. + none + false + none + + + hal.make.cxx_post_process + CXX_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.cc + CC + UnquotedString + nios2-elf-gcc -xc + nios2-elf-gcc -xc + makefile_variable + C compiler command. + none + false + none + + + hal.make.bsp_cxx_flags + BSP_CXXFLAGS + UnquotedString + none + none + makefile_variable + Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. + none + false + none + + + hal.make.bsp_inc_dirs + BSP_INC_DIRS + UnquotedString + none + none + makefile_variable + Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. + none + false + none + + + hal.make.cxx + CXX + UnquotedString + nios2-elf-gcc -xc++ + nios2-elf-gcc -xc++ + makefile_variable + C++ compiler command. + none + false + none + + + hal.make.bsp_cflags_user_flags + BSP_CFLAGS_USER_FLAGS + UnquotedString + none + none + makefile_variable + Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_id + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_timestamp + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_base_address + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_simulation_enabled + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.fpu_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_multiplier_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_mulx_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_divide_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. + none + false + none + + + hal.make.ignore_system_derived.debug_core_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. + none + false + none + + + hal.make.ignore_system_derived.big_endian + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.enable_exit + ALT_NO_EXIT + Boolean + 1 + 1 + public_mk_define + Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint + none + false + none + + + hal.enable_small_c_library + NONE + Boolean + 0 + 0 + public_mk_define + Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. + none + false + common + + + hal.enable_clean_exit + ALT_NO_CLEAN_EXIT + Boolean + 1 + 1 + public_mk_define + When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. + none + false + none + + + hal.enable_runtime_stack_checking + ALT_STACK_CHECK + Boolean + 0 + 0 + public_mk_define + Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_gprof + ALT_PROVIDE_GMON + Boolean + 0 + 0 + public_mk_define + Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. + none + false + common + + + hal.enable_c_plus_plus + ALT_NO_C_PLUS_PLUS + Boolean + 1 + 1 + public_mk_define + Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. + none + false + none + + + hal.enable_reduced_device_drivers + ALT_USE_SMALL_DRIVERS + Boolean + 0 + 0 + public_mk_define + Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. + none + false + common + + + hal.enable_lightweight_device_driver_api + ALT_USE_DIRECT_DRIVERS + Boolean + 0 + 0 + public_mk_define + Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. + The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. + false + none + + + hal.enable_mul_div_emulation + ALT_NO_INSTRUCTION_EMULATION + Boolean + 0 + 0 + public_mk_define + Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_sim_optimize + ALT_SIM_OPTIMIZE + Boolean + 0 + 0 + public_mk_define + The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. + When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. + false + common + + + hal.enable_sopc_sysid_check + NONE + Boolean + 1 + 1 + public_mk_define + Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. + none + false + none + + + hal.custom_newlib_flags + CUSTOM_NEWLIB_FLAGS + UnquotedString + none + none + public_mk_define + Build a custom version of newlib with the specified space-separated compiler flags. + The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP. + false + none + + + hal.log_flags + ALT_LOG_FLAGS + DecimalNumber + 0 + 0 + public_mk_define + The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. + hal.log_port must be set for this to be used. + false + none + + + altera_avalon_jtag_uart_driver.enable_small_driver + ALTERA_AVALON_JTAG_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error + ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR + BooleanDefineOnly + false + false + public_mk_define + Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery. + none + false + + + + onchip_memory + 0x00000000 - 0x00031FFF + 204800 + memory + + + lcd_on + 0x00041010 - 0x0004101F + 16 + + + + lcd_blon + 0x00041020 - 0x0004102F + 16 + + + + lcd_16207_0 + 0x00041030 - 0x0004103F + 16 + printable + + + hex7 + 0x00041040 - 0x0004104F + 16 + + + + hex6 + 0x00041050 - 0x0004105F + 16 + + + + hex5 + 0x00041060 - 0x0004106F + 16 + + + + hex4 + 0x00041070 - 0x0004107F + 16 + + + + hex3 + 0x00041080 - 0x0004108F + 16 + + + + hex2 + 0x00041090 - 0x0004109F + 16 + + + + hex1 + 0x000410A0 - 0x000410AF + 16 + + + + hex0 + 0x000410B0 - 0x000410BF + 16 + + + + push_switches + 0x000410C0 - 0x000410CF + 16 + + + + switches + 0x000410D0 - 0x000410DF + 16 + + + + LEDRs + 0x000410E0 - 0x000410EF + 16 + + + + LEDs + 0x000410F0 - 0x000410FF + 16 + + + + jtag_uart + 0x00041100 - 0x00041107 + 8 + printable + + + .text + onchip_memory + + + .rodata + onchip_memory + + + .rwdata + onchip_memory + + + .bss + onchip_memory + + + .heap + onchip_memory + + + .stack + onchip_memory + + \ No newline at end of file diff --git a/software/DE2_115_ASM_bsp/summary.html b/software/DE2_115_ASM_bsp/summary.html new file mode 100644 index 0000000..285ce87 --- /dev/null +++ b/software/DE2_115_ASM_bsp/summary.html @@ -0,0 +1,2047 @@ + +Altera Nios II BSP Summary + +

BSP Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BSP Type:hal
SOPC Design File:C:\Users\takayun\Documents\DE2-115\qsys_tutorial\nios_system.sopcinfo
Quartus JDI File:default
CPU:nios2_processor
BSP Settings File:.\settings.bsp
BSP Version:default
BSP Generated On:2016/12/22 10:07:59
BSP Generated Timestamp:1482368879543
BSP Generated Location:C:\Users\takayun\Documents\DE2-115\qsys_tutorial\software\DE2_115_ASM_bsp
+
+

Nios II Memory Map

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Slave DescriptorAddress RangeSizeAttributes
jtag_uart0x00041100 - 0x000411078printable
LEDs0x000410F0 - 0x000410FF16 
LEDRs0x000410E0 - 0x000410EF16 
switches0x000410D0 - 0x000410DF16 
push_switches0x000410C0 - 0x000410CF16 
hex00x000410B0 - 0x000410BF16 
hex10x000410A0 - 0x000410AF16 
hex20x00041090 - 0x0004109F16 
hex30x00041080 - 0x0004108F16 
hex40x00041070 - 0x0004107F16 
hex50x00041060 - 0x0004106F16 
hex60x00041050 - 0x0004105F16 
hex70x00041040 - 0x0004104F16 
lcd_16207_00x00041030 - 0x0004103F16printable
lcd_blon0x00041020 - 0x0004102F16 
lcd_on0x00041010 - 0x0004101F16 
onchip_memory0x00000000 - 0x00031FFF204800memory
+
+
+

Linker Regions

+ + + + +
RegionAddress RangeSizeMemoryOffset
+
+
+

Linker Section Mappings

+ + + + + + + + + + + + + + + + + + + + + + +
SectionRegion
.textonchip_memory
.rodataonchip_memory
.rwdataonchip_memory
.bssonchip_memory
.heaponchip_memory
.stackonchip_memory
+

Settings

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_jtag_uart_driver.enable_jtag_uart_ignore_fifo_full_error
Identifier:ALTERA_AVALON_JTAG_UART_IGNORE_FIFO_FULL_ERROR
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Enable JTAG UART driver to recover when host is inactive causing buffer to full without returning error. Printf will not fail with this recovery.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_JTAG_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.custom_newlib_flags
Identifier:CUSTOM_NEWLIB_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_c_plus_plus
Identifier:ALT_NO_C_PLUS_PLUS
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_clean_exit
Identifier:ALT_NO_CLEAN_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_exit
Identifier:ALT_NO_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_gprof
Identifier:ALT_PROVIDE_GMON
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_instruction_related_exceptions_api
Identifier:ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:system_h_define
Description:Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_lightweight_device_driver_api
Identifier:ALT_USE_DIRECT_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_mul_div_emulation
Identifier:ALT_NO_INSTRUCTION_EMULATION
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_reduced_device_drivers
Identifier:ALT_USE_SMALL_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_runtime_stack_checking
Identifier:ALT_STACK_CHECK
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sim_optimize
Identifier:ALT_SIM_OPTIMIZE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_small_c_library
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sopc_sysid_check
Identifier:NONE
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.allow_code_at_reset
Identifier:ALT_ALLOW_CODE_AT_RESET
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_exceptions
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rodata
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rwdata
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_exception_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_interrupt_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:onchip_memory
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the exception stack in bytes.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.interrupt_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:onchip_memory
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.interrupt_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the interrupt stack in bytes.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_flags
Identifier:ALT_LOG_FLAGS
Default Value:0
Value:0
Type:DecimalNumber
Destination:public_mk_define
Description:The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:hal.log_port must be set for this to be used.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_port
Identifier:NONE
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar
Identifier:AR
Default Value:nios2-elf-ar
Value:nios2-elf-ar
Type:UnquotedString
Destination:makefile_variable
Description:Archiver command. Creates library files.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_post_process
Identifier:AR_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after archiver execution.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_pre_process
Identifier:AR_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before archiver execution.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as
Identifier:AS
Default Value:nios2-elf-gcc
Value:nios2-elf-gcc
Type:UnquotedString
Destination:makefile_variable
Description:Assembler command. Note that CC is used for .S files.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_post_process
Identifier:AS_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each assembly file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_pre_process
Identifier:AS_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each assembly file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_arflags
Identifier:BSP_ARFLAGS
Default Value:-src
Value:-src
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_asflags
Identifier:BSP_ASFLAGS
Default Value:-Wa,-gdwarf2
Value:-Wa,-gdwarf2
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_debug
Identifier:BSP_CFLAGS_DEBUG
Default Value:-g
Value:-g
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_defined_symbols
Identifier:BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_optimization
Identifier:BSP_CFLAGS_OPTIMIZATION
Default Value:-O0
Value:-O0
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_undefined_symbols
Identifier:BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_user_flags
Identifier:BSP_CFLAGS_USER_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_warnings
Identifier:BSP_CFLAGS_WARNINGS
Default Value:-Wall
Value:-Wall
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cxx_flags
Identifier:BSP_CXXFLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_inc_dirs
Identifier:BSP_INC_DIRS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_post_process
Identifier:BUILD_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after BSP built.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_pre_process
Identifier:BUILD_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before BSP built.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc
Identifier:CC
Default Value:nios2-elf-gcc -xc
Value:nios2-elf-gcc -xc
Type:UnquotedString
Destination:makefile_variable
Description:C compiler command.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_post_process
Identifier:CC_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each .c/.S file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_pre_process
Identifier:CC_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each .c/.S file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx
Identifier:CXX
Default Value:nios2-elf-gcc -xc++
Value:nios2-elf-gcc -xc++
Type:UnquotedString
Destination:makefile_variable
Description:C++ compiler command.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_post_process
Identifier:CXX_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_pre_process
Identifier:CXX_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.big_endian
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.debug_core_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.fpu_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_divide_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_mulx_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_base_address
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_id
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.rm
Identifier:RM
Default Value:rm -f
Value:rm -f
Type:UnquotedString
Destination:makefile_variable
Description:Command used to remove files during 'clean' target.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.max_file_descriptors
Identifier:ALT_MAX_FD
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stderr
Identifier:NONE
Default Value:none
Value:jtag_uart
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdin
Identifier:NONE
Default Value:none
Value:jtag_uart
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdout
Identifier:NONE
Default Value:none
Value:jtag_uart
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.sys_clk_timer
Identifier:ALT_SYS_CLK
Default Value:none
Value:none
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.timestamp_timer
Identifier:ALT_TIMESTAMP_CLK
Default Value:none
Value:none
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:none
+
+
+
+ + diff --git a/software/DE2_115_ASM_bsp/system.h b/software/DE2_115_ASM_bsp/system.h new file mode 100644 index 0000000..6ff122a --- /dev/null +++ b/software/DE2_115_ASM_bsp/system.h @@ -0,0 +1,617 @@ +/* + * system.h - SOPC Builder system and BSP software package information + * + * Machine generated for CPU 'nios2_processor' in SOPC Builder design 'nios_system' + * SOPC Builder design path: C:/Users/takayun/Documents/DE2-115/qsys_tutorial/nios_system.sopcinfo + * + * Generated: Thu Dec 22 10:08:01 JST 2016 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __SYSTEM_H_ +#define __SYSTEM_H_ + +/* Include definitions from linker script generator */ +#include "linker.h" + + +/* + * CPU configuration + * + */ + +#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" +#define ALT_CPU_BIG_ENDIAN 0 +#define ALT_CPU_BREAK_ADDR 0x40820 +#define ALT_CPU_CPU_FREQ 50000000u +#define ALT_CPU_CPU_ID_SIZE 1 +#define ALT_CPU_CPU_ID_VALUE 0x00000000 +#define ALT_CPU_CPU_IMPLEMENTATION "tiny" +#define ALT_CPU_DATA_ADDR_WIDTH 0x13 +#define ALT_CPU_DCACHE_LINE_SIZE 0 +#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0 +#define ALT_CPU_DCACHE_SIZE 0 +#define ALT_CPU_EXCEPTION_ADDR 0x20 +#define ALT_CPU_FLUSHDA_SUPPORTED +#define ALT_CPU_FREQ 50000000 +#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 +#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0 +#define ALT_CPU_HARDWARE_MULX_PRESENT 0 +#define ALT_CPU_HAS_DEBUG_CORE 1 +#define ALT_CPU_HAS_DEBUG_STUB +#define ALT_CPU_HAS_JMPI_INSTRUCTION +#define ALT_CPU_ICACHE_LINE_SIZE 0 +#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0 +#define ALT_CPU_ICACHE_SIZE 0 +#define ALT_CPU_INST_ADDR_WIDTH 0x13 +#define ALT_CPU_NAME "nios2_processor" +#define ALT_CPU_RESET_ADDR 0x0 + + +/* + * CPU configuration (with legacy prefix - don't use these anymore) + * + */ + +#define NIOS2_BIG_ENDIAN 0 +#define NIOS2_BREAK_ADDR 0x40820 +#define NIOS2_CPU_FREQ 50000000u +#define NIOS2_CPU_ID_SIZE 1 +#define NIOS2_CPU_ID_VALUE 0x00000000 +#define NIOS2_CPU_IMPLEMENTATION "tiny" +#define NIOS2_DATA_ADDR_WIDTH 0x13 +#define NIOS2_DCACHE_LINE_SIZE 0 +#define NIOS2_DCACHE_LINE_SIZE_LOG2 0 +#define NIOS2_DCACHE_SIZE 0 +#define NIOS2_EXCEPTION_ADDR 0x20 +#define NIOS2_FLUSHDA_SUPPORTED +#define NIOS2_HARDWARE_DIVIDE_PRESENT 0 +#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0 +#define NIOS2_HARDWARE_MULX_PRESENT 0 +#define NIOS2_HAS_DEBUG_CORE 1 +#define NIOS2_HAS_DEBUG_STUB +#define NIOS2_HAS_JMPI_INSTRUCTION +#define NIOS2_ICACHE_LINE_SIZE 0 +#define NIOS2_ICACHE_LINE_SIZE_LOG2 0 +#define NIOS2_ICACHE_SIZE 0 +#define NIOS2_INST_ADDR_WIDTH 0x13 +#define NIOS2_RESET_ADDR 0x0 + + +/* + * Define for each module class mastered by the CPU + * + */ + +#define __ALTERA_AVALON_JTAG_UART +#define __ALTERA_AVALON_LCD_16207 +#define __ALTERA_AVALON_ONCHIP_MEMORY2 +#define __ALTERA_AVALON_PIO +#define __ALTERA_NIOS2_QSYS + + +/* + * LEDRs configuration + * + */ + +#define ALT_MODULE_CLASS_LEDRs altera_avalon_pio +#define LEDRS_BASE 0x410e0 +#define LEDRS_BIT_CLEARING_EDGE_REGISTER 0 +#define LEDRS_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LEDRS_CAPTURE 0 +#define LEDRS_DATA_WIDTH 18 +#define LEDRS_DO_TEST_BENCH_WIRING 0 +#define LEDRS_DRIVEN_SIM_VALUE 0 +#define LEDRS_EDGE_TYPE "NONE" +#define LEDRS_FREQ 50000000 +#define LEDRS_HAS_IN 0 +#define LEDRS_HAS_OUT 1 +#define LEDRS_HAS_TRI 0 +#define LEDRS_IRQ -1 +#define LEDRS_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LEDRS_IRQ_TYPE "NONE" +#define LEDRS_NAME "/dev/LEDRs" +#define LEDRS_RESET_VALUE 0 +#define LEDRS_SPAN 16 +#define LEDRS_TYPE "altera_avalon_pio" + + +/* + * LEDs configuration + * + */ + +#define ALT_MODULE_CLASS_LEDs altera_avalon_pio +#define LEDS_BASE 0x410f0 +#define LEDS_BIT_CLEARING_EDGE_REGISTER 0 +#define LEDS_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LEDS_CAPTURE 0 +#define LEDS_DATA_WIDTH 8 +#define LEDS_DO_TEST_BENCH_WIRING 0 +#define LEDS_DRIVEN_SIM_VALUE 0 +#define LEDS_EDGE_TYPE "NONE" +#define LEDS_FREQ 50000000 +#define LEDS_HAS_IN 0 +#define LEDS_HAS_OUT 1 +#define LEDS_HAS_TRI 0 +#define LEDS_IRQ -1 +#define LEDS_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LEDS_IRQ_TYPE "NONE" +#define LEDS_NAME "/dev/LEDs" +#define LEDS_RESET_VALUE 0 +#define LEDS_SPAN 16 +#define LEDS_TYPE "altera_avalon_pio" + + +/* + * System configuration + * + */ + +#define ALT_DEVICE_FAMILY "Cyclone IV E" +#define ALT_ENHANCED_INTERRUPT_API_PRESENT +#define ALT_IRQ_BASE NULL +#define ALT_LOG_PORT "/dev/null" +#define ALT_LOG_PORT_BASE 0x0 +#define ALT_LOG_PORT_DEV null +#define ALT_LOG_PORT_TYPE "" +#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 +#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 +#define ALT_NUM_INTERRUPT_CONTROLLERS 1 +#define ALT_STDERR "/dev/jtag_uart" +#define ALT_STDERR_BASE 0x41100 +#define ALT_STDERR_DEV jtag_uart +#define ALT_STDERR_IS_JTAG_UART +#define ALT_STDERR_PRESENT +#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" +#define ALT_STDIN "/dev/jtag_uart" +#define ALT_STDIN_BASE 0x41100 +#define ALT_STDIN_DEV jtag_uart +#define ALT_STDIN_IS_JTAG_UART +#define ALT_STDIN_PRESENT +#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" +#define ALT_STDOUT "/dev/jtag_uart" +#define ALT_STDOUT_BASE 0x41100 +#define ALT_STDOUT_DEV jtag_uart +#define ALT_STDOUT_IS_JTAG_UART +#define ALT_STDOUT_PRESENT +#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" +#define ALT_SYSTEM_NAME "nios_system" + + +/* + * hal configuration + * + */ + +#define ALT_MAX_FD 32 +#define ALT_SYS_CLK none +#define ALT_TIMESTAMP_CLK none + + +/* + * hex0 configuration + * + */ + +#define ALT_MODULE_CLASS_hex0 altera_avalon_pio +#define HEX0_BASE 0x410b0 +#define HEX0_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX0_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX0_CAPTURE 0 +#define HEX0_DATA_WIDTH 7 +#define HEX0_DO_TEST_BENCH_WIRING 0 +#define HEX0_DRIVEN_SIM_VALUE 0 +#define HEX0_EDGE_TYPE "NONE" +#define HEX0_FREQ 50000000 +#define HEX0_HAS_IN 0 +#define HEX0_HAS_OUT 1 +#define HEX0_HAS_TRI 0 +#define HEX0_IRQ -1 +#define HEX0_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX0_IRQ_TYPE "NONE" +#define HEX0_NAME "/dev/hex0" +#define HEX0_RESET_VALUE 0 +#define HEX0_SPAN 16 +#define HEX0_TYPE "altera_avalon_pio" + + +/* + * hex1 configuration + * + */ + +#define ALT_MODULE_CLASS_hex1 altera_avalon_pio +#define HEX1_BASE 0x410a0 +#define HEX1_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX1_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX1_CAPTURE 0 +#define HEX1_DATA_WIDTH 7 +#define HEX1_DO_TEST_BENCH_WIRING 0 +#define HEX1_DRIVEN_SIM_VALUE 0 +#define HEX1_EDGE_TYPE "NONE" +#define HEX1_FREQ 50000000 +#define HEX1_HAS_IN 0 +#define HEX1_HAS_OUT 1 +#define HEX1_HAS_TRI 0 +#define HEX1_IRQ -1 +#define HEX1_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX1_IRQ_TYPE "NONE" +#define HEX1_NAME "/dev/hex1" +#define HEX1_RESET_VALUE 0 +#define HEX1_SPAN 16 +#define HEX1_TYPE "altera_avalon_pio" + + +/* + * hex2 configuration + * + */ + +#define ALT_MODULE_CLASS_hex2 altera_avalon_pio +#define HEX2_BASE 0x41090 +#define HEX2_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX2_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX2_CAPTURE 0 +#define HEX2_DATA_WIDTH 7 +#define HEX2_DO_TEST_BENCH_WIRING 0 +#define HEX2_DRIVEN_SIM_VALUE 0 +#define HEX2_EDGE_TYPE "NONE" +#define HEX2_FREQ 50000000 +#define HEX2_HAS_IN 0 +#define HEX2_HAS_OUT 1 +#define HEX2_HAS_TRI 0 +#define HEX2_IRQ -1 +#define HEX2_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX2_IRQ_TYPE "NONE" +#define HEX2_NAME "/dev/hex2" +#define HEX2_RESET_VALUE 0 +#define HEX2_SPAN 16 +#define HEX2_TYPE "altera_avalon_pio" + + +/* + * hex3 configuration + * + */ + +#define ALT_MODULE_CLASS_hex3 altera_avalon_pio +#define HEX3_BASE 0x41080 +#define HEX3_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX3_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX3_CAPTURE 0 +#define HEX3_DATA_WIDTH 7 +#define HEX3_DO_TEST_BENCH_WIRING 0 +#define HEX3_DRIVEN_SIM_VALUE 0 +#define HEX3_EDGE_TYPE "NONE" +#define HEX3_FREQ 50000000 +#define HEX3_HAS_IN 0 +#define HEX3_HAS_OUT 1 +#define HEX3_HAS_TRI 0 +#define HEX3_IRQ -1 +#define HEX3_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX3_IRQ_TYPE "NONE" +#define HEX3_NAME "/dev/hex3" +#define HEX3_RESET_VALUE 0 +#define HEX3_SPAN 16 +#define HEX3_TYPE "altera_avalon_pio" + + +/* + * hex4 configuration + * + */ + +#define ALT_MODULE_CLASS_hex4 altera_avalon_pio +#define HEX4_BASE 0x41070 +#define HEX4_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX4_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX4_CAPTURE 0 +#define HEX4_DATA_WIDTH 7 +#define HEX4_DO_TEST_BENCH_WIRING 0 +#define HEX4_DRIVEN_SIM_VALUE 0 +#define HEX4_EDGE_TYPE "NONE" +#define HEX4_FREQ 50000000 +#define HEX4_HAS_IN 0 +#define HEX4_HAS_OUT 1 +#define HEX4_HAS_TRI 0 +#define HEX4_IRQ -1 +#define HEX4_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX4_IRQ_TYPE "NONE" +#define HEX4_NAME "/dev/hex4" +#define HEX4_RESET_VALUE 0 +#define HEX4_SPAN 16 +#define HEX4_TYPE "altera_avalon_pio" + + +/* + * hex5 configuration + * + */ + +#define ALT_MODULE_CLASS_hex5 altera_avalon_pio +#define HEX5_BASE 0x41060 +#define HEX5_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX5_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX5_CAPTURE 0 +#define HEX5_DATA_WIDTH 7 +#define HEX5_DO_TEST_BENCH_WIRING 0 +#define HEX5_DRIVEN_SIM_VALUE 0 +#define HEX5_EDGE_TYPE "NONE" +#define HEX5_FREQ 50000000 +#define HEX5_HAS_IN 0 +#define HEX5_HAS_OUT 1 +#define HEX5_HAS_TRI 0 +#define HEX5_IRQ -1 +#define HEX5_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX5_IRQ_TYPE "NONE" +#define HEX5_NAME "/dev/hex5" +#define HEX5_RESET_VALUE 0 +#define HEX5_SPAN 16 +#define HEX5_TYPE "altera_avalon_pio" + + +/* + * hex6 configuration + * + */ + +#define ALT_MODULE_CLASS_hex6 altera_avalon_pio +#define HEX6_BASE 0x41050 +#define HEX6_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX6_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX6_CAPTURE 0 +#define HEX6_DATA_WIDTH 7 +#define HEX6_DO_TEST_BENCH_WIRING 0 +#define HEX6_DRIVEN_SIM_VALUE 0 +#define HEX6_EDGE_TYPE "NONE" +#define HEX6_FREQ 50000000 +#define HEX6_HAS_IN 0 +#define HEX6_HAS_OUT 1 +#define HEX6_HAS_TRI 0 +#define HEX6_IRQ -1 +#define HEX6_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX6_IRQ_TYPE "NONE" +#define HEX6_NAME "/dev/hex6" +#define HEX6_RESET_VALUE 0 +#define HEX6_SPAN 16 +#define HEX6_TYPE "altera_avalon_pio" + + +/* + * hex7 configuration + * + */ + +#define ALT_MODULE_CLASS_hex7 altera_avalon_pio +#define HEX7_BASE 0x41040 +#define HEX7_BIT_CLEARING_EDGE_REGISTER 0 +#define HEX7_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define HEX7_CAPTURE 0 +#define HEX7_DATA_WIDTH 7 +#define HEX7_DO_TEST_BENCH_WIRING 0 +#define HEX7_DRIVEN_SIM_VALUE 0 +#define HEX7_EDGE_TYPE "NONE" +#define HEX7_FREQ 50000000 +#define HEX7_HAS_IN 0 +#define HEX7_HAS_OUT 1 +#define HEX7_HAS_TRI 0 +#define HEX7_IRQ -1 +#define HEX7_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define HEX7_IRQ_TYPE "NONE" +#define HEX7_NAME "/dev/hex7" +#define HEX7_RESET_VALUE 0 +#define HEX7_SPAN 16 +#define HEX7_TYPE "altera_avalon_pio" + + +/* + * jtag_uart configuration + * + */ + +#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart +#define JTAG_UART_BASE 0x41100 +#define JTAG_UART_IRQ 5 +#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define JTAG_UART_NAME "/dev/jtag_uart" +#define JTAG_UART_READ_DEPTH 64 +#define JTAG_UART_READ_THRESHOLD 8 +#define JTAG_UART_SPAN 8 +#define JTAG_UART_TYPE "altera_avalon_jtag_uart" +#define JTAG_UART_WRITE_DEPTH 64 +#define JTAG_UART_WRITE_THRESHOLD 8 + + +/* + * lcd_16207_0 configuration + * + */ + +#define ALT_MODULE_CLASS_lcd_16207_0 altera_avalon_lcd_16207 +#define LCD_16207_0_BASE 0x41030 +#define LCD_16207_0_IRQ -1 +#define LCD_16207_0_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LCD_16207_0_NAME "/dev/lcd_16207_0" +#define LCD_16207_0_SPAN 16 +#define LCD_16207_0_TYPE "altera_avalon_lcd_16207" + + +/* + * lcd_blon configuration + * + */ + +#define ALT_MODULE_CLASS_lcd_blon altera_avalon_pio +#define LCD_BLON_BASE 0x41020 +#define LCD_BLON_BIT_CLEARING_EDGE_REGISTER 0 +#define LCD_BLON_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LCD_BLON_CAPTURE 0 +#define LCD_BLON_DATA_WIDTH 1 +#define LCD_BLON_DO_TEST_BENCH_WIRING 0 +#define LCD_BLON_DRIVEN_SIM_VALUE 0 +#define LCD_BLON_EDGE_TYPE "NONE" +#define LCD_BLON_FREQ 50000000 +#define LCD_BLON_HAS_IN 0 +#define LCD_BLON_HAS_OUT 1 +#define LCD_BLON_HAS_TRI 0 +#define LCD_BLON_IRQ -1 +#define LCD_BLON_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LCD_BLON_IRQ_TYPE "NONE" +#define LCD_BLON_NAME "/dev/lcd_blon" +#define LCD_BLON_RESET_VALUE 0 +#define LCD_BLON_SPAN 16 +#define LCD_BLON_TYPE "altera_avalon_pio" + + +/* + * lcd_on configuration + * + */ + +#define ALT_MODULE_CLASS_lcd_on altera_avalon_pio +#define LCD_ON_BASE 0x41010 +#define LCD_ON_BIT_CLEARING_EDGE_REGISTER 0 +#define LCD_ON_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LCD_ON_CAPTURE 0 +#define LCD_ON_DATA_WIDTH 1 +#define LCD_ON_DO_TEST_BENCH_WIRING 0 +#define LCD_ON_DRIVEN_SIM_VALUE 0 +#define LCD_ON_EDGE_TYPE "NONE" +#define LCD_ON_FREQ 50000000 +#define LCD_ON_HAS_IN 0 +#define LCD_ON_HAS_OUT 1 +#define LCD_ON_HAS_TRI 0 +#define LCD_ON_IRQ -1 +#define LCD_ON_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define LCD_ON_IRQ_TYPE "NONE" +#define LCD_ON_NAME "/dev/lcd_on" +#define LCD_ON_RESET_VALUE 0 +#define LCD_ON_SPAN 16 +#define LCD_ON_TYPE "altera_avalon_pio" + + +/* + * onchip_memory configuration + * + */ + +#define ALT_MODULE_CLASS_onchip_memory altera_avalon_onchip_memory2 +#define ONCHIP_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 +#define ONCHIP_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define ONCHIP_MEMORY_BASE 0x0 +#define ONCHIP_MEMORY_CONTENTS_INFO "" +#define ONCHIP_MEMORY_DUAL_PORT 0 +#define ONCHIP_MEMORY_GUI_RAM_BLOCK_TYPE "AUTO" +#define ONCHIP_MEMORY_INIT_CONTENTS_FILE "nios_system_onchip_memory" +#define ONCHIP_MEMORY_INIT_MEM_CONTENT 1 +#define ONCHIP_MEMORY_INSTANCE_ID "NONE" +#define ONCHIP_MEMORY_IRQ -1 +#define ONCHIP_MEMORY_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define ONCHIP_MEMORY_NAME "/dev/onchip_memory" +#define ONCHIP_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0 +#define ONCHIP_MEMORY_RAM_BLOCK_TYPE "AUTO" +#define ONCHIP_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE" +#define ONCHIP_MEMORY_SINGLE_CLOCK_OP 0 +#define ONCHIP_MEMORY_SIZE_MULTIPLE 1 +#define ONCHIP_MEMORY_SIZE_VALUE 204800 +#define ONCHIP_MEMORY_SPAN 204800 +#define ONCHIP_MEMORY_TYPE "altera_avalon_onchip_memory2" +#define ONCHIP_MEMORY_WRITABLE 1 + + +/* + * push_switches configuration + * + */ + +#define ALT_MODULE_CLASS_push_switches altera_avalon_pio +#define PUSH_SWITCHES_BASE 0x410c0 +#define PUSH_SWITCHES_BIT_CLEARING_EDGE_REGISTER 0 +#define PUSH_SWITCHES_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PUSH_SWITCHES_CAPTURE 0 +#define PUSH_SWITCHES_DATA_WIDTH 3 +#define PUSH_SWITCHES_DO_TEST_BENCH_WIRING 0 +#define PUSH_SWITCHES_DRIVEN_SIM_VALUE 0 +#define PUSH_SWITCHES_EDGE_TYPE "NONE" +#define PUSH_SWITCHES_FREQ 50000000 +#define PUSH_SWITCHES_HAS_IN 1 +#define PUSH_SWITCHES_HAS_OUT 0 +#define PUSH_SWITCHES_HAS_TRI 0 +#define PUSH_SWITCHES_IRQ -1 +#define PUSH_SWITCHES_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PUSH_SWITCHES_IRQ_TYPE "NONE" +#define PUSH_SWITCHES_NAME "/dev/push_switches" +#define PUSH_SWITCHES_RESET_VALUE 0 +#define PUSH_SWITCHES_SPAN 16 +#define PUSH_SWITCHES_TYPE "altera_avalon_pio" + + +/* + * switches configuration + * + */ + +#define ALT_MODULE_CLASS_switches altera_avalon_pio +#define SWITCHES_BASE 0x410d0 +#define SWITCHES_BIT_CLEARING_EDGE_REGISTER 0 +#define SWITCHES_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define SWITCHES_CAPTURE 0 +#define SWITCHES_DATA_WIDTH 18 +#define SWITCHES_DO_TEST_BENCH_WIRING 0 +#define SWITCHES_DRIVEN_SIM_VALUE 0 +#define SWITCHES_EDGE_TYPE "NONE" +#define SWITCHES_FREQ 50000000 +#define SWITCHES_HAS_IN 1 +#define SWITCHES_HAS_OUT 0 +#define SWITCHES_HAS_TRI 0 +#define SWITCHES_IRQ -1 +#define SWITCHES_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SWITCHES_IRQ_TYPE "NONE" +#define SWITCHES_NAME "/dev/switches" +#define SWITCHES_RESET_VALUE 0 +#define SWITCHES_SPAN 16 +#define SWITCHES_TYPE "altera_avalon_pio" + +#endif /* __SYSTEM_H_ */ diff --git a/software/qsys_tutorial_lcd4/hello_world_small.c b/software/qsys_tutorial_lcd4/hello_world_small.c index 373fff9..5d06d9b 100644 --- a/software/qsys_tutorial_lcd4/hello_world_small.c +++ b/software/qsys_tutorial_lcd4/hello_world_small.c @@ -1,214 +1,214 @@ -#include "sys/alt_stdio.h" -#include -#include "system.h" -#include "hex_out.h" -#include "lcd_out.h" -#include "sys_register.h" -#include "sys_memory.h" -#include "input_int.h" -#include "sys_debug.h" -#include "sys_prog.h" - -#define ledrs (volatile int *) LEDRS_BASE - -static void init() { - // lcd - lcd_init(); - lcd_print("Starting now..."); - - registers_init(); - memory_init(); - // hex - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); - print_block("he", 2, HEX6_7); - print_block("lo", 2, HEX4_5); - print_block("you1", 4, HEX0_3); - delay10ms(200); - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); - - lcd_caret_reset2(); - lcd_print("Ok!"); -} - -char stack[5]; - -void store_value(){ - unsigned int memi = global_registers[Ssw_memi]; - memory_store(memi, Ssw_data); - - { // �f�o�b�N�\�� - char buf[5]; - sprintf(buf, "%02x", (unsigned char)memi); - print_block(buf, 2, HEX6_7); - print_block("--", 2, HEX4_5); - sprintf(buf, "%04d", global_registers[Ssw_data]); - print_block(buf, 4, HEX0_3); - - display_mem((unsigned char)memi, global_registers[Ssw_data]); - } -} -void store_inst(){ - char inst; - char mem_index; - char reg_index; - unsigned int stored_pc; - struct InstRec inst_rec; - - // �K�v�ȏ��̎擾 - inst = global_registers[Ssw_inst]; - mem_index = global_registers[Ssw_memi]; - reg_index = global_registers[Ssw_regi]; - inst_rec.inst = (unsigned int)inst; - inst_rec.memi = (unsigned int)mem_index; - inst_rec.regi = (unsigned int)reg_index; - - // �X�g�A���� - stored_pc = (unsigned char)global_registers[Spc]; - inst_memory_store((unsigned int)global_registers[Spc], inst_rec); - inc_pc(); - { // �f�o�b�N�\�� - char buf[5]; - sprintf(buf, "%04d", inst_rec.inst); - print_block(buf, 4, HEX0_3); - sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); - print_block(buf, 2, HEX4_5); - - display_inst(inst_rec, stored_pc); - } -} - -void print_change_memory(unsigned int current_memory) { - char buf[17]; - sprintf(buf, "Current page:%2d", current_memory); - lcd_caret_reset(); - lcd_print("Change program"); - lcd_caret_reset2(); - lcd_print(buf); - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); -} - -static void reset_mem_cancel() { - lcd_caret_reset(); - lcd_print("rewrite all 0?"); - lcd_caret_reset2(); - lcd_print("push again -> NG"); -} -static char reset_mem(char confirmed) { - if (confirmed == 0) { - lcd_caret_reset(); - lcd_print("rewrite all 0?"); - lcd_caret_reset2(); - lcd_print("push again"); - // �m�F�v�� - return 1; - } else { - int i; - for (i = 0; i < MEM_SIZE; i++){ - memory_store(i,Szero); - } - lcd_caret_reset(); - lcd_print("rewrite all 0?"); - lcd_caret_reset2(); - lcd_print("push again -> OK"); - - // PC���Z�b�g���� - return 0; - } -} -static void reset_pc_cancel() { - lcd_caret_reset(); - lcd_print("reset pc?"); - lcd_caret_reset2(); - lcd_print("push again -> NG"); -} -static char reset_pc(char confirmed) { - if (confirmed == 0) { - lcd_caret_reset(); - lcd_print("reset pc?"); - lcd_caret_reset2(); - lcd_print("push again"); - // �m�F�v�� - return 1; - } else { - global_registers[Spc]=0; - - lcd_caret_reset(); - lcd_print("reset pc?"); - lcd_caret_reset2(); - lcd_print("push again -> OK"); - - // PC���Z�b�g���� - return 0; - } -} - - -int main() -{ - init(); - - enum RunMode fRun = RUN_STOP; - char reset_pc_confirmed = 0; - char reset_mem_confirmed = 0; - - while(1) { - // interrupt - in_int(); - - // event - // CANCEL - if (global_registers[Ssw_rw] == 0 - || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_VALSTR))) { - if (reset_mem_confirmed == 1) { - reset_mem_confirmed = 0; //�m�F�L�����Z�� - reset_mem_cancel(); - } - } - if (global_registers[Ssw_rw] == 0 - || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_INSSTR))) { - if (reset_pc_confirmed == 1) { - reset_pc_confirmed = 0; //�m�F�L�����Z�� - reset_pc_cancel(); - } - } - // CONFIRM - if (PUSH_EVENT & PUSH_VALSTR) { - // �l�̃X�g�A - if (global_registers[Ssw_rw] == 1) { - //�폜 - char res = reset_mem(reset_mem_confirmed);//���m�F�̏��F - if (1 == res) reset_mem_confirmed = 1; //���m�F - if (0 == res) reset_mem_confirmed = 0; //���Z�b�g�̊m�F - } else { - store_value(); - } - } - if (PUSH_EVENT & PUSH_INSSTR) { - // ���߂̃X�g�A - if (global_registers[Ssw_rw] == 1) { - //PC�̃��Z�b�g - char res = reset_pc(reset_pc_confirmed);//���m�F�̏��F - if (1 == res) reset_pc_confirmed = 1; //���m�F - if (0 == res) reset_pc_confirmed = 0; //���Z�b�g�̊m�F - } else { - store_inst(); - } - } - // RUN - if (PUSH_EVENT & PUSH_RUN) { - if (global_current_memory != (unsigned int)global_registers[Ssw_psel]) { - global_current_memory = (unsigned int)global_registers[Ssw_psel]; - print_change_memory(global_current_memory); - } - else { - // �v���O�����������ݒ� - fRun = RUN_INIT; - } - } - if (fRun != RUN_STOP) { - // �v���O�������s���荞�� & ���s���[�h�X�V - fRun = run_proc(fRun); - } - } - return 0; -} +#include "sys/alt_stdio.h" +#include +#include "system.h" +#include "hex_out.h" +#include "lcd_out.h" +#include "sys_register.h" +#include "sys_memory.h" +#include "input_int.h" +#include "sys_debug.h" +#include "sys_prog.h" + +#define ledrs (volatile int *) LEDRS_BASE + +static void init() { + // lcd + lcd_init(); + lcd_print("Starting now..."); + + registers_init(); + memory_init(); + // hex + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + print_block("he", 2, HEX6_7); + print_block("lo", 2, HEX4_5); + print_block("you1", 4, HEX0_3); + delay10ms(200); + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + + lcd_caret_reset2(); + lcd_print("Ok!"); +} + +char stack[5]; + +void store_value(){ + unsigned int memi = global_registers[Ssw_memi]; + memory_store(memi, Ssw_data); + + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "%02x", (unsigned char)memi); + print_block(buf, 2, HEX6_7); + print_block("--", 2, HEX4_5); + sprintf(buf, "%04d", global_registers[Ssw_data]); + print_block(buf, 4, HEX0_3); + + display_mem((unsigned char)memi, global_registers[Ssw_data]); + } +} +void store_inst(){ + char inst; + char mem_index; + char reg_index; + unsigned int stored_pc; + struct InstRec inst_rec; + + // �K�v�ȏ��̎擾 + inst = global_registers[Ssw_inst]; + mem_index = global_registers[Ssw_memi]; + reg_index = global_registers[Ssw_regi]; + inst_rec.inst = (unsigned int)inst; + inst_rec.memi = (unsigned int)mem_index; + inst_rec.regi = (unsigned int)reg_index; + + // �X�g�A���� + stored_pc = get_pc(); + inst_memory_store(get_pc(), inst_rec); + inc_pc(); + { // �f�o�b�N�\�� + char buf[5]; + sprintf(buf, "%04d", inst_rec.inst); + print_block(buf, 4, HEX0_3); + sprintf(buf, "%02x", get_pc()); + print_block(buf, 2, HEX4_5); + + display_inst(inst_rec, stored_pc); + } +} + +void print_change_memory(unsigned int current_memory) { + char buf[17]; + sprintf(buf, "Current page:%2d", current_memory); + lcd_caret_reset(); + lcd_print("Change program"); + lcd_caret_reset2(); + lcd_print(buf); + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); +} + +static void reset_mem_cancel() { + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again -> NG"); +} +static char reset_mem(char confirmed) { + if (confirmed == 0) { + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again"); + // �m�F�v�� + return 1; + } else { + int i; + for (i = 0; i < MEM_SIZE; i++){ + memory_store(i,Szero); + } + lcd_caret_reset(); + lcd_print("rewrite all 0?"); + lcd_caret_reset2(); + lcd_print("push again -> OK"); + + // PC���Z�b�g���� + return 0; + } +} +static void reset_pc_cancel() { + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again -> NG"); +} +static char reset_pc(char confirmed) { + if (confirmed == 0) { + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again"); + // �m�F�v�� + return 1; + } else { + set_pc(0); + + lcd_caret_reset(); + lcd_print("reset pc?"); + lcd_caret_reset2(); + lcd_print("push again -> OK"); + + // PC���Z�b�g���� + return 0; + } +} + + +int main() +{ + init(); + + enum RunMode fRun = RUN_STOP; + char reset_pc_confirmed = 0; + char reset_mem_confirmed = 0; + + while(1) { + // interrupt + in_int(); + + // event + // CANCEL + if (global_registers[Ssw_rw] == 0 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_VALSTR))) { + if (reset_mem_confirmed == 1) { + reset_mem_confirmed = 0; //�m�F�L�����Z�� + reset_mem_cancel(); + } + } + if (global_registers[Ssw_rw] == 0 + || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_INSSTR))) { + if (reset_pc_confirmed == 1) { + reset_pc_confirmed = 0; //�m�F�L�����Z�� + reset_pc_cancel(); + } + } + // CONFIRM + if (PUSH_EVENT & PUSH_VALSTR) { + // �l�̃X�g�A + if (global_registers[Ssw_rw] == 1) { + //�폜 + char res = reset_mem(reset_mem_confirmed);//���m�F�̏��F + if (1 == res) reset_mem_confirmed = 1; //���m�F + if (0 == res) reset_mem_confirmed = 0; //���Z�b�g�̊m�F + } else { + store_value(); + } + } + if (PUSH_EVENT & PUSH_INSSTR) { + // ���߂̃X�g�A + if (global_registers[Ssw_rw] == 1) { + //PC�̃��Z�b�g + char res = reset_pc(reset_pc_confirmed);//���m�F�̏��F + if (1 == res) reset_pc_confirmed = 1; //���m�F + if (0 == res) reset_pc_confirmed = 0; //���Z�b�g�̊m�F + } else { + store_inst(); + } + } + // RUN + if (PUSH_EVENT & PUSH_RUN) { + if (global_current_memory != (unsigned int)global_registers[Ssw_psel]) { + global_current_memory = (unsigned int)global_registers[Ssw_psel]; + print_change_memory(global_current_memory); + } + else { + // �v���O�����������ݒ� + fRun = RUN_INIT; + } + } + if (fRun != RUN_STOP) { + // �v���O�������s���荞�� & ���s���[�h�X�V + fRun = run_proc(fRun); + } + } + return 0; +} diff --git a/software/qsys_tutorial_lcd4/inst_decoder.c b/software/qsys_tutorial_lcd4/inst_decoder.c index d4b34fa..3e6e8a9 100644 --- a/software/qsys_tutorial_lcd4/inst_decoder.c +++ b/software/qsys_tutorial_lcd4/inst_decoder.c @@ -1,114 +1,120 @@ -/* - * inst_decoder.c - * - * Created on: 2016/11/25 - * Author: takayun - */ - -#include "inst_decoder.h" -#include "sys_memory.h" -#include "sys_register.h" -#include "hex_out.h" -#include "sys_prog.h" -#include -#include - -struct InstRec inst_fetch(){ - struct InstRec rec = inst_memory_load((unsigned int)global_registers[Spc]); - inc_pc(); - return rec; -} - -void inst_decode(struct InstRec inst_rec){ - switch(inst_rec.inst) { - case INST_END: - break; - case INST_JUMP: - inst_jump(inst_rec.regi, inst_rec.memi); - break; - case INST_OUTPUT: - inst_output(inst_rec.regi, inst_rec.memi); - break; - case INST_LOAD: - inst_load(inst_rec.regi, inst_rec.memi); - break; - case INST_STORE: - inst_store(inst_rec.regi, inst_rec.memi); - break; - case INST_DELAY: - inst_delay(inst_rec.regi, inst_rec.memi); - break; - case INST_ADD: - inst_add(inst_rec.regi, inst_rec.memi); - break; - case INST_COMP: - inst_comp(inst_rec.regi, inst_rec.memi); - break; - case INST_JEQ: - inst_jeq(inst_rec.regi, inst_rec.memi); - break; - case INST_JNE: - inst_jne(inst_rec.regi, inst_rec.memi); - break; - case INST_JIEQ: - inst_jieq(inst_rec.regi, inst_rec.memi); - break; - case INST_JINE: - inst_jine(inst_rec.regi, inst_rec.memi); - break; - } -} - -void inst_jump(enum Register reg, unsigned char memory_index){ - set_pc(global_registers[reg]+memory_index); -} -void inst_output(enum Register reg, unsigned char memory_index){ - //�������̒l��7�Z�O�ɕ\�� - char buf[5]; - memory_load(memory_index, Sseg); - sprintf(buf, "%04d", global_registers[Sseg]); - print_block(buf, 4, HEX0_3); -} -void inst_load(enum Register reg, unsigned char memory_index){ - memory_load(memory_index, reg); -} -void inst_store(enum Register reg, unsigned char memory_index){ - memory_store(memory_index, reg); -} -void inst_delay(enum Register reg, unsigned char memory_index){ - //���W�X�^�̒l*10ms�҂� - usleep((int)global_registers[reg]*10000); -} -void inst_add(enum Register reg, unsigned char memory_index){ - global_registers[Sacc]+=global_registers[reg]; -} -void inst_comp(enum Register reg, unsigned char memory_index){ - if(global_registers[Sacc]==global_registers[reg]){ - global_registers[Sflg]=0; - } else if(global_registers[Sacc] > global_registers[reg]){ - global_registers[Sflg]=-1; - }else{ - global_registers[Sflg]=1; - } -} -void inst_jeq(enum Register reg, unsigned char memory_index){ - if(global_registers[Sflg]==global_registers[reg]){ - inc_pc(); - } -} -void inst_jne(enum Register reg, unsigned char memory_index){ - if(global_registers[Sflg]!=global_registers[reg]){ - inc_pc(); - } -} -void inst_jieq(char im, unsigned char memory_index){ - if(global_registers[Sflg]==im){ - inc_pc(); - } -} -void inst_jine(char im, unsigned char memory_index){ - if(global_registers[Sflg]!=im){ - inc_pc(); - } -} - +/* + * inst_decoder.c + * + * Created on: 2016/11/25 + * Author: takayun + */ + +#include "inst_decoder.h" +#include "sys_memory.h" +#include "sys_register.h" +#include "hex_out.h" +#include "sys_prog.h" +#include +#include + +struct InstRec inst_fetch(){ + struct InstRec rec = inst_memory_load((unsigned int)global_registers[Spc]); + inc_pc(); + return rec; +} + +void inst_decode(struct InstRec inst_rec){ + switch(inst_rec.inst) { + case INST_END: + break; + case INST_JUMP: + inst_jump(inst_rec.regi, inst_rec.memi); + break; + case INST_OUTPUT: + inst_output(inst_rec.regi, inst_rec.memi); + break; + case INST_LOAD: + inst_load(inst_rec.regi, inst_rec.memi); + break; + case INST_STORE: + inst_store(inst_rec.regi, inst_rec.memi); + break; + case INST_DELAY: + inst_delay(inst_rec.regi, inst_rec.memi); + break; + case INST_ADD: + inst_add(inst_rec.regi, inst_rec.memi); + break; + case INST_SUB: + inst_sub(inst_rec.regi, inst_rec.memi); + break; + case INST_COMP: + inst_comp(inst_rec.regi, inst_rec.memi); + break; + case INST_JEQ: + inst_jeq(inst_rec.regi, inst_rec.memi); + break; + case INST_JNE: + inst_jne(inst_rec.regi, inst_rec.memi); + break; + case INST_JIEQ: + inst_jieq(inst_rec.regi, inst_rec.memi); + break; + case INST_JINE: + inst_jine(inst_rec.regi, inst_rec.memi); + break; + } +} + +void inst_jump(enum Register reg, unsigned char memory_index){ + set_pc(global_registers[reg]+memory_index); +} +void inst_output(enum Register reg, unsigned char memory_index){ + //�������̒l��7�Z�O�ɕ\�� + char buf[5]; + memory_load(memory_index, Sseg); + sprintf(buf, "%04d", global_registers[Sseg]); + print_block(buf, 4, HEX0_3); +} +void inst_load(enum Register reg, unsigned char memory_index){ + memory_load(memory_index, reg); +} +void inst_store(enum Register reg, unsigned char memory_index){ + memory_store(memory_index, reg); +} +void inst_delay(enum Register reg, unsigned char memory_index){ + //���W�X�^�̒l*10ms�҂� + usleep((int)global_registers[reg]*10000); +} +void inst_add(enum Register reg, unsigned char memory_index){ + global_registers[Sacc]+=global_registers[reg]; +} +void inst_sub(enum Register reg, unsigned char memory_index){ + global_registers[Sacc]-=global_registers[reg]; +} +void inst_comp(enum Register reg, unsigned char memory_index){ + if(global_registers[Sacc]==global_registers[reg]){ + global_registers[Sflg]=0; + } else if(global_registers[Sacc] > global_registers[reg]){ + global_registers[Sflg]=-1; + }else{ + global_registers[Sflg]=1; + } +} +void inst_jeq(enum Register reg, unsigned char memory_index){ + if(global_registers[Sflg]==global_registers[reg]){ + inc_pc(); + } +} +void inst_jne(enum Register reg, unsigned char memory_index){ + if(global_registers[Sflg]!=global_registers[reg]){ + inc_pc(); + } +} +void inst_jieq(char im, unsigned char memory_index){ + if(global_registers[Sflg]==im){ + inc_pc(); + } +} +void inst_jine(char im, unsigned char memory_index){ + if(global_registers[Sflg]!=im){ + inc_pc(); + } +} + diff --git a/software/qsys_tutorial_lcd4/inst_decoder.h b/software/qsys_tutorial_lcd4/inst_decoder.h index 9860750..036e179 100644 --- a/software/qsys_tutorial_lcd4/inst_decoder.h +++ b/software/qsys_tutorial_lcd4/inst_decoder.h @@ -1,49 +1,51 @@ -/* - * inst_decoder.h - * - * Created on: 2016/11/25 - * Author: takayun - */ - -#ifndef INST_DECODER_H_ -#define INST_DECODER_H_ - -#include "sys_register.h" - -#define INST_END 0x0 -#define INST_JUMP 0x1 -#define INST_OUTPUT 0x2 -#define INST_LOAD 0x3 -#define INST_STORE 0x4 -#define INST_DELAY 0x5 -#define INST_ADD 0x6 -#define INST_COMP 0x7 -#define INST_JEQ 0x8 -#define INST_JNE 0x9 -#define INST_JIEQ 0xA -#define INST_JINE 0xB - -struct InstRec { - unsigned int inst : 4; - unsigned int memi : 4; - unsigned int regi : 4; -}; - -struct InstRec inst_fetch(); - -void inst_decode(struct InstRec inst_rec); - -void inst_jump(enum Register reg, unsigned char memory_index); -void inst_output(enum Register reg, unsigned char memory_index); -void inst_load(enum Register reg, unsigned char memory_index); -void inst_store(enum Register reg, unsigned char memory_index); -void inst_delay(enum Register reg, unsigned char memory_index); -void inst_add(enum Register reg, unsigned char memory_index); -void inst_comp(enum Register reg, unsigned char memory_index); -void inst_jeq(enum Register reg, unsigned char memory_index); -void inst_jne(enum Register reg, unsigned char memory_index); -void inst_jieq(char im, unsigned char memory_index); -void inst_jine(char im, unsigned char memory_index); - - -#endif /* INST_DECODER_H_ */ +/* + * inst_decoder.h + * + * Created on: 2016/11/25 + * Author: takayun + */ + +#ifndef INST_DECODER_H_ +#define INST_DECODER_H_ + +#include "sys_register.h" + +#define INST_END 0x0 +#define INST_JUMP 0x1 +#define INST_OUTPUT 0x2 +#define INST_LOAD 0x3 +#define INST_STORE 0x4 +#define INST_DELAY 0x5 +#define INST_ADD 0x6 +#define INST_COMP 0x7 +#define INST_JEQ 0x8 +#define INST_JNE 0x9 +#define INST_JIEQ 0xA +#define INST_JINE 0xB +#define INST_SUB 0xC + +struct InstRec { + unsigned int inst : 4; + unsigned int memi : 4; + unsigned int regi : 4; +}; + +struct InstRec inst_fetch(); + +void inst_decode(struct InstRec inst_rec); + +void inst_jump(enum Register reg, unsigned char memory_index); +void inst_output(enum Register reg, unsigned char memory_index); +void inst_load(enum Register reg, unsigned char memory_index); +void inst_store(enum Register reg, unsigned char memory_index); +void inst_delay(enum Register reg, unsigned char memory_index); +void inst_add(enum Register reg, unsigned char memory_index); +void inst_sub(enum Register reg, unsigned char memory_index); +void inst_comp(enum Register reg, unsigned char memory_index); +void inst_jeq(enum Register reg, unsigned char memory_index); +void inst_jne(enum Register reg, unsigned char memory_index); +void inst_jieq(char im, unsigned char memory_index); +void inst_jine(char im, unsigned char memory_index); + + +#endif /* INST_DECODER_H_ */ diff --git a/software/qsys_tutorial_lcd4/obj/default/LCD.d b/software/qsys_tutorial_lcd4/obj/default/LCD.d deleted file mode 100644 index 2634512..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/LCD.d +++ /dev/null @@ -1,14 +0,0 @@ -obj/default/LCD.o: LCD.c ../qsys_tutorial_lcd4_bsp//HAL/inc/io.h \ - ../qsys_tutorial_lcd4_bsp//HAL/inc/alt_types.h \ - ../qsys_tutorial_lcd4_bsp/system.h ../qsys_tutorial_lcd4_bsp/linker.h \ - LCD.h - -../qsys_tutorial_lcd4_bsp//HAL/inc/io.h: - -../qsys_tutorial_lcd4_bsp//HAL/inc/alt_types.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: - -LCD.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/LCD.o b/software/qsys_tutorial_lcd4/obj/default/LCD.o deleted file mode 100644 index 0ef0cec..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/LCD.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/hello_world_small.d b/software/qsys_tutorial_lcd4/obj/default/hello_world_small.d deleted file mode 100644 index 1c86f1a..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/hello_world_small.d +++ /dev/null @@ -1,27 +0,0 @@ -obj/default/hello_world_small.o: hello_world_small.c \ - ../qsys_tutorial_lcd4_bsp//HAL/inc/sys/alt_stdio.h \ - ../qsys_tutorial_lcd4_bsp/system.h ../qsys_tutorial_lcd4_bsp/linker.h \ - hex_out.h lcd_out.h sys_register.h sys_memory.h inst_decoder.h \ - input_int.h sys_debug.h sys_prog.h - -../qsys_tutorial_lcd4_bsp//HAL/inc/sys/alt_stdio.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: - -hex_out.h: - -lcd_out.h: - -sys_register.h: - -sys_memory.h: - -inst_decoder.h: - -input_int.h: - -sys_debug.h: - -sys_prog.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/hello_world_small.o b/software/qsys_tutorial_lcd4/obj/default/hello_world_small.o deleted file mode 100644 index a6ae350..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/hello_world_small.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/hex_encoder.d b/software/qsys_tutorial_lcd4/obj/default/hex_encoder.d deleted file mode 100644 index 600af0b..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/hex_encoder.d +++ /dev/null @@ -1,8 +0,0 @@ -obj/default/hex_encoder.o: hex_encoder.c hex_encoder.h \ - ../qsys_tutorial_lcd4_bsp/system.h ../qsys_tutorial_lcd4_bsp/linker.h - -hex_encoder.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/hex_encoder.o b/software/qsys_tutorial_lcd4/obj/default/hex_encoder.o deleted file mode 100644 index e6f5f32..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/hex_encoder.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/hex_out.d b/software/qsys_tutorial_lcd4/obj/default/hex_out.d deleted file mode 100644 index fb61bcb..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/hex_out.d +++ /dev/null @@ -1,13 +0,0 @@ -obj/default/hex_out.o: hex_out.c hex_out.h hex_encoder.h \ - ../qsys_tutorial_lcd4_bsp/system.h ../qsys_tutorial_lcd4_bsp/linker.h \ - sys_except.h - -hex_out.h: - -hex_encoder.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: - -sys_except.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/hex_out.o b/software/qsys_tutorial_lcd4/obj/default/hex_out.o deleted file mode 100644 index 2279113..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/hex_out.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/input_int.d b/software/qsys_tutorial_lcd4/obj/default/input_int.d deleted file mode 100644 index 5f6f066..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/input_int.d +++ /dev/null @@ -1,11 +0,0 @@ -obj/default/input_int.o: input_int.c input_int.h \ - ../qsys_tutorial_lcd4_bsp/system.h ../qsys_tutorial_lcd4_bsp/linker.h \ - sys_register.h - -input_int.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: - -sys_register.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/input_int.o b/software/qsys_tutorial_lcd4/obj/default/input_int.o deleted file mode 100644 index 2ccc4dc..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/input_int.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/inst_decoder.d b/software/qsys_tutorial_lcd4/obj/default/inst_decoder.d deleted file mode 100644 index 66c5270..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/inst_decoder.d +++ /dev/null @@ -1,12 +0,0 @@ -obj/default/inst_decoder.o: inst_decoder.c inst_decoder.h sys_register.h \ - sys_memory.h hex_out.h sys_prog.h - -inst_decoder.h: - -sys_register.h: - -sys_memory.h: - -hex_out.h: - -sys_prog.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/inst_decoder.o b/software/qsys_tutorial_lcd4/obj/default/inst_decoder.o deleted file mode 100644 index cf85fb6..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/inst_decoder.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/lcd_out.d b/software/qsys_tutorial_lcd4/obj/default/lcd_out.d deleted file mode 100644 index f1e03d1..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/lcd_out.d +++ /dev/null @@ -1,11 +0,0 @@ -obj/default/lcd_out.o: lcd_out.c lcd_out.h \ - ../qsys_tutorial_lcd4_bsp/system.h ../qsys_tutorial_lcd4_bsp/linker.h \ - LCD.h - -lcd_out.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: - -LCD.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/lcd_out.o b/software/qsys_tutorial_lcd4/obj/default/lcd_out.o deleted file mode 100644 index b2e5dd5..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/lcd_out.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_debug.d b/software/qsys_tutorial_lcd4/obj/default/sys_debug.d deleted file mode 100644 index 4d04c60..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_debug.d +++ /dev/null @@ -1,15 +0,0 @@ -obj/default/sys_debug.o: sys_debug.c sys_debug.h inst_decoder.h \ - sys_register.h lcd_out.h ../qsys_tutorial_lcd4_bsp/system.h \ - ../qsys_tutorial_lcd4_bsp/linker.h - -sys_debug.h: - -inst_decoder.h: - -sys_register.h: - -lcd_out.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_debug.o b/software/qsys_tutorial_lcd4/obj/default/sys_debug.o deleted file mode 100644 index a3a94af..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_debug.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_except.d b/software/qsys_tutorial_lcd4/obj/default/sys_except.d deleted file mode 100644 index 81b0c01..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_except.d +++ /dev/null @@ -1,8 +0,0 @@ -obj/default/sys_except.o: sys_except.c ../qsys_tutorial_lcd4_bsp/system.h \ - ../qsys_tutorial_lcd4_bsp/linker.h hex_out.h - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: - -hex_out.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_except.o b/software/qsys_tutorial_lcd4/obj/default/sys_except.o deleted file mode 100644 index 904dcf7..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_except.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_memory.d b/software/qsys_tutorial_lcd4/obj/default/sys_memory.d deleted file mode 100644 index d04c3db..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_memory.d +++ /dev/null @@ -1,15 +0,0 @@ -obj/default/sys_memory.o: sys_memory.c ../qsys_tutorial_lcd4_bsp/system.h \ - ../qsys_tutorial_lcd4_bsp/linker.h sys_memory.h sys_register.h \ - inst_decoder.h sys_except.h - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: - -sys_memory.h: - -sys_register.h: - -inst_decoder.h: - -sys_except.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_memory.o b/software/qsys_tutorial_lcd4/obj/default/sys_memory.o deleted file mode 100644 index 0f1e3a7..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_memory.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_prog.d b/software/qsys_tutorial_lcd4/obj/default/sys_prog.d deleted file mode 100644 index fa88e64..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_prog.d +++ /dev/null @@ -1,21 +0,0 @@ -obj/default/sys_prog.o: sys_prog.c sys_prog.h sys_debug.h inst_decoder.h \ - sys_register.h sys_memory.h hex_out.h lcd_out.h \ - ../qsys_tutorial_lcd4_bsp/system.h ../qsys_tutorial_lcd4_bsp/linker.h - -sys_prog.h: - -sys_debug.h: - -inst_decoder.h: - -sys_register.h: - -sys_memory.h: - -hex_out.h: - -lcd_out.h: - -../qsys_tutorial_lcd4_bsp/system.h: - -../qsys_tutorial_lcd4_bsp/linker.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_prog.o b/software/qsys_tutorial_lcd4/obj/default/sys_prog.o deleted file mode 100644 index faf9a82..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_prog.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_register.d b/software/qsys_tutorial_lcd4/obj/default/sys_register.d deleted file mode 100644 index ec29589..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_register.d +++ /dev/null @@ -1,3 +0,0 @@ -obj/default/sys_register.o: sys_register.c sys_register.h - -sys_register.h: diff --git a/software/qsys_tutorial_lcd4/obj/default/sys_register.o b/software/qsys_tutorial_lcd4/obj/default/sys_register.o deleted file mode 100644 index 51e9247..0000000 --- a/software/qsys_tutorial_lcd4/obj/default/sys_register.o +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.elf b/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.elf deleted file mode 100644 index b226624..0000000 --- a/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.elf +++ /dev/null Binary files differ diff --git a/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.map b/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.map deleted file mode 100644 index 0e3cec0..0000000 --- a/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.map +++ /dev/null @@ -1,2508 +0,0 @@ -Archive member included because of file (symbol) - -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-divmod.o) - obj/default/hex_out.o (__divsi3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-mul.o) - obj/default/inst_decoder.o (__mulsi3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-ctype_.o) - obj/default/hex_encoder.o (__ctype_ptr) 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-c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-makebuf.o) (_isatty_r) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_lseek_r) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-stdio.o) (_read_r) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (__udivdi3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_umoddi3.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (__umoddi3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__subdf3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__muldf3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_div_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__divdf3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_eq_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (__eqdf2) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_ne_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (__nedf2) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_gt_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__gtdf2) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_ge_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__gedf2) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_lt_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) (__ltdf2) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_si_to_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__floatsidf) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_df_to_si.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__fixdfsi) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_thenan_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__thenan_df) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) (__floatunsidf) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) (__muldi3) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clz.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) (__clz_tab) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_si_to_df.o) (__clzsi2) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__pack_d) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_unpack_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) (__unpack_d) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_fpcmp_parts_df.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_eq_df.o) (__fpcmp_parts_d) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_close.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-closer.o) (close) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_dev.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_close.o) (alt_fd_list) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_errno.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_close.o) (alt_errno) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_fstat.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fstatr.o) (fstat) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_isatty.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-isattyr.o) (isatty) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_load.o) - ../qsys_tutorial_lcd4_bsp//obj/HAL/src/crt0.o (alt_load) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_lseek.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-lseekr.o) (lseek) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_main.o) - ../qsys_tutorial_lcd4_bsp//obj/HAL/src/crt0.o (alt_main) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_malloc_lock.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o) (__malloc_lock) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_read.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-readr.o) (read) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_release_fd.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_close.o) (alt_release_fd) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sbrk.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sbrkr.o) (sbrk) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_usleep.o) - obj/default/LCD.o (usleep) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_write.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-writer.o) (write) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sys_init.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_main.o) (alt_irq_init) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_lcd_16207.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_lcd_16207_init) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_avalon_lcd_16207_write_fd) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_alarm_start.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_busy_sleep.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_usleep.o) (alt_busy_sleep) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_load.o) (alt_dcache_flush_all) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sys_init.o) (alt_dev_llist_insert) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_do_ctors.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_main.o) (_do_ctors) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_do_dtors.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_main.o) (_do_dtors) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_icache_flush_all.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_load.o) (alt_icache_flush_all) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (alt_ic_isr_register) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic_isr_register.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic.o) (alt_iic_isr_register) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_io_redirect.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_main.o) (alt_io_redirect) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_entry) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_handler.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic_isr_register.o) (alt_irq_handler) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_vars.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic.o) (alt_irq_active) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_open.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_io_redirect.o) (open) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_tick.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_sys_init.o) (altera_nios2_qsys_irq_init) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) (alt_exception) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_find_dev.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_open.o) (alt_find_dev) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_find_file.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_open.o) (alt_find_file) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_get_fd.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_open.o) (alt_get_fd) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_main.o) (atexit) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_main.o) (exit) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) - ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_find_dev.o) (memcmp) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) (__register_exitproc) -c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (__call_exitprocs) -../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exit.o) - c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) (_exit) - -Allocating common symbols -Common symbol size file - -alt_irq 0x100 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_handler.o) -errno 0x4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-int_errno.o) -stack 0x5 obj/default/hello_world_small.o -global_registers 0xf obj/default/sys_register.o -_atexit0 0x190 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) - -Memory Configuration - -Name Origin Length Attributes -reset 0x00000000 0x00000020 -onchip_memory 0x00000020 0x00031fe0 -*default* 0x00000000 0xffffffff - -Linker script and memory map - -LOAD ../qsys_tutorial_lcd4_bsp//obj/HAL/src/crt0.o -LOAD obj/default/LCD.o -LOAD obj/default/hello_world_small.o -LOAD obj/default/hex_encoder.o -LOAD obj/default/hex_out.o -LOAD obj/default/input_int.o -LOAD obj/default/inst_decoder.o -LOAD obj/default/lcd_out.o -LOAD obj/default/sys_debug.o -LOAD obj/default/sys_except.o -LOAD obj/default/sys_memory.o -LOAD obj/default/sys_prog.o -LOAD obj/default/sys_register.o -LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libstdc++.a -LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libm.a -LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a -START GROUP -LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a -LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a -LOAD ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a -END GROUP -LOAD c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a - 0x00000000 __alt_mem_onchip_memory = 0x0 - -.entry 0x00000000 0x20 - *(.entry) - .entry 0x00000000 0x20 ../qsys_tutorial_lcd4_bsp//obj/HAL/src/crt0.o - 0x00000000 __reset - -.exceptions 0x00000020 0x194 - 0x00000020 PROVIDE (__ram_exceptions_start, ABSOLUTE (.)) - 0x00000020 . = ALIGN (0x20) - *(.irq) - *(.exceptions.entry.label) - .exceptions.entry.label - 0x00000020 0x0 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - 0x00000020 alt_irq_entry - .exceptions.entry.label - 0x00000020 0x0 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - 0x00000020 alt_exception - *(.exceptions.entry.user) - *(.exceptions.entry) - .exceptions.entry - 0x00000020 0x54 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - *(.exceptions.irqtest.user) - *(.exceptions.irqtest) - .exceptions.irqtest - 0x00000074 0x10 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - *(.exceptions.irqhandler.user) - *(.exceptions.irqhandler) - .exceptions.irqhandler - 0x00000084 0x4 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - *(.exceptions.irqreturn.user) - *(.exceptions.irqreturn) - .exceptions.irqreturn - 0x00000088 0x4 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - *(.exceptions.notirq.label) - .exceptions.notirq.label - 0x0000008c 0x0 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - *(.exceptions.notirq.user) - *(.exceptions.notirq) - .exceptions.notirq - 0x0000008c 0x8 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - *(.exceptions.soft.user) - *(.exceptions.soft) - *(.exceptions.unknown.user) - *(.exceptions.unknown) - .exceptions.unknown - 0x00000094 0x4 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - *(.exceptions.exit.label) - .exceptions.exit.label - 0x00000098 0x0 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - .exceptions.exit.label - 0x00000098 0x0 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - *(.exceptions.exit.user) - *(.exceptions.exit) - .exceptions.exit - 0x00000098 0x54 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - *(.exceptions) - .exceptions 0x000000ec 0xc8 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_handler.o) - 0x000000ec alt_irq_handler - 0x000001b4 PROVIDE (__ram_exceptions_end, ABSOLUTE (.)) - 0x00000020 PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions)) - -.text 0x000001b4 0xfce4 - 0x000001b4 PROVIDE (stext, ABSOLUTE (.)) - *(.interp) - *(.hash) - *(.dynsym) - *(.dynstr) - *(.gnu.version) - *(.gnu.version_d) - *(.gnu.version_r) - *(.rel.init) - *(.rela.init) - *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rel.fini) - *(.rela.fini) - *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rel.ctors) - *(.rela.ctors) - *(.rel.dtors) - *(.rela.dtors) - *(.rel.got) - *(.rela.got) - *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - *(.rel.plt) - *(.rela.plt) - *(.rel.dyn) - *(.init) - *(.plt) - *(.text .stub .text.* .gnu.linkonce.t.*) - .text 0x000001b4 0x3c ../qsys_tutorial_lcd4_bsp//obj/HAL/src/crt0.o - 0x000001b4 _start - .text 0x000001f0 0x1ec obj/default/LCD.o - 0x000001f0 LCD_Init - 0x0000028c LCD_Show_Text - 0x00000314 LCD_Line2 - 0x00000350 LCD_Test - .text 0x000003dc 0x7d4 obj/default/hello_world_small.o - 0x0000049c store_value - 0x00000580 store_inst - 0x000006e8 print_change_memory - 0x00000928 main - .text 0x00000bb0 0x630 obj/default/hex_encoder.o - 0x00000bb0 encodeNumHex - 0x00000d8c encodeLatHex - .text 0x000011e0 0x318 obj/default/hex_out.o - 0x000011e0 print_block - 0x00001370 clear_block - 0x00001400 print_number - .text 0x000014f8 0x2c0 obj/default/input_int.o - 0x000014f8 in_int - 0x00001608 push_decode - 0x000016b4 push_int - .text 0x000017b8 0x6d4 obj/default/inst_decoder.o - 0x000017b8 inst_fetch - 0x00001804 inst_decode - 0x00001a50 inst_jump - 0x00001aac inst_output - 0x00001b1c inst_load - 0x00001b54 inst_store - 0x00001b8c inst_delay - 0x00001be8 inst_add - 0x00001c44 inst_comp - 0x00001d14 inst_jeq - 0x00001d80 inst_jne - 0x00001dec inst_jieq - 0x00001e3c inst_jine - .text 0x00001e8c 0xc8 obj/default/lcd_out.o - 0x00001e8c lcd_init - 0x00001ed4 lcd_caret_reset - 0x00001efc lcd_caret_reset2 - 0x00001f24 lcd_print - .text 0x00001f54 0x560 obj/default/sys_debug.o - 0x00001f54 display_inst - 0x00002000 display_mem - 0x0000206c convertRegName - 0x000021dc convertInstName - 0x00002478 delay10ms - .text 0x000024b4 0x40 obj/default/sys_except.o - 0x000024b4 panic - .text 0x000024f4 0x240 obj/default/sys_memory.o - 0x000024f4 memory_init - 0x00002570 inst_memory_store - 0x000025c0 inst_memory_load - 0x00002608 memory_store - 0x000026a4 memory_load - .text 0x00002734 0x25c obj/default/sys_prog.o - 0x00002734 inc_pc - 0x000027b8 add_pc - 0x00002808 set_pc - 0x00002840 run_proc - .text 0x00002990 0x50 obj/default/sys_register.o - 0x00002990 registers_init - .text 0x000029e0 0x14c c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-divmod.o) - 0x00002a5c __divsi3 - 0x00002abc __modsi3 - 0x00002b1c __udivsi3 - 0x00002b24 __umodsi3 - .text 0x00002b2c 0x38 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(lib2-mul.o) - 0x00002b2c __mulsi3 - .text 0x00002b64 0x0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-ctype_.o) - .text 0x00002b64 0xd4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-sprintf.o) - 0x00002b64 sprintf - 0x00002bd8 _sprintf_r - .text 0x00002c38 0x74 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-strlen.o) - 0x00002c38 strlen - .text 0x00002cac 0x1f40 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) - 0x00002d04 ___vfprintf_internal_r - 0x00004bc8 __vfprintf_internal - .text 0x00004bec 0x13c c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-wsetup.o) - 0x00004bec __swsetup_r - .text 0x00004d28 0x17f8 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-dtoa.o) - 0x00004f6c _dtoa_r - .text 0x00006520 0x230 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o) - 0x00006520 _fflush_r - 0x0000671c fflush - .text 0x00006750 0x2f4 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-findfp.o) - 0x000067a8 __sfp_lock_acquire - 0x000067ac __sfp_lock_release - 0x000067b0 __sinit_lock_acquire - 0x000067b4 __sinit_lock_release - 0x000067b8 __sinit - 0x0000686c __fp_unlock_all - 0x00006884 __fp_lock_all - 0x0000689c _cleanup_r - 0x000068a8 _cleanup - 0x000068b8 __sfmoreglue - 0x00006954 __sfp - .text 0x00006a44 0x440 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-freer.o) - 0x00006a44 _malloc_trim_r - 0x00006b70 _free_r - .text 0x00006e84 0x49c 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0x0000bbc6 0xac ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_init.o) - .debug_loc 0x0000bc72 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_ioctl.o) - .debug_loc 0x0000bc9d 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_read.o) - .debug_loc 0x0000bcc8 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_jtag_uart_write.o) - .debug_loc 0x0000bcf3 0x184 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_lcd_16207.o) - .debug_loc 0x0000be77 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_avalon_lcd_16207_fd.o) - .debug_loc 0x0000bea2 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_alarm_start.o) - .debug_loc 0x0000becd 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_busy_sleep.o) - .debug_loc 0x0000bef8 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_dcache_flush_all.o) - .debug_loc 0x0000bf23 0x56 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_dev_llist_insert.o) - .debug_loc 0x0000bf79 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_do_ctors.o) - .debug_loc 0x0000bfa4 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_do_dtors.o) - .debug_loc 0x0000bfcf 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_icache_flush_all.o) - .debug_loc 0x0000bffa 0xac ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic.o) - .debug_loc 0x0000c0a6 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_iic_isr_register.o) - .debug_loc 0x0000c0d1 0x56 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_io_redirect.o) - .debug_loc 0x0000c127 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_handler.o) - .debug_loc 0x0000c152 0x81 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_open.o) - .debug_loc 0x0000c1d3 0x56 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_tick.o) - .debug_loc 0x0000c229 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(altera_nios2_qsys_irq.o) - .debug_loc 0x0000c254 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_find_dev.o) - .debug_loc 0x0000c27f 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_find_file.o) - .debug_loc 0x0000c2aa 0x2b ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_get_fd.o) - .debug_loc 0x0000c2d5 0x1e c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-atexit.o) - .debug_loc 0x0000c2f3 0x3d c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-exit.o) - .debug_loc 0x0000c330 0x114 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-memcmp.o) - .debug_loc 0x0000c444 0x120 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__atexit.o) - .debug_loc 0x0000c564 0x1cb c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) - .debug_loc 0x0000c72f 0x56 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exit.o) - -.debug_macinfo - *(.debug_macinfo) - -.debug_weaknames - *(.debug_weaknames) - -.debug_funcnames - *(.debug_funcnames) - -.debug_typenames - *(.debug_typenames) - -.debug_varnames - *(.debug_varnames) - -.debug_alt_sim_info - 0x00000000 0x40 - *(.debug_alt_sim_info) - .debug_alt_sim_info - 0x00000000 0x10 ../qsys_tutorial_lcd4_bsp//obj/HAL/src/crt0.o - .debug_alt_sim_info - 0x00000010 0x30 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_busy_sleep.o) - 0x00032000 __alt_data_end = 0x32000 - 0x00032000 PROVIDE (__alt_stack_pointer, __alt_data_end) - 0x000144dc PROVIDE (__alt_stack_limit, __alt_stack_base) - 0x000144dc PROVIDE (__alt_heap_start, end) - 0x00032000 PROVIDE (__alt_heap_limit, 0x32000) -OUTPUT(qsys_tutorial_lcd4.elf elf32-littlenios2) - -.debug_ranges 0x00000000 0x9e0 - .debug_ranges 0x00000000 0x20 ../qsys_tutorial_lcd4_bsp//obj/HAL/src/crt0.o - .debug_ranges 0x00000020 0x168 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-vfprintf.o) - .debug_ranges 0x00000188 0x20 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fflush.o) - .debug_ranges 0x000001a8 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fvwrite.o) - .debug_ranges 0x000001d0 0xa0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-fwalk.o) - .debug_ranges 0x00000270 0x70 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-mallocr.o) - .debug_ranges 0x000002e0 0x110 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-reallocr.o) - .debug_ranges 0x000003f0 0x38 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-callocr.o) - .debug_ranges 0x00000428 0x190 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_udivdi3.o) - .debug_ranges 0x000005b8 0x1c0 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_umoddi3.o) - .debug_ranges 0x00000778 0x30 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_addsub_df.o) - .debug_ranges 0x000007a8 0x88 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_mul_df.o) - .debug_ranges 0x00000830 0x50 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_div_df.o) - .debug_ranges 0x00000880 0x18 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_usi_to_df.o) - .debug_ranges 0x00000898 0x88 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_muldi3.o) - .debug_ranges 0x00000920 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_clzsi2.o) - .debug_ranges 0x00000948 0x28 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/mno-hw-mul\libgcc.a(_pack_df.o) - .debug_ranges 0x00000970 0x28 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_irq_entry.o) - .debug_ranges 0x00000998 0x30 ../qsys_tutorial_lcd4_bsp/\libhal_bsp.a(alt_exception_entry.o) - .debug_ranges 0x000009c8 0x18 c:/altera/13.0sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib/mno-hw-mul\libc.a(lib_a-__call_atexit.o) diff --git a/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.objdump b/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.objdump deleted file mode 100644 index 8d3995c..0000000 --- a/software/qsys_tutorial_lcd4/qsys_tutorial_lcd4.objdump +++ /dev/null @@ -1,20849 +0,0 @@ - -qsys_tutorial_lcd4.elf: file format elf32-littlenios2 -qsys_tutorial_lcd4.elf -architecture: nios2, flags 0x00000112: -EXEC_P, HAS_SYMS, D_PAGED -start address 0x000001b4 - -Program Header: - LOAD off 0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12 - filesz 0x00000020 memsz 0x00000020 flags r-x - LOAD off 0x00001020 vaddr 0x00000020 paddr 0x00000020 align 2**12 - filesz 0x0001059c memsz 0x0001059c flags r-x - LOAD off 0x000115bc vaddr 0x000105bc paddr 0x00012144 align 2**12 - filesz 0x00001b88 memsz 0x00001b88 flags rw- - LOAD off 0x00013ccc vaddr 0x00013ccc paddr 0x00013ccc align 2**12 - filesz 0x00000000 memsz 0x00000810 flags rw- - -Sections: -Idx Name Size VMA LMA File off Algn - 0 .entry 00000020 00000000 00000000 00001000 2**5 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .exceptions 00000194 00000020 00000020 00001020 2**2 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .text 0000fce4 000001b4 000001b4 000011b4 2**2 - CONTENTS, ALLOC, LOAD, READONLY, CODE - 3 .rodata 00000724 0000fe98 0000fe98 00010e98 2**2 - CONTENTS, ALLOC, LOAD, READONLY, DATA - 4 .rwdata 00001b88 000105bc 00012144 000115bc 2**2 - CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA - 5 .bss 00000810 00013ccc 00013ccc 00013ccc 2**2 - ALLOC, SMALL_DATA - 6 .comment 00000026 00000000 00000000 00013144 2**0 - CONTENTS, READONLY - 7 .debug_aranges 00000e18 00000000 00000000 00013170 2**3 - CONTENTS, READONLY, DEBUGGING - 8 .debug_pubnames 000017c0 00000000 00000000 00013f88 2**0 - CONTENTS, READONLY, DEBUGGING - 9 .debug_info 000252ff 00000000 00000000 00015748 2**0 - CONTENTS, READONLY, DEBUGGING - 10 .debug_abbrev 00008258 00000000 00000000 0003aa47 2**0 - CONTENTS, READONLY, DEBUGGING - 11 .debug_line 00015d29 00000000 00000000 00042c9f 2**0 - CONTENTS, READONLY, DEBUGGING - 12 .debug_frame 00001ff4 00000000 00000000 000589c8 2**2 - CONTENTS, READONLY, DEBUGGING - 13 .debug_str 000023b5 00000000 00000000 0005a9bc 2**0 - CONTENTS, READONLY, DEBUGGING - 14 .debug_loc 0000c785 00000000 00000000 0005cd71 2**0 - CONTENTS, READONLY, DEBUGGING - 15 .debug_alt_sim_info 00000040 00000000 00000000 000694f8 2**2 - CONTENTS, READONLY, DEBUGGING - 16 .debug_ranges 000009e0 00000000 00000000 00069538 2**3 - CONTENTS, READONLY, DEBUGGING - 17 .thread_model 00000003 00000000 00000000 0006d707 2**0 - CONTENTS, READONLY - 18 .cpu 0000000f 00000000 00000000 0006d70a 2**0 - CONTENTS, READONLY - 19 .qsys 00000001 00000000 00000000 0006d719 2**0 - CONTENTS, READONLY - 20 .simulation_enabled 00000001 00000000 00000000 0006d71a 2**0 - CONTENTS, READONLY - 21 .stderr_dev 00000009 00000000 00000000 0006d71b 2**0 - CONTENTS, READONLY - 22 .stdin_dev 00000009 00000000 00000000 0006d724 2**0 - CONTENTS, READONLY - 23 .stdout_dev 00000009 00000000 00000000 0006d72d 2**0 - CONTENTS, READONLY - 24 .sopc_system_name 0000000b 00000000 00000000 0006d736 2**0 - CONTENTS, READONLY - 25 .quartus_project_dir 00000030 00000000 00000000 0006d741 2**0 - CONTENTS, READONLY - 26 .sopcinfo 0007d2ad 00000000 00000000 0006d771 2**0 - CONTENTS, READONLY -SYMBOL TABLE: -00000000 l d .entry 00000000 .entry -00000020 l d .exceptions 00000000 .exceptions -000001b4 l d .text 00000000 .text -0000fe98 l d .rodata 00000000 .rodata -000105bc l d .rwdata 00000000 .rwdata -00013ccc l d .bss 00000000 .bss -00000000 l d .comment 00000000 .comment -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_pubnames 00000000 .debug_pubnames -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .debug_loc 00000000 .debug_loc -00000000 l d .debug_alt_sim_info 00000000 .debug_alt_sim_info -00000000 l d .debug_ranges 00000000 .debug_ranges -000001ec l .text 00000000 alt_after_alt_main -00000000 l df *ABS* 00000000 alt_irq_handler.c -00000000 l df *ABS* 00000000 LCD.c -00000000 l df *ABS* 00000000 hello_world_small.c -000003dc l F .text 000000c0 init -00000758 l F .text 00000044 reset_mem_cancel -0000079c l F .text 000000b4 reset_mem -00000850 l F .text 00000044 reset_pc_cancel -00000894 l F .text 00000094 reset_pc -00000000 l df *ABS* 00000000 hex_encoder.c -00000000 l df *ABS* 00000000 hex_out.c -00000000 l df *ABS* 00000000 input_int.c -00001520 l F .text 000000e8 update_sw_reg -00013cd4 l O .bss 00000004 event_code.1400 -00013cd8 l O .bss 00000001 status.1399 -00000000 l df *ABS* 00000000 inst_decoder.c -00000000 l df *ABS* 00000000 lcd_out.c -00000000 l df *ABS* 00000000 sys_debug.c -00000000 l df *ABS* 00000000 sys_except.c -00000000 l df *ABS* 00000000 sys_memory.c -00013d14 l O .bss 00000100 memory -00013e14 l O .bss 00000400 inst_memory -00000000 l df *ABS* 00000000 sys_prog.c -00000000 l df *ABS* 00000000 sys_register.c -00000000 l df *ABS* 00000000 lib2-divmod.c -000029e0 l F .text 0000007c udivmodsi4 -00000000 l df *ABS* 00000000 lib2-mul.c -00000000 l df *ABS* 00000000 ctype_.c -000100ed l O .rodata 00000180 _ctype_b -00000000 l df *ABS* 00000000 sprintf.c -00000000 l df *ABS* 00000000 strlen.c -00000000 l df *ABS* 00000000 vfprintf.c -00002cac l F .text 00000058 __sprint_r -000102de l O .rodata 00000010 blanks.3452 -000102ce l O .rodata 00000010 zeroes.3453 -00000000 l df *ABS* 00000000 wsetup.c -00000000 l df *ABS* 00000000 dtoa.c -00004d28 l F .text 00000244 quorem -00000000 l df *ABS* 00000000 fflush.c -00000000 l df *ABS* 00000000 findfp.c -00006750 l F .text 00000058 std -0000685c l F .text 00000008 __fp_lock -00006864 l F .text 00000008 __fp_unlock -00000000 l df *ABS* 00000000 mallocr.c -00000000 l df *ABS* 00000000 fvwrite.c -00000000 l df *ABS* 00000000 fwalk.c -00000000 l df *ABS* 00000000 impure.c -000105bc l O .rwdata 00000400 impure_data -00000000 l df *ABS* 00000000 locale.c -0001210c l O .rwdata 00000004 charset -00010314 l O .rodata 00000030 lconv -00000000 l df *ABS* 00000000 makebuf.c -00000000 l df *ABS* 00000000 mallocr.c -00000000 l df *ABS* 00000000 memchr.c -00000000 l df *ABS* 00000000 memcpy.c -00000000 l df *ABS* 00000000 memmove.c -00000000 l df *ABS* 00000000 memset.c -00000000 l df *ABS* 00000000 mprec.c -0001045c l O .rodata 0000000c p05.2458 -00000000 l df *ABS* 00000000 mallocr.c -00000000 l df *ABS* 00000000 s_isinfd.c -00000000 l df *ABS* 00000000 s_isnand.c -00000000 l df *ABS* 00000000 sbrkr.c -00000000 l df *ABS* 00000000 stdio.c -00000000 l df *ABS* 00000000 strcmp.c -00000000 l df *ABS* 00000000 writer.c -00000000 l df *ABS* 00000000 mallocr.c -00000000 l df *ABS* 00000000 closer.c -00000000 l df *ABS* 00000000 fclose.c -00000000 l df *ABS* 00000000 fstatr.c -00000000 l df *ABS* 00000000 int_errno.c -00000000 l df *ABS* 00000000 isattyr.c -00000000 l df *ABS* 00000000 lseekr.c -00000000 l df *ABS* 00000000 readr.c -00000000 l df *ABS* 00000000 libgcc2.c -00000000 l df *ABS* 00000000 libgcc2.c -00000000 l df *ABS* 00000000 dp-bit.c -0000ac10 l F .text 00000410 _fpadd_parts -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 libgcc2.c -00000000 l df *ABS* 00000000 libgcc2.c -00000000 l df *ABS* 00000000 libgcc2.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 dp-bit.c -00000000 l df *ABS* 00000000 alt_close.c -0000c4f4 l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_dev.c -0000c554 l F .text 0000002c alt_dev_null_write -00000000 l df *ABS* 00000000 alt_errno.c -00000000 l df *ABS* 00000000 alt_fstat.c -0000c658 l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_isatty.c -0000c77c l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_load.c -0000c85c l F .text 0000006c alt_load_section -00000000 l df *ABS* 00000000 alt_lseek.c -0000c9bc l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_main.c -00000000 l df *ABS* 00000000 alt_malloc_lock.c -00000000 l df *ABS* 00000000 alt_read.c -0000cbec l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_release_fd.c -00000000 l df *ABS* 00000000 alt_sbrk.c -00012130 l O .rwdata 00000004 heap_end -00000000 l df *ABS* 00000000 alt_usleep.c -00000000 l df *ABS* 00000000 alt_write.c -0000ced4 l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_sys_init.c -00010f78 l O .rwdata 00001060 jtag_uart -00011fd8 l O .rwdata 00000120 lcd_16207_0 -0000cfc4 l F .text 00000038 alt_dev_reg -00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_fd.c -00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_init.c -0000d204 l F .text 00000228 altera_avalon_jtag_uart_irq -0000d42c l F .text 000000b0 altera_avalon_jtag_uart_timeout -00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_ioctl.c -00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_read.c -00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_write.c -00000000 l df *ABS* 00000000 altera_avalon_lcd_16207.c -00012134 l O .rwdata 00000004 colstart -0000daa8 l F .text 000000b8 lcd_write_command -0000db60 l F .text 000000d4 lcd_write_data -0000dc34 l F .text 000000d8 lcd_clear_screen -0000dd0c l F .text 00000214 lcd_repaint_screen -0000df20 l F .text 000000e0 lcd_scroll_up -0000e000 l F .text 000002e4 lcd_handle_escape -0000e820 l F .text 000000cc alt_lcd_16207_timeout -00000000 l df *ABS* 00000000 altera_avalon_lcd_16207_fd.c -00000000 l df *ABS* 00000000 alt_alarm_start.c -00000000 l df *ABS* 00000000 alt_busy_sleep.c -00000000 l df *ABS* 00000000 alt_dcache_flush_all.c -00000000 l df *ABS* 00000000 alt_dev_llist_insert.c -0000ee00 l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_do_ctors.c -00000000 l df *ABS* 00000000 alt_do_dtors.c -00000000 l df *ABS* 00000000 alt_icache_flush_all.c -00000000 l df *ABS* 00000000 alt_iic.c -00000000 l df *ABS* 00000000 alt_iic_isr_register.c -00000000 l df *ABS* 00000000 alt_io_redirect.c -0000f210 l F .text 000000d8 alt_open_fd -00000000 l df *ABS* 00000000 alt_irq_vars.c -00000000 l df *ABS* 00000000 alt_open.c -0000f360 l F .text 000000f8 alt_file_locked -0000f5e4 l F .text 00000060 alt_get_errno -00000000 l df *ABS* 00000000 alt_tick.c -00000000 l df *ABS* 00000000 altera_nios2_qsys_irq.c -00000000 l df *ABS* 00000000 alt_find_dev.c -00000000 l df *ABS* 00000000 alt_find_file.c -00000000 l df *ABS* 00000000 alt_get_fd.c -00000000 l df *ABS* 00000000 atexit.c -00000000 l df *ABS* 00000000 exit.c -00000000 l df *ABS* 00000000 memcmp.c -00000000 l df *ABS* 00000000 __atexit.c -00000000 l df *ABS* 00000000 __call_atexit.c -0000fc80 l F .text 00000004 register_fini -00000000 l df *ABS* 00000000 alt_exit.c -0000fe34 l F .text 00000040 alt_sim_halt -00008540 g F .text 00000094 _mprec_log10 -0000862c g F .text 00000088 __any_on -00009de4 g F .text 00000070 _isatty_r -00010434 g O .rodata 00000028 __mprec_tinytens -00001b1c g F .text 00000038 inst_load -0000ca1c g F .text 0000006c alt_main -0001424c g O .bss 00000100 alt_irq -00009e54 g F .text 00000078 _lseek_r -00012144 g *ABS* 00000000 __flash_rwdata_start -0000b730 g F .text 00000088 __eqdf2 -000144dc g *ABS* 00000000 __alt_heap_start -0000989c g F .text 00000068 __sseek -000067b8 g F .text 000000a4 __sinit -00002734 g F .text 00000084 inc_pc -00001370 g F .text 00000090 clear_block -000074c4 g F .text 00000084 _setlocale_r -0000049c g F .text 000000e4 store_value -000068b8 g F .text 0000009c __sfmoreglue -0000caa8 g F .text 00000020 __malloc_unlock -00001be8 g F .text 0000005c inst_add -00001e3c g F .text 00000050 inst_jine -00007fbc g F .text 000000e0 memmove -000068a8 g F .text 00000010 _cleanup -000086b4 g F .text 000000bc _Balloc -00000350 g F .text 0000008c LCD_Test -0000b840 g F .text 00000088 __gtdf2 -00000000 w *UND* 00000000 __errno -00000000 g F .entry 0000000c __reset -00000020 g *ABS* 00000000 __flash_exceptions_start -00009d70 g F .text 00000074 _fstat_r -00013cf8 g O .bss 00000004 errno -00013d00 g O .bss 00000004 alt_argv -0001a0f8 g *ABS* 00000000 _gp -0000cd80 g F .text 00000030 usleep -00010df8 g O .rwdata 00000180 alt_fd_list -00001a50 g F .text 0000005c inst_jump -00002478 g F .text 0000003c delay10ms -0000f808 g F .text 00000094 alt_find_dev -00007f1c g F .text 000000a0 memcpy -0000689c g F .text 0000000c _cleanup_r -0000b9d8 g F .text 000000f8 __floatsidf -0000f2e8 g F .text 00000078 alt_io_redirect -0000b950 g F .text 00000088 __ltdf2 -0000fe98 g *ABS* 00000000 __DTOR_END__ -00008490 g F .text 000000b0 __ratio -00002840 g F .text 00000150 run_proc -0000d644 g F .text 00000224 altera_avalon_jtag_uart_read -00000000 w *UND* 00000000 malloc -00002b1c g F .text 00000008 __udivsi3 -0000c6b8 g F .text 000000c4 isatty -00010344 g O .rodata 000000c8 __mprec_tens -000074a0 g F .text 00000008 __locale_charset -00013cec g O .bss 00000004 __malloc_top_pad -00012108 g O .rwdata 00000004 __mb_cur_max -000074a8 g F .text 0000000c _localeconv_r -00008e18 g F .text 0000003c __i2b -00006e84 g F .text 0000049c __sfvwrite_r -00009824 g F .text 00000070 _sbrk_r -00001ed4 g F .text 00000028 lcd_caret_reset -00001dec g F .text 00000050 inst_jieq -00009ecc g F .text 00000078 _read_r -000109bc g O .rwdata 0000000c __lc_ctype -00012128 g O .rwdata 00000004 alt_max_fd -0000c1f4 g F .text 00000138 __unpack_d -00009c4c g F .text 00000110 _fclose_r -0000206c g F .text 00000170 convertRegName -0000671c g F .text 00000034 fflush -00013cf0 g O .bss 00000004 __malloc_max_sbrked_mem -00001aac g F .text 00000070 inst_output -0000b0a0 g F .text 00000074 __adddf3 -00008370 g F .text 00000120 __b2d -00002608 g F .text 0000009c memory_store -0000a5b0 g F .text 00000660 __umoddi3 -0000c8c8 g F .text 000000f4 lseek -00012104 g O .rwdata 00000004 _global_impure_ptr -000091c0 g F .text 000005f4 _realloc_r -000144dc g *ABS* 00000000 __bss_end -0000f118 g F .text 000000f8 alt_iic_isr_register -0000f6dc g F .text 0000010c alt_tick -00013ccc g O .bss 00000005 stack -00009f44 g F .text 0000066c __udivdi3 -0001040c g O .rodata 00000028 __mprec_bigtens -000090a0 g F .text 00000120 __s2b -0000bba8 g F .text 00000194 __floatunsidf -00008290 g F .text 00000060 __mcmp -000120fc g O .rwdata 00000004 __ctype_ptr -00006884 g F .text 00000018 __fp_lock_all -0000f0d0 g F .text 00000048 alt_ic_irq_enabled -0000f644 g F .text 00000098 alt_alarm_stop -00013d08 g O .bss 00000004 alt_irq_active -000017b8 g F .text 0000004c inst_fetch -000000ec g F .exceptions 000000c8 alt_irq_handler -00010dd0 g O .rwdata 00000028 alt_dev_null -0000ed30 g F .text 0000001c alt_dcache_flush_all -0000815c g F .text 00000070 __hi0bits -0001423c g O .bss 0000000f global_registers -0000bad0 g F .text 000000d8 __fixdfsi -00001d14 g F .text 0000006c inst_jeq -00012144 g *ABS* 00000000 __ram_rwdata_end -00000000 g *ABS* 00000000 __alt_mem_onchip_memory -00012120 g O .rwdata 00000008 alt_dev_list -0000cdb0 g F .text 00000124 write -000105bc g *ABS* 00000000 __ram_rodata_end -0000c580 g F .text 000000d8 fstat -00008f80 g F .text 00000120 __pow5mult -00013ce0 g O .bss 00000004 __nlocale_changed -00002b24 g F .text 00000008 __umodsi3 -000144dc g *ABS* 00000000 end -0000e2e4 g F .text 0000053c altera_avalon_lcd_16207_write -000027b8 g F .text 00000050 add_pc -0000d144 g F .text 000000c0 altera_avalon_jtag_uart_init -0000fe94 g *ABS* 00000000 __CTOR_LIST__ -00032000 g *ABS* 00000000 __alt_stack_pointer -0000be60 g F .text 00000080 __clzsi2 -0000d868 g F .text 00000240 altera_avalon_jtag_uart_write -000067a8 g F .text 00000004 __sfp_lock_acquire -00007e38 g F .text 000000e4 memchr -00002d04 g F .text 00001ec4 ___vfprintf_internal_r -00002bd8 g F .text 00000060 _sprintf_r -00006b70 g F .text 00000314 _free_r -0000fc84 g F .text 000001b0 __call_exitprocs -00013ce4 g O .bss 00000004 __mlocale_changed -00001400 g F .text 000000f8 print_number -00012114 g O .rwdata 00000004 __malloc_sbrk_base -000001b4 g F .text 0000003c _start -00013d0c g O .bss 00000004 _alt_tick_rate -000011e0 g F .text 00000190 print_block -00008a78 g F .text 0000014c __lshift -00013d10 g O .bss 00000004 _alt_nticks -0000cac8 g F .text 00000124 read -0000cf68 g F .text 0000005c alt_sys_init -0000fb4c g F .text 00000134 __register_exitproc -00008bc4 g F .text 00000254 __multiply -00001f24 g F .text 00000030 lcd_print -0000d4dc g F .text 00000074 altera_avalon_jtag_uart_close -00002b2c g F .text 00000038 __mulsi3 -000105bc g *ABS* 00000000 __ram_rwdata_start -0000fe98 g *ABS* 00000000 __ram_rodata_start -00014214 g O .bss 00000028 __malloc_current_mallinfo -00008770 g F .text 0000017c __d2b -0000cffc g F .text 00000058 altera_avalon_jtag_uart_read_fd -0000f9bc g F .text 000000d0 alt_get_fd -000024b4 g F .text 00000040 panic -0000ebd4 g F .text 0000015c alt_busy_sleep -0000c32c g F .text 000000c8 __fpcmp_parts_d -00009bdc g F .text 00000070 _close_r -0000fad8 g F .text 00000074 memcmp -0000d0ac g F .text 00000048 altera_avalon_jtag_uart_close_fd -000144dc g *ABS* 00000000 __alt_stack_base -0000d0f4 g F .text 00000050 altera_avalon_jtag_uart_ioctl_fd -00001b8c g F .text 0000005c inst_delay -00001b54 g F .text 00000038 inst_store -00001f54 g F .text 000000ac display_inst -00004bec g F .text 0000013c __swsetup_r -0000b4d8 g F .text 00000258 __divdf3 -00006954 g F .text 000000f0 __sfp -000085d4 g F .text 00000058 __copybits -000109c8 g O .rwdata 00000408 __malloc_av_ -000067b4 g F .text 00000004 __sinit_lock_release -0000b114 g F .text 000003c4 __muldf3 -00009980 g F .text 00000060 __sread -0000f89c g F .text 00000120 alt_find_file -0000ed4c g F .text 000000b4 alt_dev_llist_insert -0000ca88 g F .text 00000020 __malloc_lock -0000ccc4 g F .text 000000bc sbrk -00006520 g F .text 000001fc _fflush_r -00009b14 g F .text 000000c8 _calloc_r -00013ccc g *ABS* 00000000 __bss_start -000001f0 g F .text 0000009c LCD_Init -0000809c g F .text 00000098 memset -00001e8c g F .text 00000048 lcd_init -00000928 g F .text 00000288 main -00013d04 g O .bss 00000004 alt_envp -00013cf4 g O .bss 00000004 __malloc_max_total_mem -0000d054 g F .text 00000058 altera_avalon_jtag_uart_write_fd -0000e8ec g F .text 0000013c altera_avalon_lcd_16207_init -00000314 g F .text 0000003c LCD_Line2 -00000bb0 g F .text 000001dc encodeNumHex -00009894 g F .text 00000008 __sclose -00032000 g *ABS* 00000000 __alt_heap_limit -00009d5c g F .text 00000014 fclose -0001434c g O .bss 00000190 _atexit0 -00004f6c g F .text 000015b4 _dtoa_r -000076f8 g F .text 00000740 _malloc_r -0001212c g O .rwdata 00000004 alt_errno -000073e8 g F .text 000000b8 _fwalk -000014f8 g F .text 00000028 in_int -00002a5c g F .text 00000060 __divsi3 -00010468 g O .rodata 00000014 __thenan_df -00006a44 g F .text 0000012c _malloc_trim_r -0000fe98 g *ABS* 00000000 __CTOR_END__ -000099e0 g F .text 000000bc strcmp -0000fe98 g *ABS* 00000000 __flash_rodata_start -0000fe98 g *ABS* 00000000 __DTOR_LIST__ -0000b7b8 g F .text 00000088 __nedf2 -0000cf34 g F .text 00000034 alt_irq_init -0000028c g F .text 00000088 LCD_Show_Text -0000cc4c g F .text 00000078 alt_release_fd -00002b64 g F .text 00000074 sprintf -0001047c g O .rodata 00000100 __clz_tab -00013ce8 g O .bss 00000004 _PathLocale -0000fa8c g F .text 00000014 atexit -00002808 g F .text 00000038 set_pc -00009a9c g F .text 00000078 _write_r -00007548 g F .text 0000001c setlocale -000006e8 g F .text 00000070 print_change_memory -000016b4 g F .text 00000104 push_int -00002000 g F .text 0000006c display_mem -00012100 g O .rwdata 00000004 _impure_ptr -00013cfc g O .bss 00000004 alt_argc -00013cdc g O .bss 00000004 global_current_memory -0000eec4 g F .text 00000064 _do_dtors -00000020 g .exceptions 00000000 alt_irq_entry -000082f0 g F .text 00000080 __ulp -000097b4 g F .text 00000040 __isinfd -0000686c g F .text 00000018 __fp_unlock_all -0000ea28 g F .text 00000058 altera_avalon_lcd_16207_write_fd -00012118 g O .rwdata 00000008 alt_fs_list -00000020 g *ABS* 00000000 __ram_exceptions_start -000074b4 g F .text 00000010 localeconv -00000d8c g F .text 00000454 encodeLatHex -000021dc g F .text 0000029c convertInstName -0000ef44 g F .text 00000050 alt_ic_isr_register -00012144 g *ABS* 00000000 _edata -000144dc g *ABS* 00000000 _end -000001b4 g *ABS* 00000000 __ram_exceptions_end -0000d550 g F .text 000000f4 altera_avalon_jtag_uart_ioctl -00001efc g F .text 00000028 lcd_caret_reset2 -0000f030 g F .text 000000a0 alt_ic_irq_disable -000024f4 g F .text 0000007c memory_init -00009904 g F .text 0000007c __swrite -00012110 g O .rwdata 00000004 __malloc_trim_threshold -0000f7e8 g F .text 00000020 altera_nios2_qsys_irq_init -0000faa0 g F .text 00000038 exit -000026a4 g F .text 00000090 memory_load -00007320 g F .text 000000c8 _fwalk_reent -000088ec g F .text 0000018c __mdiff -00002abc g F .text 00000060 __modsi3 -00032000 g *ABS* 00000000 __alt_data_end -00000020 g F .exceptions 00000000 alt_exception -000067ac g F .text 00000004 __sfp_lock_release -00001804 g F .text 0000024c inst_decode -0000ffec g O .rodata 00000101 _ctype_ -00001c44 g F .text 000000d0 inst_comp -0000fe74 g F .text 00000020 _exit -000097f4 g F .text 00000030 __isnand -00002990 g F .text 00000050 registers_init -0000ea80 g F .text 00000154 alt_alarm_start -0000bd3c g F .text 00000124 __muldi3 -00007564 g F .text 00000194 __smakebuf_r -00001d80 g F .text 0000006c inst_jne -00002c38 g F .text 00000074 strlen -0000f458 g F .text 0000018c open -0000b8c8 g F .text 00000088 __gedf2 -00000580 g F .text 00000168 store_inst -0000ef28 g F .text 0000001c alt_icache_flush_all -00012138 g O .rwdata 00000004 alt_priority_mask -0000ef94 g F .text 0000009c alt_ic_irq_enable -00004bc8 g F .text 00000024 __vfprintf_internal -0000b020 g F .text 00000080 __subdf3 -000081cc g F .text 000000c4 __lo0bits -0001213c g O .rwdata 00000008 alt_alarm_list -0000ee60 g F .text 00000064 _do_ctors -00002570 g F .text 00000050 inst_memory_store -0000c3f4 g F .text 00000100 close -00001608 g F .text 000000ac push_decode -0000c7dc g F .text 00000080 alt_load -0000bee0 g F .text 00000314 __pack_d -000120f8 g O .rwdata 00000001 PUSH_EVENT -000025c0 g F .text 00000048 inst_memory_load -00000000 w *UND* 00000000 free -000067b0 g F .text 00000004 __sinit_lock_acquire -00008e54 g F .text 0000012c __multadd -00008134 g F .text 00000028 _Bfree - - - -Disassembly of section .entry: - -00000000 <__reset>: - * Jump to the _start entry point in the .text section if reset code - * is allowed or if optimizing for RTL simulation. - */ -#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) - /* Jump to the _start entry point in the .text section. */ - movhi r1, %hi(_start) - 0: 00400034 movhi at,0 - ori r1, r1, %lo(_start) - 4: 08406d14 ori at,at,436 - jmp r1 - 8: 0800683a jmp at - ... - -Disassembly of section .exceptions: - -00000020 : - * Process an exception. For all exceptions we must preserve all - * caller saved registers on the stack (See the Nios2 ABI - * documentation for details). - */ - - addi sp, sp, -76 - 20: deffed04 addi sp,sp,-76 - -#endif - -#endif - - stw ra, 0(sp) - 24: dfc00015 stw ra,0(sp) - /* - * Leave a gap in the stack frame at 4(sp) for the muldiv handler to - * store zero into. - */ - - stw r1, 8(sp) - 28: d8400215 stw at,8(sp) - stw r2, 12(sp) - 2c: d8800315 stw r2,12(sp) - stw r3, 16(sp) - 30: d8c00415 stw r3,16(sp) - stw r4, 20(sp) - 34: d9000515 stw r4,20(sp) - stw r5, 24(sp) - 38: d9400615 stw r5,24(sp) - stw r6, 28(sp) - 3c: d9800715 stw r6,28(sp) - stw r7, 32(sp) - 40: d9c00815 stw r7,32(sp) - - rdctl r5, estatus - 44: 000b307a rdctl r5,estatus - - stw r8, 36(sp) - 48: da000915 stw r8,36(sp) - stw r9, 40(sp) - 4c: da400a15 stw r9,40(sp) - stw r10, 44(sp) - 50: da800b15 stw r10,44(sp) - stw r11, 48(sp) - 54: dac00c15 stw r11,48(sp) - stw r12, 52(sp) - 58: db000d15 stw r12,52(sp) - stw r13, 56(sp) - 5c: db400e15 stw r13,56(sp) - stw r14, 60(sp) - 60: db800f15 stw r14,60(sp) - stw r15, 64(sp) - 64: dbc01015 stw r15,64(sp) - /* - * ea-4 contains the address of the instruction being executed - * when the exception occured. For interrupt exceptions, we will - * will be re-issue the isntruction. Store it in 72(sp) - */ - stw r5, 68(sp) /* estatus */ - 68: d9401115 stw r5,68(sp) - addi r15, ea, -4 /* instruction that caused exception */ - 6c: ebffff04 addi r15,ea,-4 - stw r15, 72(sp) - 70: dbc01215 stw r15,72(sp) -#else - /* - * Test to see if the exception was a software exception or caused - * by an external interrupt, and vector accordingly. - */ - rdctl r4, ipending - 74: 0009313a rdctl r4,ipending - andi r2, r5, 1 - 78: 2880004c andi r2,r5,1 - beq r2, zero, .Lnot_irq - 7c: 10000326 beq r2,zero,8c - beq r4, zero, .Lnot_irq - 80: 20000226 beq r4,zero,8c - /* - * Now that all necessary registers have been preserved, call - * alt_irq_handler() to process the interrupts. - */ - - call alt_irq_handler - 84: 00000ec0 call ec - - .section .exceptions.irqreturn, "xa" - - br .Lexception_exit - 88: 00000306 br 98 - * upon completion, so we write ea (address of instruction *after* - * the one where the exception occured) into 72(sp). The actual - * instruction that caused the exception is written in r2, which these - * handlers will utilize. - */ - stw ea, 72(sp) /* Don't re-issue */ - 8c: df401215 stw ea,72(sp) - ldw r2, -4(ea) /* Instruction that caused exception */ - 90: e8bfff17 ldw r2,-4(ea) -#ifdef NIOS2_HAS_DEBUG_STUB - /* - * Either tell the user now (if there is a debugger attached) or go into - * the debug monitor which will loop until a debugger is attached. - */ - break - 94: 003da03a break 0 - /* - * Restore the saved registers, so that all general purpose registers - * have been restored to their state at the time the interrupt occured. - */ - - ldw r5, 68(sp) - 98: d9401117 ldw r5,68(sp) - ldw ea, 72(sp) /* This becomes the PC once eret is executed */ - 9c: df401217 ldw ea,72(sp) - ldw ra, 0(sp) - a0: dfc00017 ldw ra,0(sp) - - wrctl estatus, r5 - a4: 2801707a wrctl estatus,r5 - - ldw r1, 8(sp) - a8: d8400217 ldw at,8(sp) - ldw r2, 12(sp) - ac: d8800317 ldw r2,12(sp) - ldw r3, 16(sp) - b0: d8c00417 ldw r3,16(sp) - ldw r4, 20(sp) - b4: d9000517 ldw r4,20(sp) - ldw r5, 24(sp) - b8: d9400617 ldw r5,24(sp) - ldw r6, 28(sp) - bc: d9800717 ldw r6,28(sp) - ldw r7, 32(sp) - c0: d9c00817 ldw r7,32(sp) -#ifdef ALT_STACK_CHECK - ldw et, %gprel(alt_exception_old_stack_limit)(gp) -#endif -#endif - - ldw r8, 36(sp) - c4: da000917 ldw r8,36(sp) - ldw r9, 40(sp) - c8: da400a17 ldw r9,40(sp) - ldw r10, 44(sp) - cc: da800b17 ldw r10,44(sp) - ldw r11, 48(sp) - d0: dac00c17 ldw r11,48(sp) - ldw r12, 52(sp) - d4: db000d17 ldw r12,52(sp) - ldw r13, 56(sp) - d8: db400e17 ldw r13,56(sp) - ldw r14, 60(sp) - dc: db800f17 ldw r14,60(sp) - ldw r15, 64(sp) - e0: dbc01017 ldw r15,64(sp) -#endif - - ldw sp, 76(sp) - -#else - addi sp, sp, 76 - e4: dec01304 addi sp,sp,76 - - /* - * Return to the interrupted instruction. - */ - - eret - e8: ef80083a eret - -000000ec : - * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. - */ - -void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); -void alt_irq_handler (void) -{ - ec: defff904 addi sp,sp,-28 - f0: dfc00615 stw ra,24(sp) - f4: df000515 stw fp,20(sp) - f8: df000504 addi fp,sp,20 -#ifndef NIOS2_EIC_PRESENT -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) -{ - alt_u32 active; - - NIOS2_READ_IPENDING (active); - fc: 0005313a rdctl r2,ipending - 100: e0bffc15 stw r2,-16(fp) - - return active; - 104: e0bffc17 ldw r2,-16(fp) - * Consider the case where the high priority interupt is asserted during - * the interrupt entry sequence for a lower priority interrupt to see why - * this is the case. - */ - - active = alt_irq_pending (); - 108: e0bfff15 stw r2,-4(fp) - - do - { - i = 0; - 10c: e03ffd15 stw zero,-12(fp) - mask = 1; - 110: 00800044 movi r2,1 - 114: e0bffe15 stw r2,-8(fp) - * called to clear the interrupt condition. - */ - - do - { - if (active & mask) - 118: e0ffff17 ldw r3,-4(fp) - 11c: e0bffe17 ldw r2,-8(fp) - 120: 1884703a and r2,r3,r2 - 124: 1005003a cmpeq r2,r2,zero - 128: 1000161e bne r2,zero,184 - { -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - alt_irq[i].handler(alt_irq[i].context); - 12c: e0bffd17 ldw r2,-12(fp) - 130: 00c00074 movhi r3,1 - 134: 18d09304 addi r3,r3,16972 - 138: 100490fa slli r2,r2,3 - 13c: 10c5883a add r2,r2,r3 - 140: 11400017 ldw r5,0(r2) - 144: e0bffd17 ldw r2,-12(fp) - 148: 00c00074 movhi r3,1 - 14c: 18d09304 addi r3,r3,16972 - 150: 100490fa slli r2,r2,3 - 154: 10c5883a add r2,r2,r3 - 158: 10800104 addi r2,r2,4 - 15c: 11000017 ldw r4,0(r2) - 160: 283ee83a callr r5 -#ifndef NIOS2_EIC_PRESENT -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) -{ - alt_u32 active; - - NIOS2_READ_IPENDING (active); - 164: 0005313a rdctl r2,ipending - 168: e0bffb15 stw r2,-20(fp) - - return active; - 16c: e0bffb17 ldw r2,-20(fp) - mask <<= 1; - i++; - - } while (1); - - active = alt_irq_pending (); - 170: e0bfff15 stw r2,-4(fp) - - } while (active); - 174: e0bfff17 ldw r2,-4(fp) - 178: 1004c03a cmpne r2,r2,zero - 17c: 103fe31e bne r2,zero,10c - 180: 00000706 br 1a0 -#else - alt_irq[i].handler(alt_irq[i].context, i); -#endif - break; - } - mask <<= 1; - 184: e0bffe17 ldw r2,-8(fp) - 188: 1085883a add r2,r2,r2 - 18c: e0bffe15 stw r2,-8(fp) - i++; - 190: e0bffd17 ldw r2,-12(fp) - 194: 10800044 addi r2,r2,1 - 198: e0bffd15 stw r2,-12(fp) - - } while (1); - 19c: 003fde06 br 118 - /* - * Notify the operating system that interrupt processing is complete. - */ - - ALT_OS_INT_EXIT(); -} - 1a0: e037883a mov sp,fp - 1a4: dfc00117 ldw ra,4(sp) - 1a8: df000017 ldw fp,0(sp) - 1ac: dec00204 addi sp,sp,8 - 1b0: f800283a ret - -Disassembly of section .text: - -000001b4 <_start>: -#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) - /* - * Now that the caches are initialized, set up the stack pointer. - * The value provided by the linker is assumed to be correctly aligned. - */ - movhi sp, %hi(__alt_stack_pointer) - 1b4: 06c000f4 movhi sp,3 - ori sp, sp, %lo(__alt_stack_pointer) - 1b8: dec80014 ori sp,sp,8192 - - /* Set up the global pointer. */ - movhi gp, %hi(_gp) - 1bc: 06800074 movhi gp,1 - ori gp, gp, %lo(_gp) - 1c0: d6a83e14 ori gp,gp,41208 - */ -#ifndef ALT_SIM_OPTIMIZE - /* Log that the BSS is about to be cleared. */ - ALT_LOG_PUTS(alt_log_msg_bss) - - movhi r2, %hi(__bss_start) - 1c4: 00800074 movhi r2,1 - ori r2, r2, %lo(__bss_start) - 1c8: 108f3314 ori r2,r2,15564 - - movhi r3, %hi(__bss_end) - 1cc: 00c00074 movhi r3,1 - ori r3, r3, %lo(__bss_end) - 1d0: 18d13714 ori r3,r3,17628 - - beq r2, r3, 1f - 1d4: 10c00326 beq r2,r3,1e4 <_start+0x30> - -0: - stw zero, (r2) - 1d8: 10000015 stw zero,0(r2) - addi r2, r2, 4 - 1dc: 10800104 addi r2,r2,4 - bltu r2, r3, 0b - 1e0: 10fffd36 bltu r2,r3,1d8 <_start+0x24> - * section aren't defined until alt_load() has been called). - */ - mov et, zero -#endif - - call alt_load - 1e4: 000c7dc0 call c7dc - - /* Log that alt_main is about to be called. */ - ALT_LOG_PUTS(alt_log_msg_alt_main) - - /* Call the C entry point. It should never return. */ - call alt_main - 1e8: 000ca1c0 call ca1c - -000001ec : - - /* Wait in infinite loop in case alt_main does return. */ -alt_after_alt_main: - br alt_after_alt_main - 1ec: 003fff06 br 1ec - -000001f0 : -#include -#include "system.h" -#include "LCD.h" -//------------------------------------------------------------------------- -void LCD_Init() -{ - 1f0: defffe04 addi sp,sp,-8 - 1f4: dfc00115 stw ra,4(sp) - 1f8: df000015 stw fp,0(sp) - 1fc: d839883a mov fp,sp - lcd_write_cmd(LCD_16207_0_BASE,0x38); - 200: 00c00134 movhi r3,4 - 204: 18c40c04 addi r3,r3,4144 - 208: 00800e04 movi r2,56 - 20c: 18800035 stwio r2,0(r3) - usleep(2000); - 210: 0101f404 movi r4,2000 - 214: 000cd800 call cd80 - lcd_write_cmd(LCD_16207_0_BASE,0x0C); - 218: 00c00134 movhi r3,4 - 21c: 18c40c04 addi r3,r3,4144 - 220: 00800304 movi r2,12 - 224: 18800035 stwio r2,0(r3) - usleep(2000); - 228: 0101f404 movi r4,2000 - 22c: 000cd800 call cd80 - lcd_write_cmd(LCD_16207_0_BASE,0x01); - 230: 00c00134 movhi r3,4 - 234: 18c40c04 addi r3,r3,4144 - 238: 00800044 movi r2,1 - 23c: 18800035 stwio r2,0(r3) - usleep(2000); - 240: 0101f404 movi r4,2000 - 244: 000cd800 call cd80 - lcd_write_cmd(LCD_16207_0_BASE,0x06); - 248: 00c00134 movhi r3,4 - 24c: 18c40c04 addi r3,r3,4144 - 250: 00800184 movi r2,6 - 254: 18800035 stwio r2,0(r3) - usleep(2000); - 258: 0101f404 movi r4,2000 - 25c: 000cd800 call cd80 - lcd_write_cmd(LCD_16207_0_BASE,0x80); - 260: 00c00134 movhi r3,4 - 264: 18c40c04 addi r3,r3,4144 - 268: 00802004 movi r2,128 - 26c: 18800035 stwio r2,0(r3) - usleep(2000); - 270: 0101f404 movi r4,2000 - 274: 000cd800 call cd80 -} - 278: e037883a mov sp,fp - 27c: dfc00117 ldw ra,4(sp) - 280: df000017 ldw fp,0(sp) - 284: dec00204 addi sp,sp,8 - 288: f800283a ret - -0000028c : -//------------------------------------------------------------------------- -void LCD_Show_Text(const char* Text) -{ - 28c: defffb04 addi sp,sp,-20 - 290: dfc00415 stw ra,16(sp) - 294: df000315 stw fp,12(sp) - 298: dc000215 stw r16,8(sp) - 29c: df000204 addi fp,sp,8 - 2a0: e13fff15 stw r4,-4(fp) - int i; - for(i=0;i - { - lcd_write_data(LCD_16207_0_BASE,Text[i]); - 2ac: e0bffe17 ldw r2,-8(fp) - 2b0: 1007883a mov r3,r2 - 2b4: e0bfff17 ldw r2,-4(fp) - 2b8: 1885883a add r2,r3,r2 - 2bc: 10800003 ldbu r2,0(r2) - 2c0: 10c03fcc andi r3,r2,255 - 2c4: 18c0201c xori r3,r3,128 - 2c8: 18ffe004 addi r3,r3,-128 - 2cc: 00800134 movhi r2,4 - 2d0: 10840e04 addi r2,r2,4152 - 2d4: 10c00035 stwio r3,0(r2) - usleep(2000); - 2d8: 0101f404 movi r4,2000 - 2dc: 000cd800 call cd80 -} -//------------------------------------------------------------------------- -void LCD_Show_Text(const char* Text) -{ - int i; - for(i=0;i - 2f8: 80bfec36 bltu r16,r2,2ac - { - lcd_write_data(LCD_16207_0_BASE,Text[i]); - usleep(2000); - } -} - 2fc: e037883a mov sp,fp - 300: dfc00217 ldw ra,8(sp) - 304: df000117 ldw fp,4(sp) - 308: dc000017 ldw r16,0(sp) - 30c: dec00304 addi sp,sp,12 - 310: f800283a ret - -00000314 : -//------------------------------------------------------------------------- -void LCD_Line2() -{ - 314: defffe04 addi sp,sp,-8 - 318: dfc00115 stw ra,4(sp) - 31c: df000015 stw fp,0(sp) - 320: d839883a mov fp,sp - lcd_write_cmd(LCD_16207_0_BASE,0xC0); - 324: 00c00134 movhi r3,4 - 328: 18c40c04 addi r3,r3,4144 - 32c: 00803004 movi r2,192 - 330: 18800035 stwio r2,0(r3) - usleep(2000); - 334: 0101f404 movi r4,2000 - 338: 000cd800 call cd80 -} - 33c: e037883a mov sp,fp - 340: dfc00117 ldw ra,4(sp) - 344: df000017 ldw fp,0(sp) - 348: dec00204 addi sp,sp,8 - 34c: f800283a ret - -00000350 : -//------------------------------------------------------------------------- -void LCD_Test() -{ - 350: defff604 addi sp,sp,-40 - 354: dfc00915 stw ra,36(sp) - 358: df000815 stw fp,32(sp) - 35c: df000804 addi fp,sp,32 - char Text1[16] = ""; - 360: 00c00074 movhi r3,1 - 364: 18ffa604 addi r3,r3,-360 - 368: 18800017 ldw r2,0(r3) - 36c: e0bff815 stw r2,-32(fp) - 370: 18800117 ldw r2,4(r3) - 374: e0bff915 stw r2,-28(fp) - 378: 18800217 ldw r2,8(r3) - 37c: e0bffa15 stw r2,-24(fp) - 380: 18800317 ldw r2,12(r3) - 384: e0bffb15 stw r2,-20(fp) - char Text2[16] = "Nice to See You!"; - 388: 00c00074 movhi r3,1 - 38c: 18ffab04 addi r3,r3,-340 - 390: 18800017 ldw r2,0(r3) - 394: e0bffc15 stw r2,-16(fp) - 398: 18800117 ldw r2,4(r3) - 39c: e0bffd15 stw r2,-12(fp) - 3a0: 18800217 ldw r2,8(r3) - 3a4: e0bffe15 stw r2,-8(fp) - 3a8: 18800317 ldw r2,12(r3) - 3ac: e0bfff15 stw r2,-4(fp) - // Initial LCD - LCD_Init(); - 3b0: 00001f00 call 1f0 - // Show Text to LCD - LCD_Show_Text(Text1); - 3b4: e13ff804 addi r4,fp,-32 - 3b8: 000028c0 call 28c - // Change Line2 - LCD_Line2(); - 3bc: 00003140 call 314 - // Show Text to LCD - LCD_Show_Text(Text2); - 3c0: e13ffc04 addi r4,fp,-16 - 3c4: 000028c0 call 28c -} - 3c8: e037883a mov sp,fp - 3cc: dfc00117 ldw ra,4(sp) - 3d0: df000017 ldw fp,0(sp) - 3d4: dec00204 addi sp,sp,8 - 3d8: f800283a ret - -000003dc : -#include "sys_debug.h" -#include "sys_prog.h" - -#define ledrs (volatile int *) LEDRS_BASE - -static void init() { - 3dc: defffe04 addi sp,sp,-8 - 3e0: dfc00115 stw ra,4(sp) - 3e4: df000015 stw fp,0(sp) - 3e8: d839883a mov fp,sp - // lcd - lcd_init(); - 3ec: 0001e8c0 call 1e8c - lcd_print("Starting now..."); - 3f0: 01000074 movhi r4,1 - 3f4: 213fb004 addi r4,r4,-320 - 3f8: 0001f240 call 1f24 - - registers_init(); - 3fc: 00029900 call 2990 - memory_init(); - 400: 00024f40 call 24f4 - // hex - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); - 404: 0009883a mov r4,zero - 408: 00013700 call 1370 - 40c: 01000044 movi r4,1 - 410: 00013700 call 1370 - 414: 01000084 movi r4,2 - 418: 00013700 call 1370 - print_block("he", 2, HEX6_7); - 41c: 01000074 movhi r4,1 - 420: 213fb404 addi r4,r4,-304 - 424: 01400084 movi r5,2 - 428: 01800084 movi r6,2 - 42c: 00011e00 call 11e0 - print_block("lo", 2, HEX4_5); - 430: 01000074 movhi r4,1 - 434: 213fb504 addi r4,r4,-300 - 438: 01400084 movi r5,2 - 43c: 01800044 movi r6,1 - 440: 00011e00 call 11e0 - print_block("you1", 4, HEX0_3); - 444: 01000074 movhi r4,1 - 448: 213fb604 addi r4,r4,-296 - 44c: 01400104 movi r5,4 - 450: 000d883a mov r6,zero - 454: 00011e00 call 11e0 - delay10ms(200); - 458: 01003204 movi r4,200 - 45c: 00024780 call 2478 - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); - 460: 0009883a mov r4,zero - 464: 00013700 call 1370 - 468: 01000044 movi r4,1 - 46c: 00013700 call 1370 - 470: 01000084 movi r4,2 - 474: 00013700 call 1370 - - lcd_caret_reset2(); - 478: 0001efc0 call 1efc - lcd_print("Ok!"); - 47c: 01000074 movhi r4,1 - 480: 213fb804 addi r4,r4,-288 - 484: 0001f240 call 1f24 -} - 488: e037883a mov sp,fp - 48c: dfc00117 ldw ra,4(sp) - 490: df000017 ldw fp,0(sp) - 494: dec00204 addi sp,sp,8 - 498: f800283a ret - -0000049c : - -char stack[5]; - -void store_value(){ - 49c: defffb04 addi sp,sp,-20 - 4a0: dfc00415 stw ra,16(sp) - 4a4: df000315 stw fp,12(sp) - 4a8: df000304 addi fp,sp,12 - unsigned int memi = global_registers[Ssw_memi]; - 4ac: 00800074 movhi r2,1 - 4b0: 10908f04 addi r2,r2,16956 - 4b4: 10800283 ldbu r2,10(r2) - 4b8: 10803fcc andi r2,r2,255 - 4bc: 1080201c xori r2,r2,128 - 4c0: 10bfe004 addi r2,r2,-128 - 4c4: e0bffd15 stw r2,-12(fp) - memory_store(memi, Ssw_data); - 4c8: e13ffd17 ldw r4,-12(fp) - 4cc: 014001c4 movi r5,7 - 4d0: 00026080 call 2608 - - { // �f�o�b�N�\�� - char buf[5]; - sprintf(buf, "%02x", (unsigned char)memi); - 4d4: e0bffd17 ldw r2,-12(fp) - 4d8: 11803fcc andi r6,r2,255 - 4dc: e13ffe04 addi r4,fp,-8 - 4e0: 01400074 movhi r5,1 - 4e4: 297fb904 addi r5,r5,-284 - 4e8: 0002b640 call 2b64 - print_block(buf, 2, HEX6_7); - 4ec: e13ffe04 addi r4,fp,-8 - 4f0: 01400084 movi r5,2 - 4f4: 01800084 movi r6,2 - 4f8: 00011e00 call 11e0 - print_block("--", 2, HEX4_5); - 4fc: 01000074 movhi r4,1 - 500: 213fbb04 addi r4,r4,-276 - 504: 01400084 movi r5,2 - 508: 01800044 movi r6,1 - 50c: 00011e00 call 11e0 - sprintf(buf, "%04d", global_registers[Ssw_data]); - 510: 00800074 movhi r2,1 - 514: 10908f04 addi r2,r2,16956 - 518: 108001c3 ldbu r2,7(r2) - 51c: 11803fcc andi r6,r2,255 - 520: 3180201c xori r6,r6,128 - 524: 31bfe004 addi r6,r6,-128 - 528: e13ffe04 addi r4,fp,-8 - 52c: 01400074 movhi r5,1 - 530: 297fbc04 addi r5,r5,-272 - 534: 0002b640 call 2b64 - print_block(buf, 4, HEX0_3); - 538: e13ffe04 addi r4,fp,-8 - 53c: 01400104 movi r5,4 - 540: 000d883a mov r6,zero - 544: 00011e00 call 11e0 - - display_mem((unsigned char)memi, global_registers[Ssw_data]); - 548: e0bffd17 ldw r2,-12(fp) - 54c: 11003fcc andi r4,r2,255 - 550: 00800074 movhi r2,1 - 554: 10908f04 addi r2,r2,16956 - 558: 108001c3 ldbu r2,7(r2) - 55c: 11403fcc andi r5,r2,255 - 560: 2940201c xori r5,r5,128 - 564: 297fe004 addi r5,r5,-128 - 568: 00020000 call 2000 - } -} - 56c: e037883a mov sp,fp - 570: dfc00117 ldw ra,4(sp) - 574: df000017 ldw fp,0(sp) - 578: dec00204 addi sp,sp,8 - 57c: f800283a ret - -00000580 : -void store_inst(){ - 580: defff904 addi sp,sp,-28 - 584: dfc00615 stw ra,24(sp) - 588: df000515 stw fp,20(sp) - 58c: df000504 addi fp,sp,20 - char reg_index; - unsigned int stored_pc; - struct InstRec inst_rec; - - // �K�v�ȏ��̎擾 - inst = global_registers[Ssw_inst]; - 590: 00800074 movhi r2,1 - 594: 10908f04 addi r2,r2,16956 - 598: 10800203 ldbu r2,8(r2) - 59c: e0bffc85 stb r2,-14(fp) - mem_index = global_registers[Ssw_memi]; - 5a0: 00800074 movhi r2,1 - 5a4: 10908f04 addi r2,r2,16956 - 5a8: 10800283 ldbu r2,10(r2) - 5ac: e0bffc45 stb r2,-15(fp) - reg_index = global_registers[Ssw_regi]; - 5b0: 00800074 movhi r2,1 - 5b4: 10908f04 addi r2,r2,16956 - 5b8: 10800243 ldbu r2,9(r2) - 5bc: e0bffc05 stb r2,-16(fp) - inst_rec.inst = (unsigned int)inst; - 5c0: e0bffc83 ldbu r2,-14(fp) - 5c4: 108003cc andi r2,r2,15 - 5c8: 10803fcc andi r2,r2,255 - 5cc: 110003cc andi r4,r2,15 - 5d0: e0fffd17 ldw r3,-12(fp) - 5d4: 00bffc04 movi r2,-16 - 5d8: 1884703a and r2,r3,r2 - 5dc: 1104b03a or r2,r2,r4 - 5e0: e0bffd15 stw r2,-12(fp) - inst_rec.memi = (unsigned int)mem_index; - 5e4: e0bffc43 ldbu r2,-15(fp) - 5e8: 108003cc andi r2,r2,15 - 5ec: 10803fcc andi r2,r2,255 - 5f0: 108003cc andi r2,r2,15 - 5f4: 1008913a slli r4,r2,4 - 5f8: e0fffd17 ldw r3,-12(fp) - 5fc: 00bfc3c4 movi r2,-241 - 600: 1884703a and r2,r3,r2 - 604: 1104b03a or r2,r2,r4 - 608: e0bffd15 stw r2,-12(fp) - inst_rec.regi = (unsigned int)reg_index; - 60c: e0bffc03 ldbu r2,-16(fp) - 610: 108003cc andi r2,r2,15 - 614: 10803fcc andi r2,r2,255 - 618: 108003cc andi r2,r2,15 - 61c: 1008923a slli r4,r2,8 - 620: e0fffd17 ldw r3,-12(fp) - 624: 00bc3fc4 movi r2,-3841 - 628: 1884703a and r2,r3,r2 - 62c: 1104b03a or r2,r2,r4 - 630: e0bffd15 stw r2,-12(fp) - - // �X�g�A���� - stored_pc = (unsigned char)global_registers[Spc]; - 634: 00800074 movhi r2,1 - 638: 10908f04 addi r2,r2,16956 - 63c: 10800043 ldbu r2,1(r2) - 640: 10803fcc andi r2,r2,255 - 644: e0bffb15 stw r2,-20(fp) - inst_memory_store((unsigned int)global_registers[Spc], inst_rec); - 648: 00800074 movhi r2,1 - 64c: 10908f04 addi r2,r2,16956 - 650: 10800043 ldbu r2,1(r2) - 654: 11003fcc andi r4,r2,255 - 658: 2100201c xori r4,r4,128 - 65c: 213fe004 addi r4,r4,-128 - 660: e17ffd17 ldw r5,-12(fp) - 664: 00025700 call 2570 - inc_pc(); - 668: 00027340 call 2734 - { // �f�o�b�N�\�� - char buf[5]; - sprintf(buf, "%04d", inst_rec.inst); - 66c: e0bffd17 ldw r2,-12(fp) - 670: 108003cc andi r2,r2,15 - 674: 11803fcc andi r6,r2,255 - 678: e13ffe04 addi r4,fp,-8 - 67c: 01400074 movhi r5,1 - 680: 297fbc04 addi r5,r5,-272 - 684: 0002b640 call 2b64 - print_block(buf, 4, HEX0_3); - 688: e13ffe04 addi r4,fp,-8 - 68c: 01400104 movi r5,4 - 690: 000d883a mov r6,zero - 694: 00011e00 call 11e0 - sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); - 698: 00800074 movhi r2,1 - 69c: 10908f04 addi r2,r2,16956 - 6a0: 10800043 ldbu r2,1(r2) - 6a4: 11803fcc andi r6,r2,255 - 6a8: e13ffe04 addi r4,fp,-8 - 6ac: 01400074 movhi r5,1 - 6b0: 297fb904 addi r5,r5,-284 - 6b4: 0002b640 call 2b64 - print_block(buf, 2, HEX4_5); - 6b8: e13ffe04 addi r4,fp,-8 - 6bc: 01400084 movi r5,2 - 6c0: 01800044 movi r6,1 - 6c4: 00011e00 call 11e0 - - display_inst(inst_rec, stored_pc); - 6c8: e13ffd17 ldw r4,-12(fp) - 6cc: e17ffb17 ldw r5,-20(fp) - 6d0: 0001f540 call 1f54 - } -} - 6d4: e037883a mov sp,fp - 6d8: dfc00117 ldw ra,4(sp) - 6dc: df000017 ldw fp,0(sp) - 6e0: dec00204 addi sp,sp,8 - 6e4: f800283a ret - -000006e8 : - -void print_change_memory(unsigned int current_memory) { - 6e8: defff804 addi sp,sp,-32 - 6ec: dfc00715 stw ra,28(sp) - 6f0: df000615 stw fp,24(sp) - 6f4: df000604 addi fp,sp,24 - 6f8: e13fff15 stw r4,-4(fp) - char buf[17]; - sprintf(buf, "Current page:%2d", current_memory); - 6fc: e13ffa04 addi r4,fp,-24 - 700: 01400074 movhi r5,1 - 704: 297fbe04 addi r5,r5,-264 - 708: e1bfff17 ldw r6,-4(fp) - 70c: 0002b640 call 2b64 - lcd_caret_reset(); - 710: 0001ed40 call 1ed4 - lcd_print("Change program"); - 714: 01000074 movhi r4,1 - 718: 213fc304 addi r4,r4,-244 - 71c: 0001f240 call 1f24 - lcd_caret_reset2(); - 720: 0001efc0 call 1efc - lcd_print(buf); - 724: e13ffa04 addi r4,fp,-24 - 728: 0001f240 call 1f24 - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); - 72c: 0009883a mov r4,zero - 730: 00013700 call 1370 - 734: 01000044 movi r4,1 - 738: 00013700 call 1370 - 73c: 01000084 movi r4,2 - 740: 00013700 call 1370 -} - 744: e037883a mov sp,fp - 748: dfc00117 ldw ra,4(sp) - 74c: df000017 ldw fp,0(sp) - 750: dec00204 addi sp,sp,8 - 754: f800283a ret - -00000758 : - -static void reset_mem_cancel() { - 758: defffe04 addi sp,sp,-8 - 75c: dfc00115 stw ra,4(sp) - 760: df000015 stw fp,0(sp) - 764: d839883a mov fp,sp - lcd_caret_reset(); - 768: 0001ed40 call 1ed4 - lcd_print("rewrite all 0?"); - 76c: 01000074 movhi r4,1 - 770: 213fc704 addi r4,r4,-228 - 774: 0001f240 call 1f24 - lcd_caret_reset2(); - 778: 0001efc0 call 1efc - lcd_print("push again -> NG"); - 77c: 01000074 movhi r4,1 - 780: 213fcb04 addi r4,r4,-212 - 784: 0001f240 call 1f24 -} - 788: e037883a mov sp,fp - 78c: dfc00117 ldw ra,4(sp) - 790: df000017 ldw fp,0(sp) - 794: dec00204 addi sp,sp,8 - 798: f800283a ret - -0000079c : -static char reset_mem(char confirmed) { - 79c: defffb04 addi sp,sp,-20 - 7a0: dfc00415 stw ra,16(sp) - 7a4: df000315 stw fp,12(sp) - 7a8: df000304 addi fp,sp,12 - 7ac: e13ffe05 stb r4,-8(fp) - if (confirmed == 0) { - 7b0: e0bffe07 ldb r2,-8(fp) - 7b4: 1004c03a cmpne r2,r2,zero - 7b8: 10000b1e bne r2,zero,7e8 - lcd_caret_reset(); - 7bc: 0001ed40 call 1ed4 - lcd_print("rewrite all 0?"); - 7c0: 01000074 movhi r4,1 - 7c4: 213fc704 addi r4,r4,-228 - 7c8: 0001f240 call 1f24 - lcd_caret_reset2(); - 7cc: 0001efc0 call 1efc - lcd_print("push again"); - 7d0: 01000074 movhi r4,1 - 7d4: 213fd004 addi r4,r4,-192 - 7d8: 0001f240 call 1f24 - // �m�F�v�� - return 1; - 7dc: 00800044 movi r2,1 - 7e0: e0bfff15 stw r2,-4(fp) - 7e4: 00001406 br 838 - } else { - int i; - for (i = 0; i < MEM_SIZE; i++){ - 7e8: e03ffd15 stw zero,-12(fp) - 7ec: 00000606 br 808 - memory_store(i,Szero); - 7f0: e13ffd17 ldw r4,-12(fp) - 7f4: 000b883a mov r5,zero - 7f8: 00026080 call 2608 - lcd_print("push again"); - // �m�F�v�� - return 1; - } else { - int i; - for (i = 0; i < MEM_SIZE; i++){ - 7fc: e0bffd17 ldw r2,-12(fp) - 800: 10800044 addi r2,r2,1 - 804: e0bffd15 stw r2,-12(fp) - 808: e0bffd17 ldw r2,-12(fp) - 80c: 10800410 cmplti r2,r2,16 - 810: 103ff71e bne r2,zero,7f0 - memory_store(i,Szero); - } - lcd_caret_reset(); - 814: 0001ed40 call 1ed4 - lcd_print("rewrite all 0?"); - 818: 01000074 movhi r4,1 - 81c: 213fc704 addi r4,r4,-228 - 820: 0001f240 call 1f24 - lcd_caret_reset2(); - 824: 0001efc0 call 1efc - lcd_print("push again -> OK"); - 828: 01000074 movhi r4,1 - 82c: 213fd304 addi r4,r4,-180 - 830: 0001f240 call 1f24 - - // PC���Z�b�g���� - return 0; - 834: e03fff15 stw zero,-4(fp) - 838: e0bfff17 ldw r2,-4(fp) - } -} - 83c: e037883a mov sp,fp - 840: dfc00117 ldw ra,4(sp) - 844: df000017 ldw fp,0(sp) - 848: dec00204 addi sp,sp,8 - 84c: f800283a ret - -00000850 : -static void reset_pc_cancel() { - 850: defffe04 addi sp,sp,-8 - 854: dfc00115 stw ra,4(sp) - 858: df000015 stw fp,0(sp) - 85c: d839883a mov fp,sp - lcd_caret_reset(); - 860: 0001ed40 call 1ed4 - lcd_print("reset pc?"); - 864: 01000074 movhi r4,1 - 868: 213fd804 addi r4,r4,-160 - 86c: 0001f240 call 1f24 - lcd_caret_reset2(); - 870: 0001efc0 call 1efc - lcd_print("push again -> NG"); - 874: 01000074 movhi r4,1 - 878: 213fcb04 addi r4,r4,-212 - 87c: 0001f240 call 1f24 -} - 880: e037883a mov sp,fp - 884: dfc00117 ldw ra,4(sp) - 888: df000017 ldw fp,0(sp) - 88c: dec00204 addi sp,sp,8 - 890: f800283a ret - -00000894 : -static char reset_pc(char confirmed) { - 894: defffc04 addi sp,sp,-16 - 898: dfc00315 stw ra,12(sp) - 89c: df000215 stw fp,8(sp) - 8a0: df000204 addi fp,sp,8 - 8a4: e13ffe05 stb r4,-8(fp) - if (confirmed == 0) { - 8a8: e0bffe07 ldb r2,-8(fp) - 8ac: 1004c03a cmpne r2,r2,zero - 8b0: 10000b1e bne r2,zero,8e0 - lcd_caret_reset(); - 8b4: 0001ed40 call 1ed4 - lcd_print("reset pc?"); - 8b8: 01000074 movhi r4,1 - 8bc: 213fd804 addi r4,r4,-160 - 8c0: 0001f240 call 1f24 - lcd_caret_reset2(); - 8c4: 0001efc0 call 1efc - lcd_print("push again"); - 8c8: 01000074 movhi r4,1 - 8cc: 213fd004 addi r4,r4,-192 - 8d0: 0001f240 call 1f24 - // �m�F�v�� - return 1; - 8d4: 00800044 movi r2,1 - 8d8: e0bfff15 stw r2,-4(fp) - 8dc: 00000c06 br 910 - } else { - global_registers[Spc]=0; - 8e0: 00800074 movhi r2,1 - 8e4: 10908f04 addi r2,r2,16956 - 8e8: 10000045 stb zero,1(r2) - - lcd_caret_reset(); - 8ec: 0001ed40 call 1ed4 - lcd_print("reset pc?"); - 8f0: 01000074 movhi r4,1 - 8f4: 213fd804 addi r4,r4,-160 - 8f8: 0001f240 call 1f24 - lcd_caret_reset2(); - 8fc: 0001efc0 call 1efc - lcd_print("push again -> OK"); - 900: 01000074 movhi r4,1 - 904: 213fd304 addi r4,r4,-180 - 908: 0001f240 call 1f24 - - // PC���Z�b�g���� - return 0; - 90c: e03fff15 stw zero,-4(fp) - 910: e0bfff17 ldw r2,-4(fp) - } -} - 914: e037883a mov sp,fp - 918: dfc00117 ldw ra,4(sp) - 91c: df000017 ldw fp,0(sp) - 920: dec00204 addi sp,sp,8 - 924: f800283a ret - -00000928
: - - -int main() -{ - 928: defffc04 addi sp,sp,-16 - 92c: dfc00315 stw ra,12(sp) - 930: df000215 stw fp,8(sp) - 934: df000204 addi fp,sp,8 - init(); - 938: 00003dc0 call 3dc - - enum RunMode fRun = RUN_STOP; - 93c: e03fff15 stw zero,-4(fp) - char reset_pc_confirmed = 0; - 940: e03ffec5 stb zero,-5(fp) - char reset_mem_confirmed = 0; - 944: e03ffe85 stb zero,-6(fp) - 948: 00000006 br 94c - - while(1) { - // interrupt - in_int(); - 94c: 00014f80 call 14f8 - - // event - // CANCEL - if (global_registers[Ssw_rw] == 0 - 950: 00800074 movhi r2,1 - 954: 10908f04 addi r2,r2,16956 - 958: 10800303 ldbu r2,12(r2) - 95c: 10803fcc andi r2,r2,255 - 960: 1080201c xori r2,r2,128 - 964: 10bfe004 addi r2,r2,-128 - 968: 1005003a cmpeq r2,r2,zero - 96c: 10000e1e bne r2,zero,9a8 - 970: 00800074 movhi r2,1 - 974: 10883e04 addi r2,r2,8440 - 978: 10800003 ldbu r2,0(r2) - 97c: 10803fcc andi r2,r2,255 - 980: 1080008c andi r2,r2,2 - 984: 1005003a cmpeq r2,r2,zero - 988: 10000c1e bne r2,zero,9bc - 98c: 00800074 movhi r2,1 - 990: 10883e04 addi r2,r2,8440 - 994: 10800003 ldbu r2,0(r2) - 998: 10803fcc andi r2,r2,255 - 99c: 1080010c andi r2,r2,4 - 9a0: 1004c03a cmpne r2,r2,zero - 9a4: 1000051e bne r2,zero,9bc - || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_VALSTR))) { - if (reset_mem_confirmed == 1) { - 9a8: e0bffe87 ldb r2,-6(fp) - 9ac: 10800058 cmpnei r2,r2,1 - 9b0: 1000021e bne r2,zero,9bc - reset_mem_confirmed = 0; //�m�F�L�����Z�� - 9b4: e03ffe85 stb zero,-6(fp) - reset_mem_cancel(); - 9b8: 00007580 call 758 - } - } - if (global_registers[Ssw_rw] == 0 - 9bc: 00800074 movhi r2,1 - 9c0: 10908f04 addi r2,r2,16956 - 9c4: 10800303 ldbu r2,12(r2) - 9c8: 10803fcc andi r2,r2,255 - 9cc: 1080201c xori r2,r2,128 - 9d0: 10bfe004 addi r2,r2,-128 - 9d4: 1005003a cmpeq r2,r2,zero - 9d8: 10000e1e bne r2,zero,a14 - 9dc: 00800074 movhi r2,1 - 9e0: 10883e04 addi r2,r2,8440 - 9e4: 10800003 ldbu r2,0(r2) - 9e8: 10803fcc andi r2,r2,255 - 9ec: 1080008c andi r2,r2,2 - 9f0: 1005003a cmpeq r2,r2,zero - 9f4: 10000c1e bne r2,zero,a28 - 9f8: 00800074 movhi r2,1 - 9fc: 10883e04 addi r2,r2,8440 - a00: 10800003 ldbu r2,0(r2) - a04: 10803fcc andi r2,r2,255 - a08: 1080020c andi r2,r2,8 - a0c: 1004c03a cmpne r2,r2,zero - a10: 1000051e bne r2,zero,a28 - || ((PUSH_EVENT & PUSH_ANY) && !(PUSH_EVENT & PUSH_INSSTR))) { - if (reset_pc_confirmed == 1) { - a14: e0bffec7 ldb r2,-5(fp) - a18: 10800058 cmpnei r2,r2,1 - a1c: 1000021e bne r2,zero,a28 - reset_pc_confirmed = 0; //�m�F�L�����Z�� - a20: e03ffec5 stb zero,-5(fp) - reset_pc_cancel(); - a24: 00008500 call 850 - } - } - // CONFIRM - if (PUSH_EVENT & PUSH_VALSTR) { - a28: 00800074 movhi r2,1 - a2c: 10883e04 addi r2,r2,8440 - a30: 10800003 ldbu r2,0(r2) - a34: 10803fcc andi r2,r2,255 - a38: 1080010c andi r2,r2,4 - a3c: 1005003a cmpeq r2,r2,zero - a40: 1000161e bne r2,zero,a9c - // �l�̃X�g�A - if (global_registers[Ssw_rw] == 1) { - a44: 00800074 movhi r2,1 - a48: 10908f04 addi r2,r2,16956 - a4c: 10800303 ldbu r2,12(r2) - a50: 10803fcc andi r2,r2,255 - a54: 1080201c xori r2,r2,128 - a58: 10bfe004 addi r2,r2,-128 - a5c: 10800058 cmpnei r2,r2,1 - a60: 10000d1e bne r2,zero,a98 - //�폜 - char res = reset_mem(reset_mem_confirmed);//���m�F�̏��F - a64: e13ffe87 ldb r4,-6(fp) - a68: 000079c0 call 79c - a6c: e0bffe45 stb r2,-7(fp) - if (1 == res) reset_mem_confirmed = 1; //���m�F - a70: e0bffe47 ldb r2,-7(fp) - a74: 10800058 cmpnei r2,r2,1 - a78: 1000021e bne r2,zero,a84 - a7c: 00800044 movi r2,1 - a80: e0bffe85 stb r2,-6(fp) - if (0 == res) reset_mem_confirmed = 0; //���Z�b�g�̊m�F - a84: e0bffe47 ldb r2,-7(fp) - a88: 1004c03a cmpne r2,r2,zero - a8c: 1000031e bne r2,zero,a9c - a90: e03ffe85 stb zero,-6(fp) - a94: 00000106 br a9c - } else { - store_value(); - a98: 000049c0 call 49c - } - } - if (PUSH_EVENT & PUSH_INSSTR) { - a9c: 00800074 movhi r2,1 - aa0: 10883e04 addi r2,r2,8440 - aa4: 10800003 ldbu r2,0(r2) - aa8: 10803fcc andi r2,r2,255 - aac: 1080020c andi r2,r2,8 - ab0: 1005003a cmpeq r2,r2,zero - ab4: 1000161e bne r2,zero,b10 - // ���߂̃X�g�A - if (global_registers[Ssw_rw] == 1) { - ab8: 00800074 movhi r2,1 - abc: 10908f04 addi r2,r2,16956 - ac0: 10800303 ldbu r2,12(r2) - ac4: 10803fcc andi r2,r2,255 - ac8: 1080201c xori r2,r2,128 - acc: 10bfe004 addi r2,r2,-128 - ad0: 10800058 cmpnei r2,r2,1 - ad4: 10000d1e bne r2,zero,b0c - //PC�̃��Z�b�g - char res = reset_pc(reset_pc_confirmed);//���m�F�̏��F - ad8: e13ffec7 ldb r4,-5(fp) - adc: 00008940 call 894 - ae0: e0bffe05 stb r2,-8(fp) - if (1 == res) reset_pc_confirmed = 1; //���m�F - ae4: e0bffe07 ldb r2,-8(fp) - ae8: 10800058 cmpnei r2,r2,1 - aec: 1000021e bne r2,zero,af8 - af0: 00800044 movi r2,1 - af4: e0bffec5 stb r2,-5(fp) - if (0 == res) reset_pc_confirmed = 0; //���Z�b�g�̊m�F - af8: e0bffe07 ldb r2,-8(fp) - afc: 1004c03a cmpne r2,r2,zero - b00: 1000031e bne r2,zero,b10 - b04: e03ffec5 stb zero,-5(fp) - b08: 00000106 br b10 - } else { - store_inst(); - b0c: 00005800 call 580 - } - } - // RUN - if (PUSH_EVENT & PUSH_RUN) { - b10: 00800074 movhi r2,1 - b14: 10883e04 addi r2,r2,8440 - b18: 10800003 ldbu r2,0(r2) - b1c: 10803fcc andi r2,r2,255 - b20: 1080040c andi r2,r2,16 - b24: 1005003a cmpeq r2,r2,zero - b28: 10001a1e bne r2,zero,b94 - if (global_current_memory != (unsigned int)global_registers[Ssw_psel]) { - b2c: 00800074 movhi r2,1 - b30: 10908f04 addi r2,r2,16956 - b34: 108002c3 ldbu r2,11(r2) - b38: 10c03fcc andi r3,r2,255 - b3c: 18c0201c xori r3,r3,128 - b40: 18ffe004 addi r3,r3,-128 - b44: 00800074 movhi r2,1 - b48: 108f3704 addi r2,r2,15580 - b4c: 10800017 ldw r2,0(r2) - b50: 18800e26 beq r3,r2,b8c - global_current_memory = (unsigned int)global_registers[Ssw_psel]; - b54: 00800074 movhi r2,1 - b58: 10908f04 addi r2,r2,16956 - b5c: 108002c3 ldbu r2,11(r2) - b60: 10c03fcc andi r3,r2,255 - b64: 18c0201c xori r3,r3,128 - b68: 18ffe004 addi r3,r3,-128 - b6c: 00800074 movhi r2,1 - b70: 108f3704 addi r2,r2,15580 - b74: 10c00015 stw r3,0(r2) - print_change_memory(global_current_memory); - b78: 00800074 movhi r2,1 - b7c: 108f3704 addi r2,r2,15580 - b80: 11000017 ldw r4,0(r2) - b84: 00006e80 call 6e8 - b88: 00000206 br b94 - } - else { - // �v���O�����������ݒ� - fRun = RUN_INIT; - b8c: 00800044 movi r2,1 - b90: e0bfff15 stw r2,-4(fp) - } - } - if (fRun != RUN_STOP) { - b94: e0bfff17 ldw r2,-4(fp) - b98: 1005003a cmpeq r2,r2,zero - b9c: 103f6b1e bne r2,zero,94c - // �v���O�������s���荞�� & ���s���[�h�X�V - fRun = run_proc(fRun); - ba0: e13fff17 ldw r4,-4(fp) - ba4: 00028400 call 2840 - ba8: e0bfff15 stw r2,-4(fp) - } - } - bac: 003f6706 br 94c - -00000bb0 : - */ - -#include "hex_encoder.h" -#include - -void encodeNumHex(int hex_i, int num) { - bb0: defffc04 addi sp,sp,-16 - bb4: df000315 stw fp,12(sp) - bb8: df000304 addi fp,sp,12 - bbc: e13ffe15 stw r4,-8(fp) - bc0: e17fff15 stw r5,-4(fp) - char encoded = 0; - bc4: e03ffd05 stb zero,-12(fp) - switch (num) { - bc8: e0bfff17 ldw r2,-4(fp) - bcc: 108002a8 cmpgeui r2,r2,10 - bd0: 10002f1e bne r2,zero,c90 - bd4: e0bfff17 ldw r2,-4(fp) - bd8: 1085883a add r2,r2,r2 - bdc: 1087883a add r3,r2,r2 - be0: 00800034 movhi r2,0 - be4: 1082fd04 addi r2,r2,3060 - be8: 1885883a add r2,r3,r2 - bec: 10800017 ldw r2,0(r2) - bf0: 1000683a jmp r2 - bf4: 00000c1c xori zero,zero,48 - bf8: 00000c28 cmpgeui zero,zero,48 - bfc: 00000c34 movhi zero,48 - c00: 00000c40 call c4 <__flash_exceptions_start+0xa4> - c04: 00000c4c andi zero,zero,49 - c08: 00000c58 cmpnei zero,zero,49 - c0c: 00000c64 muli zero,zero,49 - c10: 00000c70 cmpltui zero,zero,49 - c14: 00000c7c xorhi zero,zero,49 - c18: 00000c84 movi zero,50 - case 0: - encoded = (char)0x40; // 100 0000 - c1c: 00801004 movi r2,64 - c20: e0bffd05 stb r2,-12(fp) - break; - c24: 00001b06 br c94 - case 1: - encoded = (char)0xF9; // 111 1001 - c28: 00bffe44 movi r2,-7 - c2c: e0bffd05 stb r2,-12(fp) - break; - c30: 00001806 br c94 - case 2: - encoded = (char)0x24; // 010 0100 - c34: 00800904 movi r2,36 - c38: e0bffd05 stb r2,-12(fp) - break; - c3c: 00001506 br c94 - case 3: - encoded = (char)0x30; // 011 0000 - c40: 00800c04 movi r2,48 - c44: e0bffd05 stb r2,-12(fp) - break; - c48: 00001206 br c94 - case 4: - encoded = (char)0x19; // 001 1001 - c4c: 00800644 movi r2,25 - c50: e0bffd05 stb r2,-12(fp) - break; - c54: 00000f06 br c94 - case 5: - encoded = (char)0x12; // 001 0010 - c58: 00800484 movi r2,18 - c5c: e0bffd05 stb r2,-12(fp) - break; - c60: 00000c06 br c94 - case 6: - encoded = (char)0x02; // 000 0010 - c64: 00800084 movi r2,2 - c68: e0bffd05 stb r2,-12(fp) - break; - c6c: 00000906 br c94 - case 7: - encoded = (char)0x58; // 101 1000 - c70: 00801604 movi r2,88 - c74: e0bffd05 stb r2,-12(fp) - break; - c78: 00000606 br c94 - case 8: - encoded = (char)0x00; // 000 0000 - c7c: e03ffd05 stb zero,-12(fp) - break; - c80: 00000406 br c94 - case 9: - encoded = (char)0x10; // 001 0000 - c84: 00800404 movi r2,16 - c88: e0bffd05 stb r2,-12(fp) - break; - c8c: 00000106 br c94 - default: - encoded = 0; - c90: e03ffd05 stb zero,-12(fp) - break; - } - - switch (hex_i) { - c94: e0bffe17 ldw r2,-8(fp) - c98: 10800228 cmpgeui r2,r2,8 - c9c: 1000371e bne r2,zero,d7c - ca0: e0bffe17 ldw r2,-8(fp) - ca4: 1085883a add r2,r2,r2 - ca8: 1087883a add r3,r2,r2 - cac: 00800034 movhi r2,0 - cb0: 10833004 addi r2,r2,3264 - cb4: 1885883a add r2,r3,r2 - cb8: 10800017 ldw r2,0(r2) - cbc: 1000683a jmp r2 - cc0: 00000ce0 cmpeqi zero,zero,51 - cc4: 00000cf4 movhi zero,51 - cc8: 00000d08 cmpgei zero,zero,52 - ccc: 00000d1c xori zero,zero,52 - cd0: 00000d30 cmpltui zero,zero,52 - cd4: 00000d44 movi zero,53 - cd8: 00000d58 cmpnei zero,zero,53 - cdc: 00000d6c andhi zero,zero,53 - case 0: - *hex0 = encoded; - ce0: 00c00134 movhi r3,4 - ce4: 18c42c04 addi r3,r3,4272 - ce8: e0bffd03 ldbu r2,-12(fp) - cec: 18800005 stb r2,0(r3) - break; - cf0: 00002206 br d7c - case 1: - *hex1 = encoded; - cf4: 00c00134 movhi r3,4 - cf8: 18c42804 addi r3,r3,4256 - cfc: e0bffd03 ldbu r2,-12(fp) - d00: 18800005 stb r2,0(r3) - break; - d04: 00001d06 br d7c - case 2: - *hex2 = encoded; - d08: 00c00134 movhi r3,4 - d0c: 18c42404 addi r3,r3,4240 - d10: e0bffd03 ldbu r2,-12(fp) - d14: 18800005 stb r2,0(r3) - break; - d18: 00001806 br d7c - case 3: - *hex3 = encoded; - d1c: 00c00134 movhi r3,4 - d20: 18c42004 addi r3,r3,4224 - d24: e0bffd03 ldbu r2,-12(fp) - d28: 18800005 stb r2,0(r3) - break; - d2c: 00001306 br d7c - case 4: - *hex4 = encoded; - d30: 00c00134 movhi r3,4 - d34: 18c41c04 addi r3,r3,4208 - d38: e0bffd03 ldbu r2,-12(fp) - d3c: 18800005 stb r2,0(r3) - break; - d40: 00000e06 br d7c - case 5: - *hex5 = encoded; - d44: 00c00134 movhi r3,4 - d48: 18c41804 addi r3,r3,4192 - d4c: e0bffd03 ldbu r2,-12(fp) - d50: 18800005 stb r2,0(r3) - break; - d54: 00000906 br d7c - case 6: - *hex6 = encoded; - d58: 00c00134 movhi r3,4 - d5c: 18c41404 addi r3,r3,4176 - d60: e0bffd03 ldbu r2,-12(fp) - d64: 18800005 stb r2,0(r3) - break; - d68: 00000406 br d7c - case 7: - *hex7 = encoded; - d6c: 00c00134 movhi r3,4 - d70: 18c41004 addi r3,r3,4160 - d74: e0bffd03 ldbu r2,-12(fp) - d78: 18800005 stb r2,0(r3) - break; - default: - break; - } -} - d7c: e037883a mov sp,fp - d80: df000017 ldw fp,0(sp) - d84: dec00104 addi sp,sp,4 - d88: f800283a ret - -00000d8c : - -void encodeLatHex(int hex_i, char c) { - d8c: defffa04 addi sp,sp,-24 - d90: dfc00515 stw ra,20(sp) - d94: df000415 stw fp,16(sp) - d98: df000404 addi fp,sp,16 - d9c: e13ffd15 stw r4,-12(fp) - da0: e17ffe05 stb r5,-8(fp) - char encoded = 0; - da4: e03ffc05 stb zero,-16(fp) - - if (isdigit(c)) { - da8: e0bffe07 ldb r2,-8(fp) - dac: 1007883a mov r3,r2 - db0: 00800074 movhi r2,1 - db4: 10883f04 addi r2,r2,8444 - db8: 10800017 ldw r2,0(r2) - dbc: 1885883a add r2,r3,r2 - dc0: 10800003 ldbu r2,0(r2) - dc4: 10803fcc andi r2,r2,255 - dc8: 1080010c andi r2,r2,4 - dcc: 1005003a cmpeq r2,r2,zero - dd0: 1000051e bne r2,zero,de8 - encodeNumHex(hex_i, c-'0'); - dd4: e0bffe07 ldb r2,-8(fp) - dd8: 117ff404 addi r5,r2,-48 - ddc: e13ffd17 ldw r4,-12(fp) - de0: 0000bb00 call bb0 - return; - de4: 0000f906 br 11cc - } - - switch (c) { - de8: e0bffe07 ldb r2,-8(fp) - dec: 10bff804 addi r2,r2,-32 - df0: e0bfff15 stw r2,-4(fp) - df4: e0ffff17 ldw r3,-4(fp) - df8: 188016e8 cmpgeui r2,r3,91 - dfc: 1000b81e bne r2,zero,10e0 - e00: e13fff17 ldw r4,-4(fp) - e04: e13fff17 ldw r4,-4(fp) - e08: 2105883a add r2,r4,r4 - e0c: 1087883a add r3,r2,r2 - e10: 00800034 movhi r2,0 - e14: 10838904 addi r2,r2,3620 - e18: 1885883a add r2,r3,r2 - e1c: 10800017 ldw r2,0(r2) - e20: 1000683a jmp r2 - e24: 00000f90 cmplti zero,zero,62 - e28: 000010e0 cmpeqi zero,zero,67 - e2c: 000010e0 cmpeqi zero,zero,67 - e30: 000010e0 cmpeqi zero,zero,67 - e34: 000010e0 cmpeqi zero,zero,67 - e38: 000010e0 cmpeqi zero,zero,67 - e3c: 000010e0 cmpeqi zero,zero,67 - e40: 000010e0 cmpeqi zero,zero,67 - e44: 000010e0 cmpeqi zero,zero,67 - e48: 000010e0 cmpeqi zero,zero,67 - e4c: 000010e0 cmpeqi zero,zero,67 - e50: 000010e0 cmpeqi zero,zero,67 - e54: 000010e0 cmpeqi zero,zero,67 - e58: 00000f9c xori zero,zero,62 - e5c: 000010e0 cmpeqi zero,zero,67 - e60: 000010e0 cmpeqi zero,zero,67 - e64: 000010e0 cmpeqi zero,zero,67 - e68: 000010e0 cmpeqi zero,zero,67 - e6c: 000010e0 cmpeqi zero,zero,67 - e70: 000010e0 cmpeqi zero,zero,67 - e74: 000010e0 cmpeqi zero,zero,67 - e78: 000010e0 cmpeqi zero,zero,67 - e7c: 000010e0 cmpeqi zero,zero,67 - e80: 000010e0 cmpeqi zero,zero,67 - e84: 000010e0 cmpeqi zero,zero,67 - e88: 000010e0 cmpeqi zero,zero,67 - e8c: 000010e0 cmpeqi zero,zero,67 - e90: 000010e0 cmpeqi zero,zero,67 - e94: 000010e0 cmpeqi zero,zero,67 - e98: 000010e0 cmpeqi zero,zero,67 - e9c: 000010e0 cmpeqi zero,zero,67 - ea0: 000010e0 cmpeqi zero,zero,67 - ea4: 000010e0 cmpeqi zero,zero,67 - ea8: 000010e0 cmpeqi zero,zero,67 - eac: 000010e0 cmpeqi zero,zero,67 - eb0: 000010e0 cmpeqi zero,zero,67 - eb4: 000010e0 cmpeqi zero,zero,67 - eb8: 000010e0 cmpeqi zero,zero,67 - ebc: 000010e0 cmpeqi zero,zero,67 - ec0: 000010e0 cmpeqi zero,zero,67 - ec4: 000010e0 cmpeqi zero,zero,67 - ec8: 000010e0 cmpeqi zero,zero,67 - ecc: 000010e0 cmpeqi zero,zero,67 - ed0: 000010e0 cmpeqi zero,zero,67 - ed4: 000010e0 cmpeqi zero,zero,67 - ed8: 000010e0 cmpeqi zero,zero,67 - edc: 000010e0 cmpeqi zero,zero,67 - ee0: 000010e0 cmpeqi zero,zero,67 - ee4: 000010e0 cmpeqi zero,zero,67 - ee8: 000010e0 cmpeqi zero,zero,67 - eec: 000010e0 cmpeqi zero,zero,67 - ef0: 000010e0 cmpeqi zero,zero,67 - ef4: 000010e0 cmpeqi zero,zero,67 - ef8: 000010e0 cmpeqi zero,zero,67 - efc: 000010e0 cmpeqi zero,zero,67 - f00: 000010e0 cmpeqi zero,zero,67 - f04: 000010e0 cmpeqi zero,zero,67 - f08: 000010e0 cmpeqi zero,zero,67 - f0c: 000010e0 cmpeqi zero,zero,67 - f10: 000010e0 cmpeqi zero,zero,67 - f14: 000010e0 cmpeqi zero,zero,67 - f18: 000010e0 cmpeqi zero,zero,67 - f1c: 000010e0 cmpeqi zero,zero,67 - f20: 000010e0 cmpeqi zero,zero,67 - f24: 000010e0 cmpeqi zero,zero,67 - f28: 00000fa8 cmpgeui zero,zero,62 - f2c: 00000fb4 movhi zero,62 - f30: 00000fc0 call fc - f34: 00000fcc andi zero,zero,63 - f38: 00000fd8 cmpnei zero,zero,63 - f3c: 00000fe4 muli zero,zero,63 - f40: 00000ff0 cmpltui zero,zero,63 - f44: 00000ffc xorhi zero,zero,63 - f48: 00001008 cmpgei zero,zero,64 - f4c: 00001014 movui zero,64 - f50: 00001020 cmpeqi zero,zero,64 - f54: 0000102c andhi zero,zero,64 - f58: 00001038 rdprs zero,zero,64 - f5c: 00001044 movi zero,65 - f60: 00001050 cmplti zero,zero,65 - f64: 0000105c xori zero,zero,65 - f68: 00001068 cmpgeui zero,zero,65 - f6c: 00001074 movhi zero,65 - f70: 00001080 call 108 - f74: 0000108c andi zero,zero,66 - f78: 00001098 cmpnei zero,zero,66 - f7c: 000010a4 muli zero,zero,66 - f80: 000010b0 cmpltui zero,zero,66 - f84: 000010bc xorhi zero,zero,66 - f88: 000010c8 cmpgei zero,zero,67 - f8c: 000010d4 movui zero,67 - case ' ': - encoded = (char)0xFF; // 111 1111 - f90: 00bfffc4 movi r2,-1 - f94: e0bffc05 stb r2,-16(fp) - break; - f98: 00005206 br 10e4 - case '-': - encoded = (char)0x3F; // 011 1111 - f9c: 00800fc4 movi r2,63 - fa0: e0bffc05 stb r2,-16(fp) - break; - fa4: 00004f06 br 10e4 - case 'a': - encoded = (char)0x08; // 000 1000 - fa8: 00800204 movi r2,8 - fac: e0bffc05 stb r2,-16(fp) - break; - fb0: 00004c06 br 10e4 - case 'b': - encoded = (char)0x03; // 000 0011 - fb4: 008000c4 movi r2,3 - fb8: e0bffc05 stb r2,-16(fp) - break; - fbc: 00004906 br 10e4 - case 'c': - encoded = (char)0x27; // 010 0111 - fc0: 008009c4 movi r2,39 - fc4: e0bffc05 stb r2,-16(fp) - break; - fc8: 00004606 br 10e4 - case 'd': - encoded = (char)0x21; // 010 0001 - fcc: 00800844 movi r2,33 - fd0: e0bffc05 stb r2,-16(fp) - break; - fd4: 00004306 br 10e4 - case 'e': - encoded = (char)0x06; // 000 0110 - fd8: 00800184 movi r2,6 - fdc: e0bffc05 stb r2,-16(fp) - break; - fe0: 00004006 br 10e4 - case 'f': - encoded = (char)0x0E; // 000 1110 - fe4: 00800384 movi r2,14 - fe8: e0bffc05 stb r2,-16(fp) - break; - fec: 00003d06 br 10e4 - case 'g': - encoded = (char)0x42; // 100 0010 - ff0: 00801084 movi r2,66 - ff4: e0bffc05 stb r2,-16(fp) - break; - ff8: 00003a06 br 10e4 - case 'h': - encoded = (char)0x0B; // 000 1011 - ffc: 008002c4 movi r2,11 - 1000: e0bffc05 stb r2,-16(fp) - break; - 1004: 00003706 br 10e4 - case 'i': - encoded = (char)0xFB; // 111 1011 - 1008: 00bffec4 movi r2,-5 - 100c: e0bffc05 stb r2,-16(fp) - break; - 1010: 00003406 br 10e4 - case 'j': - encoded = (char)0x61; // 110 0001 - 1014: 00801844 movi r2,97 - 1018: e0bffc05 stb r2,-16(fp) - break; - 101c: 00003106 br 10e4 - case 'k': - encoded = (char)0x0A; // 000 1010 - 1020: 00800284 movi r2,10 - 1024: e0bffc05 stb r2,-16(fp) - break; - 1028: 00002e06 br 10e4 - case 'l': - encoded = (char)0x47; // 100 0111 - 102c: 008011c4 movi r2,71 - 1030: e0bffc05 stb r2,-16(fp) - break; - 1034: 00002b06 br 10e4 - case 'm': - encoded = (char)0x48; // 100 1000 - 1038: 00801204 movi r2,72 - 103c: e0bffc05 stb r2,-16(fp) - break; - 1040: 00002806 br 10e4 - case 'n': - encoded = (char)0x2B; // 010 1011 - 1044: 00800ac4 movi r2,43 - 1048: e0bffc05 stb r2,-16(fp) - break; - 104c: 00002506 br 10e4 - case 'o': - encoded = (char)0x23; // 010 0011 - 1050: 008008c4 movi r2,35 - 1054: e0bffc05 stb r2,-16(fp) - break; - 1058: 00002206 br 10e4 - case 'p': - encoded = (char)0x0C; // 000 1100 - 105c: 00800304 movi r2,12 - 1060: e0bffc05 stb r2,-16(fp) - break; - 1064: 00001f06 br 10e4 - case 'q': - encoded = (char)0x04; // 000 0100 - 1068: 00800104 movi r2,4 - 106c: e0bffc05 stb r2,-16(fp) - break; - 1070: 00001c06 br 10e4 - case 'r': - encoded = (char)0x2F; // 010 1111 - 1074: 00800bc4 movi r2,47 - 1078: e0bffc05 stb r2,-16(fp) - break; - 107c: 00001906 br 10e4 - case 's': - encoded = (char)0x13; // 001 0011 - 1080: 008004c4 movi r2,19 - 1084: e0bffc05 stb r2,-16(fp) - break; - 1088: 00001606 br 10e4 - case 't': - encoded = (char)0x07; // 000 0111 - 108c: 008001c4 movi r2,7 - 1090: e0bffc05 stb r2,-16(fp) - break; - 1094: 00001306 br 10e4 - case 'u': - encoded = (char)0x63; // 110 0011 - 1098: 008018c4 movi r2,99 - 109c: e0bffc05 stb r2,-16(fp) - break; - 10a0: 00001006 br 10e4 - case 'v': - encoded = (char)0x41; // 100 0001 - 10a4: 00801044 movi r2,65 - 10a8: e0bffc05 stb r2,-16(fp) - break; - 10ac: 00000d06 br 10e4 - case 'w': - encoded = (char)0x01; // 000 0001 - 10b0: 00800044 movi r2,1 - 10b4: e0bffc05 stb r2,-16(fp) - break; - 10b8: 00000a06 br 10e4 - case 'x': - encoded = (char)0x09; // 000 1001 - 10bc: 00800244 movi r2,9 - 10c0: e0bffc05 stb r2,-16(fp) - break; - 10c4: 00000706 br 10e4 - case 'y': - encoded = (char)0x11; // 001 0001 - 10c8: 00800444 movi r2,17 - 10cc: e0bffc05 stb r2,-16(fp) - break; - 10d0: 00000406 br 10e4 - case 'z': - encoded = (char)0x64; // 110 0100 - 10d4: 00801904 movi r2,100 - 10d8: e0bffc05 stb r2,-16(fp) - break; - 10dc: 00000106 br 10e4 - default: - encoded = 0; - 10e0: e03ffc05 stb zero,-16(fp) - break; - } - - switch (hex_i) { - 10e4: e0bffd17 ldw r2,-12(fp) - 10e8: 10800228 cmpgeui r2,r2,8 - 10ec: 1000371e bne r2,zero,11cc - 10f0: e0bffd17 ldw r2,-12(fp) - 10f4: 1085883a add r2,r2,r2 - 10f8: 1087883a add r3,r2,r2 - 10fc: 00800034 movhi r2,0 - 1100: 10844404 addi r2,r2,4368 - 1104: 1885883a add r2,r3,r2 - 1108: 10800017 ldw r2,0(r2) - 110c: 1000683a jmp r2 - 1110: 00001130 cmpltui zero,zero,68 - 1114: 00001144 movi zero,69 - 1118: 00001158 cmpnei zero,zero,69 - 111c: 0000116c andhi zero,zero,69 - 1120: 00001180 call 118 - 1124: 00001194 movui zero,70 - 1128: 000011a8 cmpgeui zero,zero,70 - 112c: 000011bc xorhi zero,zero,70 - case 0: - *hex0 = encoded; - 1130: 00c00134 movhi r3,4 - 1134: 18c42c04 addi r3,r3,4272 - 1138: e0bffc03 ldbu r2,-16(fp) - 113c: 18800005 stb r2,0(r3) - break; - 1140: 00002206 br 11cc - case 1: - *hex1 = encoded; - 1144: 00c00134 movhi r3,4 - 1148: 18c42804 addi r3,r3,4256 - 114c: e0bffc03 ldbu r2,-16(fp) - 1150: 18800005 stb r2,0(r3) - break; - 1154: 00001d06 br 11cc - case 2: - *hex2 = encoded; - 1158: 00c00134 movhi r3,4 - 115c: 18c42404 addi r3,r3,4240 - 1160: e0bffc03 ldbu r2,-16(fp) - 1164: 18800005 stb r2,0(r3) - break; - 1168: 00001806 br 11cc - case 3: - *hex3 = encoded; - 116c: 00c00134 movhi r3,4 - 1170: 18c42004 addi r3,r3,4224 - 1174: e0bffc03 ldbu r2,-16(fp) - 1178: 18800005 stb r2,0(r3) - break; - 117c: 00001306 br 11cc - case 4: - *hex4 = encoded; - 1180: 00c00134 movhi r3,4 - 1184: 18c41c04 addi r3,r3,4208 - 1188: e0bffc03 ldbu r2,-16(fp) - 118c: 18800005 stb r2,0(r3) - break; - 1190: 00000e06 br 11cc - case 5: - *hex5 = encoded; - 1194: 00c00134 movhi r3,4 - 1198: 18c41804 addi r3,r3,4192 - 119c: e0bffc03 ldbu r2,-16(fp) - 11a0: 18800005 stb r2,0(r3) - break; - 11a4: 00000906 br 11cc - case 6: - *hex6 = encoded; - 11a8: 00c00134 movhi r3,4 - 11ac: 18c41404 addi r3,r3,4176 - 11b0: e0bffc03 ldbu r2,-16(fp) - 11b4: 18800005 stb r2,0(r3) - break; - 11b8: 00000406 br 11cc - case 7: - *hex7 = encoded; - 11bc: 00c00134 movhi r3,4 - 11c0: 18c41004 addi r3,r3,4160 - 11c4: e0bffc03 ldbu r2,-16(fp) - 11c8: 18800005 stb r2,0(r3) - break; - default: - break; - } -} - 11cc: e037883a mov sp,fp - 11d0: dfc00117 ldw ra,4(sp) - 11d4: df000017 ldw fp,0(sp) - 11d8: dec00204 addi sp,sp,8 - 11dc: f800283a ret - -000011e0 : - */ -#include "hex_out.h" -#include "hex_encoder.h" -#include "sys_except.h" - -void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { - 11e0: defffa04 addi sp,sp,-24 - 11e4: dfc00515 stw ra,20(sp) - 11e8: df000415 stw fp,16(sp) - 11ec: df000404 addi fp,sp,16 - 11f0: e13ffd15 stw r4,-12(fp) - 11f4: e17ffe15 stw r5,-8(fp) - 11f8: e1bfff15 stw r6,-4(fp) - int i; - if (block_i == HEX0_3) { - 11fc: e0bfff17 ldw r2,-4(fp) - 1200: 1004c03a cmpne r2,r2,zero - 1204: 10001a1e bne r2,zero,1270 - if (size > 4) panic(); - 1208: e0bffe17 ldw r2,-8(fp) - 120c: 10800170 cmpltui r2,r2,5 - 1210: 1000011e bne r2,zero,1218 - 1214: 00024b40 call 24b4 - for (i = 0; i < size; i++) { - 1218: e03ffc15 stw zero,-16(fp) - 121c: 00001006 br 1260 - encodeLatHex(i,str[size-1-i]); - 1220: e0fffc17 ldw r3,-16(fp) - 1224: e0bffe17 ldw r2,-8(fp) - 1228: 10c5c83a sub r2,r2,r3 - 122c: 1007883a mov r3,r2 - 1230: e0bffd17 ldw r2,-12(fp) - 1234: 1885883a add r2,r3,r2 - 1238: 10bfffc4 addi r2,r2,-1 - 123c: 10800003 ldbu r2,0(r2) - 1240: 11403fcc andi r5,r2,255 - 1244: 2940201c xori r5,r5,128 - 1248: 297fe004 addi r5,r5,-128 - 124c: e13ffc17 ldw r4,-16(fp) - 1250: 0000d8c0 call d8c - -void print_block(char * str, unsigned int size, enum BLOCK_N block_i) { - int i; - if (block_i == HEX0_3) { - if (size > 4) panic(); - for (i = 0; i < size; i++) { - 1254: e0bffc17 ldw r2,-16(fp) - 1258: 10800044 addi r2,r2,1 - 125c: e0bffc15 stw r2,-16(fp) - 1260: e0fffc17 ldw r3,-16(fp) - 1264: e0bffe17 ldw r2,-8(fp) - 1268: 18bfed36 bltu r3,r2,1220 - 126c: 00003b06 br 135c - encodeLatHex(i,str[size-1-i]); - } - } - else if (block_i == HEX4_5) { - 1270: e0bfff17 ldw r2,-4(fp) - 1274: 10800058 cmpnei r2,r2,1 - 1278: 10001b1e bne r2,zero,12e8 - if (size > 2) panic(); - 127c: e0bffe17 ldw r2,-8(fp) - 1280: 108000f0 cmpltui r2,r2,3 - 1284: 1000011e bne r2,zero,128c - 1288: 00024b40 call 24b4 - for (i = 0; i < size; i++) { - 128c: e03ffc15 stw zero,-16(fp) - 1290: 00001106 br 12d8 - encodeLatHex(i+4,str[size-1-i]); - 1294: e0bffc17 ldw r2,-16(fp) - 1298: 11000104 addi r4,r2,4 - 129c: e0fffc17 ldw r3,-16(fp) - 12a0: e0bffe17 ldw r2,-8(fp) - 12a4: 10c5c83a sub r2,r2,r3 - 12a8: 1007883a mov r3,r2 - 12ac: e0bffd17 ldw r2,-12(fp) - 12b0: 1885883a add r2,r3,r2 - 12b4: 10bfffc4 addi r2,r2,-1 - 12b8: 10800003 ldbu r2,0(r2) - 12bc: 11403fcc andi r5,r2,255 - 12c0: 2940201c xori r5,r5,128 - 12c4: 297fe004 addi r5,r5,-128 - 12c8: 0000d8c0 call d8c - encodeLatHex(i,str[size-1-i]); - } - } - else if (block_i == HEX4_5) { - if (size > 2) panic(); - for (i = 0; i < size; i++) { - 12cc: e0bffc17 ldw r2,-16(fp) - 12d0: 10800044 addi r2,r2,1 - 12d4: e0bffc15 stw r2,-16(fp) - 12d8: e0fffc17 ldw r3,-16(fp) - 12dc: e0bffe17 ldw r2,-8(fp) - 12e0: 18bfec36 bltu r3,r2,1294 - 12e4: 00001d06 br 135c - encodeLatHex(i+4,str[size-1-i]); - } - } - else if (block_i == HEX6_7) { - 12e8: e0bfff17 ldw r2,-4(fp) - 12ec: 10800098 cmpnei r2,r2,2 - 12f0: 10001a1e bne r2,zero,135c - if (size > 2) panic(); - 12f4: e0bffe17 ldw r2,-8(fp) - 12f8: 108000f0 cmpltui r2,r2,3 - 12fc: 1000011e bne r2,zero,1304 - 1300: 00024b40 call 24b4 - for (i = 0; i < size; i++) { - 1304: e03ffc15 stw zero,-16(fp) - 1308: 00001106 br 1350 - encodeLatHex(i+6,str[size-1-i]); - 130c: e0bffc17 ldw r2,-16(fp) - 1310: 11000184 addi r4,r2,6 - 1314: e0fffc17 ldw r3,-16(fp) - 1318: e0bffe17 ldw r2,-8(fp) - 131c: 10c5c83a sub r2,r2,r3 - 1320: 1007883a mov r3,r2 - 1324: e0bffd17 ldw r2,-12(fp) - 1328: 1885883a add r2,r3,r2 - 132c: 10bfffc4 addi r2,r2,-1 - 1330: 10800003 ldbu r2,0(r2) - 1334: 11403fcc andi r5,r2,255 - 1338: 2940201c xori r5,r5,128 - 133c: 297fe004 addi r5,r5,-128 - 1340: 0000d8c0 call d8c - encodeLatHex(i+4,str[size-1-i]); - } - } - else if (block_i == HEX6_7) { - if (size > 2) panic(); - for (i = 0; i < size; i++) { - 1344: e0bffc17 ldw r2,-16(fp) - 1348: 10800044 addi r2,r2,1 - 134c: e0bffc15 stw r2,-16(fp) - 1350: e0fffc17 ldw r3,-16(fp) - 1354: e0bffe17 ldw r2,-8(fp) - 1358: 18bfec36 bltu r3,r2,130c - encodeLatHex(i+6,str[size-1-i]); - } - } -} - 135c: e037883a mov sp,fp - 1360: dfc00117 ldw ra,4(sp) - 1364: df000017 ldw fp,0(sp) - 1368: dec00204 addi sp,sp,8 - 136c: f800283a ret - -00001370 : - -void clear_block(enum BLOCK_N block_i) { - 1370: defffd04 addi sp,sp,-12 - 1374: dfc00215 stw ra,8(sp) - 1378: df000115 stw fp,4(sp) - 137c: df000104 addi fp,sp,4 - 1380: e13fff15 stw r4,-4(fp) - if (block_i == HEX0_3) { - 1384: e0bfff17 ldw r2,-4(fp) - 1388: 1004c03a cmpne r2,r2,zero - 138c: 1000061e bne r2,zero,13a8 - print_block(" ", 4, HEX0_3); - 1390: 01000074 movhi r4,1 - 1394: 213fdb04 addi r4,r4,-148 - 1398: 01400104 movi r5,4 - 139c: 000d883a mov r6,zero - 13a0: 00011e00 call 11e0 - 13a4: 00001106 br 13ec - } - else if (block_i == HEX4_5) { - 13a8: e0bfff17 ldw r2,-4(fp) - 13ac: 10800058 cmpnei r2,r2,1 - 13b0: 1000061e bne r2,zero,13cc - print_block(" ", 2, HEX4_5); - 13b4: 01000074 movhi r4,1 - 13b8: 213fdd04 addi r4,r4,-140 - 13bc: 01400084 movi r5,2 - 13c0: 01800044 movi r6,1 - 13c4: 00011e00 call 11e0 - 13c8: 00000806 br 13ec - } - else if (block_i == HEX6_7) { - 13cc: e0bfff17 ldw r2,-4(fp) - 13d0: 10800098 cmpnei r2,r2,2 - 13d4: 1000051e bne r2,zero,13ec - print_block(" ", 2, HEX6_7); - 13d8: 01000074 movhi r4,1 - 13dc: 213fdd04 addi r4,r4,-140 - 13e0: 01400084 movi r5,2 - 13e4: 01800084 movi r6,2 - 13e8: 00011e00 call 11e0 - } -} - 13ec: e037883a mov sp,fp - 13f0: dfc00117 ldw ra,4(sp) - 13f4: df000017 ldw fp,0(sp) - 13f8: dec00204 addi sp,sp,8 - 13fc: f800283a ret - -00001400 : - -void print_number(char num) { - 1400: defff904 addi sp,sp,-28 - 1404: dfc00615 stw ra,24(sp) - 1408: df000515 stw fp,20(sp) - 140c: df000504 addi fp,sp,20 - 1410: e13fff05 stb r4,-4(fp) - int i; - char buf[5]; - char val; - for (i = 0; i < 4; i++) { - 1414: e03ffc15 stw zero,-16(fp) - 1418: 00002906 br 14c0 - if (num < 0) { - 141c: e0bfff07 ldb r2,-4(fp) - 1420: 1004403a cmpge r2,r2,zero - 1424: 1000061e bne r2,zero,1440 - buf[0] = '-'; - 1428: 00800b44 movi r2,45 - 142c: e0bffd05 stb r2,-12(fp) - val = -num; - 1430: e0bfff03 ldbu r2,-4(fp) - 1434: 0085c83a sub r2,zero,r2 - 1438: e0bffb05 stb r2,-20(fp) - 143c: 00000406 br 1450 - } else { - buf[0] = ' '; - 1440: 00800804 movi r2,32 - 1444: e0bffd05 stb r2,-12(fp) - val = num; - 1448: e0bfff03 ldbu r2,-4(fp) - 144c: e0bffb05 stb r2,-20(fp) - } - buf[1] = val/100%10 + '0'; - 1450: e13ffb07 ldb r4,-20(fp) - 1454: 01401904 movi r5,100 - 1458: 0002a5c0 call 2a5c <__divsi3> - 145c: 11003fcc andi r4,r2,255 - 1460: 2100201c xori r4,r4,128 - 1464: 213fe004 addi r4,r4,-128 - 1468: 01400284 movi r5,10 - 146c: 0002abc0 call 2abc <__modsi3> - 1470: 10800c04 addi r2,r2,48 - 1474: e0bffd45 stb r2,-11(fp) - buf[2] = val/10%10 + '0'; - 1478: e13ffb07 ldb r4,-20(fp) - 147c: 01400284 movi r5,10 - 1480: 0002a5c0 call 2a5c <__divsi3> - 1484: 11003fcc andi r4,r2,255 - 1488: 2100201c xori r4,r4,128 - 148c: 213fe004 addi r4,r4,-128 - 1490: 01400284 movi r5,10 - 1494: 0002abc0 call 2abc <__modsi3> - 1498: 10800c04 addi r2,r2,48 - 149c: e0bffd85 stb r2,-10(fp) - buf[3] = val%10 + '0'; - 14a0: e13ffb07 ldb r4,-20(fp) - 14a4: 01400284 movi r5,10 - 14a8: 0002abc0 call 2abc <__modsi3> - 14ac: 10800c04 addi r2,r2,48 - 14b0: e0bffdc5 stb r2,-9(fp) - -void print_number(char num) { - int i; - char buf[5]; - char val; - for (i = 0; i < 4; i++) { - 14b4: e0bffc17 ldw r2,-16(fp) - 14b8: 10800044 addi r2,r2,1 - 14bc: e0bffc15 stw r2,-16(fp) - 14c0: e0bffc17 ldw r2,-16(fp) - 14c4: 10800110 cmplti r2,r2,4 - 14c8: 103fd41e bne r2,zero,141c - } - buf[1] = val/100%10 + '0'; - buf[2] = val/10%10 + '0'; - buf[3] = val%10 + '0'; - } - clear_block(HEX0_3); - 14cc: 0009883a mov r4,zero - 14d0: 00013700 call 1370 - print_block(buf, 4, HEX0_3); - 14d4: e13ffd04 addi r4,fp,-12 - 14d8: 01400104 movi r5,4 - 14dc: 000d883a mov r6,zero - 14e0: 00011e00 call 11e0 -} - 14e4: e037883a mov sp,fp - 14e8: dfc00117 ldw ra,4(sp) - 14ec: df000017 ldw fp,0(sp) - 14f0: dec00204 addi sp,sp,8 - 14f4: f800283a ret - -000014f8 : -#include "input_int.h" -#include "sys_register.h" - -unsigned char PUSH_EVENT = PUSH_NONE; - -void in_int() { - 14f8: defffe04 addi sp,sp,-8 - 14fc: dfc00115 stw ra,4(sp) - 1500: df000015 stw fp,0(sp) - 1504: d839883a mov fp,sp - push_int(); - 1508: 00016b40 call 16b4 -} - 150c: e037883a mov sp,fp - 1510: dfc00117 ldw ra,4(sp) - 1514: df000017 ldw fp,0(sp) - 1518: dec00204 addi sp,sp,8 - 151c: f800283a ret - -00001520 : - -static void update_sw_reg(sw_t s) { - 1520: defffe04 addi sp,sp,-8 - 1524: df000115 stw fp,4(sp) - 1528: df000104 addi fp,sp,4 - 152c: e13fff15 stw r4,-4(fp) - global_registers[Ssw_data] = (char)s.data.value; - 1530: e0bfff17 ldw r2,-4(fp) - 1534: 1004d2ba srli r2,r2,10 - 1538: 1007883a mov r3,r2 - 153c: 00bfffc4 movi r2,-1 - 1540: 1884703a and r2,r3,r2 - 1544: 1007883a mov r3,r2 - 1548: 00800074 movhi r2,1 - 154c: 10908f04 addi r2,r2,16956 - 1550: 10c001c5 stb r3,7(r2) - global_registers[Ssw_inst] = (char)s.splited.instruction_code; - 1554: e0bfff17 ldw r2,-4(fp) - 1558: 1004d3ba srli r2,r2,14 - 155c: 108003cc andi r2,r2,15 - 1560: 1007883a mov r3,r2 - 1564: 00800074 movhi r2,1 - 1568: 10908f04 addi r2,r2,16956 - 156c: 10c00205 stb r3,8(r2) - global_registers[Ssw_memi] = (char)s.splited.memory_index; - 1570: e0bfff17 ldw r2,-4(fp) - 1574: 1004d1ba srli r2,r2,6 - 1578: 108003cc andi r2,r2,15 - 157c: 1007883a mov r3,r2 - 1580: 00800074 movhi r2,1 - 1584: 10908f04 addi r2,r2,16956 - 1588: 10c00285 stb r3,10(r2) - global_registers[Ssw_regi] = (char)s.splited.register_index; - 158c: e0bfff17 ldw r2,-4(fp) - 1590: 1004d2ba srli r2,r2,10 - 1594: 108003cc andi r2,r2,15 - 1598: 1007883a mov r3,r2 - 159c: 00800074 movhi r2,1 - 15a0: 10908f04 addi r2,r2,16956 - 15a4: 10c00245 stb r3,9(r2) - global_registers[Ssw_psel] = (char)s.splited.program_selecter; - 15a8: e0bfff17 ldw r2,-4(fp) - 15ac: 1004d0ba srli r2,r2,2 - 15b0: 108003cc andi r2,r2,15 - 15b4: 1007883a mov r3,r2 - 15b8: 00800074 movhi r2,1 - 15bc: 10908f04 addi r2,r2,16956 - 15c0: 10c002c5 stb r3,11(r2) - global_registers[Ssw_rw] = (char)s.splited.rw_mode; - 15c4: e0bfff17 ldw r2,-4(fp) - 15c8: 1004d07a srli r2,r2,1 - 15cc: 1080004c andi r2,r2,1 - 15d0: 1007883a mov r3,r2 - 15d4: 00800074 movhi r2,1 - 15d8: 10908f04 addi r2,r2,16956 - 15dc: 10c00305 stb r3,12(r2) - global_registers[Ssw_run] = (char)s.splited.run_mode; - 15e0: e0bfff17 ldw r2,-4(fp) - 15e4: 1080004c andi r2,r2,1 - 15e8: 1007883a mov r3,r2 - 15ec: 00800074 movhi r2,1 - 15f0: 10908f04 addi r2,r2,16956 - 15f4: 10c00345 stb r3,13(r2) -} - 15f8: e037883a mov sp,fp - 15fc: df000017 ldw fp,0(sp) - 1600: dec00104 addi sp,sp,4 - 1604: f800283a ret - -00001608 : - -enum PushEvent push_decode(char psw) { - 1608: defffc04 addi sp,sp,-16 - 160c: df000315 stw fp,12(sp) - 1610: df000304 addi fp,sp,12 - 1614: e13ffe05 stb r4,-8(fp) - int result = PUSH_NONE; - 1618: 00800044 movi r2,1 - 161c: e0bffd15 stw r2,-12(fp) - switch(psw) { - 1620: e0bffe07 ldb r2,-8(fp) - 1624: e0bfff15 stw r2,-4(fp) - 1628: e0ffff17 ldw r3,-4(fp) - 162c: 18800160 cmpeqi r2,r3,5 - 1630: 10000e1e bne r2,zero,166c - 1634: e0ffff17 ldw r3,-4(fp) - 1638: 188001a0 cmpeqi r2,r3,6 - 163c: 1000121e bne r2,zero,1688 - 1640: e0ffff17 ldw r3,-4(fp) - 1644: 188000e0 cmpeqi r2,r3,3 - 1648: 1000011e bne r2,zero,1650 - 164c: 00001406 br 16a0 - case 0x3: - result += PUSH_ANY; - 1650: e0bffd17 ldw r2,-12(fp) - 1654: 10800084 addi r2,r2,2 - 1658: e0bffd15 stw r2,-12(fp) - result += PUSH_VALSTR; - 165c: e0bffd17 ldw r2,-12(fp) - 1660: 10800104 addi r2,r2,4 - 1664: e0bffd15 stw r2,-12(fp) - break; - 1668: 00000d06 br 16a0 - case 0x5: - result += PUSH_ANY; - 166c: e0bffd17 ldw r2,-12(fp) - 1670: 10800084 addi r2,r2,2 - 1674: e0bffd15 stw r2,-12(fp) - result += PUSH_INSSTR; - 1678: e0bffd17 ldw r2,-12(fp) - 167c: 10800204 addi r2,r2,8 - 1680: e0bffd15 stw r2,-12(fp) - break; - 1684: 00000606 br 16a0 - case 0x6: - result += PUSH_ANY; - 1688: e0bffd17 ldw r2,-12(fp) - 168c: 10800084 addi r2,r2,2 - 1690: e0bffd15 stw r2,-12(fp) - result += PUSH_RUN; - 1694: e0bffd17 ldw r2,-12(fp) - 1698: 10800404 addi r2,r2,16 - 169c: e0bffd15 stw r2,-12(fp) - break; - } - return result; - 16a0: e0bffd17 ldw r2,-12(fp) -} - 16a4: e037883a mov sp,fp - 16a8: df000017 ldw fp,0(sp) - 16ac: dec00104 addi sp,sp,4 - 16b0: f800283a ret - -000016b4 : - -void push_int() { - 16b4: defffc04 addi sp,sp,-16 - 16b8: dfc00315 stw ra,12(sp) - 16bc: df000215 stw fp,8(sp) - 16c0: df000204 addi fp,sp,8 - static unsigned char status = 0; - static enum PushEvent event_code; - volatile sw_t s; - s.sw = *switches; - 16c4: 00800134 movhi r2,4 - 16c8: 10843404 addi r2,r2,4304 - 16cc: 10800017 ldw r2,0(r2) - 16d0: e0bffe15 stw r2,-8(fp) - - switch (status) { - 16d4: d0a6f803 ldbu r2,-25632(gp) - 16d8: 10803fcc andi r2,r2,255 - 16dc: e0bfff15 stw r2,-4(fp) - 16e0: e0ffff17 ldw r3,-4(fp) - 16e4: 18800060 cmpeqi r2,r3,1 - 16e8: 10001e1e bne r2,zero,1764 - 16ec: e0ffff17 ldw r3,-4(fp) - 16f0: 188000a0 cmpeqi r2,r3,2 - 16f4: 1000261e bne r2,zero,1790 - 16f8: e0ffff17 ldw r3,-4(fp) - 16fc: 1805003a cmpeq r2,r3,zero - 1700: 1000011e bne r2,zero,1708 - 1704: 00002606 br 17a0 - case 0: - PUSH_EVENT = PUSH_NONE; - 1708: 00800044 movi r2,1 - 170c: d0a00005 stb r2,-32768(gp) - if (*push_switches != 7) { - 1710: 00800134 movhi r2,4 - 1714: 10843004 addi r2,r2,4288 - 1718: 10800003 ldbu r2,0(r2) - 171c: 10803fcc andi r2,r2,255 - 1720: 1080201c xori r2,r2,128 - 1724: 10bfe004 addi r2,r2,-128 - 1728: 108001e0 cmpeqi r2,r2,7 - 172c: 10000a1e bne r2,zero,1758 - event_code = push_decode(*push_switches); - 1730: 00800134 movhi r2,4 - 1734: 10843004 addi r2,r2,4288 - 1738: 10800003 ldbu r2,0(r2) - 173c: 11003fcc andi r4,r2,255 - 1740: 2100201c xori r4,r4,128 - 1744: 213fe004 addi r4,r4,-128 - 1748: 00016080 call 1608 - 174c: d0a6f715 stw r2,-25636(gp) - status = 1; - 1750: 00800044 movi r2,1 - 1754: d0a6f805 stb r2,-25632(gp) - } - update_sw_reg(s); // �X�C�b�`���W�X�^�X�V - 1758: e13ffe17 ldw r4,-8(fp) - 175c: 00015200 call 1520 - break; - 1760: 00001006 br 17a4 - case 1: - if (*push_switches == 7) status = 2; - 1764: 00800134 movhi r2,4 - 1768: 10843004 addi r2,r2,4288 - 176c: 10800003 ldbu r2,0(r2) - 1770: 10803fcc andi r2,r2,255 - 1774: 1080201c xori r2,r2,128 - 1778: 10bfe004 addi r2,r2,-128 - 177c: 108001d8 cmpnei r2,r2,7 - 1780: 1000081e bne r2,zero,17a4 - 1784: 00800084 movi r2,2 - 1788: d0a6f805 stb r2,-25632(gp) - break; - 178c: 00000506 br 17a4 - case 2: - PUSH_EVENT = event_code; - 1790: d0a6f717 ldw r2,-25636(gp) - 1794: d0a00005 stb r2,-32768(gp) - status = 0; - 1798: d026f805 stb zero,-25632(gp) - break; - 179c: 00000106 br 17a4 - default: - status = 0; - 17a0: d026f805 stb zero,-25632(gp) - break; - } -} - 17a4: e037883a mov sp,fp - 17a8: dfc00117 ldw ra,4(sp) - 17ac: df000017 ldw fp,0(sp) - 17b0: dec00204 addi sp,sp,8 - 17b4: f800283a ret - -000017b8 : -#include "hex_out.h" -#include "sys_prog.h" -#include -#include - -struct InstRec inst_fetch(){ - 17b8: defffd04 addi sp,sp,-12 - 17bc: dfc00215 stw ra,8(sp) - 17c0: df000115 stw fp,4(sp) - 17c4: df000104 addi fp,sp,4 - struct InstRec rec = inst_memory_load((unsigned int)global_registers[Spc]); - 17c8: 00800074 movhi r2,1 - 17cc: 10908f04 addi r2,r2,16956 - 17d0: 10800043 ldbu r2,1(r2) - 17d4: 11003fcc andi r4,r2,255 - 17d8: 2100201c xori r4,r4,128 - 17dc: 213fe004 addi r4,r4,-128 - 17e0: 00025c00 call 25c0 - 17e4: e0bfff15 stw r2,-4(fp) - inc_pc(); - 17e8: 00027340 call 2734 - return rec; - 17ec: e0bfff17 ldw r2,-4(fp) -} - 17f0: e037883a mov sp,fp - 17f4: dfc00117 ldw ra,4(sp) - 17f8: df000017 ldw fp,0(sp) - 17fc: dec00204 addi sp,sp,8 - 1800: f800283a ret - -00001804 : - -void inst_decode(struct InstRec inst_rec){ - 1804: defffc04 addi sp,sp,-16 - 1808: dfc00315 stw ra,12(sp) - 180c: df000215 stw fp,8(sp) - 1810: df000204 addi fp,sp,8 - 1814: e13ffe15 stw r4,-8(fp) - switch(inst_rec.inst) { - 1818: e0bffe17 ldw r2,-8(fp) - 181c: 108003cc andi r2,r2,15 - 1820: 10803fcc andi r2,r2,255 - 1824: e0bfff15 stw r2,-4(fp) - 1828: e0ffff17 ldw r3,-4(fp) - 182c: 18800328 cmpgeui r2,r3,12 - 1830: 1000821e bne r2,zero,1a3c - 1834: e13fff17 ldw r4,-4(fp) - 1838: e13fff17 ldw r4,-4(fp) - 183c: 2105883a add r2,r4,r4 - 1840: 1087883a add r3,r2,r2 - 1844: 00800034 movhi r2,0 - 1848: 10861604 addi r2,r2,6232 - 184c: 1885883a add r2,r3,r2 - 1850: 10800017 ldw r2,0(r2) - 1854: 1000683a jmp r2 - 1858: 00001a3c xorhi zero,zero,104 - 185c: 00001888 cmpgei zero,zero,98 - 1860: 000018b0 cmpltui zero,zero,98 - 1864: 000018d8 cmpnei zero,zero,99 - 1868: 00001900 call 190 - 186c: 00001928 cmpgeui zero,zero,100 - 1870: 00001950 cmplti zero,zero,101 - 1874: 00001978 rdprs zero,zero,101 - 1878: 000019a0 cmpeqi zero,zero,102 - 187c: 000019c8 cmpgei zero,zero,103 - 1880: 000019f0 cmpltui zero,zero,103 - 1884: 00001a18 cmpnei zero,zero,104 - case INST_END: - break; - case INST_JUMP: - inst_jump(inst_rec.regi, inst_rec.memi); - 1888: e0bffe17 ldw r2,-8(fp) - 188c: 1004d23a srli r2,r2,8 - 1890: 108003cc andi r2,r2,15 - 1894: 11003fcc andi r4,r2,255 - 1898: e0bffe17 ldw r2,-8(fp) - 189c: 1004d13a srli r2,r2,4 - 18a0: 108003cc andi r2,r2,15 - 18a4: 11403fcc andi r5,r2,255 - 18a8: 0001a500 call 1a50 - break; - 18ac: 00006306 br 1a3c - case INST_OUTPUT: - inst_output(inst_rec.regi, inst_rec.memi); - 18b0: e0bffe17 ldw r2,-8(fp) - 18b4: 1004d23a srli r2,r2,8 - 18b8: 108003cc andi r2,r2,15 - 18bc: 11003fcc andi r4,r2,255 - 18c0: e0bffe17 ldw r2,-8(fp) - 18c4: 1004d13a srli r2,r2,4 - 18c8: 108003cc andi r2,r2,15 - 18cc: 11403fcc andi r5,r2,255 - 18d0: 0001aac0 call 1aac - break; - 18d4: 00005906 br 1a3c - case INST_LOAD: - inst_load(inst_rec.regi, inst_rec.memi); - 18d8: e0bffe17 ldw r2,-8(fp) - 18dc: 1004d23a srli r2,r2,8 - 18e0: 108003cc andi r2,r2,15 - 18e4: 11003fcc andi r4,r2,255 - 18e8: e0bffe17 ldw r2,-8(fp) - 18ec: 1004d13a srli r2,r2,4 - 18f0: 108003cc andi r2,r2,15 - 18f4: 11403fcc andi r5,r2,255 - 18f8: 0001b1c0 call 1b1c - break; - 18fc: 00004f06 br 1a3c - case INST_STORE: - inst_store(inst_rec.regi, inst_rec.memi); - 1900: e0bffe17 ldw r2,-8(fp) - 1904: 1004d23a srli r2,r2,8 - 1908: 108003cc andi r2,r2,15 - 190c: 11003fcc andi r4,r2,255 - 1910: e0bffe17 ldw r2,-8(fp) - 1914: 1004d13a srli r2,r2,4 - 1918: 108003cc andi r2,r2,15 - 191c: 11403fcc andi r5,r2,255 - 1920: 0001b540 call 1b54 - break; - 1924: 00004506 br 1a3c - case INST_DELAY: - inst_delay(inst_rec.regi, inst_rec.memi); - 1928: e0bffe17 ldw r2,-8(fp) - 192c: 1004d23a srli r2,r2,8 - 1930: 108003cc andi r2,r2,15 - 1934: 11003fcc andi r4,r2,255 - 1938: e0bffe17 ldw r2,-8(fp) - 193c: 1004d13a srli r2,r2,4 - 1940: 108003cc andi r2,r2,15 - 1944: 11403fcc andi r5,r2,255 - 1948: 0001b8c0 call 1b8c - break; - 194c: 00003b06 br 1a3c - case INST_ADD: - inst_add(inst_rec.regi, inst_rec.memi); - 1950: e0bffe17 ldw r2,-8(fp) - 1954: 1004d23a srli r2,r2,8 - 1958: 108003cc andi r2,r2,15 - 195c: 11003fcc andi r4,r2,255 - 1960: e0bffe17 ldw r2,-8(fp) - 1964: 1004d13a srli r2,r2,4 - 1968: 108003cc andi r2,r2,15 - 196c: 11403fcc andi r5,r2,255 - 1970: 0001be80 call 1be8 - break; - 1974: 00003106 br 1a3c - case INST_COMP: - inst_comp(inst_rec.regi, inst_rec.memi); - 1978: e0bffe17 ldw r2,-8(fp) - 197c: 1004d23a srli r2,r2,8 - 1980: 108003cc andi r2,r2,15 - 1984: 11003fcc andi r4,r2,255 - 1988: e0bffe17 ldw r2,-8(fp) - 198c: 1004d13a srli r2,r2,4 - 1990: 108003cc andi r2,r2,15 - 1994: 11403fcc andi r5,r2,255 - 1998: 0001c440 call 1c44 - break; - 199c: 00002706 br 1a3c - case INST_JEQ: - inst_jeq(inst_rec.regi, inst_rec.memi); - 19a0: e0bffe17 ldw r2,-8(fp) - 19a4: 1004d23a srli r2,r2,8 - 19a8: 108003cc andi r2,r2,15 - 19ac: 11003fcc andi r4,r2,255 - 19b0: e0bffe17 ldw r2,-8(fp) - 19b4: 1004d13a srli r2,r2,4 - 19b8: 108003cc andi r2,r2,15 - 19bc: 11403fcc andi r5,r2,255 - 19c0: 0001d140 call 1d14 - break; - 19c4: 00001d06 br 1a3c - case INST_JNE: - inst_jne(inst_rec.regi, inst_rec.memi); - 19c8: e0bffe17 ldw r2,-8(fp) - 19cc: 1004d23a srli r2,r2,8 - 19d0: 108003cc andi r2,r2,15 - 19d4: 11003fcc andi r4,r2,255 - 19d8: e0bffe17 ldw r2,-8(fp) - 19dc: 1004d13a srli r2,r2,4 - 19e0: 108003cc andi r2,r2,15 - 19e4: 11403fcc andi r5,r2,255 - 19e8: 0001d800 call 1d80 - break; - 19ec: 00001306 br 1a3c - case INST_JIEQ: - inst_jieq(inst_rec.regi, inst_rec.memi); - 19f0: e0bffe17 ldw r2,-8(fp) - 19f4: 1004d23a srli r2,r2,8 - 19f8: 108003cc andi r2,r2,15 - 19fc: 11003fcc andi r4,r2,255 - 1a00: e0bffe17 ldw r2,-8(fp) - 1a04: 1004d13a srli r2,r2,4 - 1a08: 108003cc andi r2,r2,15 - 1a0c: 11403fcc andi r5,r2,255 - 1a10: 0001dec0 call 1dec - break; - 1a14: 00000906 br 1a3c - case INST_JINE: - inst_jine(inst_rec.regi, inst_rec.memi); - 1a18: e0bffe17 ldw r2,-8(fp) - 1a1c: 1004d23a srli r2,r2,8 - 1a20: 108003cc andi r2,r2,15 - 1a24: 11003fcc andi r4,r2,255 - 1a28: e0bffe17 ldw r2,-8(fp) - 1a2c: 1004d13a srli r2,r2,4 - 1a30: 108003cc andi r2,r2,15 - 1a34: 11403fcc andi r5,r2,255 - 1a38: 0001e3c0 call 1e3c - break; - } -} - 1a3c: e037883a mov sp,fp - 1a40: dfc00117 ldw ra,4(sp) - 1a44: df000017 ldw fp,0(sp) - 1a48: dec00204 addi sp,sp,8 - 1a4c: f800283a ret - -00001a50 : - -void inst_jump(enum Register reg, unsigned char memory_index){ - 1a50: defffc04 addi sp,sp,-16 - 1a54: dfc00315 stw ra,12(sp) - 1a58: df000215 stw fp,8(sp) - 1a5c: df000204 addi fp,sp,8 - 1a60: e13ffe15 stw r4,-8(fp) - 1a64: e17fff05 stb r5,-4(fp) - set_pc(global_registers[reg]+memory_index); - 1a68: e0fffe17 ldw r3,-8(fp) - 1a6c: 00800074 movhi r2,1 - 1a70: 10908f04 addi r2,r2,16956 - 1a74: 10c5883a add r2,r2,r3 - 1a78: 10800003 ldbu r2,0(r2) - 1a7c: 10c03fcc andi r3,r2,255 - 1a80: 18c0201c xori r3,r3,128 - 1a84: 18ffe004 addi r3,r3,-128 - 1a88: e0bfff03 ldbu r2,-4(fp) - 1a8c: 1885883a add r2,r3,r2 - 1a90: 1009883a mov r4,r2 - 1a94: 00028080 call 2808 -} - 1a98: e037883a mov sp,fp - 1a9c: dfc00117 ldw ra,4(sp) - 1aa0: df000017 ldw fp,0(sp) - 1aa4: dec00204 addi sp,sp,8 - 1aa8: f800283a ret - -00001aac : -void inst_output(enum Register reg, unsigned char memory_index){ - 1aac: defffa04 addi sp,sp,-24 - 1ab0: dfc00515 stw ra,20(sp) - 1ab4: df000415 stw fp,16(sp) - 1ab8: df000404 addi fp,sp,16 - 1abc: e13ffe15 stw r4,-8(fp) - 1ac0: e17fff05 stb r5,-4(fp) - //�������̒l��7�Z�O�ɕ\�� - char buf[5]; - memory_load(memory_index, Sseg); - 1ac4: e13fff03 ldbu r4,-4(fp) - 1ac8: 01400384 movi r5,14 - 1acc: 00026a40 call 26a4 - sprintf(buf, "%04d", global_registers[Sseg]); - 1ad0: 00800074 movhi r2,1 - 1ad4: 10908f04 addi r2,r2,16956 - 1ad8: 10800383 ldbu r2,14(r2) - 1adc: 11803fcc andi r6,r2,255 - 1ae0: 3180201c xori r6,r6,128 - 1ae4: 31bfe004 addi r6,r6,-128 - 1ae8: e13ffc04 addi r4,fp,-16 - 1aec: 01400074 movhi r5,1 - 1af0: 297fde04 addi r5,r5,-136 - 1af4: 0002b640 call 2b64 - print_block(buf, 4, HEX0_3); - 1af8: e13ffc04 addi r4,fp,-16 - 1afc: 01400104 movi r5,4 - 1b00: 000d883a mov r6,zero - 1b04: 00011e00 call 11e0 -} - 1b08: e037883a mov sp,fp - 1b0c: dfc00117 ldw ra,4(sp) - 1b10: df000017 ldw fp,0(sp) - 1b14: dec00204 addi sp,sp,8 - 1b18: f800283a ret - -00001b1c : -void inst_load(enum Register reg, unsigned char memory_index){ - 1b1c: defffc04 addi sp,sp,-16 - 1b20: dfc00315 stw ra,12(sp) - 1b24: df000215 stw fp,8(sp) - 1b28: df000204 addi fp,sp,8 - 1b2c: e13ffe15 stw r4,-8(fp) - 1b30: e17fff05 stb r5,-4(fp) - memory_load(memory_index, reg); - 1b34: e13fff03 ldbu r4,-4(fp) - 1b38: e17ffe17 ldw r5,-8(fp) - 1b3c: 00026a40 call 26a4 -} - 1b40: e037883a mov sp,fp - 1b44: dfc00117 ldw ra,4(sp) - 1b48: df000017 ldw fp,0(sp) - 1b4c: dec00204 addi sp,sp,8 - 1b50: f800283a ret - -00001b54 : -void inst_store(enum Register reg, unsigned char memory_index){ - 1b54: defffc04 addi sp,sp,-16 - 1b58: dfc00315 stw ra,12(sp) - 1b5c: df000215 stw fp,8(sp) - 1b60: df000204 addi fp,sp,8 - 1b64: e13ffe15 stw r4,-8(fp) - 1b68: e17fff05 stb r5,-4(fp) - memory_store(memory_index, reg); - 1b6c: e13fff03 ldbu r4,-4(fp) - 1b70: e17ffe17 ldw r5,-8(fp) - 1b74: 00026080 call 2608 -} - 1b78: e037883a mov sp,fp - 1b7c: dfc00117 ldw ra,4(sp) - 1b80: df000017 ldw fp,0(sp) - 1b84: dec00204 addi sp,sp,8 - 1b88: f800283a ret - -00001b8c : -void inst_delay(enum Register reg, unsigned char memory_index){ - 1b8c: defffc04 addi sp,sp,-16 - 1b90: dfc00315 stw ra,12(sp) - 1b94: df000215 stw fp,8(sp) - 1b98: df000204 addi fp,sp,8 - 1b9c: e13ffe15 stw r4,-8(fp) - 1ba0: e17fff05 stb r5,-4(fp) - //���W�X�^�̒l*10ms�҂� - usleep((int)global_registers[reg]*10000); - 1ba4: e0fffe17 ldw r3,-8(fp) - 1ba8: 00800074 movhi r2,1 - 1bac: 10908f04 addi r2,r2,16956 - 1bb0: 10c5883a add r2,r2,r3 - 1bb4: 10800003 ldbu r2,0(r2) - 1bb8: 11003fcc andi r4,r2,255 - 1bbc: 2100201c xori r4,r4,128 - 1bc0: 213fe004 addi r4,r4,-128 - 1bc4: 0149c404 movi r5,10000 - 1bc8: 0002b2c0 call 2b2c <__mulsi3> - 1bcc: 1009883a mov r4,r2 - 1bd0: 000cd800 call cd80 -} - 1bd4: e037883a mov sp,fp - 1bd8: dfc00117 ldw ra,4(sp) - 1bdc: df000017 ldw fp,0(sp) - 1be0: dec00204 addi sp,sp,8 - 1be4: f800283a ret - -00001be8 : -void inst_add(enum Register reg, unsigned char memory_index){ - 1be8: defffd04 addi sp,sp,-12 - 1bec: df000215 stw fp,8(sp) - 1bf0: df000204 addi fp,sp,8 - 1bf4: e13ffe15 stw r4,-8(fp) - 1bf8: e17fff05 stb r5,-4(fp) - global_registers[Sacc]+=global_registers[reg]; - 1bfc: 00800074 movhi r2,1 - 1c00: 10908f04 addi r2,r2,16956 - 1c04: 10800143 ldbu r2,5(r2) - 1c08: 1009883a mov r4,r2 - 1c0c: e0fffe17 ldw r3,-8(fp) - 1c10: 00800074 movhi r2,1 - 1c14: 10908f04 addi r2,r2,16956 - 1c18: 10c5883a add r2,r2,r3 - 1c1c: 10800003 ldbu r2,0(r2) - 1c20: 2085883a add r2,r4,r2 - 1c24: 1007883a mov r3,r2 - 1c28: 00800074 movhi r2,1 - 1c2c: 10908f04 addi r2,r2,16956 - 1c30: 10c00145 stb r3,5(r2) -} - 1c34: e037883a mov sp,fp - 1c38: df000017 ldw fp,0(sp) - 1c3c: dec00104 addi sp,sp,4 - 1c40: f800283a ret - -00001c44 : -void inst_comp(enum Register reg, unsigned char memory_index){ - 1c44: defffd04 addi sp,sp,-12 - 1c48: df000215 stw fp,8(sp) - 1c4c: df000204 addi fp,sp,8 - 1c50: e13ffe15 stw r4,-8(fp) - 1c54: e17fff05 stb r5,-4(fp) - if(global_registers[Sacc]==global_registers[reg]){ - 1c58: 00800074 movhi r2,1 - 1c5c: 10908f04 addi r2,r2,16956 - 1c60: 11000143 ldbu r4,5(r2) - 1c64: e0fffe17 ldw r3,-8(fp) - 1c68: 00800074 movhi r2,1 - 1c6c: 10908f04 addi r2,r2,16956 - 1c70: 10c5883a add r2,r2,r3 - 1c74: 10800003 ldbu r2,0(r2) - 1c78: 20c03fcc andi r3,r4,255 - 1c7c: 18c0201c xori r3,r3,128 - 1c80: 18ffe004 addi r3,r3,-128 - 1c84: 10803fcc andi r2,r2,255 - 1c88: 1080201c xori r2,r2,128 - 1c8c: 10bfe004 addi r2,r2,-128 - 1c90: 1880041e bne r3,r2,1ca4 - global_registers[Sflg]=0; - 1c94: 00800074 movhi r2,1 - 1c98: 10908f04 addi r2,r2,16956 - 1c9c: 10000185 stb zero,6(r2) - 1ca0: 00001806 br 1d04 - } else if(global_registers[Sacc] > global_registers[reg]){ - 1ca4: 00800074 movhi r2,1 - 1ca8: 10908f04 addi r2,r2,16956 - 1cac: 11000143 ldbu r4,5(r2) - 1cb0: e0fffe17 ldw r3,-8(fp) - 1cb4: 00800074 movhi r2,1 - 1cb8: 10908f04 addi r2,r2,16956 - 1cbc: 10c5883a add r2,r2,r3 - 1cc0: 10800003 ldbu r2,0(r2) - 1cc4: 20c03fcc andi r3,r4,255 - 1cc8: 18c0201c xori r3,r3,128 - 1ccc: 18ffe004 addi r3,r3,-128 - 1cd0: 10803fcc andi r2,r2,255 - 1cd4: 1080201c xori r2,r2,128 - 1cd8: 10bfe004 addi r2,r2,-128 - 1cdc: 10c0050e bge r2,r3,1cf4 - global_registers[Sflg]=-1; - 1ce0: 00c00074 movhi r3,1 - 1ce4: 18d08f04 addi r3,r3,16956 - 1ce8: 00bfffc4 movi r2,-1 - 1cec: 18800185 stb r2,6(r3) - 1cf0: 00000406 br 1d04 - }else{ - global_registers[Sflg]=1; - 1cf4: 00c00074 movhi r3,1 - 1cf8: 18d08f04 addi r3,r3,16956 - 1cfc: 00800044 movi r2,1 - 1d00: 18800185 stb r2,6(r3) - } -} - 1d04: e037883a mov sp,fp - 1d08: df000017 ldw fp,0(sp) - 1d0c: dec00104 addi sp,sp,4 - 1d10: f800283a ret - -00001d14 : -void inst_jeq(enum Register reg, unsigned char memory_index){ - 1d14: defffc04 addi sp,sp,-16 - 1d18: dfc00315 stw ra,12(sp) - 1d1c: df000215 stw fp,8(sp) - 1d20: df000204 addi fp,sp,8 - 1d24: e13ffe15 stw r4,-8(fp) - 1d28: e17fff05 stb r5,-4(fp) - if(global_registers[Sflg]==global_registers[reg]){ - 1d2c: 00800074 movhi r2,1 - 1d30: 10908f04 addi r2,r2,16956 - 1d34: 11000183 ldbu r4,6(r2) - 1d38: e0fffe17 ldw r3,-8(fp) - 1d3c: 00800074 movhi r2,1 - 1d40: 10908f04 addi r2,r2,16956 - 1d44: 10c5883a add r2,r2,r3 - 1d48: 10800003 ldbu r2,0(r2) - 1d4c: 20c03fcc andi r3,r4,255 - 1d50: 18c0201c xori r3,r3,128 - 1d54: 18ffe004 addi r3,r3,-128 - 1d58: 10803fcc andi r2,r2,255 - 1d5c: 1080201c xori r2,r2,128 - 1d60: 10bfe004 addi r2,r2,-128 - 1d64: 1880011e bne r3,r2,1d6c - inc_pc(); - 1d68: 00027340 call 2734 - } -} - 1d6c: e037883a mov sp,fp - 1d70: dfc00117 ldw ra,4(sp) - 1d74: df000017 ldw fp,0(sp) - 1d78: dec00204 addi sp,sp,8 - 1d7c: f800283a ret - -00001d80 : -void inst_jne(enum Register reg, unsigned char memory_index){ - 1d80: defffc04 addi sp,sp,-16 - 1d84: dfc00315 stw ra,12(sp) - 1d88: df000215 stw fp,8(sp) - 1d8c: df000204 addi fp,sp,8 - 1d90: e13ffe15 stw r4,-8(fp) - 1d94: e17fff05 stb r5,-4(fp) - if(global_registers[Sflg]!=global_registers[reg]){ - 1d98: 00800074 movhi r2,1 - 1d9c: 10908f04 addi r2,r2,16956 - 1da0: 11000183 ldbu r4,6(r2) - 1da4: e0fffe17 ldw r3,-8(fp) - 1da8: 00800074 movhi r2,1 - 1dac: 10908f04 addi r2,r2,16956 - 1db0: 10c5883a add r2,r2,r3 - 1db4: 10800003 ldbu r2,0(r2) - 1db8: 20c03fcc andi r3,r4,255 - 1dbc: 18c0201c xori r3,r3,128 - 1dc0: 18ffe004 addi r3,r3,-128 - 1dc4: 10803fcc andi r2,r2,255 - 1dc8: 1080201c xori r2,r2,128 - 1dcc: 10bfe004 addi r2,r2,-128 - 1dd0: 18800126 beq r3,r2,1dd8 - inc_pc(); - 1dd4: 00027340 call 2734 - } -} - 1dd8: e037883a mov sp,fp - 1ddc: dfc00117 ldw ra,4(sp) - 1de0: df000017 ldw fp,0(sp) - 1de4: dec00204 addi sp,sp,8 - 1de8: f800283a ret - -00001dec : -void inst_jieq(char im, unsigned char memory_index){ - 1dec: defffc04 addi sp,sp,-16 - 1df0: dfc00315 stw ra,12(sp) - 1df4: df000215 stw fp,8(sp) - 1df8: df000204 addi fp,sp,8 - 1dfc: e13ffe05 stb r4,-8(fp) - 1e00: e17fff05 stb r5,-4(fp) - if(global_registers[Sflg]==im){ - 1e04: 00800074 movhi r2,1 - 1e08: 10908f04 addi r2,r2,16956 - 1e0c: 10800183 ldbu r2,6(r2) - 1e10: 10c03fcc andi r3,r2,255 - 1e14: 18c0201c xori r3,r3,128 - 1e18: 18ffe004 addi r3,r3,-128 - 1e1c: e0bffe07 ldb r2,-8(fp) - 1e20: 1880011e bne r3,r2,1e28 - inc_pc(); - 1e24: 00027340 call 2734 - } -} - 1e28: e037883a mov sp,fp - 1e2c: dfc00117 ldw ra,4(sp) - 1e30: df000017 ldw fp,0(sp) - 1e34: dec00204 addi sp,sp,8 - 1e38: f800283a ret - -00001e3c : -void inst_jine(char im, unsigned char memory_index){ - 1e3c: defffc04 addi sp,sp,-16 - 1e40: dfc00315 stw ra,12(sp) - 1e44: df000215 stw fp,8(sp) - 1e48: df000204 addi fp,sp,8 - 1e4c: e13ffe05 stb r4,-8(fp) - 1e50: e17fff05 stb r5,-4(fp) - if(global_registers[Sflg]!=im){ - 1e54: 00800074 movhi r2,1 - 1e58: 10908f04 addi r2,r2,16956 - 1e5c: 10800183 ldbu r2,6(r2) - 1e60: 10c03fcc andi r3,r2,255 - 1e64: 18c0201c xori r3,r3,128 - 1e68: 18ffe004 addi r3,r3,-128 - 1e6c: e0bffe07 ldb r2,-8(fp) - 1e70: 18800126 beq r3,r2,1e78 - inc_pc(); - 1e74: 00027340 call 2734 - } -} - 1e78: e037883a mov sp,fp - 1e7c: dfc00117 ldw ra,4(sp) - 1e80: df000017 ldw fp,0(sp) - 1e84: dec00204 addi sp,sp,8 - 1e88: f800283a ret - -00001e8c : -#include -#include "system.h" -#include "LCD.h" - -// LCD�̏����� -void lcd_init() { - 1e8c: defffe04 addi sp,sp,-8 - 1e90: dfc00115 stw ra,4(sp) - 1e94: df000015 stw fp,0(sp) - 1e98: d839883a mov fp,sp - *lcd_on = 1; - 1e9c: 00c00134 movhi r3,4 - 1ea0: 18c40404 addi r3,r3,4112 - 1ea4: 00800044 movi r2,1 - 1ea8: 18800005 stb r2,0(r3) - *lcd_blon = 1; - 1eac: 00c00134 movhi r3,4 - 1eb0: 18c40804 addi r3,r3,4128 - 1eb4: 00800044 movi r2,1 - 1eb8: 18800005 stb r2,0(r3) - LCD_Init(); - 1ebc: 00001f00 call 1f0 -} - 1ec0: e037883a mov sp,fp - 1ec4: dfc00117 ldw ra,4(sp) - 1ec8: df000017 ldw fp,0(sp) - 1ecc: dec00204 addi sp,sp,8 - 1ed0: f800283a ret - -00001ed4 : - -// LCD�̃L�����b�g���P�s�ڂ̂͂��߂Ɉړ����� -void lcd_caret_reset() { - 1ed4: defffe04 addi sp,sp,-8 - 1ed8: dfc00115 stw ra,4(sp) - 1edc: df000015 stw fp,0(sp) - 1ee0: d839883a mov fp,sp - LCD_Init(); - 1ee4: 00001f00 call 1f0 -} - 1ee8: e037883a mov sp,fp - 1eec: dfc00117 ldw ra,4(sp) - 1ef0: df000017 ldw fp,0(sp) - 1ef4: dec00204 addi sp,sp,8 - 1ef8: f800283a ret - -00001efc : - -// LCD�̃L�����b�g���Q�s�ڂ̂͂��߂Ɉړ����� -void lcd_caret_reset2() { - 1efc: defffe04 addi sp,sp,-8 - 1f00: dfc00115 stw ra,4(sp) - 1f04: df000015 stw fp,0(sp) - 1f08: d839883a mov fp,sp - LCD_Line2(); - 1f0c: 00003140 call 314 -} - 1f10: e037883a mov sp,fp - 1f14: dfc00117 ldw ra,4(sp) - 1f18: df000017 ldw fp,0(sp) - 1f1c: dec00204 addi sp,sp,8 - 1f20: f800283a ret - -00001f24 : - -// LCD�ɕ�����\������ -void lcd_print(const char *str) { - 1f24: defffd04 addi sp,sp,-12 - 1f28: dfc00215 stw ra,8(sp) - 1f2c: df000115 stw fp,4(sp) - 1f30: df000104 addi fp,sp,4 - 1f34: e13fff15 stw r4,-4(fp) - LCD_Show_Text(str); - 1f38: e13fff17 ldw r4,-4(fp) - 1f3c: 000028c0 call 28c -} - 1f40: e037883a mov sp,fp - 1f44: dfc00117 ldw ra,4(sp) - 1f48: df000017 ldw fp,0(sp) - 1f4c: dec00204 addi sp,sp,8 - 1f50: f800283a ret - -00001f54 : -#include "sys_debug.h" -#include -#include "lcd_out.h" -#include - -void display_inst(struct InstRec inst, unsigned int pc) { - 1f54: defff504 addi sp,sp,-44 - 1f58: dfc00a15 stw ra,40(sp) - 1f5c: df000915 stw fp,36(sp) - 1f60: df000904 addi fp,sp,36 - 1f64: e13ffe15 stw r4,-8(fp) - 1f68: e17fff15 stw r5,-4(fp) - char inst_name[INST_NAME_ARRAY_LEN]; // ���ߖ� - char reg_name[REG_NAME_ARRAY_LEN]; // ���W�X�^�� - char buf[17]; - - // ���߂̖��O�̎擾 - convertInstName(inst_name, inst.inst); - 1f6c: e0bffe17 ldw r2,-8(fp) - 1f70: 108003cc andi r2,r2,15 - 1f74: 11403fcc andi r5,r2,255 - 1f78: e13ff704 addi r4,fp,-36 - 1f7c: 00021dc0 call 21dc - // ���W�X�^�̖��O�̎擾 - convertRegName(reg_name, inst.regi); - 1f80: e0bffe17 ldw r2,-8(fp) - 1f84: 1004d23a srli r2,r2,8 - 1f88: 108003cc andi r2,r2,15 - 1f8c: 11403fcc andi r5,r2,255 - 1f90: e13ff844 addi r4,fp,-31 - 1f94: 000206c0 call 206c - - lcd_caret_reset(); - 1f98: 0001ed40 call 1ed4 - sprintf(buf, "PC:0x%02x -> %4s",pc,inst_name); - 1f9c: e13ff944 addi r4,fp,-27 - 1fa0: 01400074 movhi r5,1 - 1fa4: 297fe004 addi r5,r5,-128 - 1fa8: e1bfff17 ldw r6,-4(fp) - 1fac: e1fff704 addi r7,fp,-36 - 1fb0: 0002b640 call 2b64 - lcd_print(buf); - 1fb4: e13ff944 addi r4,fp,-27 - 1fb8: 0001f240 call 1f24 - lcd_caret_reset2(); - 1fbc: 0001efc0 call 1efc - sprintf(buf, "REG:%3s,MEM:0x%1x",reg_name,inst.memi); - 1fc0: e0bffe17 ldw r2,-8(fp) - 1fc4: 1004d13a srli r2,r2,4 - 1fc8: 108003cc andi r2,r2,15 - 1fcc: 11c03fcc andi r7,r2,255 - 1fd0: e13ff944 addi r4,fp,-27 - 1fd4: e1bff844 addi r6,fp,-31 - 1fd8: 01400074 movhi r5,1 - 1fdc: 297fe504 addi r5,r5,-108 - 1fe0: 0002b640 call 2b64 - lcd_print(buf); - 1fe4: e13ff944 addi r4,fp,-27 - 1fe8: 0001f240 call 1f24 -} - 1fec: e037883a mov sp,fp - 1ff0: dfc00117 ldw ra,4(sp) - 1ff4: df000017 ldw fp,0(sp) - 1ff8: dec00204 addi sp,sp,8 - 1ffc: f800283a ret - -00002000 : - -void display_mem(unsigned char memi, char memv) { - 2000: defff704 addi sp,sp,-36 - 2004: dfc00815 stw ra,32(sp) - 2008: df000715 stw fp,28(sp) - 200c: df000704 addi fp,sp,28 - 2010: e13ffe05 stb r4,-8(fp) - 2014: e17fff05 stb r5,-4(fp) - char buf[17]; - - lcd_caret_reset(); - 2018: 0001ed40 call 1ed4 - sprintf(buf, "MEM:0x%1x",memi); - 201c: e1bffe03 ldbu r6,-8(fp) - 2020: e13ff904 addi r4,fp,-28 - 2024: 01400074 movhi r5,1 - 2028: 297fea04 addi r5,r5,-88 - 202c: 0002b640 call 2b64 - lcd_print(buf); - 2030: e13ff904 addi r4,fp,-28 - 2034: 0001f240 call 1f24 - lcd_caret_reset2(); - 2038: 0001efc0 call 1efc - sprintf(buf, "value:%d",memv); - 203c: e1bfff07 ldb r6,-4(fp) - 2040: e13ff904 addi r4,fp,-28 - 2044: 01400074 movhi r5,1 - 2048: 297fed04 addi r5,r5,-76 - 204c: 0002b640 call 2b64 - lcd_print(buf); - 2050: e13ff904 addi r4,fp,-28 - 2054: 0001f240 call 1f24 -} - 2058: e037883a mov sp,fp - 205c: dfc00117 ldw ra,4(sp) - 2060: df000017 ldw fp,0(sp) - 2064: dec00204 addi sp,sp,8 - 2068: f800283a ret - -0000206c : - -void convertRegName(char reg_name[REG_NAME_ARRAY_LEN], enum Register reg_code) { - 206c: defffd04 addi sp,sp,-12 - 2070: df000215 stw fp,8(sp) - 2074: df000204 addi fp,sp,8 - 2078: e13ffe15 stw r4,-8(fp) - 207c: e17fff15 stw r5,-4(fp) - switch(reg_code) { - 2080: e0bfff17 ldw r2,-4(fp) - 2084: 108001e8 cmpgeui r2,r2,7 - 2088: 1000481e bne r2,zero,21ac - 208c: e0bfff17 ldw r2,-4(fp) - 2090: 1085883a add r2,r2,r2 - 2094: 1087883a add r3,r2,r2 - 2098: 00800034 movhi r2,0 - 209c: 10882b04 addi r2,r2,8364 - 20a0: 1885883a add r2,r3,r2 - 20a4: 10800017 ldw r2,0(r2) - 20a8: 1000683a jmp r2 - 20ac: 000020c8 cmpgei zero,zero,131 - 20b0: 000020e4 muli zero,zero,131 - 20b4: 00002100 call 210 - 20b8: 0000211c xori zero,zero,132 - 20bc: 00002140 call 214 - 20c0: 00002164 muli zero,zero,133 - 20c4: 00002188 cmpgei zero,zero,134 - case Szero: - sprintf(reg_name, STRING_REG_ZERO); - 20c8: e0bffe17 ldw r2,-8(fp) - 20cc: 00c01684 movi r3,90 - 20d0: 10c00005 stb r3,0(r2) - 20d4: 00c01144 movi r3,69 - 20d8: 10c00045 stb r3,1(r2) - 20dc: 10000085 stb zero,2(r2) - break; - 20e0: 00003a06 br 21cc - case Spc: - sprintf(reg_name, STRING_REG_PC); - 20e4: e0bffe17 ldw r2,-8(fp) - 20e8: 00c01404 movi r3,80 - 20ec: 10c00005 stb r3,0(r2) - 20f0: 00c010c4 movi r3,67 - 20f4: 10c00045 stb r3,1(r2) - 20f8: 10000085 stb zero,2(r2) - break; - 20fc: 00003306 br 21cc - case Ssp: - sprintf(reg_name, STRING_REG_SP); - 2100: e0bffe17 ldw r2,-8(fp) - 2104: 00c014c4 movi r3,83 - 2108: 10c00005 stb r3,0(r2) - 210c: 00c01404 movi r3,80 - 2110: 10c00045 stb r3,1(r2) - 2114: 10000085 stb zero,2(r2) - break; - 2118: 00002c06 br 21cc - case Sgp0: - sprintf(reg_name, STRING_REG_GP0); - 211c: e0fffe17 ldw r3,-8(fp) - 2120: 008011c4 movi r2,71 - 2124: 18800005 stb r2,0(r3) - 2128: 00801404 movi r2,80 - 212c: 18800045 stb r2,1(r3) - 2130: 00800c04 movi r2,48 - 2134: 18800085 stb r2,2(r3) - 2138: 180000c5 stb zero,3(r3) - break; - 213c: 00002306 br 21cc - case Sgp1: - sprintf(reg_name, STRING_REG_GP1); - 2140: e0fffe17 ldw r3,-8(fp) - 2144: 008011c4 movi r2,71 - 2148: 18800005 stb r2,0(r3) - 214c: 00801404 movi r2,80 - 2150: 18800045 stb r2,1(r3) - 2154: 00800c44 movi r2,49 - 2158: 18800085 stb r2,2(r3) - 215c: 180000c5 stb zero,3(r3) - break; - 2160: 00001a06 br 21cc - case Sacc: - sprintf(reg_name, STRING_REG_ACC); - 2164: e0fffe17 ldw r3,-8(fp) - 2168: 00801044 movi r2,65 - 216c: 18800005 stb r2,0(r3) - 2170: 008010c4 movi r2,67 - 2174: 18800045 stb r2,1(r3) - 2178: 008010c4 movi r2,67 - 217c: 18800085 stb r2,2(r3) - 2180: 180000c5 stb zero,3(r3) - break; - 2184: 00001106 br 21cc - case Sflg: - sprintf(reg_name, STRING_REG_FLG); - 2188: e0fffe17 ldw r3,-8(fp) - 218c: 00801184 movi r2,70 - 2190: 18800005 stb r2,0(r3) - 2194: 00801304 movi r2,76 - 2198: 18800045 stb r2,1(r3) - 219c: 008011c4 movi r2,71 - 21a0: 18800085 stb r2,2(r3) - 21a4: 180000c5 stb zero,3(r3) - break; - 21a8: 00000806 br 21cc - default: - sprintf(reg_name, "non"); - 21ac: e0fffe17 ldw r3,-8(fp) - 21b0: 00801b84 movi r2,110 - 21b4: 18800005 stb r2,0(r3) - 21b8: 00801bc4 movi r2,111 - 21bc: 18800045 stb r2,1(r3) - 21c0: 00801b84 movi r2,110 - 21c4: 18800085 stb r2,2(r3) - 21c8: 180000c5 stb zero,3(r3) - break; - } -} - 21cc: e037883a mov sp,fp - 21d0: df000017 ldw fp,0(sp) - 21d4: dec00104 addi sp,sp,4 - 21d8: f800283a ret - -000021dc : - - -void convertInstName(char inst_name[INST_NAME_ARRAY_LEN], unsigned char inst_code) { - 21dc: defffc04 addi sp,sp,-16 - 21e0: df000315 stw fp,12(sp) - 21e4: df000304 addi fp,sp,12 - 21e8: e13ffd15 stw r4,-12(fp) - 21ec: e17ffe05 stb r5,-8(fp) - switch(inst_code) { - 21f0: e0bffe03 ldbu r2,-8(fp) - 21f4: e0bfff15 stw r2,-4(fp) - 21f8: e0ffff17 ldw r3,-4(fp) - 21fc: 18800328 cmpgeui r2,r3,12 - 2200: 10008f1e bne r2,zero,2440 - 2204: e13fff17 ldw r4,-4(fp) - 2208: e13fff17 ldw r4,-4(fp) - 220c: 2105883a add r2,r4,r4 - 2210: 1087883a add r3,r2,r2 - 2214: 00800034 movhi r2,0 - 2218: 10888a04 addi r2,r2,8744 - 221c: 1885883a add r2,r3,r2 - 2220: 10800017 ldw r2,0(r2) - 2224: 1000683a jmp r2 - 2228: 00002258 cmpnei zero,zero,137 - 222c: 0000227c xorhi zero,zero,137 - 2230: 000022a8 cmpgeui zero,zero,138 - 2234: 000022cc andi zero,zero,139 - 2238: 000022f8 rdprs zero,zero,139 - 223c: 00002324 muli zero,zero,140 - 2240: 00002350 cmplti zero,zero,141 - 2244: 00002374 movhi zero,141 - 2248: 000023a0 cmpeqi zero,zero,142 - 224c: 000023c4 movi zero,143 - 2250: 000023e8 cmpgeui zero,zero,143 - 2254: 00002414 movui zero,144 - case INST_END: - sprintf(inst_name, STRING_INST_END); - 2258: e0fffd17 ldw r3,-12(fp) - 225c: 00801144 movi r2,69 - 2260: 18800005 stb r2,0(r3) - 2264: 00801384 movi r2,78 - 2268: 18800045 stb r2,1(r3) - 226c: 00801104 movi r2,68 - 2270: 18800085 stb r2,2(r3) - 2274: 180000c5 stb zero,3(r3) - break; - 2278: 00007b06 br 2468 - case INST_JUMP: - sprintf(inst_name, STRING_INST_JUMP); - 227c: e0fffd17 ldw r3,-12(fp) - 2280: 00801284 movi r2,74 - 2284: 18800005 stb r2,0(r3) - 2288: 00801544 movi r2,85 - 228c: 18800045 stb r2,1(r3) - 2290: 00801344 movi r2,77 - 2294: 18800085 stb r2,2(r3) - 2298: 00801404 movi r2,80 - 229c: 188000c5 stb r2,3(r3) - 22a0: 18000105 stb zero,4(r3) - break; - 22a4: 00007006 br 2468 - case INST_OUTPUT: - sprintf(inst_name, STRING_INST_OUTPUT); - 22a8: e0fffd17 ldw r3,-12(fp) - 22ac: 008013c4 movi r2,79 - 22b0: 18800005 stb r2,0(r3) - 22b4: 00801544 movi r2,85 - 22b8: 18800045 stb r2,1(r3) - 22bc: 00801504 movi r2,84 - 22c0: 18800085 stb r2,2(r3) - 22c4: 180000c5 stb zero,3(r3) - break; - 22c8: 00006706 br 2468 - case INST_LOAD: - sprintf(inst_name, STRING_INST_LOAD); - 22cc: e0fffd17 ldw r3,-12(fp) - 22d0: 00801304 movi r2,76 - 22d4: 18800005 stb r2,0(r3) - 22d8: 008013c4 movi r2,79 - 22dc: 18800045 stb r2,1(r3) - 22e0: 00801044 movi r2,65 - 22e4: 18800085 stb r2,2(r3) - 22e8: 00801104 movi r2,68 - 22ec: 188000c5 stb r2,3(r3) - 22f0: 18000105 stb zero,4(r3) - break; - 22f4: 00005c06 br 2468 - case INST_STORE: - sprintf(inst_name, STRING_INST_STORE); - 22f8: e0fffd17 ldw r3,-12(fp) - 22fc: 008014c4 movi r2,83 - 2300: 18800005 stb r2,0(r3) - 2304: 00801504 movi r2,84 - 2308: 18800045 stb r2,1(r3) - 230c: 008013c4 movi r2,79 - 2310: 18800085 stb r2,2(r3) - 2314: 00801484 movi r2,82 - 2318: 188000c5 stb r2,3(r3) - 231c: 18000105 stb zero,4(r3) - break; - 2320: 00005106 br 2468 - case INST_DELAY: - sprintf(inst_name, STRING_INST_DELAY); - 2324: e0fffd17 ldw r3,-12(fp) - 2328: 00801104 movi r2,68 - 232c: 18800005 stb r2,0(r3) - 2330: 00801144 movi r2,69 - 2334: 18800045 stb r2,1(r3) - 2338: 00801304 movi r2,76 - 233c: 18800085 stb r2,2(r3) - 2340: 00801644 movi r2,89 - 2344: 188000c5 stb r2,3(r3) - 2348: 18000105 stb zero,4(r3) - break; - 234c: 00004606 br 2468 - case INST_ADD: - sprintf(inst_name, STRING_INST_ADD); - 2350: e0fffd17 ldw r3,-12(fp) - 2354: 00801044 movi r2,65 - 2358: 18800005 stb r2,0(r3) - 235c: 00801104 movi r2,68 - 2360: 18800045 stb r2,1(r3) - 2364: 00801104 movi r2,68 - 2368: 18800085 stb r2,2(r3) - 236c: 180000c5 stb zero,3(r3) - break; - 2370: 00003d06 br 2468 - case INST_COMP: - sprintf(inst_name, STRING_INST_COMP); - 2374: e0fffd17 ldw r3,-12(fp) - 2378: 008010c4 movi r2,67 - 237c: 18800005 stb r2,0(r3) - 2380: 008013c4 movi r2,79 - 2384: 18800045 stb r2,1(r3) - 2388: 00801344 movi r2,77 - 238c: 18800085 stb r2,2(r3) - 2390: 00801404 movi r2,80 - 2394: 188000c5 stb r2,3(r3) - 2398: 18000105 stb zero,4(r3) - break; - 239c: 00003206 br 2468 - case INST_JEQ: - sprintf(inst_name, STRING_INST_JEQ); - 23a0: e0fffd17 ldw r3,-12(fp) - 23a4: 00801284 movi r2,74 - 23a8: 18800005 stb r2,0(r3) - 23ac: 00801144 movi r2,69 - 23b0: 18800045 stb r2,1(r3) - 23b4: 00801444 movi r2,81 - 23b8: 18800085 stb r2,2(r3) - 23bc: 180000c5 stb zero,3(r3) - break; - 23c0: 00002906 br 2468 - case INST_JNE: - sprintf(inst_name, STRING_INST_JNE); - 23c4: e0fffd17 ldw r3,-12(fp) - 23c8: 00801284 movi r2,74 - 23cc: 18800005 stb r2,0(r3) - 23d0: 00801384 movi r2,78 - 23d4: 18800045 stb r2,1(r3) - 23d8: 00801144 movi r2,69 - 23dc: 18800085 stb r2,2(r3) - 23e0: 180000c5 stb zero,3(r3) - break; - 23e4: 00002006 br 2468 - case INST_JIEQ: - sprintf(inst_name, STRING_INST_JIEQ); - 23e8: e0fffd17 ldw r3,-12(fp) - 23ec: 00801284 movi r2,74 - 23f0: 18800005 stb r2,0(r3) - 23f4: 00801244 movi r2,73 - 23f8: 18800045 stb r2,1(r3) - 23fc: 00801144 movi r2,69 - 2400: 18800085 stb r2,2(r3) - 2404: 00801444 movi r2,81 - 2408: 188000c5 stb r2,3(r3) - 240c: 18000105 stb zero,4(r3) - break; - 2410: 00001506 br 2468 - case INST_JINE: - sprintf(inst_name, STRING_INST_JINE); - 2414: e0fffd17 ldw r3,-12(fp) - 2418: 00801284 movi r2,74 - 241c: 18800005 stb r2,0(r3) - 2420: 00801244 movi r2,73 - 2424: 18800045 stb r2,1(r3) - 2428: 00801384 movi r2,78 - 242c: 18800085 stb r2,2(r3) - 2430: 00801144 movi r2,69 - 2434: 188000c5 stb r2,3(r3) - 2438: 18000105 stb zero,4(r3) - break; - 243c: 00000a06 br 2468 - default: - sprintf(inst_name, "NoOp"); - 2440: e0fffd17 ldw r3,-12(fp) - 2444: 00801384 movi r2,78 - 2448: 18800005 stb r2,0(r3) - 244c: 00801bc4 movi r2,111 - 2450: 18800045 stb r2,1(r3) - 2454: 008013c4 movi r2,79 - 2458: 18800085 stb r2,2(r3) - 245c: 00801c04 movi r2,112 - 2460: 188000c5 stb r2,3(r3) - 2464: 18000105 stb zero,4(r3) - break; - } -} - 2468: e037883a mov sp,fp - 246c: df000017 ldw fp,0(sp) - 2470: dec00104 addi sp,sp,4 - 2474: f800283a ret - -00002478 : - -void delay10ms(unsigned int s) { - 2478: defffd04 addi sp,sp,-12 - 247c: dfc00215 stw ra,8(sp) - 2480: df000115 stw fp,4(sp) - 2484: df000104 addi fp,sp,4 - 2488: e13fff15 stw r4,-4(fp) - usleep(s*10000); - 248c: e13fff17 ldw r4,-4(fp) - 2490: 0149c404 movi r5,10000 - 2494: 0002b2c0 call 2b2c <__mulsi3> - 2498: 1009883a mov r4,r2 - 249c: 000cd800 call cd80 -} - 24a0: e037883a mov sp,fp - 24a4: dfc00117 ldw ra,4(sp) - 24a8: df000017 ldw fp,0(sp) - 24ac: dec00204 addi sp,sp,8 - 24b0: f800283a ret - -000024b4 : - * Author: takayun - */ -#include "system.h" -#include "hex_out.h" - -void panic() { - 24b4: defffe04 addi sp,sp,-8 - 24b8: dfc00115 stw ra,4(sp) - 24bc: df000015 stw fp,0(sp) - 24c0: d839883a mov fp,sp - clear_block(HEX0_3); - 24c4: 0009883a mov r4,zero - 24c8: 00013700 call 1370 - print_block("err ", 4, HEX0_3); - 24cc: 01000074 movhi r4,1 - 24d0: 213ff004 addi r4,r4,-64 - 24d4: 01400104 movi r5,4 - 24d8: 000d883a mov r6,zero - 24dc: 00011e00 call 11e0 -} - 24e0: e037883a mov sp,fp - 24e4: dfc00117 ldw ra,4(sp) - 24e8: df000017 ldw fp,0(sp) - 24ec: dec00204 addi sp,sp,8 - 24f0: f800283a ret - -000024f4 : - -/************************************************** - * Impl - **************************************************/ - -void memory_init() { - 24f4: defffd04 addi sp,sp,-12 - 24f8: df000215 stw fp,8(sp) - 24fc: df000204 addi fp,sp,8 - int i, j; - for (i = 0; i < MEMS_COUNT; i++) - 2500: e03fff15 stw zero,-4(fp) - 2504: 00001306 br 2554 - for (j = 0; j < MEM_SIZE; j++) { - 2508: e03ffe15 stw zero,-8(fp) - 250c: 00000b06 br 253c - memory[i][j] = 0; - 2510: e0bfff17 ldw r2,-4(fp) - 2514: e13ffe17 ldw r4,-8(fp) - 2518: 00c00074 movhi r3,1 - 251c: 18cf4504 addi r3,r3,15636 - 2520: 1004913a slli r2,r2,4 - 2524: 10c5883a add r2,r2,r3 - 2528: 1105883a add r2,r2,r4 - 252c: 10000005 stb zero,0(r2) - **************************************************/ - -void memory_init() { - int i, j; - for (i = 0; i < MEMS_COUNT; i++) - for (j = 0; j < MEM_SIZE; j++) { - 2530: e0bffe17 ldw r2,-8(fp) - 2534: 10800044 addi r2,r2,1 - 2538: e0bffe15 stw r2,-8(fp) - 253c: e0bffe17 ldw r2,-8(fp) - 2540: 10800410 cmplti r2,r2,16 - 2544: 103ff21e bne r2,zero,2510 - * Impl - **************************************************/ - -void memory_init() { - int i, j; - for (i = 0; i < MEMS_COUNT; i++) - 2548: e0bfff17 ldw r2,-4(fp) - 254c: 10800044 addi r2,r2,1 - 2550: e0bfff15 stw r2,-4(fp) - 2554: e0bfff17 ldw r2,-4(fp) - 2558: 10800410 cmplti r2,r2,16 - 255c: 103fea1e bne r2,zero,2508 - for (j = 0; j < MEM_SIZE; j++) { - memory[i][j] = 0; - } -} - 2560: e037883a mov sp,fp - 2564: df000017 ldw fp,0(sp) - 2568: dec00104 addi sp,sp,4 - 256c: f800283a ret - -00002570 : - -void inst_memory_store(unsigned int mem_addr, struct InstRec inst_rec){ - 2570: defffd04 addi sp,sp,-12 - 2574: df000215 stw fp,8(sp) - 2578: df000204 addi fp,sp,8 - 257c: e13ffe15 stw r4,-8(fp) - 2580: e17fff15 stw r5,-4(fp) - inst_memory[global_current_memory][mem_addr] = inst_rec; - 2584: d0a6f917 ldw r2,-25628(gp) - 2588: e0fffe17 ldw r3,-8(fp) - 258c: 01000074 movhi r4,1 - 2590: 210f8504 addi r4,r4,15892 - 2594: 1004913a slli r2,r2,4 - 2598: 10c5883a add r2,r2,r3 - 259c: 1085883a add r2,r2,r2 - 25a0: 1085883a add r2,r2,r2 - 25a4: 1107883a add r3,r2,r4 - 25a8: e0bfff17 ldw r2,-4(fp) - 25ac: 18800015 stw r2,0(r3) -} - 25b0: e037883a mov sp,fp - 25b4: df000017 ldw fp,0(sp) - 25b8: dec00104 addi sp,sp,4 - 25bc: f800283a ret - -000025c0 : -struct InstRec inst_memory_load(unsigned int mem_addr){ - 25c0: defffe04 addi sp,sp,-8 - 25c4: df000115 stw fp,4(sp) - 25c8: df000104 addi fp,sp,4 - 25cc: e13fff15 stw r4,-4(fp) - return inst_memory[global_current_memory][mem_addr]; - 25d0: d0a6f917 ldw r2,-25628(gp) - 25d4: e0ffff17 ldw r3,-4(fp) - 25d8: 01000074 movhi r4,1 - 25dc: 210f8504 addi r4,r4,15892 - 25e0: 1004913a slli r2,r2,4 - 25e4: 10c5883a add r2,r2,r3 - 25e8: 1085883a add r2,r2,r2 - 25ec: 1085883a add r2,r2,r2 - 25f0: 1105883a add r2,r2,r4 - 25f4: 10800017 ldw r2,0(r2) -} - 25f8: e037883a mov sp,fp - 25fc: df000017 ldw fp,0(sp) - 2600: dec00104 addi sp,sp,4 - 2604: f800283a ret - -00002608 : - -char memory_store(unsigned int mem_addr, enum Register reg) { - 2608: defffc04 addi sp,sp,-16 - 260c: dfc00315 stw ra,12(sp) - 2610: df000215 stw fp,8(sp) - 2614: df000204 addi fp,sp,8 - 2618: e13ffe15 stw r4,-8(fp) - 261c: e17fff15 stw r5,-4(fp) - if (!(mem_addr < MEM_SIZE)) panic(); - 2620: e0bffe17 ldw r2,-8(fp) - 2624: 10800430 cmpltui r2,r2,16 - 2628: 1000011e bne r2,zero,2630 - 262c: 00024b40 call 24b4 - memory[global_current_memory][mem_addr] = global_registers[reg]; - 2630: d166f917 ldw r5,-25628(gp) - 2634: e1bffe17 ldw r6,-8(fp) - 2638: e0ffff17 ldw r3,-4(fp) - 263c: 00800074 movhi r2,1 - 2640: 10908f04 addi r2,r2,16956 - 2644: 10c5883a add r2,r2,r3 - 2648: 11000003 ldbu r4,0(r2) - 264c: 00c00074 movhi r3,1 - 2650: 18cf4504 addi r3,r3,15636 - 2654: 2804913a slli r2,r5,4 - 2658: 10c5883a add r2,r2,r3 - 265c: 1185883a add r2,r2,r6 - 2660: 11000005 stb r4,0(r2) - return memory[global_current_memory][mem_addr]; - 2664: d0a6f917 ldw r2,-25628(gp) - 2668: e13ffe17 ldw r4,-8(fp) - 266c: 00c00074 movhi r3,1 - 2670: 18cf4504 addi r3,r3,15636 - 2674: 1004913a slli r2,r2,4 - 2678: 10c5883a add r2,r2,r3 - 267c: 1105883a add r2,r2,r4 - 2680: 10800003 ldbu r2,0(r2) - 2684: 10803fcc andi r2,r2,255 - 2688: 1080201c xori r2,r2,128 - 268c: 10bfe004 addi r2,r2,-128 -} - 2690: e037883a mov sp,fp - 2694: dfc00117 ldw ra,4(sp) - 2698: df000017 ldw fp,0(sp) - 269c: dec00204 addi sp,sp,8 - 26a0: f800283a ret - -000026a4 : - -char memory_load(unsigned int mem_addr, enum Register reg) { - 26a4: defffc04 addi sp,sp,-16 - 26a8: dfc00315 stw ra,12(sp) - 26ac: df000215 stw fp,8(sp) - 26b0: df000204 addi fp,sp,8 - 26b4: e13ffe15 stw r4,-8(fp) - 26b8: e17fff15 stw r5,-4(fp) - if (!(mem_addr < MEM_SIZE)) panic(); - 26bc: e0bffe17 ldw r2,-8(fp) - 26c0: 10800430 cmpltui r2,r2,16 - 26c4: 1000011e bne r2,zero,26cc - 26c8: 00024b40 call 24b4 - global_registers[reg] = memory[global_current_memory][mem_addr]; - 26cc: e17fff17 ldw r5,-4(fp) - 26d0: d0a6f917 ldw r2,-25628(gp) - 26d4: e13ffe17 ldw r4,-8(fp) - 26d8: 00c00074 movhi r3,1 - 26dc: 18cf4504 addi r3,r3,15636 - 26e0: 1004913a slli r2,r2,4 - 26e4: 10c5883a add r2,r2,r3 - 26e8: 1105883a add r2,r2,r4 - 26ec: 10c00003 ldbu r3,0(r2) - 26f0: 00800074 movhi r2,1 - 26f4: 10908f04 addi r2,r2,16956 - 26f8: 1145883a add r2,r2,r5 - 26fc: 10c00005 stb r3,0(r2) - return global_registers[reg]; - 2700: e0ffff17 ldw r3,-4(fp) - 2704: 00800074 movhi r2,1 - 2708: 10908f04 addi r2,r2,16956 - 270c: 10c5883a add r2,r2,r3 - 2710: 10800003 ldbu r2,0(r2) - 2714: 10803fcc andi r2,r2,255 - 2718: 1080201c xori r2,r2,128 - 271c: 10bfe004 addi r2,r2,-128 -} - 2720: e037883a mov sp,fp - 2724: dfc00117 ldw ra,4(sp) - 2728: df000017 ldw fp,0(sp) - 272c: dec00204 addi sp,sp,8 - 2730: f800283a ret - -00002734 : -#include "sys_register.h" -#include "sys_memory.h" -#include "hex_out.h" -#include "lcd_out.h" - -unsigned int inc_pc() { - 2734: deffff04 addi sp,sp,-4 - 2738: df000015 stw fp,0(sp) - 273c: d839883a mov fp,sp - if ((unsigned char)global_registers[Spc]+1 < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { - 2740: 00800074 movhi r2,1 - 2744: 10908f04 addi r2,r2,16956 - 2748: 10800043 ldbu r2,1(r2) - 274c: 10803fcc andi r2,r2,255 - 2750: 10800044 addi r2,r2,1 - 2754: 1009883a mov r4,r2 - 2758: 00800074 movhi r2,1 - 275c: 108f3704 addi r2,r2,15580 - 2760: 10800017 ldw r2,0(r2) - 2764: 1006913a slli r3,r2,4 - 2768: 00804004 movi r2,256 - 276c: 10c5c83a sub r2,r2,r3 - 2770: 2080092e bgeu r4,r2,2798 - global_registers[Spc] = (unsigned char)global_registers[Spc] + 1; - 2774: 00800074 movhi r2,1 - 2778: 10908f04 addi r2,r2,16956 - 277c: 10800043 ldbu r2,1(r2) - 2780: 10800044 addi r2,r2,1 - 2784: 1007883a mov r3,r2 - 2788: 00800074 movhi r2,1 - 278c: 10908f04 addi r2,r2,16956 - 2790: 10c00045 stb r3,1(r2) - 2794: 00000306 br 27a4 - } else { - global_registers[Spc] = 0; - 2798: 00800074 movhi r2,1 - 279c: 10908f04 addi r2,r2,16956 - 27a0: 10000045 stb zero,1(r2) - } - return 0; - 27a4: 0005883a mov r2,zero -} - 27a8: e037883a mov sp,fp - 27ac: df000017 ldw fp,0(sp) - 27b0: dec00104 addi sp,sp,4 - 27b4: f800283a ret - -000027b8 : -unsigned int add_pc(unsigned int cnt) { - 27b8: defffc04 addi sp,sp,-16 - 27bc: dfc00315 stw ra,12(sp) - 27c0: df000215 stw fp,8(sp) - 27c4: df000204 addi fp,sp,8 - 27c8: e13fff15 stw r4,-4(fp) - int i; - for (i = 0; i < cnt; i++) inc_pc(); - 27cc: e03ffe15 stw zero,-8(fp) - 27d0: 00000406 br 27e4 - 27d4: 00027340 call 2734 - 27d8: e0bffe17 ldw r2,-8(fp) - 27dc: 10800044 addi r2,r2,1 - 27e0: e0bffe15 stw r2,-8(fp) - 27e4: e0fffe17 ldw r3,-8(fp) - 27e8: e0bfff17 ldw r2,-4(fp) - 27ec: 18bff936 bltu r3,r2,27d4 - return 0; - 27f0: 0005883a mov r2,zero -} - 27f4: e037883a mov sp,fp - 27f8: dfc00117 ldw ra,4(sp) - 27fc: df000017 ldw fp,0(sp) - 2800: dec00204 addi sp,sp,8 - 2804: f800283a ret - -00002808 : -unsigned int set_pc(unsigned int cnt) { - 2808: defffe04 addi sp,sp,-8 - 280c: df000115 stw fp,4(sp) - 2810: df000104 addi fp,sp,4 - 2814: e13fff15 stw r4,-4(fp) - global_registers[Spc]=cnt; - 2818: e0bfff17 ldw r2,-4(fp) - 281c: 1007883a mov r3,r2 - 2820: 00800074 movhi r2,1 - 2824: 10908f04 addi r2,r2,16956 - 2828: 10c00045 stb r3,1(r2) - return 0; - 282c: 0005883a mov r2,zero -} - 2830: e037883a mov sp,fp - 2834: df000017 ldw fp,0(sp) - 2838: dec00104 addi sp,sp,4 - 283c: f800283a ret - -00002840 : - - -enum RunMode run_proc(enum RunMode mode) { - 2840: defff904 addi sp,sp,-28 - 2844: dfc00615 stw ra,24(sp) - 2848: df000515 stw fp,20(sp) - 284c: df000504 addi fp,sp,20 - 2850: e13ffe15 stw r4,-8(fp) - volatile struct InstRec inst_rec; - - if (RUN_INIT == mode) { - 2854: e0bffe17 ldw r2,-8(fp) - 2858: 10800058 cmpnei r2,r2,1 - 285c: 1000101e bne r2,zero,28a0 - lcd_caret_reset(); - 2860: 0001ed40 call 1ed4 - lcd_print("Run...now"); - 2864: 01000074 movhi r4,1 - 2868: 213ff204 addi r4,r4,-56 - 286c: 0001f240 call 1f24 - - global_registers[Spc] = 0; - 2870: 00800074 movhi r2,1 - 2874: 10908f04 addi r2,r2,16956 - 2878: 10000045 stb zero,1(r2) - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); - 287c: 0009883a mov r4,zero - 2880: 00013700 call 1370 - 2884: 01000044 movi r4,1 - 2888: 00013700 call 1370 - 288c: 01000084 movi r4,2 - 2890: 00013700 call 1370 - - // �v���O�������s���֑J�� - return RUN_PROC; - 2894: 00800084 movi r2,2 - 2898: e0bfff15 stw r2,-4(fp) - 289c: 00003606 br 2978 - } - - if (RUN_PROC == mode) { - 28a0: e0bffe17 ldw r2,-8(fp) - 28a4: 10800098 cmpnei r2,r2,2 - 28a8: 1000291e bne r2,zero,2950 - // ���߃t�F�b�` - inst_rec = inst_fetch(); - 28ac: 00017b80 call 17b8 - 28b0: e0bffb15 stw r2,-20(fp) - // ���߃f�R�[�h���s - inst_decode(inst_rec); - 28b4: e13ffb17 ldw r4,-20(fp) - 28b8: 00018040 call 1804 - // pc�\�� - { - char buf[5]; - sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); - 28bc: 00800074 movhi r2,1 - 28c0: 10908f04 addi r2,r2,16956 - 28c4: 10800043 ldbu r2,1(r2) - 28c8: 11803fcc andi r6,r2,255 - 28cc: e13ffc04 addi r4,fp,-16 - 28d0: 01400074 movhi r5,1 - 28d4: 297ff504 addi r5,r5,-44 - 28d8: 0002b640 call 2b64 - print_block("pc", 2, HEX6_7); - 28dc: 01000074 movhi r4,1 - 28e0: 213ff704 addi r4,r4,-36 - 28e4: 01400084 movi r5,2 - 28e8: 01800084 movi r6,2 - 28ec: 00011e00 call 11e0 - print_block(buf, 2, HEX4_5); - 28f0: e13ffc04 addi r4,fp,-16 - 28f4: 01400084 movi r5,2 - 28f8: 01800044 movi r6,1 - 28fc: 00011e00 call 11e0 - } - - // �f�o�b�N�p - if ( global_registers[Ssw_run] ) delay10ms(100U); - 2900: 00800074 movhi r2,1 - 2904: 10908f04 addi r2,r2,16956 - 2908: 10800343 ldbu r2,13(r2) - 290c: 10803fcc andi r2,r2,255 - 2910: 1080201c xori r2,r2,128 - 2914: 10bfe004 addi r2,r2,-128 - 2918: 1005003a cmpeq r2,r2,zero - 291c: 1000021e bne r2,zero,2928 - 2920: 01001904 movi r4,100 - 2924: 00024780 call 2478 - - // �v���O�����I������ - if (inst_rec.inst != INST_END) return RUN_PROC; - 2928: e0bffb17 ldw r2,-20(fp) - 292c: 108003cc andi r2,r2,15 - 2930: 1005003a cmpeq r2,r2,zero - 2934: 1000031e bne r2,zero,2944 - 2938: 00800084 movi r2,2 - 293c: e0bfff15 stw r2,-4(fp) - 2940: 00000d06 br 2978 - return RUN_TERM; - 2944: 008000c4 movi r2,3 - 2948: e0bfff15 stw r2,-4(fp) - 294c: 00000a06 br 2978 - } - - if (RUN_TERM == mode) { - 2950: e0bffe17 ldw r2,-8(fp) - 2954: 108000d8 cmpnei r2,r2,3 - 2958: 1000061e bne r2,zero,2974 - lcd_caret_reset(); - 295c: 0001ed40 call 1ed4 - lcd_print("Run...Exit"); - 2960: 01000074 movhi r4,1 - 2964: 213ff804 addi r4,r4,-32 - 2968: 0001f240 call 1f24 - return RUN_STOP; - 296c: e03fff15 stw zero,-4(fp) - 2970: 00000106 br 2978 - } - - // Default - return RUN_STOP; - 2974: e03fff15 stw zero,-4(fp) - 2978: e0bfff17 ldw r2,-4(fp) -} - 297c: e037883a mov sp,fp - 2980: dfc00117 ldw ra,4(sp) - 2984: df000017 ldw fp,0(sp) - 2988: dec00204 addi sp,sp,8 - 298c: f800283a ret - -00002990 : - */ -#include "sys_register.h" - -char global_registers[REG_MAX_COUNT]; - -void registers_init() { - 2990: defffe04 addi sp,sp,-8 - 2994: df000115 stw fp,4(sp) - 2998: df000104 addi fp,sp,4 - int i; - for (i = 0; i < REG_MAX_COUNT; i++) global_registers[i] = 0; - 299c: e03fff15 stw zero,-4(fp) - 29a0: 00000806 br 29c4 - 29a4: e0ffff17 ldw r3,-4(fp) - 29a8: 00800074 movhi r2,1 - 29ac: 10908f04 addi r2,r2,16956 - 29b0: 10c5883a add r2,r2,r3 - 29b4: 10000005 stb zero,0(r2) - 29b8: e0bfff17 ldw r2,-4(fp) - 29bc: 10800044 addi r2,r2,1 - 29c0: e0bfff15 stw r2,-4(fp) - 29c4: e0bfff17 ldw r2,-4(fp) - 29c8: 108003d0 cmplti r2,r2,15 - 29cc: 103ff51e bne r2,zero,29a4 -} - 29d0: e037883a mov sp,fp - 29d4: df000017 ldw fp,0(sp) - 29d8: dec00104 addi sp,sp,4 - 29dc: f800283a ret - -000029e0 : - 29e0: 29001b2e bgeu r5,r4,2a50 - 29e4: 28001a16 blt r5,zero,2a50 - 29e8: 00800044 movi r2,1 - 29ec: 0007883a mov r3,zero - 29f0: 01c007c4 movi r7,31 - 29f4: 00000306 br 2a04 - 29f8: 19c01326 beq r3,r7,2a48 - 29fc: 18c00044 addi r3,r3,1 - 2a00: 28000416 blt r5,zero,2a14 - 2a04: 294b883a add r5,r5,r5 - 2a08: 1085883a add r2,r2,r2 - 2a0c: 293ffa36 bltu r5,r4,29f8 - 2a10: 10000d26 beq r2,zero,2a48 - 2a14: 0007883a mov r3,zero - 2a18: 21400236 bltu r4,r5,2a24 - 2a1c: 2149c83a sub r4,r4,r5 - 2a20: 1886b03a or r3,r3,r2 - 2a24: 1004d07a srli r2,r2,1 - 2a28: 280ad07a srli r5,r5,1 - 2a2c: 103ffa1e bne r2,zero,2a18 - 2a30: 30000226 beq r6,zero,2a3c - 2a34: 2005883a mov r2,r4 - 2a38: f800283a ret - 2a3c: 1809883a mov r4,r3 - 2a40: 2005883a mov r2,r4 - 2a44: f800283a ret - 2a48: 0007883a mov r3,zero - 2a4c: 003ff806 br 2a30 - 2a50: 00800044 movi r2,1 - 2a54: 0007883a mov r3,zero - 2a58: 003fef06 br 2a18 - -00002a5c <__divsi3>: - 2a5c: defffe04 addi sp,sp,-8 - 2a60: dc000015 stw r16,0(sp) - 2a64: dfc00115 stw ra,4(sp) - 2a68: 0021883a mov r16,zero - 2a6c: 20000c16 blt r4,zero,2aa0 <__divsi3+0x44> - 2a70: 000d883a mov r6,zero - 2a74: 28000e16 blt r5,zero,2ab0 <__divsi3+0x54> - 2a78: 00029e00 call 29e0 - 2a7c: 1007883a mov r3,r2 - 2a80: 8005003a cmpeq r2,r16,zero - 2a84: 1000011e bne r2,zero,2a8c <__divsi3+0x30> - 2a88: 00c7c83a sub r3,zero,r3 - 2a8c: 1805883a mov r2,r3 - 2a90: dfc00117 ldw ra,4(sp) - 2a94: dc000017 ldw r16,0(sp) - 2a98: dec00204 addi sp,sp,8 - 2a9c: f800283a ret - 2aa0: 0109c83a sub r4,zero,r4 - 2aa4: 04000044 movi r16,1 - 2aa8: 000d883a mov r6,zero - 2aac: 283ff20e bge r5,zero,2a78 <__divsi3+0x1c> - 2ab0: 014bc83a sub r5,zero,r5 - 2ab4: 8021003a cmpeq r16,r16,zero - 2ab8: 003fef06 br 2a78 <__divsi3+0x1c> - -00002abc <__modsi3>: - 2abc: deffff04 addi sp,sp,-4 - 2ac0: dfc00015 stw ra,0(sp) - 2ac4: 01800044 movi r6,1 - 2ac8: 2807883a mov r3,r5 - 2acc: 20000416 blt r4,zero,2ae0 <__modsi3+0x24> - 2ad0: 28000c16 blt r5,zero,2b04 <__modsi3+0x48> - 2ad4: dfc00017 ldw ra,0(sp) - 2ad8: dec00104 addi sp,sp,4 - 2adc: 00029e01 jmpi 29e0 - 2ae0: 0109c83a sub r4,zero,r4 - 2ae4: 28000b16 blt r5,zero,2b14 <__modsi3+0x58> - 2ae8: 180b883a mov r5,r3 - 2aec: 01800044 movi r6,1 - 2af0: 00029e00 call 29e0 - 2af4: 0085c83a sub r2,zero,r2 - 2af8: dfc00017 ldw ra,0(sp) - 2afc: dec00104 addi sp,sp,4 - 2b00: f800283a ret - 2b04: 014bc83a sub r5,zero,r5 - 2b08: dfc00017 ldw ra,0(sp) - 2b0c: dec00104 addi sp,sp,4 - 2b10: 00029e01 jmpi 29e0 - 2b14: 0147c83a sub r3,zero,r5 - 2b18: 003ff306 br 2ae8 <__modsi3+0x2c> - -00002b1c <__udivsi3>: - 2b1c: 000d883a mov r6,zero - 2b20: 00029e01 jmpi 29e0 - -00002b24 <__umodsi3>: - 2b24: 01800044 movi r6,1 - 2b28: 00029e01 jmpi 29e0 - -00002b2c <__mulsi3>: - 2b2c: 20000a26 beq r4,zero,2b58 <__mulsi3+0x2c> - 2b30: 0007883a mov r3,zero - 2b34: 2080004c andi r2,r4,1 - 2b38: 1005003a cmpeq r2,r2,zero - 2b3c: 2008d07a srli r4,r4,1 - 2b40: 1000011e bne r2,zero,2b48 <__mulsi3+0x1c> - 2b44: 1947883a add r3,r3,r5 - 2b48: 294b883a add r5,r5,r5 - 2b4c: 203ff91e bne r4,zero,2b34 <__mulsi3+0x8> - 2b50: 1805883a mov r2,r3 - 2b54: f800283a ret - 2b58: 0007883a mov r3,zero - 2b5c: 1805883a mov r2,r3 - 2b60: f800283a ret - -00002b64 : - 2b64: deffe504 addi sp,sp,-108 - 2b68: 2013883a mov r9,r4 - 2b6c: dfc01815 stw ra,96(sp) - 2b70: d9801915 stw r6,100(sp) - 2b74: d9c01a15 stw r7,104(sp) - 2b78: d8801904 addi r2,sp,100 - 2b7c: d8800015 stw r2,0(sp) - 2b80: 00800074 movhi r2,1 - 2b84: 10884004 addi r2,r2,8448 - 2b88: 11000017 ldw r4,0(r2) - 2b8c: d9c00017 ldw r7,0(sp) - 2b90: 00808204 movi r2,520 - 2b94: 00e00034 movhi r3,32768 - 2b98: 18ffffc4 addi r3,r3,-1 - 2b9c: 280d883a mov r6,r5 - 2ba0: d880040d sth r2,16(sp) - 2ba4: d9400104 addi r5,sp,4 - 2ba8: 00bfffc4 movi r2,-1 - 2bac: d8c00615 stw r3,24(sp) - 2bb0: d8c00315 stw r3,12(sp) - 2bb4: da400515 stw r9,20(sp) - 2bb8: d880048d sth r2,18(sp) - 2bbc: da400115 stw r9,4(sp) - 2bc0: 0002d040 call 2d04 <___vfprintf_internal_r> - 2bc4: d8c00117 ldw r3,4(sp) - 2bc8: 18000005 stb zero,0(r3) - 2bcc: dfc01817 ldw ra,96(sp) - 2bd0: dec01b04 addi sp,sp,108 - 2bd4: f800283a ret - -00002bd8 <_sprintf_r>: - 2bd8: deffe604 addi sp,sp,-104 - 2bdc: 2813883a mov r9,r5 - 2be0: dfc01815 stw ra,96(sp) - 2be4: d9c01915 stw r7,100(sp) - 2be8: d8801904 addi r2,sp,100 - 2bec: d8800015 stw r2,0(sp) - 2bf0: 100f883a mov r7,r2 - 2bf4: 00808204 movi r2,520 - 2bf8: 00e00034 movhi r3,32768 - 2bfc: 18ffffc4 addi r3,r3,-1 - 2c00: d880040d sth r2,16(sp) - 2c04: d9400104 addi r5,sp,4 - 2c08: 00bfffc4 movi r2,-1 - 2c0c: d8c00615 stw r3,24(sp) - 2c10: d8c00315 stw r3,12(sp) - 2c14: da400515 stw r9,20(sp) - 2c18: d880048d sth r2,18(sp) - 2c1c: da400115 stw r9,4(sp) - 2c20: 0002d040 call 2d04 <___vfprintf_internal_r> - 2c24: d8c00117 ldw r3,4(sp) - 2c28: 18000005 stb zero,0(r3) - 2c2c: dfc01817 ldw ra,96(sp) - 2c30: dec01a04 addi sp,sp,104 - 2c34: f800283a ret - -00002c38 : - 2c38: 208000cc andi r2,r4,3 - 2c3c: 2011883a mov r8,r4 - 2c40: 1000161e bne r2,zero,2c9c - 2c44: 20c00017 ldw r3,0(r4) - 2c48: 017fbff4 movhi r5,65279 - 2c4c: 297fbfc4 addi r5,r5,-257 - 2c50: 01e02074 movhi r7,32897 - 2c54: 39e02004 addi r7,r7,-32640 - 2c58: 1945883a add r2,r3,r5 - 2c5c: 11c4703a and r2,r2,r7 - 2c60: 00c6303a nor r3,zero,r3 - 2c64: 1886703a and r3,r3,r2 - 2c68: 18000c1e bne r3,zero,2c9c - 2c6c: 280d883a mov r6,r5 - 2c70: 380b883a mov r5,r7 - 2c74: 21000104 addi r4,r4,4 - 2c78: 20800017 ldw r2,0(r4) - 2c7c: 1187883a add r3,r2,r6 - 2c80: 1946703a and r3,r3,r5 - 2c84: 0084303a nor r2,zero,r2 - 2c88: 10c4703a and r2,r2,r3 - 2c8c: 103ff926 beq r2,zero,2c74 - 2c90: 20800007 ldb r2,0(r4) - 2c94: 10000326 beq r2,zero,2ca4 - 2c98: 21000044 addi r4,r4,1 - 2c9c: 20800007 ldb r2,0(r4) - 2ca0: 103ffd1e bne r2,zero,2c98 - 2ca4: 2205c83a sub r2,r4,r8 - 2ca8: f800283a ret - -00002cac <__sprint_r>: - 2cac: 30800217 ldw r2,8(r6) - 2cb0: defffe04 addi sp,sp,-8 - 2cb4: dc000015 stw r16,0(sp) - 2cb8: dfc00115 stw ra,4(sp) - 2cbc: 3021883a mov r16,r6 - 2cc0: 0007883a mov r3,zero - 2cc4: 1000061e bne r2,zero,2ce0 <__sprint_r+0x34> - 2cc8: 1805883a mov r2,r3 - 2ccc: 30000115 stw zero,4(r6) - 2cd0: dfc00117 ldw ra,4(sp) - 2cd4: dc000017 ldw r16,0(sp) - 2cd8: dec00204 addi sp,sp,8 - 2cdc: f800283a ret - 2ce0: 0006e840 call 6e84 <__sfvwrite_r> - 2ce4: 1007883a mov r3,r2 - 2ce8: 1805883a mov r2,r3 - 2cec: 80000115 stw zero,4(r16) - 2cf0: 80000215 stw zero,8(r16) - 2cf4: dfc00117 ldw ra,4(sp) - 2cf8: dc000017 ldw r16,0(sp) - 2cfc: dec00204 addi sp,sp,8 - 2d00: f800283a ret - -00002d04 <___vfprintf_internal_r>: - 2d04: defea404 addi sp,sp,-1392 - 2d08: dd815815 stw r22,1376(sp) - 2d0c: dc015215 stw r16,1352(sp) - 2d10: d9c15115 stw r7,1348(sp) - 2d14: dfc15b15 stw ra,1388(sp) - 2d18: df015a15 stw fp,1384(sp) - 2d1c: ddc15915 stw r23,1380(sp) - 2d20: dd415715 stw r21,1372(sp) - 2d24: dd015615 stw r20,1368(sp) - 2d28: dcc15515 stw r19,1364(sp) - 2d2c: dc815415 stw r18,1360(sp) - 2d30: dc415315 stw r17,1356(sp) - 2d34: 282d883a mov r22,r5 - 2d38: 3021883a mov r16,r6 - 2d3c: d9014f15 stw r4,1340(sp) - 2d40: 00074a80 call 74a8 <_localeconv_r> - 2d44: 10800017 ldw r2,0(r2) - 2d48: d9c15117 ldw r7,1348(sp) - 2d4c: d8814915 stw r2,1316(sp) - 2d50: d8814f17 ldw r2,1340(sp) - 2d54: 10000226 beq r2,zero,2d60 <___vfprintf_internal_r+0x5c> - 2d58: 10800e17 ldw r2,56(r2) - 2d5c: 10020d26 beq r2,zero,3594 <___vfprintf_internal_r+0x890> - 2d60: b080030b ldhu r2,12(r22) - 2d64: 1080020c andi r2,r2,8 - 2d68: 10020e26 beq r2,zero,35a4 <___vfprintf_internal_r+0x8a0> - 2d6c: b0800417 ldw r2,16(r22) - 2d70: 10020c26 beq r2,zero,35a4 <___vfprintf_internal_r+0x8a0> - 2d74: b200030b ldhu r8,12(r22) - 2d78: 00800284 movi r2,10 - 2d7c: 40c0068c andi r3,r8,26 - 2d80: 18802f1e bne r3,r2,2e40 <___vfprintf_internal_r+0x13c> - 2d84: b080038f ldh r2,14(r22) - 2d88: 10002d16 blt r2,zero,2e40 <___vfprintf_internal_r+0x13c> - 2d8c: b240038b ldhu r9,14(r22) - 2d90: b2800717 ldw r10,28(r22) - 2d94: b2c00917 ldw r11,36(r22) - 2d98: d9014f17 ldw r4,1340(sp) - 2d9c: dc402904 addi r17,sp,164 - 2da0: d8804004 addi r2,sp,256 - 2da4: 00c10004 movi r3,1024 - 2da8: 423fff4c andi r8,r8,65533 - 2dac: 800d883a mov r6,r16 - 2db0: 880b883a mov r5,r17 - 2db4: da002c0d sth r8,176(sp) - 2db8: da402c8d sth r9,178(sp) - 2dbc: da803015 stw r10,192(sp) - 2dc0: dac03215 stw r11,200(sp) - 2dc4: d8802d15 stw r2,180(sp) - 2dc8: d8c02e15 stw r3,184(sp) - 2dcc: d8802915 stw r2,164(sp) - 2dd0: d8c02b15 stw r3,172(sp) - 2dd4: d8002f15 stw zero,188(sp) - 2dd8: 0002d040 call 2d04 <___vfprintf_internal_r> - 2ddc: d8814b15 stw r2,1324(sp) - 2de0: 10000416 blt r2,zero,2df4 <___vfprintf_internal_r+0xf0> - 2de4: d9014f17 ldw r4,1340(sp) - 2de8: 880b883a mov r5,r17 - 2dec: 00065200 call 6520 <_fflush_r> - 2df0: 1002321e bne r2,zero,36bc <___vfprintf_internal_r+0x9b8> - 2df4: d8802c0b ldhu r2,176(sp) - 2df8: 1080100c andi r2,r2,64 - 2dfc: 10000326 beq r2,zero,2e0c <___vfprintf_internal_r+0x108> - 2e00: b080030b ldhu r2,12(r22) - 2e04: 10801014 ori r2,r2,64 - 2e08: b080030d sth r2,12(r22) - 2e0c: d8814b17 ldw r2,1324(sp) - 2e10: dfc15b17 ldw ra,1388(sp) - 2e14: df015a17 ldw fp,1384(sp) - 2e18: ddc15917 ldw r23,1380(sp) - 2e1c: dd815817 ldw r22,1376(sp) - 2e20: dd415717 ldw r21,1372(sp) - 2e24: dd015617 ldw r20,1368(sp) - 2e28: dcc15517 ldw r19,1364(sp) - 2e2c: dc815417 ldw r18,1360(sp) - 2e30: dc415317 ldw r17,1356(sp) - 2e34: dc015217 ldw r16,1352(sp) - 2e38: dec15c04 addi sp,sp,1392 - 2e3c: f800283a ret - 2e40: 0005883a mov r2,zero - 2e44: 0007883a mov r3,zero - 2e48: dd401904 addi r21,sp,100 - 2e4c: d8814215 stw r2,1288(sp) - 2e50: 802f883a mov r23,r16 - 2e54: d8c14315 stw r3,1292(sp) - 2e58: d8014b15 stw zero,1324(sp) - 2e5c: d8014815 stw zero,1312(sp) - 2e60: d8014415 stw zero,1296(sp) - 2e64: d8014715 stw zero,1308(sp) - 2e68: dd400c15 stw r21,48(sp) - 2e6c: d8000e15 stw zero,56(sp) - 2e70: d8000d15 stw zero,52(sp) - 2e74: b8800007 ldb r2,0(r23) - 2e78: 10001926 beq r2,zero,2ee0 <___vfprintf_internal_r+0x1dc> - 2e7c: 00c00944 movi r3,37 - 2e80: 10c01726 beq r2,r3,2ee0 <___vfprintf_internal_r+0x1dc> - 2e84: b821883a mov r16,r23 - 2e88: 00000106 br 2e90 <___vfprintf_internal_r+0x18c> - 2e8c: 10c00326 beq r2,r3,2e9c <___vfprintf_internal_r+0x198> - 2e90: 84000044 addi r16,r16,1 - 2e94: 80800007 ldb r2,0(r16) - 2e98: 103ffc1e bne r2,zero,2e8c <___vfprintf_internal_r+0x188> - 2e9c: 85e7c83a sub r19,r16,r23 - 2ea0: 98000e26 beq r19,zero,2edc <___vfprintf_internal_r+0x1d8> - 2ea4: dc800e17 ldw r18,56(sp) - 2ea8: dc400d17 ldw r17,52(sp) - 2eac: 008001c4 movi r2,7 - 2eb0: 94e5883a add r18,r18,r19 - 2eb4: 8c400044 addi r17,r17,1 - 2eb8: adc00015 stw r23,0(r21) - 2ebc: dc800e15 stw r18,56(sp) - 2ec0: acc00115 stw r19,4(r21) - 2ec4: dc400d15 stw r17,52(sp) - 2ec8: 14428b16 blt r2,r17,38f8 <___vfprintf_internal_r+0xbf4> - 2ecc: ad400204 addi r21,r21,8 - 2ed0: d9014b17 ldw r4,1324(sp) - 2ed4: 24c9883a add r4,r4,r19 - 2ed8: d9014b15 stw r4,1324(sp) - 2edc: 802f883a mov r23,r16 - 2ee0: b8800007 ldb r2,0(r23) - 2ee4: 10013c26 beq r2,zero,33d8 <___vfprintf_internal_r+0x6d4> - 2ee8: bdc00044 addi r23,r23,1 - 2eec: d8000405 stb zero,16(sp) - 2ef0: b8c00007 ldb r3,0(r23) - 2ef4: 04ffffc4 movi r19,-1 - 2ef8: d8014c15 stw zero,1328(sp) - 2efc: d8014a15 stw zero,1320(sp) - 2f00: d8c14d15 stw r3,1332(sp) - 2f04: bdc00044 addi r23,r23,1 - 2f08: d9414d17 ldw r5,1332(sp) - 2f0c: 00801604 movi r2,88 - 2f10: 28fff804 addi r3,r5,-32 - 2f14: 10c06036 bltu r2,r3,3098 <___vfprintf_internal_r+0x394> - 2f18: 18c5883a add r2,r3,r3 - 2f1c: 1085883a add r2,r2,r2 - 2f20: 00c00034 movhi r3,0 - 2f24: 18cbcd04 addi r3,r3,12084 - 2f28: 10c5883a add r2,r2,r3 - 2f2c: 11000017 ldw r4,0(r2) - 2f30: 2000683a jmp r4 - 2f34: 00003ea8 cmpgeui zero,zero,250 - 2f38: 00003098 cmpnei zero,zero,194 - 2f3c: 00003098 cmpnei zero,zero,194 - 2f40: 00003e94 movui zero,250 - 2f44: 00003098 cmpnei zero,zero,194 - 2f48: 00003098 cmpnei zero,zero,194 - 2f4c: 00003098 cmpnei zero,zero,194 - 2f50: 00003098 cmpnei zero,zero,194 - 2f54: 00003098 cmpnei zero,zero,194 - 2f58: 00003098 cmpnei zero,zero,194 - 2f5c: 00003c74 movhi zero,241 - 2f60: 00003e84 movi zero,250 - 2f64: 00003098 cmpnei zero,zero,194 - 2f68: 00003c8c andi zero,zero,242 - 2f6c: 00003f2c andhi zero,zero,252 - 2f70: 00003098 cmpnei zero,zero,194 - 2f74: 00003f18 cmpnei zero,zero,252 - 2f78: 00003ed4 movui zero,251 - 2f7c: 00003ed4 movui zero,251 - 2f80: 00003ed4 movui zero,251 - 2f84: 00003ed4 movui zero,251 - 2f88: 00003ed4 movui zero,251 - 2f8c: 00003ed4 movui zero,251 - 2f90: 00003ed4 movui zero,251 - 2f94: 00003ed4 movui zero,251 - 2f98: 00003ed4 movui zero,251 - 2f9c: 00003098 cmpnei zero,zero,194 - 2fa0: 00003098 cmpnei zero,zero,194 - 2fa4: 00003098 cmpnei zero,zero,194 - 2fa8: 00003098 cmpnei zero,zero,194 - 2fac: 00003098 cmpnei zero,zero,194 - 2fb0: 00003098 cmpnei zero,zero,194 - 2fb4: 00003098 cmpnei zero,zero,194 - 2fb8: 00003098 cmpnei zero,zero,194 - 2fbc: 00003098 cmpnei zero,zero,194 - 2fc0: 00003098 cmpnei zero,zero,194 - 2fc4: 000036f0 cmpltui zero,zero,219 - 2fc8: 00003d5c xori zero,zero,245 - 2fcc: 00003098 cmpnei zero,zero,194 - 2fd0: 00003d5c xori zero,zero,245 - 2fd4: 00003098 cmpnei zero,zero,194 - 2fd8: 00003098 cmpnei zero,zero,194 - 2fdc: 00003098 cmpnei zero,zero,194 - 2fe0: 00003098 cmpnei zero,zero,194 - 2fe4: 00003ec0 call 3ec - 2fe8: 00003098 cmpnei zero,zero,194 - 2fec: 00003098 cmpnei zero,zero,194 - 2ff0: 000037a4 muli zero,zero,222 - 2ff4: 00003098 cmpnei zero,zero,194 - 2ff8: 00003098 cmpnei zero,zero,194 - 2ffc: 00003098 cmpnei zero,zero,194 - 3000: 00003098 cmpnei zero,zero,194 - 3004: 00003098 cmpnei zero,zero,194 - 3008: 000037f0 cmpltui zero,zero,223 - 300c: 00003098 cmpnei zero,zero,194 - 3010: 00003098 cmpnei zero,zero,194 - 3014: 00003e10 cmplti zero,zero,248 - 3018: 00003098 cmpnei zero,zero,194 - 301c: 00003098 cmpnei zero,zero,194 - 3020: 00003098 cmpnei zero,zero,194 - 3024: 00003098 cmpnei zero,zero,194 - 3028: 00003098 cmpnei zero,zero,194 - 302c: 00003098 cmpnei zero,zero,194 - 3030: 00003098 cmpnei zero,zero,194 - 3034: 00003098 cmpnei zero,zero,194 - 3038: 00003098 cmpnei zero,zero,194 - 303c: 00003098 cmpnei zero,zero,194 - 3040: 00003de4 muli zero,zero,247 - 3044: 000036fc xorhi zero,zero,219 - 3048: 00003d5c xori zero,zero,245 - 304c: 00003d5c xori zero,zero,245 - 3050: 00003d5c xori zero,zero,245 - 3054: 00003d48 cmpgei zero,zero,245 - 3058: 000036fc xorhi zero,zero,219 - 305c: 00003098 cmpnei zero,zero,194 - 3060: 00003098 cmpnei zero,zero,194 - 3064: 00003cd0 cmplti zero,zero,243 - 3068: 00003098 cmpnei zero,zero,194 - 306c: 00003ca0 cmpeqi zero,zero,242 - 3070: 000037b0 cmpltui zero,zero,222 - 3074: 00003d00 call 3d0 - 3078: 00003cec andhi zero,zero,243 - 307c: 00003098 cmpnei zero,zero,194 - 3080: 00003f94 movui zero,254 - 3084: 00003098 cmpnei zero,zero,194 - 3088: 000037fc xorhi zero,zero,223 - 308c: 00003098 cmpnei zero,zero,194 - 3090: 00003098 cmpnei zero,zero,194 - 3094: 00003e74 movhi zero,249 - 3098: d9014d17 ldw r4,1332(sp) - 309c: 2000ce26 beq r4,zero,33d8 <___vfprintf_internal_r+0x6d4> - 30a0: 01400044 movi r5,1 - 30a4: d9800f04 addi r6,sp,60 - 30a8: d9c14015 stw r7,1280(sp) - 30ac: d9414515 stw r5,1300(sp) - 30b0: d9814115 stw r6,1284(sp) - 30b4: 280f883a mov r7,r5 - 30b8: d9000f05 stb r4,60(sp) - 30bc: d8000405 stb zero,16(sp) - 30c0: d8014615 stw zero,1304(sp) - 30c4: d8c14c17 ldw r3,1328(sp) - 30c8: 1880008c andi r2,r3,2 - 30cc: 1005003a cmpeq r2,r2,zero - 30d0: d8815015 stw r2,1344(sp) - 30d4: 1000031e bne r2,zero,30e4 <___vfprintf_internal_r+0x3e0> - 30d8: d9014517 ldw r4,1300(sp) - 30dc: 21000084 addi r4,r4,2 - 30e0: d9014515 stw r4,1300(sp) - 30e4: d9414c17 ldw r5,1328(sp) - 30e8: 2940210c andi r5,r5,132 - 30ec: d9414e15 stw r5,1336(sp) - 30f0: 28002d1e bne r5,zero,31a8 <___vfprintf_internal_r+0x4a4> - 30f4: d9814a17 ldw r6,1320(sp) - 30f8: d8814517 ldw r2,1300(sp) - 30fc: 30a1c83a sub r16,r6,r2 - 3100: 0400290e bge zero,r16,31a8 <___vfprintf_internal_r+0x4a4> - 3104: 00800404 movi r2,16 - 3108: 14045e0e bge r2,r16,4284 <___vfprintf_internal_r+0x1580> - 310c: dc800e17 ldw r18,56(sp) - 3110: dc400d17 ldw r17,52(sp) - 3114: 1027883a mov r19,r2 - 3118: 07000074 movhi fp,1 - 311c: e700b784 addi fp,fp,734 - 3120: 050001c4 movi r20,7 - 3124: 00000306 br 3134 <___vfprintf_internal_r+0x430> - 3128: 843ffc04 addi r16,r16,-16 - 312c: ad400204 addi r21,r21,8 - 3130: 9c00130e bge r19,r16,3180 <___vfprintf_internal_r+0x47c> - 3134: 94800404 addi r18,r18,16 - 3138: 8c400044 addi r17,r17,1 - 313c: af000015 stw fp,0(r21) - 3140: acc00115 stw r19,4(r21) - 3144: dc800e15 stw r18,56(sp) - 3148: dc400d15 stw r17,52(sp) - 314c: a47ff60e bge r20,r17,3128 <___vfprintf_internal_r+0x424> - 3150: d9014f17 ldw r4,1340(sp) - 3154: b00b883a mov r5,r22 - 3158: d9800c04 addi r6,sp,48 - 315c: d9c15115 stw r7,1348(sp) - 3160: 0002cac0 call 2cac <__sprint_r> - 3164: d9c15117 ldw r7,1348(sp) - 3168: 10009e1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 316c: 843ffc04 addi r16,r16,-16 - 3170: dc800e17 ldw r18,56(sp) - 3174: dc400d17 ldw r17,52(sp) - 3178: dd401904 addi r21,sp,100 - 317c: 9c3fed16 blt r19,r16,3134 <___vfprintf_internal_r+0x430> - 3180: 9425883a add r18,r18,r16 - 3184: 8c400044 addi r17,r17,1 - 3188: 008001c4 movi r2,7 - 318c: af000015 stw fp,0(r21) - 3190: ac000115 stw r16,4(r21) - 3194: dc800e15 stw r18,56(sp) - 3198: dc400d15 stw r17,52(sp) - 319c: 1441f516 blt r2,r17,3974 <___vfprintf_internal_r+0xc70> - 31a0: ad400204 addi r21,r21,8 - 31a4: 00000206 br 31b0 <___vfprintf_internal_r+0x4ac> - 31a8: dc800e17 ldw r18,56(sp) - 31ac: dc400d17 ldw r17,52(sp) - 31b0: d8800407 ldb r2,16(sp) - 31b4: 10000b26 beq r2,zero,31e4 <___vfprintf_internal_r+0x4e0> - 31b8: 00800044 movi r2,1 - 31bc: 94800044 addi r18,r18,1 - 31c0: 8c400044 addi r17,r17,1 - 31c4: a8800115 stw r2,4(r21) - 31c8: d8c00404 addi r3,sp,16 - 31cc: 008001c4 movi r2,7 - 31d0: a8c00015 stw r3,0(r21) - 31d4: dc800e15 stw r18,56(sp) - 31d8: dc400d15 stw r17,52(sp) - 31dc: 1441da16 blt r2,r17,3948 <___vfprintf_internal_r+0xc44> - 31e0: ad400204 addi r21,r21,8 - 31e4: d9015017 ldw r4,1344(sp) - 31e8: 20000b1e bne r4,zero,3218 <___vfprintf_internal_r+0x514> - 31ec: d8800444 addi r2,sp,17 - 31f0: 94800084 addi r18,r18,2 - 31f4: 8c400044 addi r17,r17,1 - 31f8: a8800015 stw r2,0(r21) - 31fc: 00c00084 movi r3,2 - 3200: 008001c4 movi r2,7 - 3204: a8c00115 stw r3,4(r21) - 3208: dc800e15 stw r18,56(sp) - 320c: dc400d15 stw r17,52(sp) - 3210: 1441c216 blt r2,r17,391c <___vfprintf_internal_r+0xc18> - 3214: ad400204 addi r21,r21,8 - 3218: d9414e17 ldw r5,1336(sp) - 321c: 00802004 movi r2,128 - 3220: 2880b126 beq r5,r2,34e8 <___vfprintf_internal_r+0x7e4> - 3224: d8c14617 ldw r3,1304(sp) - 3228: 19e1c83a sub r16,r3,r7 - 322c: 0400260e bge zero,r16,32c8 <___vfprintf_internal_r+0x5c4> - 3230: 00800404 movi r2,16 - 3234: 1403cf0e bge r2,r16,4174 <___vfprintf_internal_r+0x1470> - 3238: 1027883a mov r19,r2 - 323c: 07000074 movhi fp,1 - 3240: e700b384 addi fp,fp,718 - 3244: 050001c4 movi r20,7 - 3248: 00000306 br 3258 <___vfprintf_internal_r+0x554> - 324c: 843ffc04 addi r16,r16,-16 - 3250: ad400204 addi r21,r21,8 - 3254: 9c00130e bge r19,r16,32a4 <___vfprintf_internal_r+0x5a0> - 3258: 94800404 addi r18,r18,16 - 325c: 8c400044 addi r17,r17,1 - 3260: af000015 stw fp,0(r21) - 3264: acc00115 stw r19,4(r21) - 3268: dc800e15 stw r18,56(sp) - 326c: dc400d15 stw r17,52(sp) - 3270: a47ff60e bge r20,r17,324c <___vfprintf_internal_r+0x548> - 3274: d9014f17 ldw r4,1340(sp) - 3278: b00b883a mov r5,r22 - 327c: d9800c04 addi r6,sp,48 - 3280: d9c15115 stw r7,1348(sp) - 3284: 0002cac0 call 2cac <__sprint_r> - 3288: d9c15117 ldw r7,1348(sp) - 328c: 1000551e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3290: 843ffc04 addi r16,r16,-16 - 3294: dc800e17 ldw r18,56(sp) - 3298: dc400d17 ldw r17,52(sp) - 329c: dd401904 addi r21,sp,100 - 32a0: 9c3fed16 blt r19,r16,3258 <___vfprintf_internal_r+0x554> - 32a4: 9425883a add r18,r18,r16 - 32a8: 8c400044 addi r17,r17,1 - 32ac: 008001c4 movi r2,7 - 32b0: af000015 stw fp,0(r21) - 32b4: ac000115 stw r16,4(r21) - 32b8: dc800e15 stw r18,56(sp) - 32bc: dc400d15 stw r17,52(sp) - 32c0: 14418216 blt r2,r17,38cc <___vfprintf_internal_r+0xbc8> - 32c4: ad400204 addi r21,r21,8 - 32c8: d9014c17 ldw r4,1328(sp) - 32cc: 2080400c andi r2,r4,256 - 32d0: 10004a1e bne r2,zero,33fc <___vfprintf_internal_r+0x6f8> - 32d4: d9414117 ldw r5,1284(sp) - 32d8: 91e5883a add r18,r18,r7 - 32dc: 8c400044 addi r17,r17,1 - 32e0: 008001c4 movi r2,7 - 32e4: a9400015 stw r5,0(r21) - 32e8: a9c00115 stw r7,4(r21) - 32ec: dc800e15 stw r18,56(sp) - 32f0: dc400d15 stw r17,52(sp) - 32f4: 14416716 blt r2,r17,3894 <___vfprintf_internal_r+0xb90> - 32f8: a8c00204 addi r3,r21,8 - 32fc: d9814c17 ldw r6,1328(sp) - 3300: 3080010c andi r2,r6,4 - 3304: 10002826 beq r2,zero,33a8 <___vfprintf_internal_r+0x6a4> - 3308: d8814a17 ldw r2,1320(sp) - 330c: d9014517 ldw r4,1300(sp) - 3310: 1121c83a sub r16,r2,r4 - 3314: 0400240e bge zero,r16,33a8 <___vfprintf_internal_r+0x6a4> - 3318: 00800404 movi r2,16 - 331c: 1404550e bge r2,r16,4474 <___vfprintf_internal_r+0x1770> - 3320: dc400d17 ldw r17,52(sp) - 3324: 1027883a mov r19,r2 - 3328: 07000074 movhi fp,1 - 332c: e700b784 addi fp,fp,734 - 3330: 050001c4 movi r20,7 - 3334: 00000306 br 3344 <___vfprintf_internal_r+0x640> - 3338: 843ffc04 addi r16,r16,-16 - 333c: 18c00204 addi r3,r3,8 - 3340: 9c00110e bge r19,r16,3388 <___vfprintf_internal_r+0x684> - 3344: 94800404 addi r18,r18,16 - 3348: 8c400044 addi r17,r17,1 - 334c: 1f000015 stw fp,0(r3) - 3350: 1cc00115 stw r19,4(r3) - 3354: dc800e15 stw r18,56(sp) - 3358: dc400d15 stw r17,52(sp) - 335c: a47ff60e bge r20,r17,3338 <___vfprintf_internal_r+0x634> - 3360: d9014f17 ldw r4,1340(sp) - 3364: b00b883a mov r5,r22 - 3368: d9800c04 addi r6,sp,48 - 336c: 0002cac0 call 2cac <__sprint_r> - 3370: 10001c1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3374: 843ffc04 addi r16,r16,-16 - 3378: dc800e17 ldw r18,56(sp) - 337c: dc400d17 ldw r17,52(sp) - 3380: d8c01904 addi r3,sp,100 - 3384: 9c3fef16 blt r19,r16,3344 <___vfprintf_internal_r+0x640> - 3388: 9425883a add r18,r18,r16 - 338c: 8c400044 addi r17,r17,1 - 3390: 008001c4 movi r2,7 - 3394: 1f000015 stw fp,0(r3) - 3398: 1c000115 stw r16,4(r3) - 339c: dc800e15 stw r18,56(sp) - 33a0: dc400d15 stw r17,52(sp) - 33a4: 1440cb16 blt r2,r17,36d4 <___vfprintf_internal_r+0x9d0> - 33a8: d8814a17 ldw r2,1320(sp) - 33ac: d9414517 ldw r5,1300(sp) - 33b0: 1140010e bge r2,r5,33b8 <___vfprintf_internal_r+0x6b4> - 33b4: 2805883a mov r2,r5 - 33b8: d9814b17 ldw r6,1324(sp) - 33bc: 308d883a add r6,r6,r2 - 33c0: d9814b15 stw r6,1324(sp) - 33c4: 90013b1e bne r18,zero,38b4 <___vfprintf_internal_r+0xbb0> - 33c8: d9c14017 ldw r7,1280(sp) - 33cc: dd401904 addi r21,sp,100 - 33d0: d8000d15 stw zero,52(sp) - 33d4: 003ea706 br 2e74 <___vfprintf_internal_r+0x170> - 33d8: d8800e17 ldw r2,56(sp) - 33dc: 1005451e bne r2,zero,48f4 <___vfprintf_internal_r+0x1bf0> - 33e0: d8000d15 stw zero,52(sp) - 33e4: b080030b ldhu r2,12(r22) - 33e8: 1080100c andi r2,r2,64 - 33ec: 103e8726 beq r2,zero,2e0c <___vfprintf_internal_r+0x108> - 33f0: 00bfffc4 movi r2,-1 - 33f4: d8814b15 stw r2,1324(sp) - 33f8: 003e8406 br 2e0c <___vfprintf_internal_r+0x108> - 33fc: d9814d17 ldw r6,1332(sp) - 3400: 00801944 movi r2,101 - 3404: 11806e16 blt r2,r6,35c0 <___vfprintf_internal_r+0x8bc> - 3408: d9414717 ldw r5,1308(sp) - 340c: 00c00044 movi r3,1 - 3410: 1943490e bge r3,r5,4138 <___vfprintf_internal_r+0x1434> - 3414: d8814117 ldw r2,1284(sp) - 3418: 94800044 addi r18,r18,1 - 341c: 8c400044 addi r17,r17,1 - 3420: a8800015 stw r2,0(r21) - 3424: 008001c4 movi r2,7 - 3428: a8c00115 stw r3,4(r21) - 342c: dc800e15 stw r18,56(sp) - 3430: dc400d15 stw r17,52(sp) - 3434: 1441ca16 blt r2,r17,3b60 <___vfprintf_internal_r+0xe5c> - 3438: a8c00204 addi r3,r21,8 - 343c: d9014917 ldw r4,1316(sp) - 3440: 00800044 movi r2,1 - 3444: 94800044 addi r18,r18,1 - 3448: 8c400044 addi r17,r17,1 - 344c: 18800115 stw r2,4(r3) - 3450: 008001c4 movi r2,7 - 3454: 19000015 stw r4,0(r3) - 3458: dc800e15 stw r18,56(sp) - 345c: dc400d15 stw r17,52(sp) - 3460: 1441b616 blt r2,r17,3b3c <___vfprintf_internal_r+0xe38> - 3464: 1cc00204 addi r19,r3,8 - 3468: d9014217 ldw r4,1288(sp) - 346c: d9414317 ldw r5,1292(sp) - 3470: 000d883a mov r6,zero - 3474: 000f883a mov r7,zero - 3478: 000b7b80 call b7b8 <__nedf2> - 347c: 10017426 beq r2,zero,3a50 <___vfprintf_internal_r+0xd4c> - 3480: d9414717 ldw r5,1308(sp) - 3484: d9814117 ldw r6,1284(sp) - 3488: 8c400044 addi r17,r17,1 - 348c: 2c85883a add r2,r5,r18 - 3490: 14bfffc4 addi r18,r2,-1 - 3494: 28bfffc4 addi r2,r5,-1 - 3498: 30c00044 addi r3,r6,1 - 349c: 98800115 stw r2,4(r19) - 34a0: 008001c4 movi r2,7 - 34a4: 98c00015 stw r3,0(r19) - 34a8: dc800e15 stw r18,56(sp) - 34ac: dc400d15 stw r17,52(sp) - 34b0: 14418e16 blt r2,r17,3aec <___vfprintf_internal_r+0xde8> - 34b4: 9cc00204 addi r19,r19,8 - 34b8: d9414817 ldw r5,1312(sp) - 34bc: d8800804 addi r2,sp,32 - 34c0: 8c400044 addi r17,r17,1 - 34c4: 9165883a add r18,r18,r5 - 34c8: 98800015 stw r2,0(r19) - 34cc: 008001c4 movi r2,7 - 34d0: 99400115 stw r5,4(r19) - 34d4: dc800e15 stw r18,56(sp) - 34d8: dc400d15 stw r17,52(sp) - 34dc: 1440ed16 blt r2,r17,3894 <___vfprintf_internal_r+0xb90> - 34e0: 98c00204 addi r3,r19,8 - 34e4: 003f8506 br 32fc <___vfprintf_internal_r+0x5f8> - 34e8: d9814a17 ldw r6,1320(sp) - 34ec: d8814517 ldw r2,1300(sp) - 34f0: 30a1c83a sub r16,r6,r2 - 34f4: 043f4b0e bge zero,r16,3224 <___vfprintf_internal_r+0x520> - 34f8: 00800404 movi r2,16 - 34fc: 14043a0e bge r2,r16,45e8 <___vfprintf_internal_r+0x18e4> - 3500: 1027883a mov r19,r2 - 3504: 07000074 movhi fp,1 - 3508: e700b384 addi fp,fp,718 - 350c: 050001c4 movi r20,7 - 3510: 00000306 br 3520 <___vfprintf_internal_r+0x81c> - 3514: 843ffc04 addi r16,r16,-16 - 3518: ad400204 addi r21,r21,8 - 351c: 9c00130e bge r19,r16,356c <___vfprintf_internal_r+0x868> - 3520: 94800404 addi r18,r18,16 - 3524: 8c400044 addi r17,r17,1 - 3528: af000015 stw fp,0(r21) - 352c: acc00115 stw r19,4(r21) - 3530: dc800e15 stw r18,56(sp) - 3534: dc400d15 stw r17,52(sp) - 3538: a47ff60e bge r20,r17,3514 <___vfprintf_internal_r+0x810> - 353c: d9014f17 ldw r4,1340(sp) - 3540: b00b883a mov r5,r22 - 3544: d9800c04 addi r6,sp,48 - 3548: d9c15115 stw r7,1348(sp) - 354c: 0002cac0 call 2cac <__sprint_r> - 3550: d9c15117 ldw r7,1348(sp) - 3554: 103fa31e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3558: 843ffc04 addi r16,r16,-16 - 355c: dc800e17 ldw r18,56(sp) - 3560: dc400d17 ldw r17,52(sp) - 3564: dd401904 addi r21,sp,100 - 3568: 9c3fed16 blt r19,r16,3520 <___vfprintf_internal_r+0x81c> - 356c: 9425883a add r18,r18,r16 - 3570: 8c400044 addi r17,r17,1 - 3574: 008001c4 movi r2,7 - 3578: af000015 stw fp,0(r21) - 357c: ac000115 stw r16,4(r21) - 3580: dc800e15 stw r18,56(sp) - 3584: dc400d15 stw r17,52(sp) - 3588: 14416116 blt r2,r17,3b10 <___vfprintf_internal_r+0xe0c> - 358c: ad400204 addi r21,r21,8 - 3590: 003f2406 br 3224 <___vfprintf_internal_r+0x520> - 3594: d9014f17 ldw r4,1340(sp) - 3598: 00067b80 call 67b8 <__sinit> - 359c: d9c15117 ldw r7,1348(sp) - 35a0: 003def06 br 2d60 <___vfprintf_internal_r+0x5c> - 35a4: d9014f17 ldw r4,1340(sp) - 35a8: b00b883a mov r5,r22 - 35ac: d9c15115 stw r7,1348(sp) - 35b0: 0004bec0 call 4bec <__swsetup_r> - 35b4: d9c15117 ldw r7,1348(sp) - 35b8: 103dee26 beq r2,zero,2d74 <___vfprintf_internal_r+0x70> - 35bc: 003f8c06 br 33f0 <___vfprintf_internal_r+0x6ec> - 35c0: d9014217 ldw r4,1288(sp) - 35c4: d9414317 ldw r5,1292(sp) - 35c8: 000d883a mov r6,zero - 35cc: 000f883a mov r7,zero - 35d0: 000b7300 call b730 <__eqdf2> - 35d4: 1000f21e bne r2,zero,39a0 <___vfprintf_internal_r+0xc9c> - 35d8: 00800074 movhi r2,1 - 35dc: 1080b304 addi r2,r2,716 - 35e0: 94800044 addi r18,r18,1 - 35e4: 8c400044 addi r17,r17,1 - 35e8: a8800015 stw r2,0(r21) - 35ec: 00c00044 movi r3,1 - 35f0: 008001c4 movi r2,7 - 35f4: a8c00115 stw r3,4(r21) - 35f8: dc800e15 stw r18,56(sp) - 35fc: dc400d15 stw r17,52(sp) - 3600: 14430016 blt r2,r17,4204 <___vfprintf_internal_r+0x1500> - 3604: a8c00204 addi r3,r21,8 - 3608: d8800517 ldw r2,20(sp) - 360c: d9014717 ldw r4,1308(sp) - 3610: 11015c0e bge r2,r4,3b84 <___vfprintf_internal_r+0xe80> - 3614: dc400d17 ldw r17,52(sp) - 3618: d9814917 ldw r6,1316(sp) - 361c: 00800044 movi r2,1 - 3620: 94800044 addi r18,r18,1 - 3624: 8c400044 addi r17,r17,1 - 3628: 18800115 stw r2,4(r3) - 362c: 008001c4 movi r2,7 - 3630: 19800015 stw r6,0(r3) - 3634: dc800e15 stw r18,56(sp) - 3638: dc400d15 stw r17,52(sp) - 363c: 14431616 blt r2,r17,4298 <___vfprintf_internal_r+0x1594> - 3640: 18c00204 addi r3,r3,8 - 3644: d8814717 ldw r2,1308(sp) - 3648: 143fffc4 addi r16,r2,-1 - 364c: 043f2b0e bge zero,r16,32fc <___vfprintf_internal_r+0x5f8> - 3650: 00800404 movi r2,16 - 3654: 1402a80e bge r2,r16,40f8 <___vfprintf_internal_r+0x13f4> - 3658: dc400d17 ldw r17,52(sp) - 365c: 1027883a mov r19,r2 - 3660: 07000074 movhi fp,1 - 3664: e700b384 addi fp,fp,718 - 3668: 050001c4 movi r20,7 - 366c: 00000306 br 367c <___vfprintf_internal_r+0x978> - 3670: 18c00204 addi r3,r3,8 - 3674: 843ffc04 addi r16,r16,-16 - 3678: 9c02a20e bge r19,r16,4104 <___vfprintf_internal_r+0x1400> - 367c: 94800404 addi r18,r18,16 - 3680: 8c400044 addi r17,r17,1 - 3684: 1f000015 stw fp,0(r3) - 3688: 1cc00115 stw r19,4(r3) - 368c: dc800e15 stw r18,56(sp) - 3690: dc400d15 stw r17,52(sp) - 3694: a47ff60e bge r20,r17,3670 <___vfprintf_internal_r+0x96c> - 3698: d9014f17 ldw r4,1340(sp) - 369c: b00b883a mov r5,r22 - 36a0: d9800c04 addi r6,sp,48 - 36a4: 0002cac0 call 2cac <__sprint_r> - 36a8: 103f4e1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 36ac: dc800e17 ldw r18,56(sp) - 36b0: dc400d17 ldw r17,52(sp) - 36b4: d8c01904 addi r3,sp,100 - 36b8: 003fee06 br 3674 <___vfprintf_internal_r+0x970> - 36bc: d8802c0b ldhu r2,176(sp) - 36c0: 00ffffc4 movi r3,-1 - 36c4: d8c14b15 stw r3,1324(sp) - 36c8: 1080100c andi r2,r2,64 - 36cc: 103dcc1e bne r2,zero,2e00 <___vfprintf_internal_r+0xfc> - 36d0: 003dce06 br 2e0c <___vfprintf_internal_r+0x108> - 36d4: d9014f17 ldw r4,1340(sp) - 36d8: b00b883a mov r5,r22 - 36dc: d9800c04 addi r6,sp,48 - 36e0: 0002cac0 call 2cac <__sprint_r> - 36e4: 103f3f1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 36e8: dc800e17 ldw r18,56(sp) - 36ec: 003f2e06 br 33a8 <___vfprintf_internal_r+0x6a4> - 36f0: d9414c17 ldw r5,1328(sp) - 36f4: 29400414 ori r5,r5,16 - 36f8: d9414c15 stw r5,1328(sp) - 36fc: d9814c17 ldw r6,1328(sp) - 3700: 3080080c andi r2,r6,32 - 3704: 10014f1e bne r2,zero,3c44 <___vfprintf_internal_r+0xf40> - 3708: d8c14c17 ldw r3,1328(sp) - 370c: 1880040c andi r2,r3,16 - 3710: 1002f01e bne r2,zero,42d4 <___vfprintf_internal_r+0x15d0> - 3714: d9014c17 ldw r4,1328(sp) - 3718: 2080100c andi r2,r4,64 - 371c: 1002ed26 beq r2,zero,42d4 <___vfprintf_internal_r+0x15d0> - 3720: 3880000f ldh r2,0(r7) - 3724: 39c00104 addi r7,r7,4 - 3728: d9c14015 stw r7,1280(sp) - 372c: 1023d7fa srai r17,r2,31 - 3730: 1021883a mov r16,r2 - 3734: 88037816 blt r17,zero,4518 <___vfprintf_internal_r+0x1814> - 3738: 01000044 movi r4,1 - 373c: 98000416 blt r19,zero,3750 <___vfprintf_internal_r+0xa4c> - 3740: d8c14c17 ldw r3,1328(sp) - 3744: 00bfdfc4 movi r2,-129 - 3748: 1886703a and r3,r3,r2 - 374c: d8c14c15 stw r3,1328(sp) - 3750: 8444b03a or r2,r16,r17 - 3754: 10022c1e bne r2,zero,4008 <___vfprintf_internal_r+0x1304> - 3758: 98022b1e bne r19,zero,4008 <___vfprintf_internal_r+0x1304> - 375c: 20803fcc andi r2,r4,255 - 3760: 1002a126 beq r2,zero,41e8 <___vfprintf_internal_r+0x14e4> - 3764: d8c01904 addi r3,sp,100 - 3768: dd000f04 addi r20,sp,60 - 376c: d8c14115 stw r3,1284(sp) - 3770: d8c14117 ldw r3,1284(sp) - 3774: dcc14515 stw r19,1300(sp) - 3778: a0c5c83a sub r2,r20,r3 - 377c: 11c00a04 addi r7,r2,40 - 3780: 99c0010e bge r19,r7,3788 <___vfprintf_internal_r+0xa84> - 3784: d9c14515 stw r7,1300(sp) - 3788: dcc14615 stw r19,1304(sp) - 378c: d8800407 ldb r2,16(sp) - 3790: 103e4c26 beq r2,zero,30c4 <___vfprintf_internal_r+0x3c0> - 3794: d8814517 ldw r2,1300(sp) - 3798: 10800044 addi r2,r2,1 - 379c: d8814515 stw r2,1300(sp) - 37a0: 003e4806 br 30c4 <___vfprintf_internal_r+0x3c0> - 37a4: d9814c17 ldw r6,1328(sp) - 37a8: 31800414 ori r6,r6,16 - 37ac: d9814c15 stw r6,1328(sp) - 37b0: d8c14c17 ldw r3,1328(sp) - 37b4: 1880080c andi r2,r3,32 - 37b8: 1001271e bne r2,zero,3c58 <___vfprintf_internal_r+0xf54> - 37bc: d9414c17 ldw r5,1328(sp) - 37c0: 2880040c andi r2,r5,16 - 37c4: 1002bc1e bne r2,zero,42b8 <___vfprintf_internal_r+0x15b4> - 37c8: d9814c17 ldw r6,1328(sp) - 37cc: 3080100c andi r2,r6,64 - 37d0: 1002b926 beq r2,zero,42b8 <___vfprintf_internal_r+0x15b4> - 37d4: 3c00000b ldhu r16,0(r7) - 37d8: 0009883a mov r4,zero - 37dc: 39c00104 addi r7,r7,4 - 37e0: 0023883a mov r17,zero - 37e4: d9c14015 stw r7,1280(sp) - 37e8: d8000405 stb zero,16(sp) - 37ec: 003fd306 br 373c <___vfprintf_internal_r+0xa38> - 37f0: d9014c17 ldw r4,1328(sp) - 37f4: 21000414 ori r4,r4,16 - 37f8: d9014c15 stw r4,1328(sp) - 37fc: d9414c17 ldw r5,1328(sp) - 3800: 2880080c andi r2,r5,32 - 3804: 1001081e bne r2,zero,3c28 <___vfprintf_internal_r+0xf24> - 3808: d8c14c17 ldw r3,1328(sp) - 380c: 1880040c andi r2,r3,16 - 3810: 1002b61e bne r2,zero,42ec <___vfprintf_internal_r+0x15e8> - 3814: d9014c17 ldw r4,1328(sp) - 3818: 2080100c andi r2,r4,64 - 381c: 1002b326 beq r2,zero,42ec <___vfprintf_internal_r+0x15e8> - 3820: 3c00000b ldhu r16,0(r7) - 3824: 01000044 movi r4,1 - 3828: 39c00104 addi r7,r7,4 - 382c: 0023883a mov r17,zero - 3830: d9c14015 stw r7,1280(sp) - 3834: d8000405 stb zero,16(sp) - 3838: 003fc006 br 373c <___vfprintf_internal_r+0xa38> - 383c: d9014f17 ldw r4,1340(sp) - 3840: b00b883a mov r5,r22 - 3844: d9800c04 addi r6,sp,48 - 3848: 0002cac0 call 2cac <__sprint_r> - 384c: 103ee51e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3850: dc800e17 ldw r18,56(sp) - 3854: d8c01904 addi r3,sp,100 - 3858: d9814c17 ldw r6,1328(sp) - 385c: 3080004c andi r2,r6,1 - 3860: 1005003a cmpeq r2,r2,zero - 3864: 103ea51e bne r2,zero,32fc <___vfprintf_internal_r+0x5f8> - 3868: 00800044 movi r2,1 - 386c: dc400d17 ldw r17,52(sp) - 3870: 18800115 stw r2,4(r3) - 3874: d8814917 ldw r2,1316(sp) - 3878: 94800044 addi r18,r18,1 - 387c: 8c400044 addi r17,r17,1 - 3880: 18800015 stw r2,0(r3) - 3884: 008001c4 movi r2,7 - 3888: dc800e15 stw r18,56(sp) - 388c: dc400d15 stw r17,52(sp) - 3890: 1442240e bge r2,r17,4124 <___vfprintf_internal_r+0x1420> - 3894: d9014f17 ldw r4,1340(sp) - 3898: b00b883a mov r5,r22 - 389c: d9800c04 addi r6,sp,48 - 38a0: 0002cac0 call 2cac <__sprint_r> - 38a4: 103ecf1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 38a8: dc800e17 ldw r18,56(sp) - 38ac: d8c01904 addi r3,sp,100 - 38b0: 003e9206 br 32fc <___vfprintf_internal_r+0x5f8> - 38b4: d9014f17 ldw r4,1340(sp) - 38b8: b00b883a mov r5,r22 - 38bc: d9800c04 addi r6,sp,48 - 38c0: 0002cac0 call 2cac <__sprint_r> - 38c4: 103ec026 beq r2,zero,33c8 <___vfprintf_internal_r+0x6c4> - 38c8: 003ec606 br 33e4 <___vfprintf_internal_r+0x6e0> - 38cc: d9014f17 ldw r4,1340(sp) - 38d0: b00b883a mov r5,r22 - 38d4: d9800c04 addi r6,sp,48 - 38d8: d9c15115 stw r7,1348(sp) - 38dc: 0002cac0 call 2cac <__sprint_r> - 38e0: d9c15117 ldw r7,1348(sp) - 38e4: 103ebf1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 38e8: dc800e17 ldw r18,56(sp) - 38ec: dc400d17 ldw r17,52(sp) - 38f0: dd401904 addi r21,sp,100 - 38f4: 003e7406 br 32c8 <___vfprintf_internal_r+0x5c4> - 38f8: d9014f17 ldw r4,1340(sp) - 38fc: b00b883a mov r5,r22 - 3900: d9800c04 addi r6,sp,48 - 3904: d9c15115 stw r7,1348(sp) - 3908: 0002cac0 call 2cac <__sprint_r> - 390c: d9c15117 ldw r7,1348(sp) - 3910: 103eb41e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3914: dd401904 addi r21,sp,100 - 3918: 003d6d06 br 2ed0 <___vfprintf_internal_r+0x1cc> - 391c: d9014f17 ldw r4,1340(sp) - 3920: b00b883a mov r5,r22 - 3924: d9800c04 addi r6,sp,48 - 3928: d9c15115 stw r7,1348(sp) - 392c: 0002cac0 call 2cac <__sprint_r> - 3930: d9c15117 ldw r7,1348(sp) - 3934: 103eab1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3938: dc800e17 ldw r18,56(sp) - 393c: dc400d17 ldw r17,52(sp) - 3940: dd401904 addi r21,sp,100 - 3944: 003e3406 br 3218 <___vfprintf_internal_r+0x514> - 3948: d9014f17 ldw r4,1340(sp) - 394c: b00b883a mov r5,r22 - 3950: d9800c04 addi r6,sp,48 - 3954: d9c15115 stw r7,1348(sp) - 3958: 0002cac0 call 2cac <__sprint_r> - 395c: d9c15117 ldw r7,1348(sp) - 3960: 103ea01e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3964: dc800e17 ldw r18,56(sp) - 3968: dc400d17 ldw r17,52(sp) - 396c: dd401904 addi r21,sp,100 - 3970: 003e1c06 br 31e4 <___vfprintf_internal_r+0x4e0> - 3974: d9014f17 ldw r4,1340(sp) - 3978: b00b883a mov r5,r22 - 397c: d9800c04 addi r6,sp,48 - 3980: d9c15115 stw r7,1348(sp) - 3984: 0002cac0 call 2cac <__sprint_r> - 3988: d9c15117 ldw r7,1348(sp) - 398c: 103e951e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3990: dc800e17 ldw r18,56(sp) - 3994: dc400d17 ldw r17,52(sp) - 3998: dd401904 addi r21,sp,100 - 399c: 003e0406 br 31b0 <___vfprintf_internal_r+0x4ac> - 39a0: d9000517 ldw r4,20(sp) - 39a4: 0102580e bge zero,r4,4308 <___vfprintf_internal_r+0x1604> - 39a8: d9814717 ldw r6,1308(sp) - 39ac: 21807a16 blt r4,r6,3b98 <___vfprintf_internal_r+0xe94> - 39b0: d8814117 ldw r2,1284(sp) - 39b4: 91a5883a add r18,r18,r6 - 39b8: 8c400044 addi r17,r17,1 - 39bc: a8800015 stw r2,0(r21) - 39c0: 008001c4 movi r2,7 - 39c4: a9800115 stw r6,4(r21) - 39c8: dc800e15 stw r18,56(sp) - 39cc: dc400d15 stw r17,52(sp) - 39d0: 1442fc16 blt r2,r17,45c4 <___vfprintf_internal_r+0x18c0> - 39d4: a8c00204 addi r3,r21,8 - 39d8: d9414717 ldw r5,1308(sp) - 39dc: 2161c83a sub r16,r4,r5 - 39e0: 043f9d0e bge zero,r16,3858 <___vfprintf_internal_r+0xb54> - 39e4: 00800404 movi r2,16 - 39e8: 1402190e bge r2,r16,4250 <___vfprintf_internal_r+0x154c> - 39ec: dc400d17 ldw r17,52(sp) - 39f0: 1027883a mov r19,r2 - 39f4: 07000074 movhi fp,1 - 39f8: e700b384 addi fp,fp,718 - 39fc: 050001c4 movi r20,7 - 3a00: 00000306 br 3a10 <___vfprintf_internal_r+0xd0c> - 3a04: 18c00204 addi r3,r3,8 - 3a08: 843ffc04 addi r16,r16,-16 - 3a0c: 9c02130e bge r19,r16,425c <___vfprintf_internal_r+0x1558> - 3a10: 94800404 addi r18,r18,16 - 3a14: 8c400044 addi r17,r17,1 - 3a18: 1f000015 stw fp,0(r3) - 3a1c: 1cc00115 stw r19,4(r3) - 3a20: dc800e15 stw r18,56(sp) - 3a24: dc400d15 stw r17,52(sp) - 3a28: a47ff60e bge r20,r17,3a04 <___vfprintf_internal_r+0xd00> - 3a2c: d9014f17 ldw r4,1340(sp) - 3a30: b00b883a mov r5,r22 - 3a34: d9800c04 addi r6,sp,48 - 3a38: 0002cac0 call 2cac <__sprint_r> - 3a3c: 103e691e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3a40: dc800e17 ldw r18,56(sp) - 3a44: dc400d17 ldw r17,52(sp) - 3a48: d8c01904 addi r3,sp,100 - 3a4c: 003fee06 br 3a08 <___vfprintf_internal_r+0xd04> - 3a50: d8814717 ldw r2,1308(sp) - 3a54: 143fffc4 addi r16,r2,-1 - 3a58: 043e970e bge zero,r16,34b8 <___vfprintf_internal_r+0x7b4> - 3a5c: 00800404 movi r2,16 - 3a60: 1400180e bge r2,r16,3ac4 <___vfprintf_internal_r+0xdc0> - 3a64: 1029883a mov r20,r2 - 3a68: 07000074 movhi fp,1 - 3a6c: e700b384 addi fp,fp,718 - 3a70: 054001c4 movi r21,7 - 3a74: 00000306 br 3a84 <___vfprintf_internal_r+0xd80> - 3a78: 9cc00204 addi r19,r19,8 - 3a7c: 843ffc04 addi r16,r16,-16 - 3a80: a400120e bge r20,r16,3acc <___vfprintf_internal_r+0xdc8> - 3a84: 94800404 addi r18,r18,16 - 3a88: 8c400044 addi r17,r17,1 - 3a8c: 9f000015 stw fp,0(r19) - 3a90: 9d000115 stw r20,4(r19) - 3a94: dc800e15 stw r18,56(sp) - 3a98: dc400d15 stw r17,52(sp) - 3a9c: ac7ff60e bge r21,r17,3a78 <___vfprintf_internal_r+0xd74> - 3aa0: d9014f17 ldw r4,1340(sp) - 3aa4: b00b883a mov r5,r22 - 3aa8: d9800c04 addi r6,sp,48 - 3aac: 0002cac0 call 2cac <__sprint_r> - 3ab0: 103e4c1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3ab4: dc800e17 ldw r18,56(sp) - 3ab8: dc400d17 ldw r17,52(sp) - 3abc: dcc01904 addi r19,sp,100 - 3ac0: 003fee06 br 3a7c <___vfprintf_internal_r+0xd78> - 3ac4: 07000074 movhi fp,1 - 3ac8: e700b384 addi fp,fp,718 - 3acc: 9425883a add r18,r18,r16 - 3ad0: 8c400044 addi r17,r17,1 - 3ad4: 008001c4 movi r2,7 - 3ad8: 9f000015 stw fp,0(r19) - 3adc: 9c000115 stw r16,4(r19) - 3ae0: dc800e15 stw r18,56(sp) - 3ae4: dc400d15 stw r17,52(sp) - 3ae8: 147e720e bge r2,r17,34b4 <___vfprintf_internal_r+0x7b0> - 3aec: d9014f17 ldw r4,1340(sp) - 3af0: b00b883a mov r5,r22 - 3af4: d9800c04 addi r6,sp,48 - 3af8: 0002cac0 call 2cac <__sprint_r> - 3afc: 103e391e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3b00: dc800e17 ldw r18,56(sp) - 3b04: dc400d17 ldw r17,52(sp) - 3b08: dcc01904 addi r19,sp,100 - 3b0c: 003e6a06 br 34b8 <___vfprintf_internal_r+0x7b4> - 3b10: d9014f17 ldw r4,1340(sp) - 3b14: b00b883a mov r5,r22 - 3b18: d9800c04 addi r6,sp,48 - 3b1c: d9c15115 stw r7,1348(sp) - 3b20: 0002cac0 call 2cac <__sprint_r> - 3b24: d9c15117 ldw r7,1348(sp) - 3b28: 103e2e1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3b2c: dc800e17 ldw r18,56(sp) - 3b30: dc400d17 ldw r17,52(sp) - 3b34: dd401904 addi r21,sp,100 - 3b38: 003dba06 br 3224 <___vfprintf_internal_r+0x520> - 3b3c: d9014f17 ldw r4,1340(sp) - 3b40: b00b883a mov r5,r22 - 3b44: d9800c04 addi r6,sp,48 - 3b48: 0002cac0 call 2cac <__sprint_r> - 3b4c: 103e251e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3b50: dc800e17 ldw r18,56(sp) - 3b54: dc400d17 ldw r17,52(sp) - 3b58: dcc01904 addi r19,sp,100 - 3b5c: 003e4206 br 3468 <___vfprintf_internal_r+0x764> - 3b60: d9014f17 ldw r4,1340(sp) - 3b64: b00b883a mov r5,r22 - 3b68: d9800c04 addi r6,sp,48 - 3b6c: 0002cac0 call 2cac <__sprint_r> - 3b70: 103e1c1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 3b74: dc800e17 ldw r18,56(sp) - 3b78: dc400d17 ldw r17,52(sp) - 3b7c: d8c01904 addi r3,sp,100 - 3b80: 003e2e06 br 343c <___vfprintf_internal_r+0x738> - 3b84: d9414c17 ldw r5,1328(sp) - 3b88: 2880004c andi r2,r5,1 - 3b8c: 1005003a cmpeq r2,r2,zero - 3b90: 103dda1e bne r2,zero,32fc <___vfprintf_internal_r+0x5f8> - 3b94: 003e9f06 br 3614 <___vfprintf_internal_r+0x910> - 3b98: d8c14117 ldw r3,1284(sp) - 3b9c: 9125883a add r18,r18,r4 - 3ba0: 8c400044 addi r17,r17,1 - 3ba4: 008001c4 movi r2,7 - 3ba8: a8c00015 stw r3,0(r21) - 3bac: a9000115 stw r4,4(r21) - 3bb0: dc800e15 stw r18,56(sp) - 3bb4: dc400d15 stw r17,52(sp) - 3bb8: 14426c16 blt r2,r17,456c <___vfprintf_internal_r+0x1868> - 3bbc: a8c00204 addi r3,r21,8 - 3bc0: d9414917 ldw r5,1316(sp) - 3bc4: 00800044 movi r2,1 - 3bc8: 94800044 addi r18,r18,1 - 3bcc: 8c400044 addi r17,r17,1 - 3bd0: 18800115 stw r2,4(r3) - 3bd4: 008001c4 movi r2,7 - 3bd8: 19400015 stw r5,0(r3) - 3bdc: dc800e15 stw r18,56(sp) - 3be0: dc400d15 stw r17,52(sp) - 3be4: 2021883a mov r16,r4 - 3be8: 14425616 blt r2,r17,4544 <___vfprintf_internal_r+0x1840> - 3bec: 19400204 addi r5,r3,8 - 3bf0: d9814717 ldw r6,1308(sp) - 3bf4: 8c400044 addi r17,r17,1 - 3bf8: dc400d15 stw r17,52(sp) - 3bfc: 3107c83a sub r3,r6,r4 - 3c00: d9014117 ldw r4,1284(sp) - 3c04: 90e5883a add r18,r18,r3 - 3c08: 28c00115 stw r3,4(r5) - 3c0c: 8105883a add r2,r16,r4 - 3c10: 28800015 stw r2,0(r5) - 3c14: 008001c4 movi r2,7 - 3c18: dc800e15 stw r18,56(sp) - 3c1c: 147f1d16 blt r2,r17,3894 <___vfprintf_internal_r+0xb90> - 3c20: 28c00204 addi r3,r5,8 - 3c24: 003db506 br 32fc <___vfprintf_internal_r+0x5f8> - 3c28: 3c000017 ldw r16,0(r7) - 3c2c: 3c400117 ldw r17,4(r7) - 3c30: 39800204 addi r6,r7,8 - 3c34: 01000044 movi r4,1 - 3c38: d9814015 stw r6,1280(sp) - 3c3c: d8000405 stb zero,16(sp) - 3c40: 003ebe06 br 373c <___vfprintf_internal_r+0xa38> - 3c44: 3c000017 ldw r16,0(r7) - 3c48: 3c400117 ldw r17,4(r7) - 3c4c: 38800204 addi r2,r7,8 - 3c50: d8814015 stw r2,1280(sp) - 3c54: 003eb706 br 3734 <___vfprintf_internal_r+0xa30> - 3c58: 3c000017 ldw r16,0(r7) - 3c5c: 3c400117 ldw r17,4(r7) - 3c60: 39000204 addi r4,r7,8 - 3c64: d9014015 stw r4,1280(sp) - 3c68: 0009883a mov r4,zero - 3c6c: d8000405 stb zero,16(sp) - 3c70: 003eb206 br 373c <___vfprintf_internal_r+0xa38> - 3c74: 38c00017 ldw r3,0(r7) - 3c78: 39c00104 addi r7,r7,4 - 3c7c: d8c14a15 stw r3,1320(sp) - 3c80: 1800d70e bge r3,zero,3fe0 <___vfprintf_internal_r+0x12dc> - 3c84: 00c7c83a sub r3,zero,r3 - 3c88: d8c14a15 stw r3,1320(sp) - 3c8c: d9014c17 ldw r4,1328(sp) - 3c90: b8c00007 ldb r3,0(r23) - 3c94: 21000114 ori r4,r4,4 - 3c98: d9014c15 stw r4,1328(sp) - 3c9c: 003c9806 br 2f00 <___vfprintf_internal_r+0x1fc> - 3ca0: d9814c17 ldw r6,1328(sp) - 3ca4: 3080080c andi r2,r6,32 - 3ca8: 1001f626 beq r2,zero,4484 <___vfprintf_internal_r+0x1780> - 3cac: d9014b17 ldw r4,1324(sp) - 3cb0: 38800017 ldw r2,0(r7) - 3cb4: 39c00104 addi r7,r7,4 - 3cb8: d9c14015 stw r7,1280(sp) - 3cbc: 2007d7fa srai r3,r4,31 - 3cc0: d9c14017 ldw r7,1280(sp) - 3cc4: 11000015 stw r4,0(r2) - 3cc8: 10c00115 stw r3,4(r2) - 3ccc: 003c6906 br 2e74 <___vfprintf_internal_r+0x170> - 3cd0: b8c00007 ldb r3,0(r23) - 3cd4: 00801b04 movi r2,108 - 3cd8: 18825526 beq r3,r2,4630 <___vfprintf_internal_r+0x192c> - 3cdc: d9414c17 ldw r5,1328(sp) - 3ce0: 29400414 ori r5,r5,16 - 3ce4: d9414c15 stw r5,1328(sp) - 3ce8: 003c8506 br 2f00 <___vfprintf_internal_r+0x1fc> - 3cec: d9814c17 ldw r6,1328(sp) - 3cf0: b8c00007 ldb r3,0(r23) - 3cf4: 31800814 ori r6,r6,32 - 3cf8: d9814c15 stw r6,1328(sp) - 3cfc: 003c8006 br 2f00 <___vfprintf_internal_r+0x1fc> - 3d00: d8814c17 ldw r2,1328(sp) - 3d04: 3c000017 ldw r16,0(r7) - 3d08: 00c01e04 movi r3,120 - 3d0c: 10800094 ori r2,r2,2 - 3d10: d8814c15 stw r2,1328(sp) - 3d14: 39c00104 addi r7,r7,4 - 3d18: 01400074 movhi r5,1 - 3d1c: 29409c04 addi r5,r5,624 - 3d20: 00800c04 movi r2,48 - 3d24: 0023883a mov r17,zero - 3d28: 01000084 movi r4,2 - 3d2c: d9c14015 stw r7,1280(sp) - 3d30: d8c14d15 stw r3,1332(sp) - 3d34: d9414415 stw r5,1296(sp) - 3d38: d8800445 stb r2,17(sp) - 3d3c: d8c00485 stb r3,18(sp) - 3d40: d8000405 stb zero,16(sp) - 3d44: 003e7d06 br 373c <___vfprintf_internal_r+0xa38> - 3d48: d8814c17 ldw r2,1328(sp) - 3d4c: b8c00007 ldb r3,0(r23) - 3d50: 10801014 ori r2,r2,64 - 3d54: d8814c15 stw r2,1328(sp) - 3d58: 003c6906 br 2f00 <___vfprintf_internal_r+0x1fc> - 3d5c: d9414c17 ldw r5,1328(sp) - 3d60: 2880020c andi r2,r5,8 - 3d64: 1001e526 beq r2,zero,44fc <___vfprintf_internal_r+0x17f8> - 3d68: 39800017 ldw r6,0(r7) - 3d6c: 38800204 addi r2,r7,8 - 3d70: d8814015 stw r2,1280(sp) - 3d74: d9814215 stw r6,1288(sp) - 3d78: 39c00117 ldw r7,4(r7) - 3d7c: d9c14315 stw r7,1292(sp) - 3d80: d9014217 ldw r4,1288(sp) - 3d84: d9414317 ldw r5,1292(sp) - 3d88: 00097b40 call 97b4 <__isinfd> - 3d8c: 10021d26 beq r2,zero,4604 <___vfprintf_internal_r+0x1900> - 3d90: d9014217 ldw r4,1288(sp) - 3d94: d9414317 ldw r5,1292(sp) - 3d98: 000d883a mov r6,zero - 3d9c: 000f883a mov r7,zero - 3da0: 000b9500 call b950 <__ltdf2> - 3da4: 1002d016 blt r2,zero,48e8 <___vfprintf_internal_r+0x1be4> - 3da8: d9414d17 ldw r5,1332(sp) - 3dac: 008011c4 movi r2,71 - 3db0: 11421016 blt r2,r5,45f4 <___vfprintf_internal_r+0x18f0> - 3db4: 01800074 movhi r6,1 - 3db8: 3180a104 addi r6,r6,644 - 3dbc: d9814115 stw r6,1284(sp) - 3dc0: d9014c17 ldw r4,1328(sp) - 3dc4: 00c000c4 movi r3,3 - 3dc8: 00bfdfc4 movi r2,-129 - 3dcc: 2088703a and r4,r4,r2 - 3dd0: 180f883a mov r7,r3 - 3dd4: d8c14515 stw r3,1300(sp) - 3dd8: d9014c15 stw r4,1328(sp) - 3ddc: d8014615 stw zero,1304(sp) - 3de0: 003e6a06 br 378c <___vfprintf_internal_r+0xa88> - 3de4: 38800017 ldw r2,0(r7) - 3de8: 00c00044 movi r3,1 - 3dec: 39c00104 addi r7,r7,4 - 3df0: d9c14015 stw r7,1280(sp) - 3df4: d9000f04 addi r4,sp,60 - 3df8: 180f883a mov r7,r3 - 3dfc: d8c14515 stw r3,1300(sp) - 3e00: d9014115 stw r4,1284(sp) - 3e04: d8800f05 stb r2,60(sp) - 3e08: d8000405 stb zero,16(sp) - 3e0c: 003cac06 br 30c0 <___vfprintf_internal_r+0x3bc> - 3e10: 01400074 movhi r5,1 - 3e14: 2940a704 addi r5,r5,668 - 3e18: d9414415 stw r5,1296(sp) - 3e1c: d9814c17 ldw r6,1328(sp) - 3e20: 3080080c andi r2,r6,32 - 3e24: 1000ff26 beq r2,zero,4224 <___vfprintf_internal_r+0x1520> - 3e28: 3c000017 ldw r16,0(r7) - 3e2c: 3c400117 ldw r17,4(r7) - 3e30: 38800204 addi r2,r7,8 - 3e34: d8814015 stw r2,1280(sp) - 3e38: d9414c17 ldw r5,1328(sp) - 3e3c: 2880004c andi r2,r5,1 - 3e40: 1005003a cmpeq r2,r2,zero - 3e44: 1000b91e bne r2,zero,412c <___vfprintf_internal_r+0x1428> - 3e48: 8444b03a or r2,r16,r17 - 3e4c: 1000b726 beq r2,zero,412c <___vfprintf_internal_r+0x1428> - 3e50: d9814d17 ldw r6,1332(sp) - 3e54: 29400094 ori r5,r5,2 - 3e58: 00800c04 movi r2,48 - 3e5c: 01000084 movi r4,2 - 3e60: d9414c15 stw r5,1328(sp) - 3e64: d8800445 stb r2,17(sp) - 3e68: d9800485 stb r6,18(sp) - 3e6c: d8000405 stb zero,16(sp) - 3e70: 003e3206 br 373c <___vfprintf_internal_r+0xa38> - 3e74: 01800074 movhi r6,1 - 3e78: 31809c04 addi r6,r6,624 - 3e7c: d9814415 stw r6,1296(sp) - 3e80: 003fe606 br 3e1c <___vfprintf_internal_r+0x1118> - 3e84: 00800ac4 movi r2,43 - 3e88: d8800405 stb r2,16(sp) - 3e8c: b8c00007 ldb r3,0(r23) - 3e90: 003c1b06 br 2f00 <___vfprintf_internal_r+0x1fc> - 3e94: d8814c17 ldw r2,1328(sp) - 3e98: b8c00007 ldb r3,0(r23) - 3e9c: 10800054 ori r2,r2,1 - 3ea0: d8814c15 stw r2,1328(sp) - 3ea4: 003c1606 br 2f00 <___vfprintf_internal_r+0x1fc> - 3ea8: d8800407 ldb r2,16(sp) - 3eac: 10004c1e bne r2,zero,3fe0 <___vfprintf_internal_r+0x12dc> - 3eb0: 00800804 movi r2,32 - 3eb4: d8800405 stb r2,16(sp) - 3eb8: b8c00007 ldb r3,0(r23) - 3ebc: 003c1006 br 2f00 <___vfprintf_internal_r+0x1fc> - 3ec0: d9814c17 ldw r6,1328(sp) - 3ec4: b8c00007 ldb r3,0(r23) - 3ec8: 31800214 ori r6,r6,8 - 3ecc: d9814c15 stw r6,1328(sp) - 3ed0: 003c0b06 br 2f00 <___vfprintf_internal_r+0x1fc> - 3ed4: 0009883a mov r4,zero - 3ed8: 04000244 movi r16,9 - 3edc: 01400284 movi r5,10 - 3ee0: d9c15115 stw r7,1348(sp) - 3ee4: 0002b2c0 call 2b2c <__mulsi3> - 3ee8: b9000007 ldb r4,0(r23) - 3eec: d8c14d17 ldw r3,1332(sp) - 3ef0: bdc00044 addi r23,r23,1 - 3ef4: d9014d15 stw r4,1332(sp) - 3ef8: d9414d17 ldw r5,1332(sp) - 3efc: 1885883a add r2,r3,r2 - 3f00: 113ff404 addi r4,r2,-48 - 3f04: 28bff404 addi r2,r5,-48 - 3f08: d9c15117 ldw r7,1348(sp) - 3f0c: 80bff32e bgeu r16,r2,3edc <___vfprintf_internal_r+0x11d8> - 3f10: d9014a15 stw r4,1320(sp) - 3f14: 003bfc06 br 2f08 <___vfprintf_internal_r+0x204> - 3f18: d8814c17 ldw r2,1328(sp) - 3f1c: b8c00007 ldb r3,0(r23) - 3f20: 10802014 ori r2,r2,128 - 3f24: d8814c15 stw r2,1328(sp) - 3f28: 003bf506 br 2f00 <___vfprintf_internal_r+0x1fc> - 3f2c: b8c00007 ldb r3,0(r23) - 3f30: 00800a84 movi r2,42 - 3f34: bdc00044 addi r23,r23,1 - 3f38: 18831826 beq r3,r2,4b9c <___vfprintf_internal_r+0x1e98> - 3f3c: d8c14d15 stw r3,1332(sp) - 3f40: 18bff404 addi r2,r3,-48 - 3f44: 00c00244 movi r3,9 - 3f48: 18827b36 bltu r3,r2,4938 <___vfprintf_internal_r+0x1c34> - 3f4c: 1821883a mov r16,r3 - 3f50: 0009883a mov r4,zero - 3f54: 01400284 movi r5,10 - 3f58: d9c15115 stw r7,1348(sp) - 3f5c: 0002b2c0 call 2b2c <__mulsi3> - 3f60: d9414d17 ldw r5,1332(sp) - 3f64: b9800007 ldb r6,0(r23) - 3f68: d9c15117 ldw r7,1348(sp) - 3f6c: 1145883a add r2,r2,r5 - 3f70: 113ff404 addi r4,r2,-48 - 3f74: 30bff404 addi r2,r6,-48 - 3f78: d9814d15 stw r6,1332(sp) - 3f7c: bdc00044 addi r23,r23,1 - 3f80: 80bff42e bgeu r16,r2,3f54 <___vfprintf_internal_r+0x1250> - 3f84: 2027883a mov r19,r4 - 3f88: 203bdf0e bge r4,zero,2f08 <___vfprintf_internal_r+0x204> - 3f8c: 04ffffc4 movi r19,-1 - 3f90: 003bdd06 br 2f08 <___vfprintf_internal_r+0x204> - 3f94: d8000405 stb zero,16(sp) - 3f98: 39800017 ldw r6,0(r7) - 3f9c: 39c00104 addi r7,r7,4 - 3fa0: d9c14015 stw r7,1280(sp) - 3fa4: d9814115 stw r6,1284(sp) - 3fa8: 3001c926 beq r6,zero,46d0 <___vfprintf_internal_r+0x19cc> - 3fac: 98000e16 blt r19,zero,3fe8 <___vfprintf_internal_r+0x12e4> - 3fb0: d9014117 ldw r4,1284(sp) - 3fb4: 000b883a mov r5,zero - 3fb8: 980d883a mov r6,r19 - 3fbc: 0007e380 call 7e38 - 3fc0: 10025926 beq r2,zero,4928 <___vfprintf_internal_r+0x1c24> - 3fc4: d8c14117 ldw r3,1284(sp) - 3fc8: 10cfc83a sub r7,r2,r3 - 3fcc: 99c19e16 blt r19,r7,4648 <___vfprintf_internal_r+0x1944> - 3fd0: d9c14515 stw r7,1300(sp) - 3fd4: 38000916 blt r7,zero,3ffc <___vfprintf_internal_r+0x12f8> - 3fd8: d8014615 stw zero,1304(sp) - 3fdc: 003deb06 br 378c <___vfprintf_internal_r+0xa88> - 3fe0: b8c00007 ldb r3,0(r23) - 3fe4: 003bc606 br 2f00 <___vfprintf_internal_r+0x1fc> - 3fe8: d9014117 ldw r4,1284(sp) - 3fec: 0002c380 call 2c38 - 3ff0: d8814515 stw r2,1300(sp) - 3ff4: 100f883a mov r7,r2 - 3ff8: 103ff70e bge r2,zero,3fd8 <___vfprintf_internal_r+0x12d4> - 3ffc: d8014515 stw zero,1300(sp) - 4000: d8014615 stw zero,1304(sp) - 4004: 003de106 br 378c <___vfprintf_internal_r+0xa88> - 4008: 20c03fcc andi r3,r4,255 - 400c: 00800044 movi r2,1 - 4010: 18802d26 beq r3,r2,40c8 <___vfprintf_internal_r+0x13c4> - 4014: 18800e36 bltu r3,r2,4050 <___vfprintf_internal_r+0x134c> - 4018: 00800084 movi r2,2 - 401c: 1880fa26 beq r3,r2,4408 <___vfprintf_internal_r+0x1704> - 4020: 01000074 movhi r4,1 - 4024: 2100ac04 addi r4,r4,688 - 4028: 0002c380 call 2c38 - 402c: 100f883a mov r7,r2 - 4030: dcc14515 stw r19,1300(sp) - 4034: 9880010e bge r19,r2,403c <___vfprintf_internal_r+0x1338> - 4038: d8814515 stw r2,1300(sp) - 403c: 00800074 movhi r2,1 - 4040: 1080ac04 addi r2,r2,688 - 4044: dcc14615 stw r19,1304(sp) - 4048: d8814115 stw r2,1284(sp) - 404c: 003dcf06 br 378c <___vfprintf_internal_r+0xa88> - 4050: d9401904 addi r5,sp,100 - 4054: dd000f04 addi r20,sp,60 - 4058: d9414115 stw r5,1284(sp) - 405c: 880a977a slli r5,r17,29 - 4060: d9814117 ldw r6,1284(sp) - 4064: 8004d0fa srli r2,r16,3 - 4068: 8806d0fa srli r3,r17,3 - 406c: 810001cc andi r4,r16,7 - 4070: 2884b03a or r2,r5,r2 - 4074: 31bfffc4 addi r6,r6,-1 - 4078: 21000c04 addi r4,r4,48 - 407c: d9814115 stw r6,1284(sp) - 4080: 10cab03a or r5,r2,r3 - 4084: 31000005 stb r4,0(r6) - 4088: 1021883a mov r16,r2 - 408c: 1823883a mov r17,r3 - 4090: 283ff21e bne r5,zero,405c <___vfprintf_internal_r+0x1358> - 4094: d8c14c17 ldw r3,1328(sp) - 4098: 1880004c andi r2,r3,1 - 409c: 1005003a cmpeq r2,r2,zero - 40a0: 103db31e bne r2,zero,3770 <___vfprintf_internal_r+0xa6c> - 40a4: 20803fcc andi r2,r4,255 - 40a8: 1080201c xori r2,r2,128 - 40ac: 10bfe004 addi r2,r2,-128 - 40b0: 00c00c04 movi r3,48 - 40b4: 10fdae26 beq r2,r3,3770 <___vfprintf_internal_r+0xa6c> - 40b8: 31bfffc4 addi r6,r6,-1 - 40bc: d9814115 stw r6,1284(sp) - 40c0: 30c00005 stb r3,0(r6) - 40c4: 003daa06 br 3770 <___vfprintf_internal_r+0xa6c> - 40c8: 88800068 cmpgeui r2,r17,1 - 40cc: 10002c1e bne r2,zero,4180 <___vfprintf_internal_r+0x147c> - 40d0: 8800021e bne r17,zero,40dc <___vfprintf_internal_r+0x13d8> - 40d4: 00800244 movi r2,9 - 40d8: 14002936 bltu r2,r16,4180 <___vfprintf_internal_r+0x147c> - 40dc: d90018c4 addi r4,sp,99 - 40e0: dd000f04 addi r20,sp,60 - 40e4: d9014115 stw r4,1284(sp) - 40e8: d9014117 ldw r4,1284(sp) - 40ec: 80800c04 addi r2,r16,48 - 40f0: 20800005 stb r2,0(r4) - 40f4: 003d9e06 br 3770 <___vfprintf_internal_r+0xa6c> - 40f8: dc400d17 ldw r17,52(sp) - 40fc: 07000074 movhi fp,1 - 4100: e700b384 addi fp,fp,718 - 4104: 9425883a add r18,r18,r16 - 4108: 8c400044 addi r17,r17,1 - 410c: 008001c4 movi r2,7 - 4110: 1f000015 stw fp,0(r3) - 4114: 1c000115 stw r16,4(r3) - 4118: dc800e15 stw r18,56(sp) - 411c: dc400d15 stw r17,52(sp) - 4120: 147ddc16 blt r2,r17,3894 <___vfprintf_internal_r+0xb90> - 4124: 18c00204 addi r3,r3,8 - 4128: 003c7406 br 32fc <___vfprintf_internal_r+0x5f8> - 412c: 01000084 movi r4,2 - 4130: d8000405 stb zero,16(sp) - 4134: 003d8106 br 373c <___vfprintf_internal_r+0xa38> - 4138: d9814c17 ldw r6,1328(sp) - 413c: 30c4703a and r2,r6,r3 - 4140: 1005003a cmpeq r2,r2,zero - 4144: 103cb326 beq r2,zero,3414 <___vfprintf_internal_r+0x710> - 4148: d9014117 ldw r4,1284(sp) - 414c: 94800044 addi r18,r18,1 - 4150: 8c400044 addi r17,r17,1 - 4154: 008001c4 movi r2,7 - 4158: a9000015 stw r4,0(r21) - 415c: a8c00115 stw r3,4(r21) - 4160: dc800e15 stw r18,56(sp) - 4164: dc400d15 stw r17,52(sp) - 4168: 147e6016 blt r2,r17,3aec <___vfprintf_internal_r+0xde8> - 416c: acc00204 addi r19,r21,8 - 4170: 003cd106 br 34b8 <___vfprintf_internal_r+0x7b4> - 4174: 07000074 movhi fp,1 - 4178: e700b384 addi fp,fp,718 - 417c: 003c4906 br 32a4 <___vfprintf_internal_r+0x5a0> - 4180: dd000f04 addi r20,sp,60 - 4184: dc801904 addi r18,sp,100 - 4188: 8009883a mov r4,r16 - 418c: 880b883a mov r5,r17 - 4190: 01800284 movi r6,10 - 4194: 000f883a mov r7,zero - 4198: 000a5b00 call a5b0 <__umoddi3> - 419c: 12000c04 addi r8,r2,48 - 41a0: 94bfffc4 addi r18,r18,-1 - 41a4: 8009883a mov r4,r16 - 41a8: 880b883a mov r5,r17 - 41ac: 01800284 movi r6,10 - 41b0: 000f883a mov r7,zero - 41b4: 92000005 stb r8,0(r18) - 41b8: 0009f440 call 9f44 <__udivdi3> - 41bc: 1009883a mov r4,r2 - 41c0: 1021883a mov r16,r2 - 41c4: 18800068 cmpgeui r2,r3,1 - 41c8: 1823883a mov r17,r3 - 41cc: 103fee1e bne r2,zero,4188 <___vfprintf_internal_r+0x1484> - 41d0: 1800021e bne r3,zero,41dc <___vfprintf_internal_r+0x14d8> - 41d4: 00800244 movi r2,9 - 41d8: 113feb36 bltu r2,r4,4188 <___vfprintf_internal_r+0x1484> - 41dc: 94bfffc4 addi r18,r18,-1 - 41e0: dc814115 stw r18,1284(sp) - 41e4: 003fc006 br 40e8 <___vfprintf_internal_r+0x13e4> - 41e8: d9014c17 ldw r4,1328(sp) - 41ec: 2080004c andi r2,r4,1 - 41f0: 10009a1e bne r2,zero,445c <___vfprintf_internal_r+0x1758> - 41f4: d9401904 addi r5,sp,100 - 41f8: dd000f04 addi r20,sp,60 - 41fc: d9414115 stw r5,1284(sp) - 4200: 003d5b06 br 3770 <___vfprintf_internal_r+0xa6c> - 4204: d9014f17 ldw r4,1340(sp) - 4208: b00b883a mov r5,r22 - 420c: d9800c04 addi r6,sp,48 - 4210: 0002cac0 call 2cac <__sprint_r> - 4214: 103c731e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 4218: dc800e17 ldw r18,56(sp) - 421c: d8c01904 addi r3,sp,100 - 4220: 003cf906 br 3608 <___vfprintf_internal_r+0x904> - 4224: d8c14c17 ldw r3,1328(sp) - 4228: 1880040c andi r2,r3,16 - 422c: 1000711e bne r2,zero,43f4 <___vfprintf_internal_r+0x16f0> - 4230: d9014c17 ldw r4,1328(sp) - 4234: 2080100c andi r2,r4,64 - 4238: 10006e26 beq r2,zero,43f4 <___vfprintf_internal_r+0x16f0> - 423c: 3c00000b ldhu r16,0(r7) - 4240: 0023883a mov r17,zero - 4244: 39c00104 addi r7,r7,4 - 4248: d9c14015 stw r7,1280(sp) - 424c: 003efa06 br 3e38 <___vfprintf_internal_r+0x1134> - 4250: dc400d17 ldw r17,52(sp) - 4254: 07000074 movhi fp,1 - 4258: e700b384 addi fp,fp,718 - 425c: 9425883a add r18,r18,r16 - 4260: 8c400044 addi r17,r17,1 - 4264: 008001c4 movi r2,7 - 4268: 1f000015 stw fp,0(r3) - 426c: 1c000115 stw r16,4(r3) - 4270: dc800e15 stw r18,56(sp) - 4274: dc400d15 stw r17,52(sp) - 4278: 147d7016 blt r2,r17,383c <___vfprintf_internal_r+0xb38> - 427c: 18c00204 addi r3,r3,8 - 4280: 003d7506 br 3858 <___vfprintf_internal_r+0xb54> - 4284: dc800e17 ldw r18,56(sp) - 4288: dc400d17 ldw r17,52(sp) - 428c: 07000074 movhi fp,1 - 4290: e700b784 addi fp,fp,734 - 4294: 003bba06 br 3180 <___vfprintf_internal_r+0x47c> - 4298: d9014f17 ldw r4,1340(sp) - 429c: b00b883a mov r5,r22 - 42a0: d9800c04 addi r6,sp,48 - 42a4: 0002cac0 call 2cac <__sprint_r> - 42a8: 103c4e1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 42ac: dc800e17 ldw r18,56(sp) - 42b0: d8c01904 addi r3,sp,100 - 42b4: 003ce306 br 3644 <___vfprintf_internal_r+0x940> - 42b8: 3c000017 ldw r16,0(r7) - 42bc: 0009883a mov r4,zero - 42c0: 39c00104 addi r7,r7,4 - 42c4: 0023883a mov r17,zero - 42c8: d9c14015 stw r7,1280(sp) - 42cc: d8000405 stb zero,16(sp) - 42d0: 003d1a06 br 373c <___vfprintf_internal_r+0xa38> - 42d4: 38800017 ldw r2,0(r7) - 42d8: 39c00104 addi r7,r7,4 - 42dc: d9c14015 stw r7,1280(sp) - 42e0: 1023d7fa srai r17,r2,31 - 42e4: 1021883a mov r16,r2 - 42e8: 003d1206 br 3734 <___vfprintf_internal_r+0xa30> - 42ec: 3c000017 ldw r16,0(r7) - 42f0: 01000044 movi r4,1 - 42f4: 39c00104 addi r7,r7,4 - 42f8: 0023883a mov r17,zero - 42fc: d9c14015 stw r7,1280(sp) - 4300: d8000405 stb zero,16(sp) - 4304: 003d0d06 br 373c <___vfprintf_internal_r+0xa38> - 4308: 00800074 movhi r2,1 - 430c: 1080b304 addi r2,r2,716 - 4310: 94800044 addi r18,r18,1 - 4314: 8c400044 addi r17,r17,1 - 4318: a8800015 stw r2,0(r21) - 431c: 00c00044 movi r3,1 - 4320: 008001c4 movi r2,7 - 4324: a8c00115 stw r3,4(r21) - 4328: dc800e15 stw r18,56(sp) - 432c: dc400d15 stw r17,52(sp) - 4330: 1440ca16 blt r2,r17,465c <___vfprintf_internal_r+0x1958> - 4334: a8c00204 addi r3,r21,8 - 4338: 2000061e bne r4,zero,4354 <___vfprintf_internal_r+0x1650> - 433c: d9414717 ldw r5,1308(sp) - 4340: 2800041e bne r5,zero,4354 <___vfprintf_internal_r+0x1650> - 4344: d9814c17 ldw r6,1328(sp) - 4348: 3080004c andi r2,r6,1 - 434c: 1005003a cmpeq r2,r2,zero - 4350: 103bea1e bne r2,zero,32fc <___vfprintf_internal_r+0x5f8> - 4354: 00800044 movi r2,1 - 4358: dc400d17 ldw r17,52(sp) - 435c: 18800115 stw r2,4(r3) - 4360: d8814917 ldw r2,1316(sp) - 4364: 94800044 addi r18,r18,1 - 4368: 8c400044 addi r17,r17,1 - 436c: 18800015 stw r2,0(r3) - 4370: 008001c4 movi r2,7 - 4374: dc800e15 stw r18,56(sp) - 4378: dc400d15 stw r17,52(sp) - 437c: 1440ca16 blt r2,r17,46a8 <___vfprintf_internal_r+0x19a4> - 4380: 18c00204 addi r3,r3,8 - 4384: 0121c83a sub r16,zero,r4 - 4388: 0400500e bge zero,r16,44cc <___vfprintf_internal_r+0x17c8> - 438c: 00800404 movi r2,16 - 4390: 1400800e bge r2,r16,4594 <___vfprintf_internal_r+0x1890> - 4394: 1027883a mov r19,r2 - 4398: 07000074 movhi fp,1 - 439c: e700b384 addi fp,fp,718 - 43a0: 050001c4 movi r20,7 - 43a4: 00000306 br 43b4 <___vfprintf_internal_r+0x16b0> - 43a8: 18c00204 addi r3,r3,8 - 43ac: 843ffc04 addi r16,r16,-16 - 43b0: 9c007a0e bge r19,r16,459c <___vfprintf_internal_r+0x1898> - 43b4: 94800404 addi r18,r18,16 - 43b8: 8c400044 addi r17,r17,1 - 43bc: 1f000015 stw fp,0(r3) - 43c0: 1cc00115 stw r19,4(r3) - 43c4: dc800e15 stw r18,56(sp) - 43c8: dc400d15 stw r17,52(sp) - 43cc: a47ff60e bge r20,r17,43a8 <___vfprintf_internal_r+0x16a4> - 43d0: d9014f17 ldw r4,1340(sp) - 43d4: b00b883a mov r5,r22 - 43d8: d9800c04 addi r6,sp,48 - 43dc: 0002cac0 call 2cac <__sprint_r> - 43e0: 103c001e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 43e4: dc800e17 ldw r18,56(sp) - 43e8: dc400d17 ldw r17,52(sp) - 43ec: d8c01904 addi r3,sp,100 - 43f0: 003fee06 br 43ac <___vfprintf_internal_r+0x16a8> - 43f4: 3c000017 ldw r16,0(r7) - 43f8: 0023883a mov r17,zero - 43fc: 39c00104 addi r7,r7,4 - 4400: d9c14015 stw r7,1280(sp) - 4404: 003e8c06 br 3e38 <___vfprintf_internal_r+0x1134> - 4408: d9401904 addi r5,sp,100 - 440c: dd000f04 addi r20,sp,60 - 4410: d9414115 stw r5,1284(sp) - 4414: d9814417 ldw r6,1296(sp) - 4418: 880a973a slli r5,r17,28 - 441c: 8004d13a srli r2,r16,4 - 4420: 810003cc andi r4,r16,15 - 4424: 3109883a add r4,r6,r4 - 4428: 2884b03a or r2,r5,r2 - 442c: 21400003 ldbu r5,0(r4) - 4430: d9014117 ldw r4,1284(sp) - 4434: 8806d13a srli r3,r17,4 - 4438: 1021883a mov r16,r2 - 443c: 213fffc4 addi r4,r4,-1 - 4440: d9014115 stw r4,1284(sp) - 4444: d9814117 ldw r6,1284(sp) - 4448: 10c8b03a or r4,r2,r3 - 444c: 1823883a mov r17,r3 - 4450: 31400005 stb r5,0(r6) - 4454: 203fef1e bne r4,zero,4414 <___vfprintf_internal_r+0x1710> - 4458: 003cc506 br 3770 <___vfprintf_internal_r+0xa6c> - 445c: 00800c04 movi r2,48 - 4460: d98018c4 addi r6,sp,99 - 4464: dd000f04 addi r20,sp,60 - 4468: d88018c5 stb r2,99(sp) - 446c: d9814115 stw r6,1284(sp) - 4470: 003cbf06 br 3770 <___vfprintf_internal_r+0xa6c> - 4474: dc400d17 ldw r17,52(sp) - 4478: 07000074 movhi fp,1 - 447c: e700b784 addi fp,fp,734 - 4480: 003bc106 br 3388 <___vfprintf_internal_r+0x684> - 4484: d9414c17 ldw r5,1328(sp) - 4488: 2880040c andi r2,r5,16 - 448c: 10007c26 beq r2,zero,4680 <___vfprintf_internal_r+0x197c> - 4490: 38800017 ldw r2,0(r7) - 4494: 39c00104 addi r7,r7,4 - 4498: d9c14015 stw r7,1280(sp) - 449c: d9814b17 ldw r6,1324(sp) - 44a0: d9c14017 ldw r7,1280(sp) - 44a4: 11800015 stw r6,0(r2) - 44a8: 003a7206 br 2e74 <___vfprintf_internal_r+0x170> - 44ac: d9014f17 ldw r4,1340(sp) - 44b0: b00b883a mov r5,r22 - 44b4: d9800c04 addi r6,sp,48 - 44b8: 0002cac0 call 2cac <__sprint_r> - 44bc: 103bc91e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 44c0: dc800e17 ldw r18,56(sp) - 44c4: dc400d17 ldw r17,52(sp) - 44c8: d8c01904 addi r3,sp,100 - 44cc: d9014717 ldw r4,1308(sp) - 44d0: d9414117 ldw r5,1284(sp) - 44d4: 8c400044 addi r17,r17,1 - 44d8: 9125883a add r18,r18,r4 - 44dc: 008001c4 movi r2,7 - 44e0: 19400015 stw r5,0(r3) - 44e4: 19000115 stw r4,4(r3) - 44e8: dc800e15 stw r18,56(sp) - 44ec: dc400d15 stw r17,52(sp) - 44f0: 147ce816 blt r2,r17,3894 <___vfprintf_internal_r+0xb90> - 44f4: 18c00204 addi r3,r3,8 - 44f8: 003b8006 br 32fc <___vfprintf_internal_r+0x5f8> - 44fc: 38c00017 ldw r3,0(r7) - 4500: 39000204 addi r4,r7,8 - 4504: d9014015 stw r4,1280(sp) - 4508: d8c14215 stw r3,1288(sp) - 450c: 39c00117 ldw r7,4(r7) - 4510: d9c14315 stw r7,1292(sp) - 4514: 003e1a06 br 3d80 <___vfprintf_internal_r+0x107c> - 4518: 0005883a mov r2,zero - 451c: 1409c83a sub r4,r2,r16 - 4520: 1105803a cmpltu r2,r2,r4 - 4524: 044bc83a sub r5,zero,r17 - 4528: 2885c83a sub r2,r5,r2 - 452c: 2021883a mov r16,r4 - 4530: 1023883a mov r17,r2 - 4534: 01000044 movi r4,1 - 4538: 00800b44 movi r2,45 - 453c: d8800405 stb r2,16(sp) - 4540: 003c7e06 br 373c <___vfprintf_internal_r+0xa38> - 4544: d9014f17 ldw r4,1340(sp) - 4548: b00b883a mov r5,r22 - 454c: d9800c04 addi r6,sp,48 - 4550: 0002cac0 call 2cac <__sprint_r> - 4554: 103ba31e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 4558: dc800e17 ldw r18,56(sp) - 455c: dc400d17 ldw r17,52(sp) - 4560: d9000517 ldw r4,20(sp) - 4564: d9401904 addi r5,sp,100 - 4568: 003da106 br 3bf0 <___vfprintf_internal_r+0xeec> - 456c: d9014f17 ldw r4,1340(sp) - 4570: b00b883a mov r5,r22 - 4574: d9800c04 addi r6,sp,48 - 4578: 0002cac0 call 2cac <__sprint_r> - 457c: 103b991e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 4580: dc800e17 ldw r18,56(sp) - 4584: dc400d17 ldw r17,52(sp) - 4588: d9000517 ldw r4,20(sp) - 458c: d8c01904 addi r3,sp,100 - 4590: 003d8b06 br 3bc0 <___vfprintf_internal_r+0xebc> - 4594: 07000074 movhi fp,1 - 4598: e700b384 addi fp,fp,718 - 459c: 9425883a add r18,r18,r16 - 45a0: 8c400044 addi r17,r17,1 - 45a4: 008001c4 movi r2,7 - 45a8: 1f000015 stw fp,0(r3) - 45ac: 1c000115 stw r16,4(r3) - 45b0: dc800e15 stw r18,56(sp) - 45b4: dc400d15 stw r17,52(sp) - 45b8: 147fbc16 blt r2,r17,44ac <___vfprintf_internal_r+0x17a8> - 45bc: 18c00204 addi r3,r3,8 - 45c0: 003fc206 br 44cc <___vfprintf_internal_r+0x17c8> - 45c4: d9014f17 ldw r4,1340(sp) - 45c8: b00b883a mov r5,r22 - 45cc: d9800c04 addi r6,sp,48 - 45d0: 0002cac0 call 2cac <__sprint_r> - 45d4: 103b831e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 45d8: dc800e17 ldw r18,56(sp) - 45dc: d9000517 ldw r4,20(sp) - 45e0: d8c01904 addi r3,sp,100 - 45e4: 003cfc06 br 39d8 <___vfprintf_internal_r+0xcd4> - 45e8: 07000074 movhi fp,1 - 45ec: e700b384 addi fp,fp,718 - 45f0: 003bde06 br 356c <___vfprintf_internal_r+0x868> - 45f4: 00800074 movhi r2,1 - 45f8: 1080a204 addi r2,r2,648 - 45fc: d8814115 stw r2,1284(sp) - 4600: 003def06 br 3dc0 <___vfprintf_internal_r+0x10bc> - 4604: d9014217 ldw r4,1288(sp) - 4608: d9414317 ldw r5,1292(sp) - 460c: 00097f40 call 97f4 <__isnand> - 4610: 10003926 beq r2,zero,46f8 <___vfprintf_internal_r+0x19f4> - 4614: d9414d17 ldw r5,1332(sp) - 4618: 008011c4 movi r2,71 - 461c: 1140ce16 blt r2,r5,4958 <___vfprintf_internal_r+0x1c54> - 4620: 01800074 movhi r6,1 - 4624: 3180a304 addi r6,r6,652 - 4628: d9814115 stw r6,1284(sp) - 462c: 003de406 br 3dc0 <___vfprintf_internal_r+0x10bc> - 4630: d9014c17 ldw r4,1328(sp) - 4634: bdc00044 addi r23,r23,1 - 4638: b8c00007 ldb r3,0(r23) - 463c: 21000814 ori r4,r4,32 - 4640: d9014c15 stw r4,1328(sp) - 4644: 003a2e06 br 2f00 <___vfprintf_internal_r+0x1fc> - 4648: dcc14515 stw r19,1300(sp) - 464c: 98011016 blt r19,zero,4a90 <___vfprintf_internal_r+0x1d8c> - 4650: 980f883a mov r7,r19 - 4654: d8014615 stw zero,1304(sp) - 4658: 003c4c06 br 378c <___vfprintf_internal_r+0xa88> - 465c: d9014f17 ldw r4,1340(sp) - 4660: b00b883a mov r5,r22 - 4664: d9800c04 addi r6,sp,48 - 4668: 0002cac0 call 2cac <__sprint_r> - 466c: 103b5d1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 4670: dc800e17 ldw r18,56(sp) - 4674: d9000517 ldw r4,20(sp) - 4678: d8c01904 addi r3,sp,100 - 467c: 003f2e06 br 4338 <___vfprintf_internal_r+0x1634> - 4680: d8c14c17 ldw r3,1328(sp) - 4684: 1880100c andi r2,r3,64 - 4688: 1000a026 beq r2,zero,490c <___vfprintf_internal_r+0x1c08> - 468c: 38800017 ldw r2,0(r7) - 4690: 39c00104 addi r7,r7,4 - 4694: d9c14015 stw r7,1280(sp) - 4698: d9014b17 ldw r4,1324(sp) - 469c: d9c14017 ldw r7,1280(sp) - 46a0: 1100000d sth r4,0(r2) - 46a4: 0039f306 br 2e74 <___vfprintf_internal_r+0x170> - 46a8: d9014f17 ldw r4,1340(sp) - 46ac: b00b883a mov r5,r22 - 46b0: d9800c04 addi r6,sp,48 - 46b4: 0002cac0 call 2cac <__sprint_r> - 46b8: 103b4a1e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 46bc: dc800e17 ldw r18,56(sp) - 46c0: dc400d17 ldw r17,52(sp) - 46c4: d9000517 ldw r4,20(sp) - 46c8: d8c01904 addi r3,sp,100 - 46cc: 003f2d06 br 4384 <___vfprintf_internal_r+0x1680> - 46d0: 00800184 movi r2,6 - 46d4: 14c09a36 bltu r2,r19,4940 <___vfprintf_internal_r+0x1c3c> - 46d8: dcc14515 stw r19,1300(sp) - 46dc: 9800010e bge r19,zero,46e4 <___vfprintf_internal_r+0x19e0> - 46e0: d8014515 stw zero,1300(sp) - 46e4: 00800074 movhi r2,1 - 46e8: 1080a504 addi r2,r2,660 - 46ec: 980f883a mov r7,r19 - 46f0: d8814115 stw r2,1284(sp) - 46f4: 003a7206 br 30c0 <___vfprintf_internal_r+0x3bc> - 46f8: 00bfffc4 movi r2,-1 - 46fc: 9880e226 beq r19,r2,4a88 <___vfprintf_internal_r+0x1d84> - 4700: d9414d17 ldw r5,1332(sp) - 4704: 008019c4 movi r2,103 - 4708: 2880dc26 beq r5,r2,4a7c <___vfprintf_internal_r+0x1d78> - 470c: 008011c4 movi r2,71 - 4710: 2880da26 beq r5,r2,4a7c <___vfprintf_internal_r+0x1d78> - 4714: d9414c17 ldw r5,1328(sp) - 4718: d9014317 ldw r4,1292(sp) - 471c: d9814217 ldw r6,1288(sp) - 4720: 29404014 ori r5,r5,256 - 4724: d9414c15 stw r5,1328(sp) - 4728: 2000cc16 blt r4,zero,4a5c <___vfprintf_internal_r+0x1d58> - 472c: 3021883a mov r16,r6 - 4730: 2023883a mov r17,r4 - 4734: 0039883a mov fp,zero - 4738: d9414d17 ldw r5,1332(sp) - 473c: 00801984 movi r2,102 - 4740: 2880b726 beq r5,r2,4a20 <___vfprintf_internal_r+0x1d1c> - 4744: 00801184 movi r2,70 - 4748: 2880b526 beq r5,r2,4a20 <___vfprintf_internal_r+0x1d1c> - 474c: 00801944 movi r2,101 - 4750: 2880c826 beq r5,r2,4a74 <___vfprintf_internal_r+0x1d70> - 4754: 00801144 movi r2,69 - 4758: 2880c626 beq r5,r2,4a74 <___vfprintf_internal_r+0x1d70> - 475c: 9829883a mov r20,r19 - 4760: d9014f17 ldw r4,1340(sp) - 4764: d8800504 addi r2,sp,20 - 4768: 880d883a mov r6,r17 - 476c: d8800115 stw r2,4(sp) - 4770: d8c00604 addi r3,sp,24 - 4774: d8800704 addi r2,sp,28 - 4778: 800b883a mov r5,r16 - 477c: 01c00084 movi r7,2 - 4780: d8c00215 stw r3,8(sp) - 4784: d8800315 stw r2,12(sp) - 4788: dd000015 stw r20,0(sp) - 478c: 0004f6c0 call 4f6c <_dtoa_r> - 4790: d9814d17 ldw r6,1332(sp) - 4794: d8814115 stw r2,1284(sp) - 4798: 008019c4 movi r2,103 - 479c: 30809526 beq r6,r2,49f4 <___vfprintf_internal_r+0x1cf0> - 47a0: d8c14d17 ldw r3,1332(sp) - 47a4: 008011c4 movi r2,71 - 47a8: 18809226 beq r3,r2,49f4 <___vfprintf_internal_r+0x1cf0> - 47ac: d9414117 ldw r5,1284(sp) - 47b0: d9814d17 ldw r6,1332(sp) - 47b4: 00801984 movi r2,102 - 47b8: 2d25883a add r18,r5,r20 - 47bc: 30808626 beq r6,r2,49d8 <___vfprintf_internal_r+0x1cd4> - 47c0: 00801184 movi r2,70 - 47c4: 30808426 beq r6,r2,49d8 <___vfprintf_internal_r+0x1cd4> - 47c8: 000d883a mov r6,zero - 47cc: 000f883a mov r7,zero - 47d0: 880b883a mov r5,r17 - 47d4: 8009883a mov r4,r16 - 47d8: 000b7300 call b730 <__eqdf2> - 47dc: 1000751e bne r2,zero,49b4 <___vfprintf_internal_r+0x1cb0> - 47e0: 9005883a mov r2,r18 - 47e4: dc800715 stw r18,28(sp) - 47e8: d9014117 ldw r4,1284(sp) - 47ec: d9414d17 ldw r5,1332(sp) - 47f0: 00c019c4 movi r3,103 - 47f4: 1125c83a sub r18,r2,r4 - 47f8: 28c06826 beq r5,r3,499c <___vfprintf_internal_r+0x1c98> - 47fc: 008011c4 movi r2,71 - 4800: 28806626 beq r5,r2,499c <___vfprintf_internal_r+0x1c98> - 4804: d9000517 ldw r4,20(sp) - 4808: d8c14d17 ldw r3,1332(sp) - 480c: 00801944 movi r2,101 - 4810: 10c05516 blt r2,r3,4968 <___vfprintf_internal_r+0x1c64> - 4814: 213fffc4 addi r4,r4,-1 - 4818: d9000515 stw r4,20(sp) - 481c: d8c00805 stb r3,32(sp) - 4820: 2021883a mov r16,r4 - 4824: 2000c116 blt r4,zero,4b2c <___vfprintf_internal_r+0x1e28> - 4828: 00800ac4 movi r2,43 - 482c: d8800845 stb r2,33(sp) - 4830: 00800244 movi r2,9 - 4834: 1400af0e bge r2,r16,4af4 <___vfprintf_internal_r+0x1df0> - 4838: 1027883a mov r19,r2 - 483c: dc400b84 addi r17,sp,46 - 4840: 8009883a mov r4,r16 - 4844: 01400284 movi r5,10 - 4848: 0002abc0 call 2abc <__modsi3> - 484c: 10800c04 addi r2,r2,48 - 4850: 8c7fffc4 addi r17,r17,-1 - 4854: 8009883a mov r4,r16 - 4858: 01400284 movi r5,10 - 485c: 88800005 stb r2,0(r17) - 4860: 0002a5c0 call 2a5c <__divsi3> - 4864: 1021883a mov r16,r2 - 4868: 98bff516 blt r19,r2,4840 <___vfprintf_internal_r+0x1b3c> - 486c: 10c00c04 addi r3,r2,48 - 4870: d88009c4 addi r2,sp,39 - 4874: 108001c4 addi r2,r2,7 - 4878: 897fffc4 addi r5,r17,-1 - 487c: 88ffffc5 stb r3,-1(r17) - 4880: 2880a72e bgeu r5,r2,4b20 <___vfprintf_internal_r+0x1e1c> - 4884: 1009883a mov r4,r2 - 4888: d9800804 addi r6,sp,32 - 488c: d8c00884 addi r3,sp,34 - 4890: 28800003 ldbu r2,0(r5) - 4894: 29400044 addi r5,r5,1 - 4898: 18800005 stb r2,0(r3) - 489c: 18c00044 addi r3,r3,1 - 48a0: 293ffb36 bltu r5,r4,4890 <___vfprintf_internal_r+0x1b8c> - 48a4: 1987c83a sub r3,r3,r6 - 48a8: 00800044 movi r2,1 - 48ac: d8c14815 stw r3,1312(sp) - 48b0: 90cf883a add r7,r18,r3 - 48b4: 1480960e bge r2,r18,4b10 <___vfprintf_internal_r+0x1e0c> - 48b8: 39c00044 addi r7,r7,1 - 48bc: d9c14515 stw r7,1300(sp) - 48c0: 38003416 blt r7,zero,4994 <___vfprintf_internal_r+0x1c90> - 48c4: e0803fcc andi r2,fp,255 - 48c8: 1080201c xori r2,r2,128 - 48cc: 10bfe004 addi r2,r2,-128 - 48d0: 10004e26 beq r2,zero,4a0c <___vfprintf_internal_r+0x1d08> - 48d4: 00800b44 movi r2,45 - 48d8: dc814715 stw r18,1308(sp) - 48dc: d8014615 stw zero,1304(sp) - 48e0: d8800405 stb r2,16(sp) - 48e4: 003bab06 br 3794 <___vfprintf_internal_r+0xa90> - 48e8: 00800b44 movi r2,45 - 48ec: d8800405 stb r2,16(sp) - 48f0: 003d2d06 br 3da8 <___vfprintf_internal_r+0x10a4> - 48f4: d9014f17 ldw r4,1340(sp) - 48f8: b00b883a mov r5,r22 - 48fc: d9800c04 addi r6,sp,48 - 4900: 0002cac0 call 2cac <__sprint_r> - 4904: 103ab71e bne r2,zero,33e4 <___vfprintf_internal_r+0x6e0> - 4908: 003ab506 br 33e0 <___vfprintf_internal_r+0x6dc> - 490c: 38800017 ldw r2,0(r7) - 4910: 39c00104 addi r7,r7,4 - 4914: d9c14015 stw r7,1280(sp) - 4918: d9414b17 ldw r5,1324(sp) - 491c: d9c14017 ldw r7,1280(sp) - 4920: 11400015 stw r5,0(r2) - 4924: 00395306 br 2e74 <___vfprintf_internal_r+0x170> - 4928: 980f883a mov r7,r19 - 492c: dcc14515 stw r19,1300(sp) - 4930: d8014615 stw zero,1304(sp) - 4934: 003b9506 br 378c <___vfprintf_internal_r+0xa88> - 4938: 0027883a mov r19,zero - 493c: 00397206 br 2f08 <___vfprintf_internal_r+0x204> - 4940: 00c00074 movhi r3,1 - 4944: 18c0a504 addi r3,r3,660 - 4948: 100f883a mov r7,r2 - 494c: d8814515 stw r2,1300(sp) - 4950: d8c14115 stw r3,1284(sp) - 4954: 0039da06 br 30c0 <___vfprintf_internal_r+0x3bc> - 4958: 00800074 movhi r2,1 - 495c: 1080a404 addi r2,r2,656 - 4960: d8814115 stw r2,1284(sp) - 4964: 003d1606 br 3dc0 <___vfprintf_internal_r+0x10bc> - 4968: d9414d17 ldw r5,1332(sp) - 496c: 00801984 movi r2,102 - 4970: 28804926 beq r5,r2,4a98 <___vfprintf_internal_r+0x1d94> - 4974: 200f883a mov r7,r4 - 4978: 24805716 blt r4,r18,4ad8 <___vfprintf_internal_r+0x1dd4> - 497c: d9414c17 ldw r5,1328(sp) - 4980: 2880004c andi r2,r5,1 - 4984: 10000126 beq r2,zero,498c <___vfprintf_internal_r+0x1c88> - 4988: 21c00044 addi r7,r4,1 - 498c: d9c14515 stw r7,1300(sp) - 4990: 383fcc0e bge r7,zero,48c4 <___vfprintf_internal_r+0x1bc0> - 4994: d8014515 stw zero,1300(sp) - 4998: 003fca06 br 48c4 <___vfprintf_internal_r+0x1bc0> - 499c: d9000517 ldw r4,20(sp) - 49a0: 00bfff04 movi r2,-4 - 49a4: 1100480e bge r2,r4,4ac8 <___vfprintf_internal_r+0x1dc4> - 49a8: 99004716 blt r19,r4,4ac8 <___vfprintf_internal_r+0x1dc4> - 49ac: d8c14d15 stw r3,1332(sp) - 49b0: 003ff006 br 4974 <___vfprintf_internal_r+0x1c70> - 49b4: d8800717 ldw r2,28(sp) - 49b8: 14bf8b2e bgeu r2,r18,47e8 <___vfprintf_internal_r+0x1ae4> - 49bc: 9007883a mov r3,r18 - 49c0: 01000c04 movi r4,48 - 49c4: 11000005 stb r4,0(r2) - 49c8: 10800044 addi r2,r2,1 - 49cc: d8800715 stw r2,28(sp) - 49d0: 18bffc1e bne r3,r2,49c4 <___vfprintf_internal_r+0x1cc0> - 49d4: 003f8406 br 47e8 <___vfprintf_internal_r+0x1ae4> - 49d8: d8814117 ldw r2,1284(sp) - 49dc: 10c00007 ldb r3,0(r2) - 49e0: 00800c04 movi r2,48 - 49e4: 18805b26 beq r3,r2,4b54 <___vfprintf_internal_r+0x1e50> - 49e8: d9000517 ldw r4,20(sp) - 49ec: 9125883a add r18,r18,r4 - 49f0: 003f7506 br 47c8 <___vfprintf_internal_r+0x1ac4> - 49f4: d9014c17 ldw r4,1328(sp) - 49f8: 2080004c andi r2,r4,1 - 49fc: 1005003a cmpeq r2,r2,zero - 4a00: 103f6a26 beq r2,zero,47ac <___vfprintf_internal_r+0x1aa8> - 4a04: d8800717 ldw r2,28(sp) - 4a08: 003f7706 br 47e8 <___vfprintf_internal_r+0x1ae4> - 4a0c: d9c14515 stw r7,1300(sp) - 4a10: 38004d16 blt r7,zero,4b48 <___vfprintf_internal_r+0x1e44> - 4a14: dc814715 stw r18,1308(sp) - 4a18: d8014615 stw zero,1304(sp) - 4a1c: 003b5b06 br 378c <___vfprintf_internal_r+0xa88> - 4a20: d9014f17 ldw r4,1340(sp) - 4a24: d8800504 addi r2,sp,20 - 4a28: d8800115 stw r2,4(sp) - 4a2c: d8c00604 addi r3,sp,24 - 4a30: d8800704 addi r2,sp,28 - 4a34: 800b883a mov r5,r16 - 4a38: 880d883a mov r6,r17 - 4a3c: 01c000c4 movi r7,3 - 4a40: d8c00215 stw r3,8(sp) - 4a44: d8800315 stw r2,12(sp) - 4a48: dcc00015 stw r19,0(sp) - 4a4c: 9829883a mov r20,r19 - 4a50: 0004f6c0 call 4f6c <_dtoa_r> - 4a54: d8814115 stw r2,1284(sp) - 4a58: 003f5106 br 47a0 <___vfprintf_internal_r+0x1a9c> - 4a5c: d8c14217 ldw r3,1288(sp) - 4a60: d9014317 ldw r4,1292(sp) - 4a64: 07000b44 movi fp,45 - 4a68: 1821883a mov r16,r3 - 4a6c: 2460003c xorhi r17,r4,32768 - 4a70: 003f3106 br 4738 <___vfprintf_internal_r+0x1a34> - 4a74: 9d000044 addi r20,r19,1 - 4a78: 003f3906 br 4760 <___vfprintf_internal_r+0x1a5c> - 4a7c: 983f251e bne r19,zero,4714 <___vfprintf_internal_r+0x1a10> - 4a80: 04c00044 movi r19,1 - 4a84: 003f2306 br 4714 <___vfprintf_internal_r+0x1a10> - 4a88: 04c00184 movi r19,6 - 4a8c: 003f2106 br 4714 <___vfprintf_internal_r+0x1a10> - 4a90: d8014515 stw zero,1300(sp) - 4a94: 003eee06 br 4650 <___vfprintf_internal_r+0x194c> - 4a98: 200f883a mov r7,r4 - 4a9c: 0100370e bge zero,r4,4b7c <___vfprintf_internal_r+0x1e78> - 4aa0: 9800031e bne r19,zero,4ab0 <___vfprintf_internal_r+0x1dac> - 4aa4: d9814c17 ldw r6,1328(sp) - 4aa8: 3080004c andi r2,r6,1 - 4aac: 103fb726 beq r2,zero,498c <___vfprintf_internal_r+0x1c88> - 4ab0: 20800044 addi r2,r4,1 - 4ab4: 98a7883a add r19,r19,r2 - 4ab8: dcc14515 stw r19,1300(sp) - 4abc: 980f883a mov r7,r19 - 4ac0: 983f800e bge r19,zero,48c4 <___vfprintf_internal_r+0x1bc0> - 4ac4: 003fb306 br 4994 <___vfprintf_internal_r+0x1c90> - 4ac8: d9814d17 ldw r6,1332(sp) - 4acc: 31bfff84 addi r6,r6,-2 - 4ad0: d9814d15 stw r6,1332(sp) - 4ad4: 003f4c06 br 4808 <___vfprintf_internal_r+0x1b04> - 4ad8: 0100180e bge zero,r4,4b3c <___vfprintf_internal_r+0x1e38> - 4adc: 00800044 movi r2,1 - 4ae0: 1485883a add r2,r2,r18 - 4ae4: d8814515 stw r2,1300(sp) - 4ae8: 100f883a mov r7,r2 - 4aec: 103f750e bge r2,zero,48c4 <___vfprintf_internal_r+0x1bc0> - 4af0: 003fa806 br 4994 <___vfprintf_internal_r+0x1c90> - 4af4: 80c00c04 addi r3,r16,48 - 4af8: 00800c04 movi r2,48 - 4afc: d8c008c5 stb r3,35(sp) - 4b00: d9800804 addi r6,sp,32 - 4b04: d8c00904 addi r3,sp,36 - 4b08: d8800885 stb r2,34(sp) - 4b0c: 003f6506 br 48a4 <___vfprintf_internal_r+0x1ba0> - 4b10: d9014c17 ldw r4,1328(sp) - 4b14: 2084703a and r2,r4,r2 - 4b18: 103f9c26 beq r2,zero,498c <___vfprintf_internal_r+0x1c88> - 4b1c: 003f6606 br 48b8 <___vfprintf_internal_r+0x1bb4> - 4b20: d9800804 addi r6,sp,32 - 4b24: d8c00884 addi r3,sp,34 - 4b28: 003f5e06 br 48a4 <___vfprintf_internal_r+0x1ba0> - 4b2c: 00800b44 movi r2,45 - 4b30: 0121c83a sub r16,zero,r4 - 4b34: d8800845 stb r2,33(sp) - 4b38: 003f3d06 br 4830 <___vfprintf_internal_r+0x1b2c> - 4b3c: 00800084 movi r2,2 - 4b40: 1105c83a sub r2,r2,r4 - 4b44: 003fe606 br 4ae0 <___vfprintf_internal_r+0x1ddc> - 4b48: d8014515 stw zero,1300(sp) - 4b4c: dc814715 stw r18,1308(sp) - 4b50: 003fb106 br 4a18 <___vfprintf_internal_r+0x1d14> - 4b54: 000d883a mov r6,zero - 4b58: 000f883a mov r7,zero - 4b5c: 8009883a mov r4,r16 - 4b60: 880b883a mov r5,r17 - 4b64: 000b7b80 call b7b8 <__nedf2> - 4b68: 103f9f26 beq r2,zero,49e8 <___vfprintf_internal_r+0x1ce4> - 4b6c: 00800044 movi r2,1 - 4b70: 1509c83a sub r4,r2,r20 - 4b74: d9000515 stw r4,20(sp) - 4b78: 003f9b06 br 49e8 <___vfprintf_internal_r+0x1ce4> - 4b7c: 98000d1e bne r19,zero,4bb4 <___vfprintf_internal_r+0x1eb0> - 4b80: d8c14c17 ldw r3,1328(sp) - 4b84: 1880004c andi r2,r3,1 - 4b88: 10000a1e bne r2,zero,4bb4 <___vfprintf_internal_r+0x1eb0> - 4b8c: 01000044 movi r4,1 - 4b90: 200f883a mov r7,r4 - 4b94: d9014515 stw r4,1300(sp) - 4b98: 003f4a06 br 48c4 <___vfprintf_internal_r+0x1bc0> - 4b9c: 3cc00017 ldw r19,0(r7) - 4ba0: 39c00104 addi r7,r7,4 - 4ba4: 983d0e0e bge r19,zero,3fe0 <___vfprintf_internal_r+0x12dc> - 4ba8: b8c00007 ldb r3,0(r23) - 4bac: 04ffffc4 movi r19,-1 - 4bb0: 0038d306 br 2f00 <___vfprintf_internal_r+0x1fc> - 4bb4: 9cc00084 addi r19,r19,2 - 4bb8: dcc14515 stw r19,1300(sp) - 4bbc: 980f883a mov r7,r19 - 4bc0: 983f400e bge r19,zero,48c4 <___vfprintf_internal_r+0x1bc0> - 4bc4: 003f7306 br 4994 <___vfprintf_internal_r+0x1c90> - -00004bc8 <__vfprintf_internal>: - 4bc8: 00800074 movhi r2,1 - 4bcc: 10884004 addi r2,r2,8448 - 4bd0: 2013883a mov r9,r4 - 4bd4: 11000017 ldw r4,0(r2) - 4bd8: 2805883a mov r2,r5 - 4bdc: 300f883a mov r7,r6 - 4be0: 480b883a mov r5,r9 - 4be4: 100d883a mov r6,r2 - 4be8: 0002d041 jmpi 2d04 <___vfprintf_internal_r> - -00004bec <__swsetup_r>: - 4bec: 00800074 movhi r2,1 - 4bf0: 10884004 addi r2,r2,8448 - 4bf4: 10c00017 ldw r3,0(r2) - 4bf8: defffd04 addi sp,sp,-12 - 4bfc: dc400115 stw r17,4(sp) - 4c00: dc000015 stw r16,0(sp) - 4c04: dfc00215 stw ra,8(sp) - 4c08: 2023883a mov r17,r4 - 4c0c: 2821883a mov r16,r5 - 4c10: 18000226 beq r3,zero,4c1c <__swsetup_r+0x30> - 4c14: 18800e17 ldw r2,56(r3) - 4c18: 10001f26 beq r2,zero,4c98 <__swsetup_r+0xac> - 4c1c: 8100030b ldhu r4,12(r16) - 4c20: 2080020c andi r2,r4,8 - 4c24: 10002826 beq r2,zero,4cc8 <__swsetup_r+0xdc> - 4c28: 81400417 ldw r5,16(r16) - 4c2c: 28001d26 beq r5,zero,4ca4 <__swsetup_r+0xb8> - 4c30: 2080004c andi r2,r4,1 - 4c34: 1005003a cmpeq r2,r2,zero - 4c38: 10000b26 beq r2,zero,4c68 <__swsetup_r+0x7c> - 4c3c: 2080008c andi r2,r4,2 - 4c40: 10001226 beq r2,zero,4c8c <__swsetup_r+0xa0> - 4c44: 0005883a mov r2,zero - 4c48: 80800215 stw r2,8(r16) - 4c4c: 28000b26 beq r5,zero,4c7c <__swsetup_r+0x90> - 4c50: 0005883a mov r2,zero - 4c54: dfc00217 ldw ra,8(sp) - 4c58: dc400117 ldw r17,4(sp) - 4c5c: dc000017 ldw r16,0(sp) - 4c60: dec00304 addi sp,sp,12 - 4c64: f800283a ret - 4c68: 80800517 ldw r2,20(r16) - 4c6c: 80000215 stw zero,8(r16) - 4c70: 0085c83a sub r2,zero,r2 - 4c74: 80800615 stw r2,24(r16) - 4c78: 283ff51e bne r5,zero,4c50 <__swsetup_r+0x64> - 4c7c: 2080200c andi r2,r4,128 - 4c80: 103ff326 beq r2,zero,4c50 <__swsetup_r+0x64> - 4c84: 00bfffc4 movi r2,-1 - 4c88: 003ff206 br 4c54 <__swsetup_r+0x68> - 4c8c: 80800517 ldw r2,20(r16) - 4c90: 80800215 stw r2,8(r16) - 4c94: 003fed06 br 4c4c <__swsetup_r+0x60> - 4c98: 1809883a mov r4,r3 - 4c9c: 00067b80 call 67b8 <__sinit> - 4ca0: 003fde06 br 4c1c <__swsetup_r+0x30> - 4ca4: 20c0a00c andi r3,r4,640 - 4ca8: 00808004 movi r2,512 - 4cac: 18bfe026 beq r3,r2,4c30 <__swsetup_r+0x44> - 4cb0: 8809883a mov r4,r17 - 4cb4: 800b883a mov r5,r16 - 4cb8: 00075640 call 7564 <__smakebuf_r> - 4cbc: 8100030b ldhu r4,12(r16) - 4cc0: 81400417 ldw r5,16(r16) - 4cc4: 003fda06 br 4c30 <__swsetup_r+0x44> - 4cc8: 2080040c andi r2,r4,16 - 4ccc: 103fed26 beq r2,zero,4c84 <__swsetup_r+0x98> - 4cd0: 2080010c andi r2,r4,4 - 4cd4: 10001226 beq r2,zero,4d20 <__swsetup_r+0x134> - 4cd8: 81400c17 ldw r5,48(r16) - 4cdc: 28000526 beq r5,zero,4cf4 <__swsetup_r+0x108> - 4ce0: 80801004 addi r2,r16,64 - 4ce4: 28800226 beq r5,r2,4cf0 <__swsetup_r+0x104> - 4ce8: 8809883a mov r4,r17 - 4cec: 0006b700 call 6b70 <_free_r> - 4cf0: 80000c15 stw zero,48(r16) - 4cf4: 8080030b ldhu r2,12(r16) - 4cf8: 81400417 ldw r5,16(r16) - 4cfc: 80000115 stw zero,4(r16) - 4d00: 10bff6cc andi r2,r2,65499 - 4d04: 8080030d sth r2,12(r16) - 4d08: 81400015 stw r5,0(r16) - 4d0c: 8080030b ldhu r2,12(r16) - 4d10: 10800214 ori r2,r2,8 - 4d14: 113fffcc andi r4,r2,65535 - 4d18: 8080030d sth r2,12(r16) - 4d1c: 003fc306 br 4c2c <__swsetup_r+0x40> - 4d20: 81400417 ldw r5,16(r16) - 4d24: 003ff906 br 4d0c <__swsetup_r+0x120> - -00004d28 : - 4d28: 28c00417 ldw r3,16(r5) - 4d2c: 20800417 ldw r2,16(r4) - 4d30: defff104 addi sp,sp,-60 - 4d34: dfc00e15 stw ra,56(sp) - 4d38: df000d15 stw fp,52(sp) - 4d3c: ddc00c15 stw r23,48(sp) - 4d40: dd800b15 stw r22,44(sp) - 4d44: dd400a15 stw r21,40(sp) - 4d48: dd000915 stw r20,36(sp) - 4d4c: dcc00815 stw r19,32(sp) - 4d50: dc800715 stw r18,28(sp) - 4d54: dc400615 stw r17,24(sp) - 4d58: dc000515 stw r16,20(sp) - 4d5c: d9000315 stw r4,12(sp) - 4d60: d9400415 stw r5,16(sp) - 4d64: 10c07f16 blt r2,r3,4f64 - 4d68: 1d3fffc4 addi r20,r3,-1 - 4d6c: d8c00417 ldw r3,16(sp) - 4d70: d9000317 ldw r4,12(sp) - 4d74: a505883a add r2,r20,r20 - 4d78: 1085883a add r2,r2,r2 - 4d7c: 1cc00504 addi r19,r3,20 - 4d80: 25c00504 addi r23,r4,20 - 4d84: 98ad883a add r22,r19,r2 - 4d88: 15c7883a add r3,r2,r23 - 4d8c: b1400017 ldw r5,0(r22) - 4d90: 19000017 ldw r4,0(r3) - 4d94: d8c00015 stw r3,0(sp) - 4d98: 29400044 addi r5,r5,1 - 4d9c: d9000215 stw r4,8(sp) - 4da0: 0002b1c0 call 2b1c <__udivsi3> - 4da4: 1039883a mov fp,r2 - 4da8: 10003d1e bne r2,zero,4ea0 - 4dac: d9400417 ldw r5,16(sp) - 4db0: d9000317 ldw r4,12(sp) - 4db4: 00082900 call 8290 <__mcmp> - 4db8: 10002c16 blt r2,zero,4e6c - 4dbc: e7000044 addi fp,fp,1 - 4dc0: b80f883a mov r7,r23 - 4dc4: 0011883a mov r8,zero - 4dc8: 0009883a mov r4,zero - 4dcc: 99400017 ldw r5,0(r19) - 4dd0: 38c00017 ldw r3,0(r7) - 4dd4: 9cc00104 addi r19,r19,4 - 4dd8: 28bfffcc andi r2,r5,65535 - 4ddc: 2085883a add r2,r4,r2 - 4de0: 11bfffcc andi r6,r2,65535 - 4de4: 193fffcc andi r4,r3,65535 - 4de8: 1004d43a srli r2,r2,16 - 4dec: 280ad43a srli r5,r5,16 - 4df0: 2189c83a sub r4,r4,r6 - 4df4: 2209883a add r4,r4,r8 - 4df8: 1806d43a srli r3,r3,16 - 4dfc: 288b883a add r5,r5,r2 - 4e00: 200dd43a srai r6,r4,16 - 4e04: 28bfffcc andi r2,r5,65535 - 4e08: 1887c83a sub r3,r3,r2 - 4e0c: 1987883a add r3,r3,r6 - 4e10: 3900000d sth r4,0(r7) - 4e14: 38c0008d sth r3,2(r7) - 4e18: 2808d43a srli r4,r5,16 - 4e1c: 39c00104 addi r7,r7,4 - 4e20: 1811d43a srai r8,r3,16 - 4e24: b4ffe92e bgeu r22,r19,4dcc - 4e28: a505883a add r2,r20,r20 - 4e2c: 1085883a add r2,r2,r2 - 4e30: b885883a add r2,r23,r2 - 4e34: 10c00017 ldw r3,0(r2) - 4e38: 18000c1e bne r3,zero,4e6c - 4e3c: 113fff04 addi r4,r2,-4 - 4e40: b900082e bgeu r23,r4,4e64 - 4e44: 10bfff17 ldw r2,-4(r2) - 4e48: 10000326 beq r2,zero,4e58 - 4e4c: 00000506 br 4e64 - 4e50: 20800017 ldw r2,0(r4) - 4e54: 1000031e bne r2,zero,4e64 - 4e58: 213fff04 addi r4,r4,-4 - 4e5c: a53fffc4 addi r20,r20,-1 - 4e60: b93ffb36 bltu r23,r4,4e50 - 4e64: d9000317 ldw r4,12(sp) - 4e68: 25000415 stw r20,16(r4) - 4e6c: e005883a mov r2,fp - 4e70: dfc00e17 ldw ra,56(sp) - 4e74: df000d17 ldw fp,52(sp) - 4e78: ddc00c17 ldw r23,48(sp) - 4e7c: dd800b17 ldw r22,44(sp) - 4e80: dd400a17 ldw r21,40(sp) - 4e84: dd000917 ldw r20,36(sp) - 4e88: dcc00817 ldw r19,32(sp) - 4e8c: dc800717 ldw r18,28(sp) - 4e90: dc400617 ldw r17,24(sp) - 4e94: dc000517 ldw r16,20(sp) - 4e98: dec00f04 addi sp,sp,60 - 4e9c: f800283a ret - 4ea0: b823883a mov r17,r23 - 4ea4: 9825883a mov r18,r19 - 4ea8: d8000115 stw zero,4(sp) - 4eac: 002b883a mov r21,zero - 4eb0: 94000017 ldw r16,0(r18) - 4eb4: e009883a mov r4,fp - 4eb8: 94800104 addi r18,r18,4 - 4ebc: 817fffcc andi r5,r16,65535 - 4ec0: 0002b2c0 call 2b2c <__mulsi3> - 4ec4: 800ad43a srli r5,r16,16 - 4ec8: e009883a mov r4,fp - 4ecc: a8a1883a add r16,r21,r2 - 4ed0: 0002b2c0 call 2b2c <__mulsi3> - 4ed4: 89000017 ldw r4,0(r17) - 4ed8: 80ffffcc andi r3,r16,65535 - 4edc: 8020d43a srli r16,r16,16 - 4ee0: 217fffcc andi r5,r4,65535 - 4ee4: 28cbc83a sub r5,r5,r3 - 4ee8: d8c00117 ldw r3,4(sp) - 4eec: 2008d43a srli r4,r4,16 - 4ef0: 1405883a add r2,r2,r16 - 4ef4: 28cb883a add r5,r5,r3 - 4ef8: 280dd43a srai r6,r5,16 - 4efc: 10ffffcc andi r3,r2,65535 - 4f00: 20c9c83a sub r4,r4,r3 - 4f04: 2189883a add r4,r4,r6 - 4f08: 8900008d sth r4,2(r17) - 4f0c: 2009d43a srai r4,r4,16 - 4f10: 8940000d sth r5,0(r17) - 4f14: 102ad43a srli r21,r2,16 - 4f18: 8c400104 addi r17,r17,4 - 4f1c: d9000115 stw r4,4(sp) - 4f20: b4bfe32e bgeu r22,r18,4eb0 - 4f24: d9000217 ldw r4,8(sp) - 4f28: 203fa01e bne r4,zero,4dac - 4f2c: d8800017 ldw r2,0(sp) - 4f30: 10ffff04 addi r3,r2,-4 - 4f34: b8c0082e bgeu r23,r3,4f58 - 4f38: 10bfff17 ldw r2,-4(r2) - 4f3c: 10000326 beq r2,zero,4f4c - 4f40: 00000506 br 4f58 - 4f44: 18800017 ldw r2,0(r3) - 4f48: 1000031e bne r2,zero,4f58 - 4f4c: 18ffff04 addi r3,r3,-4 - 4f50: a53fffc4 addi r20,r20,-1 - 4f54: b8fffb36 bltu r23,r3,4f44 - 4f58: d8c00317 ldw r3,12(sp) - 4f5c: 1d000415 stw r20,16(r3) - 4f60: 003f9206 br 4dac - 4f64: 0005883a mov r2,zero - 4f68: 003fc106 br 4e70 - -00004f6c <_dtoa_r>: - 4f6c: 22001017 ldw r8,64(r4) - 4f70: deffda04 addi sp,sp,-152 - 4f74: dd402115 stw r21,132(sp) - 4f78: dd002015 stw r20,128(sp) - 4f7c: dc801e15 stw r18,120(sp) - 4f80: dc401d15 stw r17,116(sp) - 4f84: dfc02515 stw ra,148(sp) - 4f88: df002415 stw fp,144(sp) - 4f8c: ddc02315 stw r23,140(sp) - 4f90: dd802215 stw r22,136(sp) - 4f94: dcc01f15 stw r19,124(sp) - 4f98: dc001c15 stw r16,112(sp) - 4f9c: d9001615 stw r4,88(sp) - 4fa0: 3023883a mov r17,r6 - 4fa4: 2829883a mov r20,r5 - 4fa8: d9c01715 stw r7,92(sp) - 4fac: dc802817 ldw r18,160(sp) - 4fb0: 302b883a mov r21,r6 - 4fb4: 40000a26 beq r8,zero,4fe0 <_dtoa_r+0x74> - 4fb8: 20801117 ldw r2,68(r4) - 4fbc: 400b883a mov r5,r8 - 4fc0: 40800115 stw r2,4(r8) - 4fc4: 20c01117 ldw r3,68(r4) - 4fc8: 00800044 movi r2,1 - 4fcc: 10c4983a sll r2,r2,r3 - 4fd0: 40800215 stw r2,8(r8) - 4fd4: 00081340 call 8134 <_Bfree> - 4fd8: d8c01617 ldw r3,88(sp) - 4fdc: 18001015 stw zero,64(r3) - 4fe0: 8800a316 blt r17,zero,5270 <_dtoa_r+0x304> - 4fe4: 90000015 stw zero,0(r18) - 4fe8: a8dffc2c andhi r3,r21,32752 - 4fec: 009ffc34 movhi r2,32752 - 4ff0: 18809126 beq r3,r2,5238 <_dtoa_r+0x2cc> - 4ff4: 000d883a mov r6,zero - 4ff8: 000f883a mov r7,zero - 4ffc: a009883a mov r4,r20 - 5000: a80b883a mov r5,r21 - 5004: dd001215 stw r20,72(sp) - 5008: dd401315 stw r21,76(sp) - 500c: 000b7b80 call b7b8 <__nedf2> - 5010: 1000171e bne r2,zero,5070 <_dtoa_r+0x104> - 5014: d9802717 ldw r6,156(sp) - 5018: 00800044 movi r2,1 - 501c: 30800015 stw r2,0(r6) - 5020: d8802917 ldw r2,164(sp) - 5024: 10029b26 beq r2,zero,5a94 <_dtoa_r+0xb28> - 5028: d9002917 ldw r4,164(sp) - 502c: 00800074 movhi r2,1 - 5030: 1080b344 addi r2,r2,717 - 5034: 10ffffc4 addi r3,r2,-1 - 5038: 20800015 stw r2,0(r4) - 503c: 1805883a mov r2,r3 - 5040: dfc02517 ldw ra,148(sp) - 5044: df002417 ldw fp,144(sp) - 5048: ddc02317 ldw r23,140(sp) - 504c: dd802217 ldw r22,136(sp) - 5050: dd402117 ldw r21,132(sp) - 5054: dd002017 ldw r20,128(sp) - 5058: dcc01f17 ldw r19,124(sp) - 505c: dc801e17 ldw r18,120(sp) - 5060: dc401d17 ldw r17,116(sp) - 5064: dc001c17 ldw r16,112(sp) - 5068: dec02604 addi sp,sp,152 - 506c: f800283a ret - 5070: d9001617 ldw r4,88(sp) - 5074: d9401217 ldw r5,72(sp) - 5078: d8800104 addi r2,sp,4 - 507c: a80d883a mov r6,r21 - 5080: d9c00204 addi r7,sp,8 - 5084: d8800015 stw r2,0(sp) - 5088: 00087700 call 8770 <__d2b> - 508c: d8800715 stw r2,28(sp) - 5090: a804d53a srli r2,r21,20 - 5094: 1101ffcc andi r4,r2,2047 - 5098: 20008626 beq r4,zero,52b4 <_dtoa_r+0x348> - 509c: d8c01217 ldw r3,72(sp) - 50a0: 00800434 movhi r2,16 - 50a4: 10bfffc4 addi r2,r2,-1 - 50a8: ddc00117 ldw r23,4(sp) - 50ac: a884703a and r2,r21,r2 - 50b0: 1811883a mov r8,r3 - 50b4: 124ffc34 orhi r9,r2,16368 - 50b8: 25bf0044 addi r22,r4,-1023 - 50bc: d8000815 stw zero,32(sp) - 50c0: 0005883a mov r2,zero - 50c4: 00cffe34 movhi r3,16376 - 50c8: 480b883a mov r5,r9 - 50cc: 4009883a mov r4,r8 - 50d0: 180f883a mov r7,r3 - 50d4: 100d883a mov r6,r2 - 50d8: 000b0200 call b020 <__subdf3> - 50dc: 0218dbf4 movhi r8,25455 - 50e0: 4210d844 addi r8,r8,17249 - 50e4: 024ff4f4 movhi r9,16339 - 50e8: 4a61e9c4 addi r9,r9,-30809 - 50ec: 480f883a mov r7,r9 - 50f0: 400d883a mov r6,r8 - 50f4: 180b883a mov r5,r3 - 50f8: 1009883a mov r4,r2 - 50fc: 000b1140 call b114 <__muldf3> - 5100: 0222d874 movhi r8,35681 - 5104: 42322cc4 addi r8,r8,-14157 - 5108: 024ff1f4 movhi r9,16327 - 510c: 4a628a04 addi r9,r9,-30168 - 5110: 480f883a mov r7,r9 - 5114: 400d883a mov r6,r8 - 5118: 180b883a mov r5,r3 - 511c: 1009883a mov r4,r2 - 5120: 000b0a00 call b0a0 <__adddf3> - 5124: b009883a mov r4,r22 - 5128: 1021883a mov r16,r2 - 512c: 1823883a mov r17,r3 - 5130: 000b9d80 call b9d8 <__floatsidf> - 5134: 021427f4 movhi r8,20639 - 5138: 421e7ec4 addi r8,r8,31227 - 513c: 024ff4f4 movhi r9,16339 - 5140: 4a5104c4 addi r9,r9,17427 - 5144: 480f883a mov r7,r9 - 5148: 400d883a mov r6,r8 - 514c: 180b883a mov r5,r3 - 5150: 1009883a mov r4,r2 - 5154: 000b1140 call b114 <__muldf3> - 5158: 180f883a mov r7,r3 - 515c: 880b883a mov r5,r17 - 5160: 100d883a mov r6,r2 - 5164: 8009883a mov r4,r16 - 5168: 000b0a00 call b0a0 <__adddf3> - 516c: 1009883a mov r4,r2 - 5170: 180b883a mov r5,r3 - 5174: 1021883a mov r16,r2 - 5178: 1823883a mov r17,r3 - 517c: 000bad00 call bad0 <__fixdfsi> - 5180: 000d883a mov r6,zero - 5184: 000f883a mov r7,zero - 5188: 8009883a mov r4,r16 - 518c: 880b883a mov r5,r17 - 5190: d8800d15 stw r2,52(sp) - 5194: 000b9500 call b950 <__ltdf2> - 5198: 10031716 blt r2,zero,5df8 <_dtoa_r+0xe8c> - 519c: d8c00d17 ldw r3,52(sp) - 51a0: 00800584 movi r2,22 - 51a4: 10c1482e bgeu r2,r3,56c8 <_dtoa_r+0x75c> - 51a8: 01000044 movi r4,1 - 51ac: d9000c15 stw r4,48(sp) - 51b0: bd85c83a sub r2,r23,r22 - 51b4: 11bfffc4 addi r6,r2,-1 - 51b8: 30030b16 blt r6,zero,5de8 <_dtoa_r+0xe7c> - 51bc: d9800a15 stw r6,40(sp) - 51c0: d8001115 stw zero,68(sp) - 51c4: d8c00d17 ldw r3,52(sp) - 51c8: 1802ff16 blt r3,zero,5dc8 <_dtoa_r+0xe5c> - 51cc: d9000a17 ldw r4,40(sp) - 51d0: d8c00915 stw r3,36(sp) - 51d4: d8001015 stw zero,64(sp) - 51d8: 20c9883a add r4,r4,r3 - 51dc: d9000a15 stw r4,40(sp) - 51e0: d9001717 ldw r4,92(sp) - 51e4: 00800244 movi r2,9 - 51e8: 11004636 bltu r2,r4,5304 <_dtoa_r+0x398> - 51ec: 00800144 movi r2,5 - 51f0: 11020416 blt r2,r4,5a04 <_dtoa_r+0xa98> - 51f4: 04400044 movi r17,1 - 51f8: d8c01717 ldw r3,92(sp) - 51fc: 00800144 movi r2,5 - 5200: 10c1ed36 bltu r2,r3,59b8 <_dtoa_r+0xa4c> - 5204: 18c5883a add r2,r3,r3 - 5208: 1085883a add r2,r2,r2 - 520c: 00c00034 movhi r3,0 - 5210: 18d48804 addi r3,r3,21024 - 5214: 10c5883a add r2,r2,r3 - 5218: 11000017 ldw r4,0(r2) - 521c: 2000683a jmp r4 - 5220: 0000530c andi zero,zero,332 - 5224: 0000530c andi zero,zero,332 - 5228: 00005d0c andi zero,zero,372 - 522c: 00005ce4 muli zero,zero,371 - 5230: 00005d28 cmpgeui zero,zero,372 - 5234: 00005d34 movhi zero,372 - 5238: d9002717 ldw r4,156(sp) - 523c: 0089c3c4 movi r2,9999 - 5240: 20800015 stw r2,0(r4) - 5244: a0001026 beq r20,zero,5288 <_dtoa_r+0x31c> - 5248: 00c00074 movhi r3,1 - 524c: 18c0bf04 addi r3,r3,764 - 5250: d9802917 ldw r6,164(sp) - 5254: 303f7926 beq r6,zero,503c <_dtoa_r+0xd0> - 5258: 188000c7 ldb r2,3(r3) - 525c: 190000c4 addi r4,r3,3 - 5260: 1000101e bne r2,zero,52a4 <_dtoa_r+0x338> - 5264: d8802917 ldw r2,164(sp) - 5268: 11000015 stw r4,0(r2) - 526c: 003f7306 br 503c <_dtoa_r+0xd0> - 5270: 00a00034 movhi r2,32768 - 5274: 10bfffc4 addi r2,r2,-1 - 5278: 00c00044 movi r3,1 - 527c: 88aa703a and r21,r17,r2 - 5280: 90c00015 stw r3,0(r18) - 5284: 003f5806 br 4fe8 <_dtoa_r+0x7c> - 5288: 00800434 movhi r2,16 - 528c: 10bfffc4 addi r2,r2,-1 - 5290: a884703a and r2,r21,r2 - 5294: 103fec1e bne r2,zero,5248 <_dtoa_r+0x2dc> - 5298: 00c00074 movhi r3,1 - 529c: 18c0bc04 addi r3,r3,752 - 52a0: 003feb06 br 5250 <_dtoa_r+0x2e4> - 52a4: d8802917 ldw r2,164(sp) - 52a8: 19000204 addi r4,r3,8 - 52ac: 11000015 stw r4,0(r2) - 52b0: 003f6206 br 503c <_dtoa_r+0xd0> - 52b4: ddc00117 ldw r23,4(sp) - 52b8: d8800217 ldw r2,8(sp) - 52bc: 01000804 movi r4,32 - 52c0: b8c10c84 addi r3,r23,1074 - 52c4: 18a3883a add r17,r3,r2 - 52c8: 2441b80e bge r4,r17,59ac <_dtoa_r+0xa40> - 52cc: 00c01004 movi r3,64 - 52d0: 1c47c83a sub r3,r3,r17 - 52d4: 88bff804 addi r2,r17,-32 - 52d8: a8c6983a sll r3,r21,r3 - 52dc: a084d83a srl r2,r20,r2 - 52e0: 1888b03a or r4,r3,r2 - 52e4: 000bba80 call bba8 <__floatunsidf> - 52e8: 1011883a mov r8,r2 - 52ec: 00bf8434 movhi r2,65040 - 52f0: 01000044 movi r4,1 - 52f4: 10d3883a add r9,r2,r3 - 52f8: 8dbef344 addi r22,r17,-1075 - 52fc: d9000815 stw r4,32(sp) - 5300: 003f6f06 br 50c0 <_dtoa_r+0x154> - 5304: d8001715 stw zero,92(sp) - 5308: 04400044 movi r17,1 - 530c: 00bfffc4 movi r2,-1 - 5310: 00c00044 movi r3,1 - 5314: d8800e15 stw r2,56(sp) - 5318: d8002615 stw zero,152(sp) - 531c: d8800f15 stw r2,60(sp) - 5320: d8c00b15 stw r3,44(sp) - 5324: 1021883a mov r16,r2 - 5328: d8801617 ldw r2,88(sp) - 532c: 10001115 stw zero,68(r2) - 5330: d8801617 ldw r2,88(sp) - 5334: 11401117 ldw r5,68(r2) - 5338: 1009883a mov r4,r2 - 533c: 00086b40 call 86b4 <_Balloc> - 5340: d8c01617 ldw r3,88(sp) - 5344: d8800515 stw r2,20(sp) - 5348: 18801015 stw r2,64(r3) - 534c: 00800384 movi r2,14 - 5350: 14006836 bltu r2,r16,54f4 <_dtoa_r+0x588> - 5354: 8805003a cmpeq r2,r17,zero - 5358: 1000661e bne r2,zero,54f4 <_dtoa_r+0x588> - 535c: d9000d17 ldw r4,52(sp) - 5360: 0102300e bge zero,r4,5c24 <_dtoa_r+0xcb8> - 5364: 208003cc andi r2,r4,15 - 5368: 100490fa slli r2,r2,3 - 536c: 2025d13a srai r18,r4,4 - 5370: 00c00074 movhi r3,1 - 5374: 18c0d104 addi r3,r3,836 - 5378: 10c5883a add r2,r2,r3 - 537c: 90c0040c andi r3,r18,16 - 5380: 14000017 ldw r16,0(r2) - 5384: 14400117 ldw r17,4(r2) - 5388: 18036a1e bne r3,zero,6134 <_dtoa_r+0x11c8> - 538c: 05800084 movi r22,2 - 5390: 90001026 beq r18,zero,53d4 <_dtoa_r+0x468> - 5394: 04c00074 movhi r19,1 - 5398: 9cc10304 addi r19,r19,1036 - 539c: 9080004c andi r2,r18,1 - 53a0: 1005003a cmpeq r2,r2,zero - 53a4: 1000081e bne r2,zero,53c8 <_dtoa_r+0x45c> - 53a8: 99800017 ldw r6,0(r19) - 53ac: 99c00117 ldw r7,4(r19) - 53b0: 880b883a mov r5,r17 - 53b4: 8009883a mov r4,r16 - 53b8: 000b1140 call b114 <__muldf3> - 53bc: 1021883a mov r16,r2 - 53c0: b5800044 addi r22,r22,1 - 53c4: 1823883a mov r17,r3 - 53c8: 9025d07a srai r18,r18,1 - 53cc: 9cc00204 addi r19,r19,8 - 53d0: 903ff21e bne r18,zero,539c <_dtoa_r+0x430> - 53d4: a80b883a mov r5,r21 - 53d8: a009883a mov r4,r20 - 53dc: 880f883a mov r7,r17 - 53e0: 800d883a mov r6,r16 - 53e4: 000b4d80 call b4d8 <__divdf3> - 53e8: 1029883a mov r20,r2 - 53ec: 182b883a mov r21,r3 - 53f0: d8c00c17 ldw r3,48(sp) - 53f4: 1805003a cmpeq r2,r3,zero - 53f8: 1000081e bne r2,zero,541c <_dtoa_r+0x4b0> - 53fc: 0005883a mov r2,zero - 5400: 00cffc34 movhi r3,16368 - 5404: 180f883a mov r7,r3 - 5408: a009883a mov r4,r20 - 540c: a80b883a mov r5,r21 - 5410: 100d883a mov r6,r2 - 5414: 000b9500 call b950 <__ltdf2> - 5418: 1003fe16 blt r2,zero,6414 <_dtoa_r+0x14a8> - 541c: b009883a mov r4,r22 - 5420: 000b9d80 call b9d8 <__floatsidf> - 5424: 180b883a mov r5,r3 - 5428: 1009883a mov r4,r2 - 542c: a00d883a mov r6,r20 - 5430: a80f883a mov r7,r21 - 5434: 000b1140 call b114 <__muldf3> - 5438: 0011883a mov r8,zero - 543c: 02500734 movhi r9,16412 - 5440: 1009883a mov r4,r2 - 5444: 180b883a mov r5,r3 - 5448: 480f883a mov r7,r9 - 544c: 400d883a mov r6,r8 - 5450: 000b0a00 call b0a0 <__adddf3> - 5454: d9000f17 ldw r4,60(sp) - 5458: 102d883a mov r22,r2 - 545c: 00bf3034 movhi r2,64704 - 5460: 18b9883a add fp,r3,r2 - 5464: e02f883a mov r23,fp - 5468: 20028f1e bne r4,zero,5ea8 <_dtoa_r+0xf3c> - 546c: 0005883a mov r2,zero - 5470: 00d00534 movhi r3,16404 - 5474: a009883a mov r4,r20 - 5478: a80b883a mov r5,r21 - 547c: 180f883a mov r7,r3 - 5480: 100d883a mov r6,r2 - 5484: 000b0200 call b020 <__subdf3> - 5488: 1009883a mov r4,r2 - 548c: e00f883a mov r7,fp - 5490: 180b883a mov r5,r3 - 5494: b00d883a mov r6,r22 - 5498: 1025883a mov r18,r2 - 549c: 1827883a mov r19,r3 - 54a0: 000b8400 call b840 <__gtdf2> - 54a4: 00834f16 blt zero,r2,61e4 <_dtoa_r+0x1278> - 54a8: e0e0003c xorhi r3,fp,32768 - 54ac: 9009883a mov r4,r18 - 54b0: 980b883a mov r5,r19 - 54b4: 180f883a mov r7,r3 - 54b8: b00d883a mov r6,r22 - 54bc: 000b9500 call b950 <__ltdf2> - 54c0: 1000080e bge r2,zero,54e4 <_dtoa_r+0x578> - 54c4: 0027883a mov r19,zero - 54c8: 0025883a mov r18,zero - 54cc: d8802617 ldw r2,152(sp) - 54d0: df000517 ldw fp,20(sp) - 54d4: d8000615 stw zero,24(sp) - 54d8: 0084303a nor r2,zero,r2 - 54dc: d8800d15 stw r2,52(sp) - 54e0: 00019b06 br 5b50 <_dtoa_r+0xbe4> - 54e4: d9801217 ldw r6,72(sp) - 54e8: d8801317 ldw r2,76(sp) - 54ec: 3029883a mov r20,r6 - 54f0: 102b883a mov r21,r2 - 54f4: d8c00217 ldw r3,8(sp) - 54f8: 18008516 blt r3,zero,5710 <_dtoa_r+0x7a4> - 54fc: d9000d17 ldw r4,52(sp) - 5500: 00800384 movi r2,14 - 5504: 11008216 blt r2,r4,5710 <_dtoa_r+0x7a4> - 5508: 200490fa slli r2,r4,3 - 550c: d9802617 ldw r6,152(sp) - 5510: 00c00074 movhi r3,1 - 5514: 18c0d104 addi r3,r3,836 - 5518: 10c5883a add r2,r2,r3 - 551c: 14800017 ldw r18,0(r2) - 5520: 14c00117 ldw r19,4(r2) - 5524: 30031e16 blt r6,zero,61a0 <_dtoa_r+0x1234> - 5528: d9000517 ldw r4,20(sp) - 552c: d8c00f17 ldw r3,60(sp) - 5530: a823883a mov r17,r21 - 5534: a021883a mov r16,r20 - 5538: 192b883a add r21,r3,r4 - 553c: 2039883a mov fp,r4 - 5540: 00000f06 br 5580 <_dtoa_r+0x614> - 5544: 0005883a mov r2,zero - 5548: 00d00934 movhi r3,16420 - 554c: 5009883a mov r4,r10 - 5550: 580b883a mov r5,r11 - 5554: 180f883a mov r7,r3 - 5558: 100d883a mov r6,r2 - 555c: 000b1140 call b114 <__muldf3> - 5560: 180b883a mov r5,r3 - 5564: 000d883a mov r6,zero - 5568: 000f883a mov r7,zero - 556c: 1009883a mov r4,r2 - 5570: 1021883a mov r16,r2 - 5574: 1823883a mov r17,r3 - 5578: 000b7b80 call b7b8 <__nedf2> - 557c: 10004526 beq r2,zero,5694 <_dtoa_r+0x728> - 5580: 900d883a mov r6,r18 - 5584: 980f883a mov r7,r19 - 5588: 8009883a mov r4,r16 - 558c: 880b883a mov r5,r17 - 5590: 000b4d80 call b4d8 <__divdf3> - 5594: 180b883a mov r5,r3 - 5598: 1009883a mov r4,r2 - 559c: 000bad00 call bad0 <__fixdfsi> - 55a0: 1009883a mov r4,r2 - 55a4: 1029883a mov r20,r2 - 55a8: 000b9d80 call b9d8 <__floatsidf> - 55ac: 180f883a mov r7,r3 - 55b0: 9009883a mov r4,r18 - 55b4: 980b883a mov r5,r19 - 55b8: 100d883a mov r6,r2 - 55bc: 000b1140 call b114 <__muldf3> - 55c0: 180f883a mov r7,r3 - 55c4: 880b883a mov r5,r17 - 55c8: 8009883a mov r4,r16 - 55cc: 100d883a mov r6,r2 - 55d0: 000b0200 call b020 <__subdf3> - 55d4: 1015883a mov r10,r2 - 55d8: a0800c04 addi r2,r20,48 - 55dc: e0800005 stb r2,0(fp) - 55e0: e7000044 addi fp,fp,1 - 55e4: 1817883a mov r11,r3 - 55e8: e57fd61e bne fp,r21,5544 <_dtoa_r+0x5d8> - 55ec: 500d883a mov r6,r10 - 55f0: 180f883a mov r7,r3 - 55f4: 5009883a mov r4,r10 - 55f8: 180b883a mov r5,r3 - 55fc: 000b0a00 call b0a0 <__adddf3> - 5600: 100d883a mov r6,r2 - 5604: 9009883a mov r4,r18 - 5608: 980b883a mov r5,r19 - 560c: 180f883a mov r7,r3 - 5610: 1021883a mov r16,r2 - 5614: 1823883a mov r17,r3 - 5618: 000b9500 call b950 <__ltdf2> - 561c: 10000816 blt r2,zero,5640 <_dtoa_r+0x6d4> - 5620: 980b883a mov r5,r19 - 5624: 800d883a mov r6,r16 - 5628: 880f883a mov r7,r17 - 562c: 9009883a mov r4,r18 - 5630: 000b7300 call b730 <__eqdf2> - 5634: 1000171e bne r2,zero,5694 <_dtoa_r+0x728> - 5638: a080004c andi r2,r20,1 - 563c: 10001526 beq r2,zero,5694 <_dtoa_r+0x728> - 5640: d8800d17 ldw r2,52(sp) - 5644: d8800415 stw r2,16(sp) - 5648: e009883a mov r4,fp - 564c: 213fffc4 addi r4,r4,-1 - 5650: 20c00007 ldb r3,0(r4) - 5654: 00800e44 movi r2,57 - 5658: 1880081e bne r3,r2,567c <_dtoa_r+0x710> - 565c: d8800517 ldw r2,20(sp) - 5660: 113ffa1e bne r2,r4,564c <_dtoa_r+0x6e0> - 5664: d8c00417 ldw r3,16(sp) - 5668: d9800517 ldw r6,20(sp) - 566c: 00800c04 movi r2,48 - 5670: 18c00044 addi r3,r3,1 - 5674: d8c00415 stw r3,16(sp) - 5678: 30800005 stb r2,0(r6) - 567c: 20800003 ldbu r2,0(r4) - 5680: d8c00417 ldw r3,16(sp) - 5684: 27000044 addi fp,r4,1 - 5688: 10800044 addi r2,r2,1 - 568c: d8c00d15 stw r3,52(sp) - 5690: 20800005 stb r2,0(r4) - 5694: d9001617 ldw r4,88(sp) - 5698: d9400717 ldw r5,28(sp) - 569c: 00081340 call 8134 <_Bfree> - 56a0: e0000005 stb zero,0(fp) - 56a4: d9800d17 ldw r6,52(sp) - 56a8: d8c02717 ldw r3,156(sp) - 56ac: d9002917 ldw r4,164(sp) - 56b0: 30800044 addi r2,r6,1 - 56b4: 18800015 stw r2,0(r3) - 56b8: 20029c26 beq r4,zero,612c <_dtoa_r+0x11c0> - 56bc: d8c00517 ldw r3,20(sp) - 56c0: 27000015 stw fp,0(r4) - 56c4: 003e5d06 br 503c <_dtoa_r+0xd0> - 56c8: d9800d17 ldw r6,52(sp) - 56cc: 00c00074 movhi r3,1 - 56d0: 18c0d104 addi r3,r3,836 - 56d4: d9001217 ldw r4,72(sp) - 56d8: 300490fa slli r2,r6,3 - 56dc: d9401317 ldw r5,76(sp) - 56e0: 10c5883a add r2,r2,r3 - 56e4: 12000017 ldw r8,0(r2) - 56e8: 12400117 ldw r9,4(r2) - 56ec: 400d883a mov r6,r8 - 56f0: 480f883a mov r7,r9 - 56f4: 000b9500 call b950 <__ltdf2> - 56f8: 1000030e bge r2,zero,5708 <_dtoa_r+0x79c> - 56fc: d8800d17 ldw r2,52(sp) - 5700: 10bfffc4 addi r2,r2,-1 - 5704: d8800d15 stw r2,52(sp) - 5708: d8000c15 stw zero,48(sp) - 570c: 003ea806 br 51b0 <_dtoa_r+0x244> - 5710: d9000b17 ldw r4,44(sp) - 5714: 202cc03a cmpne r22,r4,zero - 5718: b000c71e bne r22,zero,5a38 <_dtoa_r+0xacc> - 571c: dc001117 ldw r16,68(sp) - 5720: dc801017 ldw r18,64(sp) - 5724: 0027883a mov r19,zero - 5728: 04000b0e bge zero,r16,5758 <_dtoa_r+0x7ec> - 572c: d8c00a17 ldw r3,40(sp) - 5730: 00c0090e bge zero,r3,5758 <_dtoa_r+0x7ec> - 5734: 8005883a mov r2,r16 - 5738: 1c011316 blt r3,r16,5b88 <_dtoa_r+0xc1c> - 573c: d9000a17 ldw r4,40(sp) - 5740: d9801117 ldw r6,68(sp) - 5744: 80a1c83a sub r16,r16,r2 - 5748: 2089c83a sub r4,r4,r2 - 574c: 308dc83a sub r6,r6,r2 - 5750: d9000a15 stw r4,40(sp) - 5754: d9801115 stw r6,68(sp) - 5758: d8801017 ldw r2,64(sp) - 575c: 0080150e bge zero,r2,57b4 <_dtoa_r+0x848> - 5760: d8c00b17 ldw r3,44(sp) - 5764: 1805003a cmpeq r2,r3,zero - 5768: 1001c91e bne r2,zero,5e90 <_dtoa_r+0xf24> - 576c: 04800e0e bge zero,r18,57a8 <_dtoa_r+0x83c> - 5770: d9001617 ldw r4,88(sp) - 5774: 980b883a mov r5,r19 - 5778: 900d883a mov r6,r18 - 577c: 0008f800 call 8f80 <__pow5mult> - 5780: d9001617 ldw r4,88(sp) - 5784: d9800717 ldw r6,28(sp) - 5788: 100b883a mov r5,r2 - 578c: 1027883a mov r19,r2 - 5790: 0008bc40 call 8bc4 <__multiply> - 5794: d9001617 ldw r4,88(sp) - 5798: d9400717 ldw r5,28(sp) - 579c: 1023883a mov r17,r2 - 57a0: 00081340 call 8134 <_Bfree> - 57a4: dc400715 stw r17,28(sp) - 57a8: d9001017 ldw r4,64(sp) - 57ac: 248dc83a sub r6,r4,r18 - 57b0: 30010e1e bne r6,zero,5bec <_dtoa_r+0xc80> - 57b4: d9001617 ldw r4,88(sp) - 57b8: 04400044 movi r17,1 - 57bc: 880b883a mov r5,r17 - 57c0: 0008e180 call 8e18 <__i2b> - 57c4: d9800917 ldw r6,36(sp) - 57c8: 1025883a mov r18,r2 - 57cc: 0180040e bge zero,r6,57e0 <_dtoa_r+0x874> - 57d0: d9001617 ldw r4,88(sp) - 57d4: 100b883a mov r5,r2 - 57d8: 0008f800 call 8f80 <__pow5mult> - 57dc: 1025883a mov r18,r2 - 57e0: d8801717 ldw r2,92(sp) - 57e4: 8880f30e bge r17,r2,5bb4 <_dtoa_r+0xc48> - 57e8: 0023883a mov r17,zero - 57ec: d9800917 ldw r6,36(sp) - 57f0: 30019e1e bne r6,zero,5e6c <_dtoa_r+0xf00> - 57f4: 00c00044 movi r3,1 - 57f8: d9000a17 ldw r4,40(sp) - 57fc: 20c5883a add r2,r4,r3 - 5800: 10c007cc andi r3,r2,31 - 5804: 1800841e bne r3,zero,5a18 <_dtoa_r+0xaac> - 5808: 00800704 movi r2,28 - 580c: d9000a17 ldw r4,40(sp) - 5810: d9801117 ldw r6,68(sp) - 5814: 80a1883a add r16,r16,r2 - 5818: 2089883a add r4,r4,r2 - 581c: 308d883a add r6,r6,r2 - 5820: d9000a15 stw r4,40(sp) - 5824: d9801115 stw r6,68(sp) - 5828: d8801117 ldw r2,68(sp) - 582c: 0080050e bge zero,r2,5844 <_dtoa_r+0x8d8> - 5830: d9400717 ldw r5,28(sp) - 5834: d9001617 ldw r4,88(sp) - 5838: 100d883a mov r6,r2 - 583c: 0008a780 call 8a78 <__lshift> - 5840: d8800715 stw r2,28(sp) - 5844: d8c00a17 ldw r3,40(sp) - 5848: 00c0050e bge zero,r3,5860 <_dtoa_r+0x8f4> - 584c: d9001617 ldw r4,88(sp) - 5850: 900b883a mov r5,r18 - 5854: 180d883a mov r6,r3 - 5858: 0008a780 call 8a78 <__lshift> - 585c: 1025883a mov r18,r2 - 5860: d9000c17 ldw r4,48(sp) - 5864: 2005003a cmpeq r2,r4,zero - 5868: 10016f26 beq r2,zero,5e28 <_dtoa_r+0xebc> - 586c: d9000f17 ldw r4,60(sp) - 5870: 0102170e bge zero,r4,60d0 <_dtoa_r+0x1164> - 5874: d9800b17 ldw r6,44(sp) - 5878: 3005003a cmpeq r2,r6,zero - 587c: 1000881e bne r2,zero,5aa0 <_dtoa_r+0xb34> - 5880: 0400050e bge zero,r16,5898 <_dtoa_r+0x92c> - 5884: d9001617 ldw r4,88(sp) - 5888: 980b883a mov r5,r19 - 588c: 800d883a mov r6,r16 - 5890: 0008a780 call 8a78 <__lshift> - 5894: 1027883a mov r19,r2 - 5898: 8804c03a cmpne r2,r17,zero - 589c: 1002541e bne r2,zero,61f0 <_dtoa_r+0x1284> - 58a0: 980b883a mov r5,r19 - 58a4: dd800517 ldw r22,20(sp) - 58a8: dcc00615 stw r19,24(sp) - 58ac: a700004c andi fp,r20,1 - 58b0: 2827883a mov r19,r5 - 58b4: d9000717 ldw r4,28(sp) - 58b8: 900b883a mov r5,r18 - 58bc: 0004d280 call 4d28 - 58c0: d9000717 ldw r4,28(sp) - 58c4: d9400617 ldw r5,24(sp) - 58c8: 1023883a mov r17,r2 - 58cc: 8dc00c04 addi r23,r17,48 - 58d0: 00082900 call 8290 <__mcmp> - 58d4: d9001617 ldw r4,88(sp) - 58d8: 900b883a mov r5,r18 - 58dc: 980d883a mov r6,r19 - 58e0: 1029883a mov r20,r2 - 58e4: 00088ec0 call 88ec <__mdiff> - 58e8: 102b883a mov r21,r2 - 58ec: 10800317 ldw r2,12(r2) - 58f0: 1001281e bne r2,zero,5d94 <_dtoa_r+0xe28> - 58f4: d9000717 ldw r4,28(sp) - 58f8: a80b883a mov r5,r21 - 58fc: 00082900 call 8290 <__mcmp> - 5900: d9001617 ldw r4,88(sp) - 5904: 1021883a mov r16,r2 - 5908: a80b883a mov r5,r21 - 590c: 00081340 call 8134 <_Bfree> - 5910: 8000041e bne r16,zero,5924 <_dtoa_r+0x9b8> - 5914: d8801717 ldw r2,92(sp) - 5918: 1000021e bne r2,zero,5924 <_dtoa_r+0x9b8> - 591c: e004c03a cmpne r2,fp,zero - 5920: 10011726 beq r2,zero,5d80 <_dtoa_r+0xe14> - 5924: a0010616 blt r20,zero,5d40 <_dtoa_r+0xdd4> - 5928: a000041e bne r20,zero,593c <_dtoa_r+0x9d0> - 592c: d8c01717 ldw r3,92(sp) - 5930: 1800021e bne r3,zero,593c <_dtoa_r+0x9d0> - 5934: e004c03a cmpne r2,fp,zero - 5938: 10010126 beq r2,zero,5d40 <_dtoa_r+0xdd4> - 593c: 04023d16 blt zero,r16,6234 <_dtoa_r+0x12c8> - 5940: b5c00005 stb r23,0(r22) - 5944: d9800517 ldw r6,20(sp) - 5948: d9000f17 ldw r4,60(sp) - 594c: b5800044 addi r22,r22,1 - 5950: 3105883a add r2,r6,r4 - 5954: b0806526 beq r22,r2,5aec <_dtoa_r+0xb80> - 5958: d9400717 ldw r5,28(sp) - 595c: d9001617 ldw r4,88(sp) - 5960: 01800284 movi r6,10 - 5964: 000f883a mov r7,zero - 5968: 0008e540 call 8e54 <__multadd> - 596c: d8800715 stw r2,28(sp) - 5970: d8800617 ldw r2,24(sp) - 5974: 14c10c26 beq r2,r19,5da8 <_dtoa_r+0xe3c> - 5978: d9400617 ldw r5,24(sp) - 597c: d9001617 ldw r4,88(sp) - 5980: 01800284 movi r6,10 - 5984: 000f883a mov r7,zero - 5988: 0008e540 call 8e54 <__multadd> - 598c: d9001617 ldw r4,88(sp) - 5990: 980b883a mov r5,r19 - 5994: 01800284 movi r6,10 - 5998: 000f883a mov r7,zero - 599c: d8800615 stw r2,24(sp) - 59a0: 0008e540 call 8e54 <__multadd> - 59a4: 1027883a mov r19,r2 - 59a8: 003fc206 br 58b4 <_dtoa_r+0x948> - 59ac: 2445c83a sub r2,r4,r17 - 59b0: a088983a sll r4,r20,r2 - 59b4: 003e4b06 br 52e4 <_dtoa_r+0x378> - 59b8: 01bfffc4 movi r6,-1 - 59bc: 00800044 movi r2,1 - 59c0: d9800e15 stw r6,56(sp) - 59c4: d9800f15 stw r6,60(sp) - 59c8: d8800b15 stw r2,44(sp) - 59cc: d8c01617 ldw r3,88(sp) - 59d0: 008005c4 movi r2,23 - 59d4: 18001115 stw zero,68(r3) - 59d8: 1580082e bgeu r2,r22,59fc <_dtoa_r+0xa90> - 59dc: 00c00104 movi r3,4 - 59e0: 0009883a mov r4,zero - 59e4: 18c7883a add r3,r3,r3 - 59e8: 18800504 addi r2,r3,20 - 59ec: 21000044 addi r4,r4,1 - 59f0: b0bffc2e bgeu r22,r2,59e4 <_dtoa_r+0xa78> - 59f4: d9801617 ldw r6,88(sp) - 59f8: 31001115 stw r4,68(r6) - 59fc: dc000f17 ldw r16,60(sp) - 5a00: 003e4b06 br 5330 <_dtoa_r+0x3c4> - 5a04: d9801717 ldw r6,92(sp) - 5a08: 0023883a mov r17,zero - 5a0c: 31bfff04 addi r6,r6,-4 - 5a10: d9801715 stw r6,92(sp) - 5a14: 003df806 br 51f8 <_dtoa_r+0x28c> - 5a18: 00800804 movi r2,32 - 5a1c: 10c9c83a sub r4,r2,r3 - 5a20: 00c00104 movi r3,4 - 5a24: 19005a16 blt r3,r4,5b90 <_dtoa_r+0xc24> - 5a28: 008000c4 movi r2,3 - 5a2c: 113f7e16 blt r2,r4,5828 <_dtoa_r+0x8bc> - 5a30: 20800704 addi r2,r4,28 - 5a34: 003f7506 br 580c <_dtoa_r+0x8a0> - 5a38: d9801717 ldw r6,92(sp) - 5a3c: 00800044 movi r2,1 - 5a40: 1180a10e bge r2,r6,5cc8 <_dtoa_r+0xd5c> - 5a44: d9800f17 ldw r6,60(sp) - 5a48: d8c01017 ldw r3,64(sp) - 5a4c: 30bfffc4 addi r2,r6,-1 - 5a50: 1881c616 blt r3,r2,616c <_dtoa_r+0x1200> - 5a54: 18a5c83a sub r18,r3,r2 - 5a58: d8800f17 ldw r2,60(sp) - 5a5c: 10026216 blt r2,zero,63e8 <_dtoa_r+0x147c> - 5a60: dc001117 ldw r16,68(sp) - 5a64: 1007883a mov r3,r2 - 5a68: d9800a17 ldw r6,40(sp) - 5a6c: d8801117 ldw r2,68(sp) - 5a70: d9001617 ldw r4,88(sp) - 5a74: 30cd883a add r6,r6,r3 - 5a78: 10c5883a add r2,r2,r3 - 5a7c: 01400044 movi r5,1 - 5a80: d9800a15 stw r6,40(sp) - 5a84: d8801115 stw r2,68(sp) - 5a88: 0008e180 call 8e18 <__i2b> - 5a8c: 1027883a mov r19,r2 - 5a90: 003f2506 br 5728 <_dtoa_r+0x7bc> - 5a94: 00c00074 movhi r3,1 - 5a98: 18c0b304 addi r3,r3,716 - 5a9c: 003d6706 br 503c <_dtoa_r+0xd0> - 5aa0: dd800517 ldw r22,20(sp) - 5aa4: 04000044 movi r16,1 - 5aa8: 00000706 br 5ac8 <_dtoa_r+0xb5c> - 5aac: d9400717 ldw r5,28(sp) - 5ab0: d9001617 ldw r4,88(sp) - 5ab4: 01800284 movi r6,10 - 5ab8: 000f883a mov r7,zero - 5abc: 0008e540 call 8e54 <__multadd> - 5ac0: d8800715 stw r2,28(sp) - 5ac4: 84000044 addi r16,r16,1 - 5ac8: d9000717 ldw r4,28(sp) - 5acc: 900b883a mov r5,r18 - 5ad0: 0004d280 call 4d28 - 5ad4: 15c00c04 addi r23,r2,48 - 5ad8: b5c00005 stb r23,0(r22) - 5adc: d8c00f17 ldw r3,60(sp) - 5ae0: b5800044 addi r22,r22,1 - 5ae4: 80fff116 blt r16,r3,5aac <_dtoa_r+0xb40> - 5ae8: d8000615 stw zero,24(sp) - 5aec: d9400717 ldw r5,28(sp) - 5af0: d9001617 ldw r4,88(sp) - 5af4: 01800044 movi r6,1 - 5af8: 0008a780 call 8a78 <__lshift> - 5afc: 1009883a mov r4,r2 - 5b00: 900b883a mov r5,r18 - 5b04: d8800715 stw r2,28(sp) - 5b08: 00082900 call 8290 <__mcmp> - 5b0c: 00803c0e bge zero,r2,5c00 <_dtoa_r+0xc94> - 5b10: b009883a mov r4,r22 - 5b14: 213fffc4 addi r4,r4,-1 - 5b18: 21400003 ldbu r5,0(r4) - 5b1c: 00800e44 movi r2,57 - 5b20: 28c03fcc andi r3,r5,255 - 5b24: 18c0201c xori r3,r3,128 - 5b28: 18ffe004 addi r3,r3,-128 - 5b2c: 1881981e bne r3,r2,6190 <_dtoa_r+0x1224> - 5b30: d9800517 ldw r6,20(sp) - 5b34: 21bff71e bne r4,r6,5b14 <_dtoa_r+0xba8> - 5b38: d8800d17 ldw r2,52(sp) - 5b3c: 37000044 addi fp,r6,1 - 5b40: 10800044 addi r2,r2,1 - 5b44: d8800d15 stw r2,52(sp) - 5b48: 00800c44 movi r2,49 - 5b4c: 30800005 stb r2,0(r6) - 5b50: d9001617 ldw r4,88(sp) - 5b54: 900b883a mov r5,r18 - 5b58: 00081340 call 8134 <_Bfree> - 5b5c: 983ecd26 beq r19,zero,5694 <_dtoa_r+0x728> - 5b60: d8c00617 ldw r3,24(sp) - 5b64: 18000426 beq r3,zero,5b78 <_dtoa_r+0xc0c> - 5b68: 1cc00326 beq r3,r19,5b78 <_dtoa_r+0xc0c> - 5b6c: d9001617 ldw r4,88(sp) - 5b70: 180b883a mov r5,r3 - 5b74: 00081340 call 8134 <_Bfree> - 5b78: d9001617 ldw r4,88(sp) - 5b7c: 980b883a mov r5,r19 - 5b80: 00081340 call 8134 <_Bfree> - 5b84: 003ec306 br 5694 <_dtoa_r+0x728> - 5b88: 1805883a mov r2,r3 - 5b8c: 003eeb06 br 573c <_dtoa_r+0x7d0> - 5b90: d9800a17 ldw r6,40(sp) - 5b94: d8c01117 ldw r3,68(sp) - 5b98: 20bfff04 addi r2,r4,-4 - 5b9c: 308d883a add r6,r6,r2 - 5ba0: 1887883a add r3,r3,r2 - 5ba4: 80a1883a add r16,r16,r2 - 5ba8: d9800a15 stw r6,40(sp) - 5bac: d8c01115 stw r3,68(sp) - 5bb0: 003f1d06 br 5828 <_dtoa_r+0x8bc> - 5bb4: a03f0c1e bne r20,zero,57e8 <_dtoa_r+0x87c> - 5bb8: 00800434 movhi r2,16 - 5bbc: 10bfffc4 addi r2,r2,-1 - 5bc0: a884703a and r2,r21,r2 - 5bc4: 103f081e bne r2,zero,57e8 <_dtoa_r+0x87c> - 5bc8: a89ffc2c andhi r2,r21,32752 - 5bcc: 103f0626 beq r2,zero,57e8 <_dtoa_r+0x87c> - 5bd0: d8c01117 ldw r3,68(sp) - 5bd4: d9000a17 ldw r4,40(sp) - 5bd8: 18c00044 addi r3,r3,1 - 5bdc: 21000044 addi r4,r4,1 - 5be0: d8c01115 stw r3,68(sp) - 5be4: d9000a15 stw r4,40(sp) - 5be8: 003f0006 br 57ec <_dtoa_r+0x880> - 5bec: d9400717 ldw r5,28(sp) - 5bf0: d9001617 ldw r4,88(sp) - 5bf4: 0008f800 call 8f80 <__pow5mult> - 5bf8: d8800715 stw r2,28(sp) - 5bfc: 003eed06 br 57b4 <_dtoa_r+0x848> - 5c00: 1000021e bne r2,zero,5c0c <_dtoa_r+0xca0> - 5c04: b880004c andi r2,r23,1 - 5c08: 103fc11e bne r2,zero,5b10 <_dtoa_r+0xba4> - 5c0c: b5bfffc4 addi r22,r22,-1 - 5c10: b0c00007 ldb r3,0(r22) - 5c14: 00800c04 movi r2,48 - 5c18: 18bffc26 beq r3,r2,5c0c <_dtoa_r+0xca0> - 5c1c: b7000044 addi fp,r22,1 - 5c20: 003fcb06 br 5b50 <_dtoa_r+0xbe4> - 5c24: d9800d17 ldw r6,52(sp) - 5c28: 018fc83a sub r7,zero,r6 - 5c2c: 3801f726 beq r7,zero,640c <_dtoa_r+0x14a0> - 5c30: 398003cc andi r6,r7,15 - 5c34: 300c90fa slli r6,r6,3 - 5c38: 01400074 movhi r5,1 - 5c3c: 2940d104 addi r5,r5,836 - 5c40: d9001217 ldw r4,72(sp) - 5c44: 314d883a add r6,r6,r5 - 5c48: 30c00117 ldw r3,4(r6) - 5c4c: 30800017 ldw r2,0(r6) - 5c50: d9401317 ldw r5,76(sp) - 5c54: 3821d13a srai r16,r7,4 - 5c58: 100d883a mov r6,r2 - 5c5c: 180f883a mov r7,r3 - 5c60: 000b1140 call b114 <__muldf3> - 5c64: 1011883a mov r8,r2 - 5c68: 1813883a mov r9,r3 - 5c6c: 1029883a mov r20,r2 - 5c70: 182b883a mov r21,r3 - 5c74: 8001e526 beq r16,zero,640c <_dtoa_r+0x14a0> - 5c78: 05800084 movi r22,2 - 5c7c: 04400074 movhi r17,1 - 5c80: 8c410304 addi r17,r17,1036 - 5c84: 8080004c andi r2,r16,1 - 5c88: 1005003a cmpeq r2,r2,zero - 5c8c: 1000081e bne r2,zero,5cb0 <_dtoa_r+0xd44> - 5c90: 89800017 ldw r6,0(r17) - 5c94: 89c00117 ldw r7,4(r17) - 5c98: 480b883a mov r5,r9 - 5c9c: 4009883a mov r4,r8 - 5ca0: 000b1140 call b114 <__muldf3> - 5ca4: 1011883a mov r8,r2 - 5ca8: b5800044 addi r22,r22,1 - 5cac: 1813883a mov r9,r3 - 5cb0: 8021d07a srai r16,r16,1 - 5cb4: 8c400204 addi r17,r17,8 - 5cb8: 803ff21e bne r16,zero,5c84 <_dtoa_r+0xd18> - 5cbc: 4029883a mov r20,r8 - 5cc0: 482b883a mov r21,r9 - 5cc4: 003dca06 br 53f0 <_dtoa_r+0x484> - 5cc8: d9000817 ldw r4,32(sp) - 5ccc: 2005003a cmpeq r2,r4,zero - 5cd0: 1001f61e bne r2,zero,64ac <_dtoa_r+0x1540> - 5cd4: dc001117 ldw r16,68(sp) - 5cd8: dc801017 ldw r18,64(sp) - 5cdc: 18c10cc4 addi r3,r3,1075 - 5ce0: 003f6106 br 5a68 <_dtoa_r+0xafc> - 5ce4: d8000b15 stw zero,44(sp) - 5ce8: d9802617 ldw r6,152(sp) - 5cec: d8c00d17 ldw r3,52(sp) - 5cf0: 30800044 addi r2,r6,1 - 5cf4: 18ad883a add r22,r3,r2 - 5cf8: b13fffc4 addi r4,r22,-1 - 5cfc: d9000e15 stw r4,56(sp) - 5d00: 0581f60e bge zero,r22,64dc <_dtoa_r+0x1570> - 5d04: dd800f15 stw r22,60(sp) - 5d08: 003f3006 br 59cc <_dtoa_r+0xa60> - 5d0c: d8000b15 stw zero,44(sp) - 5d10: d9002617 ldw r4,152(sp) - 5d14: 0101eb0e bge zero,r4,64c4 <_dtoa_r+0x1558> - 5d18: 202d883a mov r22,r4 - 5d1c: d9000e15 stw r4,56(sp) - 5d20: d9000f15 stw r4,60(sp) - 5d24: 003f2906 br 59cc <_dtoa_r+0xa60> - 5d28: 01800044 movi r6,1 - 5d2c: d9800b15 stw r6,44(sp) - 5d30: 003ff706 br 5d10 <_dtoa_r+0xda4> - 5d34: 01000044 movi r4,1 - 5d38: d9000b15 stw r4,44(sp) - 5d3c: 003fea06 br 5ce8 <_dtoa_r+0xd7c> - 5d40: 04000c0e bge zero,r16,5d74 <_dtoa_r+0xe08> - 5d44: d9400717 ldw r5,28(sp) - 5d48: d9001617 ldw r4,88(sp) - 5d4c: 01800044 movi r6,1 - 5d50: 0008a780 call 8a78 <__lshift> - 5d54: 1009883a mov r4,r2 - 5d58: 900b883a mov r5,r18 - 5d5c: d8800715 stw r2,28(sp) - 5d60: 00082900 call 8290 <__mcmp> - 5d64: 0081e00e bge zero,r2,64e8 <_dtoa_r+0x157c> - 5d68: bdc00044 addi r23,r23,1 - 5d6c: 00800e84 movi r2,58 - 5d70: b881a226 beq r23,r2,63fc <_dtoa_r+0x1490> - 5d74: b7000044 addi fp,r22,1 - 5d78: b5c00005 stb r23,0(r22) - 5d7c: 003f7406 br 5b50 <_dtoa_r+0xbe4> - 5d80: 00800e44 movi r2,57 - 5d84: b8819d26 beq r23,r2,63fc <_dtoa_r+0x1490> - 5d88: 053ffa0e bge zero,r20,5d74 <_dtoa_r+0xe08> - 5d8c: 8dc00c44 addi r23,r17,49 - 5d90: 003ff806 br 5d74 <_dtoa_r+0xe08> - 5d94: d9001617 ldw r4,88(sp) - 5d98: a80b883a mov r5,r21 - 5d9c: 04000044 movi r16,1 - 5da0: 00081340 call 8134 <_Bfree> - 5da4: 003edf06 br 5924 <_dtoa_r+0x9b8> - 5da8: d9001617 ldw r4,88(sp) - 5dac: 980b883a mov r5,r19 - 5db0: 01800284 movi r6,10 - 5db4: 000f883a mov r7,zero - 5db8: 0008e540 call 8e54 <__multadd> - 5dbc: 1027883a mov r19,r2 - 5dc0: d8800615 stw r2,24(sp) - 5dc4: 003ebb06 br 58b4 <_dtoa_r+0x948> - 5dc8: d9801117 ldw r6,68(sp) - 5dcc: d8800d17 ldw r2,52(sp) - 5dd0: d8000915 stw zero,36(sp) - 5dd4: 308dc83a sub r6,r6,r2 - 5dd8: 0087c83a sub r3,zero,r2 - 5ddc: d9801115 stw r6,68(sp) - 5de0: d8c01015 stw r3,64(sp) - 5de4: 003cfe06 br 51e0 <_dtoa_r+0x274> - 5de8: 018dc83a sub r6,zero,r6 - 5dec: d9801115 stw r6,68(sp) - 5df0: d8000a15 stw zero,40(sp) - 5df4: 003cf306 br 51c4 <_dtoa_r+0x258> - 5df8: d9000d17 ldw r4,52(sp) - 5dfc: 000b9d80 call b9d8 <__floatsidf> - 5e00: 880b883a mov r5,r17 - 5e04: 8009883a mov r4,r16 - 5e08: 180f883a mov r7,r3 - 5e0c: 100d883a mov r6,r2 - 5e10: 000b7b80 call b7b8 <__nedf2> - 5e14: 103ce126 beq r2,zero,519c <_dtoa_r+0x230> - 5e18: d9800d17 ldw r6,52(sp) - 5e1c: 31bfffc4 addi r6,r6,-1 - 5e20: d9800d15 stw r6,52(sp) - 5e24: 003cdd06 br 519c <_dtoa_r+0x230> - 5e28: d9000717 ldw r4,28(sp) - 5e2c: 900b883a mov r5,r18 - 5e30: 00082900 call 8290 <__mcmp> - 5e34: 103e8d0e bge r2,zero,586c <_dtoa_r+0x900> - 5e38: d9400717 ldw r5,28(sp) - 5e3c: d9001617 ldw r4,88(sp) - 5e40: 01800284 movi r6,10 - 5e44: 000f883a mov r7,zero - 5e48: 0008e540 call 8e54 <__multadd> - 5e4c: d9800d17 ldw r6,52(sp) - 5e50: d8800715 stw r2,28(sp) - 5e54: 31bfffc4 addi r6,r6,-1 - 5e58: d9800d15 stw r6,52(sp) - 5e5c: b001a71e bne r22,zero,64fc <_dtoa_r+0x1590> - 5e60: d8800e17 ldw r2,56(sp) - 5e64: d8800f15 stw r2,60(sp) - 5e68: 003e8006 br 586c <_dtoa_r+0x900> - 5e6c: 90800417 ldw r2,16(r18) - 5e70: 1085883a add r2,r2,r2 - 5e74: 1085883a add r2,r2,r2 - 5e78: 1485883a add r2,r2,r18 - 5e7c: 11000417 ldw r4,16(r2) - 5e80: 000815c0 call 815c <__hi0bits> - 5e84: 00c00804 movi r3,32 - 5e88: 1887c83a sub r3,r3,r2 - 5e8c: 003e5a06 br 57f8 <_dtoa_r+0x88c> - 5e90: d9400717 ldw r5,28(sp) - 5e94: d9801017 ldw r6,64(sp) - 5e98: d9001617 ldw r4,88(sp) - 5e9c: 0008f800 call 8f80 <__pow5mult> - 5ea0: d8800715 stw r2,28(sp) - 5ea4: 003e4306 br 57b4 <_dtoa_r+0x848> - 5ea8: d9800f17 ldw r6,60(sp) - 5eac: d8800d17 ldw r2,52(sp) - 5eb0: d9800315 stw r6,12(sp) - 5eb4: d8800415 stw r2,16(sp) - 5eb8: d8c00b17 ldw r3,44(sp) - 5ebc: 1805003a cmpeq r2,r3,zero - 5ec0: 1000e21e bne r2,zero,624c <_dtoa_r+0x12e0> - 5ec4: d9000317 ldw r4,12(sp) - 5ec8: 0005883a mov r2,zero - 5ecc: 00cff834 movhi r3,16352 - 5ed0: 200c90fa slli r6,r4,3 - 5ed4: 01000074 movhi r4,1 - 5ed8: 2100d104 addi r4,r4,836 - 5edc: 180b883a mov r5,r3 - 5ee0: 310d883a add r6,r6,r4 - 5ee4: 327fff17 ldw r9,-4(r6) - 5ee8: 323ffe17 ldw r8,-8(r6) - 5eec: 1009883a mov r4,r2 - 5ef0: 480f883a mov r7,r9 - 5ef4: 400d883a mov r6,r8 - 5ef8: 000b4d80 call b4d8 <__divdf3> - 5efc: 180b883a mov r5,r3 - 5f00: b00d883a mov r6,r22 - 5f04: b80f883a mov r7,r23 - 5f08: 1009883a mov r4,r2 - 5f0c: 000b0200 call b020 <__subdf3> - 5f10: a80b883a mov r5,r21 - 5f14: a009883a mov r4,r20 - 5f18: d8c01915 stw r3,100(sp) - 5f1c: d8801815 stw r2,96(sp) - 5f20: 000bad00 call bad0 <__fixdfsi> - 5f24: 1009883a mov r4,r2 - 5f28: 1027883a mov r19,r2 - 5f2c: 000b9d80 call b9d8 <__floatsidf> - 5f30: a80b883a mov r5,r21 - 5f34: a009883a mov r4,r20 - 5f38: 180f883a mov r7,r3 - 5f3c: 100d883a mov r6,r2 - 5f40: 000b0200 call b020 <__subdf3> - 5f44: d9801817 ldw r6,96(sp) - 5f48: 1823883a mov r17,r3 - 5f4c: d8801415 stw r2,80(sp) - 5f50: 302d883a mov r22,r6 - 5f54: d9800517 ldw r6,20(sp) - 5f58: 9cc00c04 addi r19,r19,48 - 5f5c: dc401515 stw r17,84(sp) - 5f60: d8c01917 ldw r3,100(sp) - 5f64: 34c00005 stb r19,0(r6) - 5f68: d8800517 ldw r2,20(sp) - 5f6c: d9401917 ldw r5,100(sp) - 5f70: d9801417 ldw r6,80(sp) - 5f74: b009883a mov r4,r22 - 5f78: 880f883a mov r7,r17 - 5f7c: 182f883a mov r23,r3 - 5f80: 17000044 addi fp,r2,1 - 5f84: 000b8400 call b840 <__gtdf2> - 5f88: 00804e16 blt zero,r2,60c4 <_dtoa_r+0x1158> - 5f8c: d9801417 ldw r6,80(sp) - 5f90: 0005883a mov r2,zero - 5f94: 00cffc34 movhi r3,16368 - 5f98: 180b883a mov r5,r3 - 5f9c: 880f883a mov r7,r17 - 5fa0: 1009883a mov r4,r2 - 5fa4: 000b0200 call b020 <__subdf3> - 5fa8: d9401917 ldw r5,100(sp) - 5fac: 180f883a mov r7,r3 - 5fb0: b009883a mov r4,r22 - 5fb4: 100d883a mov r6,r2 - 5fb8: 000b8400 call b840 <__gtdf2> - 5fbc: 00bda216 blt zero,r2,5648 <_dtoa_r+0x6dc> - 5fc0: d8c00317 ldw r3,12(sp) - 5fc4: 00800044 movi r2,1 - 5fc8: 10c01216 blt r2,r3,6014 <_dtoa_r+0x10a8> - 5fcc: 003d4506 br 54e4 <_dtoa_r+0x578> - 5fd0: d9801417 ldw r6,80(sp) - 5fd4: 0005883a mov r2,zero - 5fd8: 00cffc34 movhi r3,16368 - 5fdc: 180b883a mov r5,r3 - 5fe0: 880f883a mov r7,r17 - 5fe4: 1009883a mov r4,r2 - 5fe8: 000b0200 call b020 <__subdf3> - 5fec: d9c01b17 ldw r7,108(sp) - 5ff0: 180b883a mov r5,r3 - 5ff4: 1009883a mov r4,r2 - 5ff8: b00d883a mov r6,r22 - 5ffc: 000b9500 call b950 <__ltdf2> - 6000: 103d9116 blt r2,zero,5648 <_dtoa_r+0x6dc> - 6004: d9800517 ldw r6,20(sp) - 6008: d9000317 ldw r4,12(sp) - 600c: 3105883a add r2,r6,r4 - 6010: e0bd3426 beq fp,r2,54e4 <_dtoa_r+0x578> - 6014: 04500934 movhi r17,16420 - 6018: 0021883a mov r16,zero - 601c: b80b883a mov r5,r23 - 6020: b009883a mov r4,r22 - 6024: 800d883a mov r6,r16 - 6028: 880f883a mov r7,r17 - 602c: 000b1140 call b114 <__muldf3> - 6030: d9401517 ldw r5,84(sp) - 6034: d9001417 ldw r4,80(sp) - 6038: 880f883a mov r7,r17 - 603c: 000d883a mov r6,zero - 6040: d8801a15 stw r2,104(sp) - 6044: d8c01b15 stw r3,108(sp) - 6048: 000b1140 call b114 <__muldf3> - 604c: 180b883a mov r5,r3 - 6050: 1009883a mov r4,r2 - 6054: 1823883a mov r17,r3 - 6058: 1021883a mov r16,r2 - 605c: 000bad00 call bad0 <__fixdfsi> - 6060: 1009883a mov r4,r2 - 6064: 102b883a mov r21,r2 - 6068: 000b9d80 call b9d8 <__floatsidf> - 606c: 880b883a mov r5,r17 - 6070: 8009883a mov r4,r16 - 6074: 180f883a mov r7,r3 - 6078: 100d883a mov r6,r2 - 607c: 000b0200 call b020 <__subdf3> - 6080: 1021883a mov r16,r2 - 6084: d9001b17 ldw r4,108(sp) - 6088: 1823883a mov r17,r3 - 608c: dc001415 stw r16,80(sp) - 6090: ad400c04 addi r21,r21,48 - 6094: dc401515 stw r17,84(sp) - 6098: d8801a17 ldw r2,104(sp) - 609c: e5400005 stb r21,0(fp) - 60a0: 202f883a mov r23,r4 - 60a4: d9c01b17 ldw r7,108(sp) - 60a8: d9001417 ldw r4,80(sp) - 60ac: 880b883a mov r5,r17 - 60b0: 100d883a mov r6,r2 - 60b4: 102d883a mov r22,r2 - 60b8: e7000044 addi fp,fp,1 - 60bc: 000b9500 call b950 <__ltdf2> - 60c0: 103fc30e bge r2,zero,5fd0 <_dtoa_r+0x1064> - 60c4: d9000417 ldw r4,16(sp) - 60c8: d9000d15 stw r4,52(sp) - 60cc: 003d7106 br 5694 <_dtoa_r+0x728> - 60d0: d9801717 ldw r6,92(sp) - 60d4: 00800084 movi r2,2 - 60d8: 11bde60e bge r2,r6,5874 <_dtoa_r+0x908> - 60dc: 203cfb1e bne r4,zero,54cc <_dtoa_r+0x560> - 60e0: d9001617 ldw r4,88(sp) - 60e4: 900b883a mov r5,r18 - 60e8: 01800144 movi r6,5 - 60ec: 000f883a mov r7,zero - 60f0: 0008e540 call 8e54 <__multadd> - 60f4: d9000717 ldw r4,28(sp) - 60f8: 100b883a mov r5,r2 - 60fc: 1025883a mov r18,r2 - 6100: 00082900 call 8290 <__mcmp> - 6104: 00bcf10e bge zero,r2,54cc <_dtoa_r+0x560> - 6108: d8c00d17 ldw r3,52(sp) - 610c: d9000517 ldw r4,20(sp) - 6110: d8000615 stw zero,24(sp) - 6114: 18c00044 addi r3,r3,1 - 6118: d8c00d15 stw r3,52(sp) - 611c: 00800c44 movi r2,49 - 6120: 27000044 addi fp,r4,1 - 6124: 20800005 stb r2,0(r4) - 6128: 003e8906 br 5b50 <_dtoa_r+0xbe4> - 612c: d8c00517 ldw r3,20(sp) - 6130: 003bc206 br 503c <_dtoa_r+0xd0> - 6134: 01800074 movhi r6,1 - 6138: 31810304 addi r6,r6,1036 - 613c: 30c00917 ldw r3,36(r6) - 6140: 30800817 ldw r2,32(r6) - 6144: d9001217 ldw r4,72(sp) - 6148: d9401317 ldw r5,76(sp) - 614c: 180f883a mov r7,r3 - 6150: 100d883a mov r6,r2 - 6154: 000b4d80 call b4d8 <__divdf3> - 6158: 948003cc andi r18,r18,15 - 615c: 058000c4 movi r22,3 - 6160: 1029883a mov r20,r2 - 6164: 182b883a mov r21,r3 - 6168: 003c8906 br 5390 <_dtoa_r+0x424> - 616c: d9001017 ldw r4,64(sp) - 6170: d9800917 ldw r6,36(sp) - 6174: 0025883a mov r18,zero - 6178: 1105c83a sub r2,r2,r4 - 617c: 2089883a add r4,r4,r2 - 6180: 308d883a add r6,r6,r2 - 6184: d9001015 stw r4,64(sp) - 6188: d9800915 stw r6,36(sp) - 618c: 003e3206 br 5a58 <_dtoa_r+0xaec> - 6190: 28800044 addi r2,r5,1 - 6194: 27000044 addi fp,r4,1 - 6198: 20800005 stb r2,0(r4) - 619c: 003e6c06 br 5b50 <_dtoa_r+0xbe4> - 61a0: d8800f17 ldw r2,60(sp) - 61a4: 00bce016 blt zero,r2,5528 <_dtoa_r+0x5bc> - 61a8: d9800f17 ldw r6,60(sp) - 61ac: 303cc51e bne r6,zero,54c4 <_dtoa_r+0x558> - 61b0: 0005883a mov r2,zero - 61b4: 00d00534 movhi r3,16404 - 61b8: 980b883a mov r5,r19 - 61bc: 180f883a mov r7,r3 - 61c0: 9009883a mov r4,r18 - 61c4: 100d883a mov r6,r2 - 61c8: 000b1140 call b114 <__muldf3> - 61cc: 180b883a mov r5,r3 - 61d0: a80f883a mov r7,r21 - 61d4: 1009883a mov r4,r2 - 61d8: a00d883a mov r6,r20 - 61dc: 000b8c80 call b8c8 <__gedf2> - 61e0: 103cb80e bge r2,zero,54c4 <_dtoa_r+0x558> - 61e4: 0027883a mov r19,zero - 61e8: 0025883a mov r18,zero - 61ec: 003fc606 br 6108 <_dtoa_r+0x119c> - 61f0: 99400117 ldw r5,4(r19) - 61f4: d9001617 ldw r4,88(sp) - 61f8: 00086b40 call 86b4 <_Balloc> - 61fc: 99800417 ldw r6,16(r19) - 6200: 11000304 addi r4,r2,12 - 6204: 99400304 addi r5,r19,12 - 6208: 318d883a add r6,r6,r6 - 620c: 318d883a add r6,r6,r6 - 6210: 31800204 addi r6,r6,8 - 6214: 1023883a mov r17,r2 - 6218: 0007f1c0 call 7f1c - 621c: d9001617 ldw r4,88(sp) - 6220: 880b883a mov r5,r17 - 6224: 01800044 movi r6,1 - 6228: 0008a780 call 8a78 <__lshift> - 622c: 100b883a mov r5,r2 - 6230: 003d9c06 br 58a4 <_dtoa_r+0x938> - 6234: 00800e44 movi r2,57 - 6238: b8807026 beq r23,r2,63fc <_dtoa_r+0x1490> - 623c: b8800044 addi r2,r23,1 - 6240: b7000044 addi fp,r22,1 - 6244: b0800005 stb r2,0(r22) - 6248: 003e4106 br 5b50 <_dtoa_r+0xbe4> - 624c: d8800317 ldw r2,12(sp) - 6250: 01800074 movhi r6,1 - 6254: 3180d104 addi r6,r6,836 - 6258: b009883a mov r4,r22 - 625c: 100e90fa slli r7,r2,3 - 6260: b80b883a mov r5,r23 - 6264: 398f883a add r7,r7,r6 - 6268: 38bffe17 ldw r2,-8(r7) - 626c: d9800517 ldw r6,20(sp) - 6270: 38ffff17 ldw r3,-4(r7) - 6274: 37000044 addi fp,r6,1 - 6278: 180f883a mov r7,r3 - 627c: 100d883a mov r6,r2 - 6280: 000b1140 call b114 <__muldf3> - 6284: a80b883a mov r5,r21 - 6288: a009883a mov r4,r20 - 628c: 182f883a mov r23,r3 - 6290: 102d883a mov r22,r2 - 6294: 000bad00 call bad0 <__fixdfsi> - 6298: 1009883a mov r4,r2 - 629c: 1027883a mov r19,r2 - 62a0: 000b9d80 call b9d8 <__floatsidf> - 62a4: a80b883a mov r5,r21 - 62a8: a009883a mov r4,r20 - 62ac: 180f883a mov r7,r3 - 62b0: 100d883a mov r6,r2 - 62b4: 000b0200 call b020 <__subdf3> - 62b8: 180b883a mov r5,r3 - 62bc: d8c00517 ldw r3,20(sp) - 62c0: 9cc00c04 addi r19,r19,48 - 62c4: 1009883a mov r4,r2 - 62c8: 1cc00005 stb r19,0(r3) - 62cc: 2021883a mov r16,r4 - 62d0: d9000317 ldw r4,12(sp) - 62d4: 00800044 movi r2,1 - 62d8: 2823883a mov r17,r5 - 62dc: 20802226 beq r4,r2,6368 <_dtoa_r+0x13fc> - 62e0: 1029883a mov r20,r2 - 62e4: 0005883a mov r2,zero - 62e8: 00d00934 movhi r3,16420 - 62ec: 180f883a mov r7,r3 - 62f0: 100d883a mov r6,r2 - 62f4: 880b883a mov r5,r17 - 62f8: 8009883a mov r4,r16 - 62fc: 000b1140 call b114 <__muldf3> - 6300: 180b883a mov r5,r3 - 6304: 1009883a mov r4,r2 - 6308: 1823883a mov r17,r3 - 630c: 1021883a mov r16,r2 - 6310: 000bad00 call bad0 <__fixdfsi> - 6314: 1009883a mov r4,r2 - 6318: 102b883a mov r21,r2 - 631c: 000b9d80 call b9d8 <__floatsidf> - 6320: 880b883a mov r5,r17 - 6324: 8009883a mov r4,r16 - 6328: 180f883a mov r7,r3 - 632c: 100d883a mov r6,r2 - 6330: 000b0200 call b020 <__subdf3> - 6334: 180b883a mov r5,r3 - 6338: d8c00517 ldw r3,20(sp) - 633c: 1009883a mov r4,r2 - 6340: ad400c04 addi r21,r21,48 - 6344: 1d05883a add r2,r3,r20 - 6348: 15400005 stb r21,0(r2) - 634c: 2021883a mov r16,r4 - 6350: d9000317 ldw r4,12(sp) - 6354: a5000044 addi r20,r20,1 - 6358: 2823883a mov r17,r5 - 635c: a13fe11e bne r20,r4,62e4 <_dtoa_r+0x1378> - 6360: e505883a add r2,fp,r20 - 6364: 173fffc4 addi fp,r2,-1 - 6368: 0025883a mov r18,zero - 636c: 04cff834 movhi r19,16352 - 6370: b009883a mov r4,r22 - 6374: b80b883a mov r5,r23 - 6378: 900d883a mov r6,r18 - 637c: 980f883a mov r7,r19 - 6380: 000b0a00 call b0a0 <__adddf3> - 6384: 180b883a mov r5,r3 - 6388: 1009883a mov r4,r2 - 638c: 800d883a mov r6,r16 - 6390: 880f883a mov r7,r17 - 6394: 000b9500 call b950 <__ltdf2> - 6398: 103cab16 blt r2,zero,5648 <_dtoa_r+0x6dc> - 639c: 0009883a mov r4,zero - 63a0: 980b883a mov r5,r19 - 63a4: b80f883a mov r7,r23 - 63a8: b00d883a mov r6,r22 - 63ac: 000b0200 call b020 <__subdf3> - 63b0: 180b883a mov r5,r3 - 63b4: 880f883a mov r7,r17 - 63b8: 1009883a mov r4,r2 - 63bc: 800d883a mov r6,r16 - 63c0: 000b8400 call b840 <__gtdf2> - 63c4: 00bc470e bge zero,r2,54e4 <_dtoa_r+0x578> - 63c8: 00c00c04 movi r3,48 - 63cc: e73fffc4 addi fp,fp,-1 - 63d0: e0800007 ldb r2,0(fp) - 63d4: 10fffd26 beq r2,r3,63cc <_dtoa_r+0x1460> - 63d8: d9800417 ldw r6,16(sp) - 63dc: e7000044 addi fp,fp,1 - 63e0: d9800d15 stw r6,52(sp) - 63e4: 003cab06 br 5694 <_dtoa_r+0x728> - 63e8: d8c00f17 ldw r3,60(sp) - 63ec: d9001117 ldw r4,68(sp) - 63f0: 20e1c83a sub r16,r4,r3 - 63f4: 0007883a mov r3,zero - 63f8: 003d9b06 br 5a68 <_dtoa_r+0xafc> - 63fc: 00800e44 movi r2,57 - 6400: b0800005 stb r2,0(r22) - 6404: b5800044 addi r22,r22,1 - 6408: 003dc106 br 5b10 <_dtoa_r+0xba4> - 640c: 05800084 movi r22,2 - 6410: 003bf706 br 53f0 <_dtoa_r+0x484> - 6414: d9000f17 ldw r4,60(sp) - 6418: 013c000e bge zero,r4,541c <_dtoa_r+0x4b0> - 641c: d9800e17 ldw r6,56(sp) - 6420: 01bc300e bge zero,r6,54e4 <_dtoa_r+0x578> - 6424: 0005883a mov r2,zero - 6428: 00d00934 movhi r3,16420 - 642c: a80b883a mov r5,r21 - 6430: 180f883a mov r7,r3 - 6434: a009883a mov r4,r20 - 6438: 100d883a mov r6,r2 - 643c: 000b1140 call b114 <__muldf3> - 6440: b1000044 addi r4,r22,1 - 6444: 1021883a mov r16,r2 - 6448: 1823883a mov r17,r3 - 644c: 000b9d80 call b9d8 <__floatsidf> - 6450: 880b883a mov r5,r17 - 6454: 8009883a mov r4,r16 - 6458: 180f883a mov r7,r3 - 645c: 100d883a mov r6,r2 - 6460: 000b1140 call b114 <__muldf3> - 6464: 0011883a mov r8,zero - 6468: 02500734 movhi r9,16412 - 646c: 180b883a mov r5,r3 - 6470: 480f883a mov r7,r9 - 6474: 1009883a mov r4,r2 - 6478: 400d883a mov r6,r8 - 647c: 000b0a00 call b0a0 <__adddf3> - 6480: 102d883a mov r22,r2 - 6484: 00bf3034 movhi r2,64704 - 6488: 10ef883a add r23,r2,r3 - 648c: d8800d17 ldw r2,52(sp) - 6490: d8c00e17 ldw r3,56(sp) - 6494: 8029883a mov r20,r16 - 6498: 10bfffc4 addi r2,r2,-1 - 649c: 882b883a mov r21,r17 - 64a0: d8800415 stw r2,16(sp) - 64a4: d8c00315 stw r3,12(sp) - 64a8: 003e8306 br 5eb8 <_dtoa_r+0xf4c> - 64ac: d8800117 ldw r2,4(sp) - 64b0: dc001117 ldw r16,68(sp) - 64b4: dc801017 ldw r18,64(sp) - 64b8: 00c00d84 movi r3,54 - 64bc: 1887c83a sub r3,r3,r2 - 64c0: 003d6906 br 5a68 <_dtoa_r+0xafc> - 64c4: 01800044 movi r6,1 - 64c8: 3021883a mov r16,r6 - 64cc: d9800f15 stw r6,60(sp) - 64d0: d9802615 stw r6,152(sp) - 64d4: d9800e15 stw r6,56(sp) - 64d8: 003b9306 br 5328 <_dtoa_r+0x3bc> - 64dc: b021883a mov r16,r22 - 64e0: dd800f15 stw r22,60(sp) - 64e4: 003b9006 br 5328 <_dtoa_r+0x3bc> - 64e8: 103e221e bne r2,zero,5d74 <_dtoa_r+0xe08> - 64ec: b880004c andi r2,r23,1 - 64f0: 1005003a cmpeq r2,r2,zero - 64f4: 103e1f1e bne r2,zero,5d74 <_dtoa_r+0xe08> - 64f8: 003e1b06 br 5d68 <_dtoa_r+0xdfc> - 64fc: d9001617 ldw r4,88(sp) - 6500: 980b883a mov r5,r19 - 6504: 01800284 movi r6,10 - 6508: 000f883a mov r7,zero - 650c: 0008e540 call 8e54 <__multadd> - 6510: d8c00e17 ldw r3,56(sp) - 6514: 1027883a mov r19,r2 - 6518: d8c00f15 stw r3,60(sp) - 651c: 003cd306 br 586c <_dtoa_r+0x900> - -00006520 <_fflush_r>: - 6520: defffb04 addi sp,sp,-20 - 6524: dcc00315 stw r19,12(sp) - 6528: dc800215 stw r18,8(sp) - 652c: dfc00415 stw ra,16(sp) - 6530: dc400115 stw r17,4(sp) - 6534: dc000015 stw r16,0(sp) - 6538: 2027883a mov r19,r4 - 653c: 2825883a mov r18,r5 - 6540: 20000226 beq r4,zero,654c <_fflush_r+0x2c> - 6544: 20800e17 ldw r2,56(r4) - 6548: 10005626 beq r2,zero,66a4 <_fflush_r+0x184> - 654c: 9100030b ldhu r4,12(r18) - 6550: 20ffffcc andi r3,r4,65535 - 6554: 18e0001c xori r3,r3,32768 - 6558: 18e00004 addi r3,r3,-32768 - 655c: 1880020c andi r2,r3,8 - 6560: 1000261e bne r2,zero,65fc <_fflush_r+0xdc> - 6564: 90c00117 ldw r3,4(r18) - 6568: 20820014 ori r2,r4,2048 - 656c: 9080030d sth r2,12(r18) - 6570: 1009883a mov r4,r2 - 6574: 00c0400e bge zero,r3,6678 <_fflush_r+0x158> - 6578: 92000a17 ldw r8,40(r18) - 657c: 40004026 beq r8,zero,6680 <_fflush_r+0x160> - 6580: 2084000c andi r2,r4,4096 - 6584: 10005326 beq r2,zero,66d4 <_fflush_r+0x1b4> - 6588: 94001417 ldw r16,80(r18) - 658c: 9080030b ldhu r2,12(r18) - 6590: 1080010c andi r2,r2,4 - 6594: 1000481e bne r2,zero,66b8 <_fflush_r+0x198> - 6598: 91400717 ldw r5,28(r18) - 659c: 9809883a mov r4,r19 - 65a0: 800d883a mov r6,r16 - 65a4: 000f883a mov r7,zero - 65a8: 403ee83a callr r8 - 65ac: 8080261e bne r16,r2,6648 <_fflush_r+0x128> - 65b0: 9080030b ldhu r2,12(r18) - 65b4: 91000417 ldw r4,16(r18) - 65b8: 90000115 stw zero,4(r18) - 65bc: 10bdffcc andi r2,r2,63487 - 65c0: 10ffffcc andi r3,r2,65535 - 65c4: 18c4000c andi r3,r3,4096 - 65c8: 9080030d sth r2,12(r18) - 65cc: 91000015 stw r4,0(r18) - 65d0: 18002b26 beq r3,zero,6680 <_fflush_r+0x160> - 65d4: 0007883a mov r3,zero - 65d8: 1805883a mov r2,r3 - 65dc: 94001415 stw r16,80(r18) - 65e0: dfc00417 ldw ra,16(sp) - 65e4: dcc00317 ldw r19,12(sp) - 65e8: dc800217 ldw r18,8(sp) - 65ec: dc400117 ldw r17,4(sp) - 65f0: dc000017 ldw r16,0(sp) - 65f4: dec00504 addi sp,sp,20 - 65f8: f800283a ret - 65fc: 94400417 ldw r17,16(r18) - 6600: 88001f26 beq r17,zero,6680 <_fflush_r+0x160> - 6604: 90800017 ldw r2,0(r18) - 6608: 18c000cc andi r3,r3,3 - 660c: 94400015 stw r17,0(r18) - 6610: 1461c83a sub r16,r2,r17 - 6614: 18002526 beq r3,zero,66ac <_fflush_r+0x18c> - 6618: 0005883a mov r2,zero - 661c: 90800215 stw r2,8(r18) - 6620: 0400170e bge zero,r16,6680 <_fflush_r+0x160> - 6624: 90c00917 ldw r3,36(r18) - 6628: 91400717 ldw r5,28(r18) - 662c: 880d883a mov r6,r17 - 6630: 800f883a mov r7,r16 - 6634: 9809883a mov r4,r19 - 6638: 183ee83a callr r3 - 663c: 88a3883a add r17,r17,r2 - 6640: 80a1c83a sub r16,r16,r2 - 6644: 00bff616 blt zero,r2,6620 <_fflush_r+0x100> - 6648: 9080030b ldhu r2,12(r18) - 664c: 00ffffc4 movi r3,-1 - 6650: 10801014 ori r2,r2,64 - 6654: 9080030d sth r2,12(r18) - 6658: 1805883a mov r2,r3 - 665c: dfc00417 ldw ra,16(sp) - 6660: dcc00317 ldw r19,12(sp) - 6664: dc800217 ldw r18,8(sp) - 6668: dc400117 ldw r17,4(sp) - 666c: dc000017 ldw r16,0(sp) - 6670: dec00504 addi sp,sp,20 - 6674: f800283a ret - 6678: 90800f17 ldw r2,60(r18) - 667c: 00bfbe16 blt zero,r2,6578 <_fflush_r+0x58> - 6680: 0007883a mov r3,zero - 6684: 1805883a mov r2,r3 - 6688: dfc00417 ldw ra,16(sp) - 668c: dcc00317 ldw r19,12(sp) - 6690: dc800217 ldw r18,8(sp) - 6694: dc400117 ldw r17,4(sp) - 6698: dc000017 ldw r16,0(sp) - 669c: dec00504 addi sp,sp,20 - 66a0: f800283a ret - 66a4: 00067b80 call 67b8 <__sinit> - 66a8: 003fa806 br 654c <_fflush_r+0x2c> - 66ac: 90800517 ldw r2,20(r18) - 66b0: 90800215 stw r2,8(r18) - 66b4: 003fda06 br 6620 <_fflush_r+0x100> - 66b8: 90800117 ldw r2,4(r18) - 66bc: 90c00c17 ldw r3,48(r18) - 66c0: 80a1c83a sub r16,r16,r2 - 66c4: 183fb426 beq r3,zero,6598 <_fflush_r+0x78> - 66c8: 90800f17 ldw r2,60(r18) - 66cc: 80a1c83a sub r16,r16,r2 - 66d0: 003fb106 br 6598 <_fflush_r+0x78> - 66d4: 91400717 ldw r5,28(r18) - 66d8: 9809883a mov r4,r19 - 66dc: 000d883a mov r6,zero - 66e0: 01c00044 movi r7,1 - 66e4: 403ee83a callr r8 - 66e8: 1021883a mov r16,r2 - 66ec: 00bfffc4 movi r2,-1 - 66f0: 80800226 beq r16,r2,66fc <_fflush_r+0x1dc> - 66f4: 92000a17 ldw r8,40(r18) - 66f8: 003fa406 br 658c <_fflush_r+0x6c> - 66fc: 98c00017 ldw r3,0(r19) - 6700: 00800744 movi r2,29 - 6704: 18bfde26 beq r3,r2,6680 <_fflush_r+0x160> - 6708: 9080030b ldhu r2,12(r18) - 670c: 8007883a mov r3,r16 - 6710: 10801014 ori r2,r2,64 - 6714: 9080030d sth r2,12(r18) - 6718: 003fcf06 br 6658 <_fflush_r+0x138> - -0000671c : - 671c: 01400034 movhi r5,0 - 6720: 29594804 addi r5,r5,25888 - 6724: 2007883a mov r3,r4 - 6728: 20000526 beq r4,zero,6740 - 672c: 00800074 movhi r2,1 - 6730: 10884004 addi r2,r2,8448 - 6734: 11000017 ldw r4,0(r2) - 6738: 180b883a mov r5,r3 - 673c: 00065201 jmpi 6520 <_fflush_r> - 6740: 00800074 movhi r2,1 - 6744: 10884104 addi r2,r2,8452 - 6748: 11000017 ldw r4,0(r2) - 674c: 00073201 jmpi 7320 <_fwalk_reent> - -00006750 : - 6750: 00800074 movhi r2,1 - 6754: 10a62504 addi r2,r2,-26476 - 6758: 20800b15 stw r2,44(r4) - 675c: 00800074 movhi r2,1 - 6760: 10a66004 addi r2,r2,-26240 - 6764: 20800815 stw r2,32(r4) - 6768: 00c00074 movhi r3,1 - 676c: 18e64104 addi r3,r3,-26364 - 6770: 00800074 movhi r2,1 - 6774: 10a62704 addi r2,r2,-26468 - 6778: 2140030d sth r5,12(r4) - 677c: 2180038d sth r6,14(r4) - 6780: 20c00915 stw r3,36(r4) - 6784: 20800a15 stw r2,40(r4) - 6788: 20000015 stw zero,0(r4) - 678c: 20000115 stw zero,4(r4) - 6790: 20000215 stw zero,8(r4) - 6794: 20000415 stw zero,16(r4) - 6798: 20000515 stw zero,20(r4) - 679c: 20000615 stw zero,24(r4) - 67a0: 21000715 stw r4,28(r4) - 67a4: f800283a ret - -000067a8 <__sfp_lock_acquire>: - 67a8: f800283a ret - -000067ac <__sfp_lock_release>: - 67ac: f800283a ret - -000067b0 <__sinit_lock_acquire>: - 67b0: f800283a ret - -000067b4 <__sinit_lock_release>: - 67b4: f800283a ret - -000067b8 <__sinit>: - 67b8: 20800e17 ldw r2,56(r4) - 67bc: defffd04 addi sp,sp,-12 - 67c0: dc400115 stw r17,4(sp) - 67c4: dc000015 stw r16,0(sp) - 67c8: dfc00215 stw ra,8(sp) - 67cc: 04400044 movi r17,1 - 67d0: 01400104 movi r5,4 - 67d4: 000d883a mov r6,zero - 67d8: 2021883a mov r16,r4 - 67dc: 2200bb04 addi r8,r4,748 - 67e0: 200f883a mov r7,r4 - 67e4: 10000526 beq r2,zero,67fc <__sinit+0x44> - 67e8: dfc00217 ldw ra,8(sp) - 67ec: dc400117 ldw r17,4(sp) - 67f0: dc000017 ldw r16,0(sp) - 67f4: dec00304 addi sp,sp,12 - 67f8: f800283a ret - 67fc: 21000117 ldw r4,4(r4) - 6800: 00800034 movhi r2,0 - 6804: 109a2704 addi r2,r2,26780 - 6808: 00c000c4 movi r3,3 - 680c: 80800f15 stw r2,60(r16) - 6810: 80c0b915 stw r3,740(r16) - 6814: 8200ba15 stw r8,744(r16) - 6818: 84400e15 stw r17,56(r16) - 681c: 8000b815 stw zero,736(r16) - 6820: 00067500 call 6750 - 6824: 81000217 ldw r4,8(r16) - 6828: 880d883a mov r6,r17 - 682c: 800f883a mov r7,r16 - 6830: 01400284 movi r5,10 - 6834: 00067500 call 6750 - 6838: 81000317 ldw r4,12(r16) - 683c: 800f883a mov r7,r16 - 6840: 01400484 movi r5,18 - 6844: 01800084 movi r6,2 - 6848: dfc00217 ldw ra,8(sp) - 684c: dc400117 ldw r17,4(sp) - 6850: dc000017 ldw r16,0(sp) - 6854: dec00304 addi sp,sp,12 - 6858: 00067501 jmpi 6750 - -0000685c <__fp_lock>: - 685c: 0005883a mov r2,zero - 6860: f800283a ret - -00006864 <__fp_unlock>: - 6864: 0005883a mov r2,zero - 6868: f800283a ret - -0000686c <__fp_unlock_all>: - 686c: 00800074 movhi r2,1 - 6870: 10884004 addi r2,r2,8448 - 6874: 11000017 ldw r4,0(r2) - 6878: 01400034 movhi r5,0 - 687c: 295a1904 addi r5,r5,26724 - 6880: 00073e81 jmpi 73e8 <_fwalk> - -00006884 <__fp_lock_all>: - 6884: 00800074 movhi r2,1 - 6888: 10884004 addi r2,r2,8448 - 688c: 11000017 ldw r4,0(r2) - 6890: 01400034 movhi r5,0 - 6894: 295a1704 addi r5,r5,26716 - 6898: 00073e81 jmpi 73e8 <_fwalk> - -0000689c <_cleanup_r>: - 689c: 01400074 movhi r5,1 - 68a0: 29675704 addi r5,r5,-25252 - 68a4: 00073e81 jmpi 73e8 <_fwalk> - -000068a8 <_cleanup>: - 68a8: 00800074 movhi r2,1 - 68ac: 10884104 addi r2,r2,8452 - 68b0: 11000017 ldw r4,0(r2) - 68b4: 000689c1 jmpi 689c <_cleanup_r> - -000068b8 <__sfmoreglue>: - 68b8: defffc04 addi sp,sp,-16 - 68bc: dc000015 stw r16,0(sp) - 68c0: 2821883a mov r16,r5 - 68c4: dc400115 stw r17,4(sp) - 68c8: 01401704 movi r5,92 - 68cc: 2023883a mov r17,r4 - 68d0: 8009883a mov r4,r16 - 68d4: dfc00315 stw ra,12(sp) - 68d8: dcc00215 stw r19,8(sp) - 68dc: 0002b2c0 call 2b2c <__mulsi3> - 68e0: 11400304 addi r5,r2,12 - 68e4: 8809883a mov r4,r17 - 68e8: 1027883a mov r19,r2 - 68ec: 00076f80 call 76f8 <_malloc_r> - 68f0: 10c00304 addi r3,r2,12 - 68f4: 1023883a mov r17,r2 - 68f8: 1809883a mov r4,r3 - 68fc: 980d883a mov r6,r19 - 6900: 000b883a mov r5,zero - 6904: 10000b26 beq r2,zero,6934 <__sfmoreglue+0x7c> - 6908: 14000115 stw r16,4(r2) - 690c: 10c00215 stw r3,8(r2) - 6910: 10000015 stw zero,0(r2) - 6914: 000809c0 call 809c - 6918: 8805883a mov r2,r17 - 691c: dfc00317 ldw ra,12(sp) - 6920: dcc00217 ldw r19,8(sp) - 6924: dc400117 ldw r17,4(sp) - 6928: dc000017 ldw r16,0(sp) - 692c: dec00404 addi sp,sp,16 - 6930: f800283a ret - 6934: 0023883a mov r17,zero - 6938: 8805883a mov r2,r17 - 693c: dfc00317 ldw ra,12(sp) - 6940: dcc00217 ldw r19,8(sp) - 6944: dc400117 ldw r17,4(sp) - 6948: dc000017 ldw r16,0(sp) - 694c: dec00404 addi sp,sp,16 - 6950: f800283a ret - -00006954 <__sfp>: - 6954: defffd04 addi sp,sp,-12 - 6958: 00800074 movhi r2,1 - 695c: 10884104 addi r2,r2,8452 - 6960: dc000015 stw r16,0(sp) - 6964: 14000017 ldw r16,0(r2) - 6968: dc400115 stw r17,4(sp) - 696c: dfc00215 stw ra,8(sp) - 6970: 80800e17 ldw r2,56(r16) - 6974: 2023883a mov r17,r4 - 6978: 10002626 beq r2,zero,6a14 <__sfp+0xc0> - 697c: 8400b804 addi r16,r16,736 - 6980: 80800117 ldw r2,4(r16) - 6984: 81000217 ldw r4,8(r16) - 6988: 10ffffc4 addi r3,r2,-1 - 698c: 18000916 blt r3,zero,69b4 <__sfp+0x60> - 6990: 2080030f ldh r2,12(r4) - 6994: 10000b26 beq r2,zero,69c4 <__sfp+0x70> - 6998: 017fffc4 movi r5,-1 - 699c: 00000206 br 69a8 <__sfp+0x54> - 69a0: 2080030f ldh r2,12(r4) - 69a4: 10000726 beq r2,zero,69c4 <__sfp+0x70> - 69a8: 18ffffc4 addi r3,r3,-1 - 69ac: 21001704 addi r4,r4,92 - 69b0: 197ffb1e bne r3,r5,69a0 <__sfp+0x4c> - 69b4: 80800017 ldw r2,0(r16) - 69b8: 10001926 beq r2,zero,6a20 <__sfp+0xcc> - 69bc: 1021883a mov r16,r2 - 69c0: 003fef06 br 6980 <__sfp+0x2c> - 69c4: 00bfffc4 movi r2,-1 - 69c8: 00c00044 movi r3,1 - 69cc: 2080038d sth r2,14(r4) - 69d0: 20c0030d sth r3,12(r4) - 69d4: 20000015 stw zero,0(r4) - 69d8: 20000215 stw zero,8(r4) - 69dc: 20000115 stw zero,4(r4) - 69e0: 20000415 stw zero,16(r4) - 69e4: 20000515 stw zero,20(r4) - 69e8: 20000615 stw zero,24(r4) - 69ec: 20000c15 stw zero,48(r4) - 69f0: 20000d15 stw zero,52(r4) - 69f4: 20001115 stw zero,68(r4) - 69f8: 20001215 stw zero,72(r4) - 69fc: 2005883a mov r2,r4 - 6a00: dfc00217 ldw ra,8(sp) - 6a04: dc400117 ldw r17,4(sp) - 6a08: dc000017 ldw r16,0(sp) - 6a0c: dec00304 addi sp,sp,12 - 6a10: f800283a ret - 6a14: 8009883a mov r4,r16 - 6a18: 00067b80 call 67b8 <__sinit> - 6a1c: 003fd706 br 697c <__sfp+0x28> - 6a20: 8809883a mov r4,r17 - 6a24: 01400104 movi r5,4 - 6a28: 00068b80 call 68b8 <__sfmoreglue> - 6a2c: 80800015 stw r2,0(r16) - 6a30: 103fe21e bne r2,zero,69bc <__sfp+0x68> - 6a34: 00800304 movi r2,12 - 6a38: 0009883a mov r4,zero - 6a3c: 88800015 stw r2,0(r17) - 6a40: 003fee06 br 69fc <__sfp+0xa8> - -00006a44 <_malloc_trim_r>: - 6a44: defffb04 addi sp,sp,-20 - 6a48: dcc00315 stw r19,12(sp) - 6a4c: 04c00074 movhi r19,1 - 6a50: 9cc27204 addi r19,r19,2504 - 6a54: dc800215 stw r18,8(sp) - 6a58: dc400115 stw r17,4(sp) - 6a5c: dc000015 stw r16,0(sp) - 6a60: 2823883a mov r17,r5 - 6a64: 2025883a mov r18,r4 - 6a68: dfc00415 stw ra,16(sp) - 6a6c: 000ca880 call ca88 <__malloc_lock> - 6a70: 98800217 ldw r2,8(r19) - 6a74: 9009883a mov r4,r18 - 6a78: 000b883a mov r5,zero - 6a7c: 10c00117 ldw r3,4(r2) - 6a80: 00bfff04 movi r2,-4 - 6a84: 18a0703a and r16,r3,r2 - 6a88: 8463c83a sub r17,r16,r17 - 6a8c: 8c43fbc4 addi r17,r17,4079 - 6a90: 8822d33a srli r17,r17,12 - 6a94: 0083ffc4 movi r2,4095 - 6a98: 8c7fffc4 addi r17,r17,-1 - 6a9c: 8822933a slli r17,r17,12 - 6aa0: 1440060e bge r2,r17,6abc <_malloc_trim_r+0x78> - 6aa4: 00098240 call 9824 <_sbrk_r> - 6aa8: 98c00217 ldw r3,8(r19) - 6aac: 9009883a mov r4,r18 - 6ab0: 044bc83a sub r5,zero,r17 - 6ab4: 80c7883a add r3,r16,r3 - 6ab8: 10c00926 beq r2,r3,6ae0 <_malloc_trim_r+0x9c> - 6abc: 000caa80 call caa8 <__malloc_unlock> - 6ac0: 0005883a mov r2,zero - 6ac4: dfc00417 ldw ra,16(sp) - 6ac8: dcc00317 ldw r19,12(sp) - 6acc: dc800217 ldw r18,8(sp) - 6ad0: dc400117 ldw r17,4(sp) - 6ad4: dc000017 ldw r16,0(sp) - 6ad8: dec00504 addi sp,sp,20 - 6adc: f800283a ret - 6ae0: 9009883a mov r4,r18 - 6ae4: 00098240 call 9824 <_sbrk_r> - 6ae8: 844dc83a sub r6,r16,r17 - 6aec: 00ffffc4 movi r3,-1 - 6af0: 9009883a mov r4,r18 - 6af4: 000b883a mov r5,zero - 6af8: 01c00074 movhi r7,1 - 6afc: 39d08504 addi r7,r7,16916 - 6b00: 31800054 ori r6,r6,1 - 6b04: 10c00926 beq r2,r3,6b2c <_malloc_trim_r+0xe8> - 6b08: 38800017 ldw r2,0(r7) - 6b0c: 98c00217 ldw r3,8(r19) - 6b10: 9009883a mov r4,r18 - 6b14: 1445c83a sub r2,r2,r17 - 6b18: 38800015 stw r2,0(r7) - 6b1c: 19800115 stw r6,4(r3) - 6b20: 000caa80 call caa8 <__malloc_unlock> - 6b24: 00800044 movi r2,1 - 6b28: 003fe606 br 6ac4 <_malloc_trim_r+0x80> - 6b2c: 00098240 call 9824 <_sbrk_r> - 6b30: 99800217 ldw r6,8(r19) - 6b34: 100f883a mov r7,r2 - 6b38: 9009883a mov r4,r18 - 6b3c: 1187c83a sub r3,r2,r6 - 6b40: 008003c4 movi r2,15 - 6b44: 19400054 ori r5,r3,1 - 6b48: 10ffdc0e bge r2,r3,6abc <_malloc_trim_r+0x78> - 6b4c: 00800074 movhi r2,1 - 6b50: 10884504 addi r2,r2,8468 - 6b54: 10c00017 ldw r3,0(r2) - 6b58: 00800074 movhi r2,1 - 6b5c: 10908504 addi r2,r2,16916 - 6b60: 31400115 stw r5,4(r6) - 6b64: 38c7c83a sub r3,r7,r3 - 6b68: 10c00015 stw r3,0(r2) - 6b6c: 003fd306 br 6abc <_malloc_trim_r+0x78> - -00006b70 <_free_r>: - 6b70: defffd04 addi sp,sp,-12 - 6b74: dc400115 stw r17,4(sp) - 6b78: dc000015 stw r16,0(sp) - 6b7c: dfc00215 stw ra,8(sp) - 6b80: 2821883a mov r16,r5 - 6b84: 2023883a mov r17,r4 - 6b88: 28005a26 beq r5,zero,6cf4 <_free_r+0x184> - 6b8c: 000ca880 call ca88 <__malloc_lock> - 6b90: 823ffe04 addi r8,r16,-8 - 6b94: 41400117 ldw r5,4(r8) - 6b98: 00bfff84 movi r2,-2 - 6b9c: 02800074 movhi r10,1 - 6ba0: 52827204 addi r10,r10,2504 - 6ba4: 288e703a and r7,r5,r2 - 6ba8: 41cd883a add r6,r8,r7 - 6bac: 30c00117 ldw r3,4(r6) - 6bb0: 51000217 ldw r4,8(r10) - 6bb4: 00bfff04 movi r2,-4 - 6bb8: 1892703a and r9,r3,r2 - 6bbc: 5017883a mov r11,r10 - 6bc0: 31006726 beq r6,r4,6d60 <_free_r+0x1f0> - 6bc4: 2880004c andi r2,r5,1 - 6bc8: 1005003a cmpeq r2,r2,zero - 6bcc: 32400115 stw r9,4(r6) - 6bd0: 10001a1e bne r2,zero,6c3c <_free_r+0xcc> - 6bd4: 000b883a mov r5,zero - 6bd8: 3247883a add r3,r6,r9 - 6bdc: 18800117 ldw r2,4(r3) - 6be0: 1080004c andi r2,r2,1 - 6be4: 1000231e bne r2,zero,6c74 <_free_r+0x104> - 6be8: 280ac03a cmpne r5,r5,zero - 6bec: 3a4f883a add r7,r7,r9 - 6bf0: 2800451e bne r5,zero,6d08 <_free_r+0x198> - 6bf4: 31000217 ldw r4,8(r6) - 6bf8: 00800074 movhi r2,1 - 6bfc: 10827404 addi r2,r2,2512 - 6c00: 20807b26 beq r4,r2,6df0 <_free_r+0x280> - 6c04: 30800317 ldw r2,12(r6) - 6c08: 3a07883a add r3,r7,r8 - 6c0c: 19c00015 stw r7,0(r3) - 6c10: 11000215 stw r4,8(r2) - 6c14: 20800315 stw r2,12(r4) - 6c18: 38800054 ori r2,r7,1 - 6c1c: 40800115 stw r2,4(r8) - 6c20: 28001a26 beq r5,zero,6c8c <_free_r+0x11c> - 6c24: 8809883a mov r4,r17 - 6c28: dfc00217 ldw ra,8(sp) - 6c2c: dc400117 ldw r17,4(sp) - 6c30: dc000017 ldw r16,0(sp) - 6c34: dec00304 addi sp,sp,12 - 6c38: 000caa81 jmpi caa8 <__malloc_unlock> - 6c3c: 80bffe17 ldw r2,-8(r16) - 6c40: 50c00204 addi r3,r10,8 - 6c44: 4091c83a sub r8,r8,r2 - 6c48: 41000217 ldw r4,8(r8) - 6c4c: 388f883a add r7,r7,r2 - 6c50: 20c06126 beq r4,r3,6dd8 <_free_r+0x268> - 6c54: 40800317 ldw r2,12(r8) - 6c58: 3247883a add r3,r6,r9 - 6c5c: 000b883a mov r5,zero - 6c60: 11000215 stw r4,8(r2) - 6c64: 20800315 stw r2,12(r4) - 6c68: 18800117 ldw r2,4(r3) - 6c6c: 1080004c andi r2,r2,1 - 6c70: 103fdd26 beq r2,zero,6be8 <_free_r+0x78> - 6c74: 38800054 ori r2,r7,1 - 6c78: 3a07883a add r3,r7,r8 - 6c7c: 280ac03a cmpne r5,r5,zero - 6c80: 40800115 stw r2,4(r8) - 6c84: 19c00015 stw r7,0(r3) - 6c88: 283fe61e bne r5,zero,6c24 <_free_r+0xb4> - 6c8c: 00807fc4 movi r2,511 - 6c90: 11c01f2e bgeu r2,r7,6d10 <_free_r+0x1a0> - 6c94: 3806d27a srli r3,r7,9 - 6c98: 1800481e bne r3,zero,6dbc <_free_r+0x24c> - 6c9c: 3804d0fa srli r2,r7,3 - 6ca0: 100690fa slli r3,r2,3 - 6ca4: 1acd883a add r6,r3,r11 - 6ca8: 31400217 ldw r5,8(r6) - 6cac: 31405926 beq r6,r5,6e14 <_free_r+0x2a4> - 6cb0: 28800117 ldw r2,4(r5) - 6cb4: 00ffff04 movi r3,-4 - 6cb8: 10c4703a and r2,r2,r3 - 6cbc: 3880022e bgeu r7,r2,6cc8 <_free_r+0x158> - 6cc0: 29400217 ldw r5,8(r5) - 6cc4: 317ffa1e bne r6,r5,6cb0 <_free_r+0x140> - 6cc8: 29800317 ldw r6,12(r5) - 6ccc: 41800315 stw r6,12(r8) - 6cd0: 41400215 stw r5,8(r8) - 6cd4: 8809883a mov r4,r17 - 6cd8: 2a000315 stw r8,12(r5) - 6cdc: 32000215 stw r8,8(r6) - 6ce0: dfc00217 ldw ra,8(sp) - 6ce4: dc400117 ldw r17,4(sp) - 6ce8: dc000017 ldw r16,0(sp) - 6cec: dec00304 addi sp,sp,12 - 6cf0: 000caa81 jmpi caa8 <__malloc_unlock> - 6cf4: dfc00217 ldw ra,8(sp) - 6cf8: dc400117 ldw r17,4(sp) - 6cfc: dc000017 ldw r16,0(sp) - 6d00: dec00304 addi sp,sp,12 - 6d04: f800283a ret - 6d08: 31000217 ldw r4,8(r6) - 6d0c: 003fbd06 br 6c04 <_free_r+0x94> - 6d10: 3806d0fa srli r3,r7,3 - 6d14: 00800044 movi r2,1 - 6d18: 51400117 ldw r5,4(r10) - 6d1c: 180890fa slli r4,r3,3 - 6d20: 1807d0ba srai r3,r3,2 - 6d24: 22c9883a add r4,r4,r11 - 6d28: 21800217 ldw r6,8(r4) - 6d2c: 10c4983a sll r2,r2,r3 - 6d30: 41000315 stw r4,12(r8) - 6d34: 41800215 stw r6,8(r8) - 6d38: 288ab03a or r5,r5,r2 - 6d3c: 22000215 stw r8,8(r4) - 6d40: 8809883a mov r4,r17 - 6d44: 51400115 stw r5,4(r10) - 6d48: 32000315 stw r8,12(r6) - 6d4c: dfc00217 ldw ra,8(sp) - 6d50: dc400117 ldw r17,4(sp) - 6d54: dc000017 ldw r16,0(sp) - 6d58: dec00304 addi sp,sp,12 - 6d5c: 000caa81 jmpi caa8 <__malloc_unlock> - 6d60: 2880004c andi r2,r5,1 - 6d64: 3a4d883a add r6,r7,r9 - 6d68: 1000071e bne r2,zero,6d88 <_free_r+0x218> - 6d6c: 80bffe17 ldw r2,-8(r16) - 6d70: 4091c83a sub r8,r8,r2 - 6d74: 41000317 ldw r4,12(r8) - 6d78: 40c00217 ldw r3,8(r8) - 6d7c: 308d883a add r6,r6,r2 - 6d80: 20c00215 stw r3,8(r4) - 6d84: 19000315 stw r4,12(r3) - 6d88: 00800074 movhi r2,1 - 6d8c: 10884404 addi r2,r2,8464 - 6d90: 11000017 ldw r4,0(r2) - 6d94: 30c00054 ori r3,r6,1 - 6d98: 52000215 stw r8,8(r10) - 6d9c: 40c00115 stw r3,4(r8) - 6da0: 313fa036 bltu r6,r4,6c24 <_free_r+0xb4> - 6da4: 00800074 movhi r2,1 - 6da8: 108f3b04 addi r2,r2,15596 - 6dac: 11400017 ldw r5,0(r2) - 6db0: 8809883a mov r4,r17 - 6db4: 0006a440 call 6a44 <_malloc_trim_r> - 6db8: 003f9a06 br 6c24 <_free_r+0xb4> - 6dbc: 00800104 movi r2,4 - 6dc0: 10c0072e bgeu r2,r3,6de0 <_free_r+0x270> - 6dc4: 00800504 movi r2,20 - 6dc8: 10c01936 bltu r2,r3,6e30 <_free_r+0x2c0> - 6dcc: 188016c4 addi r2,r3,91 - 6dd0: 100690fa slli r3,r2,3 - 6dd4: 003fb306 br 6ca4 <_free_r+0x134> - 6dd8: 01400044 movi r5,1 - 6ddc: 003f7e06 br 6bd8 <_free_r+0x68> - 6de0: 3804d1ba srli r2,r7,6 - 6de4: 10800e04 addi r2,r2,56 - 6de8: 100690fa slli r3,r2,3 - 6dec: 003fad06 br 6ca4 <_free_r+0x134> - 6df0: 22000315 stw r8,12(r4) - 6df4: 22000215 stw r8,8(r4) - 6df8: 3a05883a add r2,r7,r8 - 6dfc: 38c00054 ori r3,r7,1 - 6e00: 11c00015 stw r7,0(r2) - 6e04: 41000215 stw r4,8(r8) - 6e08: 40c00115 stw r3,4(r8) - 6e0c: 41000315 stw r4,12(r8) - 6e10: 003f8406 br 6c24 <_free_r+0xb4> - 6e14: 1005d0ba srai r2,r2,2 - 6e18: 00c00044 movi r3,1 - 6e1c: 51000117 ldw r4,4(r10) - 6e20: 1886983a sll r3,r3,r2 - 6e24: 20c8b03a or r4,r4,r3 - 6e28: 51000115 stw r4,4(r10) - 6e2c: 003fa706 br 6ccc <_free_r+0x15c> - 6e30: 00801504 movi r2,84 - 6e34: 10c00436 bltu r2,r3,6e48 <_free_r+0x2d8> - 6e38: 3804d33a srli r2,r7,12 - 6e3c: 10801b84 addi r2,r2,110 - 6e40: 100690fa slli r3,r2,3 - 6e44: 003f9706 br 6ca4 <_free_r+0x134> - 6e48: 00805504 movi r2,340 - 6e4c: 10c00436 bltu r2,r3,6e60 <_free_r+0x2f0> - 6e50: 3804d3fa srli r2,r7,15 - 6e54: 10801dc4 addi r2,r2,119 - 6e58: 100690fa slli r3,r2,3 - 6e5c: 003f9106 br 6ca4 <_free_r+0x134> - 6e60: 00815504 movi r2,1364 - 6e64: 10c0032e bgeu r2,r3,6e74 <_free_r+0x304> - 6e68: 00801f84 movi r2,126 - 6e6c: 00c0fc04 movi r3,1008 - 6e70: 003f8c06 br 6ca4 <_free_r+0x134> - 6e74: 3804d4ba srli r2,r7,18 - 6e78: 10801f04 addi r2,r2,124 - 6e7c: 100690fa slli r3,r2,3 - 6e80: 003f8806 br 6ca4 <_free_r+0x134> - -00006e84 <__sfvwrite_r>: - 6e84: 30800217 ldw r2,8(r6) - 6e88: defff504 addi sp,sp,-44 - 6e8c: df000915 stw fp,36(sp) - 6e90: dd800715 stw r22,28(sp) - 6e94: dc800315 stw r18,12(sp) - 6e98: dfc00a15 stw ra,40(sp) - 6e9c: ddc00815 stw r23,32(sp) - 6ea0: dd400615 stw r21,24(sp) - 6ea4: dd000515 stw r20,20(sp) - 6ea8: dcc00415 stw r19,16(sp) - 6eac: dc400215 stw r17,8(sp) - 6eb0: dc000115 stw r16,4(sp) - 6eb4: 302d883a mov r22,r6 - 6eb8: 2039883a mov fp,r4 - 6ebc: 2825883a mov r18,r5 - 6ec0: 10001c26 beq r2,zero,6f34 <__sfvwrite_r+0xb0> - 6ec4: 29c0030b ldhu r7,12(r5) - 6ec8: 3880020c andi r2,r7,8 - 6ecc: 10002726 beq r2,zero,6f6c <__sfvwrite_r+0xe8> - 6ed0: 28800417 ldw r2,16(r5) - 6ed4: 10002526 beq r2,zero,6f6c <__sfvwrite_r+0xe8> - 6ed8: 3880008c andi r2,r7,2 - 6edc: b5400017 ldw r21,0(r22) - 6ee0: 10002826 beq r2,zero,6f84 <__sfvwrite_r+0x100> - 6ee4: 0021883a mov r16,zero - 6ee8: 0023883a mov r17,zero - 6eec: 880d883a mov r6,r17 - 6ef0: e009883a mov r4,fp - 6ef4: 00810004 movi r2,1024 - 6ef8: 80006e26 beq r16,zero,70b4 <__sfvwrite_r+0x230> - 6efc: 800f883a mov r7,r16 - 6f00: 91400717 ldw r5,28(r18) - 6f04: 1400012e bgeu r2,r16,6f0c <__sfvwrite_r+0x88> - 6f08: 100f883a mov r7,r2 - 6f0c: 90c00917 ldw r3,36(r18) - 6f10: 183ee83a callr r3 - 6f14: 1007883a mov r3,r2 - 6f18: 80a1c83a sub r16,r16,r2 - 6f1c: 88a3883a add r17,r17,r2 - 6f20: 00806d0e bge zero,r2,70d8 <__sfvwrite_r+0x254> - 6f24: b0800217 ldw r2,8(r22) - 6f28: 10c5c83a sub r2,r2,r3 - 6f2c: b0800215 stw r2,8(r22) - 6f30: 103fee1e bne r2,zero,6eec <__sfvwrite_r+0x68> - 6f34: 0009883a mov r4,zero - 6f38: 2005883a mov r2,r4 - 6f3c: dfc00a17 ldw ra,40(sp) - 6f40: df000917 ldw fp,36(sp) - 6f44: ddc00817 ldw r23,32(sp) - 6f48: dd800717 ldw r22,28(sp) - 6f4c: dd400617 ldw r21,24(sp) - 6f50: dd000517 ldw r20,20(sp) - 6f54: dcc00417 ldw r19,16(sp) - 6f58: dc800317 ldw r18,12(sp) - 6f5c: dc400217 ldw r17,8(sp) - 6f60: dc000117 ldw r16,4(sp) - 6f64: dec00b04 addi sp,sp,44 - 6f68: f800283a ret - 6f6c: 0004bec0 call 4bec <__swsetup_r> - 6f70: 1000e41e bne r2,zero,7304 <__sfvwrite_r+0x480> - 6f74: 91c0030b ldhu r7,12(r18) - 6f78: b5400017 ldw r21,0(r22) - 6f7c: 3880008c andi r2,r7,2 - 6f80: 103fd81e bne r2,zero,6ee4 <__sfvwrite_r+0x60> - 6f84: 3880004c andi r2,r7,1 - 6f88: 1005003a cmpeq r2,r2,zero - 6f8c: 10005726 beq r2,zero,70ec <__sfvwrite_r+0x268> - 6f90: 0029883a mov r20,zero - 6f94: 002f883a mov r23,zero - 6f98: a0004226 beq r20,zero,70a4 <__sfvwrite_r+0x220> - 6f9c: 3880800c andi r2,r7,512 - 6fa0: 94000217 ldw r16,8(r18) - 6fa4: 10008b26 beq r2,zero,71d4 <__sfvwrite_r+0x350> - 6fa8: 800d883a mov r6,r16 - 6fac: a400a536 bltu r20,r16,7244 <__sfvwrite_r+0x3c0> - 6fb0: 3881200c andi r2,r7,1152 - 6fb4: 10002726 beq r2,zero,7054 <__sfvwrite_r+0x1d0> - 6fb8: 90800517 ldw r2,20(r18) - 6fbc: 92000417 ldw r8,16(r18) - 6fc0: 91400017 ldw r5,0(r18) - 6fc4: 1087883a add r3,r2,r2 - 6fc8: 1887883a add r3,r3,r2 - 6fcc: 1808d7fa srli r4,r3,31 - 6fd0: 2a21c83a sub r16,r5,r8 - 6fd4: 80800044 addi r2,r16,1 - 6fd8: 20c9883a add r4,r4,r3 - 6fdc: 2027d07a srai r19,r4,1 - 6fe0: a085883a add r2,r20,r2 - 6fe4: 980d883a mov r6,r19 - 6fe8: 9880022e bgeu r19,r2,6ff4 <__sfvwrite_r+0x170> - 6fec: 1027883a mov r19,r2 - 6ff0: 100d883a mov r6,r2 - 6ff4: 3881000c andi r2,r7,1024 - 6ff8: 1000b826 beq r2,zero,72dc <__sfvwrite_r+0x458> - 6ffc: 300b883a mov r5,r6 - 7000: e009883a mov r4,fp - 7004: 00076f80 call 76f8 <_malloc_r> - 7008: 10003126 beq r2,zero,70d0 <__sfvwrite_r+0x24c> - 700c: 91400417 ldw r5,16(r18) - 7010: 1009883a mov r4,r2 - 7014: 800d883a mov r6,r16 - 7018: 1023883a mov r17,r2 - 701c: 0007f1c0 call 7f1c - 7020: 90c0030b ldhu r3,12(r18) - 7024: 00beffc4 movi r2,-1025 - 7028: 1886703a and r3,r3,r2 - 702c: 18c02014 ori r3,r3,128 - 7030: 90c0030d sth r3,12(r18) - 7034: 9c07c83a sub r3,r19,r16 - 7038: 8c05883a add r2,r17,r16 - 703c: a00d883a mov r6,r20 - 7040: a021883a mov r16,r20 - 7044: 90800015 stw r2,0(r18) - 7048: 90c00215 stw r3,8(r18) - 704c: 94400415 stw r17,16(r18) - 7050: 94c00515 stw r19,20(r18) - 7054: 91000017 ldw r4,0(r18) - 7058: b80b883a mov r5,r23 - 705c: a023883a mov r17,r20 - 7060: 0007fbc0 call 7fbc - 7064: 90c00217 ldw r3,8(r18) - 7068: 90800017 ldw r2,0(r18) - 706c: a027883a mov r19,r20 - 7070: 1c07c83a sub r3,r3,r16 - 7074: 1405883a add r2,r2,r16 - 7078: 90c00215 stw r3,8(r18) - 707c: a021883a mov r16,r20 - 7080: 90800015 stw r2,0(r18) - 7084: b0800217 ldw r2,8(r22) - 7088: 1405c83a sub r2,r2,r16 - 708c: b0800215 stw r2,8(r22) - 7090: 103fa826 beq r2,zero,6f34 <__sfvwrite_r+0xb0> - 7094: a469c83a sub r20,r20,r17 - 7098: 91c0030b ldhu r7,12(r18) - 709c: bcef883a add r23,r23,r19 - 70a0: a03fbe1e bne r20,zero,6f9c <__sfvwrite_r+0x118> - 70a4: adc00017 ldw r23,0(r21) - 70a8: ad000117 ldw r20,4(r21) - 70ac: ad400204 addi r21,r21,8 - 70b0: 003fb906 br 6f98 <__sfvwrite_r+0x114> - 70b4: ac400017 ldw r17,0(r21) - 70b8: ac000117 ldw r16,4(r21) - 70bc: ad400204 addi r21,r21,8 - 70c0: 003f8a06 br 6eec <__sfvwrite_r+0x68> - 70c4: 91400417 ldw r5,16(r18) - 70c8: e009883a mov r4,fp - 70cc: 0006b700 call 6b70 <_free_r> - 70d0: 00800304 movi r2,12 - 70d4: e0800015 stw r2,0(fp) - 70d8: 9080030b ldhu r2,12(r18) - 70dc: 013fffc4 movi r4,-1 - 70e0: 10801014 ori r2,r2,64 - 70e4: 9080030d sth r2,12(r18) - 70e8: 003f9306 br 6f38 <__sfvwrite_r+0xb4> - 70ec: 0027883a mov r19,zero - 70f0: 002f883a mov r23,zero - 70f4: d8000015 stw zero,0(sp) - 70f8: 0029883a mov r20,zero - 70fc: 98001e26 beq r19,zero,7178 <__sfvwrite_r+0x2f4> - 7100: d8c00017 ldw r3,0(sp) - 7104: 1804c03a cmpne r2,r3,zero - 7108: 10005e26 beq r2,zero,7284 <__sfvwrite_r+0x400> - 710c: 9821883a mov r16,r19 - 7110: a4c0012e bgeu r20,r19,7118 <__sfvwrite_r+0x294> - 7114: a021883a mov r16,r20 - 7118: 91000017 ldw r4,0(r18) - 711c: 90800417 ldw r2,16(r18) - 7120: 91800217 ldw r6,8(r18) - 7124: 91c00517 ldw r7,20(r18) - 7128: 1100022e bgeu r2,r4,7134 <__sfvwrite_r+0x2b0> - 712c: 31e3883a add r17,r6,r7 - 7130: 8c001616 blt r17,r16,718c <__sfvwrite_r+0x308> - 7134: 81c03816 blt r16,r7,7218 <__sfvwrite_r+0x394> - 7138: 90c00917 ldw r3,36(r18) - 713c: 91400717 ldw r5,28(r18) - 7140: e009883a mov r4,fp - 7144: b80d883a mov r6,r23 - 7148: 183ee83a callr r3 - 714c: 1023883a mov r17,r2 - 7150: 00bfe10e bge zero,r2,70d8 <__sfvwrite_r+0x254> - 7154: a469c83a sub r20,r20,r17 - 7158: a0001826 beq r20,zero,71bc <__sfvwrite_r+0x338> - 715c: b0800217 ldw r2,8(r22) - 7160: 1445c83a sub r2,r2,r17 - 7164: b0800215 stw r2,8(r22) - 7168: 103f7226 beq r2,zero,6f34 <__sfvwrite_r+0xb0> - 716c: 9c67c83a sub r19,r19,r17 - 7170: bc6f883a add r23,r23,r17 - 7174: 983fe21e bne r19,zero,7100 <__sfvwrite_r+0x27c> - 7178: adc00017 ldw r23,0(r21) - 717c: acc00117 ldw r19,4(r21) - 7180: ad400204 addi r21,r21,8 - 7184: d8000015 stw zero,0(sp) - 7188: 003fdc06 br 70fc <__sfvwrite_r+0x278> - 718c: b80b883a mov r5,r23 - 7190: 880d883a mov r6,r17 - 7194: 0007fbc0 call 7fbc - 7198: 90c00017 ldw r3,0(r18) - 719c: e009883a mov r4,fp - 71a0: 900b883a mov r5,r18 - 71a4: 1c47883a add r3,r3,r17 - 71a8: 90c00015 stw r3,0(r18) - 71ac: 00065200 call 6520 <_fflush_r> - 71b0: 103fc91e bne r2,zero,70d8 <__sfvwrite_r+0x254> - 71b4: a469c83a sub r20,r20,r17 - 71b8: a03fe81e bne r20,zero,715c <__sfvwrite_r+0x2d8> - 71bc: e009883a mov r4,fp - 71c0: 900b883a mov r5,r18 - 71c4: 00065200 call 6520 <_fflush_r> - 71c8: 103fc31e bne r2,zero,70d8 <__sfvwrite_r+0x254> - 71cc: d8000015 stw zero,0(sp) - 71d0: 003fe206 br 715c <__sfvwrite_r+0x2d8> - 71d4: 91000017 ldw r4,0(r18) - 71d8: 90800417 ldw r2,16(r18) - 71dc: 1100022e bgeu r2,r4,71e8 <__sfvwrite_r+0x364> - 71e0: 8023883a mov r17,r16 - 71e4: 85003136 bltu r16,r20,72ac <__sfvwrite_r+0x428> - 71e8: 91c00517 ldw r7,20(r18) - 71ec: a1c01836 bltu r20,r7,7250 <__sfvwrite_r+0x3cc> - 71f0: 90c00917 ldw r3,36(r18) - 71f4: 91400717 ldw r5,28(r18) - 71f8: e009883a mov r4,fp - 71fc: b80d883a mov r6,r23 - 7200: 183ee83a callr r3 - 7204: 1021883a mov r16,r2 - 7208: 00bfb30e bge zero,r2,70d8 <__sfvwrite_r+0x254> - 720c: 1023883a mov r17,r2 - 7210: 1027883a mov r19,r2 - 7214: 003f9b06 br 7084 <__sfvwrite_r+0x200> - 7218: b80b883a mov r5,r23 - 721c: 800d883a mov r6,r16 - 7220: 0007fbc0 call 7fbc - 7224: 90c00217 ldw r3,8(r18) - 7228: 90800017 ldw r2,0(r18) - 722c: 8023883a mov r17,r16 - 7230: 1c07c83a sub r3,r3,r16 - 7234: 1405883a add r2,r2,r16 - 7238: 90c00215 stw r3,8(r18) - 723c: 90800015 stw r2,0(r18) - 7240: 003fc406 br 7154 <__sfvwrite_r+0x2d0> - 7244: a00d883a mov r6,r20 - 7248: a021883a mov r16,r20 - 724c: 003f8106 br 7054 <__sfvwrite_r+0x1d0> - 7250: b80b883a mov r5,r23 - 7254: a00d883a mov r6,r20 - 7258: 0007fbc0 call 7fbc - 725c: 90c00217 ldw r3,8(r18) - 7260: 90800017 ldw r2,0(r18) - 7264: a021883a mov r16,r20 - 7268: 1d07c83a sub r3,r3,r20 - 726c: 1505883a add r2,r2,r20 - 7270: a023883a mov r17,r20 - 7274: a027883a mov r19,r20 - 7278: 90c00215 stw r3,8(r18) - 727c: 90800015 stw r2,0(r18) - 7280: 003f8006 br 7084 <__sfvwrite_r+0x200> - 7284: b809883a mov r4,r23 - 7288: 01400284 movi r5,10 - 728c: 980d883a mov r6,r19 - 7290: 0007e380 call 7e38 - 7294: 10001726 beq r2,zero,72f4 <__sfvwrite_r+0x470> - 7298: 15c5c83a sub r2,r2,r23 - 729c: 15000044 addi r20,r2,1 - 72a0: 00800044 movi r2,1 - 72a4: d8800015 stw r2,0(sp) - 72a8: 003f9806 br 710c <__sfvwrite_r+0x288> - 72ac: b80b883a mov r5,r23 - 72b0: 800d883a mov r6,r16 - 72b4: 0007fbc0 call 7fbc - 72b8: 90c00017 ldw r3,0(r18) - 72bc: e009883a mov r4,fp - 72c0: 900b883a mov r5,r18 - 72c4: 1c07883a add r3,r3,r16 - 72c8: 90c00015 stw r3,0(r18) - 72cc: 8027883a mov r19,r16 - 72d0: 00065200 call 6520 <_fflush_r> - 72d4: 103f6b26 beq r2,zero,7084 <__sfvwrite_r+0x200> - 72d8: 003f7f06 br 70d8 <__sfvwrite_r+0x254> - 72dc: 400b883a mov r5,r8 - 72e0: e009883a mov r4,fp - 72e4: 00091c00 call 91c0 <_realloc_r> - 72e8: 103f7626 beq r2,zero,70c4 <__sfvwrite_r+0x240> - 72ec: 1023883a mov r17,r2 - 72f0: 003f5006 br 7034 <__sfvwrite_r+0x1b0> - 72f4: 00c00044 movi r3,1 - 72f8: 9d000044 addi r20,r19,1 - 72fc: d8c00015 stw r3,0(sp) - 7300: 003f8206 br 710c <__sfvwrite_r+0x288> - 7304: 9080030b ldhu r2,12(r18) - 7308: 00c00244 movi r3,9 - 730c: 013fffc4 movi r4,-1 - 7310: 10801014 ori r2,r2,64 - 7314: 9080030d sth r2,12(r18) - 7318: e0c00015 stw r3,0(fp) - 731c: 003f0606 br 6f38 <__sfvwrite_r+0xb4> - -00007320 <_fwalk_reent>: - 7320: defff704 addi sp,sp,-36 - 7324: dcc00315 stw r19,12(sp) - 7328: 24c0b804 addi r19,r4,736 - 732c: dd800615 stw r22,24(sp) - 7330: dd400515 stw r21,20(sp) - 7334: dfc00815 stw ra,32(sp) - 7338: ddc00715 stw r23,28(sp) - 733c: dd000415 stw r20,16(sp) - 7340: dc800215 stw r18,8(sp) - 7344: dc400115 stw r17,4(sp) - 7348: dc000015 stw r16,0(sp) - 734c: 202b883a mov r21,r4 - 7350: 282d883a mov r22,r5 - 7354: 00067a80 call 67a8 <__sfp_lock_acquire> - 7358: 98002126 beq r19,zero,73e0 <_fwalk_reent+0xc0> - 735c: 002f883a mov r23,zero - 7360: 9c800117 ldw r18,4(r19) - 7364: 9c000217 ldw r16,8(r19) - 7368: 90bfffc4 addi r2,r18,-1 - 736c: 10000d16 blt r2,zero,73a4 <_fwalk_reent+0x84> - 7370: 0023883a mov r17,zero - 7374: 053fffc4 movi r20,-1 - 7378: 8080030f ldh r2,12(r16) - 737c: 8c400044 addi r17,r17,1 - 7380: 10000626 beq r2,zero,739c <_fwalk_reent+0x7c> - 7384: 8080038f ldh r2,14(r16) - 7388: 800b883a mov r5,r16 - 738c: a809883a mov r4,r21 - 7390: 15000226 beq r2,r20,739c <_fwalk_reent+0x7c> - 7394: b03ee83a callr r22 - 7398: b8aeb03a or r23,r23,r2 - 739c: 84001704 addi r16,r16,92 - 73a0: 947ff51e bne r18,r17,7378 <_fwalk_reent+0x58> - 73a4: 9cc00017 ldw r19,0(r19) - 73a8: 983fed1e bne r19,zero,7360 <_fwalk_reent+0x40> - 73ac: 00067ac0 call 67ac <__sfp_lock_release> - 73b0: b805883a mov r2,r23 - 73b4: dfc00817 ldw ra,32(sp) - 73b8: ddc00717 ldw r23,28(sp) - 73bc: dd800617 ldw r22,24(sp) - 73c0: dd400517 ldw r21,20(sp) - 73c4: dd000417 ldw r20,16(sp) - 73c8: dcc00317 ldw r19,12(sp) - 73cc: dc800217 ldw r18,8(sp) - 73d0: dc400117 ldw r17,4(sp) - 73d4: dc000017 ldw r16,0(sp) - 73d8: dec00904 addi sp,sp,36 - 73dc: f800283a ret - 73e0: 002f883a mov r23,zero - 73e4: 003ff106 br 73ac <_fwalk_reent+0x8c> - -000073e8 <_fwalk>: - 73e8: defff804 addi sp,sp,-32 - 73ec: dcc00315 stw r19,12(sp) - 73f0: 24c0b804 addi r19,r4,736 - 73f4: dd400515 stw r21,20(sp) - 73f8: dfc00715 stw ra,28(sp) - 73fc: dd800615 stw r22,24(sp) - 7400: dd000415 stw r20,16(sp) - 7404: dc800215 stw r18,8(sp) - 7408: dc400115 stw r17,4(sp) - 740c: dc000015 stw r16,0(sp) - 7410: 282b883a mov r21,r5 - 7414: 00067a80 call 67a8 <__sfp_lock_acquire> - 7418: 98001f26 beq r19,zero,7498 <_fwalk+0xb0> - 741c: 002d883a mov r22,zero - 7420: 9c800117 ldw r18,4(r19) - 7424: 9c000217 ldw r16,8(r19) - 7428: 90bfffc4 addi r2,r18,-1 - 742c: 10000c16 blt r2,zero,7460 <_fwalk+0x78> - 7430: 0023883a mov r17,zero - 7434: 053fffc4 movi r20,-1 - 7438: 8080030f ldh r2,12(r16) - 743c: 8c400044 addi r17,r17,1 - 7440: 10000526 beq r2,zero,7458 <_fwalk+0x70> - 7444: 8080038f ldh r2,14(r16) - 7448: 8009883a mov r4,r16 - 744c: 15000226 beq r2,r20,7458 <_fwalk+0x70> - 7450: a83ee83a callr r21 - 7454: b0acb03a or r22,r22,r2 - 7458: 84001704 addi r16,r16,92 - 745c: 947ff61e bne r18,r17,7438 <_fwalk+0x50> - 7460: 9cc00017 ldw r19,0(r19) - 7464: 983fee1e bne r19,zero,7420 <_fwalk+0x38> - 7468: 00067ac0 call 67ac <__sfp_lock_release> - 746c: b005883a mov r2,r22 - 7470: dfc00717 ldw ra,28(sp) - 7474: dd800617 ldw r22,24(sp) - 7478: dd400517 ldw r21,20(sp) - 747c: dd000417 ldw r20,16(sp) - 7480: dcc00317 ldw r19,12(sp) - 7484: dc800217 ldw r18,8(sp) - 7488: dc400117 ldw r17,4(sp) - 748c: dc000017 ldw r16,0(sp) - 7490: dec00804 addi sp,sp,32 - 7494: f800283a ret - 7498: 002d883a mov r22,zero - 749c: 003ff206 br 7468 <_fwalk+0x80> - -000074a0 <__locale_charset>: - 74a0: d0a00517 ldw r2,-32748(gp) - 74a4: f800283a ret - -000074a8 <_localeconv_r>: - 74a8: 00800074 movhi r2,1 - 74ac: 1080c504 addi r2,r2,788 - 74b0: f800283a ret - -000074b4 : - 74b4: 00800074 movhi r2,1 - 74b8: 10884004 addi r2,r2,8448 - 74bc: 11000017 ldw r4,0(r2) - 74c0: 00074a81 jmpi 74a8 <_localeconv_r> - -000074c4 <_setlocale_r>: - 74c4: defffc04 addi sp,sp,-16 - 74c8: 00c00074 movhi r3,1 - 74cc: 18c0c004 addi r3,r3,768 - 74d0: dc800215 stw r18,8(sp) - 74d4: dc400115 stw r17,4(sp) - 74d8: dc000015 stw r16,0(sp) - 74dc: 2023883a mov r17,r4 - 74e0: 2825883a mov r18,r5 - 74e4: dfc00315 stw ra,12(sp) - 74e8: 3021883a mov r16,r6 - 74ec: 3009883a mov r4,r6 - 74f0: 180b883a mov r5,r3 - 74f4: 30000926 beq r6,zero,751c <_setlocale_r+0x58> - 74f8: 00099e00 call 99e0 - 74fc: 8009883a mov r4,r16 - 7500: 01400074 movhi r5,1 - 7504: 2940ab04 addi r5,r5,684 - 7508: 10000b1e bne r2,zero,7538 <_setlocale_r+0x74> - 750c: 8c000d15 stw r16,52(r17) - 7510: 8c800c15 stw r18,48(r17) - 7514: 00c00074 movhi r3,1 - 7518: 18c0c004 addi r3,r3,768 - 751c: 1805883a mov r2,r3 - 7520: dfc00317 ldw ra,12(sp) - 7524: dc800217 ldw r18,8(sp) - 7528: dc400117 ldw r17,4(sp) - 752c: dc000017 ldw r16,0(sp) - 7530: dec00404 addi sp,sp,16 - 7534: f800283a ret - 7538: 00099e00 call 99e0 - 753c: 0007883a mov r3,zero - 7540: 103ff226 beq r2,zero,750c <_setlocale_r+0x48> - 7544: 003ff506 br 751c <_setlocale_r+0x58> - -00007548 : - 7548: 01800074 movhi r6,1 - 754c: 31884004 addi r6,r6,8448 - 7550: 2007883a mov r3,r4 - 7554: 31000017 ldw r4,0(r6) - 7558: 280d883a mov r6,r5 - 755c: 180b883a mov r5,r3 - 7560: 00074c41 jmpi 74c4 <_setlocale_r> - -00007564 <__smakebuf_r>: - 7564: 2880030b ldhu r2,12(r5) - 7568: deffed04 addi sp,sp,-76 - 756c: dc401015 stw r17,64(sp) - 7570: 1080008c andi r2,r2,2 - 7574: dc000f15 stw r16,60(sp) - 7578: dfc01215 stw ra,72(sp) - 757c: dc801115 stw r18,68(sp) - 7580: 2821883a mov r16,r5 - 7584: 2023883a mov r17,r4 - 7588: 10000b26 beq r2,zero,75b8 <__smakebuf_r+0x54> - 758c: 28c010c4 addi r3,r5,67 - 7590: 00800044 movi r2,1 - 7594: 28800515 stw r2,20(r5) - 7598: 28c00415 stw r3,16(r5) - 759c: 28c00015 stw r3,0(r5) - 75a0: dfc01217 ldw ra,72(sp) - 75a4: dc801117 ldw r18,68(sp) - 75a8: dc401017 ldw r17,64(sp) - 75ac: dc000f17 ldw r16,60(sp) - 75b0: dec01304 addi sp,sp,76 - 75b4: f800283a ret - 75b8: 2940038f ldh r5,14(r5) - 75bc: 28002116 blt r5,zero,7644 <__smakebuf_r+0xe0> - 75c0: d80d883a mov r6,sp - 75c4: 0009d700 call 9d70 <_fstat_r> - 75c8: 10001e16 blt r2,zero,7644 <__smakebuf_r+0xe0> - 75cc: d8800117 ldw r2,4(sp) - 75d0: 00e00014 movui r3,32768 - 75d4: 113c000c andi r4,r2,61440 - 75d8: 20c03126 beq r4,r3,76a0 <__smakebuf_r+0x13c> - 75dc: 8080030b ldhu r2,12(r16) - 75e0: 00c80004 movi r3,8192 - 75e4: 10820014 ori r2,r2,2048 - 75e8: 8080030d sth r2,12(r16) - 75ec: 20c01e26 beq r4,r3,7668 <__smakebuf_r+0x104> - 75f0: 04810004 movi r18,1024 - 75f4: 8809883a mov r4,r17 - 75f8: 900b883a mov r5,r18 - 75fc: 00076f80 call 76f8 <_malloc_r> - 7600: 1009883a mov r4,r2 - 7604: 10003126 beq r2,zero,76cc <__smakebuf_r+0x168> - 7608: 80c0030b ldhu r3,12(r16) - 760c: 00800034 movhi r2,0 - 7610: 109a2704 addi r2,r2,26780 - 7614: 88800f15 stw r2,60(r17) - 7618: 18c02014 ori r3,r3,128 - 761c: 84800515 stw r18,20(r16) - 7620: 80c0030d sth r3,12(r16) - 7624: 81000415 stw r4,16(r16) - 7628: 81000015 stw r4,0(r16) - 762c: dfc01217 ldw ra,72(sp) - 7630: dc801117 ldw r18,68(sp) - 7634: dc401017 ldw r17,64(sp) - 7638: dc000f17 ldw r16,60(sp) - 763c: dec01304 addi sp,sp,76 - 7640: f800283a ret - 7644: 80c0030b ldhu r3,12(r16) - 7648: 1880200c andi r2,r3,128 - 764c: 10000426 beq r2,zero,7660 <__smakebuf_r+0xfc> - 7650: 04801004 movi r18,64 - 7654: 18820014 ori r2,r3,2048 - 7658: 8080030d sth r2,12(r16) - 765c: 003fe506 br 75f4 <__smakebuf_r+0x90> - 7660: 04810004 movi r18,1024 - 7664: 003ffb06 br 7654 <__smakebuf_r+0xf0> - 7668: 8140038f ldh r5,14(r16) - 766c: 8809883a mov r4,r17 - 7670: 0009de40 call 9de4 <_isatty_r> - 7674: 103fde26 beq r2,zero,75f0 <__smakebuf_r+0x8c> - 7678: 8080030b ldhu r2,12(r16) - 767c: 80c010c4 addi r3,r16,67 - 7680: 04810004 movi r18,1024 - 7684: 10800054 ori r2,r2,1 - 7688: 8080030d sth r2,12(r16) - 768c: 00800044 movi r2,1 - 7690: 80c00415 stw r3,16(r16) - 7694: 80800515 stw r2,20(r16) - 7698: 80c00015 stw r3,0(r16) - 769c: 003fd506 br 75f4 <__smakebuf_r+0x90> - 76a0: 80c00a17 ldw r3,40(r16) - 76a4: 00800074 movhi r2,1 - 76a8: 10a62704 addi r2,r2,-26468 - 76ac: 18bfcb1e bne r3,r2,75dc <__smakebuf_r+0x78> - 76b0: 8080030b ldhu r2,12(r16) - 76b4: 00c10004 movi r3,1024 - 76b8: 1825883a mov r18,r3 - 76bc: 10c4b03a or r2,r2,r3 - 76c0: 8080030d sth r2,12(r16) - 76c4: 80c01315 stw r3,76(r16) - 76c8: 003fca06 br 75f4 <__smakebuf_r+0x90> - 76cc: 8100030b ldhu r4,12(r16) - 76d0: 2080800c andi r2,r4,512 - 76d4: 103fb21e bne r2,zero,75a0 <__smakebuf_r+0x3c> - 76d8: 80c010c4 addi r3,r16,67 - 76dc: 21000094 ori r4,r4,2 - 76e0: 00800044 movi r2,1 - 76e4: 80800515 stw r2,20(r16) - 76e8: 8100030d sth r4,12(r16) - 76ec: 80c00415 stw r3,16(r16) - 76f0: 80c00015 stw r3,0(r16) - 76f4: 003faa06 br 75a0 <__smakebuf_r+0x3c> - -000076f8 <_malloc_r>: - 76f8: defff604 addi sp,sp,-40 - 76fc: 28c002c4 addi r3,r5,11 - 7700: 00800584 movi r2,22 - 7704: dc800215 stw r18,8(sp) - 7708: dfc00915 stw ra,36(sp) - 770c: df000815 stw fp,32(sp) - 7710: ddc00715 stw r23,28(sp) - 7714: dd800615 stw r22,24(sp) - 7718: dd400515 stw r21,20(sp) - 771c: dd000415 stw r20,16(sp) - 7720: dcc00315 stw r19,12(sp) - 7724: dc400115 stw r17,4(sp) - 7728: dc000015 stw r16,0(sp) - 772c: 2025883a mov r18,r4 - 7730: 10c01236 bltu r2,r3,777c <_malloc_r+0x84> - 7734: 04400404 movi r17,16 - 7738: 8940142e bgeu r17,r5,778c <_malloc_r+0x94> - 773c: 00800304 movi r2,12 - 7740: 0007883a mov r3,zero - 7744: 90800015 stw r2,0(r18) - 7748: 1805883a mov r2,r3 - 774c: dfc00917 ldw ra,36(sp) - 7750: df000817 ldw fp,32(sp) - 7754: ddc00717 ldw r23,28(sp) - 7758: dd800617 ldw r22,24(sp) - 775c: dd400517 ldw r21,20(sp) - 7760: dd000417 ldw r20,16(sp) - 7764: dcc00317 ldw r19,12(sp) - 7768: dc800217 ldw r18,8(sp) - 776c: dc400117 ldw r17,4(sp) - 7770: dc000017 ldw r16,0(sp) - 7774: dec00a04 addi sp,sp,40 - 7778: f800283a ret - 777c: 00bffe04 movi r2,-8 - 7780: 18a2703a and r17,r3,r2 - 7784: 883fed16 blt r17,zero,773c <_malloc_r+0x44> - 7788: 897fec36 bltu r17,r5,773c <_malloc_r+0x44> - 778c: 9009883a mov r4,r18 - 7790: 000ca880 call ca88 <__malloc_lock> - 7794: 00807dc4 movi r2,503 - 7798: 14402b2e bgeu r2,r17,7848 <_malloc_r+0x150> - 779c: 8806d27a srli r3,r17,9 - 77a0: 18003f1e bne r3,zero,78a0 <_malloc_r+0x1a8> - 77a4: 880cd0fa srli r6,r17,3 - 77a8: 300490fa slli r2,r6,3 - 77ac: 02c00074 movhi r11,1 - 77b0: 5ac27204 addi r11,r11,2504 - 77b4: 12cb883a add r5,r2,r11 - 77b8: 2c000317 ldw r16,12(r5) - 77bc: 580f883a mov r7,r11 - 77c0: 2c00041e bne r5,r16,77d4 <_malloc_r+0xdc> - 77c4: 00000a06 br 77f0 <_malloc_r+0xf8> - 77c8: 1800860e bge r3,zero,79e4 <_malloc_r+0x2ec> - 77cc: 84000317 ldw r16,12(r16) - 77d0: 2c000726 beq r5,r16,77f0 <_malloc_r+0xf8> - 77d4: 80800117 ldw r2,4(r16) - 77d8: 00ffff04 movi r3,-4 - 77dc: 10c8703a and r4,r2,r3 - 77e0: 2447c83a sub r3,r4,r17 - 77e4: 008003c4 movi r2,15 - 77e8: 10fff70e bge r2,r3,77c8 <_malloc_r+0xd0> - 77ec: 31bfffc4 addi r6,r6,-1 - 77f0: 32400044 addi r9,r6,1 - 77f4: 02800074 movhi r10,1 - 77f8: 52827404 addi r10,r10,2512 - 77fc: 54000217 ldw r16,8(r10) - 7800: 8280a026 beq r16,r10,7a84 <_malloc_r+0x38c> - 7804: 80800117 ldw r2,4(r16) - 7808: 00ffff04 movi r3,-4 - 780c: 10ca703a and r5,r2,r3 - 7810: 2c4dc83a sub r6,r5,r17 - 7814: 008003c4 movi r2,15 - 7818: 11808316 blt r2,r6,7a28 <_malloc_r+0x330> - 781c: 52800315 stw r10,12(r10) - 7820: 52800215 stw r10,8(r10) - 7824: 30002916 blt r6,zero,78cc <_malloc_r+0x1d4> - 7828: 8147883a add r3,r16,r5 - 782c: 18800117 ldw r2,4(r3) - 7830: 9009883a mov r4,r18 - 7834: 10800054 ori r2,r2,1 - 7838: 18800115 stw r2,4(r3) - 783c: 000caa80 call caa8 <__malloc_unlock> - 7840: 80c00204 addi r3,r16,8 - 7844: 003fc006 br 7748 <_malloc_r+0x50> - 7848: 02c00074 movhi r11,1 - 784c: 5ac27204 addi r11,r11,2504 - 7850: 8ac5883a add r2,r17,r11 - 7854: 14000317 ldw r16,12(r2) - 7858: 580f883a mov r7,r11 - 785c: 8806d0fa srli r3,r17,3 - 7860: 14006c26 beq r2,r16,7a14 <_malloc_r+0x31c> - 7864: 80c00117 ldw r3,4(r16) - 7868: 00bfff04 movi r2,-4 - 786c: 81800317 ldw r6,12(r16) - 7870: 1886703a and r3,r3,r2 - 7874: 80c7883a add r3,r16,r3 - 7878: 18800117 ldw r2,4(r3) - 787c: 81400217 ldw r5,8(r16) - 7880: 9009883a mov r4,r18 - 7884: 10800054 ori r2,r2,1 - 7888: 18800115 stw r2,4(r3) - 788c: 31400215 stw r5,8(r6) - 7890: 29800315 stw r6,12(r5) - 7894: 000caa80 call caa8 <__malloc_unlock> - 7898: 80c00204 addi r3,r16,8 - 789c: 003faa06 br 7748 <_malloc_r+0x50> - 78a0: 00800104 movi r2,4 - 78a4: 10c0052e bgeu r2,r3,78bc <_malloc_r+0x1c4> - 78a8: 00800504 movi r2,20 - 78ac: 10c07836 bltu r2,r3,7a90 <_malloc_r+0x398> - 78b0: 198016c4 addi r6,r3,91 - 78b4: 300490fa slli r2,r6,3 - 78b8: 003fbc06 br 77ac <_malloc_r+0xb4> - 78bc: 8804d1ba srli r2,r17,6 - 78c0: 11800e04 addi r6,r2,56 - 78c4: 300490fa slli r2,r6,3 - 78c8: 003fb806 br 77ac <_malloc_r+0xb4> - 78cc: 00807fc4 movi r2,511 - 78d0: 1140bb36 bltu r2,r5,7bc0 <_malloc_r+0x4c8> - 78d4: 2806d0fa srli r3,r5,3 - 78d8: 573ffe04 addi fp,r10,-8 - 78dc: 00800044 movi r2,1 - 78e0: 180890fa slli r4,r3,3 - 78e4: 1807d0ba srai r3,r3,2 - 78e8: e1c00117 ldw r7,4(fp) - 78ec: 5909883a add r4,r11,r4 - 78f0: 21400217 ldw r5,8(r4) - 78f4: 10c4983a sll r2,r2,r3 - 78f8: 81000315 stw r4,12(r16) - 78fc: 81400215 stw r5,8(r16) - 7900: 388eb03a or r7,r7,r2 - 7904: 2c000315 stw r16,12(r5) - 7908: 24000215 stw r16,8(r4) - 790c: e1c00115 stw r7,4(fp) - 7910: 4807883a mov r3,r9 - 7914: 4800cd16 blt r9,zero,7c4c <_malloc_r+0x554> - 7918: 1807d0ba srai r3,r3,2 - 791c: 00800044 movi r2,1 - 7920: 10c8983a sll r4,r2,r3 - 7924: 39004436 bltu r7,r4,7a38 <_malloc_r+0x340> - 7928: 21c4703a and r2,r4,r7 - 792c: 10000a1e bne r2,zero,7958 <_malloc_r+0x260> - 7930: 2109883a add r4,r4,r4 - 7934: 00bfff04 movi r2,-4 - 7938: 4884703a and r2,r9,r2 - 793c: 3906703a and r3,r7,r4 - 7940: 12400104 addi r9,r2,4 - 7944: 1800041e bne r3,zero,7958 <_malloc_r+0x260> - 7948: 2109883a add r4,r4,r4 - 794c: 3904703a and r2,r7,r4 - 7950: 4a400104 addi r9,r9,4 - 7954: 103ffc26 beq r2,zero,7948 <_malloc_r+0x250> - 7958: 480490fa slli r2,r9,3 - 795c: 4819883a mov r12,r9 - 7960: 023fff04 movi r8,-4 - 7964: 589b883a add r13,r11,r2 - 7968: 6807883a mov r3,r13 - 796c: 014003c4 movi r5,15 - 7970: 1c000317 ldw r16,12(r3) - 7974: 1c00041e bne r3,r16,7988 <_malloc_r+0x290> - 7978: 0000a706 br 7c18 <_malloc_r+0x520> - 797c: 3000ab0e bge r6,zero,7c2c <_malloc_r+0x534> - 7980: 84000317 ldw r16,12(r16) - 7984: 1c00a426 beq r3,r16,7c18 <_malloc_r+0x520> - 7988: 80800117 ldw r2,4(r16) - 798c: 1204703a and r2,r2,r8 - 7990: 144dc83a sub r6,r2,r17 - 7994: 29bff90e bge r5,r6,797c <_malloc_r+0x284> - 7998: 81000317 ldw r4,12(r16) - 799c: 80c00217 ldw r3,8(r16) - 79a0: 89400054 ori r5,r17,1 - 79a4: 8445883a add r2,r16,r17 - 79a8: 20c00215 stw r3,8(r4) - 79ac: 19000315 stw r4,12(r3) - 79b0: 81400115 stw r5,4(r16) - 79b4: 1187883a add r3,r2,r6 - 79b8: 31000054 ori r4,r6,1 - 79bc: 50800315 stw r2,12(r10) - 79c0: 50800215 stw r2,8(r10) - 79c4: 19800015 stw r6,0(r3) - 79c8: 11000115 stw r4,4(r2) - 79cc: 12800215 stw r10,8(r2) - 79d0: 12800315 stw r10,12(r2) - 79d4: 9009883a mov r4,r18 - 79d8: 000caa80 call caa8 <__malloc_unlock> - 79dc: 80c00204 addi r3,r16,8 - 79e0: 003f5906 br 7748 <_malloc_r+0x50> - 79e4: 8109883a add r4,r16,r4 - 79e8: 20800117 ldw r2,4(r4) - 79ec: 80c00217 ldw r3,8(r16) - 79f0: 81400317 ldw r5,12(r16) - 79f4: 10800054 ori r2,r2,1 - 79f8: 20800115 stw r2,4(r4) - 79fc: 28c00215 stw r3,8(r5) - 7a00: 19400315 stw r5,12(r3) - 7a04: 9009883a mov r4,r18 - 7a08: 000caa80 call caa8 <__malloc_unlock> - 7a0c: 80c00204 addi r3,r16,8 - 7a10: 003f4d06 br 7748 <_malloc_r+0x50> - 7a14: 80800204 addi r2,r16,8 - 7a18: 14000317 ldw r16,12(r2) - 7a1c: 143f911e bne r2,r16,7864 <_malloc_r+0x16c> - 7a20: 1a400084 addi r9,r3,2 - 7a24: 003f7306 br 77f4 <_malloc_r+0xfc> - 7a28: 88c00054 ori r3,r17,1 - 7a2c: 8445883a add r2,r16,r17 - 7a30: 80c00115 stw r3,4(r16) - 7a34: 003fdf06 br 79b4 <_malloc_r+0x2bc> - 7a38: e4000217 ldw r16,8(fp) - 7a3c: 00bfff04 movi r2,-4 - 7a40: 80c00117 ldw r3,4(r16) - 7a44: 802d883a mov r22,r16 - 7a48: 18aa703a and r21,r3,r2 - 7a4c: ac401636 bltu r21,r17,7aa8 <_malloc_r+0x3b0> - 7a50: ac49c83a sub r4,r21,r17 - 7a54: 008003c4 movi r2,15 - 7a58: 1100130e bge r2,r4,7aa8 <_malloc_r+0x3b0> - 7a5c: 88800054 ori r2,r17,1 - 7a60: 8447883a add r3,r16,r17 - 7a64: 80800115 stw r2,4(r16) - 7a68: 20800054 ori r2,r4,1 - 7a6c: 18800115 stw r2,4(r3) - 7a70: e0c00215 stw r3,8(fp) - 7a74: 9009883a mov r4,r18 - 7a78: 000caa80 call caa8 <__malloc_unlock> - 7a7c: 80c00204 addi r3,r16,8 - 7a80: 003f3106 br 7748 <_malloc_r+0x50> - 7a84: 39c00117 ldw r7,4(r7) - 7a88: 573ffe04 addi fp,r10,-8 - 7a8c: 003fa006 br 7910 <_malloc_r+0x218> - 7a90: 00801504 movi r2,84 - 7a94: 10c06736 bltu r2,r3,7c34 <_malloc_r+0x53c> - 7a98: 8804d33a srli r2,r17,12 - 7a9c: 11801b84 addi r6,r2,110 - 7aa0: 300490fa slli r2,r6,3 - 7aa4: 003f4106 br 77ac <_malloc_r+0xb4> - 7aa8: d0a6fd17 ldw r2,-25612(gp) - 7aac: d0e00717 ldw r3,-32740(gp) - 7ab0: 053fffc4 movi r20,-1 - 7ab4: 10800404 addi r2,r2,16 - 7ab8: 88a7883a add r19,r17,r2 - 7abc: 1d000326 beq r3,r20,7acc <_malloc_r+0x3d4> - 7ac0: 98c3ffc4 addi r3,r19,4095 - 7ac4: 00bc0004 movi r2,-4096 - 7ac8: 18a6703a and r19,r3,r2 - 7acc: 9009883a mov r4,r18 - 7ad0: 980b883a mov r5,r19 - 7ad4: 00098240 call 9824 <_sbrk_r> - 7ad8: 1009883a mov r4,r2 - 7adc: 15000426 beq r2,r20,7af0 <_malloc_r+0x3f8> - 7ae0: 854b883a add r5,r16,r21 - 7ae4: 1029883a mov r20,r2 - 7ae8: 11405a2e bgeu r2,r5,7c54 <_malloc_r+0x55c> - 7aec: 87000c26 beq r16,fp,7b20 <_malloc_r+0x428> - 7af0: e4000217 ldw r16,8(fp) - 7af4: 80c00117 ldw r3,4(r16) - 7af8: 00bfff04 movi r2,-4 - 7afc: 1884703a and r2,r3,r2 - 7b00: 14400336 bltu r2,r17,7b10 <_malloc_r+0x418> - 7b04: 1449c83a sub r4,r2,r17 - 7b08: 008003c4 movi r2,15 - 7b0c: 113fd316 blt r2,r4,7a5c <_malloc_r+0x364> - 7b10: 9009883a mov r4,r18 - 7b14: 000caa80 call caa8 <__malloc_unlock> - 7b18: 0007883a mov r3,zero - 7b1c: 003f0a06 br 7748 <_malloc_r+0x50> - 7b20: 05c00074 movhi r23,1 - 7b24: bdd08504 addi r23,r23,16916 - 7b28: b8800017 ldw r2,0(r23) - 7b2c: 988d883a add r6,r19,r2 - 7b30: b9800015 stw r6,0(r23) - 7b34: d0e00717 ldw r3,-32740(gp) - 7b38: 00bfffc4 movi r2,-1 - 7b3c: 18808e26 beq r3,r2,7d78 <_malloc_r+0x680> - 7b40: 2145c83a sub r2,r4,r5 - 7b44: 3085883a add r2,r6,r2 - 7b48: b8800015 stw r2,0(r23) - 7b4c: 20c001cc andi r3,r4,7 - 7b50: 18005f1e bne r3,zero,7cd0 <_malloc_r+0x5d8> - 7b54: 000b883a mov r5,zero - 7b58: a4c5883a add r2,r20,r19 - 7b5c: 1083ffcc andi r2,r2,4095 - 7b60: 00c40004 movi r3,4096 - 7b64: 1887c83a sub r3,r3,r2 - 7b68: 28e7883a add r19,r5,r3 - 7b6c: 9009883a mov r4,r18 - 7b70: 980b883a mov r5,r19 - 7b74: 00098240 call 9824 <_sbrk_r> - 7b78: 1007883a mov r3,r2 - 7b7c: 00bfffc4 movi r2,-1 - 7b80: 18807a26 beq r3,r2,7d6c <_malloc_r+0x674> - 7b84: 1d05c83a sub r2,r3,r20 - 7b88: 9885883a add r2,r19,r2 - 7b8c: 10c00054 ori r3,r2,1 - 7b90: b8800017 ldw r2,0(r23) - 7b94: a021883a mov r16,r20 - 7b98: a0c00115 stw r3,4(r20) - 7b9c: 9885883a add r2,r19,r2 - 7ba0: b8800015 stw r2,0(r23) - 7ba4: e5000215 stw r20,8(fp) - 7ba8: b7003626 beq r22,fp,7c84 <_malloc_r+0x58c> - 7bac: 018003c4 movi r6,15 - 7bb0: 35404b36 bltu r6,r21,7ce0 <_malloc_r+0x5e8> - 7bb4: 00800044 movi r2,1 - 7bb8: a0800115 stw r2,4(r20) - 7bbc: 003fcd06 br 7af4 <_malloc_r+0x3fc> - 7bc0: 2808d27a srli r4,r5,9 - 7bc4: 2000371e bne r4,zero,7ca4 <_malloc_r+0x5ac> - 7bc8: 2808d0fa srli r4,r5,3 - 7bcc: 200690fa slli r3,r4,3 - 7bd0: 1ad1883a add r8,r3,r11 - 7bd4: 41800217 ldw r6,8(r8) - 7bd8: 41805b26 beq r8,r6,7d48 <_malloc_r+0x650> - 7bdc: 30800117 ldw r2,4(r6) - 7be0: 00ffff04 movi r3,-4 - 7be4: 10c4703a and r2,r2,r3 - 7be8: 2880022e bgeu r5,r2,7bf4 <_malloc_r+0x4fc> - 7bec: 31800217 ldw r6,8(r6) - 7bf0: 41bffa1e bne r8,r6,7bdc <_malloc_r+0x4e4> - 7bf4: 32000317 ldw r8,12(r6) - 7bf8: 39c00117 ldw r7,4(r7) - 7bfc: 82000315 stw r8,12(r16) - 7c00: 81800215 stw r6,8(r16) - 7c04: 07000074 movhi fp,1 - 7c08: e7027204 addi fp,fp,2504 - 7c0c: 34000315 stw r16,12(r6) - 7c10: 44000215 stw r16,8(r8) - 7c14: 003f3e06 br 7910 <_malloc_r+0x218> - 7c18: 63000044 addi r12,r12,1 - 7c1c: 608000cc andi r2,r12,3 - 7c20: 10005d26 beq r2,zero,7d98 <_malloc_r+0x6a0> - 7c24: 18c00204 addi r3,r3,8 - 7c28: 003f5106 br 7970 <_malloc_r+0x278> - 7c2c: 8089883a add r4,r16,r2 - 7c30: 003f6d06 br 79e8 <_malloc_r+0x2f0> - 7c34: 00805504 movi r2,340 - 7c38: 10c02036 bltu r2,r3,7cbc <_malloc_r+0x5c4> - 7c3c: 8804d3fa srli r2,r17,15 - 7c40: 11801dc4 addi r6,r2,119 - 7c44: 300490fa slli r2,r6,3 - 7c48: 003ed806 br 77ac <_malloc_r+0xb4> - 7c4c: 48c000c4 addi r3,r9,3 - 7c50: 003f3106 br 7918 <_malloc_r+0x220> - 7c54: 05c00074 movhi r23,1 - 7c58: bdd08504 addi r23,r23,16916 - 7c5c: b8800017 ldw r2,0(r23) - 7c60: 988d883a add r6,r19,r2 - 7c64: b9800015 stw r6,0(r23) - 7c68: 293fb21e bne r5,r4,7b34 <_malloc_r+0x43c> - 7c6c: 2083ffcc andi r2,r4,4095 - 7c70: 103fb01e bne r2,zero,7b34 <_malloc_r+0x43c> - 7c74: e4000217 ldw r16,8(fp) - 7c78: 9d45883a add r2,r19,r21 - 7c7c: 10800054 ori r2,r2,1 - 7c80: 80800115 stw r2,4(r16) - 7c84: b8c00017 ldw r3,0(r23) - 7c88: d0a6fe17 ldw r2,-25608(gp) - 7c8c: 10c0012e bgeu r2,r3,7c94 <_malloc_r+0x59c> - 7c90: d0e6fe15 stw r3,-25608(gp) - 7c94: d0a6ff17 ldw r2,-25604(gp) - 7c98: 10ff962e bgeu r2,r3,7af4 <_malloc_r+0x3fc> - 7c9c: d0e6ff15 stw r3,-25604(gp) - 7ca0: 003f9406 br 7af4 <_malloc_r+0x3fc> - 7ca4: 00800104 movi r2,4 - 7ca8: 11001e36 bltu r2,r4,7d24 <_malloc_r+0x62c> - 7cac: 2804d1ba srli r2,r5,6 - 7cb0: 11000e04 addi r4,r2,56 - 7cb4: 200690fa slli r3,r4,3 - 7cb8: 003fc506 br 7bd0 <_malloc_r+0x4d8> - 7cbc: 00815504 movi r2,1364 - 7cc0: 10c01d2e bgeu r2,r3,7d38 <_malloc_r+0x640> - 7cc4: 01801f84 movi r6,126 - 7cc8: 0080fc04 movi r2,1008 - 7ccc: 003eb706 br 77ac <_malloc_r+0xb4> - 7cd0: 00800204 movi r2,8 - 7cd4: 10cbc83a sub r5,r2,r3 - 7cd8: 2169883a add r20,r4,r5 - 7cdc: 003f9e06 br 7b58 <_malloc_r+0x460> - 7ce0: 00bffe04 movi r2,-8 - 7ce4: a93ffd04 addi r4,r21,-12 - 7ce8: 2088703a and r4,r4,r2 - 7cec: b10b883a add r5,r22,r4 - 7cf0: 00c00144 movi r3,5 - 7cf4: 28c00215 stw r3,8(r5) - 7cf8: 28c00115 stw r3,4(r5) - 7cfc: b0800117 ldw r2,4(r22) - 7d00: 1080004c andi r2,r2,1 - 7d04: 2084b03a or r2,r4,r2 - 7d08: b0800115 stw r2,4(r22) - 7d0c: 313fdd2e bgeu r6,r4,7c84 <_malloc_r+0x58c> - 7d10: b1400204 addi r5,r22,8 - 7d14: 9009883a mov r4,r18 - 7d18: 0006b700 call 6b70 <_free_r> - 7d1c: e4000217 ldw r16,8(fp) - 7d20: 003fd806 br 7c84 <_malloc_r+0x58c> - 7d24: 00800504 movi r2,20 - 7d28: 11001536 bltu r2,r4,7d80 <_malloc_r+0x688> - 7d2c: 210016c4 addi r4,r4,91 - 7d30: 200690fa slli r3,r4,3 - 7d34: 003fa606 br 7bd0 <_malloc_r+0x4d8> - 7d38: 8804d4ba srli r2,r17,18 - 7d3c: 11801f04 addi r6,r2,124 - 7d40: 300490fa slli r2,r6,3 - 7d44: 003e9906 br 77ac <_malloc_r+0xb4> - 7d48: 2009d0ba srai r4,r4,2 - 7d4c: 01400074 movhi r5,1 - 7d50: 29427204 addi r5,r5,2504 - 7d54: 00c00044 movi r3,1 - 7d58: 28800117 ldw r2,4(r5) - 7d5c: 1906983a sll r3,r3,r4 - 7d60: 10c4b03a or r2,r2,r3 - 7d64: 28800115 stw r2,4(r5) - 7d68: 003fa306 br 7bf8 <_malloc_r+0x500> - 7d6c: 0027883a mov r19,zero - 7d70: 00c00044 movi r3,1 - 7d74: 003f8606 br 7b90 <_malloc_r+0x498> - 7d78: d1200715 stw r4,-32740(gp) - 7d7c: 003f7306 br 7b4c <_malloc_r+0x454> - 7d80: 00801504 movi r2,84 - 7d84: 11001936 bltu r2,r4,7dec <_malloc_r+0x6f4> - 7d88: 2804d33a srli r2,r5,12 - 7d8c: 11001b84 addi r4,r2,110 - 7d90: 200690fa slli r3,r4,3 - 7d94: 003f8e06 br 7bd0 <_malloc_r+0x4d8> - 7d98: 480b883a mov r5,r9 - 7d9c: 6807883a mov r3,r13 - 7da0: 288000cc andi r2,r5,3 - 7da4: 18fffe04 addi r3,r3,-8 - 7da8: 297fffc4 addi r5,r5,-1 - 7dac: 10001526 beq r2,zero,7e04 <_malloc_r+0x70c> - 7db0: 18800217 ldw r2,8(r3) - 7db4: 10fffa26 beq r2,r3,7da0 <_malloc_r+0x6a8> - 7db8: 2109883a add r4,r4,r4 - 7dbc: 393f1e36 bltu r7,r4,7a38 <_malloc_r+0x340> - 7dc0: 203f1d26 beq r4,zero,7a38 <_malloc_r+0x340> - 7dc4: 21c4703a and r2,r4,r7 - 7dc8: 10000226 beq r2,zero,7dd4 <_malloc_r+0x6dc> - 7dcc: 6013883a mov r9,r12 - 7dd0: 003ee106 br 7958 <_malloc_r+0x260> - 7dd4: 2109883a add r4,r4,r4 - 7dd8: 3904703a and r2,r7,r4 - 7ddc: 63000104 addi r12,r12,4 - 7de0: 103ffc26 beq r2,zero,7dd4 <_malloc_r+0x6dc> - 7de4: 6013883a mov r9,r12 - 7de8: 003edb06 br 7958 <_malloc_r+0x260> - 7dec: 00805504 movi r2,340 - 7df0: 11000836 bltu r2,r4,7e14 <_malloc_r+0x71c> - 7df4: 2804d3fa srli r2,r5,15 - 7df8: 11001dc4 addi r4,r2,119 - 7dfc: 200690fa slli r3,r4,3 - 7e00: 003f7306 br 7bd0 <_malloc_r+0x4d8> - 7e04: 0104303a nor r2,zero,r4 - 7e08: 388e703a and r7,r7,r2 - 7e0c: e1c00115 stw r7,4(fp) - 7e10: 003fe906 br 7db8 <_malloc_r+0x6c0> - 7e14: 00815504 movi r2,1364 - 7e18: 1100032e bgeu r2,r4,7e28 <_malloc_r+0x730> - 7e1c: 01001f84 movi r4,126 - 7e20: 00c0fc04 movi r3,1008 - 7e24: 003f6a06 br 7bd0 <_malloc_r+0x4d8> - 7e28: 2804d4ba srli r2,r5,18 - 7e2c: 11001f04 addi r4,r2,124 - 7e30: 200690fa slli r3,r4,3 - 7e34: 003f6606 br 7bd0 <_malloc_r+0x4d8> - -00007e38 : - 7e38: 008000c4 movi r2,3 - 7e3c: 29403fcc andi r5,r5,255 - 7e40: 2007883a mov r3,r4 - 7e44: 1180022e bgeu r2,r6,7e50 - 7e48: 2084703a and r2,r4,r2 - 7e4c: 10000b26 beq r2,zero,7e7c - 7e50: 313fffc4 addi r4,r6,-1 - 7e54: 3000051e bne r6,zero,7e6c - 7e58: 00002c06 br 7f0c - 7e5c: 213fffc4 addi r4,r4,-1 - 7e60: 00bfffc4 movi r2,-1 - 7e64: 18c00044 addi r3,r3,1 - 7e68: 20802826 beq r4,r2,7f0c - 7e6c: 18800003 ldbu r2,0(r3) - 7e70: 28bffa1e bne r5,r2,7e5c - 7e74: 1805883a mov r2,r3 - 7e78: f800283a ret - 7e7c: 0011883a mov r8,zero - 7e80: 0007883a mov r3,zero - 7e84: 01c00104 movi r7,4 - 7e88: 4004923a slli r2,r8,8 - 7e8c: 18c00044 addi r3,r3,1 - 7e90: 1151883a add r8,r2,r5 - 7e94: 19fffc1e bne r3,r7,7e88 - 7e98: 02bfbff4 movhi r10,65279 - 7e9c: 52bfbfc4 addi r10,r10,-257 - 7ea0: 02602074 movhi r9,32897 - 7ea4: 4a602004 addi r9,r9,-32640 - 7ea8: 02c000c4 movi r11,3 - 7eac: 20800017 ldw r2,0(r4) - 7eb0: 31bfff04 addi r6,r6,-4 - 7eb4: 200f883a mov r7,r4 - 7eb8: 1204f03a xor r2,r2,r8 - 7ebc: 1287883a add r3,r2,r10 - 7ec0: 1a46703a and r3,r3,r9 - 7ec4: 0084303a nor r2,zero,r2 - 7ec8: 10c4703a and r2,r2,r3 - 7ecc: 10000b26 beq r2,zero,7efc - 7ed0: 20800003 ldbu r2,0(r4) - 7ed4: 28800f26 beq r5,r2,7f14 - 7ed8: 20800043 ldbu r2,1(r4) - 7edc: 21c00044 addi r7,r4,1 - 7ee0: 28800c26 beq r5,r2,7f14 - 7ee4: 20800083 ldbu r2,2(r4) - 7ee8: 21c00084 addi r7,r4,2 - 7eec: 28800926 beq r5,r2,7f14 - 7ef0: 208000c3 ldbu r2,3(r4) - 7ef4: 21c000c4 addi r7,r4,3 - 7ef8: 28800626 beq r5,r2,7f14 - 7efc: 21000104 addi r4,r4,4 - 7f00: 59bfea36 bltu r11,r6,7eac - 7f04: 2007883a mov r3,r4 - 7f08: 003fd106 br 7e50 - 7f0c: 0005883a mov r2,zero - 7f10: f800283a ret - 7f14: 3805883a mov r2,r7 - 7f18: f800283a ret - -00007f1c : - 7f1c: 01c003c4 movi r7,15 - 7f20: 2007883a mov r3,r4 - 7f24: 3980032e bgeu r7,r6,7f34 - 7f28: 2904b03a or r2,r5,r4 - 7f2c: 108000cc andi r2,r2,3 - 7f30: 10000926 beq r2,zero,7f58 - 7f34: 30000626 beq r6,zero,7f50 - 7f38: 30cd883a add r6,r6,r3 - 7f3c: 28800003 ldbu r2,0(r5) - 7f40: 29400044 addi r5,r5,1 - 7f44: 18800005 stb r2,0(r3) - 7f48: 18c00044 addi r3,r3,1 - 7f4c: 30fffb1e bne r6,r3,7f3c - 7f50: 2005883a mov r2,r4 - 7f54: f800283a ret - 7f58: 3811883a mov r8,r7 - 7f5c: 200f883a mov r7,r4 - 7f60: 28c00017 ldw r3,0(r5) - 7f64: 31bffc04 addi r6,r6,-16 - 7f68: 38c00015 stw r3,0(r7) - 7f6c: 28800117 ldw r2,4(r5) - 7f70: 38800115 stw r2,4(r7) - 7f74: 28c00217 ldw r3,8(r5) - 7f78: 38c00215 stw r3,8(r7) - 7f7c: 28800317 ldw r2,12(r5) - 7f80: 29400404 addi r5,r5,16 - 7f84: 38800315 stw r2,12(r7) - 7f88: 39c00404 addi r7,r7,16 - 7f8c: 41bff436 bltu r8,r6,7f60 - 7f90: 008000c4 movi r2,3 - 7f94: 1180072e bgeu r2,r6,7fb4 - 7f98: 1007883a mov r3,r2 - 7f9c: 28800017 ldw r2,0(r5) - 7fa0: 31bfff04 addi r6,r6,-4 - 7fa4: 29400104 addi r5,r5,4 - 7fa8: 38800015 stw r2,0(r7) - 7fac: 39c00104 addi r7,r7,4 - 7fb0: 19bffa36 bltu r3,r6,7f9c - 7fb4: 3807883a mov r3,r7 - 7fb8: 003fde06 br 7f34 - -00007fbc : - 7fbc: 2807883a mov r3,r5 - 7fc0: 2011883a mov r8,r4 - 7fc4: 29000c2e bgeu r5,r4,7ff8 - 7fc8: 298f883a add r7,r5,r6 - 7fcc: 21c00a2e bgeu r4,r7,7ff8 - 7fd0: 30000726 beq r6,zero,7ff0 - 7fd4: 2187883a add r3,r4,r6 - 7fd8: 198dc83a sub r6,r3,r6 - 7fdc: 39ffffc4 addi r7,r7,-1 - 7fe0: 38800003 ldbu r2,0(r7) - 7fe4: 18ffffc4 addi r3,r3,-1 - 7fe8: 18800005 stb r2,0(r3) - 7fec: 19bffb1e bne r3,r6,7fdc - 7ff0: 2005883a mov r2,r4 - 7ff4: f800283a ret - 7ff8: 01c003c4 movi r7,15 - 7ffc: 39800a36 bltu r7,r6,8028 - 8000: 303ffb26 beq r6,zero,7ff0 - 8004: 400f883a mov r7,r8 - 8008: 320d883a add r6,r6,r8 - 800c: 28800003 ldbu r2,0(r5) - 8010: 29400044 addi r5,r5,1 - 8014: 38800005 stb r2,0(r7) - 8018: 39c00044 addi r7,r7,1 - 801c: 39bffb1e bne r7,r6,800c - 8020: 2005883a mov r2,r4 - 8024: f800283a ret - 8028: 1904b03a or r2,r3,r4 - 802c: 108000cc andi r2,r2,3 - 8030: 103ff31e bne r2,zero,8000 - 8034: 3811883a mov r8,r7 - 8038: 180b883a mov r5,r3 - 803c: 200f883a mov r7,r4 - 8040: 28c00017 ldw r3,0(r5) - 8044: 31bffc04 addi r6,r6,-16 - 8048: 38c00015 stw r3,0(r7) - 804c: 28800117 ldw r2,4(r5) - 8050: 38800115 stw r2,4(r7) - 8054: 28c00217 ldw r3,8(r5) - 8058: 38c00215 stw r3,8(r7) - 805c: 28800317 ldw r2,12(r5) - 8060: 29400404 addi r5,r5,16 - 8064: 38800315 stw r2,12(r7) - 8068: 39c00404 addi r7,r7,16 - 806c: 41bff436 bltu r8,r6,8040 - 8070: 008000c4 movi r2,3 - 8074: 1180072e bgeu r2,r6,8094 - 8078: 1007883a mov r3,r2 - 807c: 28800017 ldw r2,0(r5) - 8080: 31bfff04 addi r6,r6,-4 - 8084: 29400104 addi r5,r5,4 - 8088: 38800015 stw r2,0(r7) - 808c: 39c00104 addi r7,r7,4 - 8090: 19bffa36 bltu r3,r6,807c - 8094: 3811883a mov r8,r7 - 8098: 003fd906 br 8000 - -0000809c : - 809c: 008000c4 movi r2,3 - 80a0: 29403fcc andi r5,r5,255 - 80a4: 2007883a mov r3,r4 - 80a8: 1180022e bgeu r2,r6,80b4 - 80ac: 2084703a and r2,r4,r2 - 80b0: 10000826 beq r2,zero,80d4 - 80b4: 30000526 beq r6,zero,80cc - 80b8: 2805883a mov r2,r5 - 80bc: 30cd883a add r6,r6,r3 - 80c0: 18800005 stb r2,0(r3) - 80c4: 18c00044 addi r3,r3,1 - 80c8: 19bffd1e bne r3,r6,80c0 - 80cc: 2005883a mov r2,r4 - 80d0: f800283a ret - 80d4: 2804923a slli r2,r5,8 - 80d8: 020003c4 movi r8,15 - 80dc: 200f883a mov r7,r4 - 80e0: 2884b03a or r2,r5,r2 - 80e4: 1006943a slli r3,r2,16 - 80e8: 10c6b03a or r3,r2,r3 - 80ec: 41800a2e bgeu r8,r6,8118 - 80f0: 4005883a mov r2,r8 - 80f4: 31bffc04 addi r6,r6,-16 - 80f8: 38c00015 stw r3,0(r7) - 80fc: 38c00115 stw r3,4(r7) - 8100: 38c00215 stw r3,8(r7) - 8104: 38c00315 stw r3,12(r7) - 8108: 39c00404 addi r7,r7,16 - 810c: 11bff936 bltu r2,r6,80f4 - 8110: 008000c4 movi r2,3 - 8114: 1180052e bgeu r2,r6,812c - 8118: 31bfff04 addi r6,r6,-4 - 811c: 008000c4 movi r2,3 - 8120: 38c00015 stw r3,0(r7) - 8124: 39c00104 addi r7,r7,4 - 8128: 11bffb36 bltu r2,r6,8118 - 812c: 3807883a mov r3,r7 - 8130: 003fe006 br 80b4 - -00008134 <_Bfree>: - 8134: 28000826 beq r5,zero,8158 <_Bfree+0x24> - 8138: 28800117 ldw r2,4(r5) - 813c: 21001317 ldw r4,76(r4) - 8140: 1085883a add r2,r2,r2 - 8144: 1085883a add r2,r2,r2 - 8148: 1105883a add r2,r2,r4 - 814c: 10c00017 ldw r3,0(r2) - 8150: 28c00015 stw r3,0(r5) - 8154: 11400015 stw r5,0(r2) - 8158: f800283a ret - -0000815c <__hi0bits>: - 815c: 20bfffec andhi r2,r4,65535 - 8160: 10001426 beq r2,zero,81b4 <__hi0bits+0x58> - 8164: 0007883a mov r3,zero - 8168: 20bfc02c andhi r2,r4,65280 - 816c: 1000021e bne r2,zero,8178 <__hi0bits+0x1c> - 8170: 2008923a slli r4,r4,8 - 8174: 18c00204 addi r3,r3,8 - 8178: 20bc002c andhi r2,r4,61440 - 817c: 1000021e bne r2,zero,8188 <__hi0bits+0x2c> - 8180: 2008913a slli r4,r4,4 - 8184: 18c00104 addi r3,r3,4 - 8188: 20b0002c andhi r2,r4,49152 - 818c: 1000031e bne r2,zero,819c <__hi0bits+0x40> - 8190: 2105883a add r2,r4,r4 - 8194: 18c00084 addi r3,r3,2 - 8198: 1089883a add r4,r2,r2 - 819c: 20000316 blt r4,zero,81ac <__hi0bits+0x50> - 81a0: 2090002c andhi r2,r4,16384 - 81a4: 10000626 beq r2,zero,81c0 <__hi0bits+0x64> - 81a8: 18c00044 addi r3,r3,1 - 81ac: 1805883a mov r2,r3 - 81b0: f800283a ret - 81b4: 2008943a slli r4,r4,16 - 81b8: 00c00404 movi r3,16 - 81bc: 003fea06 br 8168 <__hi0bits+0xc> - 81c0: 00c00804 movi r3,32 - 81c4: 1805883a mov r2,r3 - 81c8: f800283a ret - -000081cc <__lo0bits>: - 81cc: 20c00017 ldw r3,0(r4) - 81d0: 188001cc andi r2,r3,7 - 81d4: 10000a26 beq r2,zero,8200 <__lo0bits+0x34> - 81d8: 1880004c andi r2,r3,1 - 81dc: 1005003a cmpeq r2,r2,zero - 81e0: 10002126 beq r2,zero,8268 <__lo0bits+0x9c> - 81e4: 1880008c andi r2,r3,2 - 81e8: 1000251e bne r2,zero,8280 <__lo0bits+0xb4> - 81ec: 1804d0ba srli r2,r3,2 - 81f0: 01400084 movi r5,2 - 81f4: 20800015 stw r2,0(r4) - 81f8: 2805883a mov r2,r5 - 81fc: f800283a ret - 8200: 18bfffcc andi r2,r3,65535 - 8204: 10001526 beq r2,zero,825c <__lo0bits+0x90> - 8208: 000b883a mov r5,zero - 820c: 18803fcc andi r2,r3,255 - 8210: 1000021e bne r2,zero,821c <__lo0bits+0x50> - 8214: 1806d23a srli r3,r3,8 - 8218: 29400204 addi r5,r5,8 - 821c: 188003cc andi r2,r3,15 - 8220: 1000021e bne r2,zero,822c <__lo0bits+0x60> - 8224: 1806d13a srli r3,r3,4 - 8228: 29400104 addi r5,r5,4 - 822c: 188000cc andi r2,r3,3 - 8230: 1000021e bne r2,zero,823c <__lo0bits+0x70> - 8234: 1806d0ba srli r3,r3,2 - 8238: 29400084 addi r5,r5,2 - 823c: 1880004c andi r2,r3,1 - 8240: 1000031e bne r2,zero,8250 <__lo0bits+0x84> - 8244: 1806d07a srli r3,r3,1 - 8248: 18000a26 beq r3,zero,8274 <__lo0bits+0xa8> - 824c: 29400044 addi r5,r5,1 - 8250: 2805883a mov r2,r5 - 8254: 20c00015 stw r3,0(r4) - 8258: f800283a ret - 825c: 1806d43a srli r3,r3,16 - 8260: 01400404 movi r5,16 - 8264: 003fe906 br 820c <__lo0bits+0x40> - 8268: 000b883a mov r5,zero - 826c: 2805883a mov r2,r5 - 8270: f800283a ret - 8274: 01400804 movi r5,32 - 8278: 2805883a mov r2,r5 - 827c: f800283a ret - 8280: 1804d07a srli r2,r3,1 - 8284: 01400044 movi r5,1 - 8288: 20800015 stw r2,0(r4) - 828c: 003fda06 br 81f8 <__lo0bits+0x2c> - -00008290 <__mcmp>: - 8290: 20800417 ldw r2,16(r4) - 8294: 28c00417 ldw r3,16(r5) - 8298: 10cfc83a sub r7,r2,r3 - 829c: 38000c1e bne r7,zero,82d0 <__mcmp+0x40> - 82a0: 18c5883a add r2,r3,r3 - 82a4: 1085883a add r2,r2,r2 - 82a8: 10c00504 addi r3,r2,20 - 82ac: 21000504 addi r4,r4,20 - 82b0: 28cb883a add r5,r5,r3 - 82b4: 2085883a add r2,r4,r2 - 82b8: 10bfff04 addi r2,r2,-4 - 82bc: 297fff04 addi r5,r5,-4 - 82c0: 11800017 ldw r6,0(r2) - 82c4: 28c00017 ldw r3,0(r5) - 82c8: 30c0031e bne r6,r3,82d8 <__mcmp+0x48> - 82cc: 20bffa36 bltu r4,r2,82b8 <__mcmp+0x28> - 82d0: 3805883a mov r2,r7 - 82d4: f800283a ret - 82d8: 30c00336 bltu r6,r3,82e8 <__mcmp+0x58> - 82dc: 01c00044 movi r7,1 - 82e0: 3805883a mov r2,r7 - 82e4: f800283a ret - 82e8: 01ffffc4 movi r7,-1 - 82ec: 003ff806 br 82d0 <__mcmp+0x40> - -000082f0 <__ulp>: - 82f0: 295ffc2c andhi r5,r5,32752 - 82f4: 013f3034 movhi r4,64704 - 82f8: 290b883a add r5,r5,r4 - 82fc: 0145c83a sub r2,zero,r5 - 8300: 1007d53a srai r3,r2,20 - 8304: 000d883a mov r6,zero - 8308: 0140040e bge zero,r5,831c <__ulp+0x2c> - 830c: 280f883a mov r7,r5 - 8310: 3807883a mov r3,r7 - 8314: 3005883a mov r2,r6 - 8318: f800283a ret - 831c: 008004c4 movi r2,19 - 8320: 193ffb04 addi r4,r3,-20 - 8324: 10c00c0e bge r2,r3,8358 <__ulp+0x68> - 8328: 008007c4 movi r2,31 - 832c: 1107c83a sub r3,r2,r4 - 8330: 00800784 movi r2,30 - 8334: 01400044 movi r5,1 - 8338: 11000216 blt r2,r4,8344 <__ulp+0x54> - 833c: 00800044 movi r2,1 - 8340: 10ca983a sll r5,r2,r3 - 8344: 000f883a mov r7,zero - 8348: 280d883a mov r6,r5 - 834c: 3807883a mov r3,r7 - 8350: 3005883a mov r2,r6 - 8354: f800283a ret - 8358: 00800234 movhi r2,8 - 835c: 10cfd83a sra r7,r2,r3 - 8360: 000d883a mov r6,zero - 8364: 3005883a mov r2,r6 - 8368: 3807883a mov r3,r7 - 836c: f800283a ret - -00008370 <__b2d>: - 8370: 20800417 ldw r2,16(r4) - 8374: defff904 addi sp,sp,-28 - 8378: dd000415 stw r20,16(sp) - 837c: 1085883a add r2,r2,r2 - 8380: 25000504 addi r20,r4,20 - 8384: 1085883a add r2,r2,r2 - 8388: dc000015 stw r16,0(sp) - 838c: a0a1883a add r16,r20,r2 - 8390: dd400515 stw r21,20(sp) - 8394: 857fff17 ldw r21,-4(r16) - 8398: dc400115 stw r17,4(sp) - 839c: dfc00615 stw ra,24(sp) - 83a0: a809883a mov r4,r21 - 83a4: 2823883a mov r17,r5 - 83a8: dcc00315 stw r19,12(sp) - 83ac: dc800215 stw r18,8(sp) - 83b0: 000815c0 call 815c <__hi0bits> - 83b4: 100b883a mov r5,r2 - 83b8: 00800804 movi r2,32 - 83bc: 1145c83a sub r2,r2,r5 - 83c0: 88800015 stw r2,0(r17) - 83c4: 00800284 movi r2,10 - 83c8: 80ffff04 addi r3,r16,-4 - 83cc: 11401416 blt r2,r5,8420 <__b2d+0xb0> - 83d0: 008002c4 movi r2,11 - 83d4: 1149c83a sub r4,r2,r5 - 83d8: a0c02736 bltu r20,r3,8478 <__b2d+0x108> - 83dc: 000d883a mov r6,zero - 83e0: 28800544 addi r2,r5,21 - 83e4: a906d83a srl r3,r21,r4 - 83e8: a884983a sll r2,r21,r2 - 83ec: 1ccffc34 orhi r19,r3,16368 - 83f0: 11a4b03a or r18,r2,r6 - 83f4: 9005883a mov r2,r18 - 83f8: 9807883a mov r3,r19 - 83fc: dfc00617 ldw ra,24(sp) - 8400: dd400517 ldw r21,20(sp) - 8404: dd000417 ldw r20,16(sp) - 8408: dcc00317 ldw r19,12(sp) - 840c: dc800217 ldw r18,8(sp) - 8410: dc400117 ldw r17,4(sp) - 8414: dc000017 ldw r16,0(sp) - 8418: dec00704 addi sp,sp,28 - 841c: f800283a ret - 8420: a0c00e36 bltu r20,r3,845c <__b2d+0xec> - 8424: 293ffd44 addi r4,r5,-11 - 8428: 000d883a mov r6,zero - 842c: 20000f26 beq r4,zero,846c <__b2d+0xfc> - 8430: 00800804 movi r2,32 - 8434: 110bc83a sub r5,r2,r4 - 8438: a0c01236 bltu r20,r3,8484 <__b2d+0x114> - 843c: 000f883a mov r7,zero - 8440: a904983a sll r2,r21,r4 - 8444: 3146d83a srl r3,r6,r5 - 8448: 3108983a sll r4,r6,r4 - 844c: 108ffc34 orhi r2,r2,16368 - 8450: 18a6b03a or r19,r3,r2 - 8454: 3924b03a or r18,r7,r4 - 8458: 003fe606 br 83f4 <__b2d+0x84> - 845c: 293ffd44 addi r4,r5,-11 - 8460: 81bffe17 ldw r6,-8(r16) - 8464: 80fffe04 addi r3,r16,-8 - 8468: 203ff11e bne r4,zero,8430 <__b2d+0xc0> - 846c: accffc34 orhi r19,r21,16368 - 8470: 3025883a mov r18,r6 - 8474: 003fdf06 br 83f4 <__b2d+0x84> - 8478: 18bfff17 ldw r2,-4(r3) - 847c: 110cd83a srl r6,r2,r4 - 8480: 003fd706 br 83e0 <__b2d+0x70> - 8484: 18bfff17 ldw r2,-4(r3) - 8488: 114ed83a srl r7,r2,r5 - 848c: 003fec06 br 8440 <__b2d+0xd0> - -00008490 <__ratio>: - 8490: defff904 addi sp,sp,-28 - 8494: dc400215 stw r17,8(sp) - 8498: 2823883a mov r17,r5 - 849c: d80b883a mov r5,sp - 84a0: dfc00615 stw ra,24(sp) - 84a4: dd000515 stw r20,20(sp) - 84a8: dcc00415 stw r19,16(sp) - 84ac: dc800315 stw r18,12(sp) - 84b0: 2025883a mov r18,r4 - 84b4: 00083700 call 8370 <__b2d> - 84b8: 8809883a mov r4,r17 - 84bc: d9400104 addi r5,sp,4 - 84c0: 1027883a mov r19,r2 - 84c4: 1829883a mov r20,r3 - 84c8: 00083700 call 8370 <__b2d> - 84cc: 89000417 ldw r4,16(r17) - 84d0: 91c00417 ldw r7,16(r18) - 84d4: d9800117 ldw r6,4(sp) - 84d8: 180b883a mov r5,r3 - 84dc: 390fc83a sub r7,r7,r4 - 84e0: 1009883a mov r4,r2 - 84e4: d8800017 ldw r2,0(sp) - 84e8: 380e917a slli r7,r7,5 - 84ec: 2011883a mov r8,r4 - 84f0: 1185c83a sub r2,r2,r6 - 84f4: 11c5883a add r2,r2,r7 - 84f8: 1006953a slli r3,r2,20 - 84fc: 2813883a mov r9,r5 - 8500: 00800d0e bge zero,r2,8538 <__ratio+0xa8> - 8504: 1d29883a add r20,r3,r20 - 8508: a00b883a mov r5,r20 - 850c: 480f883a mov r7,r9 - 8510: 9809883a mov r4,r19 - 8514: 400d883a mov r6,r8 - 8518: 000b4d80 call b4d8 <__divdf3> - 851c: dfc00617 ldw ra,24(sp) - 8520: dd000517 ldw r20,20(sp) - 8524: dcc00417 ldw r19,16(sp) - 8528: dc800317 ldw r18,12(sp) - 852c: dc400217 ldw r17,8(sp) - 8530: dec00704 addi sp,sp,28 - 8534: f800283a ret - 8538: 28d3c83a sub r9,r5,r3 - 853c: 003ff206 br 8508 <__ratio+0x78> - -00008540 <_mprec_log10>: - 8540: defffe04 addi sp,sp,-8 - 8544: 008005c4 movi r2,23 - 8548: dc000015 stw r16,0(sp) - 854c: dfc00115 stw ra,4(sp) - 8550: 2021883a mov r16,r4 - 8554: 11000c16 blt r2,r4,8588 <_mprec_log10+0x48> - 8558: 200490fa slli r2,r4,3 - 855c: 00c00074 movhi r3,1 - 8560: 18c0d104 addi r3,r3,836 - 8564: 10c5883a add r2,r2,r3 - 8568: 12400117 ldw r9,4(r2) - 856c: 12000017 ldw r8,0(r2) - 8570: 4807883a mov r3,r9 - 8574: 4005883a mov r2,r8 - 8578: dfc00117 ldw ra,4(sp) - 857c: dc000017 ldw r16,0(sp) - 8580: dec00204 addi sp,sp,8 - 8584: f800283a ret - 8588: 0011883a mov r8,zero - 858c: 024ffc34 movhi r9,16368 - 8590: 0005883a mov r2,zero - 8594: 00d00934 movhi r3,16420 - 8598: 480b883a mov r5,r9 - 859c: 4009883a mov r4,r8 - 85a0: 180f883a mov r7,r3 - 85a4: 100d883a mov r6,r2 - 85a8: 000b1140 call b114 <__muldf3> - 85ac: 843fffc4 addi r16,r16,-1 - 85b0: 1011883a mov r8,r2 - 85b4: 1813883a mov r9,r3 - 85b8: 803ff51e bne r16,zero,8590 <_mprec_log10+0x50> - 85bc: 4005883a mov r2,r8 - 85c0: 4807883a mov r3,r9 - 85c4: dfc00117 ldw ra,4(sp) - 85c8: dc000017 ldw r16,0(sp) - 85cc: dec00204 addi sp,sp,8 - 85d0: f800283a ret - -000085d4 <__copybits>: - 85d4: 297fffc4 addi r5,r5,-1 - 85d8: 30800417 ldw r2,16(r6) - 85dc: 280bd17a srai r5,r5,5 - 85e0: 31800504 addi r6,r6,20 - 85e4: 1085883a add r2,r2,r2 - 85e8: 294b883a add r5,r5,r5 - 85ec: 294b883a add r5,r5,r5 - 85f0: 1085883a add r2,r2,r2 - 85f4: 290b883a add r5,r5,r4 - 85f8: 3087883a add r3,r6,r2 - 85fc: 29400104 addi r5,r5,4 - 8600: 30c0052e bgeu r6,r3,8618 <__copybits+0x44> - 8604: 30800017 ldw r2,0(r6) - 8608: 31800104 addi r6,r6,4 - 860c: 20800015 stw r2,0(r4) - 8610: 21000104 addi r4,r4,4 - 8614: 30fffb36 bltu r6,r3,8604 <__copybits+0x30> - 8618: 2140032e bgeu r4,r5,8628 <__copybits+0x54> - 861c: 20000015 stw zero,0(r4) - 8620: 21000104 addi r4,r4,4 - 8624: 217ffd36 bltu r4,r5,861c <__copybits+0x48> - 8628: f800283a ret - -0000862c <__any_on>: - 862c: 20800417 ldw r2,16(r4) - 8630: 2807d17a srai r3,r5,5 - 8634: 21000504 addi r4,r4,20 - 8638: 10c00d0e bge r2,r3,8670 <__any_on+0x44> - 863c: 1085883a add r2,r2,r2 - 8640: 1085883a add r2,r2,r2 - 8644: 208d883a add r6,r4,r2 - 8648: 2180182e bgeu r4,r6,86ac <__any_on+0x80> - 864c: 30bfff17 ldw r2,-4(r6) - 8650: 30ffff04 addi r3,r6,-4 - 8654: 1000041e bne r2,zero,8668 <__any_on+0x3c> - 8658: 20c0142e bgeu r4,r3,86ac <__any_on+0x80> - 865c: 18ffff04 addi r3,r3,-4 - 8660: 18800017 ldw r2,0(r3) - 8664: 103ffc26 beq r2,zero,8658 <__any_on+0x2c> - 8668: 00800044 movi r2,1 - 866c: f800283a ret - 8670: 18800a0e bge r3,r2,869c <__any_on+0x70> - 8674: 294007cc andi r5,r5,31 - 8678: 28000826 beq r5,zero,869c <__any_on+0x70> - 867c: 18c5883a add r2,r3,r3 - 8680: 1085883a add r2,r2,r2 - 8684: 208d883a add r6,r4,r2 - 8688: 30c00017 ldw r3,0(r6) - 868c: 1944d83a srl r2,r3,r5 - 8690: 1144983a sll r2,r2,r5 - 8694: 18bff41e bne r3,r2,8668 <__any_on+0x3c> - 8698: 003feb06 br 8648 <__any_on+0x1c> - 869c: 18c5883a add r2,r3,r3 - 86a0: 1085883a add r2,r2,r2 - 86a4: 208d883a add r6,r4,r2 - 86a8: 003fe706 br 8648 <__any_on+0x1c> - 86ac: 0005883a mov r2,zero - 86b0: f800283a ret - -000086b4 <_Balloc>: - 86b4: 20c01317 ldw r3,76(r4) - 86b8: defffb04 addi sp,sp,-20 - 86bc: dcc00315 stw r19,12(sp) - 86c0: dc800215 stw r18,8(sp) - 86c4: dfc00415 stw ra,16(sp) - 86c8: 2825883a mov r18,r5 - 86cc: dc400115 stw r17,4(sp) - 86d0: dc000015 stw r16,0(sp) - 86d4: 2027883a mov r19,r4 - 86d8: 01800404 movi r6,16 - 86dc: 01400104 movi r5,4 - 86e0: 18001726 beq r3,zero,8740 <_Balloc+0x8c> - 86e4: 01400044 movi r5,1 - 86e8: 9485883a add r2,r18,r18 - 86ec: 2ca2983a sll r17,r5,r18 - 86f0: 1085883a add r2,r2,r2 - 86f4: 10c7883a add r3,r2,r3 - 86f8: 1c000017 ldw r16,0(r3) - 86fc: 8c4d883a add r6,r17,r17 - 8700: 318d883a add r6,r6,r6 - 8704: 9809883a mov r4,r19 - 8708: 31800504 addi r6,r6,20 - 870c: 80001226 beq r16,zero,8758 <_Balloc+0xa4> - 8710: 80800017 ldw r2,0(r16) - 8714: 18800015 stw r2,0(r3) - 8718: 80000415 stw zero,16(r16) - 871c: 80000315 stw zero,12(r16) - 8720: 8005883a mov r2,r16 - 8724: dfc00417 ldw ra,16(sp) - 8728: dcc00317 ldw r19,12(sp) - 872c: dc800217 ldw r18,8(sp) - 8730: dc400117 ldw r17,4(sp) - 8734: dc000017 ldw r16,0(sp) - 8738: dec00504 addi sp,sp,20 - 873c: f800283a ret - 8740: 0009b140 call 9b14 <_calloc_r> - 8744: 1007883a mov r3,r2 - 8748: 0021883a mov r16,zero - 874c: 98801315 stw r2,76(r19) - 8750: 103fe41e bne r2,zero,86e4 <_Balloc+0x30> - 8754: 003ff206 br 8720 <_Balloc+0x6c> - 8758: 0009b140 call 9b14 <_calloc_r> - 875c: 103ff026 beq r2,zero,8720 <_Balloc+0x6c> - 8760: 1021883a mov r16,r2 - 8764: 14800115 stw r18,4(r2) - 8768: 14400215 stw r17,8(r2) - 876c: 003fea06 br 8718 <_Balloc+0x64> - -00008770 <__d2b>: - 8770: defff504 addi sp,sp,-44 - 8774: dcc00515 stw r19,20(sp) - 8778: 04c00044 movi r19,1 - 877c: dc000215 stw r16,8(sp) - 8780: 2821883a mov r16,r5 - 8784: 980b883a mov r5,r19 - 8788: ddc00915 stw r23,36(sp) - 878c: dd800815 stw r22,32(sp) - 8790: dd400715 stw r21,28(sp) - 8794: dd000615 stw r20,24(sp) - 8798: dc800415 stw r18,16(sp) - 879c: dc400315 stw r17,12(sp) - 87a0: dfc00a15 stw ra,40(sp) - 87a4: 3023883a mov r17,r6 - 87a8: 382d883a mov r22,r7 - 87ac: ddc00b17 ldw r23,44(sp) - 87b0: 00086b40 call 86b4 <_Balloc> - 87b4: 1025883a mov r18,r2 - 87b8: 00a00034 movhi r2,32768 - 87bc: 10bfffc4 addi r2,r2,-1 - 87c0: 8888703a and r4,r17,r2 - 87c4: 202ad53a srli r21,r4,20 - 87c8: 00800434 movhi r2,16 - 87cc: 10bfffc4 addi r2,r2,-1 - 87d0: 8886703a and r3,r17,r2 - 87d4: a829003a cmpeq r20,r21,zero - 87d8: 800b883a mov r5,r16 - 87dc: d8c00115 stw r3,4(sp) - 87e0: 94000504 addi r16,r18,20 - 87e4: a000021e bne r20,zero,87f0 <__d2b+0x80> - 87e8: 18c00434 orhi r3,r3,16 - 87ec: d8c00115 stw r3,4(sp) - 87f0: 28002726 beq r5,zero,8890 <__d2b+0x120> - 87f4: d809883a mov r4,sp - 87f8: d9400015 stw r5,0(sp) - 87fc: 00081cc0 call 81cc <__lo0bits> - 8800: 100d883a mov r6,r2 - 8804: 10003526 beq r2,zero,88dc <__d2b+0x16c> - 8808: d8c00117 ldw r3,4(sp) - 880c: 00800804 movi r2,32 - 8810: 1185c83a sub r2,r2,r6 - 8814: d9000017 ldw r4,0(sp) - 8818: 1886983a sll r3,r3,r2 - 881c: 1906b03a or r3,r3,r4 - 8820: 90c00515 stw r3,20(r18) - 8824: d8c00117 ldw r3,4(sp) - 8828: 1986d83a srl r3,r3,r6 - 882c: d8c00115 stw r3,4(sp) - 8830: 180b003a cmpeq r5,r3,zero - 8834: 00800084 movi r2,2 - 8838: 114bc83a sub r5,r2,r5 - 883c: 80c00115 stw r3,4(r16) - 8840: 91400415 stw r5,16(r18) - 8844: a0001a1e bne r20,zero,88b0 <__d2b+0x140> - 8848: 3545883a add r2,r6,r21 - 884c: 10bef344 addi r2,r2,-1075 - 8850: 00c00d44 movi r3,53 - 8854: b0800015 stw r2,0(r22) - 8858: 1987c83a sub r3,r3,r6 - 885c: b8c00015 stw r3,0(r23) - 8860: 9005883a mov r2,r18 - 8864: dfc00a17 ldw ra,40(sp) - 8868: ddc00917 ldw r23,36(sp) - 886c: dd800817 ldw r22,32(sp) - 8870: dd400717 ldw r21,28(sp) - 8874: dd000617 ldw r20,24(sp) - 8878: dcc00517 ldw r19,20(sp) - 887c: dc800417 ldw r18,16(sp) - 8880: dc400317 ldw r17,12(sp) - 8884: dc000217 ldw r16,8(sp) - 8888: dec00b04 addi sp,sp,44 - 888c: f800283a ret - 8890: d9000104 addi r4,sp,4 - 8894: 00081cc0 call 81cc <__lo0bits> - 8898: 11800804 addi r6,r2,32 - 889c: d8800117 ldw r2,4(sp) - 88a0: 94c00415 stw r19,16(r18) - 88a4: 980b883a mov r5,r19 - 88a8: 90800515 stw r2,20(r18) - 88ac: a03fe626 beq r20,zero,8848 <__d2b+0xd8> - 88b0: 2945883a add r2,r5,r5 - 88b4: 1085883a add r2,r2,r2 - 88b8: 1405883a add r2,r2,r16 - 88bc: 113fff17 ldw r4,-4(r2) - 88c0: 30fef384 addi r3,r6,-1074 - 88c4: 2820917a slli r16,r5,5 - 88c8: b0c00015 stw r3,0(r22) - 88cc: 000815c0 call 815c <__hi0bits> - 88d0: 80a1c83a sub r16,r16,r2 - 88d4: bc000015 stw r16,0(r23) - 88d8: 003fe106 br 8860 <__d2b+0xf0> - 88dc: d8800017 ldw r2,0(sp) - 88e0: 90800515 stw r2,20(r18) - 88e4: d8c00117 ldw r3,4(sp) - 88e8: 003fd106 br 8830 <__d2b+0xc0> - -000088ec <__mdiff>: - 88ec: defffb04 addi sp,sp,-20 - 88f0: dc000015 stw r16,0(sp) - 88f4: 2821883a mov r16,r5 - 88f8: dc800215 stw r18,8(sp) - 88fc: 300b883a mov r5,r6 - 8900: 2025883a mov r18,r4 - 8904: 8009883a mov r4,r16 - 8908: dc400115 stw r17,4(sp) - 890c: dfc00415 stw ra,16(sp) - 8910: dcc00315 stw r19,12(sp) - 8914: 3023883a mov r17,r6 - 8918: 00082900 call 8290 <__mcmp> - 891c: 10004226 beq r2,zero,8a28 <__mdiff+0x13c> - 8920: 10005016 blt r2,zero,8a64 <__mdiff+0x178> - 8924: 0027883a mov r19,zero - 8928: 81400117 ldw r5,4(r16) - 892c: 9009883a mov r4,r18 - 8930: 00086b40 call 86b4 <_Balloc> - 8934: 1019883a mov r12,r2 - 8938: 82800417 ldw r10,16(r16) - 893c: 88800417 ldw r2,16(r17) - 8940: 81800504 addi r6,r16,20 - 8944: 5287883a add r3,r10,r10 - 8948: 1085883a add r2,r2,r2 - 894c: 18c7883a add r3,r3,r3 - 8950: 1085883a add r2,r2,r2 - 8954: 8a000504 addi r8,r17,20 - 8958: 64c00315 stw r19,12(r12) - 895c: 30db883a add r13,r6,r3 - 8960: 4097883a add r11,r8,r2 - 8964: 61c00504 addi r7,r12,20 - 8968: 0013883a mov r9,zero - 896c: 31000017 ldw r4,0(r6) - 8970: 41400017 ldw r5,0(r8) - 8974: 42000104 addi r8,r8,4 - 8978: 20bfffcc andi r2,r4,65535 - 897c: 28ffffcc andi r3,r5,65535 - 8980: 10c5c83a sub r2,r2,r3 - 8984: 1245883a add r2,r2,r9 - 8988: 2008d43a srli r4,r4,16 - 898c: 280ad43a srli r5,r5,16 - 8990: 1007d43a srai r3,r2,16 - 8994: 3880000d sth r2,0(r7) - 8998: 2149c83a sub r4,r4,r5 - 899c: 20c9883a add r4,r4,r3 - 89a0: 3900008d sth r4,2(r7) - 89a4: 31800104 addi r6,r6,4 - 89a8: 39c00104 addi r7,r7,4 - 89ac: 2013d43a srai r9,r4,16 - 89b0: 42ffee36 bltu r8,r11,896c <__mdiff+0x80> - 89b4: 33400c2e bgeu r6,r13,89e8 <__mdiff+0xfc> - 89b8: 30800017 ldw r2,0(r6) - 89bc: 31800104 addi r6,r6,4 - 89c0: 10ffffcc andi r3,r2,65535 - 89c4: 1a47883a add r3,r3,r9 - 89c8: 1004d43a srli r2,r2,16 - 89cc: 1809d43a srai r4,r3,16 - 89d0: 38c0000d sth r3,0(r7) - 89d4: 1105883a add r2,r2,r4 - 89d8: 3880008d sth r2,2(r7) - 89dc: 1013d43a srai r9,r2,16 - 89e0: 39c00104 addi r7,r7,4 - 89e4: 337ff436 bltu r6,r13,89b8 <__mdiff+0xcc> - 89e8: 38bfff17 ldw r2,-4(r7) - 89ec: 38ffff04 addi r3,r7,-4 - 89f0: 1000041e bne r2,zero,8a04 <__mdiff+0x118> - 89f4: 18ffff04 addi r3,r3,-4 - 89f8: 18800017 ldw r2,0(r3) - 89fc: 52bfffc4 addi r10,r10,-1 - 8a00: 103ffc26 beq r2,zero,89f4 <__mdiff+0x108> - 8a04: 6005883a mov r2,r12 - 8a08: 62800415 stw r10,16(r12) - 8a0c: dfc00417 ldw ra,16(sp) - 8a10: dcc00317 ldw r19,12(sp) - 8a14: dc800217 ldw r18,8(sp) - 8a18: dc400117 ldw r17,4(sp) - 8a1c: dc000017 ldw r16,0(sp) - 8a20: dec00504 addi sp,sp,20 - 8a24: f800283a ret - 8a28: 9009883a mov r4,r18 - 8a2c: 000b883a mov r5,zero - 8a30: 00086b40 call 86b4 <_Balloc> - 8a34: 1019883a mov r12,r2 - 8a38: 00800044 movi r2,1 - 8a3c: 60800415 stw r2,16(r12) - 8a40: 6005883a mov r2,r12 - 8a44: 60000515 stw zero,20(r12) - 8a48: dfc00417 ldw ra,16(sp) - 8a4c: dcc00317 ldw r19,12(sp) - 8a50: dc800217 ldw r18,8(sp) - 8a54: dc400117 ldw r17,4(sp) - 8a58: dc000017 ldw r16,0(sp) - 8a5c: dec00504 addi sp,sp,20 - 8a60: f800283a ret - 8a64: 880d883a mov r6,r17 - 8a68: 04c00044 movi r19,1 - 8a6c: 8023883a mov r17,r16 - 8a70: 3021883a mov r16,r6 - 8a74: 003fac06 br 8928 <__mdiff+0x3c> - -00008a78 <__lshift>: - 8a78: defff904 addi sp,sp,-28 - 8a7c: 28800417 ldw r2,16(r5) - 8a80: dc000015 stw r16,0(sp) - 8a84: 3021d17a srai r16,r6,5 - 8a88: 28c00217 ldw r3,8(r5) - 8a8c: 10800044 addi r2,r2,1 - 8a90: dc400115 stw r17,4(sp) - 8a94: 80a3883a add r17,r16,r2 - 8a98: dd400515 stw r21,20(sp) - 8a9c: dd000415 stw r20,16(sp) - 8aa0: dc800215 stw r18,8(sp) - 8aa4: dfc00615 stw ra,24(sp) - 8aa8: 2825883a mov r18,r5 - 8aac: dcc00315 stw r19,12(sp) - 8ab0: 3029883a mov r20,r6 - 8ab4: 202b883a mov r21,r4 - 8ab8: 29400117 ldw r5,4(r5) - 8abc: 1c40030e bge r3,r17,8acc <__lshift+0x54> - 8ac0: 18c7883a add r3,r3,r3 - 8ac4: 29400044 addi r5,r5,1 - 8ac8: 1c7ffd16 blt r3,r17,8ac0 <__lshift+0x48> - 8acc: a809883a mov r4,r21 - 8ad0: 00086b40 call 86b4 <_Balloc> - 8ad4: 1027883a mov r19,r2 - 8ad8: 11400504 addi r5,r2,20 - 8adc: 0400090e bge zero,r16,8b04 <__lshift+0x8c> - 8ae0: 2805883a mov r2,r5 - 8ae4: 0007883a mov r3,zero - 8ae8: 18c00044 addi r3,r3,1 - 8aec: 10000015 stw zero,0(r2) - 8af0: 10800104 addi r2,r2,4 - 8af4: 80fffc1e bne r16,r3,8ae8 <__lshift+0x70> - 8af8: 8405883a add r2,r16,r16 - 8afc: 1085883a add r2,r2,r2 - 8b00: 288b883a add r5,r5,r2 - 8b04: 90800417 ldw r2,16(r18) - 8b08: 91000504 addi r4,r18,20 - 8b0c: a18007cc andi r6,r20,31 - 8b10: 1085883a add r2,r2,r2 - 8b14: 1085883a add r2,r2,r2 - 8b18: 208f883a add r7,r4,r2 - 8b1c: 30001e26 beq r6,zero,8b98 <__lshift+0x120> - 8b20: 00800804 movi r2,32 - 8b24: 1191c83a sub r8,r2,r6 - 8b28: 0007883a mov r3,zero - 8b2c: 20800017 ldw r2,0(r4) - 8b30: 1184983a sll r2,r2,r6 - 8b34: 1884b03a or r2,r3,r2 - 8b38: 28800015 stw r2,0(r5) - 8b3c: 20c00017 ldw r3,0(r4) - 8b40: 21000104 addi r4,r4,4 - 8b44: 29400104 addi r5,r5,4 - 8b48: 1a06d83a srl r3,r3,r8 - 8b4c: 21fff736 bltu r4,r7,8b2c <__lshift+0xb4> - 8b50: 28c00015 stw r3,0(r5) - 8b54: 18000126 beq r3,zero,8b5c <__lshift+0xe4> - 8b58: 8c400044 addi r17,r17,1 - 8b5c: 88bfffc4 addi r2,r17,-1 - 8b60: 98800415 stw r2,16(r19) - 8b64: a809883a mov r4,r21 - 8b68: 900b883a mov r5,r18 - 8b6c: 00081340 call 8134 <_Bfree> - 8b70: 9805883a mov r2,r19 - 8b74: dfc00617 ldw ra,24(sp) - 8b78: dd400517 ldw r21,20(sp) - 8b7c: dd000417 ldw r20,16(sp) - 8b80: dcc00317 ldw r19,12(sp) - 8b84: dc800217 ldw r18,8(sp) - 8b88: dc400117 ldw r17,4(sp) - 8b8c: dc000017 ldw r16,0(sp) - 8b90: dec00704 addi sp,sp,28 - 8b94: f800283a ret - 8b98: 20800017 ldw r2,0(r4) - 8b9c: 21000104 addi r4,r4,4 - 8ba0: 28800015 stw r2,0(r5) - 8ba4: 29400104 addi r5,r5,4 - 8ba8: 21ffec2e bgeu r4,r7,8b5c <__lshift+0xe4> - 8bac: 20800017 ldw r2,0(r4) - 8bb0: 21000104 addi r4,r4,4 - 8bb4: 28800015 stw r2,0(r5) - 8bb8: 29400104 addi r5,r5,4 - 8bbc: 21fff636 bltu r4,r7,8b98 <__lshift+0x120> - 8bc0: 003fe606 br 8b5c <__lshift+0xe4> - -00008bc4 <__multiply>: - 8bc4: defff004 addi sp,sp,-64 - 8bc8: dc800815 stw r18,32(sp) - 8bcc: dc400715 stw r17,28(sp) - 8bd0: 2c800417 ldw r18,16(r5) - 8bd4: 34400417 ldw r17,16(r6) - 8bd8: dcc00915 stw r19,36(sp) - 8bdc: dc000615 stw r16,24(sp) - 8be0: dfc00f15 stw ra,60(sp) - 8be4: df000e15 stw fp,56(sp) - 8be8: ddc00d15 stw r23,52(sp) - 8bec: dd800c15 stw r22,48(sp) - 8bf0: dd400b15 stw r21,44(sp) - 8bf4: dd000a15 stw r20,40(sp) - 8bf8: 2821883a mov r16,r5 - 8bfc: 3027883a mov r19,r6 - 8c00: 9440040e bge r18,r17,8c14 <__multiply+0x50> - 8c04: 8825883a mov r18,r17 - 8c08: 2c400417 ldw r17,16(r5) - 8c0c: 2827883a mov r19,r5 - 8c10: 3021883a mov r16,r6 - 8c14: 80800217 ldw r2,8(r16) - 8c18: 9447883a add r3,r18,r17 - 8c1c: d8c00415 stw r3,16(sp) - 8c20: 81400117 ldw r5,4(r16) - 8c24: 10c0010e bge r2,r3,8c2c <__multiply+0x68> - 8c28: 29400044 addi r5,r5,1 - 8c2c: 00086b40 call 86b4 <_Balloc> - 8c30: d8800515 stw r2,20(sp) - 8c34: d9000417 ldw r4,16(sp) - 8c38: d8c00517 ldw r3,20(sp) - 8c3c: 2105883a add r2,r4,r4 - 8c40: 1085883a add r2,r2,r2 - 8c44: 19000504 addi r4,r3,20 - 8c48: 2085883a add r2,r4,r2 - 8c4c: d8800315 stw r2,12(sp) - 8c50: 2080052e bgeu r4,r2,8c68 <__multiply+0xa4> - 8c54: 2005883a mov r2,r4 - 8c58: d8c00317 ldw r3,12(sp) - 8c5c: 10000015 stw zero,0(r2) - 8c60: 10800104 addi r2,r2,4 - 8c64: 10fffc36 bltu r2,r3,8c58 <__multiply+0x94> - 8c68: 8c45883a add r2,r17,r17 - 8c6c: 9487883a add r3,r18,r18 - 8c70: 9dc00504 addi r23,r19,20 - 8c74: 1085883a add r2,r2,r2 - 8c78: 84000504 addi r16,r16,20 - 8c7c: 18c7883a add r3,r3,r3 - 8c80: b885883a add r2,r23,r2 - 8c84: dc000015 stw r16,0(sp) - 8c88: d8800215 stw r2,8(sp) - 8c8c: 80f9883a add fp,r16,r3 - 8c90: b880432e bgeu r23,r2,8da0 <__multiply+0x1dc> - 8c94: d9000115 stw r4,4(sp) - 8c98: b9000017 ldw r4,0(r23) - 8c9c: 253fffcc andi r20,r4,65535 - 8ca0: a0001a26 beq r20,zero,8d0c <__multiply+0x148> - 8ca4: dcc00017 ldw r19,0(sp) - 8ca8: dc800117 ldw r18,4(sp) - 8cac: 002b883a mov r21,zero - 8cb0: 9c400017 ldw r17,0(r19) - 8cb4: 94000017 ldw r16,0(r18) - 8cb8: a009883a mov r4,r20 - 8cbc: 897fffcc andi r5,r17,65535 - 8cc0: 0002b2c0 call 2b2c <__mulsi3> - 8cc4: 880ad43a srli r5,r17,16 - 8cc8: 80ffffcc andi r3,r16,65535 - 8ccc: a8c7883a add r3,r21,r3 - 8cd0: a009883a mov r4,r20 - 8cd4: 10e3883a add r17,r2,r3 - 8cd8: 8020d43a srli r16,r16,16 - 8cdc: 0002b2c0 call 2b2c <__mulsi3> - 8ce0: 8806d43a srli r3,r17,16 - 8ce4: 1405883a add r2,r2,r16 - 8ce8: 9cc00104 addi r19,r19,4 - 8cec: 1887883a add r3,r3,r2 - 8cf0: 90c0008d sth r3,2(r18) - 8cf4: 9440000d sth r17,0(r18) - 8cf8: 182ad43a srli r21,r3,16 - 8cfc: 94800104 addi r18,r18,4 - 8d00: 9f3feb36 bltu r19,fp,8cb0 <__multiply+0xec> - 8d04: 95400015 stw r21,0(r18) - 8d08: b9000017 ldw r4,0(r23) - 8d0c: 202ad43a srli r21,r4,16 - 8d10: a8001c26 beq r21,zero,8d84 <__multiply+0x1c0> - 8d14: d9000117 ldw r4,4(sp) - 8d18: dd000017 ldw r20,0(sp) - 8d1c: 002d883a mov r22,zero - 8d20: 24c00017 ldw r19,0(r4) - 8d24: 2025883a mov r18,r4 - 8d28: 9823883a mov r17,r19 - 8d2c: a4000017 ldw r16,0(r20) - 8d30: a809883a mov r4,r21 - 8d34: a5000104 addi r20,r20,4 - 8d38: 817fffcc andi r5,r16,65535 - 8d3c: 0002b2c0 call 2b2c <__mulsi3> - 8d40: 8806d43a srli r3,r17,16 - 8d44: 800ad43a srli r5,r16,16 - 8d48: 94c0000d sth r19,0(r18) - 8d4c: b0c7883a add r3,r22,r3 - 8d50: 10e1883a add r16,r2,r3 - 8d54: 9400008d sth r16,2(r18) - 8d58: a809883a mov r4,r21 - 8d5c: 94800104 addi r18,r18,4 - 8d60: 0002b2c0 call 2b2c <__mulsi3> - 8d64: 94400017 ldw r17,0(r18) - 8d68: 8020d43a srli r16,r16,16 - 8d6c: 88ffffcc andi r3,r17,65535 - 8d70: 10c5883a add r2,r2,r3 - 8d74: 80a7883a add r19,r16,r2 - 8d78: 982cd43a srli r22,r19,16 - 8d7c: a73feb36 bltu r20,fp,8d2c <__multiply+0x168> - 8d80: 94c00015 stw r19,0(r18) - 8d84: d8800217 ldw r2,8(sp) - 8d88: bdc00104 addi r23,r23,4 - 8d8c: b880042e bgeu r23,r2,8da0 <__multiply+0x1dc> - 8d90: d8c00117 ldw r3,4(sp) - 8d94: 18c00104 addi r3,r3,4 - 8d98: d8c00115 stw r3,4(sp) - 8d9c: 003fbe06 br 8c98 <__multiply+0xd4> - 8da0: d9000417 ldw r4,16(sp) - 8da4: 01000c0e bge zero,r4,8dd8 <__multiply+0x214> - 8da8: d8c00317 ldw r3,12(sp) - 8dac: 18bfff17 ldw r2,-4(r3) - 8db0: 18ffff04 addi r3,r3,-4 - 8db4: 10000326 beq r2,zero,8dc4 <__multiply+0x200> - 8db8: 00000706 br 8dd8 <__multiply+0x214> - 8dbc: 18800017 ldw r2,0(r3) - 8dc0: 1000051e bne r2,zero,8dd8 <__multiply+0x214> - 8dc4: d9000417 ldw r4,16(sp) - 8dc8: 18ffff04 addi r3,r3,-4 - 8dcc: 213fffc4 addi r4,r4,-1 - 8dd0: d9000415 stw r4,16(sp) - 8dd4: 203ff91e bne r4,zero,8dbc <__multiply+0x1f8> - 8dd8: d8800417 ldw r2,16(sp) - 8ddc: d8c00517 ldw r3,20(sp) - 8de0: 18800415 stw r2,16(r3) - 8de4: 1805883a mov r2,r3 - 8de8: dfc00f17 ldw ra,60(sp) - 8dec: df000e17 ldw fp,56(sp) - 8df0: ddc00d17 ldw r23,52(sp) - 8df4: dd800c17 ldw r22,48(sp) - 8df8: dd400b17 ldw r21,44(sp) - 8dfc: dd000a17 ldw r20,40(sp) - 8e00: dcc00917 ldw r19,36(sp) - 8e04: dc800817 ldw r18,32(sp) - 8e08: dc400717 ldw r17,28(sp) - 8e0c: dc000617 ldw r16,24(sp) - 8e10: dec01004 addi sp,sp,64 - 8e14: f800283a ret - -00008e18 <__i2b>: - 8e18: defffd04 addi sp,sp,-12 - 8e1c: dc000015 stw r16,0(sp) - 8e20: 04000044 movi r16,1 - 8e24: dc800115 stw r18,4(sp) - 8e28: 2825883a mov r18,r5 - 8e2c: 800b883a mov r5,r16 - 8e30: dfc00215 stw ra,8(sp) - 8e34: 00086b40 call 86b4 <_Balloc> - 8e38: 14000415 stw r16,16(r2) - 8e3c: 14800515 stw r18,20(r2) - 8e40: dfc00217 ldw ra,8(sp) - 8e44: dc800117 ldw r18,4(sp) - 8e48: dc000017 ldw r16,0(sp) - 8e4c: dec00304 addi sp,sp,12 - 8e50: f800283a ret - -00008e54 <__multadd>: - 8e54: defff604 addi sp,sp,-40 - 8e58: dd800615 stw r22,24(sp) - 8e5c: 2d800417 ldw r22,16(r5) - 8e60: df000815 stw fp,32(sp) - 8e64: ddc00715 stw r23,28(sp) - 8e68: dd400515 stw r21,20(sp) - 8e6c: dd000415 stw r20,16(sp) - 8e70: dcc00315 stw r19,12(sp) - 8e74: dc800215 stw r18,8(sp) - 8e78: dfc00915 stw ra,36(sp) - 8e7c: dc400115 stw r17,4(sp) - 8e80: dc000015 stw r16,0(sp) - 8e84: 282f883a mov r23,r5 - 8e88: 2039883a mov fp,r4 - 8e8c: 302b883a mov r21,r6 - 8e90: 3829883a mov r20,r7 - 8e94: 2c800504 addi r18,r5,20 - 8e98: 0027883a mov r19,zero - 8e9c: 94400017 ldw r17,0(r18) - 8ea0: a80b883a mov r5,r21 - 8ea4: 9cc00044 addi r19,r19,1 - 8ea8: 893fffcc andi r4,r17,65535 - 8eac: 0002b2c0 call 2b2c <__mulsi3> - 8eb0: 8808d43a srli r4,r17,16 - 8eb4: 1521883a add r16,r2,r20 - 8eb8: a80b883a mov r5,r21 - 8ebc: 0002b2c0 call 2b2c <__mulsi3> - 8ec0: 8008d43a srli r4,r16,16 - 8ec4: 843fffcc andi r16,r16,65535 - 8ec8: 1105883a add r2,r2,r4 - 8ecc: 1006943a slli r3,r2,16 - 8ed0: 1028d43a srli r20,r2,16 - 8ed4: 1c07883a add r3,r3,r16 - 8ed8: 90c00015 stw r3,0(r18) - 8edc: 94800104 addi r18,r18,4 - 8ee0: 9dbfee16 blt r19,r22,8e9c <__multadd+0x48> - 8ee4: a0000826 beq r20,zero,8f08 <__multadd+0xb4> - 8ee8: b8800217 ldw r2,8(r23) - 8eec: b080130e bge r22,r2,8f3c <__multadd+0xe8> - 8ef0: b585883a add r2,r22,r22 - 8ef4: 1085883a add r2,r2,r2 - 8ef8: 15c5883a add r2,r2,r23 - 8efc: b0c00044 addi r3,r22,1 - 8f00: 15000515 stw r20,20(r2) - 8f04: b8c00415 stw r3,16(r23) - 8f08: b805883a mov r2,r23 - 8f0c: dfc00917 ldw ra,36(sp) - 8f10: df000817 ldw fp,32(sp) - 8f14: ddc00717 ldw r23,28(sp) - 8f18: dd800617 ldw r22,24(sp) - 8f1c: dd400517 ldw r21,20(sp) - 8f20: dd000417 ldw r20,16(sp) - 8f24: dcc00317 ldw r19,12(sp) - 8f28: dc800217 ldw r18,8(sp) - 8f2c: dc400117 ldw r17,4(sp) - 8f30: dc000017 ldw r16,0(sp) - 8f34: dec00a04 addi sp,sp,40 - 8f38: f800283a ret - 8f3c: b9400117 ldw r5,4(r23) - 8f40: e009883a mov r4,fp - 8f44: 29400044 addi r5,r5,1 - 8f48: 00086b40 call 86b4 <_Balloc> - 8f4c: b9800417 ldw r6,16(r23) - 8f50: b9400304 addi r5,r23,12 - 8f54: 11000304 addi r4,r2,12 - 8f58: 318d883a add r6,r6,r6 - 8f5c: 318d883a add r6,r6,r6 - 8f60: 31800204 addi r6,r6,8 - 8f64: 1023883a mov r17,r2 - 8f68: 0007f1c0 call 7f1c - 8f6c: b80b883a mov r5,r23 - 8f70: e009883a mov r4,fp - 8f74: 00081340 call 8134 <_Bfree> - 8f78: 882f883a mov r23,r17 - 8f7c: 003fdc06 br 8ef0 <__multadd+0x9c> - -00008f80 <__pow5mult>: - 8f80: defffa04 addi sp,sp,-24 - 8f84: 308000cc andi r2,r6,3 - 8f88: dd000415 stw r20,16(sp) - 8f8c: dcc00315 stw r19,12(sp) - 8f90: dc000015 stw r16,0(sp) - 8f94: dfc00515 stw ra,20(sp) - 8f98: dc800215 stw r18,8(sp) - 8f9c: dc400115 stw r17,4(sp) - 8fa0: 3021883a mov r16,r6 - 8fa4: 2027883a mov r19,r4 - 8fa8: 2829883a mov r20,r5 - 8fac: 10002b1e bne r2,zero,905c <__pow5mult+0xdc> - 8fb0: 8025d0ba srai r18,r16,2 - 8fb4: 90001b26 beq r18,zero,9024 <__pow5mult+0xa4> - 8fb8: 9c001217 ldw r16,72(r19) - 8fbc: 8000081e bne r16,zero,8fe0 <__pow5mult+0x60> - 8fc0: 00003006 br 9084 <__pow5mult+0x104> - 8fc4: 800b883a mov r5,r16 - 8fc8: 800d883a mov r6,r16 - 8fcc: 9809883a mov r4,r19 - 8fd0: 90001426 beq r18,zero,9024 <__pow5mult+0xa4> - 8fd4: 80800017 ldw r2,0(r16) - 8fd8: 10001b26 beq r2,zero,9048 <__pow5mult+0xc8> - 8fdc: 1021883a mov r16,r2 - 8fe0: 9080004c andi r2,r18,1 - 8fe4: 1005003a cmpeq r2,r2,zero - 8fe8: 9025d07a srai r18,r18,1 - 8fec: 800d883a mov r6,r16 - 8ff0: 9809883a mov r4,r19 - 8ff4: a00b883a mov r5,r20 - 8ff8: 103ff21e bne r2,zero,8fc4 <__pow5mult+0x44> - 8ffc: 0008bc40 call 8bc4 <__multiply> - 9000: a00b883a mov r5,r20 - 9004: 9809883a mov r4,r19 - 9008: 1023883a mov r17,r2 - 900c: 00081340 call 8134 <_Bfree> - 9010: 8829883a mov r20,r17 - 9014: 800b883a mov r5,r16 - 9018: 800d883a mov r6,r16 - 901c: 9809883a mov r4,r19 - 9020: 903fec1e bne r18,zero,8fd4 <__pow5mult+0x54> - 9024: a005883a mov r2,r20 - 9028: dfc00517 ldw ra,20(sp) - 902c: dd000417 ldw r20,16(sp) - 9030: dcc00317 ldw r19,12(sp) - 9034: dc800217 ldw r18,8(sp) - 9038: dc400117 ldw r17,4(sp) - 903c: dc000017 ldw r16,0(sp) - 9040: dec00604 addi sp,sp,24 - 9044: f800283a ret - 9048: 0008bc40 call 8bc4 <__multiply> - 904c: 80800015 stw r2,0(r16) - 9050: 1021883a mov r16,r2 - 9054: 10000015 stw zero,0(r2) - 9058: 003fe106 br 8fe0 <__pow5mult+0x60> - 905c: 1085883a add r2,r2,r2 - 9060: 00c00074 movhi r3,1 - 9064: 18c11704 addi r3,r3,1116 - 9068: 1085883a add r2,r2,r2 - 906c: 10c5883a add r2,r2,r3 - 9070: 11bfff17 ldw r6,-4(r2) - 9074: 000f883a mov r7,zero - 9078: 0008e540 call 8e54 <__multadd> - 907c: 1029883a mov r20,r2 - 9080: 003fcb06 br 8fb0 <__pow5mult+0x30> - 9084: 9809883a mov r4,r19 - 9088: 01409c44 movi r5,625 - 908c: 0008e180 call 8e18 <__i2b> - 9090: 98801215 stw r2,72(r19) - 9094: 1021883a mov r16,r2 - 9098: 10000015 stw zero,0(r2) - 909c: 003fd006 br 8fe0 <__pow5mult+0x60> - -000090a0 <__s2b>: - 90a0: defff904 addi sp,sp,-28 - 90a4: dcc00315 stw r19,12(sp) - 90a8: dc800215 stw r18,8(sp) - 90ac: 2827883a mov r19,r5 - 90b0: 2025883a mov r18,r4 - 90b4: 01400244 movi r5,9 - 90b8: 39000204 addi r4,r7,8 - 90bc: dd000415 stw r20,16(sp) - 90c0: dc400115 stw r17,4(sp) - 90c4: dfc00615 stw ra,24(sp) - 90c8: dd400515 stw r21,20(sp) - 90cc: dc000015 stw r16,0(sp) - 90d0: 3829883a mov r20,r7 - 90d4: 3023883a mov r17,r6 - 90d8: 0002a5c0 call 2a5c <__divsi3> - 90dc: 00c00044 movi r3,1 - 90e0: 1880350e bge r3,r2,91b8 <__s2b+0x118> - 90e4: 000b883a mov r5,zero - 90e8: 18c7883a add r3,r3,r3 - 90ec: 29400044 addi r5,r5,1 - 90f0: 18bffd16 blt r3,r2,90e8 <__s2b+0x48> - 90f4: 9009883a mov r4,r18 - 90f8: 00086b40 call 86b4 <_Balloc> - 90fc: 1011883a mov r8,r2 - 9100: d8800717 ldw r2,28(sp) - 9104: 00c00044 movi r3,1 - 9108: 01800244 movi r6,9 - 910c: 40800515 stw r2,20(r8) - 9110: 40c00415 stw r3,16(r8) - 9114: 3440260e bge r6,r17,91b0 <__s2b+0x110> - 9118: 3021883a mov r16,r6 - 911c: 99ab883a add r21,r19,r6 - 9120: 9c05883a add r2,r19,r16 - 9124: 11c00007 ldb r7,0(r2) - 9128: 400b883a mov r5,r8 - 912c: 9009883a mov r4,r18 - 9130: 39fff404 addi r7,r7,-48 - 9134: 01800284 movi r6,10 - 9138: 0008e540 call 8e54 <__multadd> - 913c: 84000044 addi r16,r16,1 - 9140: 1011883a mov r8,r2 - 9144: 8c3ff61e bne r17,r16,9120 <__s2b+0x80> - 9148: ac45883a add r2,r21,r17 - 914c: 117ffe04 addi r5,r2,-8 - 9150: 880d883a mov r6,r17 - 9154: 35000c0e bge r6,r20,9188 <__s2b+0xe8> - 9158: a185c83a sub r2,r20,r6 - 915c: 2821883a mov r16,r5 - 9160: 28a3883a add r17,r5,r2 - 9164: 81c00007 ldb r7,0(r16) - 9168: 400b883a mov r5,r8 - 916c: 9009883a mov r4,r18 - 9170: 39fff404 addi r7,r7,-48 - 9174: 01800284 movi r6,10 - 9178: 0008e540 call 8e54 <__multadd> - 917c: 84000044 addi r16,r16,1 - 9180: 1011883a mov r8,r2 - 9184: 847ff71e bne r16,r17,9164 <__s2b+0xc4> - 9188: 4005883a mov r2,r8 - 918c: dfc00617 ldw ra,24(sp) - 9190: dd400517 ldw r21,20(sp) - 9194: dd000417 ldw r20,16(sp) - 9198: dcc00317 ldw r19,12(sp) - 919c: dc800217 ldw r18,8(sp) - 91a0: dc400117 ldw r17,4(sp) - 91a4: dc000017 ldw r16,0(sp) - 91a8: dec00704 addi sp,sp,28 - 91ac: f800283a ret - 91b0: 99400284 addi r5,r19,10 - 91b4: 003fe706 br 9154 <__s2b+0xb4> - 91b8: 000b883a mov r5,zero - 91bc: 003fcd06 br 90f4 <__s2b+0x54> - -000091c0 <_realloc_r>: - 91c0: defff404 addi sp,sp,-48 - 91c4: dd800815 stw r22,32(sp) - 91c8: dc800415 stw r18,16(sp) - 91cc: dc400315 stw r17,12(sp) - 91d0: dfc00b15 stw ra,44(sp) - 91d4: df000a15 stw fp,40(sp) - 91d8: ddc00915 stw r23,36(sp) - 91dc: dd400715 stw r21,28(sp) - 91e0: dd000615 stw r20,24(sp) - 91e4: dcc00515 stw r19,20(sp) - 91e8: dc000215 stw r16,8(sp) - 91ec: 2825883a mov r18,r5 - 91f0: 3023883a mov r17,r6 - 91f4: 202d883a mov r22,r4 - 91f8: 2800c926 beq r5,zero,9520 <_realloc_r+0x360> - 91fc: 000ca880 call ca88 <__malloc_lock> - 9200: 943ffe04 addi r16,r18,-8 - 9204: 88c002c4 addi r3,r17,11 - 9208: 00800584 movi r2,22 - 920c: 82000117 ldw r8,4(r16) - 9210: 10c01b2e bgeu r2,r3,9280 <_realloc_r+0xc0> - 9214: 00bffe04 movi r2,-8 - 9218: 188e703a and r7,r3,r2 - 921c: 3839883a mov fp,r7 - 9220: 38001a16 blt r7,zero,928c <_realloc_r+0xcc> - 9224: e4401936 bltu fp,r17,928c <_realloc_r+0xcc> - 9228: 013fff04 movi r4,-4 - 922c: 4126703a and r19,r8,r4 - 9230: 99c02616 blt r19,r7,92cc <_realloc_r+0x10c> - 9234: 802b883a mov r21,r16 - 9238: 9829883a mov r20,r19 - 923c: 84000204 addi r16,r16,8 - 9240: a80f883a mov r7,r21 - 9244: a70dc83a sub r6,r20,fp - 9248: 008003c4 movi r2,15 - 924c: 1180c136 bltu r2,r6,9554 <_realloc_r+0x394> - 9250: 38800117 ldw r2,4(r7) - 9254: a549883a add r4,r20,r21 - 9258: 1080004c andi r2,r2,1 - 925c: a084b03a or r2,r20,r2 - 9260: 38800115 stw r2,4(r7) - 9264: 20c00117 ldw r3,4(r4) - 9268: 18c00054 ori r3,r3,1 - 926c: 20c00115 stw r3,4(r4) - 9270: b009883a mov r4,r22 - 9274: 000caa80 call caa8 <__malloc_unlock> - 9278: 8023883a mov r17,r16 - 927c: 00000606 br 9298 <_realloc_r+0xd8> - 9280: 01c00404 movi r7,16 - 9284: 3839883a mov fp,r7 - 9288: e47fe72e bgeu fp,r17,9228 <_realloc_r+0x68> - 928c: 00800304 movi r2,12 - 9290: 0023883a mov r17,zero - 9294: b0800015 stw r2,0(r22) - 9298: 8805883a mov r2,r17 - 929c: dfc00b17 ldw ra,44(sp) - 92a0: df000a17 ldw fp,40(sp) - 92a4: ddc00917 ldw r23,36(sp) - 92a8: dd800817 ldw r22,32(sp) - 92ac: dd400717 ldw r21,28(sp) - 92b0: dd000617 ldw r20,24(sp) - 92b4: dcc00517 ldw r19,20(sp) - 92b8: dc800417 ldw r18,16(sp) - 92bc: dc400317 ldw r17,12(sp) - 92c0: dc000217 ldw r16,8(sp) - 92c4: dec00c04 addi sp,sp,48 - 92c8: f800283a ret - 92cc: 00800074 movhi r2,1 - 92d0: 10827204 addi r2,r2,2504 - 92d4: 12400217 ldw r9,8(r2) - 92d8: 84cd883a add r6,r16,r19 - 92dc: 802b883a mov r21,r16 - 92e0: 3240b926 beq r6,r9,95c8 <_realloc_r+0x408> - 92e4: 31400117 ldw r5,4(r6) - 92e8: 00bfff84 movi r2,-2 - 92ec: 2884703a and r2,r5,r2 - 92f0: 1185883a add r2,r2,r6 - 92f4: 10c00117 ldw r3,4(r2) - 92f8: 18c0004c andi r3,r3,1 - 92fc: 1807003a cmpeq r3,r3,zero - 9300: 1800a326 beq r3,zero,9590 <_realloc_r+0x3d0> - 9304: 2908703a and r4,r5,r4 - 9308: 9929883a add r20,r19,r4 - 930c: a1c0a30e bge r20,r7,959c <_realloc_r+0x3dc> - 9310: 4080004c andi r2,r8,1 - 9314: 1000551e bne r2,zero,946c <_realloc_r+0x2ac> - 9318: 80800017 ldw r2,0(r16) - 931c: 80afc83a sub r23,r16,r2 - 9320: b8c00117 ldw r3,4(r23) - 9324: 00bfff04 movi r2,-4 - 9328: 1884703a and r2,r3,r2 - 932c: 30002e26 beq r6,zero,93e8 <_realloc_r+0x228> - 9330: 3240b926 beq r6,r9,9618 <_realloc_r+0x458> - 9334: 98a9883a add r20,r19,r2 - 9338: 2509883a add r4,r4,r20 - 933c: d9000015 stw r4,0(sp) - 9340: 21c02a16 blt r4,r7,93ec <_realloc_r+0x22c> - 9344: 30800317 ldw r2,12(r6) - 9348: 30c00217 ldw r3,8(r6) - 934c: 01400904 movi r5,36 - 9350: 99bfff04 addi r6,r19,-4 - 9354: 18800315 stw r2,12(r3) - 9358: 10c00215 stw r3,8(r2) - 935c: b9000317 ldw r4,12(r23) - 9360: b8800217 ldw r2,8(r23) - 9364: b82b883a mov r21,r23 - 9368: bc000204 addi r16,r23,8 - 936c: 20800215 stw r2,8(r4) - 9370: 11000315 stw r4,12(r2) - 9374: 2980e436 bltu r5,r6,9708 <_realloc_r+0x548> - 9378: 008004c4 movi r2,19 - 937c: 9009883a mov r4,r18 - 9380: 8011883a mov r8,r16 - 9384: 11800f2e bgeu r2,r6,93c4 <_realloc_r+0x204> - 9388: 90800017 ldw r2,0(r18) - 938c: ba000404 addi r8,r23,16 - 9390: 91000204 addi r4,r18,8 - 9394: b8800215 stw r2,8(r23) - 9398: 90c00117 ldw r3,4(r18) - 939c: 008006c4 movi r2,27 - 93a0: b8c00315 stw r3,12(r23) - 93a4: 1180072e bgeu r2,r6,93c4 <_realloc_r+0x204> - 93a8: 90c00217 ldw r3,8(r18) - 93ac: ba000604 addi r8,r23,24 - 93b0: 91000404 addi r4,r18,16 - 93b4: b8c00415 stw r3,16(r23) - 93b8: 90800317 ldw r2,12(r18) - 93bc: b8800515 stw r2,20(r23) - 93c0: 3140e726 beq r6,r5,9760 <_realloc_r+0x5a0> - 93c4: 20800017 ldw r2,0(r4) - 93c8: dd000017 ldw r20,0(sp) - 93cc: b80f883a mov r7,r23 - 93d0: 40800015 stw r2,0(r8) - 93d4: 20c00117 ldw r3,4(r4) - 93d8: 40c00115 stw r3,4(r8) - 93dc: 20800217 ldw r2,8(r4) - 93e0: 40800215 stw r2,8(r8) - 93e4: 003f9706 br 9244 <_realloc_r+0x84> - 93e8: 98a9883a add r20,r19,r2 - 93ec: a1c01f16 blt r20,r7,946c <_realloc_r+0x2ac> - 93f0: b8c00317 ldw r3,12(r23) - 93f4: b8800217 ldw r2,8(r23) - 93f8: 99bfff04 addi r6,r19,-4 - 93fc: 01400904 movi r5,36 - 9400: b82b883a mov r21,r23 - 9404: 18800215 stw r2,8(r3) - 9408: 10c00315 stw r3,12(r2) - 940c: bc000204 addi r16,r23,8 - 9410: 2980c336 bltu r5,r6,9720 <_realloc_r+0x560> - 9414: 008004c4 movi r2,19 - 9418: 9009883a mov r4,r18 - 941c: 8011883a mov r8,r16 - 9420: 11800f2e bgeu r2,r6,9460 <_realloc_r+0x2a0> - 9424: 90800017 ldw r2,0(r18) - 9428: ba000404 addi r8,r23,16 - 942c: 91000204 addi r4,r18,8 - 9430: b8800215 stw r2,8(r23) - 9434: 90c00117 ldw r3,4(r18) - 9438: 008006c4 movi r2,27 - 943c: b8c00315 stw r3,12(r23) - 9440: 1180072e bgeu r2,r6,9460 <_realloc_r+0x2a0> - 9444: 90c00217 ldw r3,8(r18) - 9448: ba000604 addi r8,r23,24 - 944c: 91000404 addi r4,r18,16 - 9450: b8c00415 stw r3,16(r23) - 9454: 90800317 ldw r2,12(r18) - 9458: b8800515 stw r2,20(r23) - 945c: 3140c726 beq r6,r5,977c <_realloc_r+0x5bc> - 9460: 20800017 ldw r2,0(r4) - 9464: b80f883a mov r7,r23 - 9468: 003fd906 br 93d0 <_realloc_r+0x210> - 946c: 880b883a mov r5,r17 - 9470: b009883a mov r4,r22 - 9474: 00076f80 call 76f8 <_malloc_r> - 9478: 1023883a mov r17,r2 - 947c: 10002526 beq r2,zero,9514 <_realloc_r+0x354> - 9480: 80800117 ldw r2,4(r16) - 9484: 00ffff84 movi r3,-2 - 9488: 893ffe04 addi r4,r17,-8 - 948c: 10c4703a and r2,r2,r3 - 9490: 8085883a add r2,r16,r2 - 9494: 20809526 beq r4,r2,96ec <_realloc_r+0x52c> - 9498: 99bfff04 addi r6,r19,-4 - 949c: 01c00904 movi r7,36 - 94a0: 39804536 bltu r7,r6,95b8 <_realloc_r+0x3f8> - 94a4: 008004c4 movi r2,19 - 94a8: 9009883a mov r4,r18 - 94ac: 880b883a mov r5,r17 - 94b0: 11800f2e bgeu r2,r6,94f0 <_realloc_r+0x330> - 94b4: 90800017 ldw r2,0(r18) - 94b8: 89400204 addi r5,r17,8 - 94bc: 91000204 addi r4,r18,8 - 94c0: 88800015 stw r2,0(r17) - 94c4: 90c00117 ldw r3,4(r18) - 94c8: 008006c4 movi r2,27 - 94cc: 88c00115 stw r3,4(r17) - 94d0: 1180072e bgeu r2,r6,94f0 <_realloc_r+0x330> - 94d4: 90c00217 ldw r3,8(r18) - 94d8: 89400404 addi r5,r17,16 - 94dc: 91000404 addi r4,r18,16 - 94e0: 88c00215 stw r3,8(r17) - 94e4: 90800317 ldw r2,12(r18) - 94e8: 88800315 stw r2,12(r17) - 94ec: 31c09126 beq r6,r7,9734 <_realloc_r+0x574> - 94f0: 20800017 ldw r2,0(r4) - 94f4: 28800015 stw r2,0(r5) - 94f8: 20c00117 ldw r3,4(r4) - 94fc: 28c00115 stw r3,4(r5) - 9500: 20800217 ldw r2,8(r4) - 9504: 28800215 stw r2,8(r5) - 9508: 900b883a mov r5,r18 - 950c: b009883a mov r4,r22 - 9510: 0006b700 call 6b70 <_free_r> - 9514: b009883a mov r4,r22 - 9518: 000caa80 call caa8 <__malloc_unlock> - 951c: 003f5e06 br 9298 <_realloc_r+0xd8> - 9520: 300b883a mov r5,r6 - 9524: dfc00b17 ldw ra,44(sp) - 9528: df000a17 ldw fp,40(sp) - 952c: ddc00917 ldw r23,36(sp) - 9530: dd800817 ldw r22,32(sp) - 9534: dd400717 ldw r21,28(sp) - 9538: dd000617 ldw r20,24(sp) - 953c: dcc00517 ldw r19,20(sp) - 9540: dc800417 ldw r18,16(sp) - 9544: dc400317 ldw r17,12(sp) - 9548: dc000217 ldw r16,8(sp) - 954c: dec00c04 addi sp,sp,48 - 9550: 00076f81 jmpi 76f8 <_malloc_r> - 9554: 38800117 ldw r2,4(r7) - 9558: e54b883a add r5,fp,r21 - 955c: 31000054 ori r4,r6,1 - 9560: 1080004c andi r2,r2,1 - 9564: 1704b03a or r2,r2,fp - 9568: 38800115 stw r2,4(r7) - 956c: 29000115 stw r4,4(r5) - 9570: 2987883a add r3,r5,r6 - 9574: 18800117 ldw r2,4(r3) - 9578: 29400204 addi r5,r5,8 - 957c: b009883a mov r4,r22 - 9580: 10800054 ori r2,r2,1 - 9584: 18800115 stw r2,4(r3) - 9588: 0006b700 call 6b70 <_free_r> - 958c: 003f3806 br 9270 <_realloc_r+0xb0> - 9590: 000d883a mov r6,zero - 9594: 0009883a mov r4,zero - 9598: 003f5d06 br 9310 <_realloc_r+0x150> - 959c: 30c00217 ldw r3,8(r6) - 95a0: 30800317 ldw r2,12(r6) - 95a4: 800f883a mov r7,r16 - 95a8: 84000204 addi r16,r16,8 - 95ac: 10c00215 stw r3,8(r2) - 95b0: 18800315 stw r2,12(r3) - 95b4: 003f2306 br 9244 <_realloc_r+0x84> - 95b8: 8809883a mov r4,r17 - 95bc: 900b883a mov r5,r18 - 95c0: 0007fbc0 call 7fbc - 95c4: 003fd006 br 9508 <_realloc_r+0x348> - 95c8: 30800117 ldw r2,4(r6) - 95cc: e0c00404 addi r3,fp,16 - 95d0: 1108703a and r4,r2,r4 - 95d4: 9905883a add r2,r19,r4 - 95d8: 10ff4d16 blt r2,r3,9310 <_realloc_r+0x150> - 95dc: 1705c83a sub r2,r2,fp - 95e0: 870b883a add r5,r16,fp - 95e4: 10800054 ori r2,r2,1 - 95e8: 28800115 stw r2,4(r5) - 95ec: 80c00117 ldw r3,4(r16) - 95f0: 00800074 movhi r2,1 - 95f4: 10827204 addi r2,r2,2504 - 95f8: b009883a mov r4,r22 - 95fc: 18c0004c andi r3,r3,1 - 9600: e0c6b03a or r3,fp,r3 - 9604: 11400215 stw r5,8(r2) - 9608: 80c00115 stw r3,4(r16) - 960c: 000caa80 call caa8 <__malloc_unlock> - 9610: 84400204 addi r17,r16,8 - 9614: 003f2006 br 9298 <_realloc_r+0xd8> - 9618: 98a9883a add r20,r19,r2 - 961c: 2509883a add r4,r4,r20 - 9620: e0800404 addi r2,fp,16 - 9624: d9000115 stw r4,4(sp) - 9628: 20bf7016 blt r4,r2,93ec <_realloc_r+0x22c> - 962c: b8c00317 ldw r3,12(r23) - 9630: b8800217 ldw r2,8(r23) - 9634: 99bfff04 addi r6,r19,-4 - 9638: 01400904 movi r5,36 - 963c: 18800215 stw r2,8(r3) - 9640: 10c00315 stw r3,12(r2) - 9644: bc400204 addi r17,r23,8 - 9648: 29804136 bltu r5,r6,9750 <_realloc_r+0x590> - 964c: 008004c4 movi r2,19 - 9650: 9009883a mov r4,r18 - 9654: 880f883a mov r7,r17 - 9658: 11800f2e bgeu r2,r6,9698 <_realloc_r+0x4d8> - 965c: 90800017 ldw r2,0(r18) - 9660: b9c00404 addi r7,r23,16 - 9664: 91000204 addi r4,r18,8 - 9668: b8800215 stw r2,8(r23) - 966c: 90c00117 ldw r3,4(r18) - 9670: 008006c4 movi r2,27 - 9674: b8c00315 stw r3,12(r23) - 9678: 1180072e bgeu r2,r6,9698 <_realloc_r+0x4d8> - 967c: 90c00217 ldw r3,8(r18) - 9680: b9c00604 addi r7,r23,24 - 9684: 91000404 addi r4,r18,16 - 9688: b8c00415 stw r3,16(r23) - 968c: 90800317 ldw r2,12(r18) - 9690: b8800515 stw r2,20(r23) - 9694: 31404026 beq r6,r5,9798 <_realloc_r+0x5d8> - 9698: 20800017 ldw r2,0(r4) - 969c: 38800015 stw r2,0(r7) - 96a0: 20c00117 ldw r3,4(r4) - 96a4: 38c00115 stw r3,4(r7) - 96a8: 20800217 ldw r2,8(r4) - 96ac: 38800215 stw r2,8(r7) - 96b0: d8c00117 ldw r3,4(sp) - 96b4: bf0b883a add r5,r23,fp - 96b8: b009883a mov r4,r22 - 96bc: 1f05c83a sub r2,r3,fp - 96c0: 10800054 ori r2,r2,1 - 96c4: 28800115 stw r2,4(r5) - 96c8: b8c00117 ldw r3,4(r23) - 96cc: 00800074 movhi r2,1 - 96d0: 10827204 addi r2,r2,2504 - 96d4: 11400215 stw r5,8(r2) - 96d8: 18c0004c andi r3,r3,1 - 96dc: e0c6b03a or r3,fp,r3 - 96e0: b8c00115 stw r3,4(r23) - 96e4: 000caa80 call caa8 <__malloc_unlock> - 96e8: 003eeb06 br 9298 <_realloc_r+0xd8> - 96ec: 20800117 ldw r2,4(r4) - 96f0: 00ffff04 movi r3,-4 - 96f4: 800f883a mov r7,r16 - 96f8: 10c4703a and r2,r2,r3 - 96fc: 98a9883a add r20,r19,r2 - 9700: 84000204 addi r16,r16,8 - 9704: 003ecf06 br 9244 <_realloc_r+0x84> - 9708: 900b883a mov r5,r18 - 970c: 8009883a mov r4,r16 - 9710: 0007fbc0 call 7fbc - 9714: dd000017 ldw r20,0(sp) - 9718: b80f883a mov r7,r23 - 971c: 003ec906 br 9244 <_realloc_r+0x84> - 9720: 900b883a mov r5,r18 - 9724: 8009883a mov r4,r16 - 9728: 0007fbc0 call 7fbc - 972c: b80f883a mov r7,r23 - 9730: 003ec406 br 9244 <_realloc_r+0x84> - 9734: 90c00417 ldw r3,16(r18) - 9738: 89400604 addi r5,r17,24 - 973c: 91000604 addi r4,r18,24 - 9740: 88c00415 stw r3,16(r17) - 9744: 90800517 ldw r2,20(r18) - 9748: 88800515 stw r2,20(r17) - 974c: 003f6806 br 94f0 <_realloc_r+0x330> - 9750: 900b883a mov r5,r18 - 9754: 8809883a mov r4,r17 - 9758: 0007fbc0 call 7fbc - 975c: 003fd406 br 96b0 <_realloc_r+0x4f0> - 9760: 90c00417 ldw r3,16(r18) - 9764: 91000604 addi r4,r18,24 - 9768: ba000804 addi r8,r23,32 - 976c: b8c00615 stw r3,24(r23) - 9770: 90800517 ldw r2,20(r18) - 9774: b8800715 stw r2,28(r23) - 9778: 003f1206 br 93c4 <_realloc_r+0x204> - 977c: 90c00417 ldw r3,16(r18) - 9780: 91000604 addi r4,r18,24 - 9784: ba000804 addi r8,r23,32 - 9788: b8c00615 stw r3,24(r23) - 978c: 90800517 ldw r2,20(r18) - 9790: b8800715 stw r2,28(r23) - 9794: 003f3206 br 9460 <_realloc_r+0x2a0> - 9798: 90c00417 ldw r3,16(r18) - 979c: 91000604 addi r4,r18,24 - 97a0: b9c00804 addi r7,r23,32 - 97a4: b8c00615 stw r3,24(r23) - 97a8: 90800517 ldw r2,20(r18) - 97ac: b8800715 stw r2,28(r23) - 97b0: 003fb906 br 9698 <_realloc_r+0x4d8> - -000097b4 <__isinfd>: - 97b4: 200d883a mov r6,r4 - 97b8: 0109c83a sub r4,zero,r4 - 97bc: 2188b03a or r4,r4,r6 - 97c0: 2008d7fa srli r4,r4,31 - 97c4: 00a00034 movhi r2,32768 - 97c8: 10bfffc4 addi r2,r2,-1 - 97cc: 1144703a and r2,r2,r5 - 97d0: 2088b03a or r4,r4,r2 - 97d4: 009ffc34 movhi r2,32752 - 97d8: 1105c83a sub r2,r2,r4 - 97dc: 0087c83a sub r3,zero,r2 - 97e0: 10c4b03a or r2,r2,r3 - 97e4: 1004d7fa srli r2,r2,31 - 97e8: 00c00044 movi r3,1 - 97ec: 1885c83a sub r2,r3,r2 - 97f0: f800283a ret - -000097f4 <__isnand>: - 97f4: 200d883a mov r6,r4 - 97f8: 0109c83a sub r4,zero,r4 - 97fc: 2188b03a or r4,r4,r6 - 9800: 2008d7fa srli r4,r4,31 - 9804: 00a00034 movhi r2,32768 - 9808: 10bfffc4 addi r2,r2,-1 - 980c: 1144703a and r2,r2,r5 - 9810: 2088b03a or r4,r4,r2 - 9814: 009ffc34 movhi r2,32752 - 9818: 1105c83a sub r2,r2,r4 - 981c: 1004d7fa srli r2,r2,31 - 9820: f800283a ret - -00009824 <_sbrk_r>: - 9824: defffd04 addi sp,sp,-12 - 9828: dc000015 stw r16,0(sp) - 982c: 04000074 movhi r16,1 - 9830: 840f3e04 addi r16,r16,15608 - 9834: dc400115 stw r17,4(sp) - 9838: 80000015 stw zero,0(r16) - 983c: 2023883a mov r17,r4 - 9840: 2809883a mov r4,r5 - 9844: dfc00215 stw ra,8(sp) - 9848: 000ccc40 call ccc4 - 984c: 1007883a mov r3,r2 - 9850: 00bfffc4 movi r2,-1 - 9854: 18800626 beq r3,r2,9870 <_sbrk_r+0x4c> - 9858: 1805883a mov r2,r3 - 985c: dfc00217 ldw ra,8(sp) - 9860: dc400117 ldw r17,4(sp) - 9864: dc000017 ldw r16,0(sp) - 9868: dec00304 addi sp,sp,12 - 986c: f800283a ret - 9870: 80800017 ldw r2,0(r16) - 9874: 103ff826 beq r2,zero,9858 <_sbrk_r+0x34> - 9878: 88800015 stw r2,0(r17) - 987c: 1805883a mov r2,r3 - 9880: dfc00217 ldw ra,8(sp) - 9884: dc400117 ldw r17,4(sp) - 9888: dc000017 ldw r16,0(sp) - 988c: dec00304 addi sp,sp,12 - 9890: f800283a ret - -00009894 <__sclose>: - 9894: 2940038f ldh r5,14(r5) - 9898: 0009bdc1 jmpi 9bdc <_close_r> - -0000989c <__sseek>: - 989c: defffe04 addi sp,sp,-8 - 98a0: dc000015 stw r16,0(sp) - 98a4: 2821883a mov r16,r5 - 98a8: 2940038f ldh r5,14(r5) - 98ac: dfc00115 stw ra,4(sp) - 98b0: 0009e540 call 9e54 <_lseek_r> - 98b4: 1007883a mov r3,r2 - 98b8: 00bfffc4 movi r2,-1 - 98bc: 18800926 beq r3,r2,98e4 <__sseek+0x48> - 98c0: 8080030b ldhu r2,12(r16) - 98c4: 80c01415 stw r3,80(r16) - 98c8: 10840014 ori r2,r2,4096 - 98cc: 8080030d sth r2,12(r16) - 98d0: 1805883a mov r2,r3 - 98d4: dfc00117 ldw ra,4(sp) - 98d8: dc000017 ldw r16,0(sp) - 98dc: dec00204 addi sp,sp,8 - 98e0: f800283a ret - 98e4: 8080030b ldhu r2,12(r16) - 98e8: 10bbffcc andi r2,r2,61439 - 98ec: 8080030d sth r2,12(r16) - 98f0: 1805883a mov r2,r3 - 98f4: dfc00117 ldw ra,4(sp) - 98f8: dc000017 ldw r16,0(sp) - 98fc: dec00204 addi sp,sp,8 - 9900: f800283a ret - -00009904 <__swrite>: - 9904: 2880030b ldhu r2,12(r5) - 9908: defffb04 addi sp,sp,-20 - 990c: dcc00315 stw r19,12(sp) - 9910: 1080400c andi r2,r2,256 - 9914: dc800215 stw r18,8(sp) - 9918: dc400115 stw r17,4(sp) - 991c: dc000015 stw r16,0(sp) - 9920: 3027883a mov r19,r6 - 9924: 3825883a mov r18,r7 - 9928: dfc00415 stw ra,16(sp) - 992c: 2821883a mov r16,r5 - 9930: 000d883a mov r6,zero - 9934: 01c00084 movi r7,2 - 9938: 2023883a mov r17,r4 - 993c: 10000226 beq r2,zero,9948 <__swrite+0x44> - 9940: 2940038f ldh r5,14(r5) - 9944: 0009e540 call 9e54 <_lseek_r> - 9948: 8080030b ldhu r2,12(r16) - 994c: 8140038f ldh r5,14(r16) - 9950: 8809883a mov r4,r17 - 9954: 10bbffcc andi r2,r2,61439 - 9958: 980d883a mov r6,r19 - 995c: 900f883a mov r7,r18 - 9960: 8080030d sth r2,12(r16) - 9964: dfc00417 ldw ra,16(sp) - 9968: dcc00317 ldw r19,12(sp) - 996c: dc800217 ldw r18,8(sp) - 9970: dc400117 ldw r17,4(sp) - 9974: dc000017 ldw r16,0(sp) - 9978: dec00504 addi sp,sp,20 - 997c: 0009a9c1 jmpi 9a9c <_write_r> - -00009980 <__sread>: - 9980: defffe04 addi sp,sp,-8 - 9984: dc000015 stw r16,0(sp) - 9988: 2821883a mov r16,r5 - 998c: 2940038f ldh r5,14(r5) - 9990: dfc00115 stw ra,4(sp) - 9994: 0009ecc0 call 9ecc <_read_r> - 9998: 1007883a mov r3,r2 - 999c: 10000816 blt r2,zero,99c0 <__sread+0x40> - 99a0: 80801417 ldw r2,80(r16) - 99a4: 10c5883a add r2,r2,r3 - 99a8: 80801415 stw r2,80(r16) - 99ac: 1805883a mov r2,r3 - 99b0: dfc00117 ldw ra,4(sp) - 99b4: dc000017 ldw r16,0(sp) - 99b8: dec00204 addi sp,sp,8 - 99bc: f800283a ret - 99c0: 8080030b ldhu r2,12(r16) - 99c4: 10bbffcc andi r2,r2,61439 - 99c8: 8080030d sth r2,12(r16) - 99cc: 1805883a mov r2,r3 - 99d0: dfc00117 ldw ra,4(sp) - 99d4: dc000017 ldw r16,0(sp) - 99d8: dec00204 addi sp,sp,8 - 99dc: f800283a ret - -000099e0 : - 99e0: 2144b03a or r2,r4,r5 - 99e4: 108000cc andi r2,r2,3 - 99e8: 10001d1e bne r2,zero,9a60 - 99ec: 200f883a mov r7,r4 - 99f0: 28800017 ldw r2,0(r5) - 99f4: 21000017 ldw r4,0(r4) - 99f8: 280d883a mov r6,r5 - 99fc: 2080161e bne r4,r2,9a58 - 9a00: 023fbff4 movhi r8,65279 - 9a04: 423fbfc4 addi r8,r8,-257 - 9a08: 2207883a add r3,r4,r8 - 9a0c: 01602074 movhi r5,32897 - 9a10: 29602004 addi r5,r5,-32640 - 9a14: 1946703a and r3,r3,r5 - 9a18: 0104303a nor r2,zero,r4 - 9a1c: 10c4703a and r2,r2,r3 - 9a20: 10001c1e bne r2,zero,9a94 - 9a24: 4013883a mov r9,r8 - 9a28: 2811883a mov r8,r5 - 9a2c: 00000106 br 9a34 - 9a30: 1800181e bne r3,zero,9a94 - 9a34: 39c00104 addi r7,r7,4 - 9a38: 39000017 ldw r4,0(r7) - 9a3c: 31800104 addi r6,r6,4 - 9a40: 31400017 ldw r5,0(r6) - 9a44: 2245883a add r2,r4,r9 - 9a48: 1204703a and r2,r2,r8 - 9a4c: 0106303a nor r3,zero,r4 - 9a50: 1886703a and r3,r3,r2 - 9a54: 217ff626 beq r4,r5,9a30 - 9a58: 3809883a mov r4,r7 - 9a5c: 300b883a mov r5,r6 - 9a60: 20c00007 ldb r3,0(r4) - 9a64: 1800051e bne r3,zero,9a7c - 9a68: 00000606 br 9a84 - 9a6c: 21000044 addi r4,r4,1 - 9a70: 20c00007 ldb r3,0(r4) - 9a74: 29400044 addi r5,r5,1 - 9a78: 18000226 beq r3,zero,9a84 - 9a7c: 28800007 ldb r2,0(r5) - 9a80: 18bffa26 beq r3,r2,9a6c - 9a84: 20c00003 ldbu r3,0(r4) - 9a88: 28800003 ldbu r2,0(r5) - 9a8c: 1885c83a sub r2,r3,r2 - 9a90: f800283a ret - 9a94: 0005883a mov r2,zero - 9a98: f800283a ret - -00009a9c <_write_r>: - 9a9c: defffd04 addi sp,sp,-12 - 9aa0: dc000015 stw r16,0(sp) - 9aa4: 04000074 movhi r16,1 - 9aa8: 840f3e04 addi r16,r16,15608 - 9aac: dc400115 stw r17,4(sp) - 9ab0: 80000015 stw zero,0(r16) - 9ab4: 2023883a mov r17,r4 - 9ab8: 2809883a mov r4,r5 - 9abc: 300b883a mov r5,r6 - 9ac0: 380d883a mov r6,r7 - 9ac4: dfc00215 stw ra,8(sp) - 9ac8: 000cdb00 call cdb0 - 9acc: 1007883a mov r3,r2 - 9ad0: 00bfffc4 movi r2,-1 - 9ad4: 18800626 beq r3,r2,9af0 <_write_r+0x54> - 9ad8: 1805883a mov r2,r3 - 9adc: dfc00217 ldw ra,8(sp) - 9ae0: dc400117 ldw r17,4(sp) - 9ae4: dc000017 ldw r16,0(sp) - 9ae8: dec00304 addi sp,sp,12 - 9aec: f800283a ret - 9af0: 80800017 ldw r2,0(r16) - 9af4: 103ff826 beq r2,zero,9ad8 <_write_r+0x3c> - 9af8: 88800015 stw r2,0(r17) - 9afc: 1805883a mov r2,r3 - 9b00: dfc00217 ldw ra,8(sp) - 9b04: dc400117 ldw r17,4(sp) - 9b08: dc000017 ldw r16,0(sp) - 9b0c: dec00304 addi sp,sp,12 - 9b10: f800283a ret - -00009b14 <_calloc_r>: - 9b14: defffe04 addi sp,sp,-8 - 9b18: dc400015 stw r17,0(sp) - 9b1c: 2023883a mov r17,r4 - 9b20: 2809883a mov r4,r5 - 9b24: 300b883a mov r5,r6 - 9b28: dfc00115 stw ra,4(sp) - 9b2c: 0002b2c0 call 2b2c <__mulsi3> - 9b30: 100b883a mov r5,r2 - 9b34: 8809883a mov r4,r17 - 9b38: 00076f80 call 76f8 <_malloc_r> - 9b3c: 1023883a mov r17,r2 - 9b40: 01c00904 movi r7,36 - 9b44: 10000d26 beq r2,zero,9b7c <_calloc_r+0x68> - 9b48: 10ffff17 ldw r3,-4(r2) - 9b4c: 1009883a mov r4,r2 - 9b50: 00bfff04 movi r2,-4 - 9b54: 1886703a and r3,r3,r2 - 9b58: 1887883a add r3,r3,r2 - 9b5c: 180d883a mov r6,r3 - 9b60: 000b883a mov r5,zero - 9b64: 38c01736 bltu r7,r3,9bc4 <_calloc_r+0xb0> - 9b68: 008004c4 movi r2,19 - 9b6c: 10c00836 bltu r2,r3,9b90 <_calloc_r+0x7c> - 9b70: 20000215 stw zero,8(r4) - 9b74: 20000015 stw zero,0(r4) - 9b78: 20000115 stw zero,4(r4) - 9b7c: 8805883a mov r2,r17 - 9b80: dfc00117 ldw ra,4(sp) - 9b84: dc400017 ldw r17,0(sp) - 9b88: dec00204 addi sp,sp,8 - 9b8c: f800283a ret - 9b90: 008006c4 movi r2,27 - 9b94: 88000015 stw zero,0(r17) - 9b98: 88000115 stw zero,4(r17) - 9b9c: 89000204 addi r4,r17,8 - 9ba0: 10fff32e bgeu r2,r3,9b70 <_calloc_r+0x5c> - 9ba4: 88000215 stw zero,8(r17) - 9ba8: 88000315 stw zero,12(r17) - 9bac: 89000404 addi r4,r17,16 - 9bb0: 19ffef1e bne r3,r7,9b70 <_calloc_r+0x5c> - 9bb4: 89000604 addi r4,r17,24 - 9bb8: 88000415 stw zero,16(r17) - 9bbc: 88000515 stw zero,20(r17) - 9bc0: 003feb06 br 9b70 <_calloc_r+0x5c> - 9bc4: 000809c0 call 809c - 9bc8: 8805883a mov r2,r17 - 9bcc: dfc00117 ldw ra,4(sp) - 9bd0: dc400017 ldw r17,0(sp) - 9bd4: dec00204 addi sp,sp,8 - 9bd8: f800283a ret - -00009bdc <_close_r>: - 9bdc: defffd04 addi sp,sp,-12 - 9be0: dc000015 stw r16,0(sp) - 9be4: 04000074 movhi r16,1 - 9be8: 840f3e04 addi r16,r16,15608 - 9bec: dc400115 stw r17,4(sp) - 9bf0: 80000015 stw zero,0(r16) - 9bf4: 2023883a mov r17,r4 - 9bf8: 2809883a mov r4,r5 - 9bfc: dfc00215 stw ra,8(sp) - 9c00: 000c3f40 call c3f4 - 9c04: 1007883a mov r3,r2 - 9c08: 00bfffc4 movi r2,-1 - 9c0c: 18800626 beq r3,r2,9c28 <_close_r+0x4c> - 9c10: 1805883a mov r2,r3 - 9c14: dfc00217 ldw ra,8(sp) - 9c18: dc400117 ldw r17,4(sp) - 9c1c: dc000017 ldw r16,0(sp) - 9c20: dec00304 addi sp,sp,12 - 9c24: f800283a ret - 9c28: 80800017 ldw r2,0(r16) - 9c2c: 103ff826 beq r2,zero,9c10 <_close_r+0x34> - 9c30: 88800015 stw r2,0(r17) - 9c34: 1805883a mov r2,r3 - 9c38: dfc00217 ldw ra,8(sp) - 9c3c: dc400117 ldw r17,4(sp) - 9c40: dc000017 ldw r16,0(sp) - 9c44: dec00304 addi sp,sp,12 - 9c48: f800283a ret - -00009c4c <_fclose_r>: - 9c4c: defffc04 addi sp,sp,-16 - 9c50: dc400115 stw r17,4(sp) - 9c54: dc000015 stw r16,0(sp) - 9c58: dfc00315 stw ra,12(sp) - 9c5c: dc800215 stw r18,8(sp) - 9c60: 2821883a mov r16,r5 - 9c64: 2023883a mov r17,r4 - 9c68: 28002926 beq r5,zero,9d10 <_fclose_r+0xc4> - 9c6c: 00067a80 call 67a8 <__sfp_lock_acquire> - 9c70: 88000226 beq r17,zero,9c7c <_fclose_r+0x30> - 9c74: 88800e17 ldw r2,56(r17) - 9c78: 10002d26 beq r2,zero,9d30 <_fclose_r+0xe4> - 9c7c: 8080030f ldh r2,12(r16) - 9c80: 10002226 beq r2,zero,9d0c <_fclose_r+0xc0> - 9c84: 8809883a mov r4,r17 - 9c88: 800b883a mov r5,r16 - 9c8c: 00065200 call 6520 <_fflush_r> - 9c90: 1025883a mov r18,r2 - 9c94: 80800b17 ldw r2,44(r16) - 9c98: 10000426 beq r2,zero,9cac <_fclose_r+0x60> - 9c9c: 81400717 ldw r5,28(r16) - 9ca0: 8809883a mov r4,r17 - 9ca4: 103ee83a callr r2 - 9ca8: 10002a16 blt r2,zero,9d54 <_fclose_r+0x108> - 9cac: 8080030b ldhu r2,12(r16) - 9cb0: 1080200c andi r2,r2,128 - 9cb4: 1000231e bne r2,zero,9d44 <_fclose_r+0xf8> - 9cb8: 81400c17 ldw r5,48(r16) - 9cbc: 28000526 beq r5,zero,9cd4 <_fclose_r+0x88> - 9cc0: 80801004 addi r2,r16,64 - 9cc4: 28800226 beq r5,r2,9cd0 <_fclose_r+0x84> - 9cc8: 8809883a mov r4,r17 - 9ccc: 0006b700 call 6b70 <_free_r> - 9cd0: 80000c15 stw zero,48(r16) - 9cd4: 81401117 ldw r5,68(r16) - 9cd8: 28000326 beq r5,zero,9ce8 <_fclose_r+0x9c> - 9cdc: 8809883a mov r4,r17 - 9ce0: 0006b700 call 6b70 <_free_r> - 9ce4: 80001115 stw zero,68(r16) - 9ce8: 8000030d sth zero,12(r16) - 9cec: 00067ac0 call 67ac <__sfp_lock_release> - 9cf0: 9005883a mov r2,r18 - 9cf4: dfc00317 ldw ra,12(sp) - 9cf8: dc800217 ldw r18,8(sp) - 9cfc: dc400117 ldw r17,4(sp) - 9d00: dc000017 ldw r16,0(sp) - 9d04: dec00404 addi sp,sp,16 - 9d08: f800283a ret - 9d0c: 00067ac0 call 67ac <__sfp_lock_release> - 9d10: 0025883a mov r18,zero - 9d14: 9005883a mov r2,r18 - 9d18: dfc00317 ldw ra,12(sp) - 9d1c: dc800217 ldw r18,8(sp) - 9d20: dc400117 ldw r17,4(sp) - 9d24: dc000017 ldw r16,0(sp) - 9d28: dec00404 addi sp,sp,16 - 9d2c: f800283a ret - 9d30: 8809883a mov r4,r17 - 9d34: 00067b80 call 67b8 <__sinit> - 9d38: 8080030f ldh r2,12(r16) - 9d3c: 103fd11e bne r2,zero,9c84 <_fclose_r+0x38> - 9d40: 003ff206 br 9d0c <_fclose_r+0xc0> - 9d44: 81400417 ldw r5,16(r16) - 9d48: 8809883a mov r4,r17 - 9d4c: 0006b700 call 6b70 <_free_r> - 9d50: 003fd906 br 9cb8 <_fclose_r+0x6c> - 9d54: 04bfffc4 movi r18,-1 - 9d58: 003fd406 br 9cac <_fclose_r+0x60> - -00009d5c : - 9d5c: 00800074 movhi r2,1 - 9d60: 10884004 addi r2,r2,8448 - 9d64: 200b883a mov r5,r4 - 9d68: 11000017 ldw r4,0(r2) - 9d6c: 0009c4c1 jmpi 9c4c <_fclose_r> - -00009d70 <_fstat_r>: - 9d70: defffd04 addi sp,sp,-12 - 9d74: dc000015 stw r16,0(sp) - 9d78: 04000074 movhi r16,1 - 9d7c: 840f3e04 addi r16,r16,15608 - 9d80: dc400115 stw r17,4(sp) - 9d84: 80000015 stw zero,0(r16) - 9d88: 2023883a mov r17,r4 - 9d8c: 2809883a mov r4,r5 - 9d90: 300b883a mov r5,r6 - 9d94: dfc00215 stw ra,8(sp) - 9d98: 000c5800 call c580 - 9d9c: 1007883a mov r3,r2 - 9da0: 00bfffc4 movi r2,-1 - 9da4: 18800626 beq r3,r2,9dc0 <_fstat_r+0x50> - 9da8: 1805883a mov r2,r3 - 9dac: dfc00217 ldw ra,8(sp) - 9db0: dc400117 ldw r17,4(sp) - 9db4: dc000017 ldw r16,0(sp) - 9db8: dec00304 addi sp,sp,12 - 9dbc: f800283a ret - 9dc0: 80800017 ldw r2,0(r16) - 9dc4: 103ff826 beq r2,zero,9da8 <_fstat_r+0x38> - 9dc8: 88800015 stw r2,0(r17) - 9dcc: 1805883a mov r2,r3 - 9dd0: dfc00217 ldw ra,8(sp) - 9dd4: dc400117 ldw r17,4(sp) - 9dd8: dc000017 ldw r16,0(sp) - 9ddc: dec00304 addi sp,sp,12 - 9de0: f800283a ret - -00009de4 <_isatty_r>: - 9de4: defffd04 addi sp,sp,-12 - 9de8: dc000015 stw r16,0(sp) - 9dec: 04000074 movhi r16,1 - 9df0: 840f3e04 addi r16,r16,15608 - 9df4: dc400115 stw r17,4(sp) - 9df8: 80000015 stw zero,0(r16) - 9dfc: 2023883a mov r17,r4 - 9e00: 2809883a mov r4,r5 - 9e04: dfc00215 stw ra,8(sp) - 9e08: 000c6b80 call c6b8 - 9e0c: 1007883a mov r3,r2 - 9e10: 00bfffc4 movi r2,-1 - 9e14: 18800626 beq r3,r2,9e30 <_isatty_r+0x4c> - 9e18: 1805883a mov r2,r3 - 9e1c: dfc00217 ldw ra,8(sp) - 9e20: dc400117 ldw r17,4(sp) - 9e24: dc000017 ldw r16,0(sp) - 9e28: dec00304 addi sp,sp,12 - 9e2c: f800283a ret - 9e30: 80800017 ldw r2,0(r16) - 9e34: 103ff826 beq r2,zero,9e18 <_isatty_r+0x34> - 9e38: 88800015 stw r2,0(r17) - 9e3c: 1805883a mov r2,r3 - 9e40: dfc00217 ldw ra,8(sp) - 9e44: dc400117 ldw r17,4(sp) - 9e48: dc000017 ldw r16,0(sp) - 9e4c: dec00304 addi sp,sp,12 - 9e50: f800283a ret - -00009e54 <_lseek_r>: - 9e54: defffd04 addi sp,sp,-12 - 9e58: dc000015 stw r16,0(sp) - 9e5c: 04000074 movhi r16,1 - 9e60: 840f3e04 addi r16,r16,15608 - 9e64: dc400115 stw r17,4(sp) - 9e68: 80000015 stw zero,0(r16) - 9e6c: 2023883a mov r17,r4 - 9e70: 2809883a mov r4,r5 - 9e74: 300b883a mov r5,r6 - 9e78: 380d883a mov r6,r7 - 9e7c: dfc00215 stw ra,8(sp) - 9e80: 000c8c80 call c8c8 - 9e84: 1007883a mov r3,r2 - 9e88: 00bfffc4 movi r2,-1 - 9e8c: 18800626 beq r3,r2,9ea8 <_lseek_r+0x54> - 9e90: 1805883a mov r2,r3 - 9e94: dfc00217 ldw ra,8(sp) - 9e98: dc400117 ldw r17,4(sp) - 9e9c: dc000017 ldw r16,0(sp) - 9ea0: dec00304 addi sp,sp,12 - 9ea4: f800283a ret - 9ea8: 80800017 ldw r2,0(r16) - 9eac: 103ff826 beq r2,zero,9e90 <_lseek_r+0x3c> - 9eb0: 88800015 stw r2,0(r17) - 9eb4: 1805883a mov r2,r3 - 9eb8: dfc00217 ldw ra,8(sp) - 9ebc: dc400117 ldw r17,4(sp) - 9ec0: dc000017 ldw r16,0(sp) - 9ec4: dec00304 addi sp,sp,12 - 9ec8: f800283a ret - -00009ecc <_read_r>: - 9ecc: defffd04 addi sp,sp,-12 - 9ed0: dc000015 stw r16,0(sp) - 9ed4: 04000074 movhi r16,1 - 9ed8: 840f3e04 addi r16,r16,15608 - 9edc: dc400115 stw r17,4(sp) - 9ee0: 80000015 stw zero,0(r16) - 9ee4: 2023883a mov r17,r4 - 9ee8: 2809883a mov r4,r5 - 9eec: 300b883a mov r5,r6 - 9ef0: 380d883a mov r6,r7 - 9ef4: dfc00215 stw ra,8(sp) - 9ef8: 000cac80 call cac8 - 9efc: 1007883a mov r3,r2 - 9f00: 00bfffc4 movi r2,-1 - 9f04: 18800626 beq r3,r2,9f20 <_read_r+0x54> - 9f08: 1805883a mov r2,r3 - 9f0c: dfc00217 ldw ra,8(sp) - 9f10: dc400117 ldw r17,4(sp) - 9f14: dc000017 ldw r16,0(sp) - 9f18: dec00304 addi sp,sp,12 - 9f1c: f800283a ret - 9f20: 80800017 ldw r2,0(r16) - 9f24: 103ff826 beq r2,zero,9f08 <_read_r+0x3c> - 9f28: 88800015 stw r2,0(r17) - 9f2c: 1805883a mov r2,r3 - 9f30: dfc00217 ldw ra,8(sp) - 9f34: dc400117 ldw r17,4(sp) - 9f38: dc000017 ldw r16,0(sp) - 9f3c: dec00304 addi sp,sp,12 - 9f40: f800283a ret - -00009f44 <__udivdi3>: - 9f44: defff104 addi sp,sp,-60 - 9f48: 0015883a mov r10,zero - 9f4c: 2005883a mov r2,r4 - 9f50: 3011883a mov r8,r6 - 9f54: df000d15 stw fp,52(sp) - 9f58: dd400a15 stw r21,40(sp) - 9f5c: dcc00815 stw r19,32(sp) - 9f60: dfc00e15 stw ra,56(sp) - 9f64: ddc00c15 stw r23,48(sp) - 9f68: dd800b15 stw r22,44(sp) - 9f6c: dd000915 stw r20,36(sp) - 9f70: dc800715 stw r18,28(sp) - 9f74: dc400615 stw r17,24(sp) - 9f78: dc000515 stw r16,20(sp) - 9f7c: da800315 stw r10,12(sp) - 9f80: 4027883a mov r19,r8 - 9f84: 1039883a mov fp,r2 - 9f88: 282b883a mov r21,r5 - 9f8c: da800415 stw r10,16(sp) - 9f90: 3800401e bne r7,zero,a094 <__udivdi3+0x150> - 9f94: 2a006536 bltu r5,r8,a12c <__udivdi3+0x1e8> - 9f98: 4000b526 beq r8,zero,a270 <__udivdi3+0x32c> - 9f9c: 00bfffd4 movui r2,65535 - 9fa0: 14c0ad36 bltu r2,r19,a258 <__udivdi3+0x314> - 9fa4: 00803fc4 movi r2,255 - 9fa8: 14c15e36 bltu r2,r19,a524 <__udivdi3+0x5e0> - 9fac: 000b883a mov r5,zero - 9fb0: 0005883a mov r2,zero - 9fb4: 9884d83a srl r2,r19,r2 - 9fb8: 01000074 movhi r4,1 - 9fbc: 21011f04 addi r4,r4,1148 - 9fc0: 01800804 movi r6,32 - 9fc4: 1105883a add r2,r2,r4 - 9fc8: 10c00003 ldbu r3,0(r2) - 9fcc: 28c7883a add r3,r5,r3 - 9fd0: 30e9c83a sub r20,r6,r3 - 9fd4: a0010a1e bne r20,zero,a400 <__udivdi3+0x4bc> - 9fd8: 982ed43a srli r23,r19,16 - 9fdc: acebc83a sub r21,r21,r19 - 9fe0: 9dbfffcc andi r22,r19,65535 - 9fe4: 05000044 movi r20,1 - 9fe8: a809883a mov r4,r21 - 9fec: b80b883a mov r5,r23 - 9ff0: 0002b1c0 call 2b1c <__udivsi3> - 9ff4: 100b883a mov r5,r2 - 9ff8: b009883a mov r4,r22 - 9ffc: 1021883a mov r16,r2 - a000: 0002b2c0 call 2b2c <__mulsi3> - a004: a809883a mov r4,r21 - a008: b80b883a mov r5,r23 - a00c: 1023883a mov r17,r2 - a010: 0002b240 call 2b24 <__umodsi3> - a014: 1004943a slli r2,r2,16 - a018: e006d43a srli r3,fp,16 - a01c: 10c4b03a or r2,r2,r3 - a020: 1440042e bgeu r2,r17,a034 <__udivdi3+0xf0> - a024: 14c5883a add r2,r2,r19 - a028: 843fffc4 addi r16,r16,-1 - a02c: 14c00136 bltu r2,r19,a034 <__udivdi3+0xf0> - a030: 14415c36 bltu r2,r17,a5a4 <__udivdi3+0x660> - a034: 1463c83a sub r17,r2,r17 - a038: 8809883a mov r4,r17 - a03c: b80b883a mov r5,r23 - a040: 0002b1c0 call 2b1c <__udivsi3> - a044: 100b883a mov r5,r2 - a048: b009883a mov r4,r22 - a04c: 102b883a mov r21,r2 - a050: 0002b2c0 call 2b2c <__mulsi3> - a054: 8809883a mov r4,r17 - a058: b80b883a mov r5,r23 - a05c: 1025883a mov r18,r2 - a060: 0002b240 call 2b24 <__umodsi3> - a064: 1004943a slli r2,r2,16 - a068: e0ffffcc andi r3,fp,65535 - a06c: 10c4b03a or r2,r2,r3 - a070: 1480042e bgeu r2,r18,a084 <__udivdi3+0x140> - a074: 9885883a add r2,r19,r2 - a078: ad7fffc4 addi r21,r21,-1 - a07c: 14c00136 bltu r2,r19,a084 <__udivdi3+0x140> - a080: 14813c36 bltu r2,r18,a574 <__udivdi3+0x630> - a084: 8004943a slli r2,r16,16 - a088: a009883a mov r4,r20 - a08c: a884b03a or r2,r21,r2 - a090: 00001506 br a0e8 <__udivdi3+0x1a4> - a094: 380d883a mov r6,r7 - a098: 29c06c36 bltu r5,r7,a24c <__udivdi3+0x308> - a09c: 00bfffd4 movui r2,65535 - a0a0: 11c06436 bltu r2,r7,a234 <__udivdi3+0x2f0> - a0a4: 00803fc4 movi r2,255 - a0a8: 11c11836 bltu r2,r7,a50c <__udivdi3+0x5c8> - a0ac: 000b883a mov r5,zero - a0b0: 0005883a mov r2,zero - a0b4: 3084d83a srl r2,r6,r2 - a0b8: 01000074 movhi r4,1 - a0bc: 21011f04 addi r4,r4,1148 - a0c0: 01c00804 movi r7,32 - a0c4: 1105883a add r2,r2,r4 - a0c8: 10c00003 ldbu r3,0(r2) - a0cc: 28c7883a add r3,r5,r3 - a0d0: 38edc83a sub r22,r7,r3 - a0d4: b000731e bne r22,zero,a2a4 <__udivdi3+0x360> - a0d8: 35400136 bltu r6,r21,a0e0 <__udivdi3+0x19c> - a0dc: e4c05b36 bltu fp,r19,a24c <__udivdi3+0x308> - a0e0: 00800044 movi r2,1 - a0e4: 0009883a mov r4,zero - a0e8: d8800315 stw r2,12(sp) - a0ec: d9400317 ldw r5,12(sp) - a0f0: 2007883a mov r3,r4 - a0f4: d9000415 stw r4,16(sp) - a0f8: 2805883a mov r2,r5 - a0fc: dfc00e17 ldw ra,56(sp) - a100: df000d17 ldw fp,52(sp) - a104: ddc00c17 ldw r23,48(sp) - a108: dd800b17 ldw r22,44(sp) - a10c: dd400a17 ldw r21,40(sp) - a110: dd000917 ldw r20,36(sp) - a114: dcc00817 ldw r19,32(sp) - a118: dc800717 ldw r18,28(sp) - a11c: dc400617 ldw r17,24(sp) - a120: dc000517 ldw r16,20(sp) - a124: dec00f04 addi sp,sp,60 - a128: f800283a ret - a12c: 00bfffd4 movui r2,65535 - a130: 12005636 bltu r2,r8,a28c <__udivdi3+0x348> - a134: 00803fc4 movi r2,255 - a138: 12010036 bltu r2,r8,a53c <__udivdi3+0x5f8> - a13c: 000b883a mov r5,zero - a140: 0005883a mov r2,zero - a144: 9884d83a srl r2,r19,r2 - a148: 01000074 movhi r4,1 - a14c: 21011f04 addi r4,r4,1148 - a150: 01800804 movi r6,32 - a154: 1105883a add r2,r2,r4 - a158: 10c00003 ldbu r3,0(r2) - a15c: 28c7883a add r3,r5,r3 - a160: 30cbc83a sub r5,r6,r3 - a164: 28000626 beq r5,zero,a180 <__udivdi3+0x23c> - a168: 3145c83a sub r2,r6,r5 - a16c: e084d83a srl r2,fp,r2 - a170: a946983a sll r3,r21,r5 - a174: e178983a sll fp,fp,r5 - a178: 9966983a sll r19,r19,r5 - a17c: 18aab03a or r21,r3,r2 - a180: 982ed43a srli r23,r19,16 - a184: a809883a mov r4,r21 - a188: 9cbfffcc andi r18,r19,65535 - a18c: b80b883a mov r5,r23 - a190: 0002b1c0 call 2b1c <__udivsi3> - a194: 100b883a mov r5,r2 - a198: 9009883a mov r4,r18 - a19c: 1021883a mov r16,r2 - a1a0: 0002b2c0 call 2b2c <__mulsi3> - a1a4: a809883a mov r4,r21 - a1a8: b80b883a mov r5,r23 - a1ac: 1023883a mov r17,r2 - a1b0: 0002b240 call 2b24 <__umodsi3> - a1b4: 1004943a slli r2,r2,16 - a1b8: e006d43a srli r3,fp,16 - a1bc: 10c4b03a or r2,r2,r3 - a1c0: 1440042e bgeu r2,r17,a1d4 <__udivdi3+0x290> - a1c4: 14c5883a add r2,r2,r19 - a1c8: 843fffc4 addi r16,r16,-1 - a1cc: 14c00136 bltu r2,r19,a1d4 <__udivdi3+0x290> - a1d0: 1440ea36 bltu r2,r17,a57c <__udivdi3+0x638> - a1d4: 1463c83a sub r17,r2,r17 - a1d8: 8809883a mov r4,r17 - a1dc: b80b883a mov r5,r23 - a1e0: 0002b1c0 call 2b1c <__udivsi3> - a1e4: 100b883a mov r5,r2 - a1e8: 9009883a mov r4,r18 - a1ec: 102b883a mov r21,r2 - a1f0: 0002b2c0 call 2b2c <__mulsi3> - a1f4: 8809883a mov r4,r17 - a1f8: b80b883a mov r5,r23 - a1fc: 1025883a mov r18,r2 - a200: 0002b240 call 2b24 <__umodsi3> - a204: 1004943a slli r2,r2,16 - a208: e0ffffcc andi r3,fp,65535 - a20c: 10c4b03a or r2,r2,r3 - a210: 1480042e bgeu r2,r18,a224 <__udivdi3+0x2e0> - a214: 9885883a add r2,r19,r2 - a218: ad7fffc4 addi r21,r21,-1 - a21c: 14c00136 bltu r2,r19,a224 <__udivdi3+0x2e0> - a220: 1480d936 bltu r2,r18,a588 <__udivdi3+0x644> - a224: 8004943a slli r2,r16,16 - a228: 0009883a mov r4,zero - a22c: a884b03a or r2,r21,r2 - a230: 003fad06 br a0e8 <__udivdi3+0x1a4> - a234: 00804034 movhi r2,256 - a238: 10bfffc4 addi r2,r2,-1 - a23c: 11c0b636 bltu r2,r7,a518 <__udivdi3+0x5d4> - a240: 01400404 movi r5,16 - a244: 2805883a mov r2,r5 - a248: 003f9a06 br a0b4 <__udivdi3+0x170> - a24c: 0005883a mov r2,zero - a250: 0009883a mov r4,zero - a254: 003fa406 br a0e8 <__udivdi3+0x1a4> - a258: 00804034 movhi r2,256 - a25c: 10bfffc4 addi r2,r2,-1 - a260: 14c0b336 bltu r2,r19,a530 <__udivdi3+0x5ec> - a264: 01400404 movi r5,16 - a268: 2805883a mov r2,r5 - a26c: 003f5106 br 9fb4 <__udivdi3+0x70> - a270: 01000044 movi r4,1 - a274: 000b883a mov r5,zero - a278: 0002b1c0 call 2b1c <__udivsi3> - a27c: 1027883a mov r19,r2 - a280: 00bfffd4 movui r2,65535 - a284: 14fff436 bltu r2,r19,a258 <__udivdi3+0x314> - a288: 003f4606 br 9fa4 <__udivdi3+0x60> - a28c: 00804034 movhi r2,256 - a290: 10bfffc4 addi r2,r2,-1 - a294: 1200ac36 bltu r2,r8,a548 <__udivdi3+0x604> - a298: 01400404 movi r5,16 - a29c: 2805883a mov r2,r5 - a2a0: 003fa806 br a144 <__udivdi3+0x200> - a2a4: 3d85c83a sub r2,r7,r22 - a2a8: 3588983a sll r4,r6,r22 - a2ac: 9886d83a srl r3,r19,r2 - a2b0: a8a2d83a srl r17,r21,r2 - a2b4: e084d83a srl r2,fp,r2 - a2b8: 20eeb03a or r23,r4,r3 - a2bc: b824d43a srli r18,r23,16 - a2c0: ad86983a sll r3,r21,r22 - a2c4: 8809883a mov r4,r17 - a2c8: 900b883a mov r5,r18 - a2cc: 1886b03a or r3,r3,r2 - a2d0: d8c00115 stw r3,4(sp) - a2d4: bc3fffcc andi r16,r23,65535 - a2d8: 0002b1c0 call 2b1c <__udivsi3> - a2dc: 100b883a mov r5,r2 - a2e0: 8009883a mov r4,r16 - a2e4: 1029883a mov r20,r2 - a2e8: 0002b2c0 call 2b2c <__mulsi3> - a2ec: 900b883a mov r5,r18 - a2f0: 8809883a mov r4,r17 - a2f4: 102b883a mov r21,r2 - a2f8: 0002b240 call 2b24 <__umodsi3> - a2fc: d9400117 ldw r5,4(sp) - a300: 1004943a slli r2,r2,16 - a304: 9da6983a sll r19,r19,r22 - a308: 2806d43a srli r3,r5,16 - a30c: 10c4b03a or r2,r2,r3 - a310: 1540032e bgeu r2,r21,a320 <__udivdi3+0x3dc> - a314: 15c5883a add r2,r2,r23 - a318: a53fffc4 addi r20,r20,-1 - a31c: 15c0912e bgeu r2,r23,a564 <__udivdi3+0x620> - a320: 1563c83a sub r17,r2,r21 - a324: 8809883a mov r4,r17 - a328: 900b883a mov r5,r18 - a32c: 0002b1c0 call 2b1c <__udivsi3> - a330: 100b883a mov r5,r2 - a334: 8009883a mov r4,r16 - a338: 102b883a mov r21,r2 - a33c: 0002b2c0 call 2b2c <__mulsi3> - a340: 8809883a mov r4,r17 - a344: 900b883a mov r5,r18 - a348: 1021883a mov r16,r2 - a34c: 0002b240 call 2b24 <__umodsi3> - a350: da800117 ldw r10,4(sp) - a354: 1004943a slli r2,r2,16 - a358: 50ffffcc andi r3,r10,65535 - a35c: 10c6b03a or r3,r2,r3 - a360: 1c00032e bgeu r3,r16,a370 <__udivdi3+0x42c> - a364: 1dc7883a add r3,r3,r23 - a368: ad7fffc4 addi r21,r21,-1 - a36c: 1dc0792e bgeu r3,r23,a554 <__udivdi3+0x610> - a370: a004943a slli r2,r20,16 - a374: 982ed43a srli r23,r19,16 - a378: 9cffffcc andi r19,r19,65535 - a37c: a8a4b03a or r18,r21,r2 - a380: 947fffcc andi r17,r18,65535 - a384: 902ad43a srli r21,r18,16 - a388: 8809883a mov r4,r17 - a38c: 980b883a mov r5,r19 - a390: 1c21c83a sub r16,r3,r16 - a394: 0002b2c0 call 2b2c <__mulsi3> - a398: 8809883a mov r4,r17 - a39c: b80b883a mov r5,r23 - a3a0: 1029883a mov r20,r2 - a3a4: 0002b2c0 call 2b2c <__mulsi3> - a3a8: 980b883a mov r5,r19 - a3ac: a809883a mov r4,r21 - a3b0: 1023883a mov r17,r2 - a3b4: 0002b2c0 call 2b2c <__mulsi3> - a3b8: a809883a mov r4,r21 - a3bc: b80b883a mov r5,r23 - a3c0: 1027883a mov r19,r2 - a3c4: 0002b2c0 call 2b2c <__mulsi3> - a3c8: 1009883a mov r4,r2 - a3cc: a004d43a srli r2,r20,16 - a3d0: 8ce3883a add r17,r17,r19 - a3d4: 1447883a add r3,r2,r17 - a3d8: 1cc0022e bgeu r3,r19,a3e4 <__udivdi3+0x4a0> - a3dc: 00800074 movhi r2,1 - a3e0: 2089883a add r4,r4,r2 - a3e4: 1804d43a srli r2,r3,16 - a3e8: 2085883a add r2,r4,r2 - a3ec: 80804436 bltu r16,r2,a500 <__udivdi3+0x5bc> - a3f0: 80803e26 beq r16,r2,a4ec <__udivdi3+0x5a8> - a3f4: 9005883a mov r2,r18 - a3f8: 0009883a mov r4,zero - a3fc: 003f3a06 br a0e8 <__udivdi3+0x1a4> - a400: 9d26983a sll r19,r19,r20 - a404: 3505c83a sub r2,r6,r20 - a408: a8a2d83a srl r17,r21,r2 - a40c: 982ed43a srli r23,r19,16 - a410: e084d83a srl r2,fp,r2 - a414: ad06983a sll r3,r21,r20 - a418: 8809883a mov r4,r17 - a41c: b80b883a mov r5,r23 - a420: 1886b03a or r3,r3,r2 - a424: d8c00015 stw r3,0(sp) - a428: 9dbfffcc andi r22,r19,65535 - a42c: 0002b1c0 call 2b1c <__udivsi3> - a430: 100b883a mov r5,r2 - a434: b009883a mov r4,r22 - a438: d8800215 stw r2,8(sp) - a43c: 0002b2c0 call 2b2c <__mulsi3> - a440: 8809883a mov r4,r17 - a444: b80b883a mov r5,r23 - a448: 102b883a mov r21,r2 - a44c: 0002b240 call 2b24 <__umodsi3> - a450: d9000017 ldw r4,0(sp) - a454: 1004943a slli r2,r2,16 - a458: 2006d43a srli r3,r4,16 - a45c: 10c4b03a or r2,r2,r3 - a460: 1540052e bgeu r2,r21,a478 <__udivdi3+0x534> - a464: d9400217 ldw r5,8(sp) - a468: 14c5883a add r2,r2,r19 - a46c: 297fffc4 addi r5,r5,-1 - a470: d9400215 stw r5,8(sp) - a474: 14c0462e bgeu r2,r19,a590 <__udivdi3+0x64c> - a478: 1563c83a sub r17,r2,r21 - a47c: 8809883a mov r4,r17 - a480: b80b883a mov r5,r23 - a484: 0002b1c0 call 2b1c <__udivsi3> - a488: 100b883a mov r5,r2 - a48c: b009883a mov r4,r22 - a490: 1025883a mov r18,r2 - a494: 0002b2c0 call 2b2c <__mulsi3> - a498: 8809883a mov r4,r17 - a49c: b80b883a mov r5,r23 - a4a0: 1021883a mov r16,r2 - a4a4: 0002b240 call 2b24 <__umodsi3> - a4a8: da800017 ldw r10,0(sp) - a4ac: 1004943a slli r2,r2,16 - a4b0: 50ffffcc andi r3,r10,65535 - a4b4: 10c6b03a or r3,r2,r3 - a4b8: 1c00062e bgeu r3,r16,a4d4 <__udivdi3+0x590> - a4bc: 1cc7883a add r3,r3,r19 - a4c0: 94bfffc4 addi r18,r18,-1 - a4c4: 1cc00336 bltu r3,r19,a4d4 <__udivdi3+0x590> - a4c8: 1c00022e bgeu r3,r16,a4d4 <__udivdi3+0x590> - a4cc: 94bfffc4 addi r18,r18,-1 - a4d0: 1cc7883a add r3,r3,r19 - a4d4: d9000217 ldw r4,8(sp) - a4d8: e538983a sll fp,fp,r20 - a4dc: 1c2bc83a sub r21,r3,r16 - a4e0: 2004943a slli r2,r4,16 - a4e4: 90a8b03a or r20,r18,r2 - a4e8: 003ebf06 br 9fe8 <__udivdi3+0xa4> - a4ec: 1804943a slli r2,r3,16 - a4f0: e588983a sll r4,fp,r22 - a4f4: a0ffffcc andi r3,r20,65535 - a4f8: 10c5883a add r2,r2,r3 - a4fc: 20bfbd2e bgeu r4,r2,a3f4 <__udivdi3+0x4b0> - a500: 90bfffc4 addi r2,r18,-1 - a504: 0009883a mov r4,zero - a508: 003ef706 br a0e8 <__udivdi3+0x1a4> - a50c: 01400204 movi r5,8 - a510: 2805883a mov r2,r5 - a514: 003ee706 br a0b4 <__udivdi3+0x170> - a518: 01400604 movi r5,24 - a51c: 2805883a mov r2,r5 - a520: 003ee406 br a0b4 <__udivdi3+0x170> - a524: 01400204 movi r5,8 - a528: 2805883a mov r2,r5 - a52c: 003ea106 br 9fb4 <__udivdi3+0x70> - a530: 01400604 movi r5,24 - a534: 2805883a mov r2,r5 - a538: 003e9e06 br 9fb4 <__udivdi3+0x70> - a53c: 01400204 movi r5,8 - a540: 2805883a mov r2,r5 - a544: 003eff06 br a144 <__udivdi3+0x200> - a548: 01400604 movi r5,24 - a54c: 2805883a mov r2,r5 - a550: 003efc06 br a144 <__udivdi3+0x200> - a554: 1c3f862e bgeu r3,r16,a370 <__udivdi3+0x42c> - a558: 1dc7883a add r3,r3,r23 - a55c: ad7fffc4 addi r21,r21,-1 - a560: 003f8306 br a370 <__udivdi3+0x42c> - a564: 157f6e2e bgeu r2,r21,a320 <__udivdi3+0x3dc> - a568: a53fffc4 addi r20,r20,-1 - a56c: 15c5883a add r2,r2,r23 - a570: 003f6b06 br a320 <__udivdi3+0x3dc> - a574: ad7fffc4 addi r21,r21,-1 - a578: 003ec206 br a084 <__udivdi3+0x140> - a57c: 843fffc4 addi r16,r16,-1 - a580: 14c5883a add r2,r2,r19 - a584: 003f1306 br a1d4 <__udivdi3+0x290> - a588: ad7fffc4 addi r21,r21,-1 - a58c: 003f2506 br a224 <__udivdi3+0x2e0> - a590: 157fb92e bgeu r2,r21,a478 <__udivdi3+0x534> - a594: 297fffc4 addi r5,r5,-1 - a598: 14c5883a add r2,r2,r19 - a59c: d9400215 stw r5,8(sp) - a5a0: 003fb506 br a478 <__udivdi3+0x534> - a5a4: 843fffc4 addi r16,r16,-1 - a5a8: 14c5883a add r2,r2,r19 - a5ac: 003ea106 br a034 <__udivdi3+0xf0> - -0000a5b0 <__umoddi3>: - a5b0: defff004 addi sp,sp,-64 - a5b4: 3011883a mov r8,r6 - a5b8: 000d883a mov r6,zero - a5bc: dd400b15 stw r21,44(sp) - a5c0: dcc00915 stw r19,36(sp) - a5c4: dc000615 stw r16,24(sp) - a5c8: dfc00f15 stw ra,60(sp) - a5cc: df000e15 stw fp,56(sp) - a5d0: ddc00d15 stw r23,52(sp) - a5d4: dd800c15 stw r22,48(sp) - a5d8: dd000a15 stw r20,40(sp) - a5dc: dc800815 stw r18,32(sp) - a5e0: dc400715 stw r17,28(sp) - a5e4: 2817883a mov r11,r5 - a5e8: d9800415 stw r6,16(sp) - a5ec: 4027883a mov r19,r8 - a5f0: d9800515 stw r6,20(sp) - a5f4: 2021883a mov r16,r4 - a5f8: 282b883a mov r21,r5 - a5fc: 38002c1e bne r7,zero,a6b0 <__umoddi3+0x100> - a600: 2a005636 bltu r5,r8,a75c <__umoddi3+0x1ac> - a604: 40009a26 beq r8,zero,a870 <__umoddi3+0x2c0> - a608: 00bfffd4 movui r2,65535 - a60c: 14c09236 bltu r2,r19,a858 <__umoddi3+0x2a8> - a610: 00803fc4 movi r2,255 - a614: 14c15c36 bltu r2,r19,ab88 <__umoddi3+0x5d8> - a618: 000b883a mov r5,zero - a61c: 0005883a mov r2,zero - a620: 9884d83a srl r2,r19,r2 - a624: 01000074 movhi r4,1 - a628: 21011f04 addi r4,r4,1148 - a62c: 01800804 movi r6,32 - a630: 1105883a add r2,r2,r4 - a634: 10c00003 ldbu r3,0(r2) - a638: 28c7883a add r3,r5,r3 - a63c: 30e5c83a sub r18,r6,r3 - a640: 9000a41e bne r18,zero,a8d4 <__umoddi3+0x324> - a644: 982ed43a srli r23,r19,16 - a648: acebc83a sub r21,r21,r19 - a64c: 9d3fffcc andi r20,r19,65535 - a650: 002d883a mov r22,zero - a654: a809883a mov r4,r21 - a658: b80b883a mov r5,r23 - a65c: 0002b1c0 call 2b1c <__udivsi3> - a660: 100b883a mov r5,r2 - a664: a009883a mov r4,r20 - a668: 0002b2c0 call 2b2c <__mulsi3> - a66c: a809883a mov r4,r21 - a670: b80b883a mov r5,r23 - a674: 1023883a mov r17,r2 - a678: 0002b240 call 2b24 <__umodsi3> - a67c: 1004943a slli r2,r2,16 - a680: 8006d43a srli r3,r16,16 - a684: 10c4b03a or r2,r2,r3 - a688: 1440032e bgeu r2,r17,a698 <__umoddi3+0xe8> - a68c: 14c5883a add r2,r2,r19 - a690: 14c00136 bltu r2,r19,a698 <__umoddi3+0xe8> - a694: 14415836 bltu r2,r17,abf8 <__umoddi3+0x648> - a698: 1463c83a sub r17,r2,r17 - a69c: 8809883a mov r4,r17 - a6a0: b80b883a mov r5,r23 - a6a4: 0002b1c0 call 2b1c <__udivsi3> - a6a8: a009883a mov r4,r20 - a6ac: 00005306 br a7fc <__umoddi3+0x24c> - a6b0: 380d883a mov r6,r7 - a6b4: 29c0132e bgeu r5,r7,a704 <__umoddi3+0x154> - a6b8: d9000415 stw r4,16(sp) - a6bc: d9400515 stw r5,20(sp) - a6c0: d9400417 ldw r5,16(sp) - a6c4: 5813883a mov r9,r11 - a6c8: 2811883a mov r8,r5 - a6cc: 4005883a mov r2,r8 - a6d0: 4807883a mov r3,r9 - a6d4: dfc00f17 ldw ra,60(sp) - a6d8: df000e17 ldw fp,56(sp) - a6dc: ddc00d17 ldw r23,52(sp) - a6e0: dd800c17 ldw r22,48(sp) - a6e4: dd400b17 ldw r21,44(sp) - a6e8: dd000a17 ldw r20,40(sp) - a6ec: dcc00917 ldw r19,36(sp) - a6f0: dc800817 ldw r18,32(sp) - a6f4: dc400717 ldw r17,28(sp) - a6f8: dc000617 ldw r16,24(sp) - a6fc: dec01004 addi sp,sp,64 - a700: f800283a ret - a704: 00bfffd4 movui r2,65535 - a708: 11c06636 bltu r2,r7,a8a4 <__umoddi3+0x2f4> - a70c: 00803fc4 movi r2,255 - a710: 11c12036 bltu r2,r7,ab94 <__umoddi3+0x5e4> - a714: 000b883a mov r5,zero - a718: 0005883a mov r2,zero - a71c: 3084d83a srl r2,r6,r2 - a720: 01000074 movhi r4,1 - a724: 21011f04 addi r4,r4,1148 - a728: 01c00804 movi r7,32 - a72c: 1105883a add r2,r2,r4 - a730: 10c00003 ldbu r3,0(r2) - a734: 28c7883a add r3,r5,r3 - a738: 38e5c83a sub r18,r7,r3 - a73c: 9000941e bne r18,zero,a990 <__umoddi3+0x3e0> - a740: 35405e36 bltu r6,r21,a8bc <__umoddi3+0x30c> - a744: 84c05d2e bgeu r16,r19,a8bc <__umoddi3+0x30c> - a748: 8011883a mov r8,r16 - a74c: a813883a mov r9,r21 - a750: dc000415 stw r16,16(sp) - a754: dd400515 stw r21,20(sp) - a758: 003fdc06 br a6cc <__umoddi3+0x11c> - a75c: 00bfffd4 movui r2,65535 - a760: 12004a36 bltu r2,r8,a88c <__umoddi3+0x2dc> - a764: 00803fc4 movi r2,255 - a768: 12010d36 bltu r2,r8,aba0 <__umoddi3+0x5f0> - a76c: 000b883a mov r5,zero - a770: 0005883a mov r2,zero - a774: 9884d83a srl r2,r19,r2 - a778: 01000074 movhi r4,1 - a77c: 21011f04 addi r4,r4,1148 - a780: 01800804 movi r6,32 - a784: 1105883a add r2,r2,r4 - a788: 10c00003 ldbu r3,0(r2) - a78c: 28c7883a add r3,r5,r3 - a790: 30c7c83a sub r3,r6,r3 - a794: 1800dc1e bne r3,zero,ab08 <__umoddi3+0x558> - a798: 002d883a mov r22,zero - a79c: 982ed43a srli r23,r19,16 - a7a0: a809883a mov r4,r21 - a7a4: 9cbfffcc andi r18,r19,65535 - a7a8: b80b883a mov r5,r23 - a7ac: 0002b1c0 call 2b1c <__udivsi3> - a7b0: 100b883a mov r5,r2 - a7b4: 9009883a mov r4,r18 - a7b8: 0002b2c0 call 2b2c <__mulsi3> - a7bc: a809883a mov r4,r21 - a7c0: b80b883a mov r5,r23 - a7c4: 1023883a mov r17,r2 - a7c8: 0002b240 call 2b24 <__umodsi3> - a7cc: 1004943a slli r2,r2,16 - a7d0: 8006d43a srli r3,r16,16 - a7d4: 10c4b03a or r2,r2,r3 - a7d8: 1440032e bgeu r2,r17,a7e8 <__umoddi3+0x238> - a7dc: 14c5883a add r2,r2,r19 - a7e0: 14c00136 bltu r2,r19,a7e8 <__umoddi3+0x238> - a7e4: 14410236 bltu r2,r17,abf0 <__umoddi3+0x640> - a7e8: 1463c83a sub r17,r2,r17 - a7ec: 8809883a mov r4,r17 - a7f0: b80b883a mov r5,r23 - a7f4: 0002b1c0 call 2b1c <__udivsi3> - a7f8: 9009883a mov r4,r18 - a7fc: 100b883a mov r5,r2 - a800: 0002b2c0 call 2b2c <__mulsi3> - a804: 8809883a mov r4,r17 - a808: b80b883a mov r5,r23 - a80c: 102b883a mov r21,r2 - a810: 0002b240 call 2b24 <__umodsi3> - a814: 1004943a slli r2,r2,16 - a818: 80ffffcc andi r3,r16,65535 - a81c: 10c4b03a or r2,r2,r3 - a820: 1540042e bgeu r2,r21,a834 <__umoddi3+0x284> - a824: 14c5883a add r2,r2,r19 - a828: 14c00236 bltu r2,r19,a834 <__umoddi3+0x284> - a82c: 1540012e bgeu r2,r21,a834 <__umoddi3+0x284> - a830: 14c5883a add r2,r2,r19 - a834: 1545c83a sub r2,r2,r21 - a838: 1584d83a srl r2,r2,r22 - a83c: 0013883a mov r9,zero - a840: d8800415 stw r2,16(sp) - a844: d8c00417 ldw r3,16(sp) - a848: 0005883a mov r2,zero - a84c: d8800515 stw r2,20(sp) - a850: 1811883a mov r8,r3 - a854: 003f9d06 br a6cc <__umoddi3+0x11c> - a858: 00804034 movhi r2,256 - a85c: 10bfffc4 addi r2,r2,-1 - a860: 14c0c636 bltu r2,r19,ab7c <__umoddi3+0x5cc> - a864: 01400404 movi r5,16 - a868: 2805883a mov r2,r5 - a86c: 003f6c06 br a620 <__umoddi3+0x70> - a870: 01000044 movi r4,1 - a874: 000b883a mov r5,zero - a878: 0002b1c0 call 2b1c <__udivsi3> - a87c: 1027883a mov r19,r2 - a880: 00bfffd4 movui r2,65535 - a884: 14fff436 bltu r2,r19,a858 <__umoddi3+0x2a8> - a888: 003f6106 br a610 <__umoddi3+0x60> - a88c: 00804034 movhi r2,256 - a890: 10bfffc4 addi r2,r2,-1 - a894: 1200c536 bltu r2,r8,abac <__umoddi3+0x5fc> - a898: 01400404 movi r5,16 - a89c: 2805883a mov r2,r5 - a8a0: 003fb406 br a774 <__umoddi3+0x1c4> - a8a4: 00804034 movhi r2,256 - a8a8: 10bfffc4 addi r2,r2,-1 - a8ac: 11c0c236 bltu r2,r7,abb8 <__umoddi3+0x608> - a8b0: 01400404 movi r5,16 - a8b4: 2805883a mov r2,r5 - a8b8: 003f9806 br a71c <__umoddi3+0x16c> - a8bc: 84c9c83a sub r4,r16,r19 - a8c0: 8105803a cmpltu r2,r16,r4 - a8c4: a987c83a sub r3,r21,r6 - a8c8: 18abc83a sub r21,r3,r2 - a8cc: 2021883a mov r16,r4 - a8d0: 003f9d06 br a748 <__umoddi3+0x198> - a8d4: 9ca6983a sll r19,r19,r18 - a8d8: 3485c83a sub r2,r6,r18 - a8dc: a8a2d83a srl r17,r21,r2 - a8e0: 982ed43a srli r23,r19,16 - a8e4: ac86983a sll r3,r21,r18 - a8e8: 8084d83a srl r2,r16,r2 - a8ec: 8809883a mov r4,r17 - a8f0: b80b883a mov r5,r23 - a8f4: 18b8b03a or fp,r3,r2 - a8f8: 9d3fffcc andi r20,r19,65535 - a8fc: 0002b1c0 call 2b1c <__udivsi3> - a900: 100b883a mov r5,r2 - a904: a009883a mov r4,r20 - a908: 0002b2c0 call 2b2c <__mulsi3> - a90c: 8809883a mov r4,r17 - a910: b80b883a mov r5,r23 - a914: 102b883a mov r21,r2 - a918: 0002b240 call 2b24 <__umodsi3> - a91c: 1004943a slli r2,r2,16 - a920: e006d43a srli r3,fp,16 - a924: 902d883a mov r22,r18 - a928: 10c4b03a or r2,r2,r3 - a92c: 1540022e bgeu r2,r21,a938 <__umoddi3+0x388> - a930: 14c5883a add r2,r2,r19 - a934: 14c0ab2e bgeu r2,r19,abe4 <__umoddi3+0x634> - a938: 1563c83a sub r17,r2,r21 - a93c: 8809883a mov r4,r17 - a940: b80b883a mov r5,r23 - a944: 0002b1c0 call 2b1c <__udivsi3> - a948: 100b883a mov r5,r2 - a94c: a009883a mov r4,r20 - a950: 0002b2c0 call 2b2c <__mulsi3> - a954: 8809883a mov r4,r17 - a958: b80b883a mov r5,r23 - a95c: 102b883a mov r21,r2 - a960: 0002b240 call 2b24 <__umodsi3> - a964: 1004943a slli r2,r2,16 - a968: e0ffffcc andi r3,fp,65535 - a96c: 10c4b03a or r2,r2,r3 - a970: 1540042e bgeu r2,r21,a984 <__umoddi3+0x3d4> - a974: 14c5883a add r2,r2,r19 - a978: 14c00236 bltu r2,r19,a984 <__umoddi3+0x3d4> - a97c: 1540012e bgeu r2,r21,a984 <__umoddi3+0x3d4> - a980: 14c5883a add r2,r2,r19 - a984: 84a0983a sll r16,r16,r18 - a988: 156bc83a sub r21,r2,r21 - a98c: 003f3106 br a654 <__umoddi3+0xa4> - a990: 3c8fc83a sub r7,r7,r18 - a994: 3486983a sll r3,r6,r18 - a998: 99c4d83a srl r2,r19,r7 - a99c: a9e2d83a srl r17,r21,r7 - a9a0: ac8c983a sll r6,r21,r18 - a9a4: 18acb03a or r22,r3,r2 - a9a8: b02ed43a srli r23,r22,16 - a9ac: 81c4d83a srl r2,r16,r7 - a9b0: 8809883a mov r4,r17 - a9b4: b80b883a mov r5,r23 - a9b8: 308cb03a or r6,r6,r2 - a9bc: d9c00315 stw r7,12(sp) - a9c0: d9800215 stw r6,8(sp) - a9c4: b53fffcc andi r20,r22,65535 - a9c8: 0002b1c0 call 2b1c <__udivsi3> - a9cc: 100b883a mov r5,r2 - a9d0: a009883a mov r4,r20 - a9d4: 1039883a mov fp,r2 - a9d8: 0002b2c0 call 2b2c <__mulsi3> - a9dc: 8809883a mov r4,r17 - a9e0: b80b883a mov r5,r23 - a9e4: 102b883a mov r21,r2 - a9e8: 0002b240 call 2b24 <__umodsi3> - a9ec: d9000217 ldw r4,8(sp) - a9f0: 1004943a slli r2,r2,16 - a9f4: 9ca6983a sll r19,r19,r18 - a9f8: 2006d43a srli r3,r4,16 - a9fc: 84a0983a sll r16,r16,r18 - aa00: dcc00015 stw r19,0(sp) - aa04: 10c4b03a or r2,r2,r3 - aa08: dc000115 stw r16,4(sp) - aa0c: 1540032e bgeu r2,r21,aa1c <__umoddi3+0x46c> - aa10: 1585883a add r2,r2,r22 - aa14: e73fffc4 addi fp,fp,-1 - aa18: 15806e2e bgeu r2,r22,abd4 <__umoddi3+0x624> - aa1c: 1563c83a sub r17,r2,r21 - aa20: 8809883a mov r4,r17 - aa24: b80b883a mov r5,r23 - aa28: 0002b1c0 call 2b1c <__udivsi3> - aa2c: 100b883a mov r5,r2 - aa30: a009883a mov r4,r20 - aa34: 1021883a mov r16,r2 - aa38: 0002b2c0 call 2b2c <__mulsi3> - aa3c: b80b883a mov r5,r23 - aa40: 8809883a mov r4,r17 - aa44: 1029883a mov r20,r2 - aa48: 0002b240 call 2b24 <__umodsi3> - aa4c: d9400217 ldw r5,8(sp) - aa50: 1004943a slli r2,r2,16 - aa54: 28ffffcc andi r3,r5,65535 - aa58: 10c4b03a or r2,r2,r3 - aa5c: 1500032e bgeu r2,r20,aa6c <__umoddi3+0x4bc> - aa60: 1585883a add r2,r2,r22 - aa64: 843fffc4 addi r16,r16,-1 - aa68: 1580562e bgeu r2,r22,abc4 <__umoddi3+0x614> - aa6c: d9800017 ldw r6,0(sp) - aa70: e022943a slli r17,fp,16 - aa74: 302ed43a srli r23,r6,16 - aa78: 8462b03a or r17,r16,r17 - aa7c: 34ffffcc andi r19,r6,65535 - aa80: 882ad43a srli r21,r17,16 - aa84: 8c7fffcc andi r17,r17,65535 - aa88: 8809883a mov r4,r17 - aa8c: 980b883a mov r5,r19 - aa90: 1521c83a sub r16,r2,r20 - aa94: 0002b2c0 call 2b2c <__mulsi3> - aa98: 8809883a mov r4,r17 - aa9c: b80b883a mov r5,r23 - aaa0: 1029883a mov r20,r2 - aaa4: 0002b2c0 call 2b2c <__mulsi3> - aaa8: 980b883a mov r5,r19 - aaac: a809883a mov r4,r21 - aab0: 1023883a mov r17,r2 - aab4: 0002b2c0 call 2b2c <__mulsi3> - aab8: a809883a mov r4,r21 - aabc: b80b883a mov r5,r23 - aac0: 1027883a mov r19,r2 - aac4: 0002b2c0 call 2b2c <__mulsi3> - aac8: 100b883a mov r5,r2 - aacc: a004d43a srli r2,r20,16 - aad0: 8ce3883a add r17,r17,r19 - aad4: 1449883a add r4,r2,r17 - aad8: 24c0022e bgeu r4,r19,aae4 <__umoddi3+0x534> - aadc: 00800074 movhi r2,1 - aae0: 288b883a add r5,r5,r2 - aae4: 2004d43a srli r2,r4,16 - aae8: 2008943a slli r4,r4,16 - aaec: a0ffffcc andi r3,r20,65535 - aaf0: 288d883a add r6,r5,r2 - aaf4: 20c9883a add r4,r4,r3 - aaf8: 81800b36 bltu r16,r6,ab28 <__umoddi3+0x578> - aafc: 81804026 beq r16,r6,ac00 <__umoddi3+0x650> - ab00: 818dc83a sub r6,r16,r6 - ab04: 00000f06 br ab44 <__umoddi3+0x594> - ab08: 30c5c83a sub r2,r6,r3 - ab0c: 182d883a mov r22,r3 - ab10: 8084d83a srl r2,r16,r2 - ab14: a8c6983a sll r3,r21,r3 - ab18: 9da6983a sll r19,r19,r22 - ab1c: 85a0983a sll r16,r16,r22 - ab20: 18aab03a or r21,r3,r2 - ab24: 003f1d06 br a79c <__umoddi3+0x1ec> - ab28: d8c00017 ldw r3,0(sp) - ab2c: 20c5c83a sub r2,r4,r3 - ab30: 2089803a cmpltu r4,r4,r2 - ab34: 3587c83a sub r3,r6,r22 - ab38: 1907c83a sub r3,r3,r4 - ab3c: 80cdc83a sub r6,r16,r3 - ab40: 1009883a mov r4,r2 - ab44: d9400117 ldw r5,4(sp) - ab48: 2905c83a sub r2,r5,r4 - ab4c: 2887803a cmpltu r3,r5,r2 - ab50: 30c7c83a sub r3,r6,r3 - ab54: d9800317 ldw r6,12(sp) - ab58: 1484d83a srl r2,r2,r18 - ab5c: 1988983a sll r4,r3,r6 - ab60: 1c86d83a srl r3,r3,r18 - ab64: 2088b03a or r4,r4,r2 - ab68: 2011883a mov r8,r4 - ab6c: 1813883a mov r9,r3 - ab70: d9000415 stw r4,16(sp) - ab74: d8c00515 stw r3,20(sp) - ab78: 003ed406 br a6cc <__umoddi3+0x11c> - ab7c: 01400604 movi r5,24 - ab80: 2805883a mov r2,r5 - ab84: 003ea606 br a620 <__umoddi3+0x70> - ab88: 01400204 movi r5,8 - ab8c: 2805883a mov r2,r5 - ab90: 003ea306 br a620 <__umoddi3+0x70> - ab94: 01400204 movi r5,8 - ab98: 2805883a mov r2,r5 - ab9c: 003edf06 br a71c <__umoddi3+0x16c> - aba0: 01400204 movi r5,8 - aba4: 2805883a mov r2,r5 - aba8: 003ef206 br a774 <__umoddi3+0x1c4> - abac: 01400604 movi r5,24 - abb0: 2805883a mov r2,r5 - abb4: 003eef06 br a774 <__umoddi3+0x1c4> - abb8: 01400604 movi r5,24 - abbc: 2805883a mov r2,r5 - abc0: 003ed606 br a71c <__umoddi3+0x16c> - abc4: 153fa92e bgeu r2,r20,aa6c <__umoddi3+0x4bc> - abc8: 843fffc4 addi r16,r16,-1 - abcc: 1585883a add r2,r2,r22 - abd0: 003fa606 br aa6c <__umoddi3+0x4bc> - abd4: 157f912e bgeu r2,r21,aa1c <__umoddi3+0x46c> - abd8: e73fffc4 addi fp,fp,-1 - abdc: 1585883a add r2,r2,r22 - abe0: 003f8e06 br aa1c <__umoddi3+0x46c> - abe4: 157f542e bgeu r2,r21,a938 <__umoddi3+0x388> - abe8: 14c5883a add r2,r2,r19 - abec: 003f5206 br a938 <__umoddi3+0x388> - abf0: 14c5883a add r2,r2,r19 - abf4: 003efc06 br a7e8 <__umoddi3+0x238> - abf8: 14c5883a add r2,r2,r19 - abfc: 003ea606 br a698 <__umoddi3+0xe8> - ac00: d8800117 ldw r2,4(sp) - ac04: 113fc836 bltu r2,r4,ab28 <__umoddi3+0x578> - ac08: 000d883a mov r6,zero - ac0c: 003fcd06 br ab44 <__umoddi3+0x594> - -0000ac10 <_fpadd_parts>: - ac10: defff804 addi sp,sp,-32 - ac14: dcc00315 stw r19,12(sp) - ac18: 2027883a mov r19,r4 - ac1c: 21000017 ldw r4,0(r4) - ac20: 00c00044 movi r3,1 - ac24: dd400515 stw r21,20(sp) - ac28: dd000415 stw r20,16(sp) - ac2c: ddc00715 stw r23,28(sp) - ac30: dd800615 stw r22,24(sp) - ac34: dc800215 stw r18,8(sp) - ac38: dc400115 stw r17,4(sp) - ac3c: dc000015 stw r16,0(sp) - ac40: 282b883a mov r21,r5 - ac44: 3029883a mov r20,r6 - ac48: 1900632e bgeu r3,r4,add8 <_fpadd_parts+0x1c8> - ac4c: 28800017 ldw r2,0(r5) - ac50: 1880812e bgeu r3,r2,ae58 <_fpadd_parts+0x248> - ac54: 00c00104 movi r3,4 - ac58: 20c0dc26 beq r4,r3,afcc <_fpadd_parts+0x3bc> - ac5c: 10c07e26 beq r2,r3,ae58 <_fpadd_parts+0x248> - ac60: 00c00084 movi r3,2 - ac64: 10c06726 beq r2,r3,ae04 <_fpadd_parts+0x1f4> - ac68: 20c07b26 beq r4,r3,ae58 <_fpadd_parts+0x248> - ac6c: 9dc00217 ldw r23,8(r19) - ac70: 28c00217 ldw r3,8(r5) - ac74: 9c400317 ldw r17,12(r19) - ac78: 2bc00317 ldw r15,12(r5) - ac7c: b8cdc83a sub r6,r23,r3 - ac80: 9c800417 ldw r18,16(r19) - ac84: 2c000417 ldw r16,16(r5) - ac88: 3009883a mov r4,r6 - ac8c: 30009716 blt r6,zero,aeec <_fpadd_parts+0x2dc> - ac90: 00800fc4 movi r2,63 - ac94: 11806b16 blt r2,r6,ae44 <_fpadd_parts+0x234> - ac98: 0100a40e bge zero,r4,af2c <_fpadd_parts+0x31c> - ac9c: 35bff804 addi r22,r6,-32 - aca0: b000bc16 blt r22,zero,af94 <_fpadd_parts+0x384> - aca4: 8596d83a srl r11,r16,r22 - aca8: 0019883a mov r12,zero - acac: 0013883a mov r9,zero - acb0: 01000044 movi r4,1 - acb4: 0015883a mov r10,zero - acb8: b000be16 blt r22,zero,afb4 <_fpadd_parts+0x3a4> - acbc: 2590983a sll r8,r4,r22 - acc0: 000f883a mov r7,zero - acc4: 00bfffc4 movi r2,-1 - acc8: 3889883a add r4,r7,r2 - accc: 408b883a add r5,r8,r2 - acd0: 21cd803a cmpltu r6,r4,r7 - acd4: 314b883a add r5,r6,r5 - acd8: 7904703a and r2,r15,r4 - acdc: 8146703a and r3,r16,r5 - ace0: 10c4b03a or r2,r2,r3 - ace4: 10000226 beq r2,zero,acf0 <_fpadd_parts+0xe0> - ace8: 02400044 movi r9,1 - acec: 0015883a mov r10,zero - acf0: 5a5eb03a or r15,r11,r9 - acf4: 62a0b03a or r16,r12,r10 - acf8: 99400117 ldw r5,4(r19) - acfc: a8800117 ldw r2,4(r21) - ad00: 28806e26 beq r5,r2,aebc <_fpadd_parts+0x2ac> - ad04: 28006626 beq r5,zero,aea0 <_fpadd_parts+0x290> - ad08: 7c45c83a sub r2,r15,r17 - ad0c: 7889803a cmpltu r4,r15,r2 - ad10: 8487c83a sub r3,r16,r18 - ad14: 1909c83a sub r4,r3,r4 - ad18: 100d883a mov r6,r2 - ad1c: 200f883a mov r7,r4 - ad20: 38007716 blt r7,zero,af00 <_fpadd_parts+0x2f0> - ad24: a5c00215 stw r23,8(r20) - ad28: a1c00415 stw r7,16(r20) - ad2c: a0000115 stw zero,4(r20) - ad30: a1800315 stw r6,12(r20) - ad34: a2000317 ldw r8,12(r20) - ad38: a2400417 ldw r9,16(r20) - ad3c: 00bfffc4 movi r2,-1 - ad40: 408b883a add r5,r8,r2 - ad44: 2a09803a cmpltu r4,r5,r8 - ad48: 488d883a add r6,r9,r2 - ad4c: 01c40034 movhi r7,4096 - ad50: 39ffffc4 addi r7,r7,-1 - ad54: 218d883a add r6,r4,r6 - ad58: 39801736 bltu r7,r6,adb8 <_fpadd_parts+0x1a8> - ad5c: 31c06526 beq r6,r7,aef4 <_fpadd_parts+0x2e4> - ad60: a3000217 ldw r12,8(r20) - ad64: 4209883a add r4,r8,r8 - ad68: 00bfffc4 movi r2,-1 - ad6c: 220f803a cmpltu r7,r4,r8 - ad70: 4a4b883a add r5,r9,r9 - ad74: 394f883a add r7,r7,r5 - ad78: 2095883a add r10,r4,r2 - ad7c: 3897883a add r11,r7,r2 - ad80: 510d803a cmpltu r6,r10,r4 - ad84: 6099883a add r12,r12,r2 - ad88: 32d7883a add r11,r6,r11 - ad8c: 00840034 movhi r2,4096 - ad90: 10bfffc4 addi r2,r2,-1 - ad94: 2011883a mov r8,r4 - ad98: 3813883a mov r9,r7 - ad9c: a1000315 stw r4,12(r20) - ada0: a1c00415 stw r7,16(r20) - ada4: a3000215 stw r12,8(r20) - ada8: 12c00336 bltu r2,r11,adb8 <_fpadd_parts+0x1a8> - adac: 58bfed1e bne r11,r2,ad64 <_fpadd_parts+0x154> - adb0: 00bfff84 movi r2,-2 - adb4: 12bfeb2e bgeu r2,r10,ad64 <_fpadd_parts+0x154> - adb8: a2800417 ldw r10,16(r20) - adbc: 008000c4 movi r2,3 - adc0: 00c80034 movhi r3,8192 - adc4: 18ffffc4 addi r3,r3,-1 - adc8: a2400317 ldw r9,12(r20) - adcc: a0800015 stw r2,0(r20) - add0: 1a802336 bltu r3,r10,ae60 <_fpadd_parts+0x250> - add4: a027883a mov r19,r20 - add8: 9805883a mov r2,r19 - addc: ddc00717 ldw r23,28(sp) - ade0: dd800617 ldw r22,24(sp) - ade4: dd400517 ldw r21,20(sp) - ade8: dd000417 ldw r20,16(sp) - adec: dcc00317 ldw r19,12(sp) - adf0: dc800217 ldw r18,8(sp) - adf4: dc400117 ldw r17,4(sp) - adf8: dc000017 ldw r16,0(sp) - adfc: dec00804 addi sp,sp,32 - ae00: f800283a ret - ae04: 20fff41e bne r4,r3,add8 <_fpadd_parts+0x1c8> - ae08: 31000015 stw r4,0(r6) - ae0c: 98800117 ldw r2,4(r19) - ae10: 30800115 stw r2,4(r6) - ae14: 98c00217 ldw r3,8(r19) - ae18: 30c00215 stw r3,8(r6) - ae1c: 98800317 ldw r2,12(r19) - ae20: 30800315 stw r2,12(r6) - ae24: 98c00417 ldw r3,16(r19) - ae28: 30c00415 stw r3,16(r6) - ae2c: 98800117 ldw r2,4(r19) - ae30: 28c00117 ldw r3,4(r5) - ae34: 3027883a mov r19,r6 - ae38: 10c4703a and r2,r2,r3 - ae3c: 30800115 stw r2,4(r6) - ae40: 003fe506 br add8 <_fpadd_parts+0x1c8> - ae44: 1dc02616 blt r3,r23,aee0 <_fpadd_parts+0x2d0> - ae48: 0023883a mov r17,zero - ae4c: 182f883a mov r23,r3 - ae50: 0025883a mov r18,zero - ae54: 003fa806 br acf8 <_fpadd_parts+0xe8> - ae58: a827883a mov r19,r21 - ae5c: 003fde06 br add8 <_fpadd_parts+0x1c8> - ae60: 01800044 movi r6,1 - ae64: 500497fa slli r2,r10,31 - ae68: 4808d07a srli r4,r9,1 - ae6c: 518ad83a srl r5,r10,r6 - ae70: a2000217 ldw r8,8(r20) - ae74: 1108b03a or r4,r2,r4 - ae78: 0007883a mov r3,zero - ae7c: 4984703a and r2,r9,r6 - ae80: 208cb03a or r6,r4,r2 - ae84: 28ceb03a or r7,r5,r3 - ae88: 42000044 addi r8,r8,1 - ae8c: a027883a mov r19,r20 - ae90: a1c00415 stw r7,16(r20) - ae94: a2000215 stw r8,8(r20) - ae98: a1800315 stw r6,12(r20) - ae9c: 003fce06 br add8 <_fpadd_parts+0x1c8> - aea0: 8bc5c83a sub r2,r17,r15 - aea4: 8889803a cmpltu r4,r17,r2 - aea8: 9407c83a sub r3,r18,r16 - aeac: 1909c83a sub r4,r3,r4 - aeb0: 100d883a mov r6,r2 - aeb4: 200f883a mov r7,r4 - aeb8: 003f9906 br ad20 <_fpadd_parts+0x110> - aebc: 7c45883a add r2,r15,r17 - aec0: 13c9803a cmpltu r4,r2,r15 - aec4: 8487883a add r3,r16,r18 - aec8: 20c9883a add r4,r4,r3 - aecc: a1400115 stw r5,4(r20) - aed0: a5c00215 stw r23,8(r20) - aed4: a0800315 stw r2,12(r20) - aed8: a1000415 stw r4,16(r20) - aedc: 003fb606 br adb8 <_fpadd_parts+0x1a8> - aee0: 001f883a mov r15,zero - aee4: 0021883a mov r16,zero - aee8: 003f8306 br acf8 <_fpadd_parts+0xe8> - aeec: 018dc83a sub r6,zero,r6 - aef0: 003f6706 br ac90 <_fpadd_parts+0x80> - aef4: 00bfff84 movi r2,-2 - aef8: 117faf36 bltu r2,r5,adb8 <_fpadd_parts+0x1a8> - aefc: 003f9806 br ad60 <_fpadd_parts+0x150> - af00: 0005883a mov r2,zero - af04: 1189c83a sub r4,r2,r6 - af08: 1105803a cmpltu r2,r2,r4 - af0c: 01cbc83a sub r5,zero,r7 - af10: 2885c83a sub r2,r5,r2 - af14: 01800044 movi r6,1 - af18: a1800115 stw r6,4(r20) - af1c: a5c00215 stw r23,8(r20) - af20: a1000315 stw r4,12(r20) - af24: a0800415 stw r2,16(r20) - af28: 003f8206 br ad34 <_fpadd_parts+0x124> - af2c: 203f7226 beq r4,zero,acf8 <_fpadd_parts+0xe8> - af30: 35bff804 addi r22,r6,-32 - af34: b9af883a add r23,r23,r6 - af38: b0003116 blt r22,zero,b000 <_fpadd_parts+0x3f0> - af3c: 959ad83a srl r13,r18,r22 - af40: 001d883a mov r14,zero - af44: 000f883a mov r7,zero - af48: 01000044 movi r4,1 - af4c: 0011883a mov r8,zero - af50: b0002516 blt r22,zero,afe8 <_fpadd_parts+0x3d8> - af54: 2594983a sll r10,r4,r22 - af58: 0013883a mov r9,zero - af5c: 00bfffc4 movi r2,-1 - af60: 4889883a add r4,r9,r2 - af64: 508b883a add r5,r10,r2 - af68: 224d803a cmpltu r6,r4,r9 - af6c: 314b883a add r5,r6,r5 - af70: 8904703a and r2,r17,r4 - af74: 9146703a and r3,r18,r5 - af78: 10c4b03a or r2,r2,r3 - af7c: 10000226 beq r2,zero,af88 <_fpadd_parts+0x378> - af80: 01c00044 movi r7,1 - af84: 0011883a mov r8,zero - af88: 69e2b03a or r17,r13,r7 - af8c: 7224b03a or r18,r14,r8 - af90: 003f5906 br acf8 <_fpadd_parts+0xe8> - af94: 8407883a add r3,r16,r16 - af98: 008007c4 movi r2,31 - af9c: 1185c83a sub r2,r2,r6 - afa0: 1886983a sll r3,r3,r2 - afa4: 7996d83a srl r11,r15,r6 - afa8: 8198d83a srl r12,r16,r6 - afac: 1ad6b03a or r11,r3,r11 - afb0: 003f3e06 br acac <_fpadd_parts+0x9c> - afb4: 2006d07a srli r3,r4,1 - afb8: 008007c4 movi r2,31 - afbc: 1185c83a sub r2,r2,r6 - afc0: 1890d83a srl r8,r3,r2 - afc4: 218e983a sll r7,r4,r6 - afc8: 003f3e06 br acc4 <_fpadd_parts+0xb4> - afcc: 113f821e bne r2,r4,add8 <_fpadd_parts+0x1c8> - afd0: 28c00117 ldw r3,4(r5) - afd4: 98800117 ldw r2,4(r19) - afd8: 10ff7f26 beq r2,r3,add8 <_fpadd_parts+0x1c8> - afdc: 04c00074 movhi r19,1 - afe0: 9cc11a04 addi r19,r19,1128 - afe4: 003f7c06 br add8 <_fpadd_parts+0x1c8> - afe8: 2006d07a srli r3,r4,1 - afec: 008007c4 movi r2,31 - aff0: 1185c83a sub r2,r2,r6 - aff4: 1894d83a srl r10,r3,r2 - aff8: 2192983a sll r9,r4,r6 - affc: 003fd706 br af5c <_fpadd_parts+0x34c> - b000: 9487883a add r3,r18,r18 - b004: 008007c4 movi r2,31 - b008: 1185c83a sub r2,r2,r6 - b00c: 1886983a sll r3,r3,r2 - b010: 899ad83a srl r13,r17,r6 - b014: 919cd83a srl r14,r18,r6 - b018: 1b5ab03a or r13,r3,r13 - b01c: 003fc906 br af44 <_fpadd_parts+0x334> - -0000b020 <__subdf3>: - b020: deffea04 addi sp,sp,-88 - b024: dcc01415 stw r19,80(sp) - b028: dcc00404 addi r19,sp,16 - b02c: 2011883a mov r8,r4 - b030: 2813883a mov r9,r5 - b034: dc401315 stw r17,76(sp) - b038: d809883a mov r4,sp - b03c: 980b883a mov r5,r19 - b040: dc400904 addi r17,sp,36 - b044: dfc01515 stw ra,84(sp) - b048: da400115 stw r9,4(sp) - b04c: d9c00315 stw r7,12(sp) - b050: da000015 stw r8,0(sp) - b054: d9800215 stw r6,8(sp) - b058: 000c1f40 call c1f4 <__unpack_d> - b05c: d9000204 addi r4,sp,8 - b060: 880b883a mov r5,r17 - b064: 000c1f40 call c1f4 <__unpack_d> - b068: d8800a17 ldw r2,40(sp) - b06c: 880b883a mov r5,r17 - b070: 9809883a mov r4,r19 - b074: d9800e04 addi r6,sp,56 - b078: 1080005c xori r2,r2,1 - b07c: d8800a15 stw r2,40(sp) - b080: 000ac100 call ac10 <_fpadd_parts> - b084: 1009883a mov r4,r2 - b088: 000bee00 call bee0 <__pack_d> - b08c: dfc01517 ldw ra,84(sp) - b090: dcc01417 ldw r19,80(sp) - b094: dc401317 ldw r17,76(sp) - b098: dec01604 addi sp,sp,88 - b09c: f800283a ret - -0000b0a0 <__adddf3>: - b0a0: deffea04 addi sp,sp,-88 - b0a4: dcc01415 stw r19,80(sp) - b0a8: dcc00404 addi r19,sp,16 - b0ac: 2011883a mov r8,r4 - b0b0: 2813883a mov r9,r5 - b0b4: dc401315 stw r17,76(sp) - b0b8: d809883a mov r4,sp - b0bc: 980b883a mov r5,r19 - b0c0: dc400904 addi r17,sp,36 - b0c4: dfc01515 stw ra,84(sp) - b0c8: da400115 stw r9,4(sp) - b0cc: d9c00315 stw r7,12(sp) - b0d0: da000015 stw r8,0(sp) - b0d4: d9800215 stw r6,8(sp) - b0d8: 000c1f40 call c1f4 <__unpack_d> - b0dc: d9000204 addi r4,sp,8 - b0e0: 880b883a mov r5,r17 - b0e4: 000c1f40 call c1f4 <__unpack_d> - b0e8: d9800e04 addi r6,sp,56 - b0ec: 9809883a mov r4,r19 - b0f0: 880b883a mov r5,r17 - b0f4: 000ac100 call ac10 <_fpadd_parts> - b0f8: 1009883a mov r4,r2 - b0fc: 000bee00 call bee0 <__pack_d> - b100: dfc01517 ldw ra,84(sp) - b104: dcc01417 ldw r19,80(sp) - b108: dc401317 ldw r17,76(sp) - b10c: dec01604 addi sp,sp,88 - b110: f800283a ret - -0000b114 <__muldf3>: - b114: deffe004 addi sp,sp,-128 - b118: dc401815 stw r17,96(sp) - b11c: dc400404 addi r17,sp,16 - b120: 2011883a mov r8,r4 - b124: 2813883a mov r9,r5 - b128: dc001715 stw r16,92(sp) - b12c: d809883a mov r4,sp - b130: 880b883a mov r5,r17 - b134: dc000904 addi r16,sp,36 - b138: dfc01f15 stw ra,124(sp) - b13c: da400115 stw r9,4(sp) - b140: d9c00315 stw r7,12(sp) - b144: da000015 stw r8,0(sp) - b148: d9800215 stw r6,8(sp) - b14c: ddc01e15 stw r23,120(sp) - b150: dd801d15 stw r22,116(sp) - b154: dd401c15 stw r21,112(sp) - b158: dd001b15 stw r20,108(sp) - b15c: dcc01a15 stw r19,104(sp) - b160: dc801915 stw r18,100(sp) - b164: 000c1f40 call c1f4 <__unpack_d> - b168: d9000204 addi r4,sp,8 - b16c: 800b883a mov r5,r16 - b170: 000c1f40 call c1f4 <__unpack_d> - b174: d9000417 ldw r4,16(sp) - b178: 00800044 movi r2,1 - b17c: 1100102e bgeu r2,r4,b1c0 <__muldf3+0xac> - b180: d8c00917 ldw r3,36(sp) - b184: 10c0062e bgeu r2,r3,b1a0 <__muldf3+0x8c> - b188: 00800104 movi r2,4 - b18c: 20800a26 beq r4,r2,b1b8 <__muldf3+0xa4> - b190: 1880cc26 beq r3,r2,b4c4 <__muldf3+0x3b0> - b194: 00800084 movi r2,2 - b198: 20800926 beq r4,r2,b1c0 <__muldf3+0xac> - b19c: 1880191e bne r3,r2,b204 <__muldf3+0xf0> - b1a0: d8c00a17 ldw r3,40(sp) - b1a4: d8800517 ldw r2,20(sp) - b1a8: 8009883a mov r4,r16 - b1ac: 10c4c03a cmpne r2,r2,r3 - b1b0: d8800a15 stw r2,40(sp) - b1b4: 00000706 br b1d4 <__muldf3+0xc0> - b1b8: 00800084 movi r2,2 - b1bc: 1880c326 beq r3,r2,b4cc <__muldf3+0x3b8> - b1c0: d8800517 ldw r2,20(sp) - b1c4: d8c00a17 ldw r3,40(sp) - b1c8: 8809883a mov r4,r17 - b1cc: 10c4c03a cmpne r2,r2,r3 - b1d0: d8800515 stw r2,20(sp) - b1d4: 000bee00 call bee0 <__pack_d> - b1d8: dfc01f17 ldw ra,124(sp) - b1dc: ddc01e17 ldw r23,120(sp) - b1e0: dd801d17 ldw r22,116(sp) - b1e4: dd401c17 ldw r21,112(sp) - b1e8: dd001b17 ldw r20,108(sp) - b1ec: dcc01a17 ldw r19,104(sp) - b1f0: dc801917 ldw r18,100(sp) - b1f4: dc401817 ldw r17,96(sp) - b1f8: dc001717 ldw r16,92(sp) - b1fc: dec02004 addi sp,sp,128 - b200: f800283a ret - b204: dd800717 ldw r22,28(sp) - b208: dc800c17 ldw r18,48(sp) - b20c: 002b883a mov r21,zero - b210: 0023883a mov r17,zero - b214: a80b883a mov r5,r21 - b218: b00d883a mov r6,r22 - b21c: 880f883a mov r7,r17 - b220: ddc00817 ldw r23,32(sp) - b224: dcc00d17 ldw r19,52(sp) - b228: 9009883a mov r4,r18 - b22c: 000bd3c0 call bd3c <__muldi3> - b230: 001b883a mov r13,zero - b234: 680f883a mov r7,r13 - b238: b009883a mov r4,r22 - b23c: 000b883a mov r5,zero - b240: 980d883a mov r6,r19 - b244: b82d883a mov r22,r23 - b248: 002f883a mov r23,zero - b24c: db401615 stw r13,88(sp) - b250: d8801315 stw r2,76(sp) - b254: d8c01415 stw r3,80(sp) - b258: dcc01515 stw r19,84(sp) - b25c: 000bd3c0 call bd3c <__muldi3> - b260: b00d883a mov r6,r22 - b264: 000b883a mov r5,zero - b268: 9009883a mov r4,r18 - b26c: b80f883a mov r7,r23 - b270: 1021883a mov r16,r2 - b274: 1823883a mov r17,r3 - b278: 000bd3c0 call bd3c <__muldi3> - b27c: 8085883a add r2,r16,r2 - b280: 140d803a cmpltu r6,r2,r16 - b284: 88c7883a add r3,r17,r3 - b288: 30cd883a add r6,r6,r3 - b28c: 1029883a mov r20,r2 - b290: 302b883a mov r21,r6 - b294: da801317 ldw r10,76(sp) - b298: dac01417 ldw r11,80(sp) - b29c: db001517 ldw r12,84(sp) - b2a0: db401617 ldw r13,88(sp) - b2a4: 3440612e bgeu r6,r17,b42c <__muldf3+0x318> - b2a8: 0009883a mov r4,zero - b2ac: 5105883a add r2,r10,r4 - b2b0: 128d803a cmpltu r6,r2,r10 - b2b4: 5d07883a add r3,r11,r20 - b2b8: 30cd883a add r6,r6,r3 - b2bc: 0021883a mov r16,zero - b2c0: 04400044 movi r17,1 - b2c4: 1025883a mov r18,r2 - b2c8: 3027883a mov r19,r6 - b2cc: 32c06236 bltu r6,r11,b458 <__muldf3+0x344> - b2d0: 59807a26 beq r11,r6,b4bc <__muldf3+0x3a8> - b2d4: 680b883a mov r5,r13 - b2d8: b80f883a mov r7,r23 - b2dc: 6009883a mov r4,r12 - b2e0: b00d883a mov r6,r22 - b2e4: 000bd3c0 call bd3c <__muldi3> - b2e8: 1009883a mov r4,r2 - b2ec: 000f883a mov r7,zero - b2f0: 1545883a add r2,r2,r21 - b2f4: 1111803a cmpltu r8,r2,r4 - b2f8: 19c7883a add r3,r3,r7 - b2fc: 40c7883a add r3,r8,r3 - b300: 88cb883a add r5,r17,r3 - b304: d8c00617 ldw r3,24(sp) - b308: 8089883a add r4,r16,r2 - b30c: d8800b17 ldw r2,44(sp) - b310: 18c00104 addi r3,r3,4 - b314: 240d803a cmpltu r6,r4,r16 - b318: 10c7883a add r3,r2,r3 - b31c: 2013883a mov r9,r4 - b320: d8800a17 ldw r2,40(sp) - b324: d9000517 ldw r4,20(sp) - b328: 314d883a add r6,r6,r5 - b32c: 3015883a mov r10,r6 - b330: 2088c03a cmpne r4,r4,r2 - b334: 00880034 movhi r2,8192 - b338: 10bfffc4 addi r2,r2,-1 - b33c: d9000f15 stw r4,60(sp) - b340: d8c01015 stw r3,64(sp) - b344: 1180162e bgeu r2,r6,b3a0 <__muldf3+0x28c> - b348: 1811883a mov r8,r3 - b34c: 101f883a mov r15,r2 - b350: 980497fa slli r2,r19,31 - b354: 9016d07a srli r11,r18,1 - b358: 500697fa slli r3,r10,31 - b35c: 480cd07a srli r6,r9,1 - b360: 500ed07a srli r7,r10,1 - b364: 12d6b03a or r11,r2,r11 - b368: 00800044 movi r2,1 - b36c: 198cb03a or r6,r3,r6 - b370: 4888703a and r4,r9,r2 - b374: 9818d07a srli r12,r19,1 - b378: 001b883a mov r13,zero - b37c: 03a00034 movhi r14,32768 - b380: 3013883a mov r9,r6 - b384: 3815883a mov r10,r7 - b388: 4091883a add r8,r8,r2 - b38c: 20000226 beq r4,zero,b398 <__muldf3+0x284> - b390: 5b64b03a or r18,r11,r13 - b394: 63a6b03a or r19,r12,r14 - b398: 7abfed36 bltu r15,r10,b350 <__muldf3+0x23c> - b39c: da001015 stw r8,64(sp) - b3a0: 00840034 movhi r2,4096 - b3a4: 10bfffc4 addi r2,r2,-1 - b3a8: 12801436 bltu r2,r10,b3fc <__muldf3+0x2e8> - b3ac: da001017 ldw r8,64(sp) - b3b0: 101f883a mov r15,r2 - b3b4: 4a45883a add r2,r9,r9 - b3b8: 124d803a cmpltu r6,r2,r9 - b3bc: 5287883a add r3,r10,r10 - b3c0: 9497883a add r11,r18,r18 - b3c4: 5c8f803a cmpltu r7,r11,r18 - b3c8: 9cd9883a add r12,r19,r19 - b3cc: 01000044 movi r4,1 - b3d0: 30cd883a add r6,r6,r3 - b3d4: 3b0f883a add r7,r7,r12 - b3d8: 423fffc4 addi r8,r8,-1 - b3dc: 1013883a mov r9,r2 - b3e0: 3015883a mov r10,r6 - b3e4: 111ab03a or r13,r2,r4 - b3e8: 98003016 blt r19,zero,b4ac <__muldf3+0x398> - b3ec: 5825883a mov r18,r11 - b3f0: 3827883a mov r19,r7 - b3f4: 7abfef2e bgeu r15,r10,b3b4 <__muldf3+0x2a0> - b3f8: da001015 stw r8,64(sp) - b3fc: 00803fc4 movi r2,255 - b400: 488e703a and r7,r9,r2 - b404: 00802004 movi r2,128 - b408: 0007883a mov r3,zero - b40c: 0011883a mov r8,zero - b410: 38801826 beq r7,r2,b474 <__muldf3+0x360> - b414: 008000c4 movi r2,3 - b418: d9000e04 addi r4,sp,56 - b41c: da801215 stw r10,72(sp) - b420: d8800e15 stw r2,56(sp) - b424: da401115 stw r9,68(sp) - b428: 003f6a06 br b1d4 <__muldf3+0xc0> - b42c: 89802126 beq r17,r6,b4b4 <__muldf3+0x3a0> - b430: 0009883a mov r4,zero - b434: 5105883a add r2,r10,r4 - b438: 128d803a cmpltu r6,r2,r10 - b43c: 5d07883a add r3,r11,r20 - b440: 30cd883a add r6,r6,r3 - b444: 0021883a mov r16,zero - b448: 0023883a mov r17,zero - b44c: 1025883a mov r18,r2 - b450: 3027883a mov r19,r6 - b454: 32ff9e2e bgeu r6,r11,b2d0 <__muldf3+0x1bc> - b458: 00800044 movi r2,1 - b45c: 8089883a add r4,r16,r2 - b460: 240d803a cmpltu r6,r4,r16 - b464: 344d883a add r6,r6,r17 - b468: 2021883a mov r16,r4 - b46c: 3023883a mov r17,r6 - b470: 003f9806 br b2d4 <__muldf3+0x1c0> - b474: 403fe71e bne r8,zero,b414 <__muldf3+0x300> - b478: 01004004 movi r4,256 - b47c: 4904703a and r2,r9,r4 - b480: 10c4b03a or r2,r2,r3 - b484: 103fe31e bne r2,zero,b414 <__muldf3+0x300> - b488: 94c4b03a or r2,r18,r19 - b48c: 103fe126 beq r2,zero,b414 <__muldf3+0x300> - b490: 49c5883a add r2,r9,r7 - b494: 1251803a cmpltu r8,r2,r9 - b498: 4291883a add r8,r8,r10 - b49c: 013fc004 movi r4,-256 - b4a0: 1112703a and r9,r2,r4 - b4a4: 4015883a mov r10,r8 - b4a8: 003fda06 br b414 <__muldf3+0x300> - b4ac: 6813883a mov r9,r13 - b4b0: 003fce06 br b3ec <__muldf3+0x2d8> - b4b4: 143f7c36 bltu r2,r16,b2a8 <__muldf3+0x194> - b4b8: 003fdd06 br b430 <__muldf3+0x31c> - b4bc: 12bf852e bgeu r2,r10,b2d4 <__muldf3+0x1c0> - b4c0: 003fe506 br b458 <__muldf3+0x344> - b4c4: 00800084 movi r2,2 - b4c8: 20bf351e bne r4,r2,b1a0 <__muldf3+0x8c> - b4cc: 01000074 movhi r4,1 - b4d0: 21011a04 addi r4,r4,1128 - b4d4: 003f3f06 br b1d4 <__muldf3+0xc0> - -0000b4d8 <__divdf3>: - b4d8: deffed04 addi sp,sp,-76 - b4dc: dcc01115 stw r19,68(sp) - b4e0: dcc00404 addi r19,sp,16 - b4e4: 2011883a mov r8,r4 - b4e8: 2813883a mov r9,r5 - b4ec: dc000e15 stw r16,56(sp) - b4f0: d809883a mov r4,sp - b4f4: 980b883a mov r5,r19 - b4f8: dc000904 addi r16,sp,36 - b4fc: dfc01215 stw ra,72(sp) - b500: da400115 stw r9,4(sp) - b504: d9c00315 stw r7,12(sp) - b508: da000015 stw r8,0(sp) - b50c: d9800215 stw r6,8(sp) - b510: dc801015 stw r18,64(sp) - b514: dc400f15 stw r17,60(sp) - b518: 000c1f40 call c1f4 <__unpack_d> - b51c: d9000204 addi r4,sp,8 - b520: 800b883a mov r5,r16 - b524: 000c1f40 call c1f4 <__unpack_d> - b528: d9000417 ldw r4,16(sp) - b52c: 00800044 movi r2,1 - b530: 11000b2e bgeu r2,r4,b560 <__divdf3+0x88> - b534: d9400917 ldw r5,36(sp) - b538: 1140762e bgeu r2,r5,b714 <__divdf3+0x23c> - b53c: d8800517 ldw r2,20(sp) - b540: d8c00a17 ldw r3,40(sp) - b544: 01800104 movi r6,4 - b548: 10c4f03a xor r2,r2,r3 - b54c: d8800515 stw r2,20(sp) - b550: 21800226 beq r4,r6,b55c <__divdf3+0x84> - b554: 00800084 movi r2,2 - b558: 2080141e bne r4,r2,b5ac <__divdf3+0xd4> - b55c: 29000926 beq r5,r4,b584 <__divdf3+0xac> - b560: 9809883a mov r4,r19 - b564: 000bee00 call bee0 <__pack_d> - b568: dfc01217 ldw ra,72(sp) - b56c: dcc01117 ldw r19,68(sp) - b570: dc801017 ldw r18,64(sp) - b574: dc400f17 ldw r17,60(sp) - b578: dc000e17 ldw r16,56(sp) - b57c: dec01304 addi sp,sp,76 - b580: f800283a ret - b584: 01000074 movhi r4,1 - b588: 21011a04 addi r4,r4,1128 - b58c: 000bee00 call bee0 <__pack_d> - b590: dfc01217 ldw ra,72(sp) - b594: dcc01117 ldw r19,68(sp) - b598: dc801017 ldw r18,64(sp) - b59c: dc400f17 ldw r17,60(sp) - b5a0: dc000e17 ldw r16,56(sp) - b5a4: dec01304 addi sp,sp,76 - b5a8: f800283a ret - b5ac: 29805b26 beq r5,r6,b71c <__divdf3+0x244> - b5b0: 28802d26 beq r5,r2,b668 <__divdf3+0x190> - b5b4: d8c00617 ldw r3,24(sp) - b5b8: d8800b17 ldw r2,44(sp) - b5bc: d9c00817 ldw r7,32(sp) - b5c0: dc400d17 ldw r17,52(sp) - b5c4: 188bc83a sub r5,r3,r2 - b5c8: d9800717 ldw r6,28(sp) - b5cc: dc000c17 ldw r16,48(sp) - b5d0: d9400615 stw r5,24(sp) - b5d4: 3c403836 bltu r7,r17,b6b8 <__divdf3+0x1e0> - b5d8: 89c03626 beq r17,r7,b6b4 <__divdf3+0x1dc> - b5dc: 0015883a mov r10,zero - b5e0: 001d883a mov r14,zero - b5e4: 02c40034 movhi r11,4096 - b5e8: 001f883a mov r15,zero - b5ec: 003f883a mov ra,zero - b5f0: 04800f44 movi r18,61 - b5f4: 00000f06 br b634 <__divdf3+0x15c> - b5f8: 601d883a mov r14,r12 - b5fc: 681f883a mov r15,r13 - b600: 400d883a mov r6,r8 - b604: 100f883a mov r7,r2 - b608: 3191883a add r8,r6,r6 - b60c: 5808d07a srli r4,r11,1 - b610: 4185803a cmpltu r2,r8,r6 - b614: 39d3883a add r9,r7,r7 - b618: 28c6b03a or r3,r5,r3 - b61c: 1245883a add r2,r2,r9 - b620: 1815883a mov r10,r3 - b624: 2017883a mov r11,r4 - b628: 400d883a mov r6,r8 - b62c: 100f883a mov r7,r2 - b630: fc801726 beq ra,r18,b690 <__divdf3+0x1b8> - b634: 580a97fa slli r5,r11,31 - b638: 5006d07a srli r3,r10,1 - b63c: ffc00044 addi ra,ra,1 - b640: 3c7ff136 bltu r7,r17,b608 <__divdf3+0x130> - b644: 3411c83a sub r8,r6,r16 - b648: 3205803a cmpltu r2,r6,r8 - b64c: 3c53c83a sub r9,r7,r17 - b650: 7298b03a or r12,r14,r10 - b654: 7adab03a or r13,r15,r11 - b658: 4885c83a sub r2,r9,r2 - b65c: 89ffe61e bne r17,r7,b5f8 <__divdf3+0x120> - b660: 343fe936 bltu r6,r16,b608 <__divdf3+0x130> - b664: 003fe406 br b5f8 <__divdf3+0x120> - b668: 9809883a mov r4,r19 - b66c: d9800415 stw r6,16(sp) - b670: 000bee00 call bee0 <__pack_d> - b674: dfc01217 ldw ra,72(sp) - b678: dcc01117 ldw r19,68(sp) - b67c: dc801017 ldw r18,64(sp) - b680: dc400f17 ldw r17,60(sp) - b684: dc000e17 ldw r16,56(sp) - b688: dec01304 addi sp,sp,76 - b68c: f800283a ret - b690: 00803fc4 movi r2,255 - b694: 7090703a and r8,r14,r2 - b698: 00802004 movi r2,128 - b69c: 0007883a mov r3,zero - b6a0: 0013883a mov r9,zero - b6a4: 40800d26 beq r8,r2,b6dc <__divdf3+0x204> - b6a8: dbc00815 stw r15,32(sp) - b6ac: db800715 stw r14,28(sp) - b6b0: 003fab06 br b560 <__divdf3+0x88> - b6b4: 343fc92e bgeu r6,r16,b5dc <__divdf3+0x104> - b6b8: 3185883a add r2,r6,r6 - b6bc: 1189803a cmpltu r4,r2,r6 - b6c0: 39c7883a add r3,r7,r7 - b6c4: 20c9883a add r4,r4,r3 - b6c8: 297fffc4 addi r5,r5,-1 - b6cc: 100d883a mov r6,r2 - b6d0: 200f883a mov r7,r4 - b6d4: d9400615 stw r5,24(sp) - b6d8: 003fc006 br b5dc <__divdf3+0x104> - b6dc: 483ff21e bne r9,zero,b6a8 <__divdf3+0x1d0> - b6e0: 01004004 movi r4,256 - b6e4: 7104703a and r2,r14,r4 - b6e8: 10c4b03a or r2,r2,r3 - b6ec: 103fee1e bne r2,zero,b6a8 <__divdf3+0x1d0> - b6f0: 31c4b03a or r2,r6,r7 - b6f4: 103fec26 beq r2,zero,b6a8 <__divdf3+0x1d0> - b6f8: 7205883a add r2,r14,r8 - b6fc: 1391803a cmpltu r8,r2,r14 - b700: 43d1883a add r8,r8,r15 - b704: 013fc004 movi r4,-256 - b708: 111c703a and r14,r2,r4 - b70c: 401f883a mov r15,r8 - b710: 003fe506 br b6a8 <__divdf3+0x1d0> - b714: 8009883a mov r4,r16 - b718: 003f9206 br b564 <__divdf3+0x8c> - b71c: 9809883a mov r4,r19 - b720: d8000715 stw zero,28(sp) - b724: d8000815 stw zero,32(sp) - b728: d8000615 stw zero,24(sp) - b72c: 003f8d06 br b564 <__divdf3+0x8c> - -0000b730 <__eqdf2>: - b730: deffef04 addi sp,sp,-68 - b734: dc400f15 stw r17,60(sp) - b738: dc400404 addi r17,sp,16 - b73c: 2005883a mov r2,r4 - b740: 2807883a mov r3,r5 - b744: dc000e15 stw r16,56(sp) - b748: d809883a mov r4,sp - b74c: 880b883a mov r5,r17 - b750: dc000904 addi r16,sp,36 - b754: d8c00115 stw r3,4(sp) - b758: d8800015 stw r2,0(sp) - b75c: d9800215 stw r6,8(sp) - b760: dfc01015 stw ra,64(sp) - b764: d9c00315 stw r7,12(sp) - b768: 000c1f40 call c1f4 <__unpack_d> - b76c: d9000204 addi r4,sp,8 - b770: 800b883a mov r5,r16 - b774: 000c1f40 call c1f4 <__unpack_d> - b778: d8800417 ldw r2,16(sp) - b77c: 00c00044 movi r3,1 - b780: 180d883a mov r6,r3 - b784: 1880062e bgeu r3,r2,b7a0 <__eqdf2+0x70> - b788: d8800917 ldw r2,36(sp) - b78c: 8809883a mov r4,r17 - b790: 800b883a mov r5,r16 - b794: 1880022e bgeu r3,r2,b7a0 <__eqdf2+0x70> - b798: 000c32c0 call c32c <__fpcmp_parts_d> - b79c: 100d883a mov r6,r2 - b7a0: 3005883a mov r2,r6 - b7a4: dfc01017 ldw ra,64(sp) - b7a8: dc400f17 ldw r17,60(sp) - b7ac: dc000e17 ldw r16,56(sp) - b7b0: dec01104 addi sp,sp,68 - b7b4: f800283a ret - -0000b7b8 <__nedf2>: - b7b8: deffef04 addi sp,sp,-68 - b7bc: dc400f15 stw r17,60(sp) - b7c0: dc400404 addi r17,sp,16 - b7c4: 2005883a mov r2,r4 - b7c8: 2807883a mov r3,r5 - b7cc: dc000e15 stw r16,56(sp) - b7d0: d809883a mov r4,sp - b7d4: 880b883a mov r5,r17 - b7d8: dc000904 addi r16,sp,36 - b7dc: d8c00115 stw r3,4(sp) - b7e0: d8800015 stw r2,0(sp) - b7e4: d9800215 stw r6,8(sp) - b7e8: dfc01015 stw ra,64(sp) - b7ec: d9c00315 stw r7,12(sp) - b7f0: 000c1f40 call c1f4 <__unpack_d> - b7f4: d9000204 addi r4,sp,8 - b7f8: 800b883a mov r5,r16 - b7fc: 000c1f40 call c1f4 <__unpack_d> - b800: d8800417 ldw r2,16(sp) - b804: 00c00044 movi r3,1 - b808: 180d883a mov r6,r3 - b80c: 1880062e bgeu r3,r2,b828 <__nedf2+0x70> - b810: d8800917 ldw r2,36(sp) - b814: 8809883a mov r4,r17 - b818: 800b883a mov r5,r16 - b81c: 1880022e bgeu r3,r2,b828 <__nedf2+0x70> - b820: 000c32c0 call c32c <__fpcmp_parts_d> - b824: 100d883a mov r6,r2 - b828: 3005883a mov r2,r6 - b82c: dfc01017 ldw ra,64(sp) - b830: dc400f17 ldw r17,60(sp) - b834: dc000e17 ldw r16,56(sp) - b838: dec01104 addi sp,sp,68 - b83c: f800283a ret - -0000b840 <__gtdf2>: - b840: deffef04 addi sp,sp,-68 - b844: dc400f15 stw r17,60(sp) - b848: dc400404 addi r17,sp,16 - b84c: 2005883a mov r2,r4 - b850: 2807883a mov r3,r5 - b854: dc000e15 stw r16,56(sp) - b858: d809883a mov r4,sp - b85c: 880b883a mov r5,r17 - b860: dc000904 addi r16,sp,36 - b864: d8c00115 stw r3,4(sp) - b868: d8800015 stw r2,0(sp) - b86c: d9800215 stw r6,8(sp) - b870: dfc01015 stw ra,64(sp) - b874: d9c00315 stw r7,12(sp) - b878: 000c1f40 call c1f4 <__unpack_d> - b87c: d9000204 addi r4,sp,8 - b880: 800b883a mov r5,r16 - b884: 000c1f40 call c1f4 <__unpack_d> - b888: d8800417 ldw r2,16(sp) - b88c: 00c00044 movi r3,1 - b890: 01bfffc4 movi r6,-1 - b894: 1880062e bgeu r3,r2,b8b0 <__gtdf2+0x70> - b898: d8800917 ldw r2,36(sp) - b89c: 8809883a mov r4,r17 - b8a0: 800b883a mov r5,r16 - b8a4: 1880022e bgeu r3,r2,b8b0 <__gtdf2+0x70> - b8a8: 000c32c0 call c32c <__fpcmp_parts_d> - b8ac: 100d883a mov r6,r2 - b8b0: 3005883a mov r2,r6 - b8b4: dfc01017 ldw ra,64(sp) - b8b8: dc400f17 ldw r17,60(sp) - b8bc: dc000e17 ldw r16,56(sp) - b8c0: dec01104 addi sp,sp,68 - b8c4: f800283a ret - -0000b8c8 <__gedf2>: - b8c8: deffef04 addi sp,sp,-68 - b8cc: dc400f15 stw r17,60(sp) - b8d0: dc400404 addi r17,sp,16 - b8d4: 2005883a mov r2,r4 - b8d8: 2807883a mov r3,r5 - b8dc: dc000e15 stw r16,56(sp) - b8e0: d809883a mov r4,sp - b8e4: 880b883a mov r5,r17 - b8e8: dc000904 addi r16,sp,36 - b8ec: d8c00115 stw r3,4(sp) - b8f0: d8800015 stw r2,0(sp) - b8f4: d9800215 stw r6,8(sp) - b8f8: dfc01015 stw ra,64(sp) - b8fc: d9c00315 stw r7,12(sp) - b900: 000c1f40 call c1f4 <__unpack_d> - b904: d9000204 addi r4,sp,8 - b908: 800b883a mov r5,r16 - b90c: 000c1f40 call c1f4 <__unpack_d> - b910: d8800417 ldw r2,16(sp) - b914: 00c00044 movi r3,1 - b918: 01bfffc4 movi r6,-1 - b91c: 1880062e bgeu r3,r2,b938 <__gedf2+0x70> - b920: d8800917 ldw r2,36(sp) - b924: 8809883a mov r4,r17 - b928: 800b883a mov r5,r16 - b92c: 1880022e bgeu r3,r2,b938 <__gedf2+0x70> - b930: 000c32c0 call c32c <__fpcmp_parts_d> - b934: 100d883a mov r6,r2 - b938: 3005883a mov r2,r6 - b93c: dfc01017 ldw ra,64(sp) - b940: dc400f17 ldw r17,60(sp) - b944: dc000e17 ldw r16,56(sp) - b948: dec01104 addi sp,sp,68 - b94c: f800283a ret - -0000b950 <__ltdf2>: - b950: deffef04 addi sp,sp,-68 - b954: dc400f15 stw r17,60(sp) - b958: dc400404 addi r17,sp,16 - b95c: 2005883a mov r2,r4 - b960: 2807883a mov r3,r5 - b964: dc000e15 stw r16,56(sp) - b968: d809883a mov r4,sp - b96c: 880b883a mov r5,r17 - b970: dc000904 addi r16,sp,36 - b974: d8c00115 stw r3,4(sp) - b978: d8800015 stw r2,0(sp) - b97c: d9800215 stw r6,8(sp) - b980: dfc01015 stw ra,64(sp) - b984: d9c00315 stw r7,12(sp) - b988: 000c1f40 call c1f4 <__unpack_d> - b98c: d9000204 addi r4,sp,8 - b990: 800b883a mov r5,r16 - b994: 000c1f40 call c1f4 <__unpack_d> - b998: d8800417 ldw r2,16(sp) - b99c: 00c00044 movi r3,1 - b9a0: 180d883a mov r6,r3 - b9a4: 1880062e bgeu r3,r2,b9c0 <__ltdf2+0x70> - b9a8: d8800917 ldw r2,36(sp) - b9ac: 8809883a mov r4,r17 - b9b0: 800b883a mov r5,r16 - b9b4: 1880022e bgeu r3,r2,b9c0 <__ltdf2+0x70> - b9b8: 000c32c0 call c32c <__fpcmp_parts_d> - b9bc: 100d883a mov r6,r2 - b9c0: 3005883a mov r2,r6 - b9c4: dfc01017 ldw ra,64(sp) - b9c8: dc400f17 ldw r17,60(sp) - b9cc: dc000e17 ldw r16,56(sp) - b9d0: dec01104 addi sp,sp,68 - b9d4: f800283a ret - -0000b9d8 <__floatsidf>: - b9d8: 2006d7fa srli r3,r4,31 - b9dc: defff604 addi sp,sp,-40 - b9e0: 008000c4 movi r2,3 - b9e4: dfc00915 stw ra,36(sp) - b9e8: dcc00815 stw r19,32(sp) - b9ec: dc800715 stw r18,28(sp) - b9f0: dc400615 stw r17,24(sp) - b9f4: dc000515 stw r16,20(sp) - b9f8: d8800015 stw r2,0(sp) - b9fc: d8c00115 stw r3,4(sp) - ba00: 20000f1e bne r4,zero,ba40 <__floatsidf+0x68> - ba04: 00800084 movi r2,2 - ba08: d8800015 stw r2,0(sp) - ba0c: d809883a mov r4,sp - ba10: 000bee00 call bee0 <__pack_d> - ba14: 1009883a mov r4,r2 - ba18: 180b883a mov r5,r3 - ba1c: 2005883a mov r2,r4 - ba20: 2807883a mov r3,r5 - ba24: dfc00917 ldw ra,36(sp) - ba28: dcc00817 ldw r19,32(sp) - ba2c: dc800717 ldw r18,28(sp) - ba30: dc400617 ldw r17,24(sp) - ba34: dc000517 ldw r16,20(sp) - ba38: dec00a04 addi sp,sp,40 - ba3c: f800283a ret - ba40: 00800f04 movi r2,60 - ba44: 1807003a cmpeq r3,r3,zero - ba48: d8800215 stw r2,8(sp) - ba4c: 18001126 beq r3,zero,ba94 <__floatsidf+0xbc> - ba50: 0027883a mov r19,zero - ba54: 2025883a mov r18,r4 - ba58: d9000315 stw r4,12(sp) - ba5c: dcc00415 stw r19,16(sp) - ba60: 000be600 call be60 <__clzsi2> - ba64: 11000744 addi r4,r2,29 - ba68: 013fe80e bge zero,r4,ba0c <__floatsidf+0x34> - ba6c: 10bfff44 addi r2,r2,-3 - ba70: 10000c16 blt r2,zero,baa4 <__floatsidf+0xcc> - ba74: 90a2983a sll r17,r18,r2 - ba78: 0021883a mov r16,zero - ba7c: d8800217 ldw r2,8(sp) - ba80: dc400415 stw r17,16(sp) - ba84: dc000315 stw r16,12(sp) - ba88: 1105c83a sub r2,r2,r4 - ba8c: d8800215 stw r2,8(sp) - ba90: 003fde06 br ba0c <__floatsidf+0x34> - ba94: 00a00034 movhi r2,32768 - ba98: 20800a26 beq r4,r2,bac4 <__floatsidf+0xec> - ba9c: 0109c83a sub r4,zero,r4 - baa0: 003feb06 br ba50 <__floatsidf+0x78> - baa4: 9006d07a srli r3,r18,1 - baa8: 008007c4 movi r2,31 - baac: 1105c83a sub r2,r2,r4 - bab0: 1886d83a srl r3,r3,r2 - bab4: 9922983a sll r17,r19,r4 - bab8: 9120983a sll r16,r18,r4 - babc: 1c62b03a or r17,r3,r17 - bac0: 003fee06 br ba7c <__floatsidf+0xa4> - bac4: 0009883a mov r4,zero - bac8: 01707834 movhi r5,49632 - bacc: 003fd306 br ba1c <__floatsidf+0x44> - -0000bad0 <__fixdfsi>: - bad0: defff804 addi sp,sp,-32 - bad4: 2005883a mov r2,r4 - bad8: 2807883a mov r3,r5 - badc: d809883a mov r4,sp - bae0: d9400204 addi r5,sp,8 - bae4: d8c00115 stw r3,4(sp) - bae8: d8800015 stw r2,0(sp) - baec: dfc00715 stw ra,28(sp) - baf0: 000c1f40 call c1f4 <__unpack_d> - baf4: d8c00217 ldw r3,8(sp) - baf8: 00800084 movi r2,2 - bafc: 1880051e bne r3,r2,bb14 <__fixdfsi+0x44> - bb00: 0007883a mov r3,zero - bb04: 1805883a mov r2,r3 - bb08: dfc00717 ldw ra,28(sp) - bb0c: dec00804 addi sp,sp,32 - bb10: f800283a ret - bb14: 00800044 movi r2,1 - bb18: 10fff92e bgeu r2,r3,bb00 <__fixdfsi+0x30> - bb1c: 00800104 movi r2,4 - bb20: 18800426 beq r3,r2,bb34 <__fixdfsi+0x64> - bb24: d8c00417 ldw r3,16(sp) - bb28: 183ff516 blt r3,zero,bb00 <__fixdfsi+0x30> - bb2c: 00800784 movi r2,30 - bb30: 10c0080e bge r2,r3,bb54 <__fixdfsi+0x84> - bb34: d8800317 ldw r2,12(sp) - bb38: 1000121e bne r2,zero,bb84 <__fixdfsi+0xb4> - bb3c: 00e00034 movhi r3,32768 - bb40: 18ffffc4 addi r3,r3,-1 - bb44: 1805883a mov r2,r3 - bb48: dfc00717 ldw ra,28(sp) - bb4c: dec00804 addi sp,sp,32 - bb50: f800283a ret - bb54: 00800f04 movi r2,60 - bb58: 10d1c83a sub r8,r2,r3 - bb5c: 40bff804 addi r2,r8,-32 - bb60: d9800517 ldw r6,20(sp) - bb64: d9c00617 ldw r7,24(sp) - bb68: 10000816 blt r2,zero,bb8c <__fixdfsi+0xbc> - bb6c: 3888d83a srl r4,r7,r2 - bb70: d8800317 ldw r2,12(sp) - bb74: 2007883a mov r3,r4 - bb78: 103fe226 beq r2,zero,bb04 <__fixdfsi+0x34> - bb7c: 0107c83a sub r3,zero,r4 - bb80: 003fe006 br bb04 <__fixdfsi+0x34> - bb84: 00e00034 movhi r3,32768 - bb88: 003fde06 br bb04 <__fixdfsi+0x34> - bb8c: 39c7883a add r3,r7,r7 - bb90: 008007c4 movi r2,31 - bb94: 1205c83a sub r2,r2,r8 - bb98: 1886983a sll r3,r3,r2 - bb9c: 3208d83a srl r4,r6,r8 - bba0: 1908b03a or r4,r3,r4 - bba4: 003ff206 br bb70 <__fixdfsi+0xa0> - -0000bba8 <__floatunsidf>: - bba8: defff204 addi sp,sp,-56 - bbac: dfc00d15 stw ra,52(sp) - bbb0: ddc00c15 stw r23,48(sp) - bbb4: dd800b15 stw r22,44(sp) - bbb8: dd400a15 stw r21,40(sp) - bbbc: dd000915 stw r20,36(sp) - bbc0: dcc00815 stw r19,32(sp) - bbc4: dc800715 stw r18,28(sp) - bbc8: dc400615 stw r17,24(sp) - bbcc: dc000515 stw r16,20(sp) - bbd0: d8000115 stw zero,4(sp) - bbd4: 20000f1e bne r4,zero,bc14 <__floatunsidf+0x6c> - bbd8: 00800084 movi r2,2 - bbdc: d8800015 stw r2,0(sp) - bbe0: d809883a mov r4,sp - bbe4: 000bee00 call bee0 <__pack_d> - bbe8: dfc00d17 ldw ra,52(sp) - bbec: ddc00c17 ldw r23,48(sp) - bbf0: dd800b17 ldw r22,44(sp) - bbf4: dd400a17 ldw r21,40(sp) - bbf8: dd000917 ldw r20,36(sp) - bbfc: dcc00817 ldw r19,32(sp) - bc00: dc800717 ldw r18,28(sp) - bc04: dc400617 ldw r17,24(sp) - bc08: dc000517 ldw r16,20(sp) - bc0c: dec00e04 addi sp,sp,56 - bc10: f800283a ret - bc14: 008000c4 movi r2,3 - bc18: 00c00f04 movi r3,60 - bc1c: 002f883a mov r23,zero - bc20: 202d883a mov r22,r4 - bc24: d8800015 stw r2,0(sp) - bc28: d8c00215 stw r3,8(sp) - bc2c: d9000315 stw r4,12(sp) - bc30: ddc00415 stw r23,16(sp) - bc34: 000be600 call be60 <__clzsi2> - bc38: 12400744 addi r9,r2,29 - bc3c: 48000b16 blt r9,zero,bc6c <__floatunsidf+0xc4> - bc40: 483fe726 beq r9,zero,bbe0 <__floatunsidf+0x38> - bc44: 10bfff44 addi r2,r2,-3 - bc48: 10002e16 blt r2,zero,bd04 <__floatunsidf+0x15c> - bc4c: b0a2983a sll r17,r22,r2 - bc50: 0021883a mov r16,zero - bc54: d8800217 ldw r2,8(sp) - bc58: dc400415 stw r17,16(sp) - bc5c: dc000315 stw r16,12(sp) - bc60: 1245c83a sub r2,r2,r9 - bc64: d8800215 stw r2,8(sp) - bc68: 003fdd06 br bbe0 <__floatunsidf+0x38> - bc6c: 0255c83a sub r10,zero,r9 - bc70: 51bff804 addi r6,r10,-32 - bc74: 30001b16 blt r6,zero,bce4 <__floatunsidf+0x13c> - bc78: b9a8d83a srl r20,r23,r6 - bc7c: 002b883a mov r21,zero - bc80: 000f883a mov r7,zero - bc84: 01000044 movi r4,1 - bc88: 0011883a mov r8,zero - bc8c: 30002516 blt r6,zero,bd24 <__floatunsidf+0x17c> - bc90: 21a6983a sll r19,r4,r6 - bc94: 0025883a mov r18,zero - bc98: 00bfffc4 movi r2,-1 - bc9c: 9089883a add r4,r18,r2 - bca0: 988b883a add r5,r19,r2 - bca4: 248d803a cmpltu r6,r4,r18 - bca8: 314b883a add r5,r6,r5 - bcac: b104703a and r2,r22,r4 - bcb0: b946703a and r3,r23,r5 - bcb4: 10c4b03a or r2,r2,r3 - bcb8: 10000226 beq r2,zero,bcc4 <__floatunsidf+0x11c> - bcbc: 01c00044 movi r7,1 - bcc0: 0011883a mov r8,zero - bcc4: d9000217 ldw r4,8(sp) - bcc8: a1c4b03a or r2,r20,r7 - bccc: aa06b03a or r3,r21,r8 - bcd0: 2249c83a sub r4,r4,r9 - bcd4: d8c00415 stw r3,16(sp) - bcd8: d9000215 stw r4,8(sp) - bcdc: d8800315 stw r2,12(sp) - bce0: 003fbf06 br bbe0 <__floatunsidf+0x38> - bce4: bdc7883a add r3,r23,r23 - bce8: 008007c4 movi r2,31 - bcec: 1285c83a sub r2,r2,r10 - bcf0: 1886983a sll r3,r3,r2 - bcf4: b2a8d83a srl r20,r22,r10 - bcf8: baaad83a srl r21,r23,r10 - bcfc: 1d28b03a or r20,r3,r20 - bd00: 003fdf06 br bc80 <__floatunsidf+0xd8> - bd04: b006d07a srli r3,r22,1 - bd08: 008007c4 movi r2,31 - bd0c: 1245c83a sub r2,r2,r9 - bd10: 1886d83a srl r3,r3,r2 - bd14: ba62983a sll r17,r23,r9 - bd18: b260983a sll r16,r22,r9 - bd1c: 1c62b03a or r17,r3,r17 - bd20: 003fcc06 br bc54 <__floatunsidf+0xac> - bd24: 2006d07a srli r3,r4,1 - bd28: 008007c4 movi r2,31 - bd2c: 1285c83a sub r2,r2,r10 - bd30: 18a6d83a srl r19,r3,r2 - bd34: 22a4983a sll r18,r4,r10 - bd38: 003fd706 br bc98 <__floatunsidf+0xf0> - -0000bd3c <__muldi3>: - bd3c: defff204 addi sp,sp,-56 - bd40: df000c15 stw fp,48(sp) - bd44: 3038d43a srli fp,r6,16 - bd48: dd000815 stw r20,32(sp) - bd4c: dc400515 stw r17,20(sp) - bd50: 2028d43a srli r20,r4,16 - bd54: 247fffcc andi r17,r4,65535 - bd58: dc000415 stw r16,16(sp) - bd5c: 343fffcc andi r16,r6,65535 - bd60: dcc00715 stw r19,28(sp) - bd64: d9000015 stw r4,0(sp) - bd68: 2827883a mov r19,r5 - bd6c: 8809883a mov r4,r17 - bd70: d9400115 stw r5,4(sp) - bd74: 800b883a mov r5,r16 - bd78: d9800215 stw r6,8(sp) - bd7c: dfc00d15 stw ra,52(sp) - bd80: d9c00315 stw r7,12(sp) - bd84: dd800a15 stw r22,40(sp) - bd88: dd400915 stw r21,36(sp) - bd8c: 302d883a mov r22,r6 - bd90: ddc00b15 stw r23,44(sp) - bd94: dc800615 stw r18,24(sp) - bd98: 0002b2c0 call 2b2c <__mulsi3> - bd9c: 8809883a mov r4,r17 - bda0: e00b883a mov r5,fp - bda4: 102b883a mov r21,r2 - bda8: 0002b2c0 call 2b2c <__mulsi3> - bdac: 800b883a mov r5,r16 - bdb0: a009883a mov r4,r20 - bdb4: 1023883a mov r17,r2 - bdb8: 0002b2c0 call 2b2c <__mulsi3> - bdbc: a009883a mov r4,r20 - bdc0: e00b883a mov r5,fp - bdc4: 1021883a mov r16,r2 - bdc8: 0002b2c0 call 2b2c <__mulsi3> - bdcc: a8ffffcc andi r3,r21,65535 - bdd0: a82ad43a srli r21,r21,16 - bdd4: 8c23883a add r17,r17,r16 - bdd8: 1011883a mov r8,r2 - bddc: ac6b883a add r21,r21,r17 - bde0: a804943a slli r2,r21,16 - bde4: b009883a mov r4,r22 - bde8: 980b883a mov r5,r19 - bdec: 10c7883a add r3,r2,r3 - bdf0: a812d43a srli r9,r21,16 - bdf4: 180d883a mov r6,r3 - bdf8: ac00022e bgeu r21,r16,be04 <__muldi3+0xc8> - bdfc: 00800074 movhi r2,1 - be00: 4091883a add r8,r8,r2 - be04: 4267883a add r19,r8,r9 - be08: 302d883a mov r22,r6 - be0c: 0002b2c0 call 2b2c <__mulsi3> - be10: d9400317 ldw r5,12(sp) - be14: d9000017 ldw r4,0(sp) - be18: 1023883a mov r17,r2 - be1c: 0002b2c0 call 2b2c <__mulsi3> - be20: 14cb883a add r5,r2,r19 - be24: 894b883a add r5,r17,r5 - be28: b005883a mov r2,r22 - be2c: 2807883a mov r3,r5 - be30: dfc00d17 ldw ra,52(sp) - be34: df000c17 ldw fp,48(sp) - be38: ddc00b17 ldw r23,44(sp) - be3c: dd800a17 ldw r22,40(sp) - be40: dd400917 ldw r21,36(sp) - be44: dd000817 ldw r20,32(sp) - be48: dcc00717 ldw r19,28(sp) - be4c: dc800617 ldw r18,24(sp) - be50: dc400517 ldw r17,20(sp) - be54: dc000417 ldw r16,16(sp) - be58: dec00e04 addi sp,sp,56 - be5c: f800283a ret - -0000be60 <__clzsi2>: - be60: 00bfffd4 movui r2,65535 - be64: 11000e36 bltu r2,r4,bea0 <__clzsi2+0x40> - be68: 00803fc4 movi r2,255 - be6c: 01400204 movi r5,8 - be70: 0007883a mov r3,zero - be74: 11001036 bltu r2,r4,beb8 <__clzsi2+0x58> - be78: 000b883a mov r5,zero - be7c: 20c6d83a srl r3,r4,r3 - be80: 00800074 movhi r2,1 - be84: 10811f04 addi r2,r2,1148 - be88: 1887883a add r3,r3,r2 - be8c: 18800003 ldbu r2,0(r3) - be90: 00c00804 movi r3,32 - be94: 2885883a add r2,r5,r2 - be98: 1885c83a sub r2,r3,r2 - be9c: f800283a ret - bea0: 01400404 movi r5,16 - bea4: 00804034 movhi r2,256 - bea8: 10bfffc4 addi r2,r2,-1 - beac: 2807883a mov r3,r5 - beb0: 113ff22e bgeu r2,r4,be7c <__clzsi2+0x1c> - beb4: 01400604 movi r5,24 - beb8: 2807883a mov r3,r5 - bebc: 20c6d83a srl r3,r4,r3 - bec0: 00800074 movhi r2,1 - bec4: 10811f04 addi r2,r2,1148 - bec8: 1887883a add r3,r3,r2 - becc: 18800003 ldbu r2,0(r3) - bed0: 00c00804 movi r3,32 - bed4: 2885883a add r2,r5,r2 - bed8: 1885c83a sub r2,r3,r2 - bedc: f800283a ret - -0000bee0 <__pack_d>: - bee0: 20c00017 ldw r3,0(r4) - bee4: defffd04 addi sp,sp,-12 - bee8: dc000015 stw r16,0(sp) - beec: dc800215 stw r18,8(sp) - bef0: dc400115 stw r17,4(sp) - bef4: 00800044 movi r2,1 - bef8: 22000317 ldw r8,12(r4) - befc: 001f883a mov r15,zero - bf00: 22400417 ldw r9,16(r4) - bf04: 24000117 ldw r16,4(r4) - bf08: 10c0552e bgeu r2,r3,c060 <__pack_d+0x180> - bf0c: 00800104 movi r2,4 - bf10: 18804f26 beq r3,r2,c050 <__pack_d+0x170> - bf14: 00800084 movi r2,2 - bf18: 18800226 beq r3,r2,bf24 <__pack_d+0x44> - bf1c: 4244b03a or r2,r8,r9 - bf20: 10001a1e bne r2,zero,bf8c <__pack_d+0xac> - bf24: 000d883a mov r6,zero - bf28: 000f883a mov r7,zero - bf2c: 0011883a mov r8,zero - bf30: 00800434 movhi r2,16 - bf34: 10bfffc4 addi r2,r2,-1 - bf38: 301d883a mov r14,r6 - bf3c: 3884703a and r2,r7,r2 - bf40: 400a953a slli r5,r8,20 - bf44: 79bffc2c andhi r6,r15,65520 - bf48: 308cb03a or r6,r6,r2 - bf4c: 00e00434 movhi r3,32784 - bf50: 18ffffc4 addi r3,r3,-1 - bf54: 800497fa slli r2,r16,31 - bf58: 30c6703a and r3,r6,r3 - bf5c: 1946b03a or r3,r3,r5 - bf60: 01600034 movhi r5,32768 - bf64: 297fffc4 addi r5,r5,-1 - bf68: 194a703a and r5,r3,r5 - bf6c: 288ab03a or r5,r5,r2 - bf70: 2807883a mov r3,r5 - bf74: 7005883a mov r2,r14 - bf78: dc800217 ldw r18,8(sp) - bf7c: dc400117 ldw r17,4(sp) - bf80: dc000017 ldw r16,0(sp) - bf84: dec00304 addi sp,sp,12 - bf88: f800283a ret - bf8c: 21000217 ldw r4,8(r4) - bf90: 00bf0084 movi r2,-1022 - bf94: 20803f16 blt r4,r2,c094 <__pack_d+0x1b4> - bf98: 0080ffc4 movi r2,1023 - bf9c: 11002c16 blt r2,r4,c050 <__pack_d+0x170> - bfa0: 00803fc4 movi r2,255 - bfa4: 408c703a and r6,r8,r2 - bfa8: 00802004 movi r2,128 - bfac: 0007883a mov r3,zero - bfb0: 000f883a mov r7,zero - bfb4: 2280ffc4 addi r10,r4,1023 - bfb8: 30801e26 beq r6,r2,c034 <__pack_d+0x154> - bfbc: 00801fc4 movi r2,127 - bfc0: 4089883a add r4,r8,r2 - bfc4: 220d803a cmpltu r6,r4,r8 - bfc8: 324d883a add r6,r6,r9 - bfcc: 2011883a mov r8,r4 - bfd0: 3013883a mov r9,r6 - bfd4: 00880034 movhi r2,8192 - bfd8: 10bfffc4 addi r2,r2,-1 - bfdc: 12400d36 bltu r2,r9,c014 <__pack_d+0x134> - bfe0: 4804963a slli r2,r9,24 - bfe4: 400cd23a srli r6,r8,8 - bfe8: 480ed23a srli r7,r9,8 - bfec: 013fffc4 movi r4,-1 - bff0: 118cb03a or r6,r2,r6 - bff4: 01400434 movhi r5,16 - bff8: 297fffc4 addi r5,r5,-1 - bffc: 3104703a and r2,r6,r4 - c000: 3946703a and r3,r7,r5 - c004: 5201ffcc andi r8,r10,2047 - c008: 100d883a mov r6,r2 - c00c: 180f883a mov r7,r3 - c010: 003fc706 br bf30 <__pack_d+0x50> - c014: 480897fa slli r4,r9,31 - c018: 4004d07a srli r2,r8,1 - c01c: 4806d07a srli r3,r9,1 - c020: 52800044 addi r10,r10,1 - c024: 2084b03a or r2,r4,r2 - c028: 1011883a mov r8,r2 - c02c: 1813883a mov r9,r3 - c030: 003feb06 br bfe0 <__pack_d+0x100> - c034: 383fe11e bne r7,zero,bfbc <__pack_d+0xdc> - c038: 01004004 movi r4,256 - c03c: 4104703a and r2,r8,r4 - c040: 10c4b03a or r2,r2,r3 - c044: 103fe326 beq r2,zero,bfd4 <__pack_d+0xf4> - c048: 3005883a mov r2,r6 - c04c: 003fdc06 br bfc0 <__pack_d+0xe0> - c050: 000d883a mov r6,zero - c054: 000f883a mov r7,zero - c058: 0201ffc4 movi r8,2047 - c05c: 003fb406 br bf30 <__pack_d+0x50> - c060: 0005883a mov r2,zero - c064: 00c00234 movhi r3,8 - c068: 408cb03a or r6,r8,r2 - c06c: 48ceb03a or r7,r9,r3 - c070: 013fffc4 movi r4,-1 - c074: 01400434 movhi r5,16 - c078: 297fffc4 addi r5,r5,-1 - c07c: 3104703a and r2,r6,r4 - c080: 3946703a and r3,r7,r5 - c084: 100d883a mov r6,r2 - c088: 180f883a mov r7,r3 - c08c: 0201ffc4 movi r8,2047 - c090: 003fa706 br bf30 <__pack_d+0x50> - c094: 1109c83a sub r4,r2,r4 - c098: 00800e04 movi r2,56 - c09c: 11004316 blt r2,r4,c1ac <__pack_d+0x2cc> - c0a0: 21fff804 addi r7,r4,-32 - c0a4: 38004516 blt r7,zero,c1bc <__pack_d+0x2dc> - c0a8: 49d8d83a srl r12,r9,r7 - c0ac: 001b883a mov r13,zero - c0b0: 0023883a mov r17,zero - c0b4: 01400044 movi r5,1 - c0b8: 0025883a mov r18,zero - c0bc: 38004716 blt r7,zero,c1dc <__pack_d+0x2fc> - c0c0: 29d6983a sll r11,r5,r7 - c0c4: 0015883a mov r10,zero - c0c8: 00bfffc4 movi r2,-1 - c0cc: 5089883a add r4,r10,r2 - c0d0: 588b883a add r5,r11,r2 - c0d4: 228d803a cmpltu r6,r4,r10 - c0d8: 314b883a add r5,r6,r5 - c0dc: 4104703a and r2,r8,r4 - c0e0: 4946703a and r3,r9,r5 - c0e4: 10c4b03a or r2,r2,r3 - c0e8: 10000226 beq r2,zero,c0f4 <__pack_d+0x214> - c0ec: 04400044 movi r17,1 - c0f0: 0025883a mov r18,zero - c0f4: 00803fc4 movi r2,255 - c0f8: 644eb03a or r7,r12,r17 - c0fc: 3892703a and r9,r7,r2 - c100: 00802004 movi r2,128 - c104: 6c90b03a or r8,r13,r18 - c108: 0015883a mov r10,zero - c10c: 48801626 beq r9,r2,c168 <__pack_d+0x288> - c110: 01001fc4 movi r4,127 - c114: 3905883a add r2,r7,r4 - c118: 11cd803a cmpltu r6,r2,r7 - c11c: 320d883a add r6,r6,r8 - c120: 100f883a mov r7,r2 - c124: 00840034 movhi r2,4096 - c128: 10bfffc4 addi r2,r2,-1 - c12c: 3011883a mov r8,r6 - c130: 0007883a mov r3,zero - c134: 11801b36 bltu r2,r6,c1a4 <__pack_d+0x2c4> - c138: 4004963a slli r2,r8,24 - c13c: 3808d23a srli r4,r7,8 - c140: 400ad23a srli r5,r8,8 - c144: 1813883a mov r9,r3 - c148: 1108b03a or r4,r2,r4 - c14c: 00bfffc4 movi r2,-1 - c150: 00c00434 movhi r3,16 - c154: 18ffffc4 addi r3,r3,-1 - c158: 208c703a and r6,r4,r2 - c15c: 28ce703a and r7,r5,r3 - c160: 4a01ffcc andi r8,r9,2047 - c164: 003f7206 br bf30 <__pack_d+0x50> - c168: 503fe91e bne r10,zero,c110 <__pack_d+0x230> - c16c: 01004004 movi r4,256 - c170: 3904703a and r2,r7,r4 - c174: 0007883a mov r3,zero - c178: 10c4b03a or r2,r2,r3 - c17c: 10000626 beq r2,zero,c198 <__pack_d+0x2b8> - c180: 3a45883a add r2,r7,r9 - c184: 11cd803a cmpltu r6,r2,r7 - c188: 320d883a add r6,r6,r8 - c18c: 100f883a mov r7,r2 - c190: 3011883a mov r8,r6 - c194: 0007883a mov r3,zero - c198: 00840034 movhi r2,4096 - c19c: 10bfffc4 addi r2,r2,-1 - c1a0: 123fe52e bgeu r2,r8,c138 <__pack_d+0x258> - c1a4: 00c00044 movi r3,1 - c1a8: 003fe306 br c138 <__pack_d+0x258> - c1ac: 0009883a mov r4,zero - c1b0: 0013883a mov r9,zero - c1b4: 000b883a mov r5,zero - c1b8: 003fe406 br c14c <__pack_d+0x26c> - c1bc: 4a47883a add r3,r9,r9 - c1c0: 008007c4 movi r2,31 - c1c4: 1105c83a sub r2,r2,r4 - c1c8: 1886983a sll r3,r3,r2 - c1cc: 4118d83a srl r12,r8,r4 - c1d0: 491ad83a srl r13,r9,r4 - c1d4: 1b18b03a or r12,r3,r12 - c1d8: 003fb506 br c0b0 <__pack_d+0x1d0> - c1dc: 2806d07a srli r3,r5,1 - c1e0: 008007c4 movi r2,31 - c1e4: 1105c83a sub r2,r2,r4 - c1e8: 1896d83a srl r11,r3,r2 - c1ec: 2914983a sll r10,r5,r4 - c1f0: 003fb506 br c0c8 <__pack_d+0x1e8> - -0000c1f4 <__unpack_d>: - c1f4: 20c00117 ldw r3,4(r4) - c1f8: 22400017 ldw r9,0(r4) - c1fc: 00800434 movhi r2,16 - c200: 10bfffc4 addi r2,r2,-1 - c204: 1808d53a srli r4,r3,20 - c208: 180cd7fa srli r6,r3,31 - c20c: 1894703a and r10,r3,r2 - c210: 2201ffcc andi r8,r4,2047 - c214: 281b883a mov r13,r5 - c218: 4817883a mov r11,r9 - c21c: 29800115 stw r6,4(r5) - c220: 5019883a mov r12,r10 - c224: 40001e1e bne r8,zero,c2a0 <__unpack_d+0xac> - c228: 4a84b03a or r2,r9,r10 - c22c: 10001926 beq r2,zero,c294 <__unpack_d+0xa0> - c230: 4804d63a srli r2,r9,24 - c234: 500c923a slli r6,r10,8 - c238: 013f0084 movi r4,-1022 - c23c: 00c40034 movhi r3,4096 - c240: 18ffffc4 addi r3,r3,-1 - c244: 118cb03a or r6,r2,r6 - c248: 008000c4 movi r2,3 - c24c: 480a923a slli r5,r9,8 - c250: 68800015 stw r2,0(r13) - c254: 69000215 stw r4,8(r13) - c258: 19800b36 bltu r3,r6,c288 <__unpack_d+0x94> - c25c: 200f883a mov r7,r4 - c260: 1811883a mov r8,r3 - c264: 2945883a add r2,r5,r5 - c268: 1149803a cmpltu r4,r2,r5 - c26c: 3187883a add r3,r6,r6 - c270: 20c9883a add r4,r4,r3 - c274: 100b883a mov r5,r2 - c278: 200d883a mov r6,r4 - c27c: 39ffffc4 addi r7,r7,-1 - c280: 413ff82e bgeu r8,r4,c264 <__unpack_d+0x70> - c284: 69c00215 stw r7,8(r13) - c288: 69800415 stw r6,16(r13) - c28c: 69400315 stw r5,12(r13) - c290: f800283a ret - c294: 00800084 movi r2,2 - c298: 28800015 stw r2,0(r5) - c29c: f800283a ret - c2a0: 0081ffc4 movi r2,2047 - c2a4: 40800f26 beq r8,r2,c2e4 <__unpack_d+0xf0> - c2a8: 480cd63a srli r6,r9,24 - c2ac: 5006923a slli r3,r10,8 - c2b0: 4804923a slli r2,r9,8 - c2b4: 0009883a mov r4,zero - c2b8: 30c6b03a or r3,r6,r3 - c2bc: 01440034 movhi r5,4096 - c2c0: 110cb03a or r6,r2,r4 - c2c4: 423f0044 addi r8,r8,-1023 - c2c8: 194eb03a or r7,r3,r5 - c2cc: 008000c4 movi r2,3 - c2d0: 69c00415 stw r7,16(r13) - c2d4: 6a000215 stw r8,8(r13) - c2d8: 68800015 stw r2,0(r13) - c2dc: 69800315 stw r6,12(r13) - c2e0: f800283a ret - c2e4: 4a84b03a or r2,r9,r10 - c2e8: 1000031e bne r2,zero,c2f8 <__unpack_d+0x104> - c2ec: 00800104 movi r2,4 - c2f0: 28800015 stw r2,0(r5) - c2f4: f800283a ret - c2f8: 0009883a mov r4,zero - c2fc: 01400234 movhi r5,8 - c300: 4904703a and r2,r9,r4 - c304: 5146703a and r3,r10,r5 - c308: 10c4b03a or r2,r2,r3 - c30c: 10000526 beq r2,zero,c324 <__unpack_d+0x130> - c310: 00800044 movi r2,1 - c314: 68800015 stw r2,0(r13) - c318: 6b000415 stw r12,16(r13) - c31c: 6ac00315 stw r11,12(r13) - c320: f800283a ret - c324: 68000015 stw zero,0(r13) - c328: 003ffb06 br c318 <__unpack_d+0x124> - -0000c32c <__fpcmp_parts_d>: - c32c: 21800017 ldw r6,0(r4) - c330: 00c00044 movi r3,1 - c334: 19800a2e bgeu r3,r6,c360 <__fpcmp_parts_d+0x34> - c338: 28800017 ldw r2,0(r5) - c33c: 1880082e bgeu r3,r2,c360 <__fpcmp_parts_d+0x34> - c340: 00c00104 movi r3,4 - c344: 30c02626 beq r6,r3,c3e0 <__fpcmp_parts_d+0xb4> - c348: 10c02226 beq r2,r3,c3d4 <__fpcmp_parts_d+0xa8> - c34c: 00c00084 movi r3,2 - c350: 30c00526 beq r6,r3,c368 <__fpcmp_parts_d+0x3c> - c354: 10c0071e bne r2,r3,c374 <__fpcmp_parts_d+0x48> - c358: 20800117 ldw r2,4(r4) - c35c: 1000091e bne r2,zero,c384 <__fpcmp_parts_d+0x58> - c360: 00800044 movi r2,1 - c364: f800283a ret - c368: 10c01a1e bne r2,r3,c3d4 <__fpcmp_parts_d+0xa8> - c36c: 0005883a mov r2,zero - c370: f800283a ret - c374: 22000117 ldw r8,4(r4) - c378: 28800117 ldw r2,4(r5) - c37c: 40800326 beq r8,r2,c38c <__fpcmp_parts_d+0x60> - c380: 403ff726 beq r8,zero,c360 <__fpcmp_parts_d+0x34> - c384: 00bfffc4 movi r2,-1 - c388: f800283a ret - c38c: 20c00217 ldw r3,8(r4) - c390: 28800217 ldw r2,8(r5) - c394: 10fffa16 blt r2,r3,c380 <__fpcmp_parts_d+0x54> - c398: 18800916 blt r3,r2,c3c0 <__fpcmp_parts_d+0x94> - c39c: 21c00417 ldw r7,16(r4) - c3a0: 28c00417 ldw r3,16(r5) - c3a4: 21800317 ldw r6,12(r4) - c3a8: 28800317 ldw r2,12(r5) - c3ac: 19fff436 bltu r3,r7,c380 <__fpcmp_parts_d+0x54> - c3b0: 38c00526 beq r7,r3,c3c8 <__fpcmp_parts_d+0x9c> - c3b4: 38c00236 bltu r7,r3,c3c0 <__fpcmp_parts_d+0x94> - c3b8: 19ffec1e bne r3,r7,c36c <__fpcmp_parts_d+0x40> - c3bc: 30bfeb2e bgeu r6,r2,c36c <__fpcmp_parts_d+0x40> - c3c0: 403fe71e bne r8,zero,c360 <__fpcmp_parts_d+0x34> - c3c4: 003fef06 br c384 <__fpcmp_parts_d+0x58> - c3c8: 11bffa2e bgeu r2,r6,c3b4 <__fpcmp_parts_d+0x88> - c3cc: 403fe426 beq r8,zero,c360 <__fpcmp_parts_d+0x34> - c3d0: 003fec06 br c384 <__fpcmp_parts_d+0x58> - c3d4: 28800117 ldw r2,4(r5) - c3d8: 103fe11e bne r2,zero,c360 <__fpcmp_parts_d+0x34> - c3dc: 003fe906 br c384 <__fpcmp_parts_d+0x58> - c3e0: 11bfdd1e bne r2,r6,c358 <__fpcmp_parts_d+0x2c> - c3e4: 28c00117 ldw r3,4(r5) - c3e8: 20800117 ldw r2,4(r4) - c3ec: 1885c83a sub r2,r3,r2 - c3f0: f800283a ret - -0000c3f4 : - * - * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h - */ - -int ALT_CLOSE (int fildes) -{ - c3f4: defff804 addi sp,sp,-32 - c3f8: dfc00715 stw ra,28(sp) - c3fc: df000615 stw fp,24(sp) - c400: df000604 addi fp,sp,24 - c404: e13ffc15 stw r4,-16(fp) - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; - c408: e0bffc17 ldw r2,-16(fp) - c40c: 1004803a cmplt r2,r2,zero - c410: 1000091e bne r2,zero,c438 - c414: e13ffc17 ldw r4,-16(fp) - c418: 01400304 movi r5,12 - c41c: 0002b2c0 call 2b2c <__mulsi3> - c420: 1007883a mov r3,r2 - c424: 00800074 movhi r2,1 - c428: 10837e04 addi r2,r2,3576 - c42c: 1887883a add r3,r3,r2 - c430: e0ffff15 stw r3,-4(fp) - c434: 00000106 br c43c - c438: e03fff15 stw zero,-4(fp) - c43c: e0bfff17 ldw r2,-4(fp) - c440: e0bffb15 stw r2,-20(fp) - - if (fd) - c444: e0bffb17 ldw r2,-20(fp) - c448: 1005003a cmpeq r2,r2,zero - c44c: 10001d1e bne r2,zero,c4c4 - /* - * If the associated file system/device has a close function, call it so - * that any necessary cleanup code can run. - */ - - rval = (fd->dev->close) ? fd->dev->close(fd) : 0; - c450: e0bffb17 ldw r2,-20(fp) - c454: 10800017 ldw r2,0(r2) - c458: 10800417 ldw r2,16(r2) - c45c: 1005003a cmpeq r2,r2,zero - c460: 1000071e bne r2,zero,c480 - c464: e0bffb17 ldw r2,-20(fp) - c468: 10800017 ldw r2,0(r2) - c46c: 10800417 ldw r2,16(r2) - c470: e13ffb17 ldw r4,-20(fp) - c474: 103ee83a callr r2 - c478: e0bffe15 stw r2,-8(fp) - c47c: 00000106 br c484 - c480: e03ffe15 stw zero,-8(fp) - c484: e0bffe17 ldw r2,-8(fp) - c488: e0bffa15 stw r2,-24(fp) - - /* Free the file descriptor structure and return. */ - - alt_release_fd (fildes); - c48c: e13ffc17 ldw r4,-16(fp) - c490: 000cc4c0 call cc4c - if (rval < 0) - c494: e0bffa17 ldw r2,-24(fp) - c498: 1004403a cmpge r2,r2,zero - c49c: 1000071e bne r2,zero,c4bc - { - ALT_ERRNO = -rval; - c4a0: 000c4f40 call c4f4 - c4a4: e0fffa17 ldw r3,-24(fp) - c4a8: 00c7c83a sub r3,zero,r3 - c4ac: 10c00015 stw r3,0(r2) - return -1; - c4b0: 00bfffc4 movi r2,-1 - c4b4: e0bffd15 stw r2,-12(fp) - c4b8: 00000806 br c4dc - } - return 0; - c4bc: e03ffd15 stw zero,-12(fp) - c4c0: 00000606 br c4dc - } - else - { - ALT_ERRNO = EBADFD; - c4c4: 000c4f40 call c4f4 - c4c8: 1007883a mov r3,r2 - c4cc: 00801444 movi r2,81 - c4d0: 18800015 stw r2,0(r3) - return -1; - c4d4: 00bfffc4 movi r2,-1 - c4d8: e0bffd15 stw r2,-12(fp) - c4dc: e0bffd17 ldw r2,-12(fp) - } -} - c4e0: e037883a mov sp,fp - c4e4: dfc00117 ldw ra,4(sp) - c4e8: df000017 ldw fp,0(sp) - c4ec: dec00204 addi sp,sp,8 - c4f0: f800283a ret - -0000c4f4 : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - c4f4: defffd04 addi sp,sp,-12 - c4f8: dfc00215 stw ra,8(sp) - c4fc: df000115 stw fp,4(sp) - c500: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - c504: 00800074 movhi r2,1 - c508: 10884b04 addi r2,r2,8492 - c50c: 10800017 ldw r2,0(r2) - c510: 1005003a cmpeq r2,r2,zero - c514: 1000061e bne r2,zero,c530 - c518: 00800074 movhi r2,1 - c51c: 10884b04 addi r2,r2,8492 - c520: 10800017 ldw r2,0(r2) - c524: 103ee83a callr r2 - c528: e0bfff15 stw r2,-4(fp) - c52c: 00000306 br c53c - c530: 00800074 movhi r2,1 - c534: 108f3e04 addi r2,r2,15608 - c538: e0bfff15 stw r2,-4(fp) - c53c: e0bfff17 ldw r2,-4(fp) -} - c540: e037883a mov sp,fp - c544: dfc00117 ldw ra,4(sp) - c548: df000017 ldw fp,0(sp) - c54c: dec00204 addi sp,sp,8 - c550: f800283a ret - -0000c554 : - * by the alt_dev_null device. It simple discards all data passed to it, and - * indicates that the data has been successfully transmitted. - */ - -static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) -{ - c554: defffc04 addi sp,sp,-16 - c558: df000315 stw fp,12(sp) - c55c: df000304 addi fp,sp,12 - c560: e13ffd15 stw r4,-12(fp) - c564: e17ffe15 stw r5,-8(fp) - c568: e1bfff15 stw r6,-4(fp) - return len; - c56c: e0bfff17 ldw r2,-4(fp) -} - c570: e037883a mov sp,fp - c574: df000017 ldw fp,0(sp) - c578: dec00104 addi sp,sp,4 - c57c: f800283a ret - -0000c580 : -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -int ALT_FSTAT (int file, struct stat *st) -{ - c580: defff904 addi sp,sp,-28 - c584: dfc00615 stw ra,24(sp) - c588: df000515 stw fp,20(sp) - c58c: df000504 addi fp,sp,20 - c590: e13ffc15 stw r4,-16(fp) - c594: e17ffd15 stw r5,-12(fp) - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - c598: e0bffc17 ldw r2,-16(fp) - c59c: 1004803a cmplt r2,r2,zero - c5a0: 1000091e bne r2,zero,c5c8 - c5a4: e13ffc17 ldw r4,-16(fp) - c5a8: 01400304 movi r5,12 - c5ac: 0002b2c0 call 2b2c <__mulsi3> - c5b0: 1007883a mov r3,r2 - c5b4: 00800074 movhi r2,1 - c5b8: 10837e04 addi r2,r2,3576 - c5bc: 1887883a add r3,r3,r2 - c5c0: e0ffff15 stw r3,-4(fp) - c5c4: 00000106 br c5cc - c5c8: e03fff15 stw zero,-4(fp) - c5cc: e0bfff17 ldw r2,-4(fp) - c5d0: e0bffb15 stw r2,-20(fp) - - if (fd) - c5d4: e0bffb17 ldw r2,-20(fp) - c5d8: 1005003a cmpeq r2,r2,zero - c5dc: 1000121e bne r2,zero,c628 - { - /* Call the drivers fstat() function to fill out the "st" structure. */ - - if (fd->dev->fstat) - c5e0: e0bffb17 ldw r2,-20(fp) - c5e4: 10800017 ldw r2,0(r2) - c5e8: 10800817 ldw r2,32(r2) - c5ec: 1005003a cmpeq r2,r2,zero - c5f0: 1000081e bne r2,zero,c614 - { - return fd->dev->fstat(fd, st); - c5f4: e0bffb17 ldw r2,-20(fp) - c5f8: 10800017 ldw r2,0(r2) - c5fc: 10800817 ldw r2,32(r2) - c600: e13ffb17 ldw r4,-20(fp) - c604: e17ffd17 ldw r5,-12(fp) - c608: 103ee83a callr r2 - c60c: e0bffe15 stw r2,-8(fp) - c610: 00000b06 br c640 - * device. - */ - - else - { - st->st_mode = _IFCHR; - c614: e0fffd17 ldw r3,-12(fp) - c618: 00880004 movi r2,8192 - c61c: 18800115 stw r2,4(r3) - return 0; - c620: e03ffe15 stw zero,-8(fp) - c624: 00000606 br c640 - } - } - else - { - ALT_ERRNO = EBADFD; - c628: 000c6580 call c658 - c62c: 1007883a mov r3,r2 - c630: 00801444 movi r2,81 - c634: 18800015 stw r2,0(r3) - return -1; - c638: 00bfffc4 movi r2,-1 - c63c: e0bffe15 stw r2,-8(fp) - c640: e0bffe17 ldw r2,-8(fp) - } -} - c644: e037883a mov sp,fp - c648: dfc00117 ldw ra,4(sp) - c64c: df000017 ldw fp,0(sp) - c650: dec00204 addi sp,sp,8 - c654: f800283a ret - -0000c658 : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - c658: defffd04 addi sp,sp,-12 - c65c: dfc00215 stw ra,8(sp) - c660: df000115 stw fp,4(sp) - c664: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - c668: 00800074 movhi r2,1 - c66c: 10884b04 addi r2,r2,8492 - c670: 10800017 ldw r2,0(r2) - c674: 1005003a cmpeq r2,r2,zero - c678: 1000061e bne r2,zero,c694 - c67c: 00800074 movhi r2,1 - c680: 10884b04 addi r2,r2,8492 - c684: 10800017 ldw r2,0(r2) - c688: 103ee83a callr r2 - c68c: e0bfff15 stw r2,-4(fp) - c690: 00000306 br c6a0 - c694: 00800074 movhi r2,1 - c698: 108f3e04 addi r2,r2,15608 - c69c: e0bfff15 stw r2,-4(fp) - c6a0: e0bfff17 ldw r2,-4(fp) -} - c6a4: e037883a mov sp,fp - c6a8: dfc00117 ldw ra,4(sp) - c6ac: df000017 ldw fp,0(sp) - c6b0: dec00204 addi sp,sp,8 - c6b4: f800283a ret - -0000c6b8 : - * - * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h - */ - -int ALT_ISATTY (int file) -{ - c6b8: deffeb04 addi sp,sp,-84 - c6bc: dfc01415 stw ra,80(sp) - c6c0: df001315 stw fp,76(sp) - c6c4: df001304 addi fp,sp,76 - c6c8: e13ffd15 stw r4,-12(fp) - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - c6cc: e0bffd17 ldw r2,-12(fp) - c6d0: 1004803a cmplt r2,r2,zero - c6d4: 1000091e bne r2,zero,c6fc - c6d8: e13ffd17 ldw r4,-12(fp) - c6dc: 01400304 movi r5,12 - c6e0: 0002b2c0 call 2b2c <__mulsi3> - c6e4: 1007883a mov r3,r2 - c6e8: 00800074 movhi r2,1 - c6ec: 10837e04 addi r2,r2,3576 - c6f0: 1887883a add r3,r3,r2 - c6f4: e0ffff15 stw r3,-4(fp) - c6f8: 00000106 br c700 - c6fc: e03fff15 stw zero,-4(fp) - c700: e0bfff17 ldw r2,-4(fp) - c704: e0bfed15 stw r2,-76(fp) - - if (fd) - c708: e0bfed17 ldw r2,-76(fp) - c70c: 1005003a cmpeq r2,r2,zero - c710: 10000f1e bne r2,zero,c750 - /* - * If a device driver does not provide an fstat() function, then it is - * treated as a terminal device by default. - */ - - if (!fd->dev->fstat) - c714: e0bfed17 ldw r2,-76(fp) - c718: 10800017 ldw r2,0(r2) - c71c: 10800817 ldw r2,32(r2) - c720: 1004c03a cmpne r2,r2,zero - c724: 1000031e bne r2,zero,c734 - { - return 1; - c728: 00800044 movi r2,1 - c72c: e0bffe15 stw r2,-8(fp) - c730: 00000c06 br c764 - * this is called so that the device can identify itself. - */ - - else - { - fstat (file, &stat); - c734: e17fee04 addi r5,fp,-72 - c738: e13ffd17 ldw r4,-12(fp) - c73c: 000c5800 call c580 - return (stat.st_mode == _IFCHR) ? 1 : 0; - c740: e0bfef17 ldw r2,-68(fp) - c744: 10880020 cmpeqi r2,r2,8192 - c748: e0bffe15 stw r2,-8(fp) - c74c: 00000506 br c764 - } - } - else - { - ALT_ERRNO = EBADFD; - c750: 000c77c0 call c77c - c754: 1007883a mov r3,r2 - c758: 00801444 movi r2,81 - c75c: 18800015 stw r2,0(r3) - return 0; - c760: e03ffe15 stw zero,-8(fp) - c764: e0bffe17 ldw r2,-8(fp) - } -} - c768: e037883a mov sp,fp - c76c: dfc00117 ldw ra,4(sp) - c770: df000017 ldw fp,0(sp) - c774: dec00204 addi sp,sp,8 - c778: f800283a ret - -0000c77c : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - c77c: defffd04 addi sp,sp,-12 - c780: dfc00215 stw ra,8(sp) - c784: df000115 stw fp,4(sp) - c788: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - c78c: 00800074 movhi r2,1 - c790: 10884b04 addi r2,r2,8492 - c794: 10800017 ldw r2,0(r2) - c798: 1005003a cmpeq r2,r2,zero - c79c: 1000061e bne r2,zero,c7b8 - c7a0: 00800074 movhi r2,1 - c7a4: 10884b04 addi r2,r2,8492 - c7a8: 10800017 ldw r2,0(r2) - c7ac: 103ee83a callr r2 - c7b0: e0bfff15 stw r2,-4(fp) - c7b4: 00000306 br c7c4 - c7b8: 00800074 movhi r2,1 - c7bc: 108f3e04 addi r2,r2,15608 - c7c0: e0bfff15 stw r2,-4(fp) - c7c4: e0bfff17 ldw r2,-4(fp) -} - c7c8: e037883a mov sp,fp - c7cc: dfc00117 ldw ra,4(sp) - c7d0: df000017 ldw fp,0(sp) - c7d4: dec00204 addi sp,sp,8 - c7d8: f800283a ret - -0000c7dc : - * there is no bootloader, so this application is responsible for loading to - * RAM any sections that are required. - */ - -void alt_load (void) -{ - c7dc: defffe04 addi sp,sp,-8 - c7e0: dfc00115 stw ra,4(sp) - c7e4: df000015 stw fp,0(sp) - c7e8: d839883a mov fp,sp - /* - * Copy the .rwdata section. - */ - - alt_load_section (&__flash_rwdata_start, - c7ec: 01000074 movhi r4,1 - c7f0: 21085104 addi r4,r4,8516 - c7f4: 01400074 movhi r5,1 - c7f8: 29416f04 addi r5,r5,1468 - c7fc: 01800074 movhi r6,1 - c800: 31885104 addi r6,r6,8516 - c804: 000c85c0 call c85c - - /* - * Copy the exception handler. - */ - - alt_load_section (&__flash_exceptions_start, - c808: 01000034 movhi r4,0 - c80c: 21000804 addi r4,r4,32 - c810: 01400034 movhi r5,0 - c814: 29400804 addi r5,r5,32 - c818: 01800034 movhi r6,0 - c81c: 31806d04 addi r6,r6,436 - c820: 000c85c0 call c85c - - /* - * Copy the .rodata section. - */ - - alt_load_section (&__flash_rodata_start, - c824: 01000074 movhi r4,1 - c828: 213fa604 addi r4,r4,-360 - c82c: 01400074 movhi r5,1 - c830: 297fa604 addi r5,r5,-360 - c834: 01800074 movhi r6,1 - c838: 31816f04 addi r6,r6,1468 - c83c: 000c85c0 call c85c - - /* - * Now ensure that the caches are in synch. - */ - - alt_dcache_flush_all(); - c840: 000ed300 call ed30 - alt_icache_flush_all(); - c844: 000ef280 call ef28 -} - c848: e037883a mov sp,fp - c84c: dfc00117 ldw ra,4(sp) - c850: df000017 ldw fp,0(sp) - c854: dec00204 addi sp,sp,8 - c858: f800283a ret - -0000c85c : - */ - -static void ALT_INLINE alt_load_section (alt_u32* from, - alt_u32* to, - alt_u32* end) -{ - c85c: defffc04 addi sp,sp,-16 - c860: df000315 stw fp,12(sp) - c864: df000304 addi fp,sp,12 - c868: e13ffd15 stw r4,-12(fp) - c86c: e17ffe15 stw r5,-8(fp) - c870: e1bfff15 stw r6,-4(fp) - if (to != from) - c874: e0fffe17 ldw r3,-8(fp) - c878: e0bffd17 ldw r2,-12(fp) - c87c: 18800e26 beq r3,r2,c8b8 - { - while( to != end ) - c880: 00000a06 br c8ac - { - *to++ = *from++; - c884: e0bffd17 ldw r2,-12(fp) - c888: 10c00017 ldw r3,0(r2) - c88c: e0bffe17 ldw r2,-8(fp) - c890: 10c00015 stw r3,0(r2) - c894: e0bffe17 ldw r2,-8(fp) - c898: 10800104 addi r2,r2,4 - c89c: e0bffe15 stw r2,-8(fp) - c8a0: e0bffd17 ldw r2,-12(fp) - c8a4: 10800104 addi r2,r2,4 - c8a8: e0bffd15 stw r2,-12(fp) - alt_u32* to, - alt_u32* end) -{ - if (to != from) - { - while( to != end ) - c8ac: e0fffe17 ldw r3,-8(fp) - c8b0: e0bfff17 ldw r2,-4(fp) - c8b4: 18bff31e bne r3,r2,c884 - { - *to++ = *from++; - } - } -} - c8b8: e037883a mov sp,fp - c8bc: df000017 ldw fp,0(sp) - c8c0: dec00104 addi sp,sp,4 - c8c4: f800283a ret - -0000c8c8 : - * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h - * - */ - -off_t ALT_LSEEK (int file, off_t ptr, int dir) -{ - c8c8: defff804 addi sp,sp,-32 - c8cc: dfc00715 stw ra,28(sp) - c8d0: df000615 stw fp,24(sp) - c8d4: df000604 addi fp,sp,24 - c8d8: e13ffc15 stw r4,-16(fp) - c8dc: e17ffd15 stw r5,-12(fp) - c8e0: e1bffe15 stw r6,-8(fp) - alt_fd* fd; - off_t rc = 0; - c8e4: e03ffa15 stw zero,-24(fp) - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - c8e8: e0bffc17 ldw r2,-16(fp) - c8ec: 1004803a cmplt r2,r2,zero - c8f0: 1000091e bne r2,zero,c918 - c8f4: e13ffc17 ldw r4,-16(fp) - c8f8: 01400304 movi r5,12 - c8fc: 0002b2c0 call 2b2c <__mulsi3> - c900: 1007883a mov r3,r2 - c904: 00800074 movhi r2,1 - c908: 10837e04 addi r2,r2,3576 - c90c: 1887883a add r3,r3,r2 - c910: e0ffff15 stw r3,-4(fp) - c914: 00000106 br c91c - c918: e03fff15 stw zero,-4(fp) - c91c: e0bfff17 ldw r2,-4(fp) - c920: e0bffb15 stw r2,-20(fp) - - if (fd) - c924: e0bffb17 ldw r2,-20(fp) - c928: 1005003a cmpeq r2,r2,zero - c92c: 1000111e bne r2,zero,c974 - /* - * If the device driver provides an implementation of the lseek() function, - * then call that to process the request. - */ - - if (fd->dev->lseek) - c930: e0bffb17 ldw r2,-20(fp) - c934: 10800017 ldw r2,0(r2) - c938: 10800717 ldw r2,28(r2) - c93c: 1005003a cmpeq r2,r2,zero - c940: 1000091e bne r2,zero,c968 - { - rc = fd->dev->lseek(fd, ptr, dir); - c944: e0bffb17 ldw r2,-20(fp) - c948: 10800017 ldw r2,0(r2) - c94c: 10800717 ldw r2,28(r2) - c950: e13ffb17 ldw r4,-20(fp) - c954: e17ffd17 ldw r5,-12(fp) - c958: e1bffe17 ldw r6,-8(fp) - c95c: 103ee83a callr r2 - c960: e0bffa15 stw r2,-24(fp) - c964: 00000506 br c97c - * Otherwise return an error. - */ - - else - { - rc = -ENOTSUP; - c968: 00bfde84 movi r2,-134 - c96c: e0bffa15 stw r2,-24(fp) - c970: 00000206 br c97c - } - } - else - { - rc = -EBADFD; - c974: 00bfebc4 movi r2,-81 - c978: e0bffa15 stw r2,-24(fp) - } - - if (rc < 0) - c97c: e0bffa17 ldw r2,-24(fp) - c980: 1004403a cmpge r2,r2,zero - c984: 1000071e bne r2,zero,c9a4 - { - ALT_ERRNO = -rc; - c988: 000c9bc0 call c9bc - c98c: 1007883a mov r3,r2 - c990: e0bffa17 ldw r2,-24(fp) - c994: 0085c83a sub r2,zero,r2 - c998: 18800015 stw r2,0(r3) - rc = -1; - c99c: 00bfffc4 movi r2,-1 - c9a0: e0bffa15 stw r2,-24(fp) - } - - return rc; - c9a4: e0bffa17 ldw r2,-24(fp) -} - c9a8: e037883a mov sp,fp - c9ac: dfc00117 ldw ra,4(sp) - c9b0: df000017 ldw fp,0(sp) - c9b4: dec00204 addi sp,sp,8 - c9b8: f800283a ret - -0000c9bc : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - c9bc: defffd04 addi sp,sp,-12 - c9c0: dfc00215 stw ra,8(sp) - c9c4: df000115 stw fp,4(sp) - c9c8: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - c9cc: 00800074 movhi r2,1 - c9d0: 10884b04 addi r2,r2,8492 - c9d4: 10800017 ldw r2,0(r2) - c9d8: 1005003a cmpeq r2,r2,zero - c9dc: 1000061e bne r2,zero,c9f8 - c9e0: 00800074 movhi r2,1 - c9e4: 10884b04 addi r2,r2,8492 - c9e8: 10800017 ldw r2,0(r2) - c9ec: 103ee83a callr r2 - c9f0: e0bfff15 stw r2,-4(fp) - c9f4: 00000306 br ca04 - c9f8: 00800074 movhi r2,1 - c9fc: 108f3e04 addi r2,r2,15608 - ca00: e0bfff15 stw r2,-4(fp) - ca04: e0bfff17 ldw r2,-4(fp) -} - ca08: e037883a mov sp,fp - ca0c: dfc00117 ldw ra,4(sp) - ca10: df000017 ldw fp,0(sp) - ca14: dec00204 addi sp,sp,8 - ca18: f800283a ret - -0000ca1c : - * devices/filesystems/components in the system; and call the entry point for - * the users application, i.e. main(). - */ - -void alt_main (void) -{ - ca1c: defffd04 addi sp,sp,-12 - ca20: dfc00215 stw ra,8(sp) - ca24: df000115 stw fp,4(sp) - ca28: df000104 addi fp,sp,4 -#endif - - /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ - ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); - /* Initialize the interrupt controller. */ - alt_irq_init (NULL); - ca2c: 0009883a mov r4,zero - ca30: 000cf340 call cf34 - ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); - ALT_SEM_CREATE (&alt_fd_list_lock, 1); - - /* Initialize the device drivers/software components. */ - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); - alt_sys_init(); - ca34: 000cf680 call cf68 - * devices be present (not equal to /dev/null) and if direct drivers - * aren't being used. - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); - alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); - ca38: 01000074 movhi r4,1 - ca3c: 21016204 addi r4,r4,1416 - ca40: 01400074 movhi r5,1 - ca44: 29416204 addi r5,r5,1416 - ca48: 01800074 movhi r6,1 - ca4c: 31816204 addi r6,r6,1416 - ca50: 000f2e80 call f2e8 - /* - * Call the C++ constructors - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); - _do_ctors (); - ca54: 000ee600 call ee60 <_do_ctors> - * redefined as _exit()). This is in the interest of reducing code footprint, - * in that the atexit() overhead is removed when it's not needed. - */ - - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); - atexit (_do_dtors); - ca58: 01000074 movhi r4,1 - ca5c: 213bb104 addi r4,r4,-4412 - ca60: 000fa8c0 call fa8c - ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); - -#ifdef ALT_NO_EXIT - main (alt_argc, alt_argv, alt_envp); -#else - result = main (alt_argc, alt_argv, alt_envp); - ca64: d1270117 ldw r4,-25596(gp) - ca68: d1670217 ldw r5,-25592(gp) - ca6c: d1a70317 ldw r6,-25588(gp) - ca70: 00009280 call 928
- ca74: e0bfff15 stw r2,-4(fp) - close(STDOUT_FILENO); - ca78: 01000044 movi r4,1 - ca7c: 000c3f40 call c3f4 - exit (result); - ca80: e13fff17 ldw r4,-4(fp) - ca84: 000faa00 call faa0 - -0000ca88 <__malloc_lock>: - * configuration is single threaded, so there is nothing to do here. Note that - * this requires that malloc is never called by an interrupt service routine. - */ - -void __malloc_lock ( struct _reent *_r ) -{ - ca88: defffe04 addi sp,sp,-8 - ca8c: df000115 stw fp,4(sp) - ca90: df000104 addi fp,sp,4 - ca94: e13fff15 stw r4,-4(fp) -} - ca98: e037883a mov sp,fp - ca9c: df000017 ldw fp,0(sp) - caa0: dec00104 addi sp,sp,4 - caa4: f800283a ret - -0000caa8 <__malloc_unlock>: -/* - * - */ - -void __malloc_unlock ( struct _reent *_r ) -{ - caa8: defffe04 addi sp,sp,-8 - caac: df000115 stw fp,4(sp) - cab0: df000104 addi fp,sp,4 - cab4: e13fff15 stw r4,-4(fp) -} - cab8: e037883a mov sp,fp - cabc: df000017 ldw fp,0(sp) - cac0: dec00104 addi sp,sp,4 - cac4: f800283a ret - -0000cac8 : -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -int ALT_READ (int file, void *ptr, size_t len) -{ - cac8: defff704 addi sp,sp,-36 - cacc: dfc00815 stw ra,32(sp) - cad0: df000715 stw fp,28(sp) - cad4: df000704 addi fp,sp,28 - cad8: e13ffb15 stw r4,-20(fp) - cadc: e17ffc15 stw r5,-16(fp) - cae0: e1bffd15 stw r6,-12(fp) - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - cae4: e0bffb17 ldw r2,-20(fp) - cae8: 1004803a cmplt r2,r2,zero - caec: 1000091e bne r2,zero,cb14 - caf0: e13ffb17 ldw r4,-20(fp) - caf4: 01400304 movi r5,12 - caf8: 0002b2c0 call 2b2c <__mulsi3> - cafc: 1007883a mov r3,r2 - cb00: 00800074 movhi r2,1 - cb04: 10837e04 addi r2,r2,3576 - cb08: 1887883a add r3,r3,r2 - cb0c: e0ffff15 stw r3,-4(fp) - cb10: 00000106 br cb18 - cb14: e03fff15 stw zero,-4(fp) - cb18: e0bfff17 ldw r2,-4(fp) - cb1c: e0bffa15 stw r2,-24(fp) - - if (fd) - cb20: e0bffa17 ldw r2,-24(fp) - cb24: 1005003a cmpeq r2,r2,zero - cb28: 1000241e bne r2,zero,cbbc - * If the file has not been opened with read access, or if the driver does - * not provide an implementation of read(), generate an error. Otherwise - * call the drivers read() function to process the request. - */ - - if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && - cb2c: e0bffa17 ldw r2,-24(fp) - cb30: 10800217 ldw r2,8(r2) - cb34: 108000cc andi r2,r2,3 - cb38: 10800060 cmpeqi r2,r2,1 - cb3c: 10001a1e bne r2,zero,cba8 - cb40: e0bffa17 ldw r2,-24(fp) - cb44: 10800017 ldw r2,0(r2) - cb48: 10800517 ldw r2,20(r2) - cb4c: 1005003a cmpeq r2,r2,zero - cb50: 1000151e bne r2,zero,cba8 - (fd->dev->read)) - { - if ((rval = fd->dev->read(fd, ptr, len)) < 0) - cb54: e0bffa17 ldw r2,-24(fp) - cb58: 10800017 ldw r2,0(r2) - cb5c: 10800517 ldw r2,20(r2) - cb60: e17ffc17 ldw r5,-16(fp) - cb64: e1bffd17 ldw r6,-12(fp) - cb68: e13ffa17 ldw r4,-24(fp) - cb6c: 103ee83a callr r2 - cb70: e0bff915 stw r2,-28(fp) - cb74: e0bff917 ldw r2,-28(fp) - cb78: 1004403a cmpge r2,r2,zero - cb7c: 1000071e bne r2,zero,cb9c - { - ALT_ERRNO = -rval; - cb80: 000cbec0 call cbec - cb84: e0fff917 ldw r3,-28(fp) - cb88: 00c7c83a sub r3,zero,r3 - cb8c: 10c00015 stw r3,0(r2) - return -1; - cb90: 00bfffc4 movi r2,-1 - cb94: e0bffe15 stw r2,-8(fp) - cb98: 00000e06 br cbd4 - } - return rval; - cb9c: e0bff917 ldw r2,-28(fp) - cba0: e0bffe15 stw r2,-8(fp) - cba4: 00000b06 br cbd4 - } - else - { - ALT_ERRNO = EACCES; - cba8: 000cbec0 call cbec - cbac: 1007883a mov r3,r2 - cbb0: 00800344 movi r2,13 - cbb4: 18800015 stw r2,0(r3) - cbb8: 00000406 br cbcc - } - } - else - { - ALT_ERRNO = EBADFD; - cbbc: 000cbec0 call cbec - cbc0: 1007883a mov r3,r2 - cbc4: 00801444 movi r2,81 - cbc8: 18800015 stw r2,0(r3) - } - return -1; - cbcc: 00bfffc4 movi r2,-1 - cbd0: e0bffe15 stw r2,-8(fp) - cbd4: e0bffe17 ldw r2,-8(fp) -} - cbd8: e037883a mov sp,fp - cbdc: dfc00117 ldw ra,4(sp) - cbe0: df000017 ldw fp,0(sp) - cbe4: dec00204 addi sp,sp,8 - cbe8: f800283a ret - -0000cbec : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - cbec: defffd04 addi sp,sp,-12 - cbf0: dfc00215 stw ra,8(sp) - cbf4: df000115 stw fp,4(sp) - cbf8: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - cbfc: 00800074 movhi r2,1 - cc00: 10884b04 addi r2,r2,8492 - cc04: 10800017 ldw r2,0(r2) - cc08: 1005003a cmpeq r2,r2,zero - cc0c: 1000061e bne r2,zero,cc28 - cc10: 00800074 movhi r2,1 - cc14: 10884b04 addi r2,r2,8492 - cc18: 10800017 ldw r2,0(r2) - cc1c: 103ee83a callr r2 - cc20: e0bfff15 stw r2,-4(fp) - cc24: 00000306 br cc34 - cc28: 00800074 movhi r2,1 - cc2c: 108f3e04 addi r2,r2,15608 - cc30: e0bfff15 stw r2,-4(fp) - cc34: e0bfff17 ldw r2,-4(fp) -} - cc38: e037883a mov sp,fp - cc3c: dfc00117 ldw ra,4(sp) - cc40: df000017 ldw fp,0(sp) - cc44: dec00204 addi sp,sp,8 - cc48: f800283a ret - -0000cc4c : - * File descriptors correcponding to standard in, standard out and standard - * error cannont be released backed to the pool. They are always reserved. - */ - -void alt_release_fd (int fd) -{ - cc4c: defffc04 addi sp,sp,-16 - cc50: dfc00315 stw ra,12(sp) - cc54: df000215 stw fp,8(sp) - cc58: dc000115 stw r16,4(sp) - cc5c: df000104 addi fp,sp,4 - cc60: e13fff15 stw r4,-4(fp) - if (fd > 2) - cc64: e0bfff17 ldw r2,-4(fp) - cc68: 108000d0 cmplti r2,r2,3 - cc6c: 10000f1e bne r2,zero,ccac - { - alt_fd_list[fd].fd_flags = 0; - cc70: e13fff17 ldw r4,-4(fp) - cc74: 04000074 movhi r16,1 - cc78: 84037e04 addi r16,r16,3576 - cc7c: 01400304 movi r5,12 - cc80: 0002b2c0 call 2b2c <__mulsi3> - cc84: 1405883a add r2,r2,r16 - cc88: 10800204 addi r2,r2,8 - cc8c: 10000015 stw zero,0(r2) - alt_fd_list[fd].dev = 0; - cc90: e13fff17 ldw r4,-4(fp) - cc94: 04000074 movhi r16,1 - cc98: 84037e04 addi r16,r16,3576 - cc9c: 01400304 movi r5,12 - cca0: 0002b2c0 call 2b2c <__mulsi3> - cca4: 1405883a add r2,r2,r16 - cca8: 10000015 stw zero,0(r2) - } -} - ccac: e037883a mov sp,fp - ccb0: dfc00217 ldw ra,8(sp) - ccb4: df000117 ldw fp,4(sp) - ccb8: dc000017 ldw r16,0(sp) - ccbc: dec00304 addi sp,sp,12 - ccc0: f800283a ret - -0000ccc4 : -#endif - -caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); - -caddr_t ALT_SBRK (int incr) -{ - ccc4: defff804 addi sp,sp,-32 - ccc8: df000715 stw fp,28(sp) - cccc: df000704 addi fp,sp,28 - ccd0: e13ffe15 stw r4,-8(fp) -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - ccd4: 0005303a rdctl r2,status - ccd8: e0bffb15 stw r2,-20(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - ccdc: e0fffb17 ldw r3,-20(fp) - cce0: 00bfff84 movi r2,-2 - cce4: 1884703a and r2,r3,r2 - cce8: 1001703a wrctl status,r2 - - return context; - ccec: e0bffb17 ldw r2,-20(fp) - alt_irq_context context; - char *prev_heap_end; - - context = alt_irq_disable_all(); - ccf0: e0bffd15 stw r2,-12(fp) - - /* Always return data aligned on a word boundary */ - heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); - ccf4: d0a00e17 ldw r2,-32712(gp) - ccf8: 10c000c4 addi r3,r2,3 - ccfc: 00bfff04 movi r2,-4 - cd00: 1884703a and r2,r3,r2 - cd04: d0a00e15 stw r2,-32712(gp) - if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { - alt_irq_enable_all(context); - return (caddr_t)-1; - } -#else - if ((heap_end + incr) > __alt_heap_limit) { - cd08: d0e00e17 ldw r3,-32712(gp) - cd0c: e0bffe17 ldw r2,-8(fp) - cd10: 1887883a add r3,r3,r2 - cd14: 008000f4 movhi r2,3 - cd18: 10880004 addi r2,r2,8192 - cd1c: 10c0072e bgeu r2,r3,cd3c - cd20: e0bffd17 ldw r2,-12(fp) - cd24: e0bffa15 stw r2,-24(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - cd28: e0bffa17 ldw r2,-24(fp) - cd2c: 1001703a wrctl status,r2 - alt_irq_enable_all(context); - return (caddr_t)-1; - cd30: 00bfffc4 movi r2,-1 - cd34: e0bfff15 stw r2,-4(fp) - cd38: 00000c06 br cd6c - } -#endif - - prev_heap_end = heap_end; - cd3c: d0a00e17 ldw r2,-32712(gp) - cd40: e0bffc15 stw r2,-16(fp) - heap_end += incr; - cd44: d0e00e17 ldw r3,-32712(gp) - cd48: e0bffe17 ldw r2,-8(fp) - cd4c: 1885883a add r2,r3,r2 - cd50: d0a00e15 stw r2,-32712(gp) - cd54: e0bffd17 ldw r2,-12(fp) - cd58: e0bff915 stw r2,-28(fp) - cd5c: e0bff917 ldw r2,-28(fp) - cd60: 1001703a wrctl status,r2 - -#endif - - alt_irq_enable_all(context); - - return (caddr_t) prev_heap_end; - cd64: e0bffc17 ldw r2,-16(fp) - cd68: e0bfff15 stw r2,-4(fp) - cd6c: e0bfff17 ldw r2,-4(fp) -} - cd70: e037883a mov sp,fp - cd74: df000017 ldw fp,0(sp) - cd78: dec00104 addi sp,sp,4 - cd7c: f800283a ret - -0000cd80 : -#if defined (__GNUC__) && __GNUC__ >= 4 -int ALT_USLEEP (useconds_t us) -#else -unsigned int ALT_USLEEP (unsigned int us) -#endif -{ - cd80: defffd04 addi sp,sp,-12 - cd84: dfc00215 stw ra,8(sp) - cd88: df000115 stw fp,4(sp) - cd8c: df000104 addi fp,sp,4 - cd90: e13fff15 stw r4,-4(fp) - return alt_busy_sleep(us); - cd94: e13fff17 ldw r4,-4(fp) - cd98: 000ebd40 call ebd4 -} - cd9c: e037883a mov sp,fp - cda0: dfc00117 ldw ra,4(sp) - cda4: df000017 ldw fp,0(sp) - cda8: dec00204 addi sp,sp,8 - cdac: f800283a ret - -0000cdb0 : -} - -#else /* !ALT_USE_DIRECT_DRIVERS */ - -int ALT_WRITE (int file, const void *ptr, size_t len) -{ - cdb0: defff704 addi sp,sp,-36 - cdb4: dfc00815 stw ra,32(sp) - cdb8: df000715 stw fp,28(sp) - cdbc: df000704 addi fp,sp,28 - cdc0: e13ffb15 stw r4,-20(fp) - cdc4: e17ffc15 stw r5,-16(fp) - cdc8: e1bffd15 stw r6,-12(fp) - * A common error case is that when the file descriptor was created, the call - * to open() failed resulting in a negative file descriptor. This is trapped - * below so that we don't try and process an invalid file descriptor. - */ - - fd = (file < 0) ? NULL : &alt_fd_list[file]; - cdcc: e0bffb17 ldw r2,-20(fp) - cdd0: 1004803a cmplt r2,r2,zero - cdd4: 1000091e bne r2,zero,cdfc - cdd8: e13ffb17 ldw r4,-20(fp) - cddc: 01400304 movi r5,12 - cde0: 0002b2c0 call 2b2c <__mulsi3> - cde4: 1007883a mov r3,r2 - cde8: 00800074 movhi r2,1 - cdec: 10837e04 addi r2,r2,3576 - cdf0: 1887883a add r3,r3,r2 - cdf4: e0ffff15 stw r3,-4(fp) - cdf8: 00000106 br ce00 - cdfc: e03fff15 stw zero,-4(fp) - ce00: e0bfff17 ldw r2,-4(fp) - ce04: e0bffa15 stw r2,-24(fp) - - if (fd) - ce08: e0bffa17 ldw r2,-24(fp) - ce0c: 1005003a cmpeq r2,r2,zero - ce10: 1000241e bne r2,zero,cea4 - * If the file has not been opened with write access, or if the driver does - * not provide an implementation of write(), generate an error. Otherwise - * call the drivers write() function to process the request. - */ - - if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) - ce14: e0bffa17 ldw r2,-24(fp) - ce18: 10800217 ldw r2,8(r2) - ce1c: 108000cc andi r2,r2,3 - ce20: 1005003a cmpeq r2,r2,zero - ce24: 10001a1e bne r2,zero,ce90 - ce28: e0bffa17 ldw r2,-24(fp) - ce2c: 10800017 ldw r2,0(r2) - ce30: 10800617 ldw r2,24(r2) - ce34: 1005003a cmpeq r2,r2,zero - ce38: 1000151e bne r2,zero,ce90 - { - - /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ - ALT_LOG_WRITE_FUNCTION(ptr,len); - - if ((rval = fd->dev->write(fd, ptr, len)) < 0) - ce3c: e0bffa17 ldw r2,-24(fp) - ce40: 10800017 ldw r2,0(r2) - ce44: 10800617 ldw r2,24(r2) - ce48: e17ffc17 ldw r5,-16(fp) - ce4c: e1bffd17 ldw r6,-12(fp) - ce50: e13ffa17 ldw r4,-24(fp) - ce54: 103ee83a callr r2 - ce58: e0bff915 stw r2,-28(fp) - ce5c: e0bff917 ldw r2,-28(fp) - ce60: 1004403a cmpge r2,r2,zero - ce64: 1000071e bne r2,zero,ce84 - { - ALT_ERRNO = -rval; - ce68: 000ced40 call ced4 - ce6c: e0fff917 ldw r3,-28(fp) - ce70: 00c7c83a sub r3,zero,r3 - ce74: 10c00015 stw r3,0(r2) - return -1; - ce78: 00bfffc4 movi r2,-1 - ce7c: e0bffe15 stw r2,-8(fp) - ce80: 00000e06 br cebc - } - return rval; - ce84: e0bff917 ldw r2,-28(fp) - ce88: e0bffe15 stw r2,-8(fp) - ce8c: 00000b06 br cebc - } - else - { - ALT_ERRNO = EACCES; - ce90: 000ced40 call ced4 - ce94: 1007883a mov r3,r2 - ce98: 00800344 movi r2,13 - ce9c: 18800015 stw r2,0(r3) - cea0: 00000406 br ceb4 - } - } - else - { - ALT_ERRNO = EBADFD; - cea4: 000ced40 call ced4 - cea8: 1007883a mov r3,r2 - ceac: 00801444 movi r2,81 - ceb0: 18800015 stw r2,0(r3) - } - return -1; - ceb4: 00bfffc4 movi r2,-1 - ceb8: e0bffe15 stw r2,-8(fp) - cebc: e0bffe17 ldw r2,-8(fp) -} - cec0: e037883a mov sp,fp - cec4: dfc00117 ldw ra,4(sp) - cec8: df000017 ldw fp,0(sp) - cecc: dec00204 addi sp,sp,8 - ced0: f800283a ret - -0000ced4 : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - ced4: defffd04 addi sp,sp,-12 - ced8: dfc00215 stw ra,8(sp) - cedc: df000115 stw fp,4(sp) - cee0: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - cee4: 00800074 movhi r2,1 - cee8: 10884b04 addi r2,r2,8492 - ceec: 10800017 ldw r2,0(r2) - cef0: 1005003a cmpeq r2,r2,zero - cef4: 1000061e bne r2,zero,cf10 - cef8: 00800074 movhi r2,1 - cefc: 10884b04 addi r2,r2,8492 - cf00: 10800017 ldw r2,0(r2) - cf04: 103ee83a callr r2 - cf08: e0bfff15 stw r2,-4(fp) - cf0c: 00000306 br cf1c - cf10: 00800074 movhi r2,1 - cf14: 108f3e04 addi r2,r2,15608 - cf18: e0bfff15 stw r2,-4(fp) - cf1c: e0bfff17 ldw r2,-4(fp) -} - cf20: e037883a mov sp,fp - cf24: dfc00117 ldw ra,4(sp) - cf28: df000017 ldw fp,0(sp) - cf2c: dec00204 addi sp,sp,8 - cf30: f800283a ret - -0000cf34 : - * The "base" parameter is ignored and only - * present for backwards-compatibility. - */ - -void alt_irq_init ( const void* base ) -{ - cf34: defffd04 addi sp,sp,-12 - cf38: dfc00215 stw ra,8(sp) - cf3c: df000115 stw fp,4(sp) - cf40: df000104 addi fp,sp,4 - cf44: e13fff15 stw r4,-4(fp) - ALTERA_NIOS2_QSYS_IRQ_INIT ( NIOS2_PROCESSOR, nios2_processor); - cf48: 000f7e80 call f7e8 - * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. - */ -static ALT_INLINE void ALT_ALWAYS_INLINE - alt_irq_cpu_enable_interrupts () -{ - NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK - cf4c: 00800044 movi r2,1 - cf50: 1001703a wrctl status,r2 - alt_irq_cpu_enable_interrupts(); -} - cf54: e037883a mov sp,fp - cf58: dfc00117 ldw ra,4(sp) - cf5c: df000017 ldw fp,0(sp) - cf60: dec00204 addi sp,sp,8 - cf64: f800283a ret - -0000cf68 : - * Initialize the non-interrupt controller devices. - * Called after alt_irq_init(). - */ - -void alt_sys_init( void ) -{ - cf68: defffe04 addi sp,sp,-8 - cf6c: dfc00115 stw ra,4(sp) - cf70: df000015 stw fp,0(sp) - cf74: d839883a mov fp,sp - ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart); - cf78: 01000074 movhi r4,1 - cf7c: 2103e804 addi r4,r4,4000 - cf80: 000b883a mov r5,zero - cf84: 01800144 movi r6,5 - cf88: 000d1440 call d144 - cf8c: 01000074 movhi r4,1 - cf90: 2103de04 addi r4,r4,3960 - cf94: 000cfc40 call cfc4 - ALTERA_AVALON_LCD_16207_INIT ( LCD_16207_0, lcd_16207_0); - cf98: 01000074 movhi r4,1 - cf9c: 21080004 addi r4,r4,8192 - cfa0: 000e8ec0 call e8ec - cfa4: 01000074 movhi r4,1 - cfa8: 2107f604 addi r4,r4,8152 - cfac: 000cfc40 call cfc4 -} - cfb0: e037883a mov sp,fp - cfb4: dfc00117 ldw ra,4(sp) - cfb8: df000017 ldw fp,0(sp) - cfbc: dec00204 addi sp,sp,8 - cfc0: f800283a ret - -0000cfc4 : - */ - -extern int alt_fs_reg (alt_dev* dev); - -static ALT_INLINE int alt_dev_reg (alt_dev* dev) -{ - cfc4: defffd04 addi sp,sp,-12 - cfc8: dfc00215 stw ra,8(sp) - cfcc: df000115 stw fp,4(sp) - cfd0: df000104 addi fp,sp,4 - cfd4: e13fff15 stw r4,-4(fp) - extern alt_llist alt_dev_list; - - return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); - cfd8: e13fff17 ldw r4,-4(fp) - cfdc: 01400074 movhi r5,1 - cfe0: 29484804 addi r5,r5,8480 - cfe4: 000ed4c0 call ed4c -} - cfe8: e037883a mov sp,fp - cfec: dfc00117 ldw ra,4(sp) - cff0: df000017 ldw fp,0(sp) - cff4: dec00204 addi sp,sp,8 - cff8: f800283a ret - -0000cffc : - * - */ - -int -altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) -{ - cffc: defffa04 addi sp,sp,-24 - d000: dfc00515 stw ra,20(sp) - d004: df000415 stw fp,16(sp) - d008: df000404 addi fp,sp,16 - d00c: e13ffd15 stw r4,-12(fp) - d010: e17ffe15 stw r5,-8(fp) - d014: e1bfff15 stw r6,-4(fp) - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - d018: e0bffd17 ldw r2,-12(fp) - d01c: 10800017 ldw r2,0(r2) - d020: e0bffc15 stw r2,-16(fp) - - return altera_avalon_jtag_uart_read(&dev->state, buffer, space, - d024: e0bffc17 ldw r2,-16(fp) - d028: 11000a04 addi r4,r2,40 - d02c: e0bffd17 ldw r2,-12(fp) - d030: 11c00217 ldw r7,8(r2) - d034: e17ffe17 ldw r5,-8(fp) - d038: e1bfff17 ldw r6,-4(fp) - d03c: 000d6440 call d644 - fd->fd_flags); -} - d040: e037883a mov sp,fp - d044: dfc00117 ldw ra,4(sp) - d048: df000017 ldw fp,0(sp) - d04c: dec00204 addi sp,sp,8 - d050: f800283a ret - -0000d054 : - -int -altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) -{ - d054: defffa04 addi sp,sp,-24 - d058: dfc00515 stw ra,20(sp) - d05c: df000415 stw fp,16(sp) - d060: df000404 addi fp,sp,16 - d064: e13ffd15 stw r4,-12(fp) - d068: e17ffe15 stw r5,-8(fp) - d06c: e1bfff15 stw r6,-4(fp) - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - d070: e0bffd17 ldw r2,-12(fp) - d074: 10800017 ldw r2,0(r2) - d078: e0bffc15 stw r2,-16(fp) - - return altera_avalon_jtag_uart_write(&dev->state, buffer, space, - d07c: e0bffc17 ldw r2,-16(fp) - d080: 11000a04 addi r4,r2,40 - d084: e0bffd17 ldw r2,-12(fp) - d088: 11c00217 ldw r7,8(r2) - d08c: e17ffe17 ldw r5,-8(fp) - d090: e1bfff17 ldw r6,-4(fp) - d094: 000d8680 call d868 - fd->fd_flags); -} - d098: e037883a mov sp,fp - d09c: dfc00117 ldw ra,4(sp) - d0a0: df000017 ldw fp,0(sp) - d0a4: dec00204 addi sp,sp,8 - d0a8: f800283a ret - -0000d0ac : - -#ifndef ALTERA_AVALON_JTAG_UART_SMALL - -int -altera_avalon_jtag_uart_close_fd(alt_fd* fd) -{ - d0ac: defffc04 addi sp,sp,-16 - d0b0: dfc00315 stw ra,12(sp) - d0b4: df000215 stw fp,8(sp) - d0b8: df000204 addi fp,sp,8 - d0bc: e13fff15 stw r4,-4(fp) - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - d0c0: e0bfff17 ldw r2,-4(fp) - d0c4: 10800017 ldw r2,0(r2) - d0c8: e0bffe15 stw r2,-8(fp) - - return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); - d0cc: e0bffe17 ldw r2,-8(fp) - d0d0: 11000a04 addi r4,r2,40 - d0d4: e0bfff17 ldw r2,-4(fp) - d0d8: 11400217 ldw r5,8(r2) - d0dc: 000d4dc0 call d4dc -} - d0e0: e037883a mov sp,fp - d0e4: dfc00117 ldw ra,4(sp) - d0e8: df000017 ldw fp,0(sp) - d0ec: dec00204 addi sp,sp,8 - d0f0: f800283a ret - -0000d0f4 : - -int -altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) -{ - d0f4: defffa04 addi sp,sp,-24 - d0f8: dfc00515 stw ra,20(sp) - d0fc: df000415 stw fp,16(sp) - d100: df000404 addi fp,sp,16 - d104: e13ffd15 stw r4,-12(fp) - d108: e17ffe15 stw r5,-8(fp) - d10c: e1bfff15 stw r6,-4(fp) - altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; - d110: e0bffd17 ldw r2,-12(fp) - d114: 10800017 ldw r2,0(r2) - d118: e0bffc15 stw r2,-16(fp) - - return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); - d11c: e0bffc17 ldw r2,-16(fp) - d120: 11000a04 addi r4,r2,40 - d124: e17ffe17 ldw r5,-8(fp) - d128: e1bfff17 ldw r6,-4(fp) - d12c: 000d5500 call d550 -} - d130: e037883a mov sp,fp - d134: dfc00117 ldw ra,4(sp) - d138: df000017 ldw fp,0(sp) - d13c: dec00204 addi sp,sp,8 - d140: f800283a ret - -0000d144 : - * Return 1 on sucessful IRQ register and 0 on failure. - */ - -void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, - int irq_controller_id, int irq) -{ - d144: defffa04 addi sp,sp,-24 - d148: dfc00515 stw ra,20(sp) - d14c: df000415 stw fp,16(sp) - d150: df000404 addi fp,sp,16 - d154: e13ffd15 stw r4,-12(fp) - d158: e17ffe15 stw r5,-8(fp) - d15c: e1bfff15 stw r6,-4(fp) - ALT_FLAG_CREATE(&sp->events, 0); - ALT_SEM_CREATE(&sp->read_lock, 1); - ALT_SEM_CREATE(&sp->write_lock, 1); - - /* enable read interrupts at the device */ - sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; - d160: e0fffd17 ldw r3,-12(fp) - d164: 00800044 movi r2,1 - d168: 18800815 stw r2,32(r3) - - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - d16c: e0bffd17 ldw r2,-12(fp) - d170: 10800017 ldw r2,0(r2) - d174: 11000104 addi r4,r2,4 - d178: e0bffd17 ldw r2,-12(fp) - d17c: 10800817 ldw r2,32(r2) - d180: 1007883a mov r3,r2 - d184: 2005883a mov r2,r4 - d188: 10c00035 stwio r3,0(r2) - - /* register the interrupt handler */ -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT - alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, - d18c: e13ffe17 ldw r4,-8(fp) - d190: e17fff17 ldw r5,-4(fp) - d194: d8000015 stw zero,0(sp) - d198: 01800074 movhi r6,1 - d19c: 31b48104 addi r6,r6,-11772 - d1a0: e1fffd17 ldw r7,-12(fp) - d1a4: 000ef440 call ef44 -#else - alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); -#endif - - /* Register an alarm to go off every second to check for presence of host */ - sp->host_inactive = 0; - d1a8: e0bffd17 ldw r2,-12(fp) - d1ac: 10000915 stw zero,36(r2) - - if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), - d1b0: e0bffd17 ldw r2,-12(fp) - d1b4: 11000204 addi r4,r2,8 - * Obtain the system clock rate in ticks/s. - */ - -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) -{ - return _alt_tick_rate; - d1b8: 00800074 movhi r2,1 - d1bc: 108f4304 addi r2,r2,15628 - d1c0: 10800017 ldw r2,0(r2) - d1c4: 100b883a mov r5,r2 - d1c8: 01800074 movhi r6,1 - d1cc: 31b50b04 addi r6,r6,-11220 - d1d0: e1fffd17 ldw r7,-12(fp) - d1d4: 000ea800 call ea80 - d1d8: 1004403a cmpge r2,r2,zero - d1dc: 1000041e bne r2,zero,d1f0 - &altera_avalon_jtag_uart_timeout, sp) < 0) - { - /* If we can't set the alarm then record "don't know if host present" - * and behave as though the host is present. - */ - sp->timeout = INT_MAX; - d1e0: e0fffd17 ldw r3,-12(fp) - d1e4: 00a00034 movhi r2,32768 - d1e8: 10bfffc4 addi r2,r2,-1 - d1ec: 18800115 stw r2,4(r3) - } - - /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ - ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); -} - d1f0: e037883a mov sp,fp - d1f4: dfc00117 ldw ra,4(sp) - d1f8: df000017 ldw fp,0(sp) - d1fc: dec00204 addi sp,sp,8 - d200: f800283a ret - -0000d204 : -#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT -static void altera_avalon_jtag_uart_irq(void* context) -#else -static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) -#endif -{ - d204: defff804 addi sp,sp,-32 - d208: df000715 stw fp,28(sp) - d20c: df000704 addi fp,sp,28 - d210: e13fff15 stw r4,-4(fp) - altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; - d214: e0bfff17 ldw r2,-4(fp) - d218: e0bffe15 stw r2,-8(fp) - unsigned int base = sp->base; - d21c: e0bffe17 ldw r2,-8(fp) - d220: 10800017 ldw r2,0(r2) - d224: e0bffd15 stw r2,-12(fp) - d228: 00000006 br d22c - /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ - ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); - - for ( ; ; ) - { - unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); - d22c: e0bffd17 ldw r2,-12(fp) - d230: 10800104 addi r2,r2,4 - d234: 10800037 ldwio r2,0(r2) - d238: e0bffc15 stw r2,-16(fp) - - /* Return once nothing more to do */ - if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) - d23c: e0bffc17 ldw r2,-16(fp) - d240: 1080c00c andi r2,r2,768 - d244: 1005003a cmpeq r2,r2,zero - d248: 1000741e bne r2,zero,d41c - break; - - if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) - d24c: e0bffc17 ldw r2,-16(fp) - d250: 1080400c andi r2,r2,256 - d254: 1005003a cmpeq r2,r2,zero - d258: 1000351e bne r2,zero,d330 - { - /* process a read irq. Start by assuming that there is data in the - * receive FIFO (otherwise why would we have been interrupted?) - */ - unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; - d25c: 00800074 movhi r2,1 - d260: e0bffb15 stw r2,-20(fp) - for ( ; ; ) - { - /* Check whether there is space in the buffer. If not then we must not - * read any characters from the buffer as they will be lost. - */ - unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - d264: e0bffe17 ldw r2,-8(fp) - d268: 10800a17 ldw r2,40(r2) - d26c: 10800044 addi r2,r2,1 - d270: 1081ffcc andi r2,r2,2047 - d274: e0bffa15 stw r2,-24(fp) - if (next == sp->rx_out) - d278: e0bffe17 ldw r2,-8(fp) - d27c: 10c00b17 ldw r3,44(r2) - d280: e0bffa17 ldw r2,-24(fp) - d284: 18801626 beq r3,r2,d2e0 - break; - - /* Try to remove a character from the FIFO and find out whether there - * are any more characters remaining. - */ - data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); - d288: e0bffd17 ldw r2,-12(fp) - d28c: 10800037 ldwio r2,0(r2) - d290: e0bffb15 stw r2,-20(fp) - - if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) - d294: e0bffb17 ldw r2,-20(fp) - d298: 10a0000c andi r2,r2,32768 - d29c: 1005003a cmpeq r2,r2,zero - d2a0: 10000f1e bne r2,zero,d2e0 - break; - - sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; - d2a4: e0bffe17 ldw r2,-8(fp) - d2a8: 10c00a17 ldw r3,40(r2) - d2ac: e0bffb17 ldw r2,-20(fp) - d2b0: 1009883a mov r4,r2 - d2b4: e0bffe17 ldw r2,-8(fp) - d2b8: 1885883a add r2,r3,r2 - d2bc: 10800e04 addi r2,r2,56 - d2c0: 11000005 stb r4,0(r2) - sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - d2c4: e0bffe17 ldw r2,-8(fp) - d2c8: 10800a17 ldw r2,40(r2) - d2cc: 10800044 addi r2,r2,1 - d2d0: 10c1ffcc andi r3,r2,2047 - d2d4: e0bffe17 ldw r2,-8(fp) - d2d8: 10c00a15 stw r3,40(r2) - - /* Post an event to notify jtag_uart_read that a character has been read */ - ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); - } - d2dc: 003fe106 br d264 - - if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) - d2e0: e0bffb17 ldw r2,-20(fp) - d2e4: 10bfffec andhi r2,r2,65535 - d2e8: 1005003a cmpeq r2,r2,zero - d2ec: 1000101e bne r2,zero,d330 - { - /* If there is still data available here then the buffer is full - * so turn off receive interrupts until some space becomes available. - */ - sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; - d2f0: e0bffe17 ldw r2,-8(fp) - d2f4: 10c00817 ldw r3,32(r2) - d2f8: 00bfff84 movi r2,-2 - d2fc: 1886703a and r3,r3,r2 - d300: e0bffe17 ldw r2,-8(fp) - d304: 10c00815 stw r3,32(r2) - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); - d308: e0bffd17 ldw r2,-12(fp) - d30c: 11000104 addi r4,r2,4 - d310: e0bffe17 ldw r2,-8(fp) - d314: 10800817 ldw r2,32(r2) - d318: 1007883a mov r3,r2 - d31c: 2005883a mov r2,r4 - d320: 10c00035 stwio r3,0(r2) - - /* Dummy read to ensure IRQ is cleared prior to ISR completion */ - IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); - d324: e0bffd17 ldw r2,-12(fp) - d328: 10800104 addi r2,r2,4 - d32c: 10800037 ldwio r2,0(r2) - } - } - - if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) - d330: e0bffc17 ldw r2,-16(fp) - d334: 1080800c andi r2,r2,512 - d338: 1005003a cmpeq r2,r2,zero - d33c: 103fbb1e bne r2,zero,d22c - { - /* process a write irq */ - unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; - d340: e0bffc17 ldw r2,-16(fp) - d344: 10bfffec andhi r2,r2,65535 - d348: 1004d43a srli r2,r2,16 - d34c: e0bff915 stw r2,-28(fp) - - while (space > 0 && sp->tx_out != sp->tx_in) - d350: 00001506 br d3a8 - { - IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); - d354: e13ffd17 ldw r4,-12(fp) - d358: e0bffe17 ldw r2,-8(fp) - d35c: 10c00d17 ldw r3,52(r2) - d360: e0bffe17 ldw r2,-8(fp) - d364: 1885883a add r2,r3,r2 - d368: 10820e04 addi r2,r2,2104 - d36c: 10800003 ldbu r2,0(r2) - d370: 10c03fcc andi r3,r2,255 - d374: 18c0201c xori r3,r3,128 - d378: 18ffe004 addi r3,r3,-128 - d37c: 2005883a mov r2,r4 - d380: 10c00035 stwio r3,0(r2) - - sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - d384: e0bffe17 ldw r2,-8(fp) - d388: 10800d17 ldw r2,52(r2) - d38c: 10800044 addi r2,r2,1 - d390: 10c1ffcc andi r3,r2,2047 - d394: e0bffe17 ldw r2,-8(fp) - d398: 10c00d15 stw r3,52(r2) - - /* Post an event to notify jtag_uart_write that a character has been written */ - ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); - - space--; - d39c: e0bff917 ldw r2,-28(fp) - d3a0: 10bfffc4 addi r2,r2,-1 - d3a4: e0bff915 stw r2,-28(fp) - if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) - { - /* process a write irq */ - unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; - - while (space > 0 && sp->tx_out != sp->tx_in) - d3a8: e0bff917 ldw r2,-28(fp) - d3ac: 1005003a cmpeq r2,r2,zero - d3b0: 1000051e bne r2,zero,d3c8 - d3b4: e0bffe17 ldw r2,-8(fp) - d3b8: 10c00d17 ldw r3,52(r2) - d3bc: e0bffe17 ldw r2,-8(fp) - d3c0: 10800c17 ldw r2,48(r2) - d3c4: 18bfe31e bne r3,r2,d354 - ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); - - space--; - } - - if (space > 0) - d3c8: e0bff917 ldw r2,-28(fp) - d3cc: 1005003a cmpeq r2,r2,zero - d3d0: 103f961e bne r2,zero,d22c - { - /* If we don't have any more data available then turn off the TX interrupt */ - sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; - d3d4: e0bffe17 ldw r2,-8(fp) - d3d8: 10c00817 ldw r3,32(r2) - d3dc: 00bfff44 movi r2,-3 - d3e0: 1886703a and r3,r3,r2 - d3e4: e0bffe17 ldw r2,-8(fp) - d3e8: 10c00815 stw r3,32(r2) - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - d3ec: e0bffe17 ldw r2,-8(fp) - d3f0: 10800017 ldw r2,0(r2) - d3f4: 11000104 addi r4,r2,4 - d3f8: e0bffe17 ldw r2,-8(fp) - d3fc: 10800817 ldw r2,32(r2) - d400: 1007883a mov r3,r2 - d404: 2005883a mov r2,r4 - d408: 10c00035 stwio r3,0(r2) - - /* Dummy read to ensure IRQ is cleared prior to ISR completion */ - IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); - d40c: e0bffd17 ldw r2,-12(fp) - d410: 10800104 addi r2,r2,4 - d414: 10800037 ldwio r2,0(r2) - } - } - } - d418: 003f8406 br d22c -} - d41c: e037883a mov sp,fp - d420: df000017 ldw fp,0(sp) - d424: dec00104 addi sp,sp,4 - d428: f800283a ret - -0000d42c : - * Timeout routine is called every second - */ - -static alt_u32 -altera_avalon_jtag_uart_timeout(void* context) -{ - d42c: defffc04 addi sp,sp,-16 - d430: df000315 stw fp,12(sp) - d434: df000304 addi fp,sp,12 - d438: e13fff15 stw r4,-4(fp) - altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; - d43c: e0bfff17 ldw r2,-4(fp) - d440: e0bffe15 stw r2,-8(fp) - - unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); - d444: e0bffe17 ldw r2,-8(fp) - d448: 10800017 ldw r2,0(r2) - d44c: 10800104 addi r2,r2,4 - d450: 10800037 ldwio r2,0(r2) - d454: e0bffd15 stw r2,-12(fp) - - if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) - d458: e0bffd17 ldw r2,-12(fp) - d45c: 1081000c andi r2,r2,1024 - d460: 1005003a cmpeq r2,r2,zero - d464: 10000c1e bne r2,zero,d498 - { - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); - d468: e0bffe17 ldw r2,-8(fp) - d46c: 10800017 ldw r2,0(r2) - d470: 11000104 addi r4,r2,4 - d474: e0bffe17 ldw r2,-8(fp) - d478: 10800817 ldw r2,32(r2) - d47c: 10810014 ori r2,r2,1024 - d480: 1007883a mov r3,r2 - d484: 2005883a mov r2,r4 - d488: 10c00035 stwio r3,0(r2) - sp->host_inactive = 0; - d48c: e0bffe17 ldw r2,-8(fp) - d490: 10000915 stw zero,36(r2) - d494: 00000a06 br d4c0 - } - else if (sp->host_inactive < INT_MAX - 2) { - d498: e0bffe17 ldw r2,-8(fp) - d49c: 10c00917 ldw r3,36(r2) - d4a0: 00a00034 movhi r2,32768 - d4a4: 10bfff04 addi r2,r2,-4 - d4a8: 10c00536 bltu r2,r3,d4c0 - sp->host_inactive++; - d4ac: e0bffe17 ldw r2,-8(fp) - d4b0: 10800917 ldw r2,36(r2) - d4b4: 10c00044 addi r3,r2,1 - d4b8: e0bffe17 ldw r2,-8(fp) - d4bc: 10c00915 stw r3,36(r2) - d4c0: 00800074 movhi r2,1 - d4c4: 108f4304 addi r2,r2,15628 - d4c8: 10800017 ldw r2,0(r2) - ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); - } - } - - return alt_ticks_per_second(); -} - d4cc: e037883a mov sp,fp - d4d0: df000017 ldw fp,0(sp) - d4d4: dec00104 addi sp,sp,4 - d4d8: f800283a ret - -0000d4dc : - * The close routine is not implemented for the small driver; instead it will - * map to null. This is because the small driver simply waits while characters - * are transmitted; there is no interrupt-serviced buffer to empty - */ -int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) -{ - d4dc: defffc04 addi sp,sp,-16 - d4e0: df000315 stw fp,12(sp) - d4e4: df000304 addi fp,sp,12 - d4e8: e13ffd15 stw r4,-12(fp) - d4ec: e17ffe15 stw r5,-8(fp) - /* - * Wait for all transmit data to be emptied by the JTAG UART ISR, or - * for a host-inactivity timeout, in which case transmit data will be lost - */ - while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { - d4f0: 00000706 br d510 - if (flags & O_NONBLOCK) { - d4f4: e0bffe17 ldw r2,-8(fp) - d4f8: 1090000c andi r2,r2,16384 - d4fc: 1005003a cmpeq r2,r2,zero - d500: 1000031e bne r2,zero,d510 - return -EWOULDBLOCK; - d504: 00bffd44 movi r2,-11 - d508: e0bfff15 stw r2,-4(fp) - d50c: 00000b06 br d53c -{ - /* - * Wait for all transmit data to be emptied by the JTAG UART ISR, or - * for a host-inactivity timeout, in which case transmit data will be lost - */ - while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { - d510: e0bffd17 ldw r2,-12(fp) - d514: 10c00d17 ldw r3,52(r2) - d518: e0bffd17 ldw r2,-12(fp) - d51c: 10800c17 ldw r2,48(r2) - d520: 18800526 beq r3,r2,d538 - d524: e0bffd17 ldw r2,-12(fp) - d528: 10c00917 ldw r3,36(r2) - d52c: e0bffd17 ldw r2,-12(fp) - d530: 10800117 ldw r2,4(r2) - d534: 18bfef36 bltu r3,r2,d4f4 - if (flags & O_NONBLOCK) { - return -EWOULDBLOCK; - } - } - - return 0; - d538: e03fff15 stw zero,-4(fp) - d53c: e0bfff17 ldw r2,-4(fp) -} - d540: e037883a mov sp,fp - d544: df000017 ldw fp,0(sp) - d548: dec00104 addi sp,sp,4 - d54c: f800283a ret - -0000d550 : -/* ----------------------------------------------------------- */ - -int -altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, - void* arg) -{ - d550: defff804 addi sp,sp,-32 - d554: df000715 stw fp,28(sp) - d558: df000704 addi fp,sp,28 - d55c: e13ffb15 stw r4,-20(fp) - d560: e17ffc15 stw r5,-16(fp) - d564: e1bffd15 stw r6,-12(fp) - int rc = -ENOTTY; - d568: 00bff9c4 movi r2,-25 - d56c: e0bffa15 stw r2,-24(fp) - - switch (req) - d570: e0bffc17 ldw r2,-16(fp) - d574: e0bfff15 stw r2,-4(fp) - d578: e0ffff17 ldw r3,-4(fp) - d57c: 189a8060 cmpeqi r2,r3,27137 - d580: 1000041e bne r2,zero,d594 - d584: e0ffff17 ldw r3,-4(fp) - d588: 189a80a0 cmpeqi r2,r3,27138 - d58c: 10001b1e bne r2,zero,d5fc - d590: 00002706 br d630 - { - case TIOCSTIMEOUT: - /* Set the time to wait until assuming host is not connected */ - if (sp->timeout != INT_MAX) - d594: e0bffb17 ldw r2,-20(fp) - d598: 10c00117 ldw r3,4(r2) - d59c: 00a00034 movhi r2,32768 - d5a0: 10bfffc4 addi r2,r2,-1 - d5a4: 18802226 beq r3,r2,d630 - { - int timeout = *((int *)arg); - d5a8: e0bffd17 ldw r2,-12(fp) - d5ac: 10800017 ldw r2,0(r2) - d5b0: e0bff915 stw r2,-28(fp) - sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; - d5b4: e0bff917 ldw r2,-28(fp) - d5b8: 10800090 cmplti r2,r2,2 - d5bc: 1000071e bne r2,zero,d5dc - d5c0: e0fff917 ldw r3,-28(fp) - d5c4: 00a00034 movhi r2,32768 - d5c8: 10bfffc4 addi r2,r2,-1 - d5cc: 18800326 beq r3,r2,d5dc - d5d0: e0bff917 ldw r2,-28(fp) - d5d4: e0bffe15 stw r2,-8(fp) - d5d8: 00000306 br d5e8 - d5dc: 00e00034 movhi r3,32768 - d5e0: 18ffff84 addi r3,r3,-2 - d5e4: e0fffe15 stw r3,-8(fp) - d5e8: e0bffb17 ldw r2,-20(fp) - d5ec: e0fffe17 ldw r3,-8(fp) - d5f0: 10c00115 stw r3,4(r2) - rc = 0; - d5f4: e03ffa15 stw zero,-24(fp) - } - break; - d5f8: 00000d06 br d630 - - case TIOCGCONNECTED: - /* Find out whether host is connected */ - if (sp->timeout != INT_MAX) - d5fc: e0bffb17 ldw r2,-20(fp) - d600: 10c00117 ldw r3,4(r2) - d604: 00a00034 movhi r2,32768 - d608: 10bfffc4 addi r2,r2,-1 - d60c: 18800826 beq r3,r2,d630 - { - *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; - d610: e13ffd17 ldw r4,-12(fp) - d614: e0bffb17 ldw r2,-20(fp) - d618: 10c00917 ldw r3,36(r2) - d61c: e0bffb17 ldw r2,-20(fp) - d620: 10800117 ldw r2,4(r2) - d624: 1885803a cmpltu r2,r3,r2 - d628: 20800015 stw r2,0(r4) - rc = 0; - d62c: e03ffa15 stw zero,-24(fp) - - default: - break; - } - - return rc; - d630: e0bffa17 ldw r2,-24(fp) -} - d634: e037883a mov sp,fp - d638: df000017 ldw fp,0(sp) - d63c: dec00104 addi sp,sp,4 - d640: f800283a ret - -0000d644 : -/* ----------------------------------------------------------- */ - -int -altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, - char * buffer, int space, int flags) -{ - d644: defff204 addi sp,sp,-56 - d648: dfc00d15 stw ra,52(sp) - d64c: df000c15 stw fp,48(sp) - d650: df000c04 addi fp,sp,48 - d654: e13ffb15 stw r4,-20(fp) - d658: e17ffc15 stw r5,-16(fp) - d65c: e1bffd15 stw r6,-12(fp) - d660: e1fffe15 stw r7,-8(fp) - char * ptr = buffer; - d664: e0bffc17 ldw r2,-16(fp) - d668: e0bffa15 stw r2,-24(fp) - * When running in a multi threaded environment, obtain the "read_lock" - * semaphore. This ensures that reading from the device is thread-safe. - */ - ALT_SEM_PEND (sp->read_lock, 0); - - while (space > 0) - d66c: 00004806 br d790 - unsigned int in, out; - - /* Read as much data as possible */ - do - { - in = sp->rx_in; - d670: e0bffb17 ldw r2,-20(fp) - d674: 10800a17 ldw r2,40(r2) - d678: e0bff715 stw r2,-36(fp) - out = sp->rx_out; - d67c: e0bffb17 ldw r2,-20(fp) - d680: 10800b17 ldw r2,44(r2) - d684: e0bff615 stw r2,-40(fp) - - if (in >= out) - d688: e0fff717 ldw r3,-36(fp) - d68c: e0bff617 ldw r2,-40(fp) - d690: 18800536 bltu r3,r2,d6a8 - n = in - out; - d694: e0bff717 ldw r2,-36(fp) - d698: e0fff617 ldw r3,-40(fp) - d69c: 10c5c83a sub r2,r2,r3 - d6a0: e0bff815 stw r2,-32(fp) - d6a4: 00000406 br d6b8 - else - n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; - d6a8: 00820004 movi r2,2048 - d6ac: e0fff617 ldw r3,-40(fp) - d6b0: 10c5c83a sub r2,r2,r3 - d6b4: e0bff815 stw r2,-32(fp) - - if (n == 0) - d6b8: e0bff817 ldw r2,-32(fp) - d6bc: 1005003a cmpeq r2,r2,zero - d6c0: 10001f1e bne r2,zero,d740 - break; /* No more data available */ - - if (n > space) - d6c4: e0fffd17 ldw r3,-12(fp) - d6c8: e0bff817 ldw r2,-32(fp) - d6cc: 1880022e bgeu r3,r2,d6d8 - n = space; - d6d0: e0bffd17 ldw r2,-12(fp) - d6d4: e0bff815 stw r2,-32(fp) - - memcpy(ptr, sp->rx_buf + out, n); - d6d8: e0bffb17 ldw r2,-20(fp) - d6dc: 10c00e04 addi r3,r2,56 - d6e0: e0bff617 ldw r2,-40(fp) - d6e4: 1887883a add r3,r3,r2 - d6e8: e0bffa17 ldw r2,-24(fp) - d6ec: 1009883a mov r4,r2 - d6f0: 180b883a mov r5,r3 - d6f4: e1bff817 ldw r6,-32(fp) - d6f8: 0007f1c0 call 7f1c - ptr += n; - d6fc: e0fff817 ldw r3,-32(fp) - d700: e0bffa17 ldw r2,-24(fp) - d704: 10c5883a add r2,r2,r3 - d708: e0bffa15 stw r2,-24(fp) - space -= n; - d70c: e0fffd17 ldw r3,-12(fp) - d710: e0bff817 ldw r2,-32(fp) - d714: 1885c83a sub r2,r3,r2 - d718: e0bffd15 stw r2,-12(fp) - - sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - d71c: e0fff617 ldw r3,-40(fp) - d720: e0bff817 ldw r2,-32(fp) - d724: 1885883a add r2,r3,r2 - d728: 10c1ffcc andi r3,r2,2047 - d72c: e0bffb17 ldw r2,-20(fp) - d730: 10c00b15 stw r3,44(r2) - } - while (space > 0); - d734: e0bffd17 ldw r2,-12(fp) - d738: 10800048 cmpgei r2,r2,1 - d73c: 103fcc1e bne r2,zero,d670 - - /* If we read any data then return it */ - if (ptr != buffer) - d740: e0fffa17 ldw r3,-24(fp) - d744: e0bffc17 ldw r2,-16(fp) - d748: 1880141e bne r3,r2,d79c - break; - - /* If in non-blocking mode then return error */ - if (flags & O_NONBLOCK) - d74c: e0bffe17 ldw r2,-8(fp) - d750: 1090000c andi r2,r2,16384 - d754: 1004c03a cmpne r2,r2,zero - d758: 1000101e bne r2,zero,d79c - while (in == sp->rx_in && sp->host_inactive < sp->timeout) - ; - } -#else - /* No OS: Always spin */ - while (in == sp->rx_in && sp->host_inactive < sp->timeout) - d75c: e0bffb17 ldw r2,-20(fp) - d760: 10c00a17 ldw r3,40(r2) - d764: e0bff717 ldw r2,-36(fp) - d768: 1880051e bne r3,r2,d780 - d76c: e0bffb17 ldw r2,-20(fp) - d770: 10c00917 ldw r3,36(r2) - d774: e0bffb17 ldw r2,-20(fp) - d778: 10800117 ldw r2,4(r2) - d77c: 18bff736 bltu r3,r2,d75c - ; -#endif /* __ucosii__ */ - - if (in == sp->rx_in) - d780: e0bffb17 ldw r2,-20(fp) - d784: 10c00a17 ldw r3,40(r2) - d788: e0bff717 ldw r2,-36(fp) - d78c: 18800326 beq r3,r2,d79c - * When running in a multi threaded environment, obtain the "read_lock" - * semaphore. This ensures that reading from the device is thread-safe. - */ - ALT_SEM_PEND (sp->read_lock, 0); - - while (space > 0) - d790: e0bffd17 ldw r2,-12(fp) - d794: 10800048 cmpgei r2,r2,1 - d798: 103fb51e bne r2,zero,d670 - * semaphore so that other threads can access the buffer. - */ - - ALT_SEM_POST (sp->read_lock); - - if (ptr != buffer) - d79c: e0fffa17 ldw r3,-24(fp) - d7a0: e0bffc17 ldw r2,-16(fp) - d7a4: 18801926 beq r3,r2,d80c -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - d7a8: 0005303a rdctl r2,status - d7ac: e0bff515 stw r2,-44(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - d7b0: e0fff517 ldw r3,-44(fp) - d7b4: 00bfff84 movi r2,-2 - d7b8: 1884703a and r2,r3,r2 - d7bc: 1001703a wrctl status,r2 - - return context; - d7c0: e0bff517 ldw r2,-44(fp) - { - /* If we read any data then there is space in the buffer so enable interrupts */ - context = alt_irq_disable_all(); - d7c4: e0bff915 stw r2,-28(fp) - sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; - d7c8: e0bffb17 ldw r2,-20(fp) - d7cc: 10800817 ldw r2,32(r2) - d7d0: 10c00054 ori r3,r2,1 - d7d4: e0bffb17 ldw r2,-20(fp) - d7d8: 10c00815 stw r3,32(r2) - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - d7dc: e0bffb17 ldw r2,-20(fp) - d7e0: 10800017 ldw r2,0(r2) - d7e4: 11000104 addi r4,r2,4 - d7e8: e0bffb17 ldw r2,-20(fp) - d7ec: 10800817 ldw r2,32(r2) - d7f0: 1007883a mov r3,r2 - d7f4: 2005883a mov r2,r4 - d7f8: 10c00035 stwio r3,0(r2) - d7fc: e0bff917 ldw r2,-28(fp) - d800: e0bff415 stw r2,-48(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - d804: e0bff417 ldw r2,-48(fp) - d808: 1001703a wrctl status,r2 - alt_irq_enable_all(context); - } - - if (ptr != buffer) - d80c: e0fffa17 ldw r3,-24(fp) - d810: e0bffc17 ldw r2,-16(fp) - d814: 18800526 beq r3,r2,d82c - return ptr - buffer; - d818: e0fffa17 ldw r3,-24(fp) - d81c: e0bffc17 ldw r2,-16(fp) - d820: 1887c83a sub r3,r3,r2 - d824: e0ffff15 stw r3,-4(fp) - d828: 00000906 br d850 - else if (flags & O_NONBLOCK) - d82c: e0bffe17 ldw r2,-8(fp) - d830: 1090000c andi r2,r2,16384 - d834: 1005003a cmpeq r2,r2,zero - d838: 1000031e bne r2,zero,d848 - return -EWOULDBLOCK; - d83c: 00bffd44 movi r2,-11 - d840: e0bfff15 stw r2,-4(fp) - d844: 00000206 br d850 - else - return -EIO; - d848: 00bffec4 movi r2,-5 - d84c: e0bfff15 stw r2,-4(fp) - d850: e0bfff17 ldw r2,-4(fp) -} - d854: e037883a mov sp,fp - d858: dfc00117 ldw ra,4(sp) - d85c: df000017 ldw fp,0(sp) - d860: dec00204 addi sp,sp,8 - d864: f800283a ret - -0000d868 : -/* ----------------------------------------------------------- */ - -int -altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, - const char * ptr, int count, int flags) -{ - d868: defff204 addi sp,sp,-56 - d86c: dfc00d15 stw ra,52(sp) - d870: df000c15 stw fp,48(sp) - d874: df000c04 addi fp,sp,48 - d878: e13ffb15 stw r4,-20(fp) - d87c: e17ffc15 stw r5,-16(fp) - d880: e1bffd15 stw r6,-12(fp) - d884: e1fffe15 stw r7,-8(fp) - /* Remove warning at optimisation level 03 by seting out to 0 */ - unsigned int in, out=0; - d888: e03ff915 stw zero,-28(fp) - unsigned int n; - alt_irq_context context; - - const char * start = ptr; - d88c: e0bffc17 ldw r2,-16(fp) - d890: e0bff615 stw r2,-40(fp) - ALT_SEM_PEND (sp->write_lock, 0); - - do - { - /* Copy as much as we can into the transmit buffer */ - while (count > 0) - d894: 00003a06 br d980 - { - /* We need a stable value of the out pointer to calculate the space available */ - in = sp->tx_in; - d898: e0bffb17 ldw r2,-20(fp) - d89c: 10800c17 ldw r2,48(r2) - d8a0: e0bffa15 stw r2,-24(fp) - out = sp->tx_out; - d8a4: e0bffb17 ldw r2,-20(fp) - d8a8: 10800d17 ldw r2,52(r2) - d8ac: e0bff915 stw r2,-28(fp) - - if (in < out) - d8b0: e0fffa17 ldw r3,-24(fp) - d8b4: e0bff917 ldw r2,-28(fp) - d8b8: 1880062e bgeu r3,r2,d8d4 - n = out - 1 - in; - d8bc: e0fff917 ldw r3,-28(fp) - d8c0: e0bffa17 ldw r2,-24(fp) - d8c4: 1885c83a sub r2,r3,r2 - d8c8: 10bfffc4 addi r2,r2,-1 - d8cc: e0bff815 stw r2,-32(fp) - d8d0: 00000c06 br d904 - else if (out > 0) - d8d4: e0bff917 ldw r2,-28(fp) - d8d8: 1005003a cmpeq r2,r2,zero - d8dc: 1000051e bne r2,zero,d8f4 - n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; - d8e0: 00820004 movi r2,2048 - d8e4: e0fffa17 ldw r3,-24(fp) - d8e8: 10c5c83a sub r2,r2,r3 - d8ec: e0bff815 stw r2,-32(fp) - d8f0: 00000406 br d904 - else - n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; - d8f4: 0081ffc4 movi r2,2047 - d8f8: e0fffa17 ldw r3,-24(fp) - d8fc: 10c5c83a sub r2,r2,r3 - d900: e0bff815 stw r2,-32(fp) - - if (n == 0) - d904: e0bff817 ldw r2,-32(fp) - d908: 1005003a cmpeq r2,r2,zero - d90c: 10001f1e bne r2,zero,d98c - break; - - if (n > count) - d910: e0fffd17 ldw r3,-12(fp) - d914: e0bff817 ldw r2,-32(fp) - d918: 1880022e bgeu r3,r2,d924 - n = count; - d91c: e0bffd17 ldw r2,-12(fp) - d920: e0bff815 stw r2,-32(fp) - - memcpy(sp->tx_buf + in, ptr, n); - d924: e0bffb17 ldw r2,-20(fp) - d928: 10c20e04 addi r3,r2,2104 - d92c: e0bffa17 ldw r2,-24(fp) - d930: 1885883a add r2,r3,r2 - d934: e0fffc17 ldw r3,-16(fp) - d938: 1009883a mov r4,r2 - d93c: 180b883a mov r5,r3 - d940: e1bff817 ldw r6,-32(fp) - d944: 0007f1c0 call 7f1c - ptr += n; - d948: e0fff817 ldw r3,-32(fp) - d94c: e0bffc17 ldw r2,-16(fp) - d950: 10c5883a add r2,r2,r3 - d954: e0bffc15 stw r2,-16(fp) - count -= n; - d958: e0fffd17 ldw r3,-12(fp) - d95c: e0bff817 ldw r2,-32(fp) - d960: 1885c83a sub r2,r3,r2 - d964: e0bffd15 stw r2,-12(fp) - - sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; - d968: e0fffa17 ldw r3,-24(fp) - d96c: e0bff817 ldw r2,-32(fp) - d970: 1885883a add r2,r3,r2 - d974: 10c1ffcc andi r3,r2,2047 - d978: e0bffb17 ldw r2,-20(fp) - d97c: 10c00c15 stw r3,48(r2) - ALT_SEM_PEND (sp->write_lock, 0); - - do - { - /* Copy as much as we can into the transmit buffer */ - while (count > 0) - d980: e0bffd17 ldw r2,-12(fp) - d984: 10800048 cmpgei r2,r2,1 - d988: 103fc31e bne r2,zero,d898 -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - d98c: 0005303a rdctl r2,status - d990: e0bff515 stw r2,-44(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - d994: e0fff517 ldw r3,-44(fp) - d998: 00bfff84 movi r2,-2 - d99c: 1884703a and r2,r3,r2 - d9a0: 1001703a wrctl status,r2 - - return context; - d9a4: e0bff517 ldw r2,-44(fp) - * to enable interrupts if there is no space left in the FIFO - * - * For now kick the interrupt routine every time to make it transmit - * the data - */ - context = alt_irq_disable_all(); - d9a8: e0bff715 stw r2,-36(fp) - sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; - d9ac: e0bffb17 ldw r2,-20(fp) - d9b0: 10800817 ldw r2,32(r2) - d9b4: 10c00094 ori r3,r2,2 - d9b8: e0bffb17 ldw r2,-20(fp) - d9bc: 10c00815 stw r3,32(r2) - IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); - d9c0: e0bffb17 ldw r2,-20(fp) - d9c4: 10800017 ldw r2,0(r2) - d9c8: 11000104 addi r4,r2,4 - d9cc: e0bffb17 ldw r2,-20(fp) - d9d0: 10800817 ldw r2,32(r2) - d9d4: 1007883a mov r3,r2 - d9d8: 2005883a mov r2,r4 - d9dc: 10c00035 stwio r3,0(r2) - d9e0: e0bff717 ldw r2,-36(fp) - d9e4: e0bff415 stw r2,-48(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - d9e8: e0bff417 ldw r2,-48(fp) - d9ec: 1001703a wrctl status,r2 - /* - * If there is any data left then either return now or block until - * some has been sent - */ - /* consider: test whether there is anything there while doing this and delay for at most 2s. */ - if (count > 0) - d9f0: e0bffd17 ldw r2,-12(fp) - d9f4: 10800050 cmplti r2,r2,1 - d9f8: 1000111e bne r2,zero,da40 - { - if (flags & O_NONBLOCK) - d9fc: e0bffe17 ldw r2,-8(fp) - da00: 1090000c andi r2,r2,16384 - da04: 1004c03a cmpne r2,r2,zero - da08: 1000101e bne r2,zero,da4c - /* - * No OS present: Always wait for data to be removed from buffer. Once - * the interrupt routine has removed some data then we will be able to - * insert some more. - */ - while (out == sp->tx_out && sp->host_inactive < sp->timeout) - da0c: e0bffb17 ldw r2,-20(fp) - da10: 10c00d17 ldw r3,52(r2) - da14: e0bff917 ldw r2,-28(fp) - da18: 1880051e bne r3,r2,da30 - da1c: e0bffb17 ldw r2,-20(fp) - da20: 10c00917 ldw r3,36(r2) - da24: e0bffb17 ldw r2,-20(fp) - da28: 10800117 ldw r2,4(r2) - da2c: 18bff736 bltu r3,r2,da0c - ; -#endif /* __ucosii__ */ - - if (out == sp->tx_out) - da30: e0bffb17 ldw r2,-20(fp) - da34: 10c00d17 ldw r3,52(r2) - da38: e0bff917 ldw r2,-28(fp) - da3c: 18800326 beq r3,r2,da4c - break; - } - } - while (count > 0); - da40: e0bffd17 ldw r2,-12(fp) - da44: 10800048 cmpgei r2,r2,1 - da48: 103fcd1e bne r2,zero,d980 - * Now that access to the circular buffer is complete, release the write - * semaphore so that other threads can access the buffer. - */ - ALT_SEM_POST (sp->write_lock); - - if (ptr != start) - da4c: e0fffc17 ldw r3,-16(fp) - da50: e0bff617 ldw r2,-40(fp) - da54: 18800526 beq r3,r2,da6c - return ptr - start; - da58: e0fffc17 ldw r3,-16(fp) - da5c: e0bff617 ldw r2,-40(fp) - da60: 1887c83a sub r3,r3,r2 - da64: e0ffff15 stw r3,-4(fp) - da68: 00000906 br da90 - else if (flags & O_NONBLOCK) - da6c: e0bffe17 ldw r2,-8(fp) - da70: 1090000c andi r2,r2,16384 - da74: 1005003a cmpeq r2,r2,zero - da78: 1000031e bne r2,zero,da88 - return -EWOULDBLOCK; - da7c: 00bffd44 movi r2,-11 - da80: e0bfff15 stw r2,-4(fp) - da84: 00000206 br da90 - sp->tx_out = sp->tx_in = 0; - return ptr - start + count; - } -#endif - else - return -EIO; /* Host not connected */ - da88: 00bffec4 movi r2,-5 - da8c: e0bfff15 stw r2,-4(fp) - da90: e0bfff17 ldw r2,-4(fp) -} - da94: e037883a mov sp,fp - da98: dfc00117 ldw ra,4(sp) - da9c: df000017 ldw fp,0(sp) - daa0: dec00204 addi sp,sp,8 - daa4: f800283a ret - -0000daa8 : - -/* --------------------------------------------------------------------- */ - -static void lcd_write_command(altera_avalon_lcd_16207_state* sp, - unsigned char command) -{ - daa8: defffa04 addi sp,sp,-24 - daac: dfc00515 stw ra,20(sp) - dab0: df000415 stw fp,16(sp) - dab4: df000404 addi fp,sp,16 - dab8: e13ffe15 stw r4,-8(fp) - dabc: e17fff05 stb r5,-4(fp) - unsigned int base = sp->base; - dac0: e0bffe17 ldw r2,-8(fp) - dac4: 10800017 ldw r2,0(r2) - dac8: e0bffd15 stw r2,-12(fp) - /* We impose a timeout on the driver in case the LCD panel isn't connected. - * The first time we call this function the timeout is approx 25ms - * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems - * with slower clocks, or debug builds, or slower memory will take longer. - */ - int i = 1000000; - dacc: 008003f4 movhi r2,15 - dad0: 10909004 addi r2,r2,16960 - dad4: e0bffc15 stw r2,-16(fp) - - /* Don't bother if the LCD panel didn't work before */ - if (sp->broken) - dad8: e0bffe17 ldw r2,-8(fp) - dadc: 10800803 ldbu r2,32(r2) - dae0: 10803fcc andi r2,r2,255 - dae4: 1080201c xori r2,r2,128 - dae8: 10bfe004 addi r2,r2,-128 - daec: 1004c03a cmpne r2,r2,zero - daf0: 1000161e bne r2,zero,db4c - return; - - /* Wait until LCD isn't busy. */ - while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) - daf4: 00000a06 br db20 - if (--i == 0) - daf8: e0bffc17 ldw r2,-16(fp) - dafc: 10bfffc4 addi r2,r2,-1 - db00: e0bffc15 stw r2,-16(fp) - db04: e0bffc17 ldw r2,-16(fp) - db08: 1004c03a cmpne r2,r2,zero - db0c: 1000041e bne r2,zero,db20 - { - sp->broken = 1; - db10: e0fffe17 ldw r3,-8(fp) - db14: 00800044 movi r2,1 - db18: 18800805 stb r2,32(r3) - return; - db1c: 00000b06 br db4c - /* Don't bother if the LCD panel didn't work before */ - if (sp->broken) - return; - - /* Wait until LCD isn't busy. */ - while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) - db20: e0bffd17 ldw r2,-12(fp) - db24: 10800104 addi r2,r2,4 - db28: 10800037 ldwio r2,0(r2) - db2c: 1080200c andi r2,r2,128 - db30: 1004c03a cmpne r2,r2,zero - db34: 103ff01e bne r2,zero,daf8 - } - - /* Despite what it says in the datasheet, the LCD isn't ready to accept - * a write immediately after it returns BUSY=0. Wait for 100us more. - */ - usleep(100); - db38: 01001904 movi r4,100 - db3c: 000cd800 call cd80 - - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, command); - db40: e0bffd17 ldw r2,-12(fp) - db44: e0ffff03 ldbu r3,-4(fp) - db48: 10c00035 stwio r3,0(r2) -} - db4c: e037883a mov sp,fp - db50: dfc00117 ldw ra,4(sp) - db54: df000017 ldw fp,0(sp) - db58: dec00204 addi sp,sp,8 - db5c: f800283a ret - -0000db60 : - -/* --------------------------------------------------------------------- */ - -static void lcd_write_data(altera_avalon_lcd_16207_state* sp, - unsigned char data) -{ - db60: defffa04 addi sp,sp,-24 - db64: dfc00515 stw ra,20(sp) - db68: df000415 stw fp,16(sp) - db6c: df000404 addi fp,sp,16 - db70: e13ffe15 stw r4,-8(fp) - db74: e17fff05 stb r5,-4(fp) - unsigned int base = sp->base; - db78: e0bffe17 ldw r2,-8(fp) - db7c: 10800017 ldw r2,0(r2) - db80: e0bffd15 stw r2,-12(fp) - /* We impose a timeout on the driver in case the LCD panel isn't connected. - * The first time we call this function the timeout is approx 25ms - * (assuming 5 cycles per loop and a 200MHz clock). Obviously systems - * with slower clocks, or debug builds, or slower memory will take longer. - */ - int i = 1000000; - db84: 008003f4 movhi r2,15 - db88: 10909004 addi r2,r2,16960 - db8c: e0bffc15 stw r2,-16(fp) - - /* Don't bother if the LCD panel didn't work before */ - if (sp->broken) - db90: e0bffe17 ldw r2,-8(fp) - db94: 10800803 ldbu r2,32(r2) - db98: 10803fcc andi r2,r2,255 - db9c: 1080201c xori r2,r2,128 - dba0: 10bfe004 addi r2,r2,-128 - dba4: 1004c03a cmpne r2,r2,zero - dba8: 10001d1e bne r2,zero,dc20 - return; - - /* Wait until LCD isn't busy. */ - while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) - dbac: 00000a06 br dbd8 - if (--i == 0) - dbb0: e0bffc17 ldw r2,-16(fp) - dbb4: 10bfffc4 addi r2,r2,-1 - dbb8: e0bffc15 stw r2,-16(fp) - dbbc: e0bffc17 ldw r2,-16(fp) - dbc0: 1004c03a cmpne r2,r2,zero - dbc4: 1000041e bne r2,zero,dbd8 - { - sp->broken = 1; - dbc8: e0fffe17 ldw r3,-8(fp) - dbcc: 00800044 movi r2,1 - dbd0: 18800805 stb r2,32(r3) - return; - dbd4: 00001206 br dc20 - /* Don't bother if the LCD panel didn't work before */ - if (sp->broken) - return; - - /* Wait until LCD isn't busy. */ - while (IORD_ALTERA_AVALON_LCD_16207_STATUS(base) & ALTERA_AVALON_LCD_16207_STATUS_BUSY_MSK) - dbd8: e0bffd17 ldw r2,-12(fp) - dbdc: 10800104 addi r2,r2,4 - dbe0: 10800037 ldwio r2,0(r2) - dbe4: 1080200c andi r2,r2,128 - dbe8: 1004c03a cmpne r2,r2,zero - dbec: 103ff01e bne r2,zero,dbb0 - } - - /* Despite what it says in the datasheet, the LCD isn't ready to accept - * a write immediately after it returns BUSY=0. Wait for 100us more. - */ - usleep(100); - dbf0: 01001904 movi r4,100 - dbf4: 000cd800 call cd80 - - IOWR_ALTERA_AVALON_LCD_16207_DATA(base, data); - dbf8: e0bffd17 ldw r2,-12(fp) - dbfc: 10800204 addi r2,r2,8 - dc00: e0ffff03 ldbu r3,-4(fp) - dc04: 10c00035 stwio r3,0(r2) - - sp->address++; - dc08: e0bffe17 ldw r2,-8(fp) - dc0c: 108008c3 ldbu r2,35(r2) - dc10: 10800044 addi r2,r2,1 - dc14: 1007883a mov r3,r2 - dc18: e0bffe17 ldw r2,-8(fp) - dc1c: 10c008c5 stb r3,35(r2) -} - dc20: e037883a mov sp,fp - dc24: dfc00117 ldw ra,4(sp) - dc28: df000017 ldw fp,0(sp) - dc2c: dec00204 addi sp,sp,8 - dc30: f800283a ret - -0000dc34 : - -/* --------------------------------------------------------------------- */ - -static void lcd_clear_screen(altera_avalon_lcd_16207_state* sp) -{ - dc34: defffb04 addi sp,sp,-20 - dc38: dfc00415 stw ra,16(sp) - dc3c: df000315 stw fp,12(sp) - dc40: dc000215 stw r16,8(sp) - dc44: df000204 addi fp,sp,8 - dc48: e13fff15 stw r4,-4(fp) - int y; - - lcd_write_command(sp, LCD_CMD_CLEAR); - dc4c: e13fff17 ldw r4,-4(fp) - dc50: 01400044 movi r5,1 - dc54: 000daa80 call daa8 - - sp->x = 0; - dc58: e0bfff17 ldw r2,-4(fp) - dc5c: 10000845 stb zero,33(r2) - sp->y = 0; - dc60: e0bfff17 ldw r2,-4(fp) - dc64: 10000885 stb zero,34(r2) - sp->address = 0; - dc68: e0bfff17 ldw r2,-4(fp) - dc6c: 100008c5 stb zero,35(r2) - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - dc70: e03ffe15 stw zero,-8(fp) - dc74: 00001c06 br dce8 - { - memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); - dc78: e13ffe17 ldw r4,-8(fp) - dc7c: 014018c4 movi r5,99 - dc80: 0002b2c0 call 2b2c <__mulsi3> - dc84: 10c01004 addi r3,r2,64 - dc88: e0bfff17 ldw r2,-4(fp) - dc8c: 1889883a add r4,r3,r2 - dc90: 01400804 movi r5,32 - dc94: 01801444 movi r6,81 - dc98: 000809c0 call 809c - memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); - dc9c: e13ffe17 ldw r4,-8(fp) - dca0: 014018c4 movi r5,99 - dca4: 0002b2c0 call 2b2c <__mulsi3> - dca8: 10c00c04 addi r3,r2,48 - dcac: e0bfff17 ldw r2,-4(fp) - dcb0: 1889883a add r4,r3,r2 - dcb4: 01400804 movi r5,32 - dcb8: 01800404 movi r6,16 - dcbc: 000809c0 call 809c - sp->line[y].width = 0; - dcc0: e13ffe17 ldw r4,-8(fp) - dcc4: e43fff17 ldw r16,-4(fp) - dcc8: 014018c4 movi r5,99 - dccc: 0002b2c0 call 2b2c <__mulsi3> - dcd0: 1405883a add r2,r2,r16 - dcd4: 10802404 addi r2,r2,144 - dcd8: 10000045 stb zero,1(r2) - - sp->x = 0; - sp->y = 0; - sp->address = 0; - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - dcdc: e0bffe17 ldw r2,-8(fp) - dce0: 10800044 addi r2,r2,1 - dce4: e0bffe15 stw r2,-8(fp) - dce8: e0bffe17 ldw r2,-8(fp) - dcec: 10800090 cmplti r2,r2,2 - dcf0: 103fe11e bne r2,zero,dc78 - { - memset(sp->line[y].data, ' ', sizeof(sp->line[0].data)); - memset(sp->line[y].visible, ' ', sizeof(sp->line[0].visible)); - sp->line[y].width = 0; - } -} - dcf4: e037883a mov sp,fp - dcf8: dfc00217 ldw ra,8(sp) - dcfc: df000117 ldw fp,4(sp) - dd00: dc000017 ldw r16,0(sp) - dd04: dec00304 addi sp,sp,12 - dd08: f800283a ret - -0000dd0c : - -/* --------------------------------------------------------------------- */ - -static void lcd_repaint_screen(altera_avalon_lcd_16207_state* sp) -{ - dd0c: defff404 addi sp,sp,-48 - dd10: dfc00b15 stw ra,44(sp) - dd14: df000a15 stw fp,40(sp) - dd18: dc800915 stw r18,36(sp) - dd1c: dc400815 stw r17,32(sp) - dd20: dc000715 stw r16,28(sp) - dd24: df000704 addi fp,sp,28 - dd28: e13fff15 stw r4,-4(fp) - /* scrollpos controls how much the lines have scrolled round. The speed - * each line scrolls at is controlled by its speed variable - while - * scrolline lines will wrap at the position set by width - */ - - int scrollpos = sp->scrollpos; - dd2c: e0bfff17 ldw r2,-4(fp) - dd30: 10800943 ldbu r2,37(r2) - dd34: 10803fcc andi r2,r2,255 - dd38: 1080201c xori r2,r2,128 - dd3c: 10bfe004 addi r2,r2,-128 - dd40: e0bffc15 stw r2,-16(fp) - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - dd44: e03ffe15 stw zero,-8(fp) - dd48: 00006a06 br def4 - { - int width = sp->line[y].width; - dd4c: e13ffe17 ldw r4,-8(fp) - dd50: e43fff17 ldw r16,-4(fp) - dd54: 014018c4 movi r5,99 - dd58: 0002b2c0 call 2b2c <__mulsi3> - dd5c: 1405883a add r2,r2,r16 - dd60: 10802404 addi r2,r2,144 - dd64: 10800043 ldbu r2,1(r2) - dd68: 10803fcc andi r2,r2,255 - dd6c: 1080201c xori r2,r2,128 - dd70: 10bfe004 addi r2,r2,-128 - dd74: e0bffb15 stw r2,-20(fp) - int offset = (scrollpos * sp->line[y].speed) >> 8; - dd78: e13ffe17 ldw r4,-8(fp) - dd7c: e43fff17 ldw r16,-4(fp) - dd80: 014018c4 movi r5,99 - dd84: 0002b2c0 call 2b2c <__mulsi3> - dd88: 1405883a add r2,r2,r16 - dd8c: 10802404 addi r2,r2,144 - dd90: 10800083 ldbu r2,2(r2) - dd94: 11003fcc andi r4,r2,255 - dd98: e17ffc17 ldw r5,-16(fp) - dd9c: 0002b2c0 call 2b2c <__mulsi3> - dda0: 1005d23a srai r2,r2,8 - dda4: e0bffa15 stw r2,-24(fp) - if (offset >= width) - dda8: e0fffa17 ldw r3,-24(fp) - ddac: e0bffb17 ldw r2,-20(fp) - ddb0: 18800116 blt r3,r2,ddb8 - offset = 0; - ddb4: e03ffa15 stw zero,-24(fp) - - for (x = 0 ; x < ALT_LCD_WIDTH ; x++) - ddb8: e03ffd15 stw zero,-12(fp) - ddbc: 00004706 br dedc - { - char c = sp->line[y].data[(x + offset) % width]; - ddc0: e47ffe17 ldw r17,-8(fp) - ddc4: e0fffd17 ldw r3,-12(fp) - ddc8: e0bffa17 ldw r2,-24(fp) - ddcc: 1889883a add r4,r3,r2 - ddd0: e17ffb17 ldw r5,-20(fp) - ddd4: 0002abc0 call 2abc <__modsi3> - ddd8: 1025883a mov r18,r2 - dddc: e43fff17 ldw r16,-4(fp) - dde0: 8809883a mov r4,r17 - dde4: 014018c4 movi r5,99 - dde8: 0002b2c0 call 2b2c <__mulsi3> - ddec: 1405883a add r2,r2,r16 - ddf0: 1485883a add r2,r2,r18 - ddf4: 10801004 addi r2,r2,64 - ddf8: 10800003 ldbu r2,0(r2) - ddfc: e0bff945 stb r2,-27(fp) - - /* Writing data takes 40us, so don't do it unless required */ - if (sp->line[y].visible[x] != c) - de00: e13ffe17 ldw r4,-8(fp) - de04: e47ffd17 ldw r17,-12(fp) - de08: e43fff17 ldw r16,-4(fp) - de0c: 014018c4 movi r5,99 - de10: 0002b2c0 call 2b2c <__mulsi3> - de14: 1405883a add r2,r2,r16 - de18: 1445883a add r2,r2,r17 - de1c: 10800c04 addi r2,r2,48 - de20: 10800003 ldbu r2,0(r2) - de24: 10c03fcc andi r3,r2,255 - de28: 18c0201c xori r3,r3,128 - de2c: 18ffe004 addi r3,r3,-128 - de30: e0bff947 ldb r2,-27(fp) - de34: 18802626 beq r3,r2,ded0 - { - unsigned char address = x + colstart[y]; - de38: e0fffe17 ldw r3,-8(fp) - de3c: d0a00f04 addi r2,gp,-32708 - de40: 1885883a add r2,r3,r2 - de44: 10800003 ldbu r2,0(r2) - de48: 1007883a mov r3,r2 - de4c: e0bffd17 ldw r2,-12(fp) - de50: 1885883a add r2,r3,r2 - de54: e0bff905 stb r2,-28(fp) - - if (address != sp->address) - de58: e0fff903 ldbu r3,-28(fp) - de5c: e0bfff17 ldw r2,-4(fp) - de60: 108008c3 ldbu r2,35(r2) - de64: 10803fcc andi r2,r2,255 - de68: 1080201c xori r2,r2,128 - de6c: 10bfe004 addi r2,r2,-128 - de70: 18800926 beq r3,r2,de98 - { - lcd_write_command(sp, LCD_CMD_WRITE_DATA | address); - de74: e0fff903 ldbu r3,-28(fp) - de78: 00bfe004 movi r2,-128 - de7c: 1884b03a or r2,r3,r2 - de80: 11403fcc andi r5,r2,255 - de84: e13fff17 ldw r4,-4(fp) - de88: 000daa80 call daa8 - sp->address = address; - de8c: e0fff903 ldbu r3,-28(fp) - de90: e0bfff17 ldw r2,-4(fp) - de94: 10c008c5 stb r3,35(r2) - } - - lcd_write_data(sp, c); - de98: e0bff943 ldbu r2,-27(fp) - de9c: 11403fcc andi r5,r2,255 - dea0: e13fff17 ldw r4,-4(fp) - dea4: 000db600 call db60 - sp->line[y].visible[x] = c; - dea8: e13ffe17 ldw r4,-8(fp) - deac: e47ffd17 ldw r17,-12(fp) - deb0: e43fff17 ldw r16,-4(fp) - deb4: 014018c4 movi r5,99 - deb8: 0002b2c0 call 2b2c <__mulsi3> - debc: 1405883a add r2,r2,r16 - dec0: 1445883a add r2,r2,r17 - dec4: 10c00c04 addi r3,r2,48 - dec8: e0bff943 ldbu r2,-27(fp) - decc: 18800005 stb r2,0(r3) - int width = sp->line[y].width; - int offset = (scrollpos * sp->line[y].speed) >> 8; - if (offset >= width) - offset = 0; - - for (x = 0 ; x < ALT_LCD_WIDTH ; x++) - ded0: e0bffd17 ldw r2,-12(fp) - ded4: 10800044 addi r2,r2,1 - ded8: e0bffd15 stw r2,-12(fp) - dedc: e0bffd17 ldw r2,-12(fp) - dee0: 10800410 cmplti r2,r2,16 - dee4: 103fb61e bne r2,zero,ddc0 - * scrolline lines will wrap at the position set by width - */ - - int scrollpos = sp->scrollpos; - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - dee8: e0bffe17 ldw r2,-8(fp) - deec: 10800044 addi r2,r2,1 - def0: e0bffe15 stw r2,-8(fp) - def4: e0bffe17 ldw r2,-8(fp) - def8: 10800090 cmplti r2,r2,2 - defc: 103f931e bne r2,zero,dd4c - lcd_write_data(sp, c); - sp->line[y].visible[x] = c; - } - } - } -} - df00: e037883a mov sp,fp - df04: dfc00417 ldw ra,16(sp) - df08: df000317 ldw fp,12(sp) - df0c: dc800217 ldw r18,8(sp) - df10: dc400117 ldw r17,4(sp) - df14: dc000017 ldw r16,0(sp) - df18: dec00504 addi sp,sp,20 - df1c: f800283a ret - -0000df20 : - -/* --------------------------------------------------------------------- */ - -static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) -{ - df20: defffb04 addi sp,sp,-20 - df24: dfc00415 stw ra,16(sp) - df28: df000315 stw fp,12(sp) - df2c: dc000215 stw r16,8(sp) - df30: df000204 addi fp,sp,8 - df34: e13fff15 stw r4,-4(fp) - int y; - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - df38: e03ffe15 stw zero,-8(fp) - df3c: 00002106 br dfc4 - { - if (y < ALT_LCD_HEIGHT-1) - df40: e0bffe17 ldw r2,-8(fp) - df44: 10800048 cmpgei r2,r2,1 - df48: 1000121e bne r2,zero,df94 - memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); - df4c: e13ffe17 ldw r4,-8(fp) - df50: 014018c4 movi r5,99 - df54: 0002b2c0 call 2b2c <__mulsi3> - df58: 10c01004 addi r3,r2,64 - df5c: e0bfff17 ldw r2,-4(fp) - df60: 18a1883a add r16,r3,r2 - df64: e0bffe17 ldw r2,-8(fp) - df68: 11000044 addi r4,r2,1 - df6c: 014018c4 movi r5,99 - df70: 0002b2c0 call 2b2c <__mulsi3> - df74: 10c01004 addi r3,r2,64 - df78: e0bfff17 ldw r2,-4(fp) - df7c: 1885883a add r2,r3,r2 - df80: 8009883a mov r4,r16 - df84: 100b883a mov r5,r2 - df88: 01801404 movi r6,80 - df8c: 0007f1c0 call 7f1c - df90: 00000906 br dfb8 - else - memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); - df94: e13ffe17 ldw r4,-8(fp) - df98: 014018c4 movi r5,99 - df9c: 0002b2c0 call 2b2c <__mulsi3> - dfa0: 10c01004 addi r3,r2,64 - dfa4: e0bfff17 ldw r2,-4(fp) - dfa8: 1889883a add r4,r3,r2 - dfac: 01400804 movi r5,32 - dfb0: 01801404 movi r6,80 - dfb4: 000809c0 call 809c - -static void lcd_scroll_up(altera_avalon_lcd_16207_state* sp) -{ - int y; - - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - dfb8: e0bffe17 ldw r2,-8(fp) - dfbc: 10800044 addi r2,r2,1 - dfc0: e0bffe15 stw r2,-8(fp) - dfc4: e0bffe17 ldw r2,-8(fp) - dfc8: 10800090 cmplti r2,r2,2 - dfcc: 103fdc1e bne r2,zero,df40 - memcpy(sp->line[y].data, sp->line[y+1].data, ALT_LCD_VIRTUAL_WIDTH); - else - memset(sp->line[y].data, ' ', ALT_LCD_VIRTUAL_WIDTH); - } - - sp->y--; - dfd0: e0bfff17 ldw r2,-4(fp) - dfd4: 10800883 ldbu r2,34(r2) - dfd8: 10bfffc4 addi r2,r2,-1 - dfdc: 1007883a mov r3,r2 - dfe0: e0bfff17 ldw r2,-4(fp) - dfe4: 10c00885 stb r3,34(r2) -} - dfe8: e037883a mov sp,fp - dfec: dfc00217 ldw ra,8(sp) - dff0: df000117 ldw fp,4(sp) - dff4: dc000017 ldw r16,0(sp) - dff8: dec00304 addi sp,sp,12 - dffc: f800283a ret - -0000e000 : - -/* --------------------------------------------------------------------- */ - -static void lcd_handle_escape(altera_avalon_lcd_16207_state* sp, char c) -{ - e000: defff804 addi sp,sp,-32 - e004: dfc00715 stw ra,28(sp) - e008: df000615 stw fp,24(sp) - e00c: df000604 addi fp,sp,24 - e010: e13ffd15 stw r4,-12(fp) - e014: e17ffe05 stb r5,-8(fp) - int parm1 = 0, parm2 = 0; - e018: e03ffc15 stw zero,-16(fp) - e01c: e03ffb15 stw zero,-20(fp) - - if (sp->escape[0] == '[') - e020: e0bffd17 ldw r2,-12(fp) - e024: 10800a03 ldbu r2,40(r2) - e028: 10803fcc andi r2,r2,255 - e02c: 1080201c xori r2,r2,128 - e030: 10bfe004 addi r2,r2,-128 - e034: 108016d8 cmpnei r2,r2,91 - e038: 10004d1e bne r2,zero,e170 - { - char * ptr = sp->escape+1; - e03c: e0bffd17 ldw r2,-12(fp) - e040: 10800a04 addi r2,r2,40 - e044: 10800044 addi r2,r2,1 - e048: e0bffa15 stw r2,-24(fp) - while (isdigit(*ptr)) - e04c: 00000f06 br e08c - parm1 = (parm1 * 10) + (*ptr++ - '0'); - e050: e13ffc17 ldw r4,-16(fp) - e054: 01400284 movi r5,10 - e058: 0002b2c0 call 2b2c <__mulsi3> - e05c: 1007883a mov r3,r2 - e060: e0bffa17 ldw r2,-24(fp) - e064: 10800003 ldbu r2,0(r2) - e068: 10803fcc andi r2,r2,255 - e06c: 1080201c xori r2,r2,128 - e070: 10bfe004 addi r2,r2,-128 - e074: 1885883a add r2,r3,r2 - e078: 10bff404 addi r2,r2,-48 - e07c: e0bffc15 stw r2,-16(fp) - e080: e0bffa17 ldw r2,-24(fp) - e084: 10800044 addi r2,r2,1 - e088: e0bffa15 stw r2,-24(fp) - int parm1 = 0, parm2 = 0; - - if (sp->escape[0] == '[') - { - char * ptr = sp->escape+1; - while (isdigit(*ptr)) - e08c: e0bffa17 ldw r2,-24(fp) - e090: 10800003 ldbu r2,0(r2) - e094: 10803fcc andi r2,r2,255 - e098: 1080201c xori r2,r2,128 - e09c: 10bfe004 addi r2,r2,-128 - e0a0: 1007883a mov r3,r2 - e0a4: 00800074 movhi r2,1 - e0a8: 10883f04 addi r2,r2,8444 - e0ac: 10800017 ldw r2,0(r2) - e0b0: 1885883a add r2,r3,r2 - e0b4: 10800003 ldbu r2,0(r2) - e0b8: 10803fcc andi r2,r2,255 - e0bc: 1080010c andi r2,r2,4 - e0c0: 1004c03a cmpne r2,r2,zero - e0c4: 103fe21e bne r2,zero,e050 - parm1 = (parm1 * 10) + (*ptr++ - '0'); - - if (*ptr == ';') - e0c8: e0bffa17 ldw r2,-24(fp) - e0cc: 10800003 ldbu r2,0(r2) - e0d0: 10803fcc andi r2,r2,255 - e0d4: 1080201c xori r2,r2,128 - e0d8: 10bfe004 addi r2,r2,-128 - e0dc: 10800ed8 cmpnei r2,r2,59 - e0e0: 1000251e bne r2,zero,e178 - { - ptr++; - e0e4: e0bffa17 ldw r2,-24(fp) - e0e8: 10800044 addi r2,r2,1 - e0ec: e0bffa15 stw r2,-24(fp) - while (isdigit(*ptr)) - e0f0: 00000f06 br e130 - parm2 = (parm2 * 10) + (*ptr++ - '0'); - e0f4: e13ffb17 ldw r4,-20(fp) - e0f8: 01400284 movi r5,10 - e0fc: 0002b2c0 call 2b2c <__mulsi3> - e100: 1007883a mov r3,r2 - e104: e0bffa17 ldw r2,-24(fp) - e108: 10800003 ldbu r2,0(r2) - e10c: 10803fcc andi r2,r2,255 - e110: 1080201c xori r2,r2,128 - e114: 10bfe004 addi r2,r2,-128 - e118: 1885883a add r2,r3,r2 - e11c: 10bff404 addi r2,r2,-48 - e120: e0bffb15 stw r2,-20(fp) - e124: e0bffa17 ldw r2,-24(fp) - e128: 10800044 addi r2,r2,1 - e12c: e0bffa15 stw r2,-24(fp) - parm1 = (parm1 * 10) + (*ptr++ - '0'); - - if (*ptr == ';') - { - ptr++; - while (isdigit(*ptr)) - e130: e0bffa17 ldw r2,-24(fp) - e134: 10800003 ldbu r2,0(r2) - e138: 10803fcc andi r2,r2,255 - e13c: 1080201c xori r2,r2,128 - e140: 10bfe004 addi r2,r2,-128 - e144: 1007883a mov r3,r2 - e148: 00800074 movhi r2,1 - e14c: 10883f04 addi r2,r2,8444 - e150: 10800017 ldw r2,0(r2) - e154: 1885883a add r2,r3,r2 - e158: 10800003 ldbu r2,0(r2) - e15c: 10803fcc andi r2,r2,255 - e160: 1080010c andi r2,r2,4 - e164: 1004c03a cmpne r2,r2,zero - e168: 103fe21e bne r2,zero,e0f4 - e16c: 00000206 br e178 - parm2 = (parm2 * 10) + (*ptr++ - '0'); - } - } - else - parm1 = -1; - e170: 00bfffc4 movi r2,-1 - e174: e0bffc15 stw r2,-16(fp) - - switch (c) - e178: e0bffe07 ldb r2,-8(fp) - e17c: e0bfff15 stw r2,-4(fp) - e180: e0ffff17 ldw r3,-4(fp) - e184: 188012a0 cmpeqi r2,r3,74 - e188: 10002f1e bne r2,zero,e248 - e18c: e0ffff17 ldw r3,-4(fp) - e190: 188012c8 cmpgei r2,r3,75 - e194: 1000041e bne r2,zero,e1a8 - e198: e0ffff17 ldw r3,-4(fp) - e19c: 18801220 cmpeqi r2,r3,72 - e1a0: 1000081e bne r2,zero,e1c4 - e1a4: 00004a06 br e2d0 - e1a8: e0ffff17 ldw r3,-4(fp) - e1ac: 188012e0 cmpeqi r2,r3,75 - e1b0: 10002b1e bne r2,zero,e260 - e1b4: e0ffff17 ldw r3,-4(fp) - e1b8: 188019a0 cmpeqi r2,r3,102 - e1bc: 1000011e bne r2,zero,e1c4 - e1c0: 00004306 br e2d0 - { - case 'H': /* ESC '[' ';' 'H' : Move cursor to location */ - case 'f': /* Same as above */ - if (parm2 > 0) - e1c4: e0bffb17 ldw r2,-20(fp) - e1c8: 10800050 cmplti r2,r2,1 - e1cc: 1000051e bne r2,zero,e1e4 - sp->x = parm2 - 1; - e1d0: e0bffb17 ldw r2,-20(fp) - e1d4: 10bfffc4 addi r2,r2,-1 - e1d8: 1007883a mov r3,r2 - e1dc: e0bffd17 ldw r2,-12(fp) - e1e0: 10c00845 stb r3,33(r2) - if (parm1 > 0) - e1e4: e0bffc17 ldw r2,-16(fp) - e1e8: 10800050 cmplti r2,r2,1 - e1ec: 1000381e bne r2,zero,e2d0 - { - sp->y = parm1 - 1; - e1f0: e0bffc17 ldw r2,-16(fp) - e1f4: 10bfffc4 addi r2,r2,-1 - e1f8: 1007883a mov r3,r2 - e1fc: e0bffd17 ldw r2,-12(fp) - e200: 10c00885 stb r3,34(r2) - if (sp->y > ALT_LCD_HEIGHT * 2) - e204: e0bffd17 ldw r2,-12(fp) - e208: 10800883 ldbu r2,34(r2) - e20c: 10803fcc andi r2,r2,255 - e210: 10800170 cmpltui r2,r2,5 - e214: 1000061e bne r2,zero,e230 - sp->y = ALT_LCD_HEIGHT * 2; - e218: e0fffd17 ldw r3,-12(fp) - e21c: 00800104 movi r2,4 - e220: 18800885 stb r2,34(r3) - while (sp->y > ALT_LCD_HEIGHT) - e224: 00000206 br e230 - lcd_scroll_up(sp); - e228: e13ffd17 ldw r4,-12(fp) - e22c: 000df200 call df20 - if (parm1 > 0) - { - sp->y = parm1 - 1; - if (sp->y > ALT_LCD_HEIGHT * 2) - sp->y = ALT_LCD_HEIGHT * 2; - while (sp->y > ALT_LCD_HEIGHT) - e230: e0bffd17 ldw r2,-12(fp) - e234: 10800883 ldbu r2,34(r2) - e238: 10803fcc andi r2,r2,255 - e23c: 108000e8 cmpgeui r2,r2,3 - e240: 103ff91e bne r2,zero,e228 - lcd_scroll_up(sp); - } - break; - e244: 00002206 br e2d0 - /* ESC J is clear to beginning of line [unimplemented] - * ESC [ 0 J is clear to bottom of screen [unimplemented] - * ESC [ 1 J is clear to beginning of screen [unimplemented] - * ESC [ 2 J is clear screen - */ - if (parm1 == 2) - e248: e0bffc17 ldw r2,-16(fp) - e24c: 10800098 cmpnei r2,r2,2 - e250: 10001f1e bne r2,zero,e2d0 - lcd_clear_screen(sp); - e254: e13ffd17 ldw r4,-12(fp) - e258: 000dc340 call dc34 - break; - e25c: 00001c06 br e2d0 - /* ESC K is clear to end of line - * ESC [ 0 K is clear to end of line - * ESC [ 1 K is clear to beginning of line [unimplemented] - * ESC [ 2 K is clear line [unimplemented] - */ - if (parm1 < 1) - e260: e0bffc17 ldw r2,-16(fp) - e264: 10800048 cmpgei r2,r2,1 - e268: 1000191e bne r2,zero,e2d0 - { - if (sp->x < ALT_LCD_VIRTUAL_WIDTH) - e26c: e0bffd17 ldw r2,-12(fp) - e270: 10800843 ldbu r2,33(r2) - e274: 10803fcc andi r2,r2,255 - e278: 10801428 cmpgeui r2,r2,80 - e27c: 1000141e bne r2,zero,e2d0 - memset(sp->line[sp->y].data + sp->x, ' ', ALT_LCD_VIRTUAL_WIDTH - sp->x); - e280: e0bffd17 ldw r2,-12(fp) - e284: 10800883 ldbu r2,34(r2) - e288: 11003fcc andi r4,r2,255 - e28c: 014018c4 movi r5,99 - e290: 0002b2c0 call 2b2c <__mulsi3> - e294: 10c01004 addi r3,r2,64 - e298: e0bffd17 ldw r2,-12(fp) - e29c: 1887883a add r3,r3,r2 - e2a0: e0bffd17 ldw r2,-12(fp) - e2a4: 10800843 ldbu r2,33(r2) - e2a8: 10803fcc andi r2,r2,255 - e2ac: 1889883a add r4,r3,r2 - e2b0: e0bffd17 ldw r2,-12(fp) - e2b4: 10800843 ldbu r2,33(r2) - e2b8: 10c03fcc andi r3,r2,255 - e2bc: 00801404 movi r2,80 - e2c0: 10c5c83a sub r2,r2,r3 - e2c4: 100d883a mov r6,r2 - e2c8: 01400804 movi r5,32 - e2cc: 000809c0 call 809c - } - break; - } -} - e2d0: e037883a mov sp,fp - e2d4: dfc00117 ldw ra,4(sp) - e2d8: df000017 ldw fp,0(sp) - e2dc: dec00204 addi sp,sp,8 - e2e0: f800283a ret - -0000e2e4 : - -/* --------------------------------------------------------------------- */ - -int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, - const char* ptr, int len, int flags) -{ - e2e4: defff004 addi sp,sp,-64 - e2e8: dfc00f15 stw ra,60(sp) - e2ec: df000e15 stw fp,56(sp) - e2f0: dc800d15 stw r18,52(sp) - e2f4: dc400c15 stw r17,48(sp) - e2f8: dc000b15 stw r16,44(sp) - e2fc: df000b04 addi fp,sp,44 - e300: e13ffc15 stw r4,-16(fp) - e304: e17ffd15 stw r5,-12(fp) - e308: e1bffe15 stw r6,-8(fp) - e30c: e1ffff15 stw r7,-4(fp) - const char* end = ptr + len; - e310: e0bffe17 ldw r2,-8(fp) - e314: 1007883a mov r3,r2 - e318: e0bffd17 ldw r2,-12(fp) - e31c: 10c5883a add r2,r2,r3 - e320: e0bffb15 stw r2,-20(fp) - - ALT_SEM_PEND (sp->write_lock, 0); - - /* Tell the routine which is called off the timer interrupt that the - * foreground routines are active so it must not repaint the display. */ - sp->active = 1; - e324: e0fffc17 ldw r3,-16(fp) - e328: 00800044 movi r2,1 - e32c: 188009c5 stb r2,39(r3) - - for ( ; ptr < end ; ptr++) - e330: 0000a306 br e5c0 - { - char c = *ptr; - e334: e0bffd17 ldw r2,-12(fp) - e338: 10800003 ldbu r2,0(r2) - e33c: e0bff805 stb r2,-32(fp) - - if (sp->esccount >= 0) - e340: e0bffc17 ldw r2,-16(fp) - e344: 10800903 ldbu r2,36(r2) - e348: 10803fcc andi r2,r2,255 - e34c: 1080201c xori r2,r2,128 - e350: 10bfe004 addi r2,r2,-128 - e354: 1004803a cmplt r2,r2,zero - e358: 10003b1e bne r2,zero,e448 - { - unsigned int esccount = sp->esccount; - e35c: e0bffc17 ldw r2,-16(fp) - e360: 10800903 ldbu r2,36(r2) - e364: 10803fcc andi r2,r2,255 - e368: 1080201c xori r2,r2,128 - e36c: 10bfe004 addi r2,r2,-128 - e370: e0bff715 stw r2,-36(fp) - - /* Single character escape sequences can end with any character - * Multi character escape sequences start with '[' and contain - * digits and semicolons before terminating - */ - if ((esccount == 0 && c != '[') || - e374: e0bff717 ldw r2,-36(fp) - e378: 1004c03a cmpne r2,r2,zero - e37c: 1000031e bne r2,zero,e38c - e380: e0bff807 ldb r2,-32(fp) - e384: 108016d8 cmpnei r2,r2,91 - e388: 1000111e bne r2,zero,e3d0 - e38c: e0bff717 ldw r2,-36(fp) - e390: 1005003a cmpeq r2,r2,zero - e394: 10001a1e bne r2,zero,e400 - e398: e0bff807 ldb r2,-32(fp) - e39c: 1007883a mov r3,r2 - e3a0: 00800074 movhi r2,1 - e3a4: 10883f04 addi r2,r2,8444 - e3a8: 10800017 ldw r2,0(r2) - e3ac: 1885883a add r2,r3,r2 - e3b0: 10800003 ldbu r2,0(r2) - e3b4: 10803fcc andi r2,r2,255 - e3b8: 1080010c andi r2,r2,4 - e3bc: 1004c03a cmpne r2,r2,zero - e3c0: 10000f1e bne r2,zero,e400 - e3c4: e0bff807 ldb r2,-32(fp) - e3c8: 10800ee0 cmpeqi r2,r2,59 - e3cc: 10000c1e bne r2,zero,e400 - (esccount > 0 && !isdigit(c) && c != ';')) - { - sp->escape[esccount] = 0; - e3d0: e0fff717 ldw r3,-36(fp) - e3d4: e0bffc17 ldw r2,-16(fp) - e3d8: 1885883a add r2,r3,r2 - e3dc: 10800a04 addi r2,r2,40 - e3e0: 10000005 stb zero,0(r2) - - lcd_handle_escape(sp, c); - e3e4: e17ff807 ldb r5,-32(fp) - e3e8: e13ffc17 ldw r4,-16(fp) - e3ec: 000e0000 call e000 - - sp->esccount = -1; - e3f0: e0fffc17 ldw r3,-16(fp) - e3f4: 00bfffc4 movi r2,-1 - e3f8: 18800905 stb r2,36(r3) - - /* Single character escape sequences can end with any character - * Multi character escape sequences start with '[' and contain - * digits and semicolons before terminating - */ - if ((esccount == 0 && c != '[') || - e3fc: 00006d06 br e5b4 - - lcd_handle_escape(sp, c); - - sp->esccount = -1; - } - else if (sp->esccount < sizeof(sp->escape)-1) - e400: e0bffc17 ldw r2,-16(fp) - e404: 10800903 ldbu r2,36(r2) - e408: 10803fcc andi r2,r2,255 - e40c: 108001e8 cmpgeui r2,r2,7 - e410: 1000681e bne r2,zero,e5b4 - { - sp->escape[esccount] = c; - e414: e0fff717 ldw r3,-36(fp) - e418: e0bffc17 ldw r2,-16(fp) - e41c: 1885883a add r2,r3,r2 - e420: 10c00a04 addi r3,r2,40 - e424: e0bff803 ldbu r2,-32(fp) - e428: 18800005 stb r2,0(r3) - sp->esccount++; - e42c: e0bffc17 ldw r2,-16(fp) - e430: 10800903 ldbu r2,36(r2) - e434: 10800044 addi r2,r2,1 - e438: 1007883a mov r3,r2 - e43c: e0bffc17 ldw r2,-16(fp) - e440: 10c00905 stb r3,36(r2) - e444: 00005b06 br e5b4 - } - } - else if (c == 27) /* ESC */ - e448: e0bff807 ldb r2,-32(fp) - e44c: 108006d8 cmpnei r2,r2,27 - e450: 1000031e bne r2,zero,e460 - { - sp->esccount = 0; - e454: e0bffc17 ldw r2,-16(fp) - e458: 10000905 stb zero,36(r2) - e45c: 00005506 br e5b4 - } - else if (c == '\r') - e460: e0bff807 ldb r2,-32(fp) - e464: 10800358 cmpnei r2,r2,13 - e468: 1000031e bne r2,zero,e478 - { - sp->x = 0; - e46c: e0bffc17 ldw r2,-16(fp) - e470: 10000845 stb zero,33(r2) - e474: 00004f06 br e5b4 - } - else if (c == '\n') - e478: e0bff807 ldb r2,-32(fp) - e47c: 10800298 cmpnei r2,r2,10 - e480: 1000101e bne r2,zero,e4c4 - { - sp->x = 0; - e484: e0bffc17 ldw r2,-16(fp) - e488: 10000845 stb zero,33(r2) - sp->y++; - e48c: e0bffc17 ldw r2,-16(fp) - e490: 10800883 ldbu r2,34(r2) - e494: 10800044 addi r2,r2,1 - e498: 1007883a mov r3,r2 - e49c: e0bffc17 ldw r2,-16(fp) - e4a0: 10c00885 stb r3,34(r2) - - /* Let the cursor sit at X=0, Y=HEIGHT without scrolling so the user - * can print two lines of data without losing one. - */ - if (sp->y > ALT_LCD_HEIGHT) - e4a4: e0bffc17 ldw r2,-16(fp) - e4a8: 10800883 ldbu r2,34(r2) - e4ac: 10803fcc andi r2,r2,255 - e4b0: 108000f0 cmpltui r2,r2,3 - e4b4: 10003f1e bne r2,zero,e5b4 - lcd_scroll_up(sp); - e4b8: e13ffc17 ldw r4,-16(fp) - e4bc: 000df200 call df20 - e4c0: 00003c06 br e5b4 - } - else if (c == '\b') - e4c4: e0bff807 ldb r2,-32(fp) - e4c8: 10800218 cmpnei r2,r2,8 - e4cc: 10000c1e bne r2,zero,e500 - { - if (sp->x > 0) - e4d0: e0bffc17 ldw r2,-16(fp) - e4d4: 10800843 ldbu r2,33(r2) - e4d8: 10803fcc andi r2,r2,255 - e4dc: 1005003a cmpeq r2,r2,zero - e4e0: 1000341e bne r2,zero,e5b4 - sp->x--; - e4e4: e0bffc17 ldw r2,-16(fp) - e4e8: 10800843 ldbu r2,33(r2) - e4ec: 10bfffc4 addi r2,r2,-1 - e4f0: 1007883a mov r3,r2 - e4f4: e0bffc17 ldw r2,-16(fp) - e4f8: 10c00845 stb r3,33(r2) - e4fc: 00002d06 br e5b4 - } - else if (isprint(c)) - e500: e0bff807 ldb r2,-32(fp) - e504: 1007883a mov r3,r2 - e508: 00800074 movhi r2,1 - e50c: 10883f04 addi r2,r2,8444 - e510: 10800017 ldw r2,0(r2) - e514: 1885883a add r2,r3,r2 - e518: 10800003 ldbu r2,0(r2) - e51c: 10803fcc andi r2,r2,255 - e520: 1080201c xori r2,r2,128 - e524: 10bfe004 addi r2,r2,-128 - e528: 108025cc andi r2,r2,151 - e52c: 1005003a cmpeq r2,r2,zero - e530: 1000201e bne r2,zero,e5b4 - { - /* If we didn't scroll on the last linefeed then we might need to do - * it now. */ - if (sp->y >= ALT_LCD_HEIGHT) - e534: e0bffc17 ldw r2,-16(fp) - e538: 10800883 ldbu r2,34(r2) - e53c: 10803fcc andi r2,r2,255 - e540: 108000b0 cmpltui r2,r2,2 - e544: 1000021e bne r2,zero,e550 - lcd_scroll_up(sp); - e548: e13ffc17 ldw r4,-16(fp) - e54c: 000df200 call df20 - - if (sp->x < ALT_LCD_VIRTUAL_WIDTH) - e550: e0bffc17 ldw r2,-16(fp) - e554: 10800843 ldbu r2,33(r2) - e558: 10803fcc andi r2,r2,255 - e55c: 10801428 cmpgeui r2,r2,80 - e560: 10000e1e bne r2,zero,e59c - sp->line[sp->y].data[sp->x] = c; - e564: e0bffc17 ldw r2,-16(fp) - e568: 10800883 ldbu r2,34(r2) - e56c: 11003fcc andi r4,r2,255 - e570: e0bffc17 ldw r2,-16(fp) - e574: 10800843 ldbu r2,33(r2) - e578: 14403fcc andi r17,r2,255 - e57c: e43ffc17 ldw r16,-16(fp) - e580: 014018c4 movi r5,99 - e584: 0002b2c0 call 2b2c <__mulsi3> - e588: 1405883a add r2,r2,r16 - e58c: 1445883a add r2,r2,r17 - e590: 10c01004 addi r3,r2,64 - e594: e0bff803 ldbu r2,-32(fp) - e598: 18800005 stb r2,0(r3) - - sp->x++; - e59c: e0bffc17 ldw r2,-16(fp) - e5a0: 10800843 ldbu r2,33(r2) - e5a4: 10800044 addi r2,r2,1 - e5a8: 1007883a mov r3,r2 - e5ac: e0bffc17 ldw r2,-16(fp) - e5b0: 10c00845 stb r3,33(r2) - - /* Tell the routine which is called off the timer interrupt that the - * foreground routines are active so it must not repaint the display. */ - sp->active = 1; - - for ( ; ptr < end ; ptr++) - e5b4: e0bffd17 ldw r2,-12(fp) - e5b8: 10800044 addi r2,r2,1 - e5bc: e0bffd15 stw r2,-12(fp) - e5c0: e0fffd17 ldw r3,-12(fp) - e5c4: e0bffb17 ldw r2,-20(fp) - e5c8: 18bf5a36 bltu r3,r2,e334 - sp->x++; - } - } - - /* Recalculate the scrolling parameters */ - widthmax = ALT_LCD_WIDTH; - e5cc: 00800404 movi r2,16 - e5d0: e0bff915 stw r2,-28(fp) - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - e5d4: e03ffa15 stw zero,-24(fp) - e5d8: 00003906 br e6c0 - { - int width; - for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) - e5dc: 00801404 movi r2,80 - e5e0: e0bff615 stw r2,-40(fp) - e5e4: 00001206 br e630 - if (sp->line[y].data[width-1] != ' ') - e5e8: e13ffa17 ldw r4,-24(fp) - e5ec: e0bff617 ldw r2,-40(fp) - e5f0: 147fffc4 addi r17,r2,-1 - e5f4: e43ffc17 ldw r16,-16(fp) - e5f8: 014018c4 movi r5,99 - e5fc: 0002b2c0 call 2b2c <__mulsi3> - e600: 1405883a add r2,r2,r16 - e604: 1445883a add r2,r2,r17 - e608: 10801004 addi r2,r2,64 - e60c: 10800003 ldbu r2,0(r2) - e610: 10803fcc andi r2,r2,255 - e614: 1080201c xori r2,r2,128 - e618: 10bfe004 addi r2,r2,-128 - e61c: 10800818 cmpnei r2,r2,32 - e620: 1000061e bne r2,zero,e63c - /* Recalculate the scrolling parameters */ - widthmax = ALT_LCD_WIDTH; - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - { - int width; - for (width = ALT_LCD_VIRTUAL_WIDTH ; width > 0 ; width--) - e624: e0bff617 ldw r2,-40(fp) - e628: 10bfffc4 addi r2,r2,-1 - e62c: e0bff615 stw r2,-40(fp) - e630: e0bff617 ldw r2,-40(fp) - e634: 10800048 cmpgei r2,r2,1 - e638: 103feb1e bne r2,zero,e5e8 - - /* The minimum width is the size of the LCD panel. If the real width - * is long enough to require scrolling then add an extra space so the - * end of the message doesn't run into the beginning of it. - */ - if (width <= ALT_LCD_WIDTH) - e63c: e0bff617 ldw r2,-40(fp) - e640: 10800448 cmpgei r2,r2,17 - e644: 1000031e bne r2,zero,e654 - width = ALT_LCD_WIDTH; - e648: 00800404 movi r2,16 - e64c: e0bff615 stw r2,-40(fp) - e650: 00000306 br e660 - else - width++; - e654: e0bff617 ldw r2,-40(fp) - e658: 10800044 addi r2,r2,1 - e65c: e0bff615 stw r2,-40(fp) - - sp->line[y].width = width; - e660: e13ffa17 ldw r4,-24(fp) - e664: e0bff617 ldw r2,-40(fp) - e668: 1023883a mov r17,r2 - e66c: e43ffc17 ldw r16,-16(fp) - e670: 014018c4 movi r5,99 - e674: 0002b2c0 call 2b2c <__mulsi3> - e678: 1405883a add r2,r2,r16 - e67c: 10802404 addi r2,r2,144 - e680: 14400045 stb r17,1(r2) - if (widthmax < width) - e684: e0fff917 ldw r3,-28(fp) - e688: e0bff617 ldw r2,-40(fp) - e68c: 1880020e bge r3,r2,e698 - widthmax = width; - e690: e0bff617 ldw r2,-40(fp) - e694: e0bff915 stw r2,-28(fp) - sp->line[y].speed = 0; /* By default lines don't scroll */ - e698: e13ffa17 ldw r4,-24(fp) - e69c: e43ffc17 ldw r16,-16(fp) - e6a0: 014018c4 movi r5,99 - e6a4: 0002b2c0 call 2b2c <__mulsi3> - e6a8: 1405883a add r2,r2,r16 - e6ac: 10802404 addi r2,r2,144 - e6b0: 10000085 stb zero,2(r2) - } - } - - /* Recalculate the scrolling parameters */ - widthmax = ALT_LCD_WIDTH; - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - e6b4: e0bffa17 ldw r2,-24(fp) - e6b8: 10800044 addi r2,r2,1 - e6bc: e0bffa15 stw r2,-24(fp) - e6c0: e0bffa17 ldw r2,-24(fp) - e6c4: 10800090 cmplti r2,r2,2 - e6c8: 103fc41e bne r2,zero,e5dc - if (widthmax < width) - widthmax = width; - sp->line[y].speed = 0; /* By default lines don't scroll */ - } - - if (widthmax <= ALT_LCD_WIDTH) - e6cc: e0bff917 ldw r2,-28(fp) - e6d0: 10800448 cmpgei r2,r2,17 - e6d4: 1000031e bne r2,zero,e6e4 - sp->scrollmax = 0; - e6d8: e0bffc17 ldw r2,-16(fp) - e6dc: 10000985 stb zero,38(r2) - e6e0: 00003106 br e7a8 - else - { - widthmax *= 2; - e6e4: e0bff917 ldw r2,-28(fp) - e6e8: 1085883a add r2,r2,r2 - e6ec: e0bff915 stw r2,-28(fp) - sp->scrollmax = widthmax; - e6f0: e0bff917 ldw r2,-28(fp) - e6f4: 1007883a mov r3,r2 - e6f8: e0bffc17 ldw r2,-16(fp) - e6fc: 10c00985 stb r3,38(r2) - - /* Now calculate how fast each of the other lines should go */ - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - e700: e03ffa15 stw zero,-24(fp) - e704: 00002506 br e79c - if (sp->line[y].width > ALT_LCD_WIDTH) - e708: e13ffa17 ldw r4,-24(fp) - e70c: e43ffc17 ldw r16,-16(fp) - e710: 014018c4 movi r5,99 - e714: 0002b2c0 call 2b2c <__mulsi3> - e718: 1405883a add r2,r2,r16 - e71c: 10802404 addi r2,r2,144 - e720: 10800043 ldbu r2,1(r2) - e724: 10803fcc andi r2,r2,255 - e728: 1080201c xori r2,r2,128 - e72c: 10bfe004 addi r2,r2,-128 - e730: 10800450 cmplti r2,r2,17 - e734: 1000161e bne r2,zero,e790 - */ -#if 1 - /* This option makes all the lines scroll round at different speeds - * which are chosen so that all the scrolls finish at the same time. - */ - sp->line[y].speed = 256 * sp->line[y].width / widthmax; - e738: e4bffa17 ldw r18,-24(fp) - e73c: e13ffa17 ldw r4,-24(fp) - e740: e43ffc17 ldw r16,-16(fp) - e744: 014018c4 movi r5,99 - e748: 0002b2c0 call 2b2c <__mulsi3> - e74c: 1405883a add r2,r2,r16 - e750: 10802404 addi r2,r2,144 - e754: 10800043 ldbu r2,1(r2) - e758: 10803fcc andi r2,r2,255 - e75c: 1080201c xori r2,r2,128 - e760: 10bfe004 addi r2,r2,-128 - e764: 1008923a slli r4,r2,8 - e768: e17ff917 ldw r5,-28(fp) - e76c: 0002a5c0 call 2a5c <__divsi3> - e770: 1023883a mov r17,r2 - e774: e43ffc17 ldw r16,-16(fp) - e778: 9009883a mov r4,r18 - e77c: 014018c4 movi r5,99 - e780: 0002b2c0 call 2b2c <__mulsi3> - e784: 1405883a add r2,r2,r16 - e788: 10802404 addi r2,r2,144 - e78c: 14400085 stb r17,2(r2) - { - widthmax *= 2; - sp->scrollmax = widthmax; - - /* Now calculate how fast each of the other lines should go */ - for (y = 0 ; y < ALT_LCD_HEIGHT ; y++) - e790: e0bffa17 ldw r2,-24(fp) - e794: 10800044 addi r2,r2,1 - e798: e0bffa15 stw r2,-24(fp) - e79c: e0bffa17 ldw r2,-24(fp) - e7a0: 10800090 cmplti r2,r2,2 - e7a4: 103fd81e bne r2,zero,e708 - * (because active was set when the timer interrupt occurred). If there - * has been a missed repaint then paint again. And again. etc. - */ - for ( ; ; ) - { - int old_scrollpos = sp->scrollpos; - e7a8: e0bffc17 ldw r2,-16(fp) - e7ac: 10800943 ldbu r2,37(r2) - e7b0: 10803fcc andi r2,r2,255 - e7b4: 1080201c xori r2,r2,128 - e7b8: 10bfe004 addi r2,r2,-128 - e7bc: e0bff515 stw r2,-44(fp) - - lcd_repaint_screen(sp); - e7c0: e13ffc17 ldw r4,-16(fp) - e7c4: 000dd0c0 call dd0c - - /* Let the timer routines repaint the display again */ - sp->active = 0; - e7c8: e0bffc17 ldw r2,-16(fp) - e7cc: 100009c5 stb zero,39(r2) - - /* Have the timer routines tried to scroll while we were painting? - * If not then we can exit */ - if (sp->scrollpos == old_scrollpos) - e7d0: e0bffc17 ldw r2,-16(fp) - e7d4: 10800943 ldbu r2,37(r2) - e7d8: 10c03fcc andi r3,r2,255 - e7dc: 18c0201c xori r3,r3,128 - e7e0: 18ffe004 addi r3,r3,-128 - e7e4: e0bff517 ldw r2,-44(fp) - e7e8: 18800426 beq r3,r2,e7fc - break; - - /* We need to repaint again since the display scrolled while we were - * painting last time */ - sp->active = 1; - e7ec: e0fffc17 ldw r3,-16(fp) - e7f0: 00800044 movi r2,1 - e7f4: 188009c5 stb r2,39(r3) - } - e7f8: 003feb06 br e7a8 - * semaphore so that other threads can access the buffer. - */ - - ALT_SEM_POST (sp->write_lock); - - return len; - e7fc: e0bffe17 ldw r2,-8(fp) -} - e800: e037883a mov sp,fp - e804: dfc00417 ldw ra,16(sp) - e808: df000317 ldw fp,12(sp) - e80c: dc800217 ldw r18,8(sp) - e810: dc400117 ldw r17,4(sp) - e814: dc000017 ldw r16,0(sp) - e818: dec00504 addi sp,sp,20 - e81c: f800283a ret - -0000e820 : -/* - * Timeout routine is called every second - */ - -static alt_u32 alt_lcd_16207_timeout(void* context) -{ - e820: defffc04 addi sp,sp,-16 - e824: dfc00315 stw ra,12(sp) - e828: df000215 stw fp,8(sp) - e82c: df000204 addi fp,sp,8 - e830: e13fff15 stw r4,-4(fp) - altera_avalon_lcd_16207_state* sp = (altera_avalon_lcd_16207_state*)context; - e834: e0bfff17 ldw r2,-4(fp) - e838: e0bffe15 stw r2,-8(fp) - - /* Update the scrolling position */ - if (sp->scrollpos + 1 >= sp->scrollmax) - e83c: e0bffe17 ldw r2,-8(fp) - e840: 10800943 ldbu r2,37(r2) - e844: 10803fcc andi r2,r2,255 - e848: 1080201c xori r2,r2,128 - e84c: 10bfe004 addi r2,r2,-128 - e850: 10c00044 addi r3,r2,1 - e854: e0bffe17 ldw r2,-8(fp) - e858: 10800983 ldbu r2,38(r2) - e85c: 10803fcc andi r2,r2,255 - e860: 1080201c xori r2,r2,128 - e864: 10bfe004 addi r2,r2,-128 - e868: 18800316 blt r3,r2,e878 - sp->scrollpos = 0; - e86c: e0bffe17 ldw r2,-8(fp) - e870: 10000945 stb zero,37(r2) - e874: 00000606 br e890 - else - sp->scrollpos = sp->scrollpos + 1; - e878: e0bffe17 ldw r2,-8(fp) - e87c: 10800943 ldbu r2,37(r2) - e880: 10800044 addi r2,r2,1 - e884: 1007883a mov r3,r2 - e888: e0bffe17 ldw r2,-8(fp) - e88c: 10c00945 stb r3,37(r2) - - /* Repaint the panel unless the foreground will do it again soon */ - if (sp->scrollmax > 0 && !sp->active) - e890: e0bffe17 ldw r2,-8(fp) - e894: 10800983 ldbu r2,38(r2) - e898: 10803fcc andi r2,r2,255 - e89c: 1080201c xori r2,r2,128 - e8a0: 10bfe004 addi r2,r2,-128 - e8a4: 10800050 cmplti r2,r2,1 - e8a8: 1000091e bne r2,zero,e8d0 - e8ac: e0bffe17 ldw r2,-8(fp) - e8b0: 108009c3 ldbu r2,39(r2) - e8b4: 10803fcc andi r2,r2,255 - e8b8: 1080201c xori r2,r2,128 - e8bc: 10bfe004 addi r2,r2,-128 - e8c0: 1004c03a cmpne r2,r2,zero - e8c4: 1000021e bne r2,zero,e8d0 - lcd_repaint_screen(sp); - e8c8: e13ffe17 ldw r4,-8(fp) - e8cc: 000dd0c0 call dd0c - - return sp->period; - e8d0: e0bffe17 ldw r2,-8(fp) - e8d4: 10800717 ldw r2,28(r2) -} - e8d8: e037883a mov sp,fp - e8dc: dfc00117 ldw ra,4(sp) - e8e0: df000017 ldw fp,0(sp) - e8e4: dec00204 addi sp,sp,8 - e8e8: f800283a ret - -0000e8ec : - -/* - * Called at boot time to initialise the LCD driver - */ -void altera_avalon_lcd_16207_init(altera_avalon_lcd_16207_state* sp) -{ - e8ec: defffc04 addi sp,sp,-16 - e8f0: dfc00315 stw ra,12(sp) - e8f4: df000215 stw fp,8(sp) - e8f8: df000204 addi fp,sp,8 - e8fc: e13fff15 stw r4,-4(fp) - unsigned int base = sp->base; - e900: e0bfff17 ldw r2,-4(fp) - e904: 10800017 ldw r2,0(r2) - e908: e0bffe15 stw r2,-8(fp) - - /* Mark the device as functional */ - sp->broken = 0; - e90c: e0bfff17 ldw r2,-4(fp) - e910: 10000805 stb zero,32(r2) - * the BUSY bit in the status register doesn't work until the display - * has been reset three times. - */ - - /* Wait for 15 ms then reset */ - usleep(15000); - e914: 010ea604 movi r4,15000 - e918: 000cd800 call cd80 - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); - e91c: e0bffe17 ldw r2,-8(fp) - e920: 1007883a mov r3,r2 - e924: 00800c04 movi r2,48 - e928: 18800035 stwio r2,0(r3) - - /* Wait for another 4.1ms and reset again */ - usleep(4100); - e92c: 01040104 movi r4,4100 - e930: 000cd800 call cd80 - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); - e934: e0bffe17 ldw r2,-8(fp) - e938: 1007883a mov r3,r2 - e93c: 00800c04 movi r2,48 - e940: 18800035 stwio r2,0(r3) - - /* Wait a further 1 ms and reset a third time */ - usleep(1000); - e944: 0100fa04 movi r4,1000 - e948: 000cd800 call cd80 - IOWR_ALTERA_AVALON_LCD_16207_COMMAND(base, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT); - e94c: e0bffe17 ldw r2,-8(fp) - e950: 1007883a mov r3,r2 - e954: 00800c04 movi r2,48 - e958: 18800035 stwio r2,0(r3) - - /* Setup interface parameters: 8 bit bus, 2 rows, 5x7 font */ - lcd_write_command(sp, LCD_CMD_FUNCTION_SET | LCD_CMD_8BIT | LCD_CMD_TWO_LINE); - e95c: e13fff17 ldw r4,-4(fp) - e960: 01400e04 movi r5,56 - e964: 000daa80 call daa8 - - /* Turn display off */ - lcd_write_command(sp, LCD_CMD_ONOFF); - e968: e13fff17 ldw r4,-4(fp) - e96c: 01400204 movi r5,8 - e970: 000daa80 call daa8 - - /* Clear display */ - lcd_clear_screen(sp); - e974: e13fff17 ldw r4,-4(fp) - e978: 000dc340 call dc34 - - /* Set mode: increment after writing, don't shift display */ - lcd_write_command(sp, LCD_CMD_MODES | LCD_CMD_MODE_INC); - e97c: e13fff17 ldw r4,-4(fp) - e980: 01400184 movi r5,6 - e984: 000daa80 call daa8 - - /* Turn display on */ - lcd_write_command(sp, LCD_CMD_ONOFF | LCD_CMD_ENABLE_DISP); - e988: e13fff17 ldw r4,-4(fp) - e98c: 01400304 movi r5,12 - e990: 000daa80 call daa8 - - sp->esccount = -1; - e994: e0ffff17 ldw r3,-4(fp) - e998: 00bfffc4 movi r2,-1 - e99c: 18800905 stb r2,36(r3) - memset(sp->escape, 0, sizeof(sp->escape)); - e9a0: e0bfff17 ldw r2,-4(fp) - e9a4: 11000a04 addi r4,r2,40 - e9a8: 000b883a mov r5,zero - e9ac: 01800204 movi r6,8 - e9b0: 000809c0 call 809c - - sp->scrollpos = 0; - e9b4: e0bfff17 ldw r2,-4(fp) - e9b8: 10000945 stb zero,37(r2) - sp->scrollmax = 0; - e9bc: e0bfff17 ldw r2,-4(fp) - e9c0: 10000985 stb zero,38(r2) - sp->active = 0; - e9c4: e0bfff17 ldw r2,-4(fp) - e9c8: 100009c5 stb zero,39(r2) - e9cc: 00800074 movhi r2,1 - e9d0: 108f4304 addi r2,r2,15628 - e9d4: 10800017 ldw r2,0(r2) - e9d8: 1009883a mov r4,r2 - - sp->period = alt_ticks_per_second() / 10; /* Call every 100ms */ - e9dc: 01400284 movi r5,10 - e9e0: 0002b1c0 call 2b1c <__udivsi3> - e9e4: 1007883a mov r3,r2 - e9e8: e0bfff17 ldw r2,-4(fp) - e9ec: 10c00715 stw r3,28(r2) - - alt_alarm_start(&sp->alarm, sp->period, &alt_lcd_16207_timeout, sp); - e9f0: e0bfff17 ldw r2,-4(fp) - e9f4: 11000104 addi r4,r2,4 - e9f8: e0bfff17 ldw r2,-4(fp) - e9fc: 10800717 ldw r2,28(r2) - ea00: 100b883a mov r5,r2 - ea04: 01800074 movhi r6,1 - ea08: 31ba0804 addi r6,r6,-6112 - ea0c: e1ffff17 ldw r7,-4(fp) - ea10: 000ea800 call ea80 -} - ea14: e037883a mov sp,fp - ea18: dfc00117 ldw ra,4(sp) - ea1c: df000017 ldw fp,0(sp) - ea20: dec00204 addi sp,sp,8 - ea24: f800283a ret - -0000ea28 : -extern int altera_avalon_lcd_16207_write(altera_avalon_lcd_16207_state* sp, - const char* ptr, int count, int flags); - -int -altera_avalon_lcd_16207_write_fd(alt_fd* fd, const char* buffer, int space) -{ - ea28: defffa04 addi sp,sp,-24 - ea2c: dfc00515 stw ra,20(sp) - ea30: df000415 stw fp,16(sp) - ea34: df000404 addi fp,sp,16 - ea38: e13ffd15 stw r4,-12(fp) - ea3c: e17ffe15 stw r5,-8(fp) - ea40: e1bfff15 stw r6,-4(fp) - altera_avalon_lcd_16207_dev* dev = (altera_avalon_lcd_16207_dev*) fd->dev; - ea44: e0bffd17 ldw r2,-12(fp) - ea48: 10800017 ldw r2,0(r2) - ea4c: e0bffc15 stw r2,-16(fp) - - return altera_avalon_lcd_16207_write(&dev->state, buffer, space, - ea50: e0bffc17 ldw r2,-16(fp) - ea54: 11000a04 addi r4,r2,40 - ea58: e0bffd17 ldw r2,-12(fp) - ea5c: 11c00217 ldw r7,8(r2) - ea60: e17ffe17 ldw r5,-8(fp) - ea64: e1bfff17 ldw r6,-4(fp) - ea68: 000e2e40 call e2e4 - fd->fd_flags); -} - ea6c: e037883a mov sp,fp - ea70: dfc00117 ldw ra,4(sp) - ea74: df000017 ldw fp,0(sp) - ea78: dec00204 addi sp,sp,8 - ea7c: f800283a ret - -0000ea80 : - */ - -int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, - alt_u32 (*callback) (void* context), - void* context) -{ - ea80: defff404 addi sp,sp,-48 - ea84: df000b15 stw fp,44(sp) - ea88: df000b04 addi fp,sp,44 - ea8c: e13ffb15 stw r4,-20(fp) - ea90: e17ffc15 stw r5,-16(fp) - ea94: e1bffd15 stw r6,-12(fp) - ea98: e1fffe15 stw r7,-8(fp) - alt_irq_context irq_context; - alt_u32 current_nticks = 0; - ea9c: e03ff915 stw zero,-28(fp) - eaa0: 00800074 movhi r2,1 - eaa4: 108f4304 addi r2,r2,15628 - eaa8: 10800017 ldw r2,0(r2) - - if (alt_ticks_per_second ()) - eaac: 1005003a cmpeq r2,r2,zero - eab0: 1000411e bne r2,zero,ebb8 - { - if (alarm) - eab4: e0bffb17 ldw r2,-20(fp) - eab8: 1005003a cmpeq r2,r2,zero - eabc: 10003b1e bne r2,zero,ebac - { - alarm->callback = callback; - eac0: e0fffb17 ldw r3,-20(fp) - eac4: e0bffd17 ldw r2,-12(fp) - eac8: 18800315 stw r2,12(r3) - alarm->context = context; - eacc: e0fffb17 ldw r3,-20(fp) - ead0: e0bffe17 ldw r2,-8(fp) - ead4: 18800515 stw r2,20(r3) -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - ead8: 0005303a rdctl r2,status - eadc: e0bff815 stw r2,-32(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - eae0: e0fff817 ldw r3,-32(fp) - eae4: 00bfff84 movi r2,-2 - eae8: 1884703a and r2,r3,r2 - eaec: 1001703a wrctl status,r2 - - return context; - eaf0: e0bff817 ldw r2,-32(fp) - - irq_context = alt_irq_disable_all (); - eaf4: e0bffa15 stw r2,-24(fp) - * alt_nticks() returns the elapsed number of system clock ticks since reset. - */ - -static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) -{ - return _alt_nticks; - eaf8: 00800074 movhi r2,1 - eafc: 108f4404 addi r2,r2,15632 - eb00: 10800017 ldw r2,0(r2) - - current_nticks = alt_nticks(); - eb04: e0bff915 stw r2,-28(fp) - - alarm->time = nticks + current_nticks + 1; - eb08: e0fffc17 ldw r3,-16(fp) - eb0c: e0bff917 ldw r2,-28(fp) - eb10: 1885883a add r2,r3,r2 - eb14: 10c00044 addi r3,r2,1 - eb18: e0bffb17 ldw r2,-20(fp) - eb1c: 10c00215 stw r3,8(r2) - /* - * If the desired alarm time causes a roll-over, set the rollover - * flag. This will prevent the subsequent tick event from causing - * an alarm too early. - */ - if(alarm->time < current_nticks) - eb20: e0bffb17 ldw r2,-20(fp) - eb24: 10c00217 ldw r3,8(r2) - eb28: e0bff917 ldw r2,-28(fp) - eb2c: 1880042e bgeu r3,r2,eb40 - { - alarm->rollover = 1; - eb30: e0fffb17 ldw r3,-20(fp) - eb34: 00800044 movi r2,1 - eb38: 18800405 stb r2,16(r3) - eb3c: 00000206 br eb48 - } - else - { - alarm->rollover = 0; - eb40: e0bffb17 ldw r2,-20(fp) - eb44: 10000405 stb zero,16(r2) - } - - alt_llist_insert (&alt_alarm_list, &alarm->llist); - eb48: e0fffb17 ldw r3,-20(fp) - eb4c: 00800074 movhi r2,1 - eb50: 10884f04 addi r2,r2,8508 - eb54: e0bff615 stw r2,-40(fp) - eb58: e0fff715 stw r3,-36(fp) - */ - -static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, - alt_llist* entry) -{ - entry->previous = list; - eb5c: e0fff717 ldw r3,-36(fp) - eb60: e0bff617 ldw r2,-40(fp) - eb64: 18800115 stw r2,4(r3) - entry->next = list->next; - eb68: e0bff617 ldw r2,-40(fp) - eb6c: 10c00017 ldw r3,0(r2) - eb70: e0bff717 ldw r2,-36(fp) - eb74: 10c00015 stw r3,0(r2) - - list->next->previous = entry; - eb78: e0bff617 ldw r2,-40(fp) - eb7c: 10c00017 ldw r3,0(r2) - eb80: e0bff717 ldw r2,-36(fp) - eb84: 18800115 stw r2,4(r3) - list->next = entry; - eb88: e0fff617 ldw r3,-40(fp) - eb8c: e0bff717 ldw r2,-36(fp) - eb90: 18800015 stw r2,0(r3) - eb94: e0bffa17 ldw r2,-24(fp) - eb98: e0bff515 stw r2,-44(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - eb9c: e0bff517 ldw r2,-44(fp) - eba0: 1001703a wrctl status,r2 - alt_irq_enable_all (irq_context); - - return 0; - eba4: e03fff15 stw zero,-4(fp) - eba8: 00000506 br ebc0 - } - else - { - return -EINVAL; - ebac: 00bffa84 movi r2,-22 - ebb0: e0bfff15 stw r2,-4(fp) - ebb4: 00000206 br ebc0 - } - } - else - { - return -ENOTSUP; - ebb8: 00bfde84 movi r2,-134 - ebbc: e0bfff15 stw r2,-4(fp) - ebc0: e0bfff17 ldw r2,-4(fp) - } -} - ebc4: e037883a mov sp,fp - ebc8: df000017 ldw fp,0(sp) - ebcc: dec00104 addi sp,sp,4 - ebd0: f800283a ret - -0000ebd4 : -#include "alt_types.h" - -#include "priv/alt_busy_sleep.h" - -unsigned int alt_busy_sleep (unsigned int us) -{ - ebd4: defffa04 addi sp,sp,-24 - ebd8: dfc00515 stw ra,20(sp) - ebdc: df000415 stw fp,16(sp) - ebe0: df000404 addi fp,sp,16 - ebe4: e13fff15 stw r4,-4(fp) - int big_loops; - alt_u32 cycles_per_loop; - - if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) - { - cycles_per_loop = 9; - ebe8: 00800244 movi r2,9 - ebec: e0bffc15 stw r2,-16(fp) - { - cycles_per_loop = 3; - } - - - big_loops = us / (INT_MAX/ - ebf0: e13ffc17 ldw r4,-16(fp) - ebf4: 014003f4 movhi r5,15 - ebf8: 29509004 addi r5,r5,16960 - ebfc: 0002b2c0 call 2b2c <__mulsi3> - ec00: 100b883a mov r5,r2 - ec04: 0100bef4 movhi r4,763 - ec08: 213c2004 addi r4,r4,-3968 - ec0c: 0002b1c0 call 2b1c <__udivsi3> - ec10: 100b883a mov r5,r2 - ec14: 01200034 movhi r4,32768 - ec18: 213fffc4 addi r4,r4,-1 - ec1c: 0002b1c0 call 2b1c <__udivsi3> - ec20: 100b883a mov r5,r2 - ec24: e13fff17 ldw r4,-4(fp) - ec28: 0002b1c0 call 2b1c <__udivsi3> - ec2c: e0bffd15 stw r2,-12(fp) - (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); - - if (big_loops) - ec30: e0bffd17 ldw r2,-12(fp) - ec34: 1005003a cmpeq r2,r2,zero - ec38: 10002a1e bne r2,zero,ece4 - { - for(i=0;i - /* - * Do NOT Try to single step the asm statement below - * (single step will never return) - * Step out of this function or set a breakpoint after the asm statements - */ - __asm__ volatile ( - ec44: 00a00034 movhi r2,32768 - ec48: 10bfffc4 addi r2,r2,-1 - ec4c: 10bfffc4 addi r2,r2,-1 - ec50: 103ffe1e bne r2,zero,ec4c - "\n1:" - "\n\t.pushsection .debug_alt_sim_info" - "\n\t.int 4, 0, 0b, 1b" - "\n\t.popsection" - :: "r" (INT_MAX)); - us -= (INT_MAX/(ALT_CPU_FREQ/ - ec54: e13ffc17 ldw r4,-16(fp) - ec58: 014003f4 movhi r5,15 - ec5c: 29509004 addi r5,r5,16960 - ec60: 0002b2c0 call 2b2c <__mulsi3> - ec64: 100b883a mov r5,r2 - ec68: 0100bef4 movhi r4,763 - ec6c: 213c2004 addi r4,r4,-3968 - ec70: 0002b1c0 call 2b1c <__udivsi3> - ec74: 100b883a mov r5,r2 - ec78: 01200034 movhi r4,32768 - ec7c: 213fffc4 addi r4,r4,-1 - ec80: 0002b1c0 call 2b1c <__udivsi3> - ec84: 1007883a mov r3,r2 - ec88: e0bfff17 ldw r2,-4(fp) - ec8c: 10c5c83a sub r2,r2,r3 - ec90: e0bfff15 stw r2,-4(fp) - big_loops = us / (INT_MAX/ - (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); - - if (big_loops) - { - for(i=0;i - /* - * Do NOT Try to single step the asm statement below - * (single step will never return) - * Step out of this function or set a breakpoint after the asm statements - */ - __asm__ volatile ( - ecac: e13ffc17 ldw r4,-16(fp) - ecb0: 014003f4 movhi r5,15 - ecb4: 29509004 addi r5,r5,16960 - ecb8: 0002b2c0 call 2b2c <__mulsi3> - ecbc: 100b883a mov r5,r2 - ecc0: 0100bef4 movhi r4,763 - ecc4: 213c2004 addi r4,r4,-3968 - ecc8: 0002b1c0 call 2b1c <__udivsi3> - eccc: 1009883a mov r4,r2 - ecd0: e17fff17 ldw r5,-4(fp) - ecd4: 0002b2c0 call 2b2c <__mulsi3> - ecd8: 10bfffc4 addi r2,r2,-1 - ecdc: 103ffe1e bne r2,zero,ecd8 - ece0: 00000d06 br ed18 - /* - * Do NOT Try to single step the asm statement below - * (single step will never return) - * Step out of this function or set a breakpoint after the asm statements - */ - __asm__ volatile ( - ece4: e13ffc17 ldw r4,-16(fp) - ece8: 014003f4 movhi r5,15 - ecec: 29509004 addi r5,r5,16960 - ecf0: 0002b2c0 call 2b2c <__mulsi3> - ecf4: 100b883a mov r5,r2 - ecf8: 0100bef4 movhi r4,763 - ecfc: 213c2004 addi r4,r4,-3968 - ed00: 0002b1c0 call 2b1c <__udivsi3> - ed04: 1009883a mov r4,r2 - ed08: e17fff17 ldw r5,-4(fp) - ed0c: 0002b2c0 call 2b2c <__mulsi3> - ed10: 10bfffc4 addi r2,r2,-1 - ed14: 00bffe16 blt zero,r2,ed10 - "\n\t.int 4, 0, 0b, 1b" - "\n\t.popsection" - :: "r" (us*(ALT_CPU_FREQ/(cycles_per_loop * 1000000)))); - } -#endif /* #ifndef ALT_SIM_OPTIMIZE */ - return 0; - ed18: 0005883a mov r2,zero -} - ed1c: e037883a mov sp,fp - ed20: dfc00117 ldw ra,4(sp) - ed24: df000017 ldw fp,0(sp) - ed28: dec00204 addi sp,sp,8 - ed2c: f800283a ret - -0000ed30 : -/* - * alt_dcache_flush_all() is called to flush the entire data cache. - */ - -void alt_dcache_flush_all (void) -{ - ed30: deffff04 addi sp,sp,-4 - ed34: df000015 stw fp,0(sp) - ed38: d839883a mov fp,sp - for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) - { - __asm__ volatile ("flushd (%0)" :: "r" (i)); - } -#endif /* NIOS2_DCACHE_SIZE > 0 */ -} - ed3c: e037883a mov sp,fp - ed40: df000017 ldw fp,0(sp) - ed44: dec00104 addi sp,sp,4 - ed48: f800283a ret - -0000ed4c : -/* - * - */ - -int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) -{ - ed4c: defff904 addi sp,sp,-28 - ed50: dfc00615 stw ra,24(sp) - ed54: df000515 stw fp,20(sp) - ed58: df000504 addi fp,sp,20 - ed5c: e13ffd15 stw r4,-12(fp) - ed60: e17ffe15 stw r5,-8(fp) - /* - * check that the device exists, and that it has a valid name. - */ - - if (!dev || !dev->name) - ed64: e0bffd17 ldw r2,-12(fp) - ed68: 1005003a cmpeq r2,r2,zero - ed6c: 1000041e bne r2,zero,ed80 - ed70: e0bffd17 ldw r2,-12(fp) - ed74: 10800217 ldw r2,8(r2) - ed78: 1004c03a cmpne r2,r2,zero - ed7c: 1000071e bne r2,zero,ed9c - { - ALT_ERRNO = EINVAL; - ed80: 000ee000 call ee00 - ed84: 1007883a mov r3,r2 - ed88: 00800584 movi r2,22 - ed8c: 18800015 stw r2,0(r3) - return -EINVAL; - ed90: 00bffa84 movi r2,-22 - ed94: e0bfff15 stw r2,-4(fp) - ed98: 00001306 br ede8 - - /* - * register the device. - */ - - alt_llist_insert(list, &dev->llist); - ed9c: e0fffd17 ldw r3,-12(fp) - eda0: e0bffe17 ldw r2,-8(fp) - eda4: e0bffb15 stw r2,-20(fp) - eda8: e0fffc15 stw r3,-16(fp) - */ - -static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, - alt_llist* entry) -{ - entry->previous = list; - edac: e0fffc17 ldw r3,-16(fp) - edb0: e0bffb17 ldw r2,-20(fp) - edb4: 18800115 stw r2,4(r3) - entry->next = list->next; - edb8: e0bffb17 ldw r2,-20(fp) - edbc: 10c00017 ldw r3,0(r2) - edc0: e0bffc17 ldw r2,-16(fp) - edc4: 10c00015 stw r3,0(r2) - - list->next->previous = entry; - edc8: e0bffb17 ldw r2,-20(fp) - edcc: 10c00017 ldw r3,0(r2) - edd0: e0bffc17 ldw r2,-16(fp) - edd4: 18800115 stw r2,4(r3) - list->next = entry; - edd8: e0fffb17 ldw r3,-20(fp) - eddc: e0bffc17 ldw r2,-16(fp) - ede0: 18800015 stw r2,0(r3) - - return 0; - ede4: e03fff15 stw zero,-4(fp) - ede8: e0bfff17 ldw r2,-4(fp) -} - edec: e037883a mov sp,fp - edf0: dfc00117 ldw ra,4(sp) - edf4: df000017 ldw fp,0(sp) - edf8: dec00204 addi sp,sp,8 - edfc: f800283a ret - -0000ee00 : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - ee00: defffd04 addi sp,sp,-12 - ee04: dfc00215 stw ra,8(sp) - ee08: df000115 stw fp,4(sp) - ee0c: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - ee10: 00800074 movhi r2,1 - ee14: 10884b04 addi r2,r2,8492 - ee18: 10800017 ldw r2,0(r2) - ee1c: 1005003a cmpeq r2,r2,zero - ee20: 1000061e bne r2,zero,ee3c - ee24: 00800074 movhi r2,1 - ee28: 10884b04 addi r2,r2,8492 - ee2c: 10800017 ldw r2,0(r2) - ee30: 103ee83a callr r2 - ee34: e0bfff15 stw r2,-4(fp) - ee38: 00000306 br ee48 - ee3c: 00800074 movhi r2,1 - ee40: 108f3e04 addi r2,r2,15608 - ee44: e0bfff15 stw r2,-4(fp) - ee48: e0bfff17 ldw r2,-4(fp) -} - ee4c: e037883a mov sp,fp - ee50: dfc00117 ldw ra,4(sp) - ee54: df000017 ldw fp,0(sp) - ee58: dec00204 addi sp,sp,8 - ee5c: f800283a ret - -0000ee60 <_do_ctors>: -/* - * Run the C++ static constructors. - */ - -void _do_ctors(void) -{ - ee60: defffd04 addi sp,sp,-12 - ee64: dfc00215 stw ra,8(sp) - ee68: df000115 stw fp,4(sp) - ee6c: df000104 addi fp,sp,4 - constructor* ctor; - - for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) - ee70: 00bfff04 movi r2,-4 - ee74: 00c00074 movhi r3,1 - ee78: 18ffa604 addi r3,r3,-360 - ee7c: 1885883a add r2,r3,r2 - ee80: e0bfff15 stw r2,-4(fp) - ee84: 00000606 br eea0 <_do_ctors+0x40> - (*ctor) (); - ee88: e0bfff17 ldw r2,-4(fp) - ee8c: 10800017 ldw r2,0(r2) - ee90: 103ee83a callr r2 - -void _do_ctors(void) -{ - constructor* ctor; - - for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) - ee94: e0bfff17 ldw r2,-4(fp) - ee98: 10bfff04 addi r2,r2,-4 - ee9c: e0bfff15 stw r2,-4(fp) - eea0: e0ffff17 ldw r3,-4(fp) - eea4: 00800074 movhi r2,1 - eea8: 10bfa504 addi r2,r2,-364 - eeac: 18bff62e bgeu r3,r2,ee88 <_do_ctors+0x28> - (*ctor) (); -} - eeb0: e037883a mov sp,fp - eeb4: dfc00117 ldw ra,4(sp) - eeb8: df000017 ldw fp,0(sp) - eebc: dec00204 addi sp,sp,8 - eec0: f800283a ret - -0000eec4 <_do_dtors>: -/* - * Run the C++ static destructors. - */ - -void _do_dtors(void) -{ - eec4: defffd04 addi sp,sp,-12 - eec8: dfc00215 stw ra,8(sp) - eecc: df000115 stw fp,4(sp) - eed0: df000104 addi fp,sp,4 - destructor* dtor; - - for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) - eed4: 00bfff04 movi r2,-4 - eed8: 00c00074 movhi r3,1 - eedc: 18ffa604 addi r3,r3,-360 - eee0: 1885883a add r2,r3,r2 - eee4: e0bfff15 stw r2,-4(fp) - eee8: 00000606 br ef04 <_do_dtors+0x40> - (*dtor) (); - eeec: e0bfff17 ldw r2,-4(fp) - eef0: 10800017 ldw r2,0(r2) - eef4: 103ee83a callr r2 - -void _do_dtors(void) -{ - destructor* dtor; - - for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) - eef8: e0bfff17 ldw r2,-4(fp) - eefc: 10bfff04 addi r2,r2,-4 - ef00: e0bfff15 stw r2,-4(fp) - ef04: e0ffff17 ldw r3,-4(fp) - ef08: 00800074 movhi r2,1 - ef0c: 10bfa604 addi r2,r2,-360 - ef10: 18bff62e bgeu r3,r2,eeec <_do_dtors+0x28> - (*dtor) (); -} - ef14: e037883a mov sp,fp - ef18: dfc00117 ldw ra,4(sp) - ef1c: df000017 ldw fp,0(sp) - ef20: dec00204 addi sp,sp,8 - ef24: f800283a ret - -0000ef28 : -/* - * alt_icache_flush_all() is called to flush the entire instruction cache. - */ - -void alt_icache_flush_all (void) -{ - ef28: deffff04 addi sp,sp,-4 - ef2c: df000015 stw fp,0(sp) - ef30: d839883a mov fp,sp -#if NIOS2_ICACHE_SIZE > 0 - alt_icache_flush (0, NIOS2_ICACHE_SIZE); -#endif -} - ef34: e037883a mov sp,fp - ef38: df000017 ldw fp,0(sp) - ef3c: dec00104 addi sp,sp,4 - ef40: f800283a ret - -0000ef44 : - * @param irq IRQ number - * @return 0 if successful, else error (-1) - */ -int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, - void *isr_context, void *flags) -{ - ef44: defff904 addi sp,sp,-28 - ef48: dfc00615 stw ra,24(sp) - ef4c: df000515 stw fp,20(sp) - ef50: df000504 addi fp,sp,20 - ef54: e13ffc15 stw r4,-16(fp) - ef58: e17ffd15 stw r5,-12(fp) - ef5c: e1bffe15 stw r6,-8(fp) - ef60: e1ffff15 stw r7,-4(fp) - return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); - ef64: e0800217 ldw r2,8(fp) - ef68: d8800015 stw r2,0(sp) - ef6c: e13ffc17 ldw r4,-16(fp) - ef70: e17ffd17 ldw r5,-12(fp) - ef74: e1bffe17 ldw r6,-8(fp) - ef78: e1ffff17 ldw r7,-4(fp) - ef7c: 000f1180 call f118 -} - ef80: e037883a mov sp,fp - ef84: dfc00117 ldw ra,4(sp) - ef88: df000017 ldw fp,0(sp) - ef8c: dec00204 addi sp,sp,8 - ef90: f800283a ret - -0000ef94 : - * @param ic_id Ignored. - * @param irq IRQ number - * @return 0 if successful, else error (-1) - */ -int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) -{ - ef94: defff904 addi sp,sp,-28 - ef98: df000615 stw fp,24(sp) - ef9c: df000604 addi fp,sp,24 - efa0: e13ffe15 stw r4,-8(fp) - efa4: e17fff15 stw r5,-4(fp) - efa8: e0bfff17 ldw r2,-4(fp) - efac: e0bffc15 stw r2,-16(fp) -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - efb0: 0005303a rdctl r2,status - efb4: e0bffb15 stw r2,-20(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - efb8: e0fffb17 ldw r3,-20(fp) - efbc: 00bfff84 movi r2,-2 - efc0: 1884703a and r2,r3,r2 - efc4: 1001703a wrctl status,r2 - - return context; - efc8: e0bffb17 ldw r2,-20(fp) -static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) -{ - alt_irq_context status; - extern volatile alt_u32 alt_irq_active; - - status = alt_irq_disable_all (); - efcc: e0bffd15 stw r2,-12(fp) - - alt_irq_active |= (1 << id); - efd0: e0fffc17 ldw r3,-16(fp) - efd4: 00800044 movi r2,1 - efd8: 10c4983a sll r2,r2,r3 - efdc: 1007883a mov r3,r2 - efe0: 00800074 movhi r2,1 - efe4: 108f4204 addi r2,r2,15624 - efe8: 10800017 ldw r2,0(r2) - efec: 1886b03a or r3,r3,r2 - eff0: 00800074 movhi r2,1 - eff4: 108f4204 addi r2,r2,15624 - eff8: 10c00015 stw r3,0(r2) - NIOS2_WRITE_IENABLE (alt_irq_active); - effc: 00800074 movhi r2,1 - f000: 108f4204 addi r2,r2,15624 - f004: 10800017 ldw r2,0(r2) - f008: 100170fa wrctl ienable,r2 - f00c: e0bffd17 ldw r2,-12(fp) - f010: e0bffa15 stw r2,-24(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - f014: e0bffa17 ldw r2,-24(fp) - f018: 1001703a wrctl status,r2 - - alt_irq_enable_all(status); - - return 0; - f01c: 0005883a mov r2,zero - return alt_irq_enable(irq); -} - f020: e037883a mov sp,fp - f024: df000017 ldw fp,0(sp) - f028: dec00104 addi sp,sp,4 - f02c: f800283a ret - -0000f030 : - * @param ic_id Ignored. - * @param irq IRQ number - * @return 0 if successful, else error (-1) - */ -int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) -{ - f030: defff904 addi sp,sp,-28 - f034: df000615 stw fp,24(sp) - f038: df000604 addi fp,sp,24 - f03c: e13ffe15 stw r4,-8(fp) - f040: e17fff15 stw r5,-4(fp) - f044: e0bfff17 ldw r2,-4(fp) - f048: e0bffc15 stw r2,-16(fp) -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - f04c: 0005303a rdctl r2,status - f050: e0bffb15 stw r2,-20(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - f054: e0fffb17 ldw r3,-20(fp) - f058: 00bfff84 movi r2,-2 - f05c: 1884703a and r2,r3,r2 - f060: 1001703a wrctl status,r2 - - return context; - f064: e0bffb17 ldw r2,-20(fp) -static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) -{ - alt_irq_context status; - extern volatile alt_u32 alt_irq_active; - - status = alt_irq_disable_all (); - f068: e0bffd15 stw r2,-12(fp) - - alt_irq_active &= ~(1 << id); - f06c: e0fffc17 ldw r3,-16(fp) - f070: 00800044 movi r2,1 - f074: 10c4983a sll r2,r2,r3 - f078: 0084303a nor r2,zero,r2 - f07c: 1007883a mov r3,r2 - f080: 00800074 movhi r2,1 - f084: 108f4204 addi r2,r2,15624 - f088: 10800017 ldw r2,0(r2) - f08c: 1886703a and r3,r3,r2 - f090: 00800074 movhi r2,1 - f094: 108f4204 addi r2,r2,15624 - f098: 10c00015 stw r3,0(r2) - NIOS2_WRITE_IENABLE (alt_irq_active); - f09c: 00800074 movhi r2,1 - f0a0: 108f4204 addi r2,r2,15624 - f0a4: 10800017 ldw r2,0(r2) - f0a8: 100170fa wrctl ienable,r2 - f0ac: e0bffd17 ldw r2,-12(fp) - f0b0: e0bffa15 stw r2,-24(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - f0b4: e0bffa17 ldw r2,-24(fp) - f0b8: 1001703a wrctl status,r2 - - alt_irq_enable_all(status); - - return 0; - f0bc: 0005883a mov r2,zero - return alt_irq_disable(irq); -} - f0c0: e037883a mov sp,fp - f0c4: df000017 ldw fp,0(sp) - f0c8: dec00104 addi sp,sp,4 - f0cc: f800283a ret - -0000f0d0 : - * @param irq IRQ number - * @return Zero if corresponding interrupt is disabled and - * non-zero otherwise. - */ -alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) -{ - f0d0: defffc04 addi sp,sp,-16 - f0d4: df000315 stw fp,12(sp) - f0d8: df000304 addi fp,sp,12 - f0dc: e13ffe15 stw r4,-8(fp) - f0e0: e17fff15 stw r5,-4(fp) - alt_u32 irq_enabled; - - NIOS2_READ_IENABLE(irq_enabled); - f0e4: 000530fa rdctl r2,ienable - f0e8: e0bffd15 stw r2,-12(fp) - - return (irq_enabled & (1 << irq)) ? 1: 0; - f0ec: e0ffff17 ldw r3,-4(fp) - f0f0: 00800044 movi r2,1 - f0f4: 10c4983a sll r2,r2,r3 - f0f8: 1007883a mov r3,r2 - f0fc: e0bffd17 ldw r2,-12(fp) - f100: 1884703a and r2,r3,r2 - f104: 1004c03a cmpne r2,r2,zero -} - f108: e037883a mov sp,fp - f10c: df000017 ldw fp,0(sp) - f110: dec00104 addi sp,sp,4 - f114: f800283a ret - -0000f118 : - * @param flags - * @return 0 if successful, else error (-1) - */ -int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, - void *isr_context, void *flags) -{ - f118: defff404 addi sp,sp,-48 - f11c: dfc00b15 stw ra,44(sp) - f120: df000a15 stw fp,40(sp) - f124: df000a04 addi fp,sp,40 - f128: e13ffb15 stw r4,-20(fp) - f12c: e17ffc15 stw r5,-16(fp) - f130: e1bffd15 stw r6,-12(fp) - f134: e1fffe15 stw r7,-8(fp) - int rc = -EINVAL; - f138: 00bffa84 movi r2,-22 - f13c: e0bffa15 stw r2,-24(fp) - int id = irq; /* IRQ interpreted as the interrupt ID. */ - f140: e0bffc17 ldw r2,-16(fp) - f144: e0bff915 stw r2,-28(fp) - alt_irq_context status; - - if (id < ALT_NIRQ) - f148: e0bff917 ldw r2,-28(fp) - f14c: 10800808 cmpgei r2,r2,32 - f150: 1000291e bne r2,zero,f1f8 -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - f154: 0005303a rdctl r2,status - f158: e0bff715 stw r2,-36(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - f15c: e0fff717 ldw r3,-36(fp) - f160: 00bfff84 movi r2,-2 - f164: 1884703a and r2,r3,r2 - f168: 1001703a wrctl status,r2 - - return context; - f16c: e0bff717 ldw r2,-36(fp) - * interrupts are disabled while the handler tables are updated to ensure - * that an interrupt doesn't occur while the tables are in an inconsistant - * state. - */ - - status = alt_irq_disable_all(); - f170: e0bff815 stw r2,-32(fp) - - alt_irq[id].handler = isr; - f174: e0bff917 ldw r2,-28(fp) - f178: 00c00074 movhi r3,1 - f17c: 18d09304 addi r3,r3,16972 - f180: 100490fa slli r2,r2,3 - f184: 10c7883a add r3,r2,r3 - f188: e0bffd17 ldw r2,-12(fp) - f18c: 18800015 stw r2,0(r3) - alt_irq[id].context = isr_context; - f190: e0bff917 ldw r2,-28(fp) - f194: 00c00074 movhi r3,1 - f198: 18d09304 addi r3,r3,16972 - f19c: 100490fa slli r2,r2,3 - f1a0: 10c5883a add r2,r2,r3 - f1a4: 10c00104 addi r3,r2,4 - f1a8: e0bffe17 ldw r2,-8(fp) - f1ac: 18800015 stw r2,0(r3) - - rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); - f1b0: e0bffd17 ldw r2,-12(fp) - f1b4: 1005003a cmpeq r2,r2,zero - f1b8: 1000051e bne r2,zero,f1d0 - f1bc: e17ff917 ldw r5,-28(fp) - f1c0: e13ffb17 ldw r4,-20(fp) - f1c4: 000ef940 call ef94 - f1c8: e0bfff15 stw r2,-4(fp) - f1cc: 00000406 br f1e0 - f1d0: e17ff917 ldw r5,-28(fp) - f1d4: e13ffb17 ldw r4,-20(fp) - f1d8: 000f0300 call f030 - f1dc: e0bfff15 stw r2,-4(fp) - f1e0: e0bfff17 ldw r2,-4(fp) - f1e4: e0bffa15 stw r2,-24(fp) - f1e8: e0bff817 ldw r2,-32(fp) - f1ec: e0bff615 stw r2,-40(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - f1f0: e0bff617 ldw r2,-40(fp) - f1f4: 1001703a wrctl status,r2 - - alt_irq_enable_all(status); - } - - return rc; - f1f8: e0bffa17 ldw r2,-24(fp) -} - f1fc: e037883a mov sp,fp - f200: dfc00117 ldw ra,4(sp) - f204: df000017 ldw fp,0(sp) - f208: dec00204 addi sp,sp,8 - f20c: f800283a ret - -0000f210 : - * If the device can not be succesfully opened, then the input file descriptor - * remains unchanged. - */ - -static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) -{ - f210: defff804 addi sp,sp,-32 - f214: dfc00715 stw ra,28(sp) - f218: df000615 stw fp,24(sp) - f21c: dc000515 stw r16,20(sp) - f220: df000504 addi fp,sp,20 - f224: e13ffc15 stw r4,-16(fp) - f228: e17ffd15 stw r5,-12(fp) - f22c: e1bffe15 stw r6,-8(fp) - f230: e1ffff15 stw r7,-4(fp) - int old; - - old = open (name, flags, mode); - f234: e13ffd17 ldw r4,-12(fp) - f238: e17ffe17 ldw r5,-8(fp) - f23c: e1bfff17 ldw r6,-4(fp) - f240: 000f4580 call f458 - f244: e0bffb15 stw r2,-20(fp) - - if (old >= 0) - f248: e0bffb17 ldw r2,-20(fp) - f24c: 1004803a cmplt r2,r2,zero - f250: 10001f1e bne r2,zero,f2d0 - { - fd->dev = alt_fd_list[old].dev; - f254: e13ffb17 ldw r4,-20(fp) - f258: 04000074 movhi r16,1 - f25c: 84037e04 addi r16,r16,3576 - f260: 01400304 movi r5,12 - f264: 0002b2c0 call 2b2c <__mulsi3> - f268: 1405883a add r2,r2,r16 - f26c: 10c00017 ldw r3,0(r2) - f270: e0bffc17 ldw r2,-16(fp) - f274: 10c00015 stw r3,0(r2) - fd->priv = alt_fd_list[old].priv; - f278: e13ffb17 ldw r4,-20(fp) - f27c: 04000074 movhi r16,1 - f280: 84037e04 addi r16,r16,3576 - f284: 01400304 movi r5,12 - f288: 0002b2c0 call 2b2c <__mulsi3> - f28c: 1405883a add r2,r2,r16 - f290: 10800104 addi r2,r2,4 - f294: 10c00017 ldw r3,0(r2) - f298: e0bffc17 ldw r2,-16(fp) - f29c: 10c00115 stw r3,4(r2) - fd->fd_flags = alt_fd_list[old].fd_flags; - f2a0: e13ffb17 ldw r4,-20(fp) - f2a4: 04000074 movhi r16,1 - f2a8: 84037e04 addi r16,r16,3576 - f2ac: 01400304 movi r5,12 - f2b0: 0002b2c0 call 2b2c <__mulsi3> - f2b4: 1405883a add r2,r2,r16 - f2b8: 10800204 addi r2,r2,8 - f2bc: 10c00017 ldw r3,0(r2) - f2c0: e0bffc17 ldw r2,-16(fp) - f2c4: 10c00215 stw r3,8(r2) - - alt_release_fd (old); - f2c8: e13ffb17 ldw r4,-20(fp) - f2cc: 000cc4c0 call cc4c - } -} - f2d0: e037883a mov sp,fp - f2d4: dfc00217 ldw ra,8(sp) - f2d8: df000117 ldw fp,4(sp) - f2dc: dc000017 ldw r16,0(sp) - f2e0: dec00304 addi sp,sp,12 - f2e4: f800283a ret - -0000f2e8 : - */ - -void alt_io_redirect(const char* stdout_dev, - const char* stdin_dev, - const char* stderr_dev) -{ - f2e8: defffb04 addi sp,sp,-20 - f2ec: dfc00415 stw ra,16(sp) - f2f0: df000315 stw fp,12(sp) - f2f4: df000304 addi fp,sp,12 - f2f8: e13ffd15 stw r4,-12(fp) - f2fc: e17ffe15 stw r5,-8(fp) - f300: e1bfff15 stw r6,-4(fp) - /* Redirect the channels */ - - alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); - f304: 01000074 movhi r4,1 - f308: 21038104 addi r4,r4,3588 - f30c: e17ffd17 ldw r5,-12(fp) - f310: 01800044 movi r6,1 - f314: 01c07fc4 movi r7,511 - f318: 000f2100 call f210 - alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); - f31c: 01000074 movhi r4,1 - f320: 21037e04 addi r4,r4,3576 - f324: e17ffe17 ldw r5,-8(fp) - f328: 000d883a mov r6,zero - f32c: 01c07fc4 movi r7,511 - f330: 000f2100 call f210 - alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); - f334: 01000074 movhi r4,1 - f338: 21038404 addi r4,r4,3600 - f33c: e17fff17 ldw r5,-4(fp) - f340: 01800044 movi r6,1 - f344: 01c07fc4 movi r7,511 - f348: 000f2100 call f210 -} - f34c: e037883a mov sp,fp - f350: dfc00117 ldw ra,4(sp) - f354: df000017 ldw fp,0(sp) - f358: dec00204 addi sp,sp,8 - f35c: f800283a ret - -0000f360 : - * performed for devices. Filesystems are required to handle the ioctl() call - * themselves, and report the error from the filesystems open() function. - */ - -static int alt_file_locked (alt_fd* fd) -{ - f360: defffa04 addi sp,sp,-24 - f364: dfc00515 stw ra,20(sp) - f368: df000415 stw fp,16(sp) - f36c: dc000315 stw r16,12(sp) - f370: df000304 addi fp,sp,12 - f374: e13ffe15 stw r4,-8(fp) - - /* - * Mark the file descriptor as belonging to a device. - */ - - fd->fd_flags |= ALT_FD_DEV; - f378: e0bffe17 ldw r2,-8(fp) - f37c: 10800217 ldw r2,8(r2) - f380: 10d00034 orhi r3,r2,16384 - f384: e0bffe17 ldw r2,-8(fp) - f388: 10c00215 stw r3,8(r2) - /* - * Loop through all current file descriptors searching for one that's locked - * for exclusive access. If a match is found, generate an error. - */ - - for (i = 0; i <= alt_max_fd; i++) - f38c: e03ffd15 stw zero,-12(fp) - f390: 00002306 br f420 - { - if ((alt_fd_list[i].dev == fd->dev) && - f394: e13ffd17 ldw r4,-12(fp) - f398: 04000074 movhi r16,1 - f39c: 84037e04 addi r16,r16,3576 - f3a0: 01400304 movi r5,12 - f3a4: 0002b2c0 call 2b2c <__mulsi3> - f3a8: 1405883a add r2,r2,r16 - f3ac: 10c00017 ldw r3,0(r2) - f3b0: e0bffe17 ldw r2,-8(fp) - f3b4: 10800017 ldw r2,0(r2) - f3b8: 1880161e bne r3,r2,f414 - f3bc: e13ffd17 ldw r4,-12(fp) - f3c0: 04000074 movhi r16,1 - f3c4: 84037e04 addi r16,r16,3576 - f3c8: 01400304 movi r5,12 - f3cc: 0002b2c0 call 2b2c <__mulsi3> - f3d0: 1405883a add r2,r2,r16 - f3d4: 10800204 addi r2,r2,8 - f3d8: 10800017 ldw r2,0(r2) - f3dc: 1004403a cmpge r2,r2,zero - f3e0: 10000c1e bne r2,zero,f414 - f3e4: e13ffd17 ldw r4,-12(fp) - f3e8: 01400304 movi r5,12 - f3ec: 0002b2c0 call 2b2c <__mulsi3> - f3f0: 1007883a mov r3,r2 - f3f4: 00800074 movhi r2,1 - f3f8: 10837e04 addi r2,r2,3576 - f3fc: 1887883a add r3,r3,r2 - f400: e0bffe17 ldw r2,-8(fp) - f404: 18800326 beq r3,r2,f414 - (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && - (&alt_fd_list[i] != fd)) - { - return -EACCES; - f408: 00bffcc4 movi r2,-13 - f40c: e0bfff15 stw r2,-4(fp) - f410: 00000a06 br f43c - /* - * Loop through all current file descriptors searching for one that's locked - * for exclusive access. If a match is found, generate an error. - */ - - for (i = 0; i <= alt_max_fd; i++) - f414: e0bffd17 ldw r2,-12(fp) - f418: 10800044 addi r2,r2,1 - f41c: e0bffd15 stw r2,-12(fp) - f420: 00800074 movhi r2,1 - f424: 10884a04 addi r2,r2,8488 - f428: 10800017 ldw r2,0(r2) - f42c: 1007883a mov r3,r2 - f430: e0bffd17 ldw r2,-12(fp) - f434: 18bfd72e bgeu r3,r2,f394 - } - } - - /* The device is not locked */ - - return 0; - f438: e03fff15 stw zero,-4(fp) - f43c: e0bfff17 ldw r2,-4(fp) -} - f440: e037883a mov sp,fp - f444: dfc00217 ldw ra,8(sp) - f448: df000117 ldw fp,4(sp) - f44c: dc000017 ldw r16,0(sp) - f450: dec00304 addi sp,sp,12 - f454: f800283a ret - -0000f458 : - * - * ALT_OPEN is mapped onto the open() system call in alt_syscall.h - */ - -int ALT_OPEN (const char* file, int flags, int mode) -{ - f458: defff404 addi sp,sp,-48 - f45c: dfc00b15 stw ra,44(sp) - f460: df000a15 stw fp,40(sp) - f464: df000a04 addi fp,sp,40 - f468: e13ffb15 stw r4,-20(fp) - f46c: e17ffc15 stw r5,-16(fp) - f470: e1bffd15 stw r6,-12(fp) - alt_dev* dev; - alt_fd* fd; - int index = -1; - f474: 00bfffc4 movi r2,-1 - f478: e0bff815 stw r2,-32(fp) - int status = -ENODEV; - f47c: 00bffb44 movi r2,-19 - f480: e0bff715 stw r2,-36(fp) - int isafs = 0; - f484: e03ff615 stw zero,-40(fp) - /* - * Check the device list, to see if a device with a matching name is - * registered. - */ - - if (!(dev = alt_find_dev (file, &alt_dev_list))) - f488: e13ffb17 ldw r4,-20(fp) - f48c: 01400074 movhi r5,1 - f490: 29484804 addi r5,r5,8480 - f494: 000f8080 call f808 - f498: e0bffa15 stw r2,-24(fp) - f49c: e0bffa17 ldw r2,-24(fp) - f4a0: 1004c03a cmpne r2,r2,zero - f4a4: 1000051e bne r2,zero,f4bc - { - /* No matching device, so try the filesystem list */ - - dev = alt_find_file (file); - f4a8: e13ffb17 ldw r4,-20(fp) - f4ac: 000f89c0 call f89c - f4b0: e0bffa15 stw r2,-24(fp) - isafs = 1; - f4b4: 00800044 movi r2,1 - f4b8: e0bff615 stw r2,-40(fp) - - /* - * If a matching device or filesystem is found, allocate a file descriptor. - */ - - if (dev) - f4bc: e0bffa17 ldw r2,-24(fp) - f4c0: 1005003a cmpeq r2,r2,zero - f4c4: 1000311e bne r2,zero,f58c - { - if ((index = alt_get_fd (dev)) < 0) - f4c8: e13ffa17 ldw r4,-24(fp) - f4cc: 000f9bc0 call f9bc - f4d0: e0bff815 stw r2,-32(fp) - f4d4: e0bff817 ldw r2,-32(fp) - f4d8: 1004403a cmpge r2,r2,zero - f4dc: 1000031e bne r2,zero,f4ec - { - status = index; - f4e0: e0bff817 ldw r2,-32(fp) - f4e4: e0bff715 stw r2,-36(fp) - f4e8: 00002a06 br f594 - } - else - { - fd = &alt_fd_list[index]; - f4ec: e13ff817 ldw r4,-32(fp) - f4f0: 01400304 movi r5,12 - f4f4: 0002b2c0 call 2b2c <__mulsi3> - f4f8: 1007883a mov r3,r2 - f4fc: 00800074 movhi r2,1 - f500: 10837e04 addi r2,r2,3576 - f504: 1885883a add r2,r3,r2 - f508: e0bff915 stw r2,-28(fp) - fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); - f50c: e0fffc17 ldw r3,-16(fp) - f510: 00900034 movhi r2,16384 - f514: 10bfffc4 addi r2,r2,-1 - f518: 1886703a and r3,r3,r2 - f51c: e0bff917 ldw r2,-28(fp) - f520: 10c00215 stw r3,8(r2) - - /* If this is a device, ensure it isn't already locked */ - - if (isafs || ((status = alt_file_locked (fd)) >= 0)) - f524: e0bff617 ldw r2,-40(fp) - f528: 1004c03a cmpne r2,r2,zero - f52c: 1000061e bne r2,zero,f548 - f530: e13ff917 ldw r4,-28(fp) - f534: 000f3600 call f360 - f538: e0bff715 stw r2,-36(fp) - f53c: e0bff717 ldw r2,-36(fp) - f540: 1004803a cmplt r2,r2,zero - f544: 1000131e bne r2,zero,f594 - /* - * If the device or filesystem provides an open() callback function, - * call it now to perform any device/filesystem specific operations. - */ - - status = (dev->open) ? dev->open(fd, file, flags, mode): 0; - f548: e0bffa17 ldw r2,-24(fp) - f54c: 10800317 ldw r2,12(r2) - f550: 1005003a cmpeq r2,r2,zero - f554: 1000091e bne r2,zero,f57c - f558: e0bffa17 ldw r2,-24(fp) - f55c: 10800317 ldw r2,12(r2) - f560: e13ff917 ldw r4,-28(fp) - f564: e17ffb17 ldw r5,-20(fp) - f568: e1bffc17 ldw r6,-16(fp) - f56c: e1fffd17 ldw r7,-12(fp) - f570: 103ee83a callr r2 - f574: e0bfff15 stw r2,-4(fp) - f578: 00000106 br f580 - f57c: e03fff15 stw zero,-4(fp) - f580: e0bfff17 ldw r2,-4(fp) - f584: e0bff715 stw r2,-36(fp) - f588: 00000206 br f594 - } - } - } - else - { - status = -ENODEV; - f58c: 00bffb44 movi r2,-19 - f590: e0bff715 stw r2,-36(fp) - } - - /* Allocation failed, so clean up and return an error */ - - if (status < 0) - f594: e0bff717 ldw r2,-36(fp) - f598: 1004403a cmpge r2,r2,zero - f59c: 1000091e bne r2,zero,f5c4 - { - alt_release_fd (index); - f5a0: e13ff817 ldw r4,-32(fp) - f5a4: 000cc4c0 call cc4c - ALT_ERRNO = -status; - f5a8: 000f5e40 call f5e4 - f5ac: e0fff717 ldw r3,-36(fp) - f5b0: 00c7c83a sub r3,zero,r3 - f5b4: 10c00015 stw r3,0(r2) - return -1; - f5b8: 00bfffc4 movi r2,-1 - f5bc: e0bffe15 stw r2,-8(fp) - f5c0: 00000206 br f5cc - } - - /* return the reference upon success */ - - return index; - f5c4: e0bff817 ldw r2,-32(fp) - f5c8: e0bffe15 stw r2,-8(fp) - f5cc: e0bffe17 ldw r2,-8(fp) -} - f5d0: e037883a mov sp,fp - f5d4: dfc00117 ldw ra,4(sp) - f5d8: df000017 ldw fp,0(sp) - f5dc: dec00204 addi sp,sp,8 - f5e0: f800283a ret - -0000f5e4 : -#undef errno - -extern int errno; - -static ALT_INLINE int* alt_get_errno(void) -{ - f5e4: defffd04 addi sp,sp,-12 - f5e8: dfc00215 stw ra,8(sp) - f5ec: df000115 stw fp,4(sp) - f5f0: df000104 addi fp,sp,4 - return ((alt_errno) ? alt_errno() : &errno); - f5f4: 00800074 movhi r2,1 - f5f8: 10884b04 addi r2,r2,8492 - f5fc: 10800017 ldw r2,0(r2) - f600: 1005003a cmpeq r2,r2,zero - f604: 1000061e bne r2,zero,f620 - f608: 00800074 movhi r2,1 - f60c: 10884b04 addi r2,r2,8492 - f610: 10800017 ldw r2,0(r2) - f614: 103ee83a callr r2 - f618: e0bfff15 stw r2,-4(fp) - f61c: 00000306 br f62c - f620: 00800074 movhi r2,1 - f624: 108f3e04 addi r2,r2,15608 - f628: e0bfff15 stw r2,-4(fp) - f62c: e0bfff17 ldw r2,-4(fp) -} - f630: e037883a mov sp,fp - f634: dfc00117 ldw ra,4(sp) - f638: df000017 ldw fp,0(sp) - f63c: dec00204 addi sp,sp,8 - f640: f800283a ret - -0000f644 : - * alarms. Alternatively an alarm can unregister itself by returning zero when - * the alarm executes. - */ - -void alt_alarm_stop (alt_alarm* alarm) -{ - f644: defffa04 addi sp,sp,-24 - f648: df000515 stw fp,20(sp) - f64c: df000504 addi fp,sp,20 - f650: e13fff15 stw r4,-4(fp) -static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE - alt_irq_disable_all (void) -{ - alt_irq_context context; - - NIOS2_READ_STATUS (context); - f654: 0005303a rdctl r2,status - f658: e0bffd15 stw r2,-12(fp) - - NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); - f65c: e0fffd17 ldw r3,-12(fp) - f660: 00bfff84 movi r2,-2 - f664: 1884703a and r2,r3,r2 - f668: 1001703a wrctl status,r2 - - return context; - f66c: e0bffd17 ldw r2,-12(fp) - alt_irq_context irq_context; - - irq_context = alt_irq_disable_all(); - f670: e0bffe15 stw r2,-8(fp) - alt_llist_remove (&alarm->llist); - f674: e0bfff17 ldw r2,-4(fp) - f678: e0bffc15 stw r2,-16(fp) - * input argument is the element to remove. - */ - -static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) -{ - entry->next->previous = entry->previous; - f67c: e0bffc17 ldw r2,-16(fp) - f680: 10c00017 ldw r3,0(r2) - f684: e0bffc17 ldw r2,-16(fp) - f688: 10800117 ldw r2,4(r2) - f68c: 18800115 stw r2,4(r3) - entry->previous->next = entry->next; - f690: e0bffc17 ldw r2,-16(fp) - f694: 10c00117 ldw r3,4(r2) - f698: e0bffc17 ldw r2,-16(fp) - f69c: 10800017 ldw r2,0(r2) - f6a0: 18800015 stw r2,0(r3) - /* - * Set the entry to point to itself, so that any further calls to - * alt_llist_remove() are harmless. - */ - - entry->previous = entry; - f6a4: e0fffc17 ldw r3,-16(fp) - f6a8: e0bffc17 ldw r2,-16(fp) - f6ac: 18800115 stw r2,4(r3) - entry->next = entry; - f6b0: e0fffc17 ldw r3,-16(fp) - f6b4: e0bffc17 ldw r2,-16(fp) - f6b8: 18800015 stw r2,0(r3) - f6bc: e0bffe17 ldw r2,-8(fp) - f6c0: e0bffb15 stw r2,-20(fp) - status &= ~NIOS2_STATUS_PIE_MSK; - status |= (context & NIOS2_STATUS_PIE_MSK); - - NIOS2_WRITE_STATUS (status); -#else - NIOS2_WRITE_STATUS (context); - f6c4: e0bffb17 ldw r2,-20(fp) - f6c8: 1001703a wrctl status,r2 - alt_irq_enable_all (irq_context); -} - f6cc: e037883a mov sp,fp - f6d0: df000017 ldw fp,0(sp) - f6d4: dec00104 addi sp,sp,4 - f6d8: f800283a ret - -0000f6dc : - * - * alt_tick() is expected to run at interrupt level. - */ - -void alt_tick (void) -{ - f6dc: defffb04 addi sp,sp,-20 - f6e0: dfc00415 stw ra,16(sp) - f6e4: df000315 stw fp,12(sp) - f6e8: df000304 addi fp,sp,12 - alt_alarm* next; - alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; - f6ec: d0a01117 ldw r2,-32700(gp) - f6f0: e0bffe15 stw r2,-8(fp) - - alt_u32 next_callback; - - /* update the tick counter */ - - _alt_nticks++; - f6f4: d0a70617 ldw r2,-25576(gp) - f6f8: 10800044 addi r2,r2,1 - f6fc: d0a70615 stw r2,-25576(gp) - - /* process the registered callbacks */ - - while (alarm != (alt_alarm*) &alt_alarm_list) - f700: 00003106 br f7c8 - { - next = (alt_alarm*) alarm->llist.next; - f704: e0bffe17 ldw r2,-8(fp) - f708: 10800017 ldw r2,0(r2) - f70c: e0bfff15 stw r2,-4(fp) - /* - * Upon the tick-counter rolling over it is safe to clear the - * roll-over flag; once the flag is cleared this (or subsequnt) - * tick events are enabled to generate an alarm event. - */ - if ((alarm->rollover) && (_alt_nticks == 0)) - f710: e0bffe17 ldw r2,-8(fp) - f714: 10800403 ldbu r2,16(r2) - f718: 10803fcc andi r2,r2,255 - f71c: 1005003a cmpeq r2,r2,zero - f720: 1000051e bne r2,zero,f738 - f724: d0a70617 ldw r2,-25576(gp) - f728: 1004c03a cmpne r2,r2,zero - f72c: 1000021e bne r2,zero,f738 - { - alarm->rollover = 0; - f730: e0bffe17 ldw r2,-8(fp) - f734: 10000405 stb zero,16(r2) - } - - /* if the alarm period has expired, make the callback */ - if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) - f738: e0bffe17 ldw r2,-8(fp) - f73c: 10c00217 ldw r3,8(r2) - f740: d0a70617 ldw r2,-25576(gp) - f744: 10c01e36 bltu r2,r3,f7c0 - f748: e0bffe17 ldw r2,-8(fp) - f74c: 10800403 ldbu r2,16(r2) - f750: 10803fcc andi r2,r2,255 - f754: 1004c03a cmpne r2,r2,zero - f758: 1000191e bne r2,zero,f7c0 - { - next_callback = alarm->callback (alarm->context); - f75c: e0bffe17 ldw r2,-8(fp) - f760: 10c00317 ldw r3,12(r2) - f764: e0bffe17 ldw r2,-8(fp) - f768: 11000517 ldw r4,20(r2) - f76c: 183ee83a callr r3 - f770: e0bffd15 stw r2,-12(fp) - - /* deactivate the alarm if the return value is zero */ - - if (next_callback == 0) - f774: e0bffd17 ldw r2,-12(fp) - f778: 1004c03a cmpne r2,r2,zero - f77c: 1000031e bne r2,zero,f78c - { - alt_alarm_stop (alarm); - f780: e13ffe17 ldw r4,-8(fp) - f784: 000f6440 call f644 - f788: 00000d06 br f7c0 - } - else - { - alarm->time += next_callback; - f78c: e0bffe17 ldw r2,-8(fp) - f790: 10c00217 ldw r3,8(r2) - f794: e0bffd17 ldw r2,-12(fp) - f798: 1887883a add r3,r3,r2 - f79c: e0bffe17 ldw r2,-8(fp) - f7a0: 10c00215 stw r3,8(r2) - /* - * If the desired alarm time causes a roll-over, set the rollover - * flag. This will prevent the subsequent tick event from causing - * an alarm too early. - */ - if(alarm->time < _alt_nticks) - f7a4: e0bffe17 ldw r2,-8(fp) - f7a8: 10c00217 ldw r3,8(r2) - f7ac: d0a70617 ldw r2,-25576(gp) - f7b0: 1880032e bgeu r3,r2,f7c0 - { - alarm->rollover = 1; - f7b4: e0fffe17 ldw r3,-8(fp) - f7b8: 00800044 movi r2,1 - f7bc: 18800405 stb r2,16(r3) - } - } - } - alarm = next; - f7c0: e0bfff17 ldw r2,-4(fp) - f7c4: e0bffe15 stw r2,-8(fp) - - _alt_nticks++; - - /* process the registered callbacks */ - - while (alarm != (alt_alarm*) &alt_alarm_list) - f7c8: d0e01104 addi r3,gp,-32700 - f7cc: e0bffe17 ldw r2,-8(fp) - f7d0: 10ffcc1e bne r2,r3,f704 - /* - * Update the operating system specific timer facilities. - */ - - ALT_OS_TIME_TICK(); -} - f7d4: e037883a mov sp,fp - f7d8: dfc00117 ldw ra,4(sp) - f7dc: df000017 ldw fp,0(sp) - f7e0: dec00204 addi sp,sp,8 - f7e4: f800283a ret - -0000f7e8 : -/* - * To initialize the internal interrupt controller, just clear the IENABLE - * register so that all possible IRQs are disabled. - */ -void altera_nios2_qsys_irq_init(void) -{ - f7e8: deffff04 addi sp,sp,-4 - f7ec: df000015 stw fp,0(sp) - f7f0: d839883a mov fp,sp - NIOS2_WRITE_IENABLE(0); - f7f4: 000170fa wrctl ienable,zero -} - f7f8: e037883a mov sp,fp - f7fc: df000017 ldw fp,0(sp) - f800: dec00104 addi sp,sp,4 - f804: f800283a ret - -0000f808 : - * "name" must be an exact match for the devices registered name for a match to - * be found. - */ - -alt_dev* alt_find_dev(const char* name, alt_llist* llist) -{ - f808: defff904 addi sp,sp,-28 - f80c: dfc00615 stw ra,24(sp) - f810: df000515 stw fp,20(sp) - f814: df000504 addi fp,sp,20 - f818: e13ffd15 stw r4,-12(fp) - f81c: e17ffe15 stw r5,-8(fp) - alt_dev* next = (alt_dev*) llist->next; - f820: e0bffe17 ldw r2,-8(fp) - f824: 10800017 ldw r2,0(r2) - f828: e0bffc15 stw r2,-16(fp) - alt_32 len; - - len = strlen(name) + 1; - f82c: e13ffd17 ldw r4,-12(fp) - f830: 0002c380 call 2c38 - f834: 10800044 addi r2,r2,1 - f838: e0bffb15 stw r2,-20(fp) - /* - * Check each list entry in turn, until a match is found, or we reach the - * end of the list (i.e. next winds up pointing back to the list head). - */ - - while (next != (alt_dev*) llist) - f83c: 00000d06 br f874 - /* - * memcmp() is used here rather than strcmp() in order to reduce the size - * of the executable. - */ - - if (!memcmp (next->name, name, len)) - f840: e0bffc17 ldw r2,-16(fp) - f844: 11000217 ldw r4,8(r2) - f848: e1bffb17 ldw r6,-20(fp) - f84c: e17ffd17 ldw r5,-12(fp) - f850: 000fad80 call fad8 - f854: 1004c03a cmpne r2,r2,zero - f858: 1000031e bne r2,zero,f868 - { - /* match found */ - - return next; - f85c: e0bffc17 ldw r2,-16(fp) - f860: e0bfff15 stw r2,-4(fp) - f864: 00000706 br f884 - } - next = (alt_dev*) next->llist.next; - f868: e0bffc17 ldw r2,-16(fp) - f86c: 10800017 ldw r2,0(r2) - f870: e0bffc15 stw r2,-16(fp) - /* - * Check each list entry in turn, until a match is found, or we reach the - * end of the list (i.e. next winds up pointing back to the list head). - */ - - while (next != (alt_dev*) llist) - f874: e0fffe17 ldw r3,-8(fp) - f878: e0bffc17 ldw r2,-16(fp) - f87c: 10fff01e bne r2,r3,f840 - next = (alt_dev*) next->llist.next; - } - - /* No match found */ - - return NULL; - f880: e03fff15 stw zero,-4(fp) - f884: e0bfff17 ldw r2,-4(fp) -} - f888: e037883a mov sp,fp - f88c: dfc00117 ldw ra,4(sp) - f890: df000017 ldw fp,0(sp) - f894: dec00204 addi sp,sp,8 - f898: f800283a ret - -0000f89c : - * either '/' or '\0' is the prefix of the filename. For example the filename: - * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". - */ - -alt_dev* alt_find_file (const char* name) -{ - f89c: defffa04 addi sp,sp,-24 - f8a0: dfc00515 stw ra,20(sp) - f8a4: df000415 stw fp,16(sp) - f8a8: df000404 addi fp,sp,16 - f8ac: e13ffe15 stw r4,-8(fp) - alt_dev* next = (alt_dev*) alt_fs_list.next; - f8b0: 00800074 movhi r2,1 - f8b4: 10884604 addi r2,r2,8472 - f8b8: 10800017 ldw r2,0(r2) - f8bc: e0bffd15 stw r2,-12(fp) - /* - * Check each list entry in turn, until a match is found, or we reach the - * end of the list (i.e. next winds up pointing back to the list head). - */ - - while (next != (alt_dev*) &alt_fs_list) - f8c0: 00003306 br f990 - { - len = strlen(next->name); - f8c4: e0bffd17 ldw r2,-12(fp) - f8c8: 11000217 ldw r4,8(r2) - f8cc: 0002c380 call 2c38 - f8d0: e0bffc15 stw r2,-16(fp) - - if (next->name[len-1] == '/') - f8d4: e0bffd17 ldw r2,-12(fp) - f8d8: 10c00217 ldw r3,8(r2) - f8dc: e0bffc17 ldw r2,-16(fp) - f8e0: 1885883a add r2,r3,r2 - f8e4: 10bfffc4 addi r2,r2,-1 - f8e8: 10800003 ldbu r2,0(r2) - f8ec: 10803fcc andi r2,r2,255 - f8f0: 1080201c xori r2,r2,128 - f8f4: 10bfe004 addi r2,r2,-128 - f8f8: 10800bd8 cmpnei r2,r2,47 - f8fc: 1000031e bne r2,zero,f90c - { - len -= 1; - f900: e0bffc17 ldw r2,-16(fp) - f904: 10bfffc4 addi r2,r2,-1 - f908: e0bffc15 stw r2,-16(fp) - } - - if (((name[len] == '/') || (name[len] == '\0')) && - f90c: e0bffc17 ldw r2,-16(fp) - f910: 1007883a mov r3,r2 - f914: e0bffe17 ldw r2,-8(fp) - f918: 1885883a add r2,r3,r2 - f91c: 10800003 ldbu r2,0(r2) - f920: 10803fcc andi r2,r2,255 - f924: 1080201c xori r2,r2,128 - f928: 10bfe004 addi r2,r2,-128 - f92c: 10800be0 cmpeqi r2,r2,47 - f930: 10000a1e bne r2,zero,f95c - f934: e0bffc17 ldw r2,-16(fp) - f938: 1007883a mov r3,r2 - f93c: e0bffe17 ldw r2,-8(fp) - f940: 1885883a add r2,r3,r2 - f944: 10800003 ldbu r2,0(r2) - f948: 10803fcc andi r2,r2,255 - f94c: 1080201c xori r2,r2,128 - f950: 10bfe004 addi r2,r2,-128 - f954: 1004c03a cmpne r2,r2,zero - f958: 10000a1e bne r2,zero,f984 - f95c: e0bffd17 ldw r2,-12(fp) - f960: 11000217 ldw r4,8(r2) - f964: e1bffc17 ldw r6,-16(fp) - f968: e17ffe17 ldw r5,-8(fp) - f96c: 000fad80 call fad8 - f970: 1004c03a cmpne r2,r2,zero - f974: 1000031e bne r2,zero,f984 - !memcmp (next->name, name, len)) - { - /* match found */ - - return next; - f978: e0bffd17 ldw r2,-12(fp) - f97c: e0bfff15 stw r2,-4(fp) - f980: 00000806 br f9a4 - } - next = (alt_dev*) next->llist.next; - f984: e0bffd17 ldw r2,-12(fp) - f988: 10800017 ldw r2,0(r2) - f98c: e0bffd15 stw r2,-12(fp) - /* - * Check each list entry in turn, until a match is found, or we reach the - * end of the list (i.e. next winds up pointing back to the list head). - */ - - while (next != (alt_dev*) &alt_fs_list) - f990: 00c00074 movhi r3,1 - f994: 18c84604 addi r3,r3,8472 - f998: e0bffd17 ldw r2,-12(fp) - f99c: 10ffc91e bne r2,r3,f8c4 - next = (alt_dev*) next->llist.next; - } - - /* No match found */ - - return NULL; - f9a0: e03fff15 stw zero,-4(fp) - f9a4: e0bfff17 ldw r2,-4(fp) -} - f9a8: e037883a mov sp,fp - f9ac: dfc00117 ldw ra,4(sp) - f9b0: df000017 ldw fp,0(sp) - f9b4: dec00204 addi sp,sp,8 - f9b8: f800283a ret - -0000f9bc : - * the offset of the file descriptor within the file descriptor array). A - * negative value indicates failure. - */ - -int alt_get_fd (alt_dev* dev) -{ - f9bc: defffa04 addi sp,sp,-24 - f9c0: dfc00515 stw ra,20(sp) - f9c4: df000415 stw fp,16(sp) - f9c8: dc000315 stw r16,12(sp) - f9cc: df000304 addi fp,sp,12 - f9d0: e13fff15 stw r4,-4(fp) - alt_32 i; - int rc = -EMFILE; - f9d4: 00bffa04 movi r2,-24 - f9d8: e0bffd15 stw r2,-12(fp) - * indicates the highest file descriptor ever allocated. This is used to - * improve efficency when searching the file descriptor list, and - * therefore reduce contention on the alt_fd_list_lock semaphore. - */ - - for (i = 0; i < ALT_MAX_FD; i++) - f9dc: e03ffe15 stw zero,-8(fp) - f9e0: 00002006 br fa64 - { - if (!alt_fd_list[i].dev) - f9e4: e13ffe17 ldw r4,-8(fp) - f9e8: 04000074 movhi r16,1 - f9ec: 84037e04 addi r16,r16,3576 - f9f0: 01400304 movi r5,12 - f9f4: 0002b2c0 call 2b2c <__mulsi3> - f9f8: 1405883a add r2,r2,r16 - f9fc: 10800017 ldw r2,0(r2) - fa00: 1004c03a cmpne r2,r2,zero - fa04: 1000141e bne r2,zero,fa58 - { - alt_fd_list[i].dev = dev; - fa08: e13ffe17 ldw r4,-8(fp) - fa0c: 04000074 movhi r16,1 - fa10: 84037e04 addi r16,r16,3576 - fa14: 01400304 movi r5,12 - fa18: 0002b2c0 call 2b2c <__mulsi3> - fa1c: 1407883a add r3,r2,r16 - fa20: e0bfff17 ldw r2,-4(fp) - fa24: 18800015 stw r2,0(r3) - if (i > alt_max_fd) - fa28: 00800074 movhi r2,1 - fa2c: 10884a04 addi r2,r2,8488 - fa30: 10c00017 ldw r3,0(r2) - fa34: e0bffe17 ldw r2,-8(fp) - fa38: 1880040e bge r3,r2,fa4c - { - alt_max_fd = i; - fa3c: 00c00074 movhi r3,1 - fa40: 18c84a04 addi r3,r3,8488 - fa44: e0bffe17 ldw r2,-8(fp) - fa48: 18800015 stw r2,0(r3) - } - rc = i; - fa4c: e0bffe17 ldw r2,-8(fp) - fa50: e0bffd15 stw r2,-12(fp) - goto alt_get_fd_exit; - fa54: 00000606 br fa70 - * indicates the highest file descriptor ever allocated. This is used to - * improve efficency when searching the file descriptor list, and - * therefore reduce contention on the alt_fd_list_lock semaphore. - */ - - for (i = 0; i < ALT_MAX_FD; i++) - fa58: e0bffe17 ldw r2,-8(fp) - fa5c: 10800044 addi r2,r2,1 - fa60: e0bffe15 stw r2,-8(fp) - fa64: e0bffe17 ldw r2,-8(fp) - fa68: 10800810 cmplti r2,r2,32 - fa6c: 103fdd1e bne r2,zero,f9e4 - * file descriptor pool. - */ - - ALT_SEM_POST(alt_fd_list_lock); - - return rc; - fa70: e0bffd17 ldw r2,-12(fp) -} - fa74: e037883a mov sp,fp - fa78: dfc00217 ldw ra,8(sp) - fa7c: df000117 ldw fp,4(sp) - fa80: dc000017 ldw r16,0(sp) - fa84: dec00304 addi sp,sp,12 - fa88: f800283a ret - -0000fa8c : - fa8c: 200b883a mov r5,r4 - fa90: 000d883a mov r6,zero - fa94: 0009883a mov r4,zero - fa98: 000f883a mov r7,zero - fa9c: 000fb4c1 jmpi fb4c <__register_exitproc> - -0000faa0 : - faa0: defffe04 addi sp,sp,-8 - faa4: 000b883a mov r5,zero - faa8: dc000015 stw r16,0(sp) - faac: dfc00115 stw ra,4(sp) - fab0: 2021883a mov r16,r4 - fab4: 000fc840 call fc84 <__call_exitprocs> - fab8: 00800074 movhi r2,1 - fabc: 10884104 addi r2,r2,8452 - fac0: 11000017 ldw r4,0(r2) - fac4: 20800f17 ldw r2,60(r4) - fac8: 10000126 beq r2,zero,fad0 - facc: 103ee83a callr r2 - fad0: 8009883a mov r4,r16 - fad4: 000fe740 call fe74 <_exit> - -0000fad8 : - fad8: 00c000c4 movi r3,3 - fadc: 1980032e bgeu r3,r6,faec - fae0: 2144b03a or r2,r4,r5 - fae4: 10c4703a and r2,r2,r3 - fae8: 10000f26 beq r2,zero,fb28 - faec: 31ffffc4 addi r7,r6,-1 - faf0: 3000061e bne r6,zero,fb0c - faf4: 00000a06 br fb20 - faf8: 39ffffc4 addi r7,r7,-1 - fafc: 00bfffc4 movi r2,-1 - fb00: 21000044 addi r4,r4,1 - fb04: 29400044 addi r5,r5,1 - fb08: 38800526 beq r7,r2,fb20 - fb0c: 20c00003 ldbu r3,0(r4) - fb10: 28800003 ldbu r2,0(r5) - fb14: 18bff826 beq r3,r2,faf8 - fb18: 1885c83a sub r2,r3,r2 - fb1c: f800283a ret - fb20: 0005883a mov r2,zero - fb24: f800283a ret - fb28: 180f883a mov r7,r3 - fb2c: 20c00017 ldw r3,0(r4) - fb30: 28800017 ldw r2,0(r5) - fb34: 18bfed1e bne r3,r2,faec - fb38: 31bfff04 addi r6,r6,-4 - fb3c: 21000104 addi r4,r4,4 - fb40: 29400104 addi r5,r5,4 - fb44: 39bff936 bltu r7,r6,fb2c - fb48: 003fe806 br faec - -0000fb4c <__register_exitproc>: - fb4c: defffa04 addi sp,sp,-24 - fb50: 00800074 movhi r2,1 - fb54: 10884104 addi r2,r2,8452 - fb58: dc000015 stw r16,0(sp) - fb5c: 14000017 ldw r16,0(r2) - fb60: dd000415 stw r20,16(sp) - fb64: 2829883a mov r20,r5 - fb68: 81405217 ldw r5,328(r16) - fb6c: dcc00315 stw r19,12(sp) - fb70: dc800215 stw r18,8(sp) - fb74: dc400115 stw r17,4(sp) - fb78: dfc00515 stw ra,20(sp) - fb7c: 2023883a mov r17,r4 - fb80: 3027883a mov r19,r6 - fb84: 3825883a mov r18,r7 - fb88: 28002526 beq r5,zero,fc20 <__register_exitproc+0xd4> - fb8c: 29000117 ldw r4,4(r5) - fb90: 008007c4 movi r2,31 - fb94: 11002716 blt r2,r4,fc34 <__register_exitproc+0xe8> - fb98: 8800101e bne r17,zero,fbdc <__register_exitproc+0x90> - fb9c: 2105883a add r2,r4,r4 - fba0: 1085883a add r2,r2,r2 - fba4: 20c00044 addi r3,r4,1 - fba8: 1145883a add r2,r2,r5 - fbac: 0009883a mov r4,zero - fbb0: 15000215 stw r20,8(r2) - fbb4: 28c00115 stw r3,4(r5) - fbb8: 2005883a mov r2,r4 - fbbc: dfc00517 ldw ra,20(sp) - fbc0: dd000417 ldw r20,16(sp) - fbc4: dcc00317 ldw r19,12(sp) - fbc8: dc800217 ldw r18,8(sp) - fbcc: dc400117 ldw r17,4(sp) - fbd0: dc000017 ldw r16,0(sp) - fbd4: dec00604 addi sp,sp,24 - fbd8: f800283a ret - fbdc: 29802204 addi r6,r5,136 - fbe0: 00800044 movi r2,1 - fbe4: 110e983a sll r7,r2,r4 - fbe8: 30c04017 ldw r3,256(r6) - fbec: 2105883a add r2,r4,r4 - fbf0: 1085883a add r2,r2,r2 - fbf4: 1185883a add r2,r2,r6 - fbf8: 19c6b03a or r3,r3,r7 - fbfc: 14802015 stw r18,128(r2) - fc00: 14c00015 stw r19,0(r2) - fc04: 00800084 movi r2,2 - fc08: 30c04015 stw r3,256(r6) - fc0c: 88bfe31e bne r17,r2,fb9c <__register_exitproc+0x50> - fc10: 30804117 ldw r2,260(r6) - fc14: 11c4b03a or r2,r2,r7 - fc18: 30804115 stw r2,260(r6) - fc1c: 003fdf06 br fb9c <__register_exitproc+0x50> - fc20: 00800074 movhi r2,1 - fc24: 1090d304 addi r2,r2,17228 - fc28: 100b883a mov r5,r2 - fc2c: 80805215 stw r2,328(r16) - fc30: 003fd606 br fb8c <__register_exitproc+0x40> - fc34: 00800034 movhi r2,0 - fc38: 10800004 addi r2,r2,0 - fc3c: 1000021e bne r2,zero,fc48 <__register_exitproc+0xfc> - fc40: 013fffc4 movi r4,-1 - fc44: 003fdc06 br fbb8 <__register_exitproc+0x6c> - fc48: 01006404 movi r4,400 - fc4c: 103ee83a callr r2 - fc50: 1007883a mov r3,r2 - fc54: 103ffa26 beq r2,zero,fc40 <__register_exitproc+0xf4> - fc58: 80805217 ldw r2,328(r16) - fc5c: 180b883a mov r5,r3 - fc60: 18000115 stw zero,4(r3) - fc64: 18800015 stw r2,0(r3) - fc68: 80c05215 stw r3,328(r16) - fc6c: 18006215 stw zero,392(r3) - fc70: 18006315 stw zero,396(r3) - fc74: 0009883a mov r4,zero - fc78: 883fc826 beq r17,zero,fb9c <__register_exitproc+0x50> - fc7c: 003fd706 br fbdc <__register_exitproc+0x90> - -0000fc80 : - fc80: f800283a ret - -0000fc84 <__call_exitprocs>: - fc84: 00800074 movhi r2,1 - fc88: 10884104 addi r2,r2,8452 - fc8c: 10800017 ldw r2,0(r2) - fc90: defff304 addi sp,sp,-52 - fc94: df000b15 stw fp,44(sp) - fc98: d8800115 stw r2,4(sp) - fc9c: 00800034 movhi r2,0 - fca0: 10800004 addi r2,r2,0 - fca4: 1005003a cmpeq r2,r2,zero - fca8: d8800215 stw r2,8(sp) - fcac: d8800117 ldw r2,4(sp) - fcb0: dd400815 stw r21,32(sp) - fcb4: dd000715 stw r20,28(sp) - fcb8: 10805204 addi r2,r2,328 - fcbc: dfc00c15 stw ra,48(sp) - fcc0: ddc00a15 stw r23,40(sp) - fcc4: dd800915 stw r22,36(sp) - fcc8: dcc00615 stw r19,24(sp) - fccc: dc800515 stw r18,20(sp) - fcd0: dc400415 stw r17,16(sp) - fcd4: dc000315 stw r16,12(sp) - fcd8: 282b883a mov r21,r5 - fcdc: 2039883a mov fp,r4 - fce0: d8800015 stw r2,0(sp) - fce4: 2829003a cmpeq r20,r5,zero - fce8: d8800117 ldw r2,4(sp) - fcec: 14405217 ldw r17,328(r2) - fcf0: 88001026 beq r17,zero,fd34 <__call_exitprocs+0xb0> - fcf4: ddc00017 ldw r23,0(sp) - fcf8: 88800117 ldw r2,4(r17) - fcfc: 8c802204 addi r18,r17,136 - fd00: 143fffc4 addi r16,r2,-1 - fd04: 80000916 blt r16,zero,fd2c <__call_exitprocs+0xa8> - fd08: 05bfffc4 movi r22,-1 - fd0c: a000151e bne r20,zero,fd64 <__call_exitprocs+0xe0> - fd10: 8409883a add r4,r16,r16 - fd14: 2105883a add r2,r4,r4 - fd18: 1485883a add r2,r2,r18 - fd1c: 10c02017 ldw r3,128(r2) - fd20: a8c01126 beq r21,r3,fd68 <__call_exitprocs+0xe4> - fd24: 843fffc4 addi r16,r16,-1 - fd28: 85bff81e bne r16,r22,fd0c <__call_exitprocs+0x88> - fd2c: d8800217 ldw r2,8(sp) - fd30: 10003126 beq r2,zero,fdf8 <__call_exitprocs+0x174> - fd34: dfc00c17 ldw ra,48(sp) - fd38: df000b17 ldw fp,44(sp) - fd3c: ddc00a17 ldw r23,40(sp) - fd40: dd800917 ldw r22,36(sp) - fd44: dd400817 ldw r21,32(sp) - fd48: dd000717 ldw r20,28(sp) - fd4c: dcc00617 ldw r19,24(sp) - fd50: dc800517 ldw r18,20(sp) - fd54: dc400417 ldw r17,16(sp) - fd58: dc000317 ldw r16,12(sp) - fd5c: dec00d04 addi sp,sp,52 - fd60: f800283a ret - fd64: 8409883a add r4,r16,r16 - fd68: 88c00117 ldw r3,4(r17) - fd6c: 2105883a add r2,r4,r4 - fd70: 1445883a add r2,r2,r17 - fd74: 18ffffc4 addi r3,r3,-1 - fd78: 11800217 ldw r6,8(r2) - fd7c: 1c001526 beq r3,r16,fdd4 <__call_exitprocs+0x150> - fd80: 10000215 stw zero,8(r2) - fd84: 303fe726 beq r6,zero,fd24 <__call_exitprocs+0xa0> - fd88: 00c00044 movi r3,1 - fd8c: 1c06983a sll r3,r3,r16 - fd90: 90804017 ldw r2,256(r18) - fd94: 8cc00117 ldw r19,4(r17) - fd98: 1884703a and r2,r3,r2 - fd9c: 10001426 beq r2,zero,fdf0 <__call_exitprocs+0x16c> - fda0: 90804117 ldw r2,260(r18) - fda4: 1884703a and r2,r3,r2 - fda8: 10000c1e bne r2,zero,fddc <__call_exitprocs+0x158> - fdac: 2105883a add r2,r4,r4 - fdb0: 1485883a add r2,r2,r18 - fdb4: 11400017 ldw r5,0(r2) - fdb8: e009883a mov r4,fp - fdbc: 303ee83a callr r6 - fdc0: 88800117 ldw r2,4(r17) - fdc4: 98bfc81e bne r19,r2,fce8 <__call_exitprocs+0x64> - fdc8: b8800017 ldw r2,0(r23) - fdcc: 147fd526 beq r2,r17,fd24 <__call_exitprocs+0xa0> - fdd0: 003fc506 br fce8 <__call_exitprocs+0x64> - fdd4: 8c000115 stw r16,4(r17) - fdd8: 003fea06 br fd84 <__call_exitprocs+0x100> - fddc: 2105883a add r2,r4,r4 - fde0: 1485883a add r2,r2,r18 - fde4: 11000017 ldw r4,0(r2) - fde8: 303ee83a callr r6 - fdec: 003ff406 br fdc0 <__call_exitprocs+0x13c> - fdf0: 303ee83a callr r6 - fdf4: 003ff206 br fdc0 <__call_exitprocs+0x13c> - fdf8: 88800117 ldw r2,4(r17) - fdfc: 1000081e bne r2,zero,fe20 <__call_exitprocs+0x19c> - fe00: 89000017 ldw r4,0(r17) - fe04: 20000726 beq r4,zero,fe24 <__call_exitprocs+0x1a0> - fe08: b9000015 stw r4,0(r23) - fe0c: 8809883a mov r4,r17 - fe10: 00000000 call 0 <__alt_mem_onchip_memory> - fe14: bc400017 ldw r17,0(r23) - fe18: 883fb71e bne r17,zero,fcf8 <__call_exitprocs+0x74> - fe1c: 003fc506 br fd34 <__call_exitprocs+0xb0> - fe20: 89000017 ldw r4,0(r17) - fe24: 882f883a mov r23,r17 - fe28: 2023883a mov r17,r4 - fe2c: 883fb21e bne r17,zero,fcf8 <__call_exitprocs+0x74> - fe30: 003fc006 br fd34 <__call_exitprocs+0xb0> - -0000fe34 : - -/* - * Routine called on exit. - */ -static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) -{ - fe34: defffd04 addi sp,sp,-12 - fe38: df000215 stw fp,8(sp) - fe3c: df000204 addi fp,sp,8 - fe40: e13fff15 stw r4,-4(fp) - int r2 = exit_code; - fe44: e0bfff17 ldw r2,-4(fp) - fe48: e0bffe15 stw r2,-8(fp) - __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ - - __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); - -#else /* !DEBUG_STUB */ - if (r2) { - fe4c: e0bffe17 ldw r2,-8(fp) - fe50: 1005003a cmpeq r2,r2,zero - fe54: 1000021e bne r2,zero,fe60 - ALT_SIM_FAIL(); - fe58: 002af070 cmpltui zero,zero,43969 - fe5c: 00000106 br fe64 - } else { - ALT_SIM_PASS(); - fe60: 002af0b0 cmpltui zero,zero,43970 - } -#endif /* DEBUG_STUB */ -} - fe64: e037883a mov sp,fp - fe68: df000017 ldw fp,0(sp) - fe6c: dec00104 addi sp,sp,4 - fe70: f800283a ret - -0000fe74 <_exit>: - * - * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h - */ - -void ALT_EXIT (int exit_code) -{ - fe74: defffd04 addi sp,sp,-12 - fe78: dfc00215 stw ra,8(sp) - fe7c: df000115 stw fp,4(sp) - fe80: df000104 addi fp,sp,4 - fe84: e13fff15 stw r4,-4(fp) - ALT_OS_STOP(); - - /* Provide notification to the simulator that we've stopped */ - - ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); - ALT_SIM_HALT(exit_code); - fe88: e13fff17 ldw r4,-4(fp) - fe8c: 000fe340 call fe34 - - /* spin forever, since there's no where to go back to */ - - ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); - while (1); - fe90: 003fff06 br fe90 <_exit+0x1c> - fe94: 0000fc80 call fc8 diff --git a/software/qsys_tutorial_lcd4/sys_prog.c b/software/qsys_tutorial_lcd4/sys_prog.c index 853e780..bbcc395 100644 --- a/software/qsys_tutorial_lcd4/sys_prog.c +++ b/software/qsys_tutorial_lcd4/sys_prog.c @@ -1,78 +1,84 @@ -/* - * sys_prog.c - * - * Created on: 2016/12/15 - * Author: takayun - */ - -#include "sys_prog.h" -#include -#include "sys_debug.h" -#include "sys_register.h" -#include "sys_memory.h" -#include "hex_out.h" -#include "lcd_out.h" - -unsigned int inc_pc() { - if ((unsigned char)global_registers[Spc]+1 < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { - global_registers[Spc] = (unsigned char)global_registers[Spc] + 1; - } else { - global_registers[Spc] = 0; - } - return 0; -} -unsigned int add_pc(unsigned int cnt) { - int i; - for (i = 0; i < cnt; i++) inc_pc(); - return 0; -} -unsigned int set_pc(unsigned int cnt) { - global_registers[Spc]=cnt; - return 0; -} - - -enum RunMode run_proc(enum RunMode mode) { - volatile struct InstRec inst_rec; - - if (RUN_INIT == mode) { - lcd_caret_reset(); - lcd_print("Run...now"); - - global_registers[Spc] = 0; - clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); - - // �v���O�������s���֑J�� - return RUN_PROC; - } - - if (RUN_PROC == mode) { - // ���߃t�F�b�` - inst_rec = inst_fetch(); - // ���߃f�R�[�h���s - inst_decode(inst_rec); - // pc�\�� - { - char buf[5]; - sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); - print_block("pc", 2, HEX6_7); - print_block(buf, 2, HEX4_5); - } - - // �f�o�b�N�p - if ( global_registers[Ssw_run] ) delay10ms(100U); - - // �v���O�����I������ - if (inst_rec.inst != INST_END) return RUN_PROC; - return RUN_TERM; - } - - if (RUN_TERM == mode) { - lcd_caret_reset(); - lcd_print("Run...Exit"); - return RUN_STOP; - } - - // Default - return RUN_STOP; -} +/* + * sys_prog.c + * + * Created on: 2016/12/15 + * Author: takayun + */ + +#include "sys_prog.h" +#include +#include "sys_debug.h" +#include "sys_register.h" +#include "sys_memory.h" +#include "hex_out.h" +#include "lcd_out.h" + +unsigned int inc_pc() { + if ((unsigned char)global_registers[Spc]+1 < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + global_registers[Spc] = (unsigned char)global_registers[Spc] + 1; + } else { + global_registers[Spc] = 0; + } + return 0; +} +unsigned int add_pc(unsigned int cnt) { + int i; + for (i = 0; i < cnt; i++) inc_pc(); + return 0; +} +unsigned int set_pc(unsigned int cnt) { + global_registers[Spc]=cnt; + return 0; +} +unsigned int get_pc() { + if ((unsigned char)global_registers[Spc] < MEM_SIZE*MEMS_COUNT - global_current_memory*MEM_SIZE ) { + return (unsigned int)global_registers[Spc]; + } else { + return 0; + } +} + +enum RunMode run_proc(enum RunMode mode) { + volatile struct InstRec inst_rec; + + if (RUN_INIT == mode) { + lcd_caret_reset(); + lcd_print("Run...now"); + + global_registers[Spc] = 0; + clear_block(HEX0_3); clear_block(HEX4_5); clear_block(HEX6_7); + + // �v���O�������s���֑J�� + return RUN_PROC; + } + + if (RUN_PROC == mode) { + // ���߃t�F�b�` + inst_rec = inst_fetch(); + // ���߃f�R�[�h���s + inst_decode(inst_rec); + // pc�\�� + { + char buf[5]; + sprintf(buf, "%02x", (unsigned char)global_registers[Spc]); + print_block("pc", 2, HEX6_7); + print_block(buf, 2, HEX4_5); + } + + // �f�o�b�N�p + if ( global_registers[Ssw_run] ) delay10ms(100U); + + // �v���O�����I������ + if (inst_rec.inst != INST_END) return RUN_PROC; + return RUN_TERM; + } + + if (RUN_TERM == mode) { + lcd_caret_reset(); + lcd_print("Run...Exit"); + return RUN_STOP; + } + + // Default + return RUN_STOP; +} diff --git a/software/qsys_tutorial_lcd4/sys_prog.h b/software/qsys_tutorial_lcd4/sys_prog.h index 25a9b44..b112e4c 100644 --- a/software/qsys_tutorial_lcd4/sys_prog.h +++ b/software/qsys_tutorial_lcd4/sys_prog.h @@ -1,33 +1,34 @@ -/* - * sys_prog.h - * - * Created on: 2016/12/15 - * Author: takayun - */ - -#ifndef SYS_PROG_H_ -#define SYS_PROG_H_ - -/************************************************** - * Defines - **************************************************/ - -// �v���O�������s��� -enum RunMode { RUN_STOP, RUN_INIT, RUN_PROC, RUN_TERM }; - -/************************************************** - * Variables - **************************************************/ - -/************************************************** - * Functions - **************************************************/ - -// ���S��PC�̃J�E���g�A�b�v���s�� -unsigned int inc_pc(); -unsigned int add_pc(unsigned int); -unsigned int set_pc(unsigned int); - -enum RunMode run_proc(enum RunMode mode); - -#endif /* SYS_PROG_H_ */ +/* + * sys_prog.h + * + * Created on: 2016/12/15 + * Author: takayun + */ + +#ifndef SYS_PROG_H_ +#define SYS_PROG_H_ + +/************************************************** + * Defines + **************************************************/ + +// �v���O�������s��� +enum RunMode { RUN_STOP, RUN_INIT, RUN_PROC, RUN_TERM }; + +/************************************************** + * Variables + **************************************************/ + +/************************************************** + * Functions + **************************************************/ + +// ���S��PC�̃J�E���g�A�b�v���s�� +unsigned int inc_pc(); +unsigned int add_pc(unsigned int); +unsigned int set_pc(unsigned int); +unsigned int get_pc(); + +enum RunMode run_proc(enum RunMode mode); + +#endif /* SYS_PROG_H_ */